From a9e97fe66bffad64ec6c21908e38ed4de3d909d8 Mon Sep 17 00:00:00 2001
From: caiussouza <caiuscsouza@gmail.com>
Date: Wed, 1 Mar 2023 22:51:38 -0300
Subject: [PATCH 01/33] creation of file sensor_data_processing

---
 Core/Src/sensors/sensor_data_processing.c | 57 +++++++++++++++++++++++
 1 file changed, 57 insertions(+)
 create mode 100644 Core/Src/sensors/sensor_data_processing.c

diff --git a/Core/Src/sensors/sensor_data_processing.c b/Core/Src/sensors/sensor_data_processing.c
new file mode 100644
index 00000000..125ce9b6
--- /dev/null
+++ b/Core/Src/sensors/sensor_data_processing.c
@@ -0,0 +1,57 @@
+/*
+ * sensor_data_processing.c
+ *
+ *  Created on: 1 de mar de 2023
+ *      Author: caius
+ */
+
+//#include "sensors/sensor_data_processing.h"
+
+// calcular a média móvel e enviá-la para as validações cruzadas
+
+extern uint16_t apps1_value;
+extern uint16_t apps2_value;
+
+void APPS_moving_average() {
+    //tempo pra média: 2s
+}
+
+void PID_init(PID_t* pid, uint8_t reset, double Kp, double Ti, double Td,
+              double max_output, double min_output, double sample_period) {
+    pid->Kp            = Kp;
+    pid->Ti            = Ti;
+    pid->Td            = Td;
+    pid->max_output    = max_output;
+    pid->min_output    = min_output;
+    pid->sample_period = sample_period;
+    PID_recalculate_constants(pid);
+
+    pid->output = 0;
+    /* Verifica se precisa de reset */
+    if (reset) {
+        /* Reseta os estados, sempre de tamanho 2 */
+        memset(pid->error_state, 0, 2U * sizeof(double)); // NOLINT
+        memset(pid->input_state, 0, 2U * sizeof(double)); // NOLINT
+    }
+}
+
+void PID_set_setpoint(PID_t* pid, double Setpoint) {
+    pid->Setpoint = Setpoint;
+}
+
+void PID_set_parameters(PID_t* pid, double Kp, double Ti, double Td) {
+    pid->Kp = Kp;
+    pid->Ti = Ti;
+    pid->Td = Td;
+    PID_recalculate_constants(pid);
+}
+
+void PID_set_limits(PID_t* pid, double max_output, double min_output) {
+    pid->max_output = max_output;
+    pid->min_output = min_output;
+}
+
+void PID_set_sample_period(PID_t* pid, double sample_period) {
+    pid->sample_period = sample_period;
+    PID_recalculate_constants(pid);
+}

From 4fe37f6ee43f3d9a25a3e91ab25eccc18161ab26 Mon Sep 17 00:00:00 2001
From: caiussouza <caiuscsouza@gmail.com>
Date: Thu, 2 Mar 2023 07:05:39 -0300
Subject: [PATCH 02/33] creation of moving average logic

---
 Core/Inc/sensors/sensor_data_processing.h |  13 ++
 Core/Src/sensors/sensor_data_processing.c | 145 ++++++++++++++++------
 2 files changed, 121 insertions(+), 37 deletions(-)
 create mode 100644 Core/Inc/sensors/sensor_data_processing.h

diff --git a/Core/Inc/sensors/sensor_data_processing.h b/Core/Inc/sensors/sensor_data_processing.h
new file mode 100644
index 00000000..92b23433
--- /dev/null
+++ b/Core/Inc/sensors/sensor_data_processing.h
@@ -0,0 +1,13 @@
+/*
+ * sensor_data_processing.h
+ *
+ *  Created on: Mar 2, 2023
+ *      Author: caius
+ */
+
+#ifndef INC_SENSORS_SENSOR_DATA_PROCESSING_H_
+#define INC_SENSORS_SENSOR_DATA_PROCESSING_H_
+
+
+
+#endif /* INC_SENSORS_SENSOR_DATA_PROCESSING_H_ */
diff --git a/Core/Src/sensors/sensor_data_processing.c b/Core/Src/sensors/sensor_data_processing.c
index 125ce9b6..15f5fa6a 100644
--- a/Core/Src/sensors/sensor_data_processing.c
+++ b/Core/Src/sensors/sensor_data_processing.c
@@ -7,51 +7,122 @@
 
 //#include "sensors/sensor_data_processing.h"
 
+#include "util/CMSIS_extra/global_variables_handler.h"
+#include "util/global_variables.h"
+#include "util/global_definitions.h"
+
 // calcular a média móvel e enviá-la para as validações cruzadas
 
-extern uint16_t apps1_value;
-extern uint16_t apps2_value;
+#define APPS_BUFFER_SIZE 100
+#define STEERING_WHEEL_BUFFER_SIZE 100
+#define SPEED_BUFFER_SIZE 100
 
-void APPS_moving_average() {
-    //tempo pra média: 2s
-}
+static uint16_t apps1 = ADC_DMA_buffer[APPS1_E];
+static uint16_t apps2 = ADC_DMA_buffer[APPS2_E];
+static STEERING_WHEEL_t steering_wheel = get_global_var_value(STEERING_WHEEL);
+static uint16_t speed = (get_global_var_value(REAR_AVG_SPEED)) / (10 * 3.6);
 
-void PID_init(PID_t* pid, uint8_t reset, double Kp, double Ti, double Td,
-              double max_output, double min_output, double sample_period) {
-    pid->Kp            = Kp;
-    pid->Ti            = Ti;
-    pid->Td            = Td;
-    pid->max_output    = max_output;
-    pid->min_output    = min_output;
-    pid->sample_period = sample_period;
-    PID_recalculate_constants(pid);
-
-    pid->output = 0;
-    /* Verifica se precisa de reset */
-    if (reset) {
-        /* Reseta os estados, sempre de tamanho 2 */
-        memset(pid->error_state, 0, 2U * sizeof(double)); // NOLINT
-        memset(pid->input_state, 0, 2U * sizeof(double)); // NOLINT
-    }
-}
 
-void PID_set_setpoint(PID_t* pid, double Setpoint) {
-    pid->Setpoint = Setpoint;
-}
 
-void PID_set_parameters(PID_t* pid, double Kp, double Ti, double Td) {
-    pid->Kp = Kp;
-    pid->Ti = Ti;
-    pid->Td = Td;
-    PID_recalculate_constants(pid);
+void APPS_mov_average(uint16_t* apps1_movave, uint16_t* apps2_movave) {
+//  fazer um vetor e calcular media movel
+//	a partir dele. comece colocando um valor de
+//	[800] e testa empiricamente. teste visualizar a curva
+//	comparando os dados crus e a média móvel
+
+	uint16_t apps1_buffer[APPS_BUFFER_SIZE];
+	uint16_t apps2_buffer[APPS_BUFFER_SIZE];
+	uint8_t buffer_index = 0;
+	uint32_t apps1_buffer_sum = 0;
+	uint32_t apps2_buffer_sum = 0;
+
+	apps1_movave = 0;
+	apps2_movave = 0;
+
+	// circular buffer for calculating the moving average of APPS signals
+
+	for(;;){
+		// Put the APPS value read by ADC into each buffer position
+		apps1_buffer[buffer_index] = apps1;
+		apps2_buffer[buffer_index] = apps2;
+
+		// circular buffer logic
+		buffer_index = (buffer_index + 1) % APPS_BUFFER_SIZE;
+
+		// Calculates the moving average based on a mutable value
+		// It requires empirical tests for choosing that value
+		for(uint8_t i = 0; i < APPS_BUFFER_SIZE; i++){
+			apps1_buffer_sum += apps1_buffer[i];
+			apps2_buffer_sum += apps2_buffer[i];
+		}
+		apps1_movave = apps1_buffer_sum / APPS_BUFFER_SIZE;
+		apps2_movave = apps2_buffer_sum / APPS_BUFFER_SIZE;
+	}
+
 }
 
-void PID_set_limits(PID_t* pid, double max_output, double min_output) {
-    pid->max_output = max_output;
-    pid->min_output = min_output;
+void steering_wheel_mov_average(uint16_t* steering_wheel_movave) {
+//  fazer um vetor e calcular media movel
+//	a partir dele. comece colocando um valor de
+//	[800] e testa empiricamente. teste visualizar a curva
+//	comparando os dados crus e a média móvel
+
+	uint16_t steering_wheel_buffer[STEERING_WHEEL_BUFFER_SIZE];
+	uint8_t buffer_index = 0;
+	uint32_t steering_wheel_buffer_sum = 0;
+
+	steering_wheel_movave = 0;
+
+	// circular buffer for calculating the moving average of APPS signals
+
+	for(;;){
+		// Put the steering wheel value read by ADC into each buffer position
+		steering_wheel_buffer[buffer_index] = steering_wheel;
+
+		// circular buffer logic
+		buffer_index = (buffer_index + 1) % STEERING_WHEEL_BUFFER_SIZE;
+
+		// Calculates the moving average based on a mutable value
+		// It requires empirical tests for choosing that value
+		for(uint8_t i = 0; i < STEERING_WHEEL_BUFFER_SIZE; i++){
+			steering_wheel_buffer_sum += steering_wheel_buffer[i];
+		}
+		steering_wheel_movave = steering_wheel_buffer_sum / STEERING_WHEEL_BUFFER_SIZE;
+	}
+
 }
 
-void PID_set_sample_period(PID_t* pid, double sample_period) {
-    pid->sample_period = sample_period;
-    PID_recalculate_constants(pid);
+void speed_mov_average(uint16_t* speed_movave) {
+//  fazer um vetor e calcular media movel
+//	a partir dele. comece colocando um valor de
+//	[800] e testa empiricamente. teste visualizar a curva
+//	comparando os dados crus e a média móvel
+
+	uint16_t speed_buffer[SPEED_BUFFER_SIZE];
+	uint8_t buffer_index = 0;
+	uint32_t speed_buffer_sum = 0;
+
+	speed_movave = 0;
+
+	// circular buffer for calculating the moving average of APPS signals
+
+	for(;;){
+		// Put the steering wheel value read by ADC into each buffer position
+		speed_buffer[buffer_index] = speed;
+
+		// circular buffer logic
+		buffer_index = (buffer_index + 1) % SPEED_BUFFER_SIZE;
+
+		// Calculates the moving average based on a mutable value
+		// It requires empirical tests for choosing that value
+		for(uint8_t i = 0; i < SPEED_BUFFER_SIZE; i++){
+			speed_buffer_sum += speed_buffer[i];
+		}
+		speed_movave = speed_buffer_sum / SPEED_BUFFER_SIZE;
+	}
+
 }
+
+
+
+

From b77eab70d4e2ee6e4e4223b7370f499c4013cbf1 Mon Sep 17 00:00:00 2001
From: caiussouza <caiuscsouza@gmail.com>
Date: Thu, 2 Mar 2023 07:13:01 -0300
Subject: [PATCH 03/33] completing the moving average

---
 Core/Inc/sensors/sensor_data_processing.h |  4 +++-
 Core/Src/sensors/sensor_data_processing.c | 29 ++++-------------------
 2 files changed, 7 insertions(+), 26 deletions(-)

diff --git a/Core/Inc/sensors/sensor_data_processing.h b/Core/Inc/sensors/sensor_data_processing.h
index 92b23433..43fd8a6e 100644
--- a/Core/Inc/sensors/sensor_data_processing.h
+++ b/Core/Inc/sensors/sensor_data_processing.h
@@ -8,6 +8,8 @@
 #ifndef INC_SENSORS_SENSOR_DATA_PROCESSING_H_
 #define INC_SENSORS_SENSOR_DATA_PROCESSING_H_
 
-
+#define APPS_BUFFER_SIZE 100
+#define STEERING_WHEEL_BUFFER_SIZE 100
+#define SPEED_BUFFER_SIZE 100
 
 #endif /* INC_SENSORS_SENSOR_DATA_PROCESSING_H_ */
diff --git a/Core/Src/sensors/sensor_data_processing.c b/Core/Src/sensors/sensor_data_processing.c
index 15f5fa6a..6345fb22 100644
--- a/Core/Src/sensors/sensor_data_processing.c
+++ b/Core/Src/sensors/sensor_data_processing.c
@@ -5,17 +5,12 @@
  *      Author: caius
  */
 
-//#include "sensors/sensor_data_processing.h"
+#include "sensors/sensor_data_processing.h"
 
 #include "util/CMSIS_extra/global_variables_handler.h"
 #include "util/global_variables.h"
 #include "util/global_definitions.h"
 
-// calcular a média móvel e enviá-la para as validações cruzadas
-
-#define APPS_BUFFER_SIZE 100
-#define STEERING_WHEEL_BUFFER_SIZE 100
-#define SPEED_BUFFER_SIZE 100
 
 static uint16_t apps1 = ADC_DMA_buffer[APPS1_E];
 static uint16_t apps2 = ADC_DMA_buffer[APPS2_E];
@@ -62,10 +57,6 @@ void APPS_mov_average(uint16_t* apps1_movave, uint16_t* apps2_movave) {
 }
 
 void steering_wheel_mov_average(uint16_t* steering_wheel_movave) {
-//  fazer um vetor e calcular media movel
-//	a partir dele. comece colocando um valor de
-//	[800] e testa empiricamente. teste visualizar a curva
-//	comparando os dados crus e a média móvel
 
 	uint16_t steering_wheel_buffer[STEERING_WHEEL_BUFFER_SIZE];
 	uint8_t buffer_index = 0;
@@ -73,30 +64,23 @@ void steering_wheel_mov_average(uint16_t* steering_wheel_movave) {
 
 	steering_wheel_movave = 0;
 
-	// circular buffer for calculating the moving average of APPS signals
 
 	for(;;){
-		// Put the steering wheel value read by ADC into each buffer position
+
 		steering_wheel_buffer[buffer_index] = steering_wheel;
 
-		// circular buffer logic
 		buffer_index = (buffer_index + 1) % STEERING_WHEEL_BUFFER_SIZE;
 
-		// Calculates the moving average based on a mutable value
-		// It requires empirical tests for choosing that value
 		for(uint8_t i = 0; i < STEERING_WHEEL_BUFFER_SIZE; i++){
 			steering_wheel_buffer_sum += steering_wheel_buffer[i];
 		}
+
 		steering_wheel_movave = steering_wheel_buffer_sum / STEERING_WHEEL_BUFFER_SIZE;
 	}
 
 }
 
 void speed_mov_average(uint16_t* speed_movave) {
-//  fazer um vetor e calcular media movel
-//	a partir dele. comece colocando um valor de
-//	[800] e testa empiricamente. teste visualizar a curva
-//	comparando os dados crus e a média móvel
 
 	uint16_t speed_buffer[SPEED_BUFFER_SIZE];
 	uint8_t buffer_index = 0;
@@ -104,17 +88,12 @@ void speed_mov_average(uint16_t* speed_movave) {
 
 	speed_movave = 0;
 
-	// circular buffer for calculating the moving average of APPS signals
-
 	for(;;){
-		// Put the steering wheel value read by ADC into each buffer position
+
 		speed_buffer[buffer_index] = speed;
 
-		// circular buffer logic
 		buffer_index = (buffer_index + 1) % SPEED_BUFFER_SIZE;
 
-		// Calculates the moving average based on a mutable value
-		// It requires empirical tests for choosing that value
 		for(uint8_t i = 0; i < SPEED_BUFFER_SIZE; i++){
 			speed_buffer_sum += speed_buffer[i];
 		}

From b148b005722d1c284bebbfcfc225f617aa9442c8 Mon Sep 17 00:00:00 2001
From: caiussouza <caiuscsouza@gmail.com>
Date: Thu, 2 Mar 2023 16:18:13 -0300
Subject: [PATCH 04/33] cross validation sketch

---
 Core/Inc/sensors/sensor_data_processing.h     |  3 +-
 .../dynamic_controls/security_architecture.c  | 41 ++++++++
 Core/Src/sensors/sensor_data_processing.c     | 93 +++++++++++++------
 3 files changed, 110 insertions(+), 27 deletions(-)
 create mode 100644 Core/Src/dynamic_controls/security_architecture.c

diff --git a/Core/Inc/sensors/sensor_data_processing.h b/Core/Inc/sensors/sensor_data_processing.h
index 43fd8a6e..8508a4d0 100644
--- a/Core/Inc/sensors/sensor_data_processing.h
+++ b/Core/Inc/sensors/sensor_data_processing.h
@@ -9,7 +9,8 @@
 #define INC_SENSORS_SENSOR_DATA_PROCESSING_H_
 
 #define APPS_BUFFER_SIZE 100
-#define STEERING_WHEEL_BUFFER_SIZE 100
+//#define STEERING_WHEEL_BUFFER_SIZE 100
 #define SPEED_BUFFER_SIZE 100
+#define IMU_BUFFER_SIZE 100
 
 #endif /* INC_SENSORS_SENSOR_DATA_PROCESSING_H_ */
diff --git a/Core/Src/dynamic_controls/security_architecture.c b/Core/Src/dynamic_controls/security_architecture.c
new file mode 100644
index 00000000..9b71eb0a
--- /dev/null
+++ b/Core/Src/dynamic_controls/security_architecture.c
@@ -0,0 +1,41 @@
+/*
+ * cross_validations.c
+ *
+ *  Created on: 2 de mar de 2023
+ *      Author: caius
+ */
+
+//steps : cross validation functions with boolean return
+//monitoring task
+
+
+
+static uint16_t apps1_filtered;
+static uint16_t apps2_filtered;
+//extern STEERING_WHEEL_t steering_wheel;
+static uint16_t speed_filtered;
+//extern int16_t IMU_yaw;
+static int16_t IMU_accel_filtered;
+
+void init_moving_average(){ //colocar essa e a init_cross_val dentro da initializer_controls.c
+	APPS_mov_average(&apps1_filtered, &apps2_filtered);
+	IMU_accel_mov_average(&IMU_accel_filtered);
+	speed_mov_average(&speed_filtered);
+}
+
+uint8_t imu_apps_cross_val(){
+	uint16_t apps_mean = (apps1_filtered + apps2_filtered) / 2;
+//	if((apps_mean > APPS_MAX_THRESHOLD) && (IMU_accel_filtered > IMU_ACCEL_MAX_THRESHOLD))...
+//		return 0;
+//	return 1;
+}
+uint8_t imu_bse(){
+//	if(bse active && imu_accel > threshold)
+//		return 0;
+//	return 1;
+}
+uint8_t imu_speed(){
+//	if(speed < threshold (parado) && imu > accel (detectando acel))
+//		return 0;
+//	return 1;
+}
diff --git a/Core/Src/sensors/sensor_data_processing.c b/Core/Src/sensors/sensor_data_processing.c
index 6345fb22..821be419 100644
--- a/Core/Src/sensors/sensor_data_processing.c
+++ b/Core/Src/sensors/sensor_data_processing.c
@@ -14,10 +14,10 @@
 
 static uint16_t apps1 = ADC_DMA_buffer[APPS1_E];
 static uint16_t apps2 = ADC_DMA_buffer[APPS2_E];
-static STEERING_WHEEL_t steering_wheel = get_global_var_value(STEERING_WHEEL);
+//static STEERING_WHEEL_t steering_wheel = get_global_var_value(STEERING_WHEEL);
 static uint16_t speed = (get_global_var_value(REAR_AVG_SPEED)) / (10 * 3.6);
-
-
+//static int16_t IMU_yaw = (int16_t)general_get_value(gyroscope_y);
+static int16_t IMU_accel = (int16_t)general_get_value(accelerometer_z);
 
 void APPS_mov_average(uint16_t* apps1_movave, uint16_t* apps2_movave) {
 //  fazer um vetor e calcular media movel
@@ -56,29 +56,29 @@ void APPS_mov_average(uint16_t* apps1_movave, uint16_t* apps2_movave) {
 
 }
 
-void steering_wheel_mov_average(uint16_t* steering_wheel_movave) {
-
-	uint16_t steering_wheel_buffer[STEERING_WHEEL_BUFFER_SIZE];
-	uint8_t buffer_index = 0;
-	uint32_t steering_wheel_buffer_sum = 0;
-
-	steering_wheel_movave = 0;
-
-
-	for(;;){
-
-		steering_wheel_buffer[buffer_index] = steering_wheel;
-
-		buffer_index = (buffer_index + 1) % STEERING_WHEEL_BUFFER_SIZE;
-
-		for(uint8_t i = 0; i < STEERING_WHEEL_BUFFER_SIZE; i++){
-			steering_wheel_buffer_sum += steering_wheel_buffer[i];
-		}
-
-		steering_wheel_movave = steering_wheel_buffer_sum / STEERING_WHEEL_BUFFER_SIZE;
-	}
-
-}
+//void steering_wheel_mov_average(uint16_t* steering_wheel_movave) {
+//
+//	uint16_t steering_wheel_buffer[STEERING_WHEEL_BUFFER_SIZE];
+//	uint8_t buffer_index = 0;
+//	uint32_t steering_wheel_buffer_sum = 0;
+//
+//	steering_wheel_movave = 0;
+//
+//
+//	for(;;){
+//
+//		steering_wheel_buffer[buffer_index] = steering_wheel;
+//
+//		buffer_index = (buffer_index + 1) % STEERING_WHEEL_BUFFER_SIZE;
+//
+//		for(uint8_t i = 0; i < STEERING_WHEEL_BUFFER_SIZE; i++){
+//			steering_wheel_buffer_sum += steering_wheel_buffer[i];
+//		}
+//
+//		steering_wheel_movave = steering_wheel_buffer_sum / STEERING_WHEEL_BUFFER_SIZE;
+//	}
+//
+//}
 
 void speed_mov_average(uint16_t* speed_movave) {
 
@@ -102,6 +102,47 @@ void speed_mov_average(uint16_t* speed_movave) {
 
 }
 
+//void IMU_yaw_mov_average(uint16_t* imu_yaw_movave) {
+//
+//	uint16_t imu_yaw_buffer[IMU_BUFFER_SIZE];
+//	uint8_t buffer_index = 0;
+//	uint32_t imu_yaw_buffer_sum = 0;
+//
+//	imu_yaw_movave = 0;
+//
+//	for(;;){
+//
+//		imu_yaw_buffer[buffer_index] = IMU_yaw;
+//
+//		buffer_index = (buffer_index + 1) % IMU_BUFFER_SIZE;
+//
+//		for(uint8_t i = 0; i < IMU_BUFFER_SIZE; i++){
+//			imu_yaw_buffer_sum += imu_yaw_buffer[i];
+//		}
+//		imu_yaw_movave = imu_yaw_buffer_sum / IMU_BUFFER_SIZE;
+//	}
+//
+//}
+
+void IMU_accel_mov_average(uint16_t* imu_accel_movave) {
+
+	uint16_t imu_accel_buffer[IMU_BUFFER_SIZE];
+	uint8_t buffer_index = 0;
+	uint32_t imu_accel_buffer_sum = 0;
+
+	imu_accel_movave = 0;
+
+	for(;;){
+
+		imu_accel_buffer[buffer_index] = IMU_accel;
+
+		buffer_index = (buffer_index + 1) % IMU_BUFFER_SIZE;
 
+		for(uint8_t i = 0; i < IMU_BUFFER_SIZE; i++){
+			imu_accel_buffer_sum += imu_accel_buffer[i];
+		}
+		imu_accel_movave = imu_accel_buffer_sum / IMU_BUFFER_SIZE;
+	}
 
+}
 

From ea57e3cb20af4d5be51497475402f2f96354ede2 Mon Sep 17 00:00:00 2001
From: caiussouza <caiuscsouza@gmail.com>
Date: Sun, 5 Mar 2023 16:07:09 -0300
Subject: [PATCH 05/33] cross validation logic implemented

---
 .../dynamic_controls/security_architecture.h  |  20 +++
 Core/Inc/sensors/sensor_data_processing.h     |   7 +-
 .../dynamic_controls/initializer_controls.c   |   3 +
 .../dynamic_controls/security_architecture.c  |  51 ++++---
 Core/Src/sensors/sensor_data_processing.c     | 132 ++----------------
 5 files changed, 69 insertions(+), 144 deletions(-)
 create mode 100644 Core/Inc/dynamic_controls/security_architecture.h

diff --git a/Core/Inc/dynamic_controls/security_architecture.h b/Core/Inc/dynamic_controls/security_architecture.h
new file mode 100644
index 00000000..a4935962
--- /dev/null
+++ b/Core/Inc/dynamic_controls/security_architecture.h
@@ -0,0 +1,20 @@
+/*
+ * security_architecture.h
+ *
+ *  Created on: 5 de mar de 2023
+ *      Author: caius
+ */
+
+#ifndef INC_DYNAMIC_CONTROLS_SECURITY_ARCHITECTURE_H_
+#define INC_DYNAMIC_CONTROLS_SECURITY_ARCHITECTURE_H_
+
+// TODO(caius): add the threshold values
+#define IMU_LONG_ACCEL_THRESHOLD 1
+#define SPEED_MIN_THRESHOLD 1
+#define IMU_MAX_LONG_ACCEL_THRESHOLD 1
+
+void init_moving_average();
+uint8_t is_imu_bse_ok();
+uint8_t is_imu_speed_ok();
+
+#endif /* INC_DYNAMIC_CONTROLS_SECURITY_ARCHITECTURE_H_ */
diff --git a/Core/Inc/sensors/sensor_data_processing.h b/Core/Inc/sensors/sensor_data_processing.h
index 8508a4d0..593f6cfa 100644
--- a/Core/Inc/sensors/sensor_data_processing.h
+++ b/Core/Inc/sensors/sensor_data_processing.h
@@ -8,9 +8,8 @@
 #ifndef INC_SENSORS_SENSOR_DATA_PROCESSING_H_
 #define INC_SENSORS_SENSOR_DATA_PROCESSING_H_
 
-#define APPS_BUFFER_SIZE 100
-//#define STEERING_WHEEL_BUFFER_SIZE 100
-#define SPEED_BUFFER_SIZE 100
-#define IMU_BUFFER_SIZE 100
+#define BUFFER_SIZE 100
+
+void moving_average(uint16_t* movave, uint16_t data);
 
 #endif /* INC_SENSORS_SENSOR_DATA_PROCESSING_H_ */
diff --git a/Core/Src/dynamic_controls/initializer_controls.c b/Core/Src/dynamic_controls/initializer_controls.c
index 0550159c..04dad96d 100644
--- a/Core/Src/dynamic_controls/initializer_controls.c
+++ b/Core/Src/dynamic_controls/initializer_controls.c
@@ -11,6 +11,7 @@
 #include "dynamic_controls/lateral_control.h"
 #include "dynamic_controls/longitudinal_control.h"
 #include "util/global_definitions.h"
+#include "security_architecture.h"
 
 void init_controls() {
 
@@ -18,4 +19,6 @@ void init_controls() {
     init_lateral_control();
     // Longitudinal Control
     init_longitudinal_control();
+    // Moving average
+    init_moving_average();
 }
diff --git a/Core/Src/dynamic_controls/security_architecture.c b/Core/Src/dynamic_controls/security_architecture.c
index 9b71eb0a..40792264 100644
--- a/Core/Src/dynamic_controls/security_architecture.c
+++ b/Core/Src/dynamic_controls/security_architecture.c
@@ -1,5 +1,5 @@
 /*
- * cross_validations.c
+ * security_architecture.c
  *
  *  Created on: 2 de mar de 2023
  *      Author: caius
@@ -7,35 +7,40 @@
 
 //steps : cross validation functions with boolean return
 //monitoring task
+#include "security_architecture.h"
 
+#include "global_variables_handler.h"
+#include "sensor_data_processing.h"
+#include "util/CMSIS_extra/global_variables_handler.h"
+#include "util/global_variables.h"
+#include "util/global_definitions.h"
 
 
-static uint16_t apps1_filtered;
-static uint16_t apps2_filtered;
-//extern STEERING_WHEEL_t steering_wheel;
 static uint16_t speed_filtered;
-//extern int16_t IMU_yaw;
-static int16_t IMU_accel_filtered;
+static int16_t IMU_long_accel_filtered;
+static bool bse_active = get_global_var_value(BRAKE_STATUS);
+
+static uint16_t raw_speed_data = (uint16_t)get_global_var_value(REAR_AVG_SPEED);
+static uint16_t raw_IMU_long_accel_data = (int16_t)general_get_value(accelerometer_y);
+
 
 void init_moving_average(){ //colocar essa e a init_cross_val dentro da initializer_controls.c
-	APPS_mov_average(&apps1_filtered, &apps2_filtered);
-	IMU_accel_mov_average(&IMU_accel_filtered);
-	speed_mov_average(&speed_filtered);
+//	moving_average(&apps1_filtered /*, apps1 nao filtrado*/);
+//	moving_average(&apps2_filtered /*, apps2 nao filtrado*/);
+	moving_average(&IMU_long_accel_filtered, raw_IMU_long_accel_data);
+	moving_average(&speed_filtered, raw_speed_data);
 }
 
-uint8_t imu_apps_cross_val(){
-	uint16_t apps_mean = (apps1_filtered + apps2_filtered) / 2;
-//	if((apps_mean > APPS_MAX_THRESHOLD) && (IMU_accel_filtered > IMU_ACCEL_MAX_THRESHOLD))...
-//		return 0;
-//	return 1;
-}
-uint8_t imu_bse(){
-//	if(bse active && imu_accel > threshold)
-//		return 0;
-//	return 1;
+uint8_t is_imu_bse_ok(){
+	if(bse_active && (IMU_long_accel_filtered > IMU_MAX_LONG_ACCEL_THRESHOLD))
+		return 0;
+	return 1;
 }
-uint8_t imu_speed(){
-//	if(speed < threshold (parado) && imu > accel (detectando acel))
-//		return 0;
-//	return 1;
+
+uint8_t is_imu_speed_ok(){
+	if((speed < SPEED_MIN_THRESHOLD) && (IMU_long_accel_filtered > IMU_MAX_LONG_ACCEL_THRESHOLD))
+		return 0;
+	return 1;
 }
+
+
diff --git a/Core/Src/sensors/sensor_data_processing.c b/Core/Src/sensors/sensor_data_processing.c
index 821be419..56d09b2e 100644
--- a/Core/Src/sensors/sensor_data_processing.c
+++ b/Core/Src/sensors/sensor_data_processing.c
@@ -7,141 +7,39 @@
 
 #include "sensors/sensor_data_processing.h"
 
-#include "util/CMSIS_extra/global_variables_handler.h"
-#include "util/global_variables.h"
-#include "util/global_definitions.h"
 
 
-static uint16_t apps1 = ADC_DMA_buffer[APPS1_E];
-static uint16_t apps2 = ADC_DMA_buffer[APPS2_E];
-//static STEERING_WHEEL_t steering_wheel = get_global_var_value(STEERING_WHEEL);
-static uint16_t speed = (get_global_var_value(REAR_AVG_SPEED)) / (10 * 3.6);
-//static int16_t IMU_yaw = (int16_t)general_get_value(gyroscope_y);
-static int16_t IMU_accel = (int16_t)general_get_value(accelerometer_z);
+// moving average genérico
 
-void APPS_mov_average(uint16_t* apps1_movave, uint16_t* apps2_movave) {
-//  fazer um vetor e calcular media movel
-//	a partir dele. comece colocando um valor de
-//	[800] e testa empiricamente. teste visualizar a curva
-//	comparando os dados crus e a média móvel
+void moving_average(uint16_t* movave, uint16_t data) {
 
-	uint16_t apps1_buffer[APPS_BUFFER_SIZE];
-	uint16_t apps2_buffer[APPS_BUFFER_SIZE];
 	uint8_t buffer_index = 0;
-	uint32_t apps1_buffer_sum = 0;
-	uint32_t apps2_buffer_sum = 0;
+	uint16_t movave_buffer[BUFFER_SIZE];
+	uint32_t buffer_sum = 0;
 
-	apps1_movave = 0;
-	apps2_movave = 0;
+	movave = 0;
 
 	// circular buffer for calculating the moving average of APPS signals
 
 	for(;;){
 		// Put the APPS value read by ADC into each buffer position
-		apps1_buffer[buffer_index] = apps1;
-		apps2_buffer[buffer_index] = apps2;
+		movave_buffer[buffer_index] = data;
 
 		// circular buffer logic
-		buffer_index = (buffer_index + 1) % APPS_BUFFER_SIZE;
+		if(buffer_index == 256)
+			buffer_index = 0;
+		buffer_index = (buffer_index + 1) % BUFFER_SIZE;
+
 
 		// Calculates the moving average based on a mutable value
 		// It requires empirical tests for choosing that value
-		for(uint8_t i = 0; i < APPS_BUFFER_SIZE; i++){
-			apps1_buffer_sum += apps1_buffer[i];
-			apps2_buffer_sum += apps2_buffer[i];
-		}
-		apps1_movave = apps1_buffer_sum / APPS_BUFFER_SIZE;
-		apps2_movave = apps2_buffer_sum / APPS_BUFFER_SIZE;
-	}
-
-}
-
-//void steering_wheel_mov_average(uint16_t* steering_wheel_movave) {
-//
-//	uint16_t steering_wheel_buffer[STEERING_WHEEL_BUFFER_SIZE];
-//	uint8_t buffer_index = 0;
-//	uint32_t steering_wheel_buffer_sum = 0;
-//
-//	steering_wheel_movave = 0;
-//
-//
-//	for(;;){
-//
-//		steering_wheel_buffer[buffer_index] = steering_wheel;
-//
-//		buffer_index = (buffer_index + 1) % STEERING_WHEEL_BUFFER_SIZE;
-//
-//		for(uint8_t i = 0; i < STEERING_WHEEL_BUFFER_SIZE; i++){
-//			steering_wheel_buffer_sum += steering_wheel_buffer[i];
-//		}
-//
-//		steering_wheel_movave = steering_wheel_buffer_sum / STEERING_WHEEL_BUFFER_SIZE;
-//	}
-//
-//}
-
-void speed_mov_average(uint16_t* speed_movave) {
-
-	uint16_t speed_buffer[SPEED_BUFFER_SIZE];
-	uint8_t buffer_index = 0;
-	uint32_t speed_buffer_sum = 0;
-
-	speed_movave = 0;
-
-	for(;;){
-
-		speed_buffer[buffer_index] = speed;
-
-		buffer_index = (buffer_index + 1) % SPEED_BUFFER_SIZE;
-
-		for(uint8_t i = 0; i < SPEED_BUFFER_SIZE; i++){
-			speed_buffer_sum += speed_buffer[i];
+		for(uint8_t i = 0; i < BUFFER_SIZE; i++){
+			buffer_sum += movave_buffer[i];
 		}
-		speed_movave = speed_buffer_sum / SPEED_BUFFER_SIZE;
-	}
-
-}
-
-//void IMU_yaw_mov_average(uint16_t* imu_yaw_movave) {
-//
-//	uint16_t imu_yaw_buffer[IMU_BUFFER_SIZE];
-//	uint8_t buffer_index = 0;
-//	uint32_t imu_yaw_buffer_sum = 0;
-//
-//	imu_yaw_movave = 0;
-//
-//	for(;;){
-//
-//		imu_yaw_buffer[buffer_index] = IMU_yaw;
-//
-//		buffer_index = (buffer_index + 1) % IMU_BUFFER_SIZE;
-//
-//		for(uint8_t i = 0; i < IMU_BUFFER_SIZE; i++){
-//			imu_yaw_buffer_sum += imu_yaw_buffer[i];
-//		}
-//		imu_yaw_movave = imu_yaw_buffer_sum / IMU_BUFFER_SIZE;
-//	}
-//
-//}
-
-void IMU_accel_mov_average(uint16_t* imu_accel_movave) {
-
-	uint16_t imu_accel_buffer[IMU_BUFFER_SIZE];
-	uint8_t buffer_index = 0;
-	uint32_t imu_accel_buffer_sum = 0;
-
-	imu_accel_movave = 0;
-
-	for(;;){
+		movave = buffer_sum / BUFFER_SIZE;
 
-		imu_accel_buffer[buffer_index] = IMU_accel;
-
-		buffer_index = (buffer_index + 1) % IMU_BUFFER_SIZE;
-
-		for(uint8_t i = 0; i < IMU_BUFFER_SIZE; i++){
-			imu_accel_buffer_sum += imu_accel_buffer[i];
-		}
-		imu_accel_movave = imu_accel_buffer_sum / IMU_BUFFER_SIZE;
+		// avoiding variable type overflow
+		buffer_sum = 0;
 	}
 
 }

From c45a78fbb33b2e9eb9f78dd09f98611f37ef74da Mon Sep 17 00:00:00 2001
From: caiussouza <caiuscsouza@gmail.com>
Date: Sun, 5 Mar 2023 17:01:48 -0300
Subject: [PATCH 06/33] security architecture sketch

---
 Core/Inc/sensors/sensor_data_processing.h     |  2 +-
 .../dynamic_controls/security_architecture.c  | 31 ++++++++++++++-----
 Core/Src/sensors/sensor_data_processing.c     | 20 ++++++------
 3 files changed, 35 insertions(+), 18 deletions(-)

diff --git a/Core/Inc/sensors/sensor_data_processing.h b/Core/Inc/sensors/sensor_data_processing.h
index 593f6cfa..25a4ef3e 100644
--- a/Core/Inc/sensors/sensor_data_processing.h
+++ b/Core/Inc/sensors/sensor_data_processing.h
@@ -10,6 +10,6 @@
 
 #define BUFFER_SIZE 100
 
-void moving_average(uint16_t* movave, uint16_t data);
+void moving_average(uint16_t* mov_ave, uint16_t data);
 
 #endif /* INC_SENSORS_SENSOR_DATA_PROCESSING_H_ */
diff --git a/Core/Src/dynamic_controls/security_architecture.c b/Core/Src/dynamic_controls/security_architecture.c
index 40792264..ae280cde 100644
--- a/Core/Src/dynamic_controls/security_architecture.c
+++ b/Core/Src/dynamic_controls/security_architecture.c
@@ -5,8 +5,7 @@
  *      Author: caius
  */
 
-//steps : cross validation functions with boolean return
-//monitoring task
+
 #include "security_architecture.h"
 
 #include "global_variables_handler.h"
@@ -15,18 +14,36 @@
 #include "util/global_variables.h"
 #include "util/global_definitions.h"
 
+// Center of gravity speed used in dynamic controls functions
+static uint16_t raw_speed_data = (uint16_t)get_global_var_value(REAR_AVG_SPEED);
+
+static uint16_t raw_IMU_long_accel_data = (int16_t)general_get_value(accelerometer_y);
 
 static uint16_t speed_filtered;
 static int16_t IMU_long_accel_filtered;
 static bool bse_active = get_global_var_value(BRAKE_STATUS);
 
-static uint16_t raw_speed_data = (uint16_t)get_global_var_value(REAR_AVG_SPEED);
-static uint16_t raw_IMU_long_accel_data = (int16_t)general_get_value(accelerometer_y);
+void cross_validation(void* argument) {
+    UNUSED(argument);
+
+    for (;;) {
+        ECU_ENABLE_BREAKPOINT_DEBUG();
+
+        is_imu_bse_ok();
+        is_imu_speed_ok();
+        if(is_imu_bse_ok && is_imu_speed_ok){
+//        	enable torque vectoring if disabled
+        }
+        else{
+//        	prevent enabling torque vectoring if disabled
+//			disable torque vectoring if enabled
+        }
+
+    }
+}
 
 
-void init_moving_average(){ //colocar essa e a init_cross_val dentro da initializer_controls.c
-//	moving_average(&apps1_filtered /*, apps1 nao filtrado*/);
-//	moving_average(&apps2_filtered /*, apps2 nao filtrado*/);
+void init_moving_average(){
 	moving_average(&IMU_long_accel_filtered, raw_IMU_long_accel_data);
 	moving_average(&speed_filtered, raw_speed_data);
 }
diff --git a/Core/Src/sensors/sensor_data_processing.c b/Core/Src/sensors/sensor_data_processing.c
index 56d09b2e..39cf0253 100644
--- a/Core/Src/sensors/sensor_data_processing.c
+++ b/Core/Src/sensors/sensor_data_processing.c
@@ -9,37 +9,37 @@
 
 
 
-// moving average genérico
+// Calculate moving average for data logged from any sensor
 
-void moving_average(uint16_t* movave, uint16_t data) {
+void moving_average(uint16_t* mov_ave, uint16_t data) {
 
 	uint8_t buffer_index = 0;
 	uint16_t movave_buffer[BUFFER_SIZE];
 	uint32_t buffer_sum = 0;
 
-	movave = 0;
+	mov_ave = 0;
 
-	// circular buffer for calculating the moving average of APPS signals
+	// Circular buffer for calculating the moving average of a signal
 
 	for(;;){
-		// Put the APPS value read by ADC into each buffer position
+		// Put the signal value read by sensor into each buffer position
 		movave_buffer[buffer_index] = data;
 
 		// circular buffer logic
-		if(buffer_index == 256)
-			buffer_index = 0;
 		buffer_index = (buffer_index + 1) % BUFFER_SIZE;
 
 
-		// Calculates the moving average based on a mutable value
+		// Calculate the moving average based on a mutable value
 		// It requires empirical tests for choosing that value
 		for(uint8_t i = 0; i < BUFFER_SIZE; i++){
 			buffer_sum += movave_buffer[i];
 		}
-		movave = buffer_sum / BUFFER_SIZE;
+		mov_ave = buffer_sum / BUFFER_SIZE;
 
-		// avoiding variable type overflow
+		// Avoid variable type overflow
 		buffer_sum = 0;
+		if(buffer_index == 256)
+			buffer_index = 0;
 	}
 
 }

From fd5d772c6555d12b705f058cd70c2d1fbced1258 Mon Sep 17 00:00:00 2001
From: caiussouza <caiuscsouza@gmail.com>
Date: Mon, 6 Mar 2023 16:30:24 -0300
Subject: [PATCH 07/33] cross validation task development

---
 .../dynamic_controls/security_architecture.h  |     1 -
 Core/Inc/util/global_definitions.h            |     1 +
 .../dynamic_controls/initializer_controls.c   |     3 -
 .../dynamic_controls/security_architecture.c  |    21 +-
 Core/Src/main.c                               |  2525 +--
 Core/Src/sensors/sensor_data_processing.c     |    48 +-
 Core/Src/stm32h7xx_hal_msp.c                  |  1380 +-
 Core/Src/torque_command/torque_manager.c      |     8 +-
 Drivers/CMSIS/Device/ST/STM32H7xx/LICENSE.txt |    12 +-
 Drivers/CMSIS/LICENSE.txt                     |   402 +-
 .../Inc/stm32h7xx_ll_bus.h                    | 13664 ++++++++--------
 .../Inc/stm32h7xx_ll_cortex.h                 |  1334 +-
 .../Inc/stm32h7xx_ll_crs.h                    |  1560 +-
 .../Inc/stm32h7xx_ll_dma.h                    |  6564 ++++----
 .../Inc/stm32h7xx_ll_dmamux.h                 |  4872 +++---
 .../Inc/stm32h7xx_ll_exti.h                   |  6570 ++++----
 .../Inc/stm32h7xx_ll_gpio.h                   |  1968 +--
 .../Inc/stm32h7xx_ll_hsem.h                   |  1804 +-
 .../Inc/stm32h7xx_ll_i2c.h                    |  4544 ++---
 .../Inc/stm32h7xx_ll_lpuart.h                 |  5300 +++---
 .../Inc/stm32h7xx_ll_pwr.h                    |  4602 +++---
 .../Inc/stm32h7xx_ll_rcc.h                    | 12814 +++++++--------
 .../Inc/stm32h7xx_ll_system.h                 |  4884 +++---
 .../Inc/stm32h7xx_ll_tim.h                    | 10426 ++++++------
 .../Inc/stm32h7xx_ll_usart.h                  |  8802 +++++-----
 .../Inc/stm32h7xx_ll_utils.h                  |   802 +-
 Drivers/STM32H7xx_HAL_Driver/LICENSE.txt      |    12 +-
 ECU.ioc                                       |     5 +-
 .../Third_Party/FreeRTOS/Source/LICENSE       |    36 +-
 STM32H743VITX_FLASH.ld                        |     4 +-
 30 files changed, 47494 insertions(+), 47474 deletions(-)

diff --git a/Core/Inc/dynamic_controls/security_architecture.h b/Core/Inc/dynamic_controls/security_architecture.h
index a4935962..65100a8c 100644
--- a/Core/Inc/dynamic_controls/security_architecture.h
+++ b/Core/Inc/dynamic_controls/security_architecture.h
@@ -13,7 +13,6 @@
 #define SPEED_MIN_THRESHOLD 1
 #define IMU_MAX_LONG_ACCEL_THRESHOLD 1
 
-void init_moving_average();
 uint8_t is_imu_bse_ok();
 uint8_t is_imu_speed_ok();
 
diff --git a/Core/Inc/util/global_definitions.h b/Core/Inc/util/global_definitions.h
index 88fe0669..d4552b1f 100644
--- a/Core/Inc/util/global_definitions.h
+++ b/Core/Inc/util/global_definitions.h
@@ -116,6 +116,7 @@ typedef enum {
 #define REGEN_WARN_FLAG           (1 << 10)
 #define DYNAMIC_CONTROL_WARN_FLAG (1 << 11)
 #define FLASH_SAVE_LIMIT_FLAG     (1 << 12)
+#define CROSS_VALIDATION_FLAG	  (1 << 13)
 // Soft error flags (RTD keeps on, torque ref to inverter is set to 0)
 
 #define BSE_ERROR_FLAG  (1 << 16) // Regulamento: EV.5.7 (2021)
diff --git a/Core/Src/dynamic_controls/initializer_controls.c b/Core/Src/dynamic_controls/initializer_controls.c
index 04dad96d..0550159c 100644
--- a/Core/Src/dynamic_controls/initializer_controls.c
+++ b/Core/Src/dynamic_controls/initializer_controls.c
@@ -11,7 +11,6 @@
 #include "dynamic_controls/lateral_control.h"
 #include "dynamic_controls/longitudinal_control.h"
 #include "util/global_definitions.h"
-#include "security_architecture.h"
 
 void init_controls() {
 
@@ -19,6 +18,4 @@ void init_controls() {
     init_lateral_control();
     // Longitudinal Control
     init_longitudinal_control();
-    // Moving average
-    init_moving_average();
 }
diff --git a/Core/Src/dynamic_controls/security_architecture.c b/Core/Src/dynamic_controls/security_architecture.c
index ae280cde..71c7fdf9 100644
--- a/Core/Src/dynamic_controls/security_architecture.c
+++ b/Core/Src/dynamic_controls/security_architecture.c
@@ -29,25 +29,18 @@ void cross_validation(void* argument) {
     for (;;) {
         ECU_ENABLE_BREAKPOINT_DEBUG();
 
-        is_imu_bse_ok();
-        is_imu_speed_ok();
-        if(is_imu_bse_ok && is_imu_speed_ok){
-//        	enable torque vectoring if disabled
-        }
-        else{
-//        	prevent enabling torque vectoring if disabled
-//			disable torque vectoring if enabled
-        }
+        moving_average(&IMU_long_accel_filtered, raw_IMU_long_accel_data);
+        moving_average(&speed_filtered, raw_speed_data);
+
+        if(!is_imu_bse_ok() || !is_imu_speed_ok())
+        	osEventFlagsSet(e_ECU_control_flagsHandle, CROSS_VALIDATION_FLAG);
+        else
+        	osEventFlagsClear(e_ECU_control_flagsHandle, CROSS_VALIDATION_FLAG);
 
     }
 }
 
 
-void init_moving_average(){
-	moving_average(&IMU_long_accel_filtered, raw_IMU_long_accel_data);
-	moving_average(&speed_filtered, raw_speed_data);
-}
-
 uint8_t is_imu_bse_ok(){
 	if(bse_active && (IMU_long_accel_filtered > IMU_MAX_LONG_ACCEL_THRESHOLD))
 		return 0;
diff --git a/Core/Src/main.c b/Core/Src/main.c
index a2ff3525..cf73f8bd 100644
--- a/Core/Src/main.c
+++ b/Core/Src/main.c
@@ -1,1257 +1,1268 @@
-/* USER CODE BEGIN Header */
-/**
-  ******************************************************************************
-  * @file           : main.c
-  * @brief          : Main program body
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-/* USER CODE END Header */
-/* Includes ------------------------------------------------------------------*/
-#include "main.h"
-#include "cmsis_os.h"
-
-/* Private includes ----------------------------------------------------------*/
-/* USER CODE BEGIN Includes */
-#include "CAN/inverter_can.h"
-#include "CAN/general_can.h"
-#include "util/initializers.h"
-#include "sensors/APPS.h"
-#include "sensors/encoder_speed.h"
-#include "util/global_instances.h"
-#include "util/main_task.h"
-#include "leds/debug_leds_handler.h"
-#include "leds/rgb_led_handler.h"
-#include "util/CMSIS_extra/global_variables_handler.h"
-#include "datalogging/speed.h"
-#include "datalogging/odometer_save.h"
-/* USER CODE END Includes */
-
-/* Private typedef -----------------------------------------------------------*/
-/* USER CODE BEGIN PTD */
-
-/* USER CODE END PTD */
-
-/* Private define ------------------------------------------------------------*/
-/* USER CODE BEGIN PD */
-/* USER CODE END PD */
-
-/* Private macro -------------------------------------------------------------*/
-/* USER CODE BEGIN PM */
-
-/* USER CODE END PM */
-
-/* Private variables ---------------------------------------------------------*/
-ADC_HandleTypeDef hadc1;
-DMA_HandleTypeDef hdma_adc1;
-
-FDCAN_HandleTypeDef hfdcan1;
-FDCAN_HandleTypeDef hfdcan2;
-
-I2C_HandleTypeDef hi2c3;
-
-UART_HandleTypeDef hlpuart1;
-
-SPI_HandleTypeDef hspi1;
-
-TIM_HandleTypeDef htim1;
-TIM_HandleTypeDef htim2;
-
-/* Definitions for t_main_task */
-osThreadId_t t_main_taskHandle;
-const osThreadAttr_t t_main_task_attributes = {
-  .name = "t_main_task",
-  .stack_size = 1024 * 4,
-  .priority = (osPriority_t) osPriorityNormal,
-};
-/* Definitions for t_torque_parameters */
-osThreadId_t t_torque_parametersHandle;
-const osThreadAttr_t t_torque_parameters_attributes = {
-  .name = "t_torque_parameters",
-  .stack_size = 1024 * 4,
-  .priority = (osPriority_t) osPriorityLow,
-};
-/* Definitions for t_datalogger */
-osThreadId_t t_dataloggerHandle;
-const osThreadAttr_t t_datalogger_attributes = {
-  .name = "t_datalogger",
-  .stack_size = 1024 * 4,
-  .priority = (osPriority_t) osPriorityLow,
-};
-/* Definitions for t_APPS_read */
-osThreadId_t t_APPS_readHandle;
-const osThreadAttr_t t_APPS_read_attributes = {
-  .name = "t_APPS_read",
-  .stack_size = 1024 * 4,
-  .priority = (osPriority_t) osPriorityLow,
-};
-/* Definitions for t_steering_read */
-osThreadId_t t_steering_readHandle;
-const osThreadAttr_t t_steering_read_attributes = {
-  .name = "t_steering_read",
-  .stack_size = 1024 * 4,
-  .priority = (osPriority_t) osPriorityLow,
-};
-/* Definitions for t_encoder_speed_calc */
-osThreadId_t t_encoder_speed_calcHandle;
-const osThreadAttr_t t_encoder_speed_calc_attributes = {
-  .name = "t_encoder_speed_calc",
-  .stack_size = 1024 * 4,
-  .priority = (osPriority_t) osPriorityLow,
-};
-/* Definitions for t_odometer_calc */
-osThreadId_t t_odometer_calcHandle;
-const osThreadAttr_t t_odometer_calc_attributes = {
-  .name = "t_odometer_calc",
-  .stack_size = 1024 * 4,
-  .priority = (osPriority_t) osPriorityLow,
-};
-/* Definitions for t_torque_message */
-osThreadId_t t_torque_messageHandle;
-const osThreadAttr_t t_torque_message_attributes = {
-  .name = "t_torque_message",
-  .stack_size = 1024 * 4,
-  .priority = (osPriority_t) osPriorityLow,
-};
-/* Definitions for t_torque_manager */
-osThreadId_t t_torque_managerHandle;
-const osThreadAttr_t t_torque_manager_attributes = {
-  .name = "t_torque_manager",
-  .stack_size = 1024 * 4,
-  .priority = (osPriority_t) osPriorityLow,
-};
-/* Definitions for t_debug_leds */
-osThreadId_t t_debug_ledsHandle;
-const osThreadAttr_t t_debug_leds_attributes = {
-  .name = "t_debug_leds",
-  .stack_size = 1024 * 4,
-  .priority = (osPriority_t) osPriorityLow,
-};
-/* Definitions for t_rgb_led */
-osThreadId_t t_rgb_ledHandle;
-const osThreadAttr_t t_rgb_led_attributes = {
-  .name = "t_rgb_led",
-  .stack_size = 1024 * 4,
-  .priority = (osPriority_t) osPriorityLow,
-};
-/* Definitions for t_seleciona_modo */
-osThreadId_t t_seleciona_modoHandle;
-const osThreadAttr_t t_seleciona_modo_attributes = {
-  .name = "t_seleciona_modo",
-  .stack_size = 1024 * 4,
-  .priority = (osPriority_t) osPriorityLow,
-};
-/* Definitions for t_RTD */
-osThreadId_t t_RTDHandle;
-const osThreadAttr_t t_RTD_attributes = {
-  .name = "t_RTD",
-  .stack_size = 1024 * 4,
-  .priority = (osPriority_t) osPriorityLow,
-};
-/* Definitions for t_throttle_control */
-osThreadId_t t_throttle_controlHandle;
-const osThreadAttr_t t_throttle_control_attributes = {
-  .name = "t_throttle_control",
-  .stack_size = 1024 * 4,
-  .priority = (osPriority_t) osPriorityLow,
-};
-/* Definitions for t_datalog_acquisition */
-osThreadId_t t_datalog_acquisitionHandle;
-const osThreadAttr_t t_datalog_acquisition_attributes = {
-  .name = "t_datalog_acquisition",
-  .stack_size = 1024 * 4,
-  .priority = (osPriority_t) osPriorityLow,
-};
-/* Definitions for t_inverter_comm_error */
-osThreadId_t t_inverter_comm_errorHandle;
-const osThreadAttr_t t_inverter_comm_error_attributes = {
-  .name = "t_inverter_comm_error",
-  .stack_size = 1024 * 4,
-  .priority = (osPriority_t) osPriorityLow,
-};
-/* Definitions for t_inverter_datalog */
-osThreadId_t t_inverter_datalogHandle;
-const osThreadAttr_t t_inverter_datalog_attributes = {
-  .name = "t_inverter_datalog",
-  .stack_size = 1024 * 4,
-  .priority = (osPriority_t) osPriorityLow,
-};
-/* Definitions for t_pilot_reset */
-osThreadId_t t_pilot_resetHandle;
-const osThreadAttr_t t_pilot_reset_attributes = {
-  .name = "t_pilot_reset",
-  .stack_size = 1024 * 4,
-  .priority = (osPriority_t) osPriorityLow,
-};
-/* Definitions for t_buttons_handler */
-osThreadId_t t_buttons_handlerHandle;
-const osThreadAttr_t t_buttons_handler_attributes = {
-  .name = "t_buttons_handler",
-  .stack_size = 1024 * 4,
-  .priority = (osPriority_t) osPriorityLow,
-};
-/* Definitions for t_speed_datalog */
-osThreadId_t t_speed_datalogHandle;
-const osThreadAttr_t t_speed_datalog_attributes = {
-  .name = "t_speed_datalog",
-  .stack_size = 1024 * 4,
-  .priority = (osPriority_t) osPriorityLow,
-};
-/* Definitions for t_odometer_save */
-osThreadId_t t_odometer_saveHandle;
-const osThreadAttr_t t_odometer_save_attributes = {
-  .name = "t_odometer_save",
-  .stack_size = 1024 * 4,
-  .priority = (osPriority_t) osPriorityLow,
-};
-/* Definitions for t_dynamic_controls_choice */
-osThreadId_t t_dynamic_controls_choiceHandle;
-const osThreadAttr_t t_dynamic_controls_choice_attributes = {
-    .name       = "t_dynamic_controls_choice",
-    .stack_size = 1024 * 4,
-    .priority   = (osPriority_t)osPriorityLow,
-};
-/* Definitions for q_encoder_int_message */
-osMessageQueueId_t q_encoder_int_messageHandle;
-const osMessageQueueAttr_t q_encoder_int_message_attributes = {
-  .name = "q_encoder_int_message"
-};
-/* Definitions for q_torque_message */
-osMessageQueueId_t q_torque_messageHandle;
-const osMessageQueueAttr_t q_torque_message_attributes = {
-  .name = "q_torque_message"
-};
-/* Definitions for q_ref_torque_message */
-osMessageQueueId_t q_ref_torque_messageHandle;
-const osMessageQueueAttr_t q_ref_torque_message_attributes = {
-  .name = "q_ref_torque_message"
-};
-/* Definitions for q_datalog_message */
-osMessageQueueId_t q_datalog_messageHandle;
-const osMessageQueueAttr_t q_datalog_message_attributes = {
-  .name = "q_datalog_message"
-};
-/* Definitions for q_debug_leds_message */
-osMessageQueueId_t q_debug_leds_messageHandle;
-const osMessageQueueAttr_t q_debug_leds_message_attributes = {
-  .name = "q_debug_leds_message"
-};
-/* Definitions for q_rgb_led_message */
-osMessageQueueId_t q_rgb_led_messageHandle;
-const osMessageQueueAttr_t q_rgb_led_message_attributes = {
-  .name = "q_rgb_led_message"
-};
-/* Definitions for q_throttle_control */
-osMessageQueueId_t q_throttle_controlHandle;
-const osMessageQueueAttr_t q_throttle_control_attributes = {
-  .name = "q_throttle_control"
-};
-/* Definitions for q_encoder_speeds_message */
-osMessageQueueId_t q_encoder_speeds_messageHandle;
-const osMessageQueueAttr_t q_encoder_speeds_message_attributes = {
-  .name = "q_encoder_speeds_message"
-};
-/* Definitions for q_odometer_calc_save_message */
-osMessageQueueId_t q_odometer_calc_save_messageHandle;
-const osMessageQueueAttr_t q_odometer_calc_save_message_attributes = {
-  .name = "q_odometer_calc_save_message"
-};
-/* Definitions for q_ids_can_inverter */
-osMessageQueueId_t q_ids_can_inverterHandle;
-const osMessageQueueAttr_t q_ids_can_inverter_attributes = {
-  .name = "q_ids_can_inverter"
-};
-/* Definitions for tim_SU_F_error */
-osTimerId_t tim_SU_F_errorHandle;
-const osTimerAttr_t tim_SU_F_error_attributes = {
-  .name = "tim_SU_F_error"
-};
-/* Definitions for tim_APPS_error */
-osTimerId_t tim_APPS_errorHandle;
-const osTimerAttr_t tim_APPS_error_attributes = {
-  .name = "tim_APPS_error"
-};
-/* Definitions for tim_inverter_BUS_OFF_error */
-osTimerId_t tim_inverter_BUS_OFF_errorHandle;
-const osTimerAttr_t tim_inverter_BUS_OFF_error_attributes = {
-  .name = "tim_inverter_BUS_OFF_error"
-};
-/* Definitions for tim_inverter_ready */
-osTimerId_t tim_inverter_readyHandle;
-const osTimerAttr_t tim_inverter_ready_attributes = {
-  .name = "tim_inverter_ready"
-};
-/* Definitions for tim_inverter_can_transmit_error */
-osTimerId_t tim_inverter_can_transmit_errorHandle;
-const osTimerAttr_t tim_inverter_can_transmit_error_attributes = {
-  .name = "tim_inverter_can_transmit_error"
-};
-/* Definitions for tim_left_inv_error */
-osTimerId_t tim_left_inv_errorHandle;
-const osTimerAttr_t tim_left_inv_error_attributes = {
-  .name = "tim_left_inv_error"
-};
-/* Definitions for tim_right_inv_error */
-osTimerId_t tim_right_inv_errorHandle;
-const osTimerAttr_t tim_right_inv_error_attributes = {
-  .name = "tim_right_inv_error"
-};
-/* Definitions for m_state_parameter_mutex */
-osMutexId_t m_state_parameter_mutexHandle;
-const osMutexAttr_t m_state_parameter_mutex_attributes = {
-  .name = "m_state_parameter_mutex"
-};
-/* Definitions for e_ECU_control_flags */
-osEventFlagsId_t e_ECU_control_flagsHandle;
-const osEventFlagsAttr_t e_ECU_control_flags_attributes = {
-  .name = "e_ECU_control_flags"
-};
-/* USER CODE BEGIN PV */
-
-/* USER CODE END PV */
-
-/* Private function prototypes -----------------------------------------------*/
-void SystemClock_Config(void);
-static void MX_GPIO_Init(void);
-static void MX_DMA_Init(void);
-static void MX_ADC1_Init(void);
-static void MX_FDCAN1_Init(void);
-static void MX_FDCAN2_Init(void);
-static void MX_LPUART1_UART_Init(void);
-static void MX_SPI1_Init(void);
-static void MX_TIM1_Init(void);
-static void MX_I2C3_Init(void);
-static void MX_TIM2_Init(void);
-void main_task(void *argument);
-extern void torque_parameters(void *argument);
-extern void datalogger(void *argument);
-extern void APPS_read(void *argument);
-extern void steering_read(void *argument);
-extern void encoder_speed_calc(void *argument);
-extern void odometer_calc(void *argument);
-extern void torque_message(void *argument);
-extern void torque_manager(void *argument);
-extern void debug_leds(void *argument);
-extern void rgb_led(void *argument);
-extern void seleciona_modo(void *argument);
-extern void RTD(void *argument);
-extern void throttle_control(void *argument);
-extern void datalog_acquisition(void *argument);
-extern void inverter_comm_error(void *argument);
-extern void inverter_datalog(void *argument);
-extern void pilot_reset(void *argument);
-extern void buttons_handler(void *argument);
-extern void speed_datalog(void *argument);
-extern void odometer_save(void *argument);
-extern void dynamic_controls_choice(void *argument);
-extern void errors_with_timer_callback(void *argument);
-extern void inverter_BUS_OFF_error_callback(void *argument);
-extern void inverter_ready_callback(void *argument);
-extern void left_inv_error_callback(void *argument);
-extern void right_inv_error_callback(void *argument);
-
-/* USER CODE BEGIN PFP */
-
-/* USER CODE END PFP */
-
-/* Private user code ---------------------------------------------------------*/
-/* USER CODE BEGIN 0 */
-
-/* USER CODE END 0 */
-
-/**
-  * @brief  The application entry point.
-  * @retval int
-  */
-int main(void)
-{
-  /* USER CODE BEGIN 1 */
-
-  /* USER CODE END 1 */
-
-  /* MCU Configuration--------------------------------------------------------*/
-
-  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
-  HAL_Init();
-
-  /* USER CODE BEGIN Init */
-//  init_NVIC_priorities();
-  /* USER CODE END Init */
-
-  /* Configure the system clock */
-  SystemClock_Config();
-
-  /* USER CODE BEGIN SysInit */
-
-  /* USER CODE END SysInit */
-
-  /* Initialize all configured peripherals */
-  MX_GPIO_Init();
-  MX_DMA_Init();
-  MX_ADC1_Init();
-  MX_FDCAN1_Init();
-  MX_FDCAN2_Init();
-  MX_LPUART1_UART_Init();
-  MX_SPI1_Init();
-  MX_TIM1_Init();
-  MX_I2C3_Init();
-  MX_TIM2_Init();
-  /* USER CODE BEGIN 2 */
-  init_ECU();
-  /* USER CODE END 2 */
-
-  /* Init scheduler */
-  osKernelInitialize();
-  /* Create the mutex(es) */
-  /* creation of m_state_parameter_mutex */
-  m_state_parameter_mutexHandle = osMutexNew(&m_state_parameter_mutex_attributes);
-
-  /* USER CODE BEGIN RTOS_MUTEX */
-  /* add mutexes, ... */
-  /* USER CODE END RTOS_MUTEX */
-
-  /* USER CODE BEGIN RTOS_SEMAPHORES */
-  /* add semaphores, ... */
-  /* USER CODE END RTOS_SEMAPHORES */
-
-  /* Create the timer(s) */
-  /* creation of tim_SU_F_error */
-  tim_SU_F_errorHandle = osTimerNew(errors_with_timer_callback, osTimerOnce, (void*) SU_F_ERROR_FLAG, &tim_SU_F_error_attributes);
-
-  /* creation of tim_APPS_error */
-  tim_APPS_errorHandle = osTimerNew(errors_with_timer_callback, osTimerOnce, (void*) APPS_ERROR_FLAG, &tim_APPS_error_attributes);
-
-  /* creation of tim_inverter_BUS_OFF_error */
-  tim_inverter_BUS_OFF_errorHandle = osTimerNew(inverter_BUS_OFF_error_callback, osTimerOnce, NULL, &tim_inverter_BUS_OFF_error_attributes);
-
-  /* creation of tim_inverter_ready */
-  tim_inverter_readyHandle = osTimerNew(inverter_ready_callback, osTimerOnce, NULL, &tim_inverter_ready_attributes);
-
-  /* creation of tim_inverter_can_transmit_error */
-  tim_inverter_can_transmit_errorHandle = osTimerNew(errors_with_timer_callback, osTimerOnce, (void*) INVERTER_CAN_TRANSMIT_ERROR_FLAG, &tim_inverter_can_transmit_error_attributes);
-
-  /* creation of tim_left_inv_error */
-  tim_left_inv_errorHandle = osTimerNew(left_inv_error_callback, osTimerPeriodic, (void*) LEFT_INVERTER_COMM_ERROR_FLAG, &tim_left_inv_error_attributes);
-
-  /* creation of tim_right_inv_error */
-  tim_right_inv_errorHandle = osTimerNew(right_inv_error_callback, osTimerPeriodic, (void*) RIGHT_INVERTER_COMM_ERROR_FLAG, &tim_right_inv_error_attributes);
-
-  /* USER CODE BEGIN RTOS_TIMERS */
-  /* start timers, add new ones, ... */
-  /* USER CODE END RTOS_TIMERS */
-
-  /* Create the queue(s) */
-  /* creation of q_encoder_int_message */
-  q_encoder_int_messageHandle = osMessageQueueNew (16, sizeof(encoder_int_message_t), &q_encoder_int_message_attributes);
-
-  /* creation of q_torque_message */
-  q_torque_messageHandle = osMessageQueueNew (16, sizeof(torque_message_t), &q_torque_message_attributes);
-
-  /* creation of q_ref_torque_message */
-  q_ref_torque_messageHandle = osMessageQueueNew (16, sizeof(ref_torque_t), &q_ref_torque_message_attributes);
-
-  /* creation of q_datalog_message */
-  q_datalog_messageHandle = osMessageQueueNew (128, sizeof(datalog_message_t), &q_datalog_message_attributes);
-
-  /* creation of q_debug_leds_message */
-  q_debug_leds_messageHandle = osMessageQueueNew (16, sizeof(debug_led_message_t), &q_debug_leds_message_attributes);
-
-  /* creation of q_rgb_led_message */
-  q_rgb_led_messageHandle = osMessageQueueNew (16, sizeof(rgb_led_message_t), &q_rgb_led_message_attributes);
-
-  /* creation of q_throttle_control */
-  q_throttle_controlHandle = osMessageQueueNew (16, sizeof(uint16_t), &q_throttle_control_attributes);
-
-  /* creation of q_encoder_speeds_message */
-  q_encoder_speeds_messageHandle = osMessageQueueNew (1, sizeof(encoder_speeds_message_t), &q_encoder_speeds_message_attributes);
-
-  /* creation of q_odometer_calc_save_message */
-  q_odometer_calc_save_messageHandle = osMessageQueueNew (1, sizeof(odometer_message_t), &q_odometer_calc_save_message_attributes);
-
-  /* creation of q_ids_can_inverter */
-  q_ids_can_inverterHandle = osMessageQueueNew (32, sizeof(uint32_t), &q_ids_can_inverter_attributes);
-
-  /* USER CODE BEGIN RTOS_QUEUES */
-  /* add queues, ... */
-  /* USER CODE END RTOS_QUEUES */
-
-  /* Create the thread(s) */
-  /* creation of t_main_task */
-  t_main_taskHandle = osThreadNew(main_task, NULL, &t_main_task_attributes);
-
-  /* creation of t_torque_parameters */
-  t_torque_parametersHandle = osThreadNew(torque_parameters, NULL, &t_torque_parameters_attributes);
-
-  /* creation of t_datalogger */
-  t_dataloggerHandle = osThreadNew(datalogger, NULL, &t_datalogger_attributes);
-
-  /* creation of t_APPS_read */
-  t_APPS_readHandle = osThreadNew(APPS_read, NULL, &t_APPS_read_attributes);
-
-  /* creation of t_steering_read */
-  t_steering_readHandle = osThreadNew(steering_read, NULL, &t_steering_read_attributes);
-
-  /* creation of t_encoder_speed_calc */
-  t_encoder_speed_calcHandle = osThreadNew(encoder_speed_calc, NULL, &t_encoder_speed_calc_attributes);
-
-  /* creation of t_odometer_calc */
-  t_odometer_calcHandle = osThreadNew(odometer_calc, NULL, &t_odometer_calc_attributes);
-
-  /* creation of t_torque_message */
-  t_torque_messageHandle = osThreadNew(torque_message, NULL, &t_torque_message_attributes);
-
-  /* creation of t_torque_manager */
-  t_torque_managerHandle = osThreadNew(torque_manager, NULL, &t_torque_manager_attributes);
-
-  /* creation of t_debug_leds */
-  t_debug_ledsHandle = osThreadNew(debug_leds, NULL, &t_debug_leds_attributes);
-
-  /* creation of t_rgb_led */
-  t_rgb_ledHandle = osThreadNew(rgb_led, NULL, &t_rgb_led_attributes);
-
-  /* creation of t_seleciona_modo */
-  t_seleciona_modoHandle = osThreadNew(seleciona_modo, NULL, &t_seleciona_modo_attributes);
-
-  /* creation of t_RTD */
-  t_RTDHandle = osThreadNew(RTD, NULL, &t_RTD_attributes);
-
-  /* creation of t_throttle_control */
-  t_throttle_controlHandle = osThreadNew(throttle_control, NULL, &t_throttle_control_attributes);
-
-  /* creation of t_datalog_acquisition */
-  t_datalog_acquisitionHandle = osThreadNew(datalog_acquisition, NULL, &t_datalog_acquisition_attributes);
-
-  /* creation of t_inverter_comm_error */
-  t_inverter_comm_errorHandle = osThreadNew(inverter_comm_error, NULL, &t_inverter_comm_error_attributes);
-
-  /* creation of t_inverter_datalog */
-  t_inverter_datalogHandle = osThreadNew(inverter_datalog, NULL, &t_inverter_datalog_attributes);
-
-  /* creation of t_pilot_reset */
-  t_pilot_resetHandle = osThreadNew(pilot_reset, NULL, &t_pilot_reset_attributes);
-
-  /* creation of t_buttons_handler */
-  t_buttons_handlerHandle = osThreadNew(buttons_handler, NULL, &t_buttons_handler_attributes);
-
-  /* creation of t_speed_datalog */
-  t_speed_datalogHandle = osThreadNew(speed_datalog, NULL, &t_speed_datalog_attributes);
-
-  /* creation of t_odometer_save */
-  t_odometer_saveHandle = osThreadNew(odometer_save, NULL, &t_odometer_save_attributes);
-
-  /* creation of t_dynamic_controls_choice */
-  t_dynamic_controls_choiceHandle = osThreadNew(dynamic_controls_choice, NULL, &t_dynamic_controls_choice_attributes);
-
-  /* USER CODE BEGIN RTOS_THREADS */
-  /* add threads, ... */
-  /* USER CODE END RTOS_THREADS */
-
-  /* creation of e_ECU_control_flags */
-  e_ECU_control_flagsHandle = osEventFlagsNew(&e_ECU_control_flags_attributes);
-
-  /* USER CODE BEGIN RTOS_EVENTS */
-  /* add events, ... */
-  /* USER CODE END RTOS_EVENTS */
-
-  /* Start scheduler */
-  osKernelStart();
-
-  /* We should never get here as control is now taken by the scheduler */
-  /* Infinite loop */
-  /* USER CODE BEGIN WHILE */
-  while (1)
-  {
-    /* USER CODE END WHILE */
-
-    /* USER CODE BEGIN 3 */
-  }
-  /* USER CODE END 3 */
-}
-
-/**
-  * @brief System Clock Configuration
-  * @retval None
-  */
-void SystemClock_Config(void)
-{
-  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
-  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
-
-  /** Supply configuration update enable
-  */
-  HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
-
-  /** Configure the main internal regulator output voltage
-  */
-  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3);
-
-  while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
-
-  /** Macro to configure the PLL clock source
-  */
-  __HAL_RCC_PLL_PLLSOURCE_CONFIG(RCC_PLLSOURCE_HSE);
-
-  /** Initializes the RCC Oscillators according to the specified parameters
-  * in the RCC_OscInitTypeDef structure.
-  */
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
-  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
-  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
-  RCC_OscInitStruct.PLL.PLLM = 1;
-  RCC_OscInitStruct.PLL.PLLN = 50;
-  RCC_OscInitStruct.PLL.PLLP = 2;
-  RCC_OscInitStruct.PLL.PLLQ = 4;
-  RCC_OscInitStruct.PLL.PLLR = 2;
-  RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_3;
-  RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
-  RCC_OscInitStruct.PLL.PLLFRACN = 0;
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    Error_Handler();
-  }
-
-  /** Initializes the CPU, AHB and APB buses clocks
-  */
-  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
-                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2
-                              |RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1;
-  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
-  RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
-  RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
-  RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV1;
-  RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV1;
-
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
-  {
-    Error_Handler();
-  }
-}
-
-/**
-  * @brief ADC1 Initialization Function
-  * @param None
-  * @retval None
-  */
-static void MX_ADC1_Init(void)
-{
-
-  /* USER CODE BEGIN ADC1_Init 0 */
-
-  /* USER CODE END ADC1_Init 0 */
-
-  ADC_MultiModeTypeDef multimode = {0};
-  ADC_ChannelConfTypeDef sConfig = {0};
-
-  /* USER CODE BEGIN ADC1_Init 1 */
-
-  /* USER CODE END ADC1_Init 1 */
-
-  /** Common config
-  */
-  hadc1.Instance = ADC1;
-  hadc1.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV2;
-  hadc1.Init.Resolution = ADC_RESOLUTION_12B_OPT;
-  hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE;
-  hadc1.Init.EOCSelection = ADC_EOC_SEQ_CONV;
-  hadc1.Init.LowPowerAutoWait = DISABLE;
-  hadc1.Init.ContinuousConvMode = ENABLE;
-  hadc1.Init.NbrOfConversion = 6;
-  hadc1.Init.DiscontinuousConvMode = DISABLE;
-  hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
-  hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
-  hadc1.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DMA_CIRCULAR;
-  hadc1.Init.Overrun = ADC_OVR_DATA_OVERWRITTEN;
-  hadc1.Init.LeftBitShift = ADC_LEFTBITSHIFT_NONE;
-  hadc1.Init.OversamplingMode = DISABLE;
-  if (HAL_ADC_Init(&hadc1) != HAL_OK)
-  {
-    Error_Handler();
-  }
-
-  /** Configure the ADC multi-mode
-  */
-  multimode.Mode = ADC_MODE_INDEPENDENT;
-  if (HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode) != HAL_OK)
-  {
-    Error_Handler();
-  }
-
-  /** Configure Regular Channel
-  */
-  sConfig.Channel = ADC_CHANNEL_3;
-  sConfig.Rank = ADC_REGULAR_RANK_1;
-  sConfig.SamplingTime = ADC_SAMPLETIME_810CYCLES_5;
-  sConfig.SingleDiff = ADC_SINGLE_ENDED;
-  sConfig.OffsetNumber = ADC_OFFSET_NONE;
-  sConfig.Offset = 0;
-  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
-  {
-    Error_Handler();
-  }
-
-  /** Configure Regular Channel
-  */
-  sConfig.Channel = ADC_CHANNEL_4;
-  sConfig.Rank = ADC_REGULAR_RANK_2;
-  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
-  {
-    Error_Handler();
-  }
-
-  /** Configure Regular Channel
-  */
-  sConfig.Channel = ADC_CHANNEL_5;
-  sConfig.Rank = ADC_REGULAR_RANK_3;
-  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
-  {
-    Error_Handler();
-  }
-
-  /** Configure Regular Channel
-  */
-  sConfig.Channel = ADC_CHANNEL_7;
-  sConfig.Rank = ADC_REGULAR_RANK_4;
-  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
-  {
-    Error_Handler();
-  }
-
-  /** Configure Regular Channel
-  */
-  sConfig.Channel = ADC_CHANNEL_8;
-  sConfig.Rank = ADC_REGULAR_RANK_5;
-  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
-  {
-    Error_Handler();
-  }
-
-  /** Configure Regular Channel
-  */
-  sConfig.Channel = ADC_CHANNEL_19;
-  sConfig.Rank = ADC_REGULAR_RANK_6;
-  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
-  {
-    Error_Handler();
-  }
-  /* USER CODE BEGIN ADC1_Init 2 */
-
-  /* USER CODE END ADC1_Init 2 */
-
-}
-
-/**
-  * @brief FDCAN1 Initialization Function
-  * @param None
-  * @retval None
-  */
-static void MX_FDCAN1_Init(void)
-{
-
-  /* USER CODE BEGIN FDCAN1_Init 0 */
-
-  /* USER CODE END FDCAN1_Init 0 */
-
-  /* USER CODE BEGIN FDCAN1_Init 1 */
-
-  /* USER CODE END FDCAN1_Init 1 */
-  hfdcan1.Instance = FDCAN1;
-  hfdcan1.Init.FrameFormat = FDCAN_FRAME_CLASSIC;
-  hfdcan1.Init.Mode = FDCAN_MODE_NORMAL;
-  hfdcan1.Init.AutoRetransmission = DISABLE;
-  hfdcan1.Init.TransmitPause = DISABLE;
-  hfdcan1.Init.ProtocolException = DISABLE;
-  hfdcan1.Init.NominalPrescaler = 5;
-  hfdcan1.Init.NominalSyncJumpWidth = 4;
-  hfdcan1.Init.NominalTimeSeg1 = 27;
-  hfdcan1.Init.NominalTimeSeg2 = 4;
-  hfdcan1.Init.DataPrescaler = 5;
-  hfdcan1.Init.DataSyncJumpWidth = 4;
-  hfdcan1.Init.DataTimeSeg1 = 27;
-  hfdcan1.Init.DataTimeSeg2 = 4;
-  hfdcan1.Init.MessageRAMOffset = 0;
-  hfdcan1.Init.StdFiltersNbr = 0;
-  hfdcan1.Init.ExtFiltersNbr = 0;
-  hfdcan1.Init.RxFifo0ElmtsNbr = 32;
-  hfdcan1.Init.RxFifo0ElmtSize = FDCAN_DATA_BYTES_8;
-  hfdcan1.Init.RxFifo1ElmtsNbr = 32;
-  hfdcan1.Init.RxFifo1ElmtSize = FDCAN_DATA_BYTES_8;
-  hfdcan1.Init.RxBuffersNbr = 32;
-  hfdcan1.Init.RxBufferSize = FDCAN_DATA_BYTES_8;
-  hfdcan1.Init.TxEventsNbr = 32;
-  hfdcan1.Init.TxBuffersNbr = 32;
-  hfdcan1.Init.TxFifoQueueElmtsNbr = 32;
-  hfdcan1.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION;
-  hfdcan1.Init.TxElmtSize = FDCAN_DATA_BYTES_8;
-  if (HAL_FDCAN_Init(&hfdcan1) != HAL_OK)
-  {
-    Error_Handler();
-  }
-  /* USER CODE BEGIN FDCAN1_Init 2 */
-
-  /* USER CODE END FDCAN1_Init 2 */
-
-}
-
-/**
-  * @brief FDCAN2 Initialization Function
-  * @param None
-  * @retval None
-  */
-static void MX_FDCAN2_Init(void)
-{
-
-  /* USER CODE BEGIN FDCAN2_Init 0 */
-
-  /* USER CODE END FDCAN2_Init 0 */
-
-  /* USER CODE BEGIN FDCAN2_Init 1 */
-
-  /* USER CODE END FDCAN2_Init 1 */
-  hfdcan2.Instance = FDCAN2;
-  hfdcan2.Init.FrameFormat = FDCAN_FRAME_CLASSIC;
-  hfdcan2.Init.Mode = FDCAN_MODE_NORMAL;
-  hfdcan2.Init.AutoRetransmission = DISABLE;
-  hfdcan2.Init.TransmitPause = DISABLE;
-  hfdcan2.Init.ProtocolException = DISABLE;
-  hfdcan2.Init.NominalPrescaler = 1;
-  hfdcan2.Init.NominalSyncJumpWidth = 2;
-  hfdcan2.Init.NominalTimeSeg1 = 13;
-  hfdcan2.Init.NominalTimeSeg2 = 2;
-  hfdcan2.Init.DataPrescaler = 1;
-  hfdcan2.Init.DataSyncJumpWidth = 2;
-  hfdcan2.Init.DataTimeSeg1 = 13;
-  hfdcan2.Init.DataTimeSeg2 = 2;
-  hfdcan2.Init.MessageRAMOffset = 1280;
-  hfdcan2.Init.StdFiltersNbr = 0;
-  hfdcan2.Init.ExtFiltersNbr = 0;
-  hfdcan2.Init.RxFifo0ElmtsNbr = 32;
-  hfdcan2.Init.RxFifo0ElmtSize = FDCAN_DATA_BYTES_8;
-  hfdcan2.Init.RxFifo1ElmtsNbr = 32;
-  hfdcan2.Init.RxFifo1ElmtSize = FDCAN_DATA_BYTES_8;
-  hfdcan2.Init.RxBuffersNbr = 32;
-  hfdcan2.Init.RxBufferSize = FDCAN_DATA_BYTES_8;
-  hfdcan2.Init.TxEventsNbr = 32;
-  hfdcan2.Init.TxBuffersNbr = 32;
-  hfdcan2.Init.TxFifoQueueElmtsNbr = 32;
-  hfdcan2.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION;
-  hfdcan2.Init.TxElmtSize = FDCAN_DATA_BYTES_8;
-  if (HAL_FDCAN_Init(&hfdcan2) != HAL_OK)
-  {
-    Error_Handler();
-  }
-  /* USER CODE BEGIN FDCAN2_Init 2 */
-
-  /* USER CODE END FDCAN2_Init 2 */
-
-}
-
-/**
-  * @brief I2C3 Initialization Function
-  * @param None
-  * @retval None
-  */
-static void MX_I2C3_Init(void)
-{
-
-  /* USER CODE BEGIN I2C3_Init 0 */
-
-  /* USER CODE END I2C3_Init 0 */
-
-  /* USER CODE BEGIN I2C3_Init 1 */
-
-  /* USER CODE END I2C3_Init 1 */
-  hi2c3.Instance = I2C3;
-  hi2c3.Init.Timing = 0x00C0EAFF;
-  hi2c3.Init.OwnAddress1 = 0;
-  hi2c3.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
-  hi2c3.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
-  hi2c3.Init.OwnAddress2 = 0;
-  hi2c3.Init.OwnAddress2Masks = I2C_OA2_NOMASK;
-  hi2c3.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
-  hi2c3.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
-  if (HAL_I2C_Init(&hi2c3) != HAL_OK)
-  {
-    Error_Handler();
-  }
-
-  /** Configure Analogue filter
-  */
-  if (HAL_I2CEx_ConfigAnalogFilter(&hi2c3, I2C_ANALOGFILTER_ENABLE) != HAL_OK)
-  {
-    Error_Handler();
-  }
-
-  /** Configure Digital filter
-  */
-  if (HAL_I2CEx_ConfigDigitalFilter(&hi2c3, 0) != HAL_OK)
-  {
-    Error_Handler();
-  }
-  /* USER CODE BEGIN I2C3_Init 2 */
-
-  /* USER CODE END I2C3_Init 2 */
-
-}
-
-/**
-  * @brief LPUART1 Initialization Function
-  * @param None
-  * @retval None
-  */
-static void MX_LPUART1_UART_Init(void)
-{
-
-  /* USER CODE BEGIN LPUART1_Init 0 */
-
-  /* USER CODE END LPUART1_Init 0 */
-
-  /* USER CODE BEGIN LPUART1_Init 1 */
-
-  /* USER CODE END LPUART1_Init 1 */
-  hlpuart1.Instance = LPUART1;
-  hlpuart1.Init.BaudRate = 209700;
-  hlpuart1.Init.WordLength = UART_WORDLENGTH_8B;
-  hlpuart1.Init.StopBits = UART_STOPBITS_1;
-  hlpuart1.Init.Parity = UART_PARITY_NONE;
-  hlpuart1.Init.Mode = UART_MODE_TX_RX;
-  hlpuart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
-  hlpuart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
-  hlpuart1.Init.ClockPrescaler = UART_PRESCALER_DIV1;
-  hlpuart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
-  hlpuart1.FifoMode = UART_FIFOMODE_DISABLE;
-  if (HAL_UART_Init(&hlpuart1) != HAL_OK)
-  {
-    Error_Handler();
-  }
-  if (HAL_UARTEx_SetTxFifoThreshold(&hlpuart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
-  {
-    Error_Handler();
-  }
-  if (HAL_UARTEx_SetRxFifoThreshold(&hlpuart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
-  {
-    Error_Handler();
-  }
-  if (HAL_UARTEx_DisableFifoMode(&hlpuart1) != HAL_OK)
-  {
-    Error_Handler();
-  }
-  /* USER CODE BEGIN LPUART1_Init 2 */
-
-  /* USER CODE END LPUART1_Init 2 */
-
-}
-
-/**
-  * @brief SPI1 Initialization Function
-  * @param None
-  * @retval None
-  */
-static void MX_SPI1_Init(void)
-{
-
-  /* USER CODE BEGIN SPI1_Init 0 */
-
-  /* USER CODE END SPI1_Init 0 */
-
-  /* USER CODE BEGIN SPI1_Init 1 */
-
-  /* USER CODE END SPI1_Init 1 */
-  /* SPI1 parameter configuration*/
-  hspi1.Instance = SPI1;
-  hspi1.Init.Mode = SPI_MODE_MASTER;
-  hspi1.Init.Direction = SPI_DIRECTION_2LINES;
-  hspi1.Init.DataSize = SPI_DATASIZE_4BIT;
-  hspi1.Init.CLKPolarity = SPI_POLARITY_LOW;
-  hspi1.Init.CLKPhase = SPI_PHASE_1EDGE;
-  hspi1.Init.NSS = SPI_NSS_SOFT;
-  hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_256;
-  hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB;
-  hspi1.Init.TIMode = SPI_TIMODE_DISABLE;
-  hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
-  hspi1.Init.CRCPolynomial = 0x0;
-  hspi1.Init.NSSPMode = SPI_NSS_PULSE_ENABLE;
-  hspi1.Init.NSSPolarity = SPI_NSS_POLARITY_LOW;
-  hspi1.Init.FifoThreshold = SPI_FIFO_THRESHOLD_01DATA;
-  hspi1.Init.TxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN;
-  hspi1.Init.RxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN;
-  hspi1.Init.MasterSSIdleness = SPI_MASTER_SS_IDLENESS_00CYCLE;
-  hspi1.Init.MasterInterDataIdleness = SPI_MASTER_INTERDATA_IDLENESS_00CYCLE;
-  hspi1.Init.MasterReceiverAutoSusp = SPI_MASTER_RX_AUTOSUSP_DISABLE;
-  hspi1.Init.MasterKeepIOState = SPI_MASTER_KEEP_IO_STATE_DISABLE;
-  hspi1.Init.IOSwap = SPI_IO_SWAP_DISABLE;
-  if (HAL_SPI_Init(&hspi1) != HAL_OK)
-  {
-    Error_Handler();
-  }
-  /* USER CODE BEGIN SPI1_Init 2 */
-
-  /* USER CODE END SPI1_Init 2 */
-
-}
-
-/**
-  * @brief TIM1 Initialization Function
-  * @param None
-  * @retval None
-  */
-static void MX_TIM1_Init(void)
-{
-
-  /* USER CODE BEGIN TIM1_Init 0 */
-
-  /* USER CODE END TIM1_Init 0 */
-
-  TIM_ClockConfigTypeDef sClockSourceConfig = {0};
-  TIM_MasterConfigTypeDef sMasterConfig = {0};
-
-  /* USER CODE BEGIN TIM1_Init 1 */
-
-  /* USER CODE END TIM1_Init 1 */
-  htim1.Instance = TIM1;
-  htim1.Init.Prescaler = 1799;
-  htim1.Init.CounterMode = TIM_COUNTERMODE_UP;
-  htim1.Init.Period = 4000;
-  htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
-  htim1.Init.RepetitionCounter = 0;
-  htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
-  if (HAL_TIM_Base_Init(&htim1) != HAL_OK)
-  {
-    Error_Handler();
-  }
-  sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
-  if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK)
-  {
-    Error_Handler();
-  }
-  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
-  sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET;
-  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
-  if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK)
-  {
-    Error_Handler();
-  }
-  /* USER CODE BEGIN TIM1_Init 2 */
-
-  /* USER CODE END TIM1_Init 2 */
-
-}
-
-/**
-  * @brief TIM2 Initialization Function
-  * @param None
-  * @retval None
-  */
-static void MX_TIM2_Init(void)
-{
-
-  /* USER CODE BEGIN TIM2_Init 0 */
-
-  /* USER CODE END TIM2_Init 0 */
-
-  TIM_ClockConfigTypeDef sClockSourceConfig = {0};
-  TIM_MasterConfigTypeDef sMasterConfig = {0};
-
-  /* USER CODE BEGIN TIM2_Init 1 */
-
-  /* USER CODE END TIM2_Init 1 */
-  htim2.Instance = TIM2;
-  htim2.Init.Prescaler = 0;
-  htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
-  htim2.Init.Period = 0xFFFFFFFF;
-  htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
-  htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
-  if (HAL_TIM_Base_Init(&htim2) != HAL_OK)
-  {
-    Error_Handler();
-  }
-  sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
-  if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK)
-  {
-    Error_Handler();
-  }
-  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
-  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
-  if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
-  {
-    Error_Handler();
-  }
-  /* USER CODE BEGIN TIM2_Init 2 */
-
-  /* USER CODE END TIM2_Init 2 */
-
-}
-
-/**
-  * Enable DMA controller clock
-  */
-static void MX_DMA_Init(void)
-{
-
-  /* DMA controller clock enable */
-  __HAL_RCC_DMA1_CLK_ENABLE();
-
-  /* DMA interrupt init */
-  /* DMA1_Stream0_IRQn interrupt configuration */
-  HAL_NVIC_SetPriority(DMA1_Stream0_IRQn, 5, 0);
-  HAL_NVIC_EnableIRQ(DMA1_Stream0_IRQn);
-
-}
-
-/**
-  * @brief GPIO Initialization Function
-  * @param None
-  * @retval None
-  */
-static void MX_GPIO_Init(void)
-{
-  GPIO_InitTypeDef GPIO_InitStruct = {0};
-
-  /* GPIO Ports Clock Enable */
-  __HAL_RCC_GPIOE_CLK_ENABLE();
-  __HAL_RCC_GPIOH_CLK_ENABLE();
-  __HAL_RCC_GPIOA_CLK_ENABLE();
-  __HAL_RCC_GPIOC_CLK_ENABLE();
-  __HAL_RCC_GPIOB_CLK_ENABLE();
-  __HAL_RCC_GPIOD_CLK_ENABLE();
-
-  /*Configure GPIO pin Output Level */
-  HAL_GPIO_WritePin(GPIOE, C_LED_DEBUG1_Pin|C_LED_DEBUG3_Pin, GPIO_PIN_SET);
-
-  /*Configure GPIO pin Output Level */
-  HAL_GPIO_WritePin(C_LED_DEBUG2_GPIO_Port, C_LED_DEBUG2_Pin, GPIO_PIN_RESET);
-
-  /*Configure GPIO pin Output Level */
-  HAL_GPIO_WritePin(GPIOD, C_LED_BLUE_Pin|C_LED_GREEN_Pin|C_LED_RED_Pin, GPIO_PIN_RESET);
-
-  /*Configure GPIO pin Output Level */
-  HAL_GPIO_WritePin(C_RTDS_GPIO_Port, C_RTDS_Pin, GPIO_PIN_RESET);
-
-  /*Configure GPIO pins : C_LED_DEBUG1_Pin C_LED_DEBUG2_Pin C_LED_DEBUG3_Pin */
-  GPIO_InitStruct.Pin = C_LED_DEBUG1_Pin|C_LED_DEBUG2_Pin|C_LED_DEBUG3_Pin;
-  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
-  HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
-
-  /*Configure GPIO pins : S_VEL1_Pin S_VEL2_Pin S_VEL3_Pin S_VEL4_Pin */
-  GPIO_InitStruct.Pin = S_VEL1_Pin|S_VEL2_Pin|S_VEL3_Pin|S_VEL4_Pin;
-  GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
-
-  /*Configure GPIO pins : C_LED_BLUE_Pin C_LED_GREEN_Pin C_LED_RED_Pin */
-  GPIO_InitStruct.Pin = C_LED_BLUE_Pin|C_LED_GREEN_Pin|C_LED_RED_Pin;
-  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
-  HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
-
-  /*Configure GPIO pins : B_DYNAMICS_CONTROLS_Pin B_MODE_Pin B_RTD_Pin */
-  GPIO_InitStruct.Pin = B_DYNAMICS_CONTROLS_Pin|B_MODE_Pin|B_RTD_Pin;
-  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
-
-  /*Configure GPIO pin : C_RTDS_Pin */
-  GPIO_InitStruct.Pin = C_RTDS_Pin;
-  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
-  HAL_GPIO_Init(C_RTDS_GPIO_Port, &GPIO_InitStruct);
-
-  /*Configure GPIO pin : BOOT1_Pin */
-  GPIO_InitStruct.Pin = BOOT1_Pin;
-  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  HAL_GPIO_Init(BOOT1_GPIO_Port, &GPIO_InitStruct);
-
-  /* EXTI interrupt init*/
-  HAL_NVIC_SetPriority(EXTI15_10_IRQn, 5, 0);
-  HAL_NVIC_EnableIRQ(EXTI15_10_IRQn);
-
-}
-
-/* USER CODE BEGIN 4 */
-
-/* USER CODE END 4 */
-
-/* USER CODE BEGIN Header_main_task */
-/**
-  * @brief  Function implementing the t_main_task thread.
-  * @param  argument: Not used
-  * @retval None
-  */
-/* USER CODE END Header_main_task */
-__weak void main_task(void *argument)
-{
-  /* USER CODE BEGIN 5 */
-  /* Infinite loop */
-  for(;;)
-  {
-    osDelay(1);
-  }
-  /* USER CODE END 5 */
-}
-
-/**
-  * @brief  Period elapsed callback in non blocking mode
-  * @note   This function is called  when TIM3 interrupt took place, inside
-  * HAL_TIM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment
-  * a global variable "uwTick" used as application time base.
-  * @param  htim : TIM handle
-  * @retval None
-  */
-void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
-{
-  /* USER CODE BEGIN Callback 0 */
-
-  /* USER CODE END Callback 0 */
-  if (htim->Instance == TIM3) {
-    HAL_IncTick();
-  }
-  /* USER CODE BEGIN Callback 1 */
-
-  /* USER CODE END Callback 1 */
-}
-
-/**
-  * @brief  This function is executed in case of error occurrence.
-  * @retval None
-  */
-void Error_Handler(void)
-{
-  /* USER CODE BEGIN Error_Handler_Debug */
-  /* User can add his own implementation to report the HAL error return state */
-
-  /* USER CODE END Error_Handler_Debug */
-}
-
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t *file, uint32_t line)
-{
-  /* USER CODE BEGIN 6 */
-  /* User can add his own implementation to report the file name and line number,
-     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-  /* USER CODE END 6 */
-}
-#endif /* USE_FULL_ASSERT */
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           : main.c
+  * @brief          : Main program body
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "cmsis_os.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "CAN/inverter_can.h"
+#include "CAN/general_can.h"
+#include "util/initializers.h"
+#include "sensors/APPS.h"
+#include "sensors/encoder_speed.h"
+#include "util/global_instances.h"
+#include "util/main_task.h"
+#include "leds/debug_leds_handler.h"
+#include "leds/rgb_led_handler.h"
+#include "util/CMSIS_extra/global_variables_handler.h"
+#include "datalogging/speed.h"
+#include "datalogging/odometer_save.h"
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+ADC_HandleTypeDef hadc1;
+DMA_HandleTypeDef hdma_adc1;
+
+FDCAN_HandleTypeDef hfdcan1;
+FDCAN_HandleTypeDef hfdcan2;
+
+I2C_HandleTypeDef hi2c3;
+
+UART_HandleTypeDef hlpuart1;
+
+SPI_HandleTypeDef hspi1;
+
+TIM_HandleTypeDef htim1;
+TIM_HandleTypeDef htim2;
+
+/* Definitions for t_main_task */
+osThreadId_t t_main_taskHandle;
+const osThreadAttr_t t_main_task_attributes = {
+  .name = "t_main_task",
+  .stack_size = 1024 * 4,
+  .priority = (osPriority_t) osPriorityNormal,
+};
+/* Definitions for t_torque_parameters */
+osThreadId_t t_torque_parametersHandle;
+const osThreadAttr_t t_torque_parameters_attributes = {
+  .name = "t_torque_parameters",
+  .stack_size = 1024 * 4,
+  .priority = (osPriority_t) osPriorityLow,
+};
+/* Definitions for t_datalogger */
+osThreadId_t t_dataloggerHandle;
+const osThreadAttr_t t_datalogger_attributes = {
+  .name = "t_datalogger",
+  .stack_size = 1024 * 4,
+  .priority = (osPriority_t) osPriorityLow,
+};
+/* Definitions for t_APPS_read */
+osThreadId_t t_APPS_readHandle;
+const osThreadAttr_t t_APPS_read_attributes = {
+  .name = "t_APPS_read",
+  .stack_size = 1024 * 4,
+  .priority = (osPriority_t) osPriorityLow,
+};
+/* Definitions for t_steering_read */
+osThreadId_t t_steering_readHandle;
+const osThreadAttr_t t_steering_read_attributes = {
+  .name = "t_steering_read",
+  .stack_size = 1024 * 4,
+  .priority = (osPriority_t) osPriorityLow,
+};
+/* Definitions for t_encoder_speed_calc */
+osThreadId_t t_encoder_speed_calcHandle;
+const osThreadAttr_t t_encoder_speed_calc_attributes = {
+  .name = "t_encoder_speed_calc",
+  .stack_size = 1024 * 4,
+  .priority = (osPriority_t) osPriorityLow,
+};
+/* Definitions for t_odometer_calc */
+osThreadId_t t_odometer_calcHandle;
+const osThreadAttr_t t_odometer_calc_attributes = {
+  .name = "t_odometer_calc",
+  .stack_size = 1024 * 4,
+  .priority = (osPriority_t) osPriorityLow,
+};
+/* Definitions for t_torque_message */
+osThreadId_t t_torque_messageHandle;
+const osThreadAttr_t t_torque_message_attributes = {
+  .name = "t_torque_message",
+  .stack_size = 1024 * 4,
+  .priority = (osPriority_t) osPriorityLow,
+};
+/* Definitions for t_torque_manager */
+osThreadId_t t_torque_managerHandle;
+const osThreadAttr_t t_torque_manager_attributes = {
+  .name = "t_torque_manager",
+  .stack_size = 1024 * 4,
+  .priority = (osPriority_t) osPriorityLow,
+};
+/* Definitions for t_debug_leds */
+osThreadId_t t_debug_ledsHandle;
+const osThreadAttr_t t_debug_leds_attributes = {
+  .name = "t_debug_leds",
+  .stack_size = 1024 * 4,
+  .priority = (osPriority_t) osPriorityLow,
+};
+/* Definitions for t_rgb_led */
+osThreadId_t t_rgb_ledHandle;
+const osThreadAttr_t t_rgb_led_attributes = {
+  .name = "t_rgb_led",
+  .stack_size = 1024 * 4,
+  .priority = (osPriority_t) osPriorityLow,
+};
+/* Definitions for t_seleciona_modo */
+osThreadId_t t_seleciona_modoHandle;
+const osThreadAttr_t t_seleciona_modo_attributes = {
+  .name = "t_seleciona_modo",
+  .stack_size = 1024 * 4,
+  .priority = (osPriority_t) osPriorityLow,
+};
+/* Definitions for t_RTD */
+osThreadId_t t_RTDHandle;
+const osThreadAttr_t t_RTD_attributes = {
+  .name = "t_RTD",
+  .stack_size = 1024 * 4,
+  .priority = (osPriority_t) osPriorityLow,
+};
+/* Definitions for t_throttle_control */
+osThreadId_t t_throttle_controlHandle;
+const osThreadAttr_t t_throttle_control_attributes = {
+  .name = "t_throttle_control",
+  .stack_size = 1024 * 4,
+  .priority = (osPriority_t) osPriorityLow,
+};
+/* Definitions for t_datalog_acquisition */
+osThreadId_t t_datalog_acquisitionHandle;
+const osThreadAttr_t t_datalog_acquisition_attributes = {
+  .name = "t_datalog_acquisition",
+  .stack_size = 1024 * 4,
+  .priority = (osPriority_t) osPriorityLow,
+};
+/* Definitions for t_inverter_comm_error */
+osThreadId_t t_inverter_comm_errorHandle;
+const osThreadAttr_t t_inverter_comm_error_attributes = {
+  .name = "t_inverter_comm_error",
+  .stack_size = 1024 * 4,
+  .priority = (osPriority_t) osPriorityLow,
+};
+/* Definitions for t_inverter_datalog */
+osThreadId_t t_inverter_datalogHandle;
+const osThreadAttr_t t_inverter_datalog_attributes = {
+  .name = "t_inverter_datalog",
+  .stack_size = 1024 * 4,
+  .priority = (osPriority_t) osPriorityLow,
+};
+/* Definitions for t_pilot_reset */
+osThreadId_t t_pilot_resetHandle;
+const osThreadAttr_t t_pilot_reset_attributes = {
+  .name = "t_pilot_reset",
+  .stack_size = 1024 * 4,
+  .priority = (osPriority_t) osPriorityLow,
+};
+/* Definitions for t_buttons_handler */
+osThreadId_t t_buttons_handlerHandle;
+const osThreadAttr_t t_buttons_handler_attributes = {
+  .name = "t_buttons_handler",
+  .stack_size = 1024 * 4,
+  .priority = (osPriority_t) osPriorityLow,
+};
+/* Definitions for t_speed_datalog */
+osThreadId_t t_speed_datalogHandle;
+const osThreadAttr_t t_speed_datalog_attributes = {
+  .name = "t_speed_datalog",
+  .stack_size = 1024 * 4,
+  .priority = (osPriority_t) osPriorityLow,
+};
+/* Definitions for t_odometer_save */
+osThreadId_t t_odometer_saveHandle;
+const osThreadAttr_t t_odometer_save_attributes = {
+  .name = "t_odometer_save",
+  .stack_size = 1024 * 4,
+  .priority = (osPriority_t) osPriorityLow,
+};
+/* Definitions for t_dynamic_controls_choice */
+osThreadId_t t_dynamic_controls_choiceHandle;
+const osThreadAttr_t t_dynamic_controls_choice_attributes = {
+  .name = "t_dynamic_controls_choice",
+  .stack_size = 1024 * 4,
+  .priority = (osPriority_t) osPriorityLow,
+};
+/* Definitions for t_cross_validation */
+osThreadId_t t_cross_validationHandle;
+const osThreadAttr_t t_cross_validation_attributes = {
+  .name = "t_cross_validation",
+  .stack_size = 1024 * 4,
+  .priority = (osPriority_t) osPriorityLow,
+};
+/* Definitions for q_encoder_int_message */
+osMessageQueueId_t q_encoder_int_messageHandle;
+const osMessageQueueAttr_t q_encoder_int_message_attributes = {
+  .name = "q_encoder_int_message"
+};
+/* Definitions for q_torque_message */
+osMessageQueueId_t q_torque_messageHandle;
+const osMessageQueueAttr_t q_torque_message_attributes = {
+  .name = "q_torque_message"
+};
+/* Definitions for q_ref_torque_message */
+osMessageQueueId_t q_ref_torque_messageHandle;
+const osMessageQueueAttr_t q_ref_torque_message_attributes = {
+  .name = "q_ref_torque_message"
+};
+/* Definitions for q_datalog_message */
+osMessageQueueId_t q_datalog_messageHandle;
+const osMessageQueueAttr_t q_datalog_message_attributes = {
+  .name = "q_datalog_message"
+};
+/* Definitions for q_debug_leds_message */
+osMessageQueueId_t q_debug_leds_messageHandle;
+const osMessageQueueAttr_t q_debug_leds_message_attributes = {
+  .name = "q_debug_leds_message"
+};
+/* Definitions for q_rgb_led_message */
+osMessageQueueId_t q_rgb_led_messageHandle;
+const osMessageQueueAttr_t q_rgb_led_message_attributes = {
+  .name = "q_rgb_led_message"
+};
+/* Definitions for q_throttle_control */
+osMessageQueueId_t q_throttle_controlHandle;
+const osMessageQueueAttr_t q_throttle_control_attributes = {
+  .name = "q_throttle_control"
+};
+/* Definitions for q_encoder_speeds_message */
+osMessageQueueId_t q_encoder_speeds_messageHandle;
+const osMessageQueueAttr_t q_encoder_speeds_message_attributes = {
+  .name = "q_encoder_speeds_message"
+};
+/* Definitions for q_odometer_calc_save_message */
+osMessageQueueId_t q_odometer_calc_save_messageHandle;
+const osMessageQueueAttr_t q_odometer_calc_save_message_attributes = {
+  .name = "q_odometer_calc_save_message"
+};
+/* Definitions for q_ids_can_inverter */
+osMessageQueueId_t q_ids_can_inverterHandle;
+const osMessageQueueAttr_t q_ids_can_inverter_attributes = {
+  .name = "q_ids_can_inverter"
+};
+/* Definitions for tim_SU_F_error */
+osTimerId_t tim_SU_F_errorHandle;
+const osTimerAttr_t tim_SU_F_error_attributes = {
+  .name = "tim_SU_F_error"
+};
+/* Definitions for tim_APPS_error */
+osTimerId_t tim_APPS_errorHandle;
+const osTimerAttr_t tim_APPS_error_attributes = {
+  .name = "tim_APPS_error"
+};
+/* Definitions for tim_inverter_BUS_OFF_error */
+osTimerId_t tim_inverter_BUS_OFF_errorHandle;
+const osTimerAttr_t tim_inverter_BUS_OFF_error_attributes = {
+  .name = "tim_inverter_BUS_OFF_error"
+};
+/* Definitions for tim_inverter_ready */
+osTimerId_t tim_inverter_readyHandle;
+const osTimerAttr_t tim_inverter_ready_attributes = {
+  .name = "tim_inverter_ready"
+};
+/* Definitions for tim_inverter_can_transmit_error */
+osTimerId_t tim_inverter_can_transmit_errorHandle;
+const osTimerAttr_t tim_inverter_can_transmit_error_attributes = {
+  .name = "tim_inverter_can_transmit_error"
+};
+/* Definitions for tim_left_inv_error */
+osTimerId_t tim_left_inv_errorHandle;
+const osTimerAttr_t tim_left_inv_error_attributes = {
+  .name = "tim_left_inv_error"
+};
+/* Definitions for tim_right_inv_error */
+osTimerId_t tim_right_inv_errorHandle;
+const osTimerAttr_t tim_right_inv_error_attributes = {
+  .name = "tim_right_inv_error"
+};
+/* Definitions for m_state_parameter_mutex */
+osMutexId_t m_state_parameter_mutexHandle;
+const osMutexAttr_t m_state_parameter_mutex_attributes = {
+  .name = "m_state_parameter_mutex"
+};
+/* Definitions for e_ECU_control_flags */
+osEventFlagsId_t e_ECU_control_flagsHandle;
+const osEventFlagsAttr_t e_ECU_control_flags_attributes = {
+  .name = "e_ECU_control_flags"
+};
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_DMA_Init(void);
+static void MX_ADC1_Init(void);
+static void MX_FDCAN1_Init(void);
+static void MX_FDCAN2_Init(void);
+static void MX_LPUART1_UART_Init(void);
+static void MX_SPI1_Init(void);
+static void MX_TIM1_Init(void);
+static void MX_I2C3_Init(void);
+static void MX_TIM2_Init(void);
+void main_task(void *argument);
+extern void torque_parameters(void *argument);
+extern void datalogger(void *argument);
+extern void APPS_read(void *argument);
+extern void steering_read(void *argument);
+extern void encoder_speed_calc(void *argument);
+extern void odometer_calc(void *argument);
+extern void torque_message(void *argument);
+extern void torque_manager(void *argument);
+extern void debug_leds(void *argument);
+extern void rgb_led(void *argument);
+extern void seleciona_modo(void *argument);
+extern void RTD(void *argument);
+extern void throttle_control(void *argument);
+extern void datalog_acquisition(void *argument);
+extern void inverter_comm_error(void *argument);
+extern void inverter_datalog(void *argument);
+extern void pilot_reset(void *argument);
+extern void buttons_handler(void *argument);
+extern void speed_datalog(void *argument);
+extern void odometer_save(void *argument);
+extern void dynamic_controls_choice(void *argument);
+extern void cross_validation(void *argument);
+extern void errors_with_timer_callback(void *argument);
+extern void inverter_BUS_OFF_error_callback(void *argument);
+extern void inverter_ready_callback(void *argument);
+extern void left_inv_error_callback(void *argument);
+extern void right_inv_error_callback(void *argument);
+
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+//  init_NVIC_priorities();
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  MX_DMA_Init();
+  MX_ADC1_Init();
+  MX_FDCAN1_Init();
+  MX_FDCAN2_Init();
+  MX_LPUART1_UART_Init();
+  MX_SPI1_Init();
+  MX_TIM1_Init();
+  MX_I2C3_Init();
+  MX_TIM2_Init();
+  /* USER CODE BEGIN 2 */
+  init_ECU();
+  /* USER CODE END 2 */
+
+  /* Init scheduler */
+  osKernelInitialize();
+  /* Create the mutex(es) */
+  /* creation of m_state_parameter_mutex */
+  m_state_parameter_mutexHandle = osMutexNew(&m_state_parameter_mutex_attributes);
+
+  /* USER CODE BEGIN RTOS_MUTEX */
+  /* add mutexes, ... */
+  /* USER CODE END RTOS_MUTEX */
+
+  /* USER CODE BEGIN RTOS_SEMAPHORES */
+  /* add semaphores, ... */
+  /* USER CODE END RTOS_SEMAPHORES */
+
+  /* Create the timer(s) */
+  /* creation of tim_SU_F_error */
+  tim_SU_F_errorHandle = osTimerNew(errors_with_timer_callback, osTimerOnce, (void*) SU_F_ERROR_FLAG, &tim_SU_F_error_attributes);
+
+  /* creation of tim_APPS_error */
+  tim_APPS_errorHandle = osTimerNew(errors_with_timer_callback, osTimerOnce, (void*) APPS_ERROR_FLAG, &tim_APPS_error_attributes);
+
+  /* creation of tim_inverter_BUS_OFF_error */
+  tim_inverter_BUS_OFF_errorHandle = osTimerNew(inverter_BUS_OFF_error_callback, osTimerOnce, NULL, &tim_inverter_BUS_OFF_error_attributes);
+
+  /* creation of tim_inverter_ready */
+  tim_inverter_readyHandle = osTimerNew(inverter_ready_callback, osTimerOnce, NULL, &tim_inverter_ready_attributes);
+
+  /* creation of tim_inverter_can_transmit_error */
+  tim_inverter_can_transmit_errorHandle = osTimerNew(errors_with_timer_callback, osTimerOnce, (void*) INVERTER_CAN_TRANSMIT_ERROR_FLAG, &tim_inverter_can_transmit_error_attributes);
+
+  /* creation of tim_left_inv_error */
+  tim_left_inv_errorHandle = osTimerNew(left_inv_error_callback, osTimerPeriodic, (void*) LEFT_INVERTER_COMM_ERROR_FLAG, &tim_left_inv_error_attributes);
+
+  /* creation of tim_right_inv_error */
+  tim_right_inv_errorHandle = osTimerNew(right_inv_error_callback, osTimerPeriodic, (void*) RIGHT_INVERTER_COMM_ERROR_FLAG, &tim_right_inv_error_attributes);
+
+  /* USER CODE BEGIN RTOS_TIMERS */
+  /* start timers, add new ones, ... */
+  /* USER CODE END RTOS_TIMERS */
+
+  /* Create the queue(s) */
+  /* creation of q_encoder_int_message */
+  q_encoder_int_messageHandle = osMessageQueueNew (16, sizeof(encoder_int_message_t), &q_encoder_int_message_attributes);
+
+  /* creation of q_torque_message */
+  q_torque_messageHandle = osMessageQueueNew (16, sizeof(torque_message_t), &q_torque_message_attributes);
+
+  /* creation of q_ref_torque_message */
+  q_ref_torque_messageHandle = osMessageQueueNew (16, sizeof(ref_torque_t), &q_ref_torque_message_attributes);
+
+  /* creation of q_datalog_message */
+  q_datalog_messageHandle = osMessageQueueNew (128, sizeof(datalog_message_t), &q_datalog_message_attributes);
+
+  /* creation of q_debug_leds_message */
+  q_debug_leds_messageHandle = osMessageQueueNew (16, sizeof(debug_led_message_t), &q_debug_leds_message_attributes);
+
+  /* creation of q_rgb_led_message */
+  q_rgb_led_messageHandle = osMessageQueueNew (16, sizeof(rgb_led_message_t), &q_rgb_led_message_attributes);
+
+  /* creation of q_throttle_control */
+  q_throttle_controlHandle = osMessageQueueNew (16, sizeof(uint16_t), &q_throttle_control_attributes);
+
+  /* creation of q_encoder_speeds_message */
+  q_encoder_speeds_messageHandle = osMessageQueueNew (1, sizeof(encoder_speeds_message_t), &q_encoder_speeds_message_attributes);
+
+  /* creation of q_odometer_calc_save_message */
+  q_odometer_calc_save_messageHandle = osMessageQueueNew (1, sizeof(odometer_message_t), &q_odometer_calc_save_message_attributes);
+
+  /* creation of q_ids_can_inverter */
+  q_ids_can_inverterHandle = osMessageQueueNew (32, sizeof(uint32_t), &q_ids_can_inverter_attributes);
+
+  /* USER CODE BEGIN RTOS_QUEUES */
+  /* add queues, ... */
+  /* USER CODE END RTOS_QUEUES */
+
+  /* Create the thread(s) */
+  /* creation of t_main_task */
+  t_main_taskHandle = osThreadNew(main_task, NULL, &t_main_task_attributes);
+
+  /* creation of t_torque_parameters */
+  t_torque_parametersHandle = osThreadNew(torque_parameters, NULL, &t_torque_parameters_attributes);
+
+  /* creation of t_datalogger */
+  t_dataloggerHandle = osThreadNew(datalogger, NULL, &t_datalogger_attributes);
+
+  /* creation of t_APPS_read */
+  t_APPS_readHandle = osThreadNew(APPS_read, NULL, &t_APPS_read_attributes);
+
+  /* creation of t_steering_read */
+  t_steering_readHandle = osThreadNew(steering_read, NULL, &t_steering_read_attributes);
+
+  /* creation of t_encoder_speed_calc */
+  t_encoder_speed_calcHandle = osThreadNew(encoder_speed_calc, NULL, &t_encoder_speed_calc_attributes);
+
+  /* creation of t_odometer_calc */
+  t_odometer_calcHandle = osThreadNew(odometer_calc, NULL, &t_odometer_calc_attributes);
+
+  /* creation of t_torque_message */
+  t_torque_messageHandle = osThreadNew(torque_message, NULL, &t_torque_message_attributes);
+
+  /* creation of t_torque_manager */
+  t_torque_managerHandle = osThreadNew(torque_manager, NULL, &t_torque_manager_attributes);
+
+  /* creation of t_debug_leds */
+  t_debug_ledsHandle = osThreadNew(debug_leds, NULL, &t_debug_leds_attributes);
+
+  /* creation of t_rgb_led */
+  t_rgb_ledHandle = osThreadNew(rgb_led, NULL, &t_rgb_led_attributes);
+
+  /* creation of t_seleciona_modo */
+  t_seleciona_modoHandle = osThreadNew(seleciona_modo, NULL, &t_seleciona_modo_attributes);
+
+  /* creation of t_RTD */
+  t_RTDHandle = osThreadNew(RTD, NULL, &t_RTD_attributes);
+
+  /* creation of t_throttle_control */
+  t_throttle_controlHandle = osThreadNew(throttle_control, NULL, &t_throttle_control_attributes);
+
+  /* creation of t_datalog_acquisition */
+  t_datalog_acquisitionHandle = osThreadNew(datalog_acquisition, NULL, &t_datalog_acquisition_attributes);
+
+  /* creation of t_inverter_comm_error */
+  t_inverter_comm_errorHandle = osThreadNew(inverter_comm_error, NULL, &t_inverter_comm_error_attributes);
+
+  /* creation of t_inverter_datalog */
+  t_inverter_datalogHandle = osThreadNew(inverter_datalog, NULL, &t_inverter_datalog_attributes);
+
+  /* creation of t_pilot_reset */
+  t_pilot_resetHandle = osThreadNew(pilot_reset, NULL, &t_pilot_reset_attributes);
+
+  /* creation of t_buttons_handler */
+  t_buttons_handlerHandle = osThreadNew(buttons_handler, NULL, &t_buttons_handler_attributes);
+
+  /* creation of t_speed_datalog */
+  t_speed_datalogHandle = osThreadNew(speed_datalog, NULL, &t_speed_datalog_attributes);
+
+  /* creation of t_odometer_save */
+  t_odometer_saveHandle = osThreadNew(odometer_save, NULL, &t_odometer_save_attributes);
+
+  /* creation of t_dynamic_controls_choice */
+  t_dynamic_controls_choiceHandle = osThreadNew(dynamic_controls_choice, NULL, &t_dynamic_controls_choice_attributes);
+
+  /* creation of t_cross_validation */
+  t_cross_validationHandle = osThreadNew(cross_validation, NULL, &t_cross_validation_attributes);
+
+  /* USER CODE BEGIN RTOS_THREADS */
+  /* add threads, ... */
+  /* USER CODE END RTOS_THREADS */
+
+  /* creation of e_ECU_control_flags */
+  e_ECU_control_flagsHandle = osEventFlagsNew(&e_ECU_control_flags_attributes);
+
+  /* USER CODE BEGIN RTOS_EVENTS */
+  /* add events, ... */
+  /* USER CODE END RTOS_EVENTS */
+
+  /* Start scheduler */
+  osKernelStart();
+
+  /* We should never get here as control is now taken by the scheduler */
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  /** Supply configuration update enable
+  */
+  HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
+
+  /** Configure the main internal regulator output voltage
+  */
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3);
+
+  while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
+
+  /** Macro to configure the PLL clock source
+  */
+  __HAL_RCC_PLL_PLLSOURCE_CONFIG(RCC_PLLSOURCE_HSE);
+
+  /** Initializes the RCC Oscillators according to the specified parameters
+  * in the RCC_OscInitTypeDef structure.
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+  RCC_OscInitStruct.PLL.PLLM = 1;
+  RCC_OscInitStruct.PLL.PLLN = 50;
+  RCC_OscInitStruct.PLL.PLLP = 2;
+  RCC_OscInitStruct.PLL.PLLQ = 4;
+  RCC_OscInitStruct.PLL.PLLR = 2;
+  RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_3;
+  RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
+  RCC_OscInitStruct.PLL.PLLFRACN = 0;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /** Initializes the CPU, AHB and APB buses clocks
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2
+                              |RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
+  RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV1;
+  RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
+  {
+    Error_Handler();
+  }
+}
+
+/**
+  * @brief ADC1 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_ADC1_Init(void)
+{
+
+  /* USER CODE BEGIN ADC1_Init 0 */
+
+  /* USER CODE END ADC1_Init 0 */
+
+  ADC_MultiModeTypeDef multimode = {0};
+  ADC_ChannelConfTypeDef sConfig = {0};
+
+  /* USER CODE BEGIN ADC1_Init 1 */
+
+  /* USER CODE END ADC1_Init 1 */
+
+  /** Common config
+  */
+  hadc1.Instance = ADC1;
+  hadc1.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV2;
+  hadc1.Init.Resolution = ADC_RESOLUTION_12B_OPT;
+  hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE;
+  hadc1.Init.EOCSelection = ADC_EOC_SEQ_CONV;
+  hadc1.Init.LowPowerAutoWait = DISABLE;
+  hadc1.Init.ContinuousConvMode = ENABLE;
+  hadc1.Init.NbrOfConversion = 6;
+  hadc1.Init.DiscontinuousConvMode = DISABLE;
+  hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
+  hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
+  hadc1.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DMA_CIRCULAR;
+  hadc1.Init.Overrun = ADC_OVR_DATA_OVERWRITTEN;
+  hadc1.Init.LeftBitShift = ADC_LEFTBITSHIFT_NONE;
+  hadc1.Init.OversamplingMode = DISABLE;
+  if (HAL_ADC_Init(&hadc1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /** Configure the ADC multi-mode
+  */
+  multimode.Mode = ADC_MODE_INDEPENDENT;
+  if (HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /** Configure Regular Channel
+  */
+  sConfig.Channel = ADC_CHANNEL_3;
+  sConfig.Rank = ADC_REGULAR_RANK_1;
+  sConfig.SamplingTime = ADC_SAMPLETIME_810CYCLES_5;
+  sConfig.SingleDiff = ADC_SINGLE_ENDED;
+  sConfig.OffsetNumber = ADC_OFFSET_NONE;
+  sConfig.Offset = 0;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /** Configure Regular Channel
+  */
+  sConfig.Channel = ADC_CHANNEL_4;
+  sConfig.Rank = ADC_REGULAR_RANK_2;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /** Configure Regular Channel
+  */
+  sConfig.Channel = ADC_CHANNEL_5;
+  sConfig.Rank = ADC_REGULAR_RANK_3;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /** Configure Regular Channel
+  */
+  sConfig.Channel = ADC_CHANNEL_7;
+  sConfig.Rank = ADC_REGULAR_RANK_4;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /** Configure Regular Channel
+  */
+  sConfig.Channel = ADC_CHANNEL_8;
+  sConfig.Rank = ADC_REGULAR_RANK_5;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /** Configure Regular Channel
+  */
+  sConfig.Channel = ADC_CHANNEL_19;
+  sConfig.Rank = ADC_REGULAR_RANK_6;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN ADC1_Init 2 */
+
+  /* USER CODE END ADC1_Init 2 */
+
+}
+
+/**
+  * @brief FDCAN1 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_FDCAN1_Init(void)
+{
+
+  /* USER CODE BEGIN FDCAN1_Init 0 */
+
+  /* USER CODE END FDCAN1_Init 0 */
+
+  /* USER CODE BEGIN FDCAN1_Init 1 */
+
+  /* USER CODE END FDCAN1_Init 1 */
+  hfdcan1.Instance = FDCAN1;
+  hfdcan1.Init.FrameFormat = FDCAN_FRAME_CLASSIC;
+  hfdcan1.Init.Mode = FDCAN_MODE_NORMAL;
+  hfdcan1.Init.AutoRetransmission = DISABLE;
+  hfdcan1.Init.TransmitPause = DISABLE;
+  hfdcan1.Init.ProtocolException = DISABLE;
+  hfdcan1.Init.NominalPrescaler = 5;
+  hfdcan1.Init.NominalSyncJumpWidth = 4;
+  hfdcan1.Init.NominalTimeSeg1 = 27;
+  hfdcan1.Init.NominalTimeSeg2 = 4;
+  hfdcan1.Init.DataPrescaler = 5;
+  hfdcan1.Init.DataSyncJumpWidth = 4;
+  hfdcan1.Init.DataTimeSeg1 = 27;
+  hfdcan1.Init.DataTimeSeg2 = 4;
+  hfdcan1.Init.MessageRAMOffset = 0;
+  hfdcan1.Init.StdFiltersNbr = 0;
+  hfdcan1.Init.ExtFiltersNbr = 0;
+  hfdcan1.Init.RxFifo0ElmtsNbr = 32;
+  hfdcan1.Init.RxFifo0ElmtSize = FDCAN_DATA_BYTES_8;
+  hfdcan1.Init.RxFifo1ElmtsNbr = 32;
+  hfdcan1.Init.RxFifo1ElmtSize = FDCAN_DATA_BYTES_8;
+  hfdcan1.Init.RxBuffersNbr = 32;
+  hfdcan1.Init.RxBufferSize = FDCAN_DATA_BYTES_8;
+  hfdcan1.Init.TxEventsNbr = 32;
+  hfdcan1.Init.TxBuffersNbr = 32;
+  hfdcan1.Init.TxFifoQueueElmtsNbr = 32;
+  hfdcan1.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION;
+  hfdcan1.Init.TxElmtSize = FDCAN_DATA_BYTES_8;
+  if (HAL_FDCAN_Init(&hfdcan1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN FDCAN1_Init 2 */
+
+  /* USER CODE END FDCAN1_Init 2 */
+
+}
+
+/**
+  * @brief FDCAN2 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_FDCAN2_Init(void)
+{
+
+  /* USER CODE BEGIN FDCAN2_Init 0 */
+
+  /* USER CODE END FDCAN2_Init 0 */
+
+  /* USER CODE BEGIN FDCAN2_Init 1 */
+
+  /* USER CODE END FDCAN2_Init 1 */
+  hfdcan2.Instance = FDCAN2;
+  hfdcan2.Init.FrameFormat = FDCAN_FRAME_CLASSIC;
+  hfdcan2.Init.Mode = FDCAN_MODE_NORMAL;
+  hfdcan2.Init.AutoRetransmission = DISABLE;
+  hfdcan2.Init.TransmitPause = DISABLE;
+  hfdcan2.Init.ProtocolException = DISABLE;
+  hfdcan2.Init.NominalPrescaler = 1;
+  hfdcan2.Init.NominalSyncJumpWidth = 2;
+  hfdcan2.Init.NominalTimeSeg1 = 13;
+  hfdcan2.Init.NominalTimeSeg2 = 2;
+  hfdcan2.Init.DataPrescaler = 1;
+  hfdcan2.Init.DataSyncJumpWidth = 2;
+  hfdcan2.Init.DataTimeSeg1 = 13;
+  hfdcan2.Init.DataTimeSeg2 = 2;
+  hfdcan2.Init.MessageRAMOffset = 1280;
+  hfdcan2.Init.StdFiltersNbr = 0;
+  hfdcan2.Init.ExtFiltersNbr = 0;
+  hfdcan2.Init.RxFifo0ElmtsNbr = 32;
+  hfdcan2.Init.RxFifo0ElmtSize = FDCAN_DATA_BYTES_8;
+  hfdcan2.Init.RxFifo1ElmtsNbr = 32;
+  hfdcan2.Init.RxFifo1ElmtSize = FDCAN_DATA_BYTES_8;
+  hfdcan2.Init.RxBuffersNbr = 32;
+  hfdcan2.Init.RxBufferSize = FDCAN_DATA_BYTES_8;
+  hfdcan2.Init.TxEventsNbr = 32;
+  hfdcan2.Init.TxBuffersNbr = 32;
+  hfdcan2.Init.TxFifoQueueElmtsNbr = 32;
+  hfdcan2.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION;
+  hfdcan2.Init.TxElmtSize = FDCAN_DATA_BYTES_8;
+  if (HAL_FDCAN_Init(&hfdcan2) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN FDCAN2_Init 2 */
+
+  /* USER CODE END FDCAN2_Init 2 */
+
+}
+
+/**
+  * @brief I2C3 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_I2C3_Init(void)
+{
+
+  /* USER CODE BEGIN I2C3_Init 0 */
+
+  /* USER CODE END I2C3_Init 0 */
+
+  /* USER CODE BEGIN I2C3_Init 1 */
+
+  /* USER CODE END I2C3_Init 1 */
+  hi2c3.Instance = I2C3;
+  hi2c3.Init.Timing = 0x00C0EAFF;
+  hi2c3.Init.OwnAddress1 = 0;
+  hi2c3.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
+  hi2c3.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
+  hi2c3.Init.OwnAddress2 = 0;
+  hi2c3.Init.OwnAddress2Masks = I2C_OA2_NOMASK;
+  hi2c3.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
+  hi2c3.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
+  if (HAL_I2C_Init(&hi2c3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /** Configure Analogue filter
+  */
+  if (HAL_I2CEx_ConfigAnalogFilter(&hi2c3, I2C_ANALOGFILTER_ENABLE) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /** Configure Digital filter
+  */
+  if (HAL_I2CEx_ConfigDigitalFilter(&hi2c3, 0) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN I2C3_Init 2 */
+
+  /* USER CODE END I2C3_Init 2 */
+
+}
+
+/**
+  * @brief LPUART1 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_LPUART1_UART_Init(void)
+{
+
+  /* USER CODE BEGIN LPUART1_Init 0 */
+
+  /* USER CODE END LPUART1_Init 0 */
+
+  /* USER CODE BEGIN LPUART1_Init 1 */
+
+  /* USER CODE END LPUART1_Init 1 */
+  hlpuart1.Instance = LPUART1;
+  hlpuart1.Init.BaudRate = 209700;
+  hlpuart1.Init.WordLength = UART_WORDLENGTH_8B;
+  hlpuart1.Init.StopBits = UART_STOPBITS_1;
+  hlpuart1.Init.Parity = UART_PARITY_NONE;
+  hlpuart1.Init.Mode = UART_MODE_TX_RX;
+  hlpuart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+  hlpuart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
+  hlpuart1.Init.ClockPrescaler = UART_PRESCALER_DIV1;
+  hlpuart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
+  hlpuart1.FifoMode = UART_FIFOMODE_DISABLE;
+  if (HAL_UART_Init(&hlpuart1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_SetTxFifoThreshold(&hlpuart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_SetRxFifoThreshold(&hlpuart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_DisableFifoMode(&hlpuart1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN LPUART1_Init 2 */
+
+  /* USER CODE END LPUART1_Init 2 */
+
+}
+
+/**
+  * @brief SPI1 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_SPI1_Init(void)
+{
+
+  /* USER CODE BEGIN SPI1_Init 0 */
+
+  /* USER CODE END SPI1_Init 0 */
+
+  /* USER CODE BEGIN SPI1_Init 1 */
+
+  /* USER CODE END SPI1_Init 1 */
+  /* SPI1 parameter configuration*/
+  hspi1.Instance = SPI1;
+  hspi1.Init.Mode = SPI_MODE_MASTER;
+  hspi1.Init.Direction = SPI_DIRECTION_2LINES;
+  hspi1.Init.DataSize = SPI_DATASIZE_4BIT;
+  hspi1.Init.CLKPolarity = SPI_POLARITY_LOW;
+  hspi1.Init.CLKPhase = SPI_PHASE_1EDGE;
+  hspi1.Init.NSS = SPI_NSS_SOFT;
+  hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_256;
+  hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB;
+  hspi1.Init.TIMode = SPI_TIMODE_DISABLE;
+  hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
+  hspi1.Init.CRCPolynomial = 0x0;
+  hspi1.Init.NSSPMode = SPI_NSS_PULSE_ENABLE;
+  hspi1.Init.NSSPolarity = SPI_NSS_POLARITY_LOW;
+  hspi1.Init.FifoThreshold = SPI_FIFO_THRESHOLD_01DATA;
+  hspi1.Init.TxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN;
+  hspi1.Init.RxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN;
+  hspi1.Init.MasterSSIdleness = SPI_MASTER_SS_IDLENESS_00CYCLE;
+  hspi1.Init.MasterInterDataIdleness = SPI_MASTER_INTERDATA_IDLENESS_00CYCLE;
+  hspi1.Init.MasterReceiverAutoSusp = SPI_MASTER_RX_AUTOSUSP_DISABLE;
+  hspi1.Init.MasterKeepIOState = SPI_MASTER_KEEP_IO_STATE_DISABLE;
+  hspi1.Init.IOSwap = SPI_IO_SWAP_DISABLE;
+  if (HAL_SPI_Init(&hspi1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN SPI1_Init 2 */
+
+  /* USER CODE END SPI1_Init 2 */
+
+}
+
+/**
+  * @brief TIM1 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_TIM1_Init(void)
+{
+
+  /* USER CODE BEGIN TIM1_Init 0 */
+
+  /* USER CODE END TIM1_Init 0 */
+
+  TIM_ClockConfigTypeDef sClockSourceConfig = {0};
+  TIM_MasterConfigTypeDef sMasterConfig = {0};
+
+  /* USER CODE BEGIN TIM1_Init 1 */
+
+  /* USER CODE END TIM1_Init 1 */
+  htim1.Instance = TIM1;
+  htim1.Init.Prescaler = 1799;
+  htim1.Init.CounterMode = TIM_COUNTERMODE_UP;
+  htim1.Init.Period = 4000;
+  htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
+  htim1.Init.RepetitionCounter = 0;
+  htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+  if (HAL_TIM_Base_Init(&htim1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
+  if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
+  sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET;
+  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
+  if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN TIM1_Init 2 */
+
+  /* USER CODE END TIM1_Init 2 */
+
+}
+
+/**
+  * @brief TIM2 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_TIM2_Init(void)
+{
+
+  /* USER CODE BEGIN TIM2_Init 0 */
+
+  /* USER CODE END TIM2_Init 0 */
+
+  TIM_ClockConfigTypeDef sClockSourceConfig = {0};
+  TIM_MasterConfigTypeDef sMasterConfig = {0};
+
+  /* USER CODE BEGIN TIM2_Init 1 */
+
+  /* USER CODE END TIM2_Init 1 */
+  htim2.Instance = TIM2;
+  htim2.Init.Prescaler = 0;
+  htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
+  htim2.Init.Period = 0xFFFFFFFF;
+  htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
+  htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+  if (HAL_TIM_Base_Init(&htim2) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
+  if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
+  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
+  if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN TIM2_Init 2 */
+
+  /* USER CODE END TIM2_Init 2 */
+
+}
+
+/**
+  * Enable DMA controller clock
+  */
+static void MX_DMA_Init(void)
+{
+
+  /* DMA controller clock enable */
+  __HAL_RCC_DMA1_CLK_ENABLE();
+
+  /* DMA interrupt init */
+  /* DMA1_Stream0_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA1_Stream0_IRQn, 5, 0);
+  HAL_NVIC_EnableIRQ(DMA1_Stream0_IRQn);
+
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+  /* GPIO Ports Clock Enable */
+  __HAL_RCC_GPIOE_CLK_ENABLE();
+  __HAL_RCC_GPIOH_CLK_ENABLE();
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  __HAL_RCC_GPIOC_CLK_ENABLE();
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+  __HAL_RCC_GPIOD_CLK_ENABLE();
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(GPIOE, C_LED_DEBUG1_Pin|C_LED_DEBUG3_Pin, GPIO_PIN_SET);
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(C_LED_DEBUG2_GPIO_Port, C_LED_DEBUG2_Pin, GPIO_PIN_RESET);
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(GPIOD, C_LED_BLUE_Pin|C_LED_GREEN_Pin|C_LED_RED_Pin, GPIO_PIN_RESET);
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(C_RTDS_GPIO_Port, C_RTDS_Pin, GPIO_PIN_RESET);
+
+  /*Configure GPIO pins : C_LED_DEBUG1_Pin C_LED_DEBUG2_Pin C_LED_DEBUG3_Pin */
+  GPIO_InitStruct.Pin = C_LED_DEBUG1_Pin|C_LED_DEBUG2_Pin|C_LED_DEBUG3_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
+
+  /*Configure GPIO pins : S_VEL1_Pin S_VEL2_Pin S_VEL3_Pin S_VEL4_Pin */
+  GPIO_InitStruct.Pin = S_VEL1_Pin|S_VEL2_Pin|S_VEL3_Pin|S_VEL4_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
+
+  /*Configure GPIO pins : C_LED_BLUE_Pin C_LED_GREEN_Pin C_LED_RED_Pin */
+  GPIO_InitStruct.Pin = C_LED_BLUE_Pin|C_LED_GREEN_Pin|C_LED_RED_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+
+  /*Configure GPIO pins : B_DYNAMICS_CONTROLS_Pin B_MODE_Pin B_RTD_Pin */
+  GPIO_InitStruct.Pin = B_DYNAMICS_CONTROLS_Pin|B_MODE_Pin|B_RTD_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+
+  /*Configure GPIO pin : C_RTDS_Pin */
+  GPIO_InitStruct.Pin = C_RTDS_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(C_RTDS_GPIO_Port, &GPIO_InitStruct);
+
+  /*Configure GPIO pin : BOOT1_Pin */
+  GPIO_InitStruct.Pin = BOOT1_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  HAL_GPIO_Init(BOOT1_GPIO_Port, &GPIO_InitStruct);
+
+  /* EXTI interrupt init*/
+  HAL_NVIC_SetPriority(EXTI15_10_IRQn, 5, 0);
+  HAL_NVIC_EnableIRQ(EXTI15_10_IRQn);
+
+}
+
+/* USER CODE BEGIN 4 */
+
+/* USER CODE END 4 */
+
+/* USER CODE BEGIN Header_main_task */
+/**
+  * @brief  Function implementing the t_main_task thread.
+  * @param  argument: Not used
+  * @retval None
+  */
+/* USER CODE END Header_main_task */
+__weak void main_task(void *argument)
+{
+  /* USER CODE BEGIN 5 */
+  /* Infinite loop */
+  for(;;)
+  {
+    osDelay(1);
+  }
+  /* USER CODE END 5 */
+}
+
+/**
+  * @brief  Period elapsed callback in non blocking mode
+  * @note   This function is called  when TIM3 interrupt took place, inside
+  * HAL_TIM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment
+  * a global variable "uwTick" used as application time base.
+  * @param  htim : TIM handle
+  * @retval None
+  */
+void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
+{
+  /* USER CODE BEGIN Callback 0 */
+
+  /* USER CODE END Callback 0 */
+  if (htim->Instance == TIM3) {
+    HAL_IncTick();
+  }
+  /* USER CODE BEGIN Callback 1 */
+
+  /* USER CODE END Callback 1 */
+}
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
diff --git a/Core/Src/sensors/sensor_data_processing.c b/Core/Src/sensors/sensor_data_processing.c
index 39cf0253..7b30f33e 100644
--- a/Core/Src/sensors/sensor_data_processing.c
+++ b/Core/Src/sensors/sensor_data_processing.c
@@ -9,7 +9,7 @@
 
 
 
-// Calculate moving average for data logged from any sensor
+// Calculate moving average for data logged from any sensor using a circular buffer
 
 void moving_average(uint16_t* mov_ave, uint16_t data) {
 
@@ -19,28 +19,42 @@ void moving_average(uint16_t* mov_ave, uint16_t data) {
 
 	mov_ave = 0;
 
-	// Circular buffer for calculating the moving average of a signal
+	// Put the signal value read by sensor into each buffer position
+	movave_buffer[buffer_index] = data;// Put the signal value read by sensor into each buffer position
+	movave_buffer[buffer_index] = data;
 
-	for(;;){
-		// Put the signal value read by sensor into each buffer position
-		movave_buffer[buffer_index] = data;
+	// circular buffer logic
+	buffer_index = (buffer_index + 1) % BUFFER_SIZE;
 
-		// circular buffer logic
-		buffer_index = (buffer_index + 1) % BUFFER_SIZE;
 
+	// Calculate the moving average based on a mutable value
+	// It requires empirical tests for choosing that value
+	for(uint8_t i = 0; i < BUFFER_SIZE; i++){
+		buffer_sum += movave_buffer[i];
+	}
+	mov_ave = buffer_sum / BUFFER_SIZE;
+
+	// Avoid variable type overflow
+	buffer_sum = 0;
+	if(buffer_index == 256)
+		buffer_index = 0;
+
+	// circular buffer logic
+	buffer_index = (buffer_index + 1) % BUFFER_SIZE;
 
-		// Calculate the moving average based on a mutable value
-		// It requires empirical tests for choosing that value
-		for(uint8_t i = 0; i < BUFFER_SIZE; i++){
-			buffer_sum += movave_buffer[i];
-		}
-		mov_ave = buffer_sum / BUFFER_SIZE;
 
-		// Avoid variable type overflow
-		buffer_sum = 0;
-		if(buffer_index == 256)
-			buffer_index = 0;
+	// Calculate the moving average based on a mutable value
+	// It requires empirical tests for choosing that value
+	for(uint8_t i = 0; i < BUFFER_SIZE; i++){
+		buffer_sum += movave_buffer[i];
 	}
+	mov_ave = buffer_sum / BUFFER_SIZE;
+
+	// Avoid variable type overflow
+	buffer_sum = 0;
+	if(buffer_index == 256)
+		buffer_index = 0;
+
 
 }
 
diff --git a/Core/Src/stm32h7xx_hal_msp.c b/Core/Src/stm32h7xx_hal_msp.c
index c18acd2c..76841626 100644
--- a/Core/Src/stm32h7xx_hal_msp.c
+++ b/Core/Src/stm32h7xx_hal_msp.c
@@ -1,690 +1,690 @@
-/* USER CODE BEGIN Header */
-/**
-  ******************************************************************************
-  * File Name          : stm32h7xx_hal_msp.c
-  * Description        : This file provides code for the MSP Initialization 
-  *                      and de-Initialization codes.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-/* USER CODE END Header */
-
-/* Includes ------------------------------------------------------------------*/
-#include "main.h"
-/* USER CODE BEGIN Includes */
-
-/* USER CODE END Includes */
-extern DMA_HandleTypeDef hdma_adc1;
-
-/* Private typedef -----------------------------------------------------------*/
-/* USER CODE BEGIN TD */
-
-/* USER CODE END TD */
-
-/* Private define ------------------------------------------------------------*/
-/* USER CODE BEGIN Define */
- 
-/* USER CODE END Define */
-
-/* Private macro -------------------------------------------------------------*/
-/* USER CODE BEGIN Macro */
-
-/* USER CODE END Macro */
-
-/* Private variables ---------------------------------------------------------*/
-/* USER CODE BEGIN PV */
-
-/* USER CODE END PV */
-
-/* Private function prototypes -----------------------------------------------*/
-/* USER CODE BEGIN PFP */
-
-/* USER CODE END PFP */
-
-/* External functions --------------------------------------------------------*/
-/* USER CODE BEGIN ExternalFunctions */
-
-/* USER CODE END ExternalFunctions */
-
-/* USER CODE BEGIN 0 */
-
-/* USER CODE END 0 */
-/**
-  * Initializes the Global MSP.
-  */
-void HAL_MspInit(void)
-{
-  /* USER CODE BEGIN MspInit 0 */
-
-  /* USER CODE END MspInit 0 */
-
-  __HAL_RCC_SYSCFG_CLK_ENABLE();
-
-  /* System interrupt init*/
-  /* PendSV_IRQn interrupt configuration */
-  HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0);
-
-  /* USER CODE BEGIN MspInit 1 */
-
-  /* USER CODE END MspInit 1 */
-}
-
-/**
-* @brief ADC MSP Initialization
-* This function configures the hardware resources used in this example
-* @param hadc: ADC handle pointer
-* @retval None
-*/
-void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
-{
-  GPIO_InitTypeDef GPIO_InitStruct = {0};
-  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
-  if(hadc->Instance==ADC1)
-  {
-  /* USER CODE BEGIN ADC1_MspInit 0 */
-
-  /* USER CODE END ADC1_MspInit 0 */
-
-  /** Initializes the peripherals clock
-  */
-    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADC;
-    PeriphClkInitStruct.PLL2.PLL2M = 1;
-    PeriphClkInitStruct.PLL2.PLL2N = 18;
-    PeriphClkInitStruct.PLL2.PLL2P = 4;
-    PeriphClkInitStruct.PLL2.PLL2Q = 2;
-    PeriphClkInitStruct.PLL2.PLL2R = 2;
-    PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_3;
-    PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2VCOMEDIUM;
-    PeriphClkInitStruct.PLL2.PLL2FRACN = 6144;
-    PeriphClkInitStruct.AdcClockSelection = RCC_ADCCLKSOURCE_PLL2;
-    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
-    {
-      Error_Handler();
-    }
-
-    /* Peripheral clock enable */
-    __HAL_RCC_ADC12_CLK_ENABLE();
-
-    __HAL_RCC_GPIOA_CLK_ENABLE();
-    __HAL_RCC_GPIOC_CLK_ENABLE();
-    __HAL_RCC_GPIOB_CLK_ENABLE();
-    /**ADC1 GPIO Configuration
-    PA5     ------> ADC1_INP19
-    PA6     ------> ADC1_INP3
-    PA7     ------> ADC1_INP7
-    PC4     ------> ADC1_INP4
-    PC5     ------> ADC1_INP8
-    PB1     ------> ADC1_INP5
-    */
-    GPIO_InitStruct.Pin = S_APPS2_Pin|S_APPS1_Pin|S_FREIO_Pin;
-    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
-    GPIO_InitStruct.Pull = GPIO_NOPULL;
-    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
-
-    GPIO_InitStruct.Pin = S_VOLANTE_Pin|S_ADC_E1_Pin;
-    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
-    GPIO_InitStruct.Pull = GPIO_NOPULL;
-    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
-
-    GPIO_InitStruct.Pin = S_ADC_E2_Pin;
-    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
-    GPIO_InitStruct.Pull = GPIO_NOPULL;
-    HAL_GPIO_Init(S_ADC_E2_GPIO_Port, &GPIO_InitStruct);
-
-    /* ADC1 DMA Init */
-    /* ADC1 Init */
-    hdma_adc1.Instance = DMA1_Stream0;
-    hdma_adc1.Init.Request = DMA_REQUEST_ADC1;
-    hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY;
-    hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE;
-    hdma_adc1.Init.MemInc = DMA_MINC_ENABLE;
-    hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
-    hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;
-    hdma_adc1.Init.Mode = DMA_CIRCULAR;
-    hdma_adc1.Init.Priority = DMA_PRIORITY_LOW;
-    hdma_adc1.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
-    if (HAL_DMA_Init(&hdma_adc1) != HAL_OK)
-    {
-      Error_Handler();
-    }
-
-    __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc1);
-
-  /* USER CODE BEGIN ADC1_MspInit 1 */
-
-  /* USER CODE END ADC1_MspInit 1 */
-  }
-
-}
-
-/**
-* @brief ADC MSP De-Initialization
-* This function freeze the hardware resources used in this example
-* @param hadc: ADC handle pointer
-* @retval None
-*/
-void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
-{
-  if(hadc->Instance==ADC1)
-  {
-  /* USER CODE BEGIN ADC1_MspDeInit 0 */
-
-  /* USER CODE END ADC1_MspDeInit 0 */
-    /* Peripheral clock disable */
-    __HAL_RCC_ADC12_CLK_DISABLE();
-
-    /**ADC1 GPIO Configuration
-    PA5     ------> ADC1_INP19
-    PA6     ------> ADC1_INP3
-    PA7     ------> ADC1_INP7
-    PC4     ------> ADC1_INP4
-    PC5     ------> ADC1_INP8
-    PB1     ------> ADC1_INP5
-    */
-    HAL_GPIO_DeInit(GPIOA, S_APPS2_Pin|S_APPS1_Pin|S_FREIO_Pin);
-
-    HAL_GPIO_DeInit(GPIOC, S_VOLANTE_Pin|S_ADC_E1_Pin);
-
-    HAL_GPIO_DeInit(S_ADC_E2_GPIO_Port, S_ADC_E2_Pin);
-
-    /* ADC1 DMA DeInit */
-    HAL_DMA_DeInit(hadc->DMA_Handle);
-  /* USER CODE BEGIN ADC1_MspDeInit 1 */
-
-  /* USER CODE END ADC1_MspDeInit 1 */
-  }
-
-}
-
-static uint32_t HAL_RCC_FDCAN_CLK_ENABLED=0;
-
-/**
-* @brief FDCAN MSP Initialization
-* This function configures the hardware resources used in this example
-* @param hfdcan: FDCAN handle pointer
-* @retval None
-*/
-void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef* hfdcan)
-{
-  GPIO_InitTypeDef GPIO_InitStruct = {0};
-  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
-  if(hfdcan->Instance==FDCAN1)
-  {
-  /* USER CODE BEGIN FDCAN1_MspInit 0 */
-
-  /* USER CODE END FDCAN1_MspInit 0 */
-
-  /** Initializes the peripherals clock
-  */
-    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_FDCAN;
-    PeriphClkInitStruct.FdcanClockSelection = RCC_FDCANCLKSOURCE_HSE;
-    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
-    {
-      Error_Handler();
-    }
-
-    /* Peripheral clock enable */
-    HAL_RCC_FDCAN_CLK_ENABLED++;
-    if(HAL_RCC_FDCAN_CLK_ENABLED==1){
-      __HAL_RCC_FDCAN_CLK_ENABLE();
-    }
-
-    __HAL_RCC_GPIOA_CLK_ENABLE();
-    /**FDCAN1 GPIO Configuration
-    PA11     ------> FDCAN1_RX
-    PA12     ------> FDCAN1_TX
-    */
-    GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12;
-    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
-    GPIO_InitStruct.Pull = GPIO_NOPULL;
-    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
-    GPIO_InitStruct.Alternate = GPIO_AF9_FDCAN1;
-    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
-
-    /* FDCAN1 interrupt Init */
-    HAL_NVIC_SetPriority(FDCAN1_IT0_IRQn, 5, 0);
-    HAL_NVIC_EnableIRQ(FDCAN1_IT0_IRQn);
-    HAL_NVIC_SetPriority(FDCAN1_IT1_IRQn, 5, 0);
-    HAL_NVIC_EnableIRQ(FDCAN1_IT1_IRQn);
-  /* USER CODE BEGIN FDCAN1_MspInit 1 */
-
-  /* USER CODE END FDCAN1_MspInit 1 */
-  }
-  else if(hfdcan->Instance==FDCAN2)
-  {
-  /* USER CODE BEGIN FDCAN2_MspInit 0 */
-
-  /* USER CODE END FDCAN2_MspInit 0 */
-
-  /** Initializes the peripherals clock
-  */
-    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_FDCAN;
-    PeriphClkInitStruct.FdcanClockSelection = RCC_FDCANCLKSOURCE_HSE;
-    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
-    {
-      Error_Handler();
-    }
-
-    /* Peripheral clock enable */
-    HAL_RCC_FDCAN_CLK_ENABLED++;
-    if(HAL_RCC_FDCAN_CLK_ENABLED==1){
-      __HAL_RCC_FDCAN_CLK_ENABLE();
-    }
-
-    __HAL_RCC_GPIOB_CLK_ENABLE();
-    /**FDCAN2 GPIO Configuration
-    PB12     ------> FDCAN2_RX
-    PB13     ------> FDCAN2_TX
-    */
-    GPIO_InitStruct.Pin = GPIO_PIN_12|GPIO_PIN_13;
-    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
-    GPIO_InitStruct.Pull = GPIO_NOPULL;
-    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
-    GPIO_InitStruct.Alternate = GPIO_AF9_FDCAN2;
-    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
-
-    /* FDCAN2 interrupt Init */
-    HAL_NVIC_SetPriority(FDCAN2_IT0_IRQn, 5, 0);
-    HAL_NVIC_EnableIRQ(FDCAN2_IT0_IRQn);
-    HAL_NVIC_SetPriority(FDCAN2_IT1_IRQn, 5, 0);
-    HAL_NVIC_EnableIRQ(FDCAN2_IT1_IRQn);
-  /* USER CODE BEGIN FDCAN2_MspInit 1 */
-
-  /* USER CODE END FDCAN2_MspInit 1 */
-  }
-
-}
-
-/**
-* @brief FDCAN MSP De-Initialization
-* This function freeze the hardware resources used in this example
-* @param hfdcan: FDCAN handle pointer
-* @retval None
-*/
-void HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef* hfdcan)
-{
-  if(hfdcan->Instance==FDCAN1)
-  {
-  /* USER CODE BEGIN FDCAN1_MspDeInit 0 */
-
-  /* USER CODE END FDCAN1_MspDeInit 0 */
-    /* Peripheral clock disable */
-    HAL_RCC_FDCAN_CLK_ENABLED--;
-    if(HAL_RCC_FDCAN_CLK_ENABLED==0){
-      __HAL_RCC_FDCAN_CLK_DISABLE();
-    }
-
-    /**FDCAN1 GPIO Configuration
-    PA11     ------> FDCAN1_RX
-    PA12     ------> FDCAN1_TX
-    */
-    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_11|GPIO_PIN_12);
-
-    /* FDCAN1 interrupt DeInit */
-    HAL_NVIC_DisableIRQ(FDCAN1_IT0_IRQn);
-    HAL_NVIC_DisableIRQ(FDCAN1_IT1_IRQn);
-  /* USER CODE BEGIN FDCAN1_MspDeInit 1 */
-
-  /* USER CODE END FDCAN1_MspDeInit 1 */
-  }
-  else if(hfdcan->Instance==FDCAN2)
-  {
-  /* USER CODE BEGIN FDCAN2_MspDeInit 0 */
-
-  /* USER CODE END FDCAN2_MspDeInit 0 */
-    /* Peripheral clock disable */
-    HAL_RCC_FDCAN_CLK_ENABLED--;
-    if(HAL_RCC_FDCAN_CLK_ENABLED==0){
-      __HAL_RCC_FDCAN_CLK_DISABLE();
-    }
-
-    /**FDCAN2 GPIO Configuration
-    PB12     ------> FDCAN2_RX
-    PB13     ------> FDCAN2_TX
-    */
-    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_12|GPIO_PIN_13);
-
-    /* FDCAN2 interrupt DeInit */
-    HAL_NVIC_DisableIRQ(FDCAN2_IT0_IRQn);
-    HAL_NVIC_DisableIRQ(FDCAN2_IT1_IRQn);
-  /* USER CODE BEGIN FDCAN2_MspDeInit 1 */
-
-  /* USER CODE END FDCAN2_MspDeInit 1 */
-  }
-
-}
-
-/**
-* @brief I2C MSP Initialization
-* This function configures the hardware resources used in this example
-* @param hi2c: I2C handle pointer
-* @retval None
-*/
-void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c)
-{
-  GPIO_InitTypeDef GPIO_InitStruct = {0};
-  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
-  if(hi2c->Instance==I2C3)
-  {
-  /* USER CODE BEGIN I2C3_MspInit 0 */
-
-  /* USER CODE END I2C3_MspInit 0 */
-
-  /** Initializes the peripherals clock
-  */
-    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_I2C3;
-    PeriphClkInitStruct.I2c123ClockSelection = RCC_I2C123CLKSOURCE_D2PCLK1;
-    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
-    {
-      Error_Handler();
-    }
-
-    __HAL_RCC_GPIOC_CLK_ENABLE();
-    __HAL_RCC_GPIOA_CLK_ENABLE();
-    /**I2C3 GPIO Configuration
-    PC9     ------> I2C3_SDA
-    PA8     ------> I2C3_SCL
-    */
-    GPIO_InitStruct.Pin = GPIO_PIN_9;
-    GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
-    GPIO_InitStruct.Pull = GPIO_PULLUP;
-    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
-    GPIO_InitStruct.Alternate = GPIO_AF4_I2C3;
-    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
-
-    GPIO_InitStruct.Pin = GPIO_PIN_8;
-    GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
-    GPIO_InitStruct.Pull = GPIO_PULLUP;
-    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
-    GPIO_InitStruct.Alternate = GPIO_AF4_I2C3;
-    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
-
-    /* Peripheral clock enable */
-    __HAL_RCC_I2C3_CLK_ENABLE();
-  /* USER CODE BEGIN I2C3_MspInit 1 */
-
-  /* USER CODE END I2C3_MspInit 1 */
-  }
-
-}
-
-/**
-* @brief I2C MSP De-Initialization
-* This function freeze the hardware resources used in this example
-* @param hi2c: I2C handle pointer
-* @retval None
-*/
-void HAL_I2C_MspDeInit(I2C_HandleTypeDef* hi2c)
-{
-  if(hi2c->Instance==I2C3)
-  {
-  /* USER CODE BEGIN I2C3_MspDeInit 0 */
-
-  /* USER CODE END I2C3_MspDeInit 0 */
-    /* Peripheral clock disable */
-    __HAL_RCC_I2C3_CLK_DISABLE();
-
-    /**I2C3 GPIO Configuration
-    PC9     ------> I2C3_SDA
-    PA8     ------> I2C3_SCL
-    */
-    HAL_GPIO_DeInit(GPIOC, GPIO_PIN_9);
-
-    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_8);
-
-  /* USER CODE BEGIN I2C3_MspDeInit 1 */
-
-  /* USER CODE END I2C3_MspDeInit 1 */
-  }
-
-}
-
-/**
-* @brief UART MSP Initialization
-* This function configures the hardware resources used in this example
-* @param huart: UART handle pointer
-* @retval None
-*/
-void HAL_UART_MspInit(UART_HandleTypeDef* huart)
-{
-  GPIO_InitTypeDef GPIO_InitStruct = {0};
-  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
-  if(huart->Instance==LPUART1)
-  {
-  /* USER CODE BEGIN LPUART1_MspInit 0 */
-
-  /* USER CODE END LPUART1_MspInit 0 */
-
-  /** Initializes the peripherals clock
-  */
-    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPUART1;
-    PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_D3PCLK1;
-    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
-    {
-      Error_Handler();
-    }
-
-    /* Peripheral clock enable */
-    __HAL_RCC_LPUART1_CLK_ENABLE();
-
-    __HAL_RCC_GPIOA_CLK_ENABLE();
-    /**LPUART1 GPIO Configuration
-    PA9     ------> LPUART1_TX
-    PA10     ------> LPUART1_RX
-    */
-    GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10;
-    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
-    GPIO_InitStruct.Pull = GPIO_NOPULL;
-    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
-    GPIO_InitStruct.Alternate = GPIO_AF3_LPUART;
-    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
-
-  /* USER CODE BEGIN LPUART1_MspInit 1 */
-
-  /* USER CODE END LPUART1_MspInit 1 */
-  }
-
-}
-
-/**
-* @brief UART MSP De-Initialization
-* This function freeze the hardware resources used in this example
-* @param huart: UART handle pointer
-* @retval None
-*/
-void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
-{
-  if(huart->Instance==LPUART1)
-  {
-  /* USER CODE BEGIN LPUART1_MspDeInit 0 */
-
-  /* USER CODE END LPUART1_MspDeInit 0 */
-    /* Peripheral clock disable */
-    __HAL_RCC_LPUART1_CLK_DISABLE();
-
-    /**LPUART1 GPIO Configuration
-    PA9     ------> LPUART1_TX
-    PA10     ------> LPUART1_RX
-    */
-    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10);
-
-  /* USER CODE BEGIN LPUART1_MspDeInit 1 */
-
-  /* USER CODE END LPUART1_MspDeInit 1 */
-  }
-
-}
-
-/**
-* @brief SPI MSP Initialization
-* This function configures the hardware resources used in this example
-* @param hspi: SPI handle pointer
-* @retval None
-*/
-void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi)
-{
-  GPIO_InitTypeDef GPIO_InitStruct = {0};
-  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
-  if(hspi->Instance==SPI1)
-  {
-  /* USER CODE BEGIN SPI1_MspInit 0 */
-
-  /* USER CODE END SPI1_MspInit 0 */
-
-  /** Initializes the peripherals clock
-  */
-    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SPI1;
-    PeriphClkInitStruct.Spi123ClockSelection = RCC_SPI123CLKSOURCE_PLL;
-    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
-    {
-      Error_Handler();
-    }
-
-    /* Peripheral clock enable */
-    __HAL_RCC_SPI1_CLK_ENABLE();
-
-    __HAL_RCC_GPIOD_CLK_ENABLE();
-    __HAL_RCC_GPIOB_CLK_ENABLE();
-    /**SPI1 GPIO Configuration
-    PD7     ------> SPI1_MOSI
-    PB3 (JTDO/TRACESWO)     ------> SPI1_SCK
-    PB4 (NJTRST)     ------> SPI1_MISO
-    */
-    GPIO_InitStruct.Pin = GPIO_PIN_7;
-    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
-    GPIO_InitStruct.Pull = GPIO_NOPULL;
-    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
-    GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;
-    HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
-
-    GPIO_InitStruct.Pin = GPIO_PIN_3|GPIO_PIN_4;
-    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
-    GPIO_InitStruct.Pull = GPIO_NOPULL;
-    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
-    GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;
-    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
-
-  /* USER CODE BEGIN SPI1_MspInit 1 */
-
-  /* USER CODE END SPI1_MspInit 1 */
-  }
-
-}
-
-/**
-* @brief SPI MSP De-Initialization
-* This function freeze the hardware resources used in this example
-* @param hspi: SPI handle pointer
-* @retval None
-*/
-void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi)
-{
-  if(hspi->Instance==SPI1)
-  {
-  /* USER CODE BEGIN SPI1_MspDeInit 0 */
-
-  /* USER CODE END SPI1_MspDeInit 0 */
-    /* Peripheral clock disable */
-    __HAL_RCC_SPI1_CLK_DISABLE();
-
-    /**SPI1 GPIO Configuration
-    PD7     ------> SPI1_MOSI
-    PB3 (JTDO/TRACESWO)     ------> SPI1_SCK
-    PB4 (NJTRST)     ------> SPI1_MISO
-    */
-    HAL_GPIO_DeInit(GPIOD, GPIO_PIN_7);
-
-    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_3|GPIO_PIN_4);
-
-  /* USER CODE BEGIN SPI1_MspDeInit 1 */
-
-  /* USER CODE END SPI1_MspDeInit 1 */
-  }
-
-}
-
-/**
-* @brief TIM_Base MSP Initialization
-* This function configures the hardware resources used in this example
-* @param htim_base: TIM_Base handle pointer
-* @retval None
-*/
-void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
-{
-  if(htim_base->Instance==TIM1)
-  {
-  /* USER CODE BEGIN TIM1_MspInit 0 */
-
-  /* USER CODE END TIM1_MspInit 0 */
-    /* Peripheral clock enable */
-    __HAL_RCC_TIM1_CLK_ENABLE();
-    /* TIM1 interrupt Init */
-    HAL_NVIC_SetPriority(TIM1_TRG_COM_IRQn, 5, 0);
-    HAL_NVIC_EnableIRQ(TIM1_TRG_COM_IRQn);
-  /* USER CODE BEGIN TIM1_MspInit 1 */
-
-  /* USER CODE END TIM1_MspInit 1 */
-  }
-  else if(htim_base->Instance==TIM2)
-  {
-  /* USER CODE BEGIN TIM2_MspInit 0 */
-
-  /* USER CODE END TIM2_MspInit 0 */
-    /* Peripheral clock enable */
-    __HAL_RCC_TIM2_CLK_ENABLE();
-  /* USER CODE BEGIN TIM2_MspInit 1 */
-
-  /* USER CODE END TIM2_MspInit 1 */
-  }
-
-}
-
-/**
-* @brief TIM_Base MSP De-Initialization
-* This function freeze the hardware resources used in this example
-* @param htim_base: TIM_Base handle pointer
-* @retval None
-*/
-void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* htim_base)
-{
-  if(htim_base->Instance==TIM1)
-  {
-  /* USER CODE BEGIN TIM1_MspDeInit 0 */
-
-  /* USER CODE END TIM1_MspDeInit 0 */
-    /* Peripheral clock disable */
-    __HAL_RCC_TIM1_CLK_DISABLE();
-
-    /* TIM1 interrupt DeInit */
-    HAL_NVIC_DisableIRQ(TIM1_TRG_COM_IRQn);
-  /* USER CODE BEGIN TIM1_MspDeInit 1 */
-
-  /* USER CODE END TIM1_MspDeInit 1 */
-  }
-  else if(htim_base->Instance==TIM2)
-  {
-  /* USER CODE BEGIN TIM2_MspDeInit 0 */
-
-  /* USER CODE END TIM2_MspDeInit 0 */
-    /* Peripheral clock disable */
-    __HAL_RCC_TIM2_CLK_DISABLE();
-  /* USER CODE BEGIN TIM2_MspDeInit 1 */
-
-  /* USER CODE END TIM2_MspDeInit 1 */
-  }
-
-}
-
-/* USER CODE BEGIN 1 */
-
-/* USER CODE END 1 */
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * File Name          : stm32h7xx_hal_msp.c
+  * Description        : This file provides code for the MSP Initialization 
+  *                      and de-Initialization codes.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+extern DMA_HandleTypeDef hdma_adc1;
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+ 
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+  /* System interrupt init*/
+  /* PendSV_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0);
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/**
+* @brief ADC MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hadc: ADC handle pointer
+* @retval None
+*/
+void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+  if(hadc->Instance==ADC1)
+  {
+  /* USER CODE BEGIN ADC1_MspInit 0 */
+
+  /* USER CODE END ADC1_MspInit 0 */
+
+  /** Initializes the peripherals clock
+  */
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADC;
+    PeriphClkInitStruct.PLL2.PLL2M = 1;
+    PeriphClkInitStruct.PLL2.PLL2N = 18;
+    PeriphClkInitStruct.PLL2.PLL2P = 4;
+    PeriphClkInitStruct.PLL2.PLL2Q = 2;
+    PeriphClkInitStruct.PLL2.PLL2R = 2;
+    PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_3;
+    PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2VCOMEDIUM;
+    PeriphClkInitStruct.PLL2.PLL2FRACN = 6144;
+    PeriphClkInitStruct.AdcClockSelection = RCC_ADCCLKSOURCE_PLL2;
+    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    /* Peripheral clock enable */
+    __HAL_RCC_ADC12_CLK_ENABLE();
+
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    __HAL_RCC_GPIOC_CLK_ENABLE();
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    /**ADC1 GPIO Configuration
+    PA5     ------> ADC1_INP19
+    PA6     ------> ADC1_INP3
+    PA7     ------> ADC1_INP7
+    PC4     ------> ADC1_INP4
+    PC5     ------> ADC1_INP8
+    PB1     ------> ADC1_INP5
+    */
+    GPIO_InitStruct.Pin = S_APPS2_Pin|S_APPS1_Pin|S_FREIO_Pin;
+    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = S_VOLANTE_Pin|S_ADC_E1_Pin;
+    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = S_ADC_E2_Pin;
+    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    HAL_GPIO_Init(S_ADC_E2_GPIO_Port, &GPIO_InitStruct);
+
+    /* ADC1 DMA Init */
+    /* ADC1 Init */
+    hdma_adc1.Instance = DMA1_Stream0;
+    hdma_adc1.Init.Request = DMA_REQUEST_ADC1;
+    hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY;
+    hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE;
+    hdma_adc1.Init.MemInc = DMA_MINC_ENABLE;
+    hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
+    hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;
+    hdma_adc1.Init.Mode = DMA_CIRCULAR;
+    hdma_adc1.Init.Priority = DMA_PRIORITY_LOW;
+    hdma_adc1.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
+    if (HAL_DMA_Init(&hdma_adc1) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc1);
+
+  /* USER CODE BEGIN ADC1_MspInit 1 */
+
+  /* USER CODE END ADC1_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief ADC MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hadc: ADC handle pointer
+* @retval None
+*/
+void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
+{
+  if(hadc->Instance==ADC1)
+  {
+  /* USER CODE BEGIN ADC1_MspDeInit 0 */
+
+  /* USER CODE END ADC1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_ADC12_CLK_DISABLE();
+
+    /**ADC1 GPIO Configuration
+    PA5     ------> ADC1_INP19
+    PA6     ------> ADC1_INP3
+    PA7     ------> ADC1_INP7
+    PC4     ------> ADC1_INP4
+    PC5     ------> ADC1_INP8
+    PB1     ------> ADC1_INP5
+    */
+    HAL_GPIO_DeInit(GPIOA, S_APPS2_Pin|S_APPS1_Pin|S_FREIO_Pin);
+
+    HAL_GPIO_DeInit(GPIOC, S_VOLANTE_Pin|S_ADC_E1_Pin);
+
+    HAL_GPIO_DeInit(S_ADC_E2_GPIO_Port, S_ADC_E2_Pin);
+
+    /* ADC1 DMA DeInit */
+    HAL_DMA_DeInit(hadc->DMA_Handle);
+  /* USER CODE BEGIN ADC1_MspDeInit 1 */
+
+  /* USER CODE END ADC1_MspDeInit 1 */
+  }
+
+}
+
+static uint32_t HAL_RCC_FDCAN_CLK_ENABLED=0;
+
+/**
+* @brief FDCAN MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hfdcan: FDCAN handle pointer
+* @retval None
+*/
+void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef* hfdcan)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+  if(hfdcan->Instance==FDCAN1)
+  {
+  /* USER CODE BEGIN FDCAN1_MspInit 0 */
+
+  /* USER CODE END FDCAN1_MspInit 0 */
+
+  /** Initializes the peripherals clock
+  */
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_FDCAN;
+    PeriphClkInitStruct.FdcanClockSelection = RCC_FDCANCLKSOURCE_HSE;
+    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    /* Peripheral clock enable */
+    HAL_RCC_FDCAN_CLK_ENABLED++;
+    if(HAL_RCC_FDCAN_CLK_ENABLED==1){
+      __HAL_RCC_FDCAN_CLK_ENABLE();
+    }
+
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    /**FDCAN1 GPIO Configuration
+    PA11     ------> FDCAN1_RX
+    PA12     ------> FDCAN1_TX
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF9_FDCAN1;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+    /* FDCAN1 interrupt Init */
+    HAL_NVIC_SetPriority(FDCAN1_IT0_IRQn, 5, 0);
+    HAL_NVIC_EnableIRQ(FDCAN1_IT0_IRQn);
+    HAL_NVIC_SetPriority(FDCAN1_IT1_IRQn, 5, 0);
+    HAL_NVIC_EnableIRQ(FDCAN1_IT1_IRQn);
+  /* USER CODE BEGIN FDCAN1_MspInit 1 */
+
+  /* USER CODE END FDCAN1_MspInit 1 */
+  }
+  else if(hfdcan->Instance==FDCAN2)
+  {
+  /* USER CODE BEGIN FDCAN2_MspInit 0 */
+
+  /* USER CODE END FDCAN2_MspInit 0 */
+
+  /** Initializes the peripherals clock
+  */
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_FDCAN;
+    PeriphClkInitStruct.FdcanClockSelection = RCC_FDCANCLKSOURCE_HSE;
+    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    /* Peripheral clock enable */
+    HAL_RCC_FDCAN_CLK_ENABLED++;
+    if(HAL_RCC_FDCAN_CLK_ENABLED==1){
+      __HAL_RCC_FDCAN_CLK_ENABLE();
+    }
+
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    /**FDCAN2 GPIO Configuration
+    PB12     ------> FDCAN2_RX
+    PB13     ------> FDCAN2_TX
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_12|GPIO_PIN_13;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF9_FDCAN2;
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+    /* FDCAN2 interrupt Init */
+    HAL_NVIC_SetPriority(FDCAN2_IT0_IRQn, 5, 0);
+    HAL_NVIC_EnableIRQ(FDCAN2_IT0_IRQn);
+    HAL_NVIC_SetPriority(FDCAN2_IT1_IRQn, 5, 0);
+    HAL_NVIC_EnableIRQ(FDCAN2_IT1_IRQn);
+  /* USER CODE BEGIN FDCAN2_MspInit 1 */
+
+  /* USER CODE END FDCAN2_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief FDCAN MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hfdcan: FDCAN handle pointer
+* @retval None
+*/
+void HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef* hfdcan)
+{
+  if(hfdcan->Instance==FDCAN1)
+  {
+  /* USER CODE BEGIN FDCAN1_MspDeInit 0 */
+
+  /* USER CODE END FDCAN1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    HAL_RCC_FDCAN_CLK_ENABLED--;
+    if(HAL_RCC_FDCAN_CLK_ENABLED==0){
+      __HAL_RCC_FDCAN_CLK_DISABLE();
+    }
+
+    /**FDCAN1 GPIO Configuration
+    PA11     ------> FDCAN1_RX
+    PA12     ------> FDCAN1_TX
+    */
+    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_11|GPIO_PIN_12);
+
+    /* FDCAN1 interrupt DeInit */
+    HAL_NVIC_DisableIRQ(FDCAN1_IT0_IRQn);
+    HAL_NVIC_DisableIRQ(FDCAN1_IT1_IRQn);
+  /* USER CODE BEGIN FDCAN1_MspDeInit 1 */
+
+  /* USER CODE END FDCAN1_MspDeInit 1 */
+  }
+  else if(hfdcan->Instance==FDCAN2)
+  {
+  /* USER CODE BEGIN FDCAN2_MspDeInit 0 */
+
+  /* USER CODE END FDCAN2_MspDeInit 0 */
+    /* Peripheral clock disable */
+    HAL_RCC_FDCAN_CLK_ENABLED--;
+    if(HAL_RCC_FDCAN_CLK_ENABLED==0){
+      __HAL_RCC_FDCAN_CLK_DISABLE();
+    }
+
+    /**FDCAN2 GPIO Configuration
+    PB12     ------> FDCAN2_RX
+    PB13     ------> FDCAN2_TX
+    */
+    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_12|GPIO_PIN_13);
+
+    /* FDCAN2 interrupt DeInit */
+    HAL_NVIC_DisableIRQ(FDCAN2_IT0_IRQn);
+    HAL_NVIC_DisableIRQ(FDCAN2_IT1_IRQn);
+  /* USER CODE BEGIN FDCAN2_MspDeInit 1 */
+
+  /* USER CODE END FDCAN2_MspDeInit 1 */
+  }
+
+}
+
+/**
+* @brief I2C MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hi2c: I2C handle pointer
+* @retval None
+*/
+void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+  if(hi2c->Instance==I2C3)
+  {
+  /* USER CODE BEGIN I2C3_MspInit 0 */
+
+  /* USER CODE END I2C3_MspInit 0 */
+
+  /** Initializes the peripherals clock
+  */
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_I2C3;
+    PeriphClkInitStruct.I2c123ClockSelection = RCC_I2C123CLKSOURCE_D2PCLK1;
+    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    __HAL_RCC_GPIOC_CLK_ENABLE();
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    /**I2C3 GPIO Configuration
+    PC9     ------> I2C3_SDA
+    PA8     ------> I2C3_SCL
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_9;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
+    GPIO_InitStruct.Pull = GPIO_PULLUP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF4_I2C3;
+    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = GPIO_PIN_8;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
+    GPIO_InitStruct.Pull = GPIO_PULLUP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF4_I2C3;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+    /* Peripheral clock enable */
+    __HAL_RCC_I2C3_CLK_ENABLE();
+  /* USER CODE BEGIN I2C3_MspInit 1 */
+
+  /* USER CODE END I2C3_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief I2C MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hi2c: I2C handle pointer
+* @retval None
+*/
+void HAL_I2C_MspDeInit(I2C_HandleTypeDef* hi2c)
+{
+  if(hi2c->Instance==I2C3)
+  {
+  /* USER CODE BEGIN I2C3_MspDeInit 0 */
+
+  /* USER CODE END I2C3_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_I2C3_CLK_DISABLE();
+
+    /**I2C3 GPIO Configuration
+    PC9     ------> I2C3_SDA
+    PA8     ------> I2C3_SCL
+    */
+    HAL_GPIO_DeInit(GPIOC, GPIO_PIN_9);
+
+    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_8);
+
+  /* USER CODE BEGIN I2C3_MspDeInit 1 */
+
+  /* USER CODE END I2C3_MspDeInit 1 */
+  }
+
+}
+
+/**
+* @brief UART MSP Initialization
+* This function configures the hardware resources used in this example
+* @param huart: UART handle pointer
+* @retval None
+*/
+void HAL_UART_MspInit(UART_HandleTypeDef* huart)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+  if(huart->Instance==LPUART1)
+  {
+  /* USER CODE BEGIN LPUART1_MspInit 0 */
+
+  /* USER CODE END LPUART1_MspInit 0 */
+
+  /** Initializes the peripherals clock
+  */
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPUART1;
+    PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_D3PCLK1;
+    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    /* Peripheral clock enable */
+    __HAL_RCC_LPUART1_CLK_ENABLE();
+
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    /**LPUART1 GPIO Configuration
+    PA9     ------> LPUART1_TX
+    PA10     ------> LPUART1_RX
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF3_LPUART;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  /* USER CODE BEGIN LPUART1_MspInit 1 */
+
+  /* USER CODE END LPUART1_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief UART MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param huart: UART handle pointer
+* @retval None
+*/
+void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
+{
+  if(huart->Instance==LPUART1)
+  {
+  /* USER CODE BEGIN LPUART1_MspDeInit 0 */
+
+  /* USER CODE END LPUART1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_LPUART1_CLK_DISABLE();
+
+    /**LPUART1 GPIO Configuration
+    PA9     ------> LPUART1_TX
+    PA10     ------> LPUART1_RX
+    */
+    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10);
+
+  /* USER CODE BEGIN LPUART1_MspDeInit 1 */
+
+  /* USER CODE END LPUART1_MspDeInit 1 */
+  }
+
+}
+
+/**
+* @brief SPI MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hspi: SPI handle pointer
+* @retval None
+*/
+void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+  if(hspi->Instance==SPI1)
+  {
+  /* USER CODE BEGIN SPI1_MspInit 0 */
+
+  /* USER CODE END SPI1_MspInit 0 */
+
+  /** Initializes the peripherals clock
+  */
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SPI1;
+    PeriphClkInitStruct.Spi123ClockSelection = RCC_SPI123CLKSOURCE_PLL;
+    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    /* Peripheral clock enable */
+    __HAL_RCC_SPI1_CLK_ENABLE();
+
+    __HAL_RCC_GPIOD_CLK_ENABLE();
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    /**SPI1 GPIO Configuration
+    PD7     ------> SPI1_MOSI
+    PB3 (JTDO/TRACESWO)     ------> SPI1_SCK
+    PB4 (NJTRST)     ------> SPI1_MISO
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_7;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;
+    HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = GPIO_PIN_3|GPIO_PIN_4;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+  /* USER CODE BEGIN SPI1_MspInit 1 */
+
+  /* USER CODE END SPI1_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief SPI MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hspi: SPI handle pointer
+* @retval None
+*/
+void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi)
+{
+  if(hspi->Instance==SPI1)
+  {
+  /* USER CODE BEGIN SPI1_MspDeInit 0 */
+
+  /* USER CODE END SPI1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_SPI1_CLK_DISABLE();
+
+    /**SPI1 GPIO Configuration
+    PD7     ------> SPI1_MOSI
+    PB3 (JTDO/TRACESWO)     ------> SPI1_SCK
+    PB4 (NJTRST)     ------> SPI1_MISO
+    */
+    HAL_GPIO_DeInit(GPIOD, GPIO_PIN_7);
+
+    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_3|GPIO_PIN_4);
+
+  /* USER CODE BEGIN SPI1_MspDeInit 1 */
+
+  /* USER CODE END SPI1_MspDeInit 1 */
+  }
+
+}
+
+/**
+* @brief TIM_Base MSP Initialization
+* This function configures the hardware resources used in this example
+* @param htim_base: TIM_Base handle pointer
+* @retval None
+*/
+void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
+{
+  if(htim_base->Instance==TIM1)
+  {
+  /* USER CODE BEGIN TIM1_MspInit 0 */
+
+  /* USER CODE END TIM1_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_TIM1_CLK_ENABLE();
+    /* TIM1 interrupt Init */
+    HAL_NVIC_SetPriority(TIM1_TRG_COM_IRQn, 5, 0);
+    HAL_NVIC_EnableIRQ(TIM1_TRG_COM_IRQn);
+  /* USER CODE BEGIN TIM1_MspInit 1 */
+
+  /* USER CODE END TIM1_MspInit 1 */
+  }
+  else if(htim_base->Instance==TIM2)
+  {
+  /* USER CODE BEGIN TIM2_MspInit 0 */
+
+  /* USER CODE END TIM2_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_TIM2_CLK_ENABLE();
+  /* USER CODE BEGIN TIM2_MspInit 1 */
+
+  /* USER CODE END TIM2_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief TIM_Base MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param htim_base: TIM_Base handle pointer
+* @retval None
+*/
+void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* htim_base)
+{
+  if(htim_base->Instance==TIM1)
+  {
+  /* USER CODE BEGIN TIM1_MspDeInit 0 */
+
+  /* USER CODE END TIM1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_TIM1_CLK_DISABLE();
+
+    /* TIM1 interrupt DeInit */
+    HAL_NVIC_DisableIRQ(TIM1_TRG_COM_IRQn);
+  /* USER CODE BEGIN TIM1_MspDeInit 1 */
+
+  /* USER CODE END TIM1_MspDeInit 1 */
+  }
+  else if(htim_base->Instance==TIM2)
+  {
+  /* USER CODE BEGIN TIM2_MspDeInit 0 */
+
+  /* USER CODE END TIM2_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_TIM2_CLK_DISABLE();
+  /* USER CODE BEGIN TIM2_MspDeInit 1 */
+
+  /* USER CODE END TIM2_MspDeInit 1 */
+  }
+
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
diff --git a/Core/Src/torque_command/torque_manager.c b/Core/Src/torque_command/torque_manager.c
index 3c3ac6b1..d0f82d0b 100644
--- a/Core/Src/torque_command/torque_manager.c
+++ b/Core/Src/torque_command/torque_manager.c
@@ -35,8 +35,10 @@ void torque_manager(void* argument) {
 
         const bool is_DYNAMIC_CONTROL_active =
             get_individual_flag(e_ECU_control_flagsHandle, DYNAMIC_CONTROL_THREAD_FLAG);
+        const bool is_CROSS_VALIDATION_ok =
+        	get_individual_flag(e_ECU_control_flagsHandle, CROSS_VALIDATION_FLAG); // COLOCA UM TIMER Q SETA ESSA FLAG
 
-        select_dynamic_control(is_DYNAMIC_CONTROL_active);
+        select_dynamic_control(is_DYNAMIC_CONTROL_active, is_CROSS_VALIDATION_ok);
 
         // todo (João Pedro): add new "case's" when the integration of controls is
         // implemented
@@ -116,9 +118,9 @@ void send_ref_torque_message(const uint32_t* ref_torque) {
     osMessageQueuePut(q_ref_torque_messageHandle, &ref_torque_message, 0, 0U);
 }
 
-void select_dynamic_control(bool is_DYNAMIC_CONTROL_active) {
+void select_dynamic_control(bool is_DYNAMIC_CONTROL_active, bool is_CROSS_VALIDATION_ok) {
     // todo (João Pedro): add new "if's" when the integration of controls is implemented
-    if (is_DYNAMIC_CONTROL_active) {
+    if (is_DYNAMIC_CONTROL_active && is_CROSS_VALIDATION_ok) {
         if (get_global_var_value(SELECTED_MODE).dif_elt == 1
             && get_global_var_value(SELECTED_MODE).traction_control == 0) {
             g_control_type = LATERAL;
diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/LICENSE.txt b/Drivers/CMSIS/Device/ST/STM32H7xx/LICENSE.txt
index 872e82b4..5306686d 100644
--- a/Drivers/CMSIS/Device/ST/STM32H7xx/LICENSE.txt
+++ b/Drivers/CMSIS/Device/ST/STM32H7xx/LICENSE.txt
@@ -1,6 +1,6 @@
-This software component is provided to you as part of a software package and
-applicable license terms are in the  Package_license file. If you received this
-software component outside of a package or without applicable license terms,
-the terms of the Apache-2.0 license shall apply. 
-You may obtain a copy of the Apache-2.0 at:
-https://opensource.org/licenses/Apache-2.0
+This software component is provided to you as part of a software package and
+applicable license terms are in the  Package_license file. If you received this
+software component outside of a package or without applicable license terms,
+the terms of the Apache-2.0 license shall apply. 
+You may obtain a copy of the Apache-2.0 at:
+https://opensource.org/licenses/Apache-2.0
diff --git a/Drivers/CMSIS/LICENSE.txt b/Drivers/CMSIS/LICENSE.txt
index 8dada3ed..c0ee8129 100644
--- a/Drivers/CMSIS/LICENSE.txt
+++ b/Drivers/CMSIS/LICENSE.txt
@@ -1,201 +1,201 @@
-                                 Apache License
-                           Version 2.0, January 2004
-                        http://www.apache.org/licenses/
-
-   TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
-
-   1. Definitions.
-
-      "License" shall mean the terms and conditions for use, reproduction,
-      and distribution as defined by Sections 1 through 9 of this document.
-
-      "Licensor" shall mean the copyright owner or entity authorized by
-      the copyright owner that is granting the License.
-
-      "Legal Entity" shall mean the union of the acting entity and all
-      other entities that control, are controlled by, or are under common
-      control with that entity. For the purposes of this definition,
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-      direction or management of such entity, whether by contract or
-      otherwise, or (ii) ownership of fifty percent (50%) or more of the
-      outstanding shares, or (iii) beneficial ownership of such entity.
-
-      "You" (or "Your") shall mean an individual or Legal Entity
-      exercising permissions granted by this License.
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-      "Source" form shall mean the preferred form for making modifications,
-      including but not limited to software source code, documentation
-      source, and configuration files.
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-      transformation or translation of a Source form, including but
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-      and conversions to other media types.
-
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-      Object form, made available under the License, as indicated by a
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-      "Derivative Works" shall mean any work, whether in Source or Object
-      form, that is based on (or derived from) the Work and for which the
-      editorial revisions, annotations, elaborations, or other modifications
-      represent, as a whole, an original work of authorship. For the purposes
-      of this License, Derivative Works shall not include works that remain
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+                                 Apache License
+                           Version 2.0, January 2004
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+
+   TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
+
+   1. Definitions.
+
+      "License" shall mean the terms and conditions for use, reproduction,
+      and distribution as defined by Sections 1 through 9 of this document.
+
+      "Licensor" shall mean the copyright owner or entity authorized by
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+      "Legal Entity" shall mean the union of the acting entity and all
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+      outstanding shares, or (iii) beneficial ownership of such entity.
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+      "You" (or "Your") shall mean an individual or Legal Entity
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+      including but not limited to software source code, documentation
+      source, and configuration files.
+
+      "Object" form shall mean any form resulting from mechanical
+      transformation or translation of a Source form, including but
+      not limited to compiled object code, generated documentation,
+      and conversions to other media types.
+
+      "Work" shall mean the work of authorship, whether in Source or
+      Object form, made available under the License, as indicated by a
+      copyright notice that is included in or attached to the work
+      (an example is provided in the Appendix below).
+
+      "Derivative Works" shall mean any work, whether in Source or Object
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+      editorial revisions, annotations, elaborations, or other modifications
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diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_bus.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_bus.h
index 89824845..acc9d165 100644
--- a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_bus.h
+++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_bus.h
@@ -1,6832 +1,6832 @@
-/**
-  ******************************************************************************
-  * @file    stm32h7xx_ll_bus.h
-  * @author  MCD Application Team
-  * @brief   Header file of BUS LL module.
-
-  @verbatim
-                      ##### RCC Limitations #####
-  ==============================================================================
-    [..]
-      A delay between an RCC peripheral clock enable and the effective peripheral
-      enabling should be taken into account in order to manage the peripheral read/write
-      from/to registers.
-      (+) This delay depends on the peripheral mapping.
-        (++) AHB & APB peripherals, 1 dummy read is necessary
-
-    [..]
-      Workarounds:
-      (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
-          inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file in
-  * the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32H7xx_LL_BUS_H
-#define STM32H7xx_LL_BUS_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx.h"
-
-/** @addtogroup STM32H7xx_LL_Driver
-  * @{
-  */
-
-#if defined(RCC)
-
-/** @defgroup BUS_LL BUS
-  * @{
-  */
-
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-
-/* Private macros ------------------------------------------------------------*/
-
-/* Exported types ------------------------------------------------------------*/
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
-  * @{
-  */
-
-/** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH  AHB3 GRP1 PERIPH
-  * @{
-  */
-#define LL_AHB3_GRP1_PERIPH_MDMA           RCC_AHB3ENR_MDMAEN
-#define LL_AHB3_GRP1_PERIPH_DMA2D          RCC_AHB3ENR_DMA2DEN
-
-#if defined(JPEG)
-#define LL_AHB3_GRP1_PERIPH_JPGDEC         RCC_AHB3ENR_JPGDECEN
-#endif /* JPEG */
-
-#define LL_AHB3_GRP1_PERIPH_FMC            RCC_AHB3ENR_FMCEN
-#if defined(QUADSPI)
-#define LL_AHB3_GRP1_PERIPH_QSPI           RCC_AHB3ENR_QSPIEN
-#endif /* QUADSPI */
-#if defined(OCTOSPI1) || defined(OCTOSPI2)
-#define LL_AHB3_GRP1_PERIPH_OSPI1          RCC_AHB3ENR_OSPI1EN
-#define LL_AHB3_GRP1_PERIPH_OSPI2          RCC_AHB3ENR_OSPI2EN
-#endif /*(OCTOSPI1) || (OCTOSPI2)*/
-#if defined(OCTOSPIM)
-#define LL_AHB3_GRP1_PERIPH_OCTOSPIM       RCC_AHB3ENR_IOMNGREN
-#endif /* OCTOSPIM */
-#if defined(OTFDEC1) || defined(OTFDEC2)
-#define LL_AHB3_GRP1_PERIPH_OTFDEC1        RCC_AHB3ENR_OTFDEC1EN
-#define LL_AHB3_GRP1_PERIPH_OTFDEC2        RCC_AHB3ENR_OTFDEC2EN
-#endif /* (OTFDEC1) || (OTFDEC2) */
-#if defined(GFXMMU)
-#define LL_AHB3_GRP1_PERIPH_GFXMMU         RCC_AHB3ENR_GFXMMUEN
-#endif /* GFXMMU */
-#define LL_AHB3_GRP1_PERIPH_SDMMC1         RCC_AHB3ENR_SDMMC1EN
-#define LL_AHB3_GRP1_PERIPH_FLASH          RCC_AHB3LPENR_FLASHLPEN
-#define LL_AHB3_GRP1_PERIPH_DTCM1          RCC_AHB3LPENR_DTCM1LPEN
-#define LL_AHB3_GRP1_PERIPH_DTCM2          RCC_AHB3LPENR_DTCM2LPEN
-#define LL_AHB3_GRP1_PERIPH_ITCM           RCC_AHB3LPENR_ITCMLPEN
-#if defined(RCC_AHB3LPENR_AXISRAMLPEN)
-#define LL_AHB3_GRP1_PERIPH_AXISRAM        RCC_AHB3LPENR_AXISRAMLPEN
-#else
-#define LL_AHB3_GRP1_PERIPH_AXISRAM1       RCC_AHB3LPENR_AXISRAM1LPEN
-#define LL_AHB3_GRP1_PERIPH_AXISRAM        LL_AHB3_GRP1_PERIPH_AXISRAM1   /* for backward compatibility*/
-#endif /* RCC_AHB3LPENR_AXISRAMLPEN */
-#if defined(CD_AXISRAM2_BASE)
-#define LL_AHB3_GRP1_PERIPH_AXISRAM2       RCC_AHB3LPENR_AXISRAM2LPEN
-#endif /* CD_AXISRAM2_BASE */
-#if defined(CD_AXISRAM3_BASE)
-#define LL_AHB3_GRP1_PERIPH_AXISRAM3       RCC_AHB3LPENR_AXISRAM3LPEN
-#endif /* CD_AXISRAM3_BASE */
-/**
-  * @}
-  */
-
-
-/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH  AHB1 GRP1 PERIPH
-  * @{
-  */
-#define LL_AHB1_GRP1_PERIPH_DMA1           RCC_AHB1ENR_DMA1EN
-#define LL_AHB1_GRP1_PERIPH_DMA2           RCC_AHB1ENR_DMA2EN
-#define LL_AHB1_GRP1_PERIPH_ADC12          RCC_AHB1ENR_ADC12EN
-#if defined(DUAL_CORE)
-#define LL_AHB1_GRP1_PERIPH_ART            RCC_AHB1ENR_ARTEN
-#endif /* DUAL_CORE */
-#if defined(RCC_AHB1ENR_CRCEN)
-#define LL_AHB1_GRP1_PERIPH_CRC            RCC_AHB1ENR_CRCEN
-#endif /* RCC_AHB1ENR_CRCEN */
-#if defined(ETH)
-#define LL_AHB1_GRP1_PERIPH_ETH1MAC        RCC_AHB1ENR_ETH1MACEN
-#define LL_AHB1_GRP1_PERIPH_ETH1TX         RCC_AHB1ENR_ETH1TXEN
-#define LL_AHB1_GRP1_PERIPH_ETH1RX         RCC_AHB1ENR_ETH1RXEN
-#endif /* ETH */
-#define LL_AHB1_GRP1_PERIPH_USB1OTGHS      RCC_AHB1ENR_USB1OTGHSEN
-#define LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI  RCC_AHB1ENR_USB1OTGHSULPIEN
-#if defined(USB2_OTG_FS)
-#define LL_AHB1_GRP1_PERIPH_USB2OTGHS      RCC_AHB1ENR_USB2OTGHSEN
-#define LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI  RCC_AHB1ENR_USB2OTGHSULPIEN
-#endif /* USB2_OTG_FS */
-/**
-  * @}
-  */
-
-
-/** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH  AHB2 GRP1 PERIPH
-  * @{
-  */
-#define LL_AHB2_GRP1_PERIPH_DCMI           RCC_AHB2ENR_DCMIEN
-#if defined(HSEM) && defined(RCC_AHB2ENR_HSEMEN)
-#define LL_AHB2_GRP1_PERIPH_HSEM           RCC_AHB2ENR_HSEMEN
-#endif /* HSEM && RCC_AHB2ENR_HSEMEN */
-#if defined(CRYP)
-#define LL_AHB2_GRP1_PERIPH_CRYP           RCC_AHB2ENR_CRYPEN
-#endif /* CRYP */
-#if defined(HASH)
-#define LL_AHB2_GRP1_PERIPH_HASH           RCC_AHB2ENR_HASHEN
-#endif /* HASH */
-#define LL_AHB2_GRP1_PERIPH_RNG            RCC_AHB2ENR_RNGEN
-#define LL_AHB2_GRP1_PERIPH_SDMMC2         RCC_AHB2ENR_SDMMC2EN
-#if defined(FMAC)
-#define LL_AHB2_GRP1_PERIPH_FMAC           RCC_AHB2ENR_FMACEN
-#endif /* FMAC */
-#if defined(CORDIC)
-#define LL_AHB2_GRP1_PERIPH_CORDIC         RCC_AHB2ENR_CORDICEN
-#endif /* CORDIC */
-#if defined(BDMA1)
-#define LL_AHB2_GRP1_PERIPH_BDMA1          RCC_AHB2ENR_BDMA1EN
-#endif /* BDMA1 */
-#if defined(RCC_AHB2ENR_D2SRAM1EN)
-#define LL_AHB2_GRP1_PERIPH_D2SRAM1        RCC_AHB2ENR_D2SRAM1EN
-#else
-#define LL_AHB2_GRP1_PERIPH_AHBSRAM1       RCC_AHB2ENR_AHBSRAM1EN
-#define LL_AHB2_GRP1_PERIPH_D2SRAM1        LL_AHB2_GRP1_PERIPH_AHBSRAM1    /* for backward compatibility*/
-#endif /* RCC_AHB2ENR_D2SRAM1EN */
-#if defined(RCC_AHB2ENR_D2SRAM2EN)
-#define LL_AHB2_GRP1_PERIPH_D2SRAM2        RCC_AHB2ENR_D2SRAM2EN
-#else
-#define LL_AHB2_GRP1_PERIPH_AHBSRAM2       RCC_AHB2ENR_AHBSRAM2EN
-#define LL_AHB2_GRP1_PERIPH_D2SRAM2        LL_AHB2_GRP1_PERIPH_AHBSRAM2    /* for backward compatibility*/
-#endif /* RCC_AHB2ENR_D2SRAM2EN */
-#if defined(RCC_AHB2ENR_D2SRAM3EN)
-#define LL_AHB2_GRP1_PERIPH_D2SRAM3        RCC_AHB2ENR_D2SRAM3EN
-#endif /* RCC_AHB2ENR_D2SRAM3EN */
-/**
-  * @}
-  */
-
-
-/** @defgroup BUS_LL_EC_AHB4_GRP1_PERIPH  AHB4 GRP1 PERIPH
-  * @{
-  */
-#define LL_AHB4_GRP1_PERIPH_GPIOA          RCC_AHB4ENR_GPIOAEN
-#define LL_AHB4_GRP1_PERIPH_GPIOB          RCC_AHB4ENR_GPIOBEN
-#define LL_AHB4_GRP1_PERIPH_GPIOC          RCC_AHB4ENR_GPIOCEN
-#define LL_AHB4_GRP1_PERIPH_GPIOD          RCC_AHB4ENR_GPIODEN
-#define LL_AHB4_GRP1_PERIPH_GPIOE          RCC_AHB4ENR_GPIOEEN
-#define LL_AHB4_GRP1_PERIPH_GPIOF          RCC_AHB4ENR_GPIOFEN
-#define LL_AHB4_GRP1_PERIPH_GPIOG          RCC_AHB4ENR_GPIOGEN
-#define LL_AHB4_GRP1_PERIPH_GPIOH          RCC_AHB4ENR_GPIOHEN
-#if defined(GPIOI)
-#define LL_AHB4_GRP1_PERIPH_GPIOI          RCC_AHB4ENR_GPIOIEN
-#endif /* GPIOI */
-#define LL_AHB4_GRP1_PERIPH_GPIOJ          RCC_AHB4ENR_GPIOJEN
-#define LL_AHB4_GRP1_PERIPH_GPIOK          RCC_AHB4ENR_GPIOKEN
-#if defined(RCC_AHB4ENR_CRCEN)
-#define LL_AHB4_GRP1_PERIPH_CRC            RCC_AHB4ENR_CRCEN
-#endif /* RCC_AHB4ENR_CRCEN */
-#if defined(BDMA2)
-#define LL_AHB4_GRP1_PERIPH_BDMA2          RCC_AHB4ENR_BDMA2EN
-#define LL_AHB4_GRP1_PERIPH_BDMA           LL_AHB4_GRP1_PERIPH_BDMA2  /* for backward compatibility*/
-#else
-#define LL_AHB4_GRP1_PERIPH_BDMA           RCC_AHB4ENR_BDMAEN
-#endif /* BDMA2 */
-#if defined(ADC3)
-#define LL_AHB4_GRP1_PERIPH_ADC3           RCC_AHB4ENR_ADC3EN
-#endif /* ADC3 */
-#if defined(HSEM) && defined(RCC_AHB4ENR_HSEMEN)
-#define LL_AHB4_GRP1_PERIPH_HSEM           RCC_AHB4ENR_HSEMEN
-#endif /* HSEM && RCC_AHB4ENR_HSEMEN*/
-#define LL_AHB4_GRP1_PERIPH_BKPRAM         RCC_AHB4ENR_BKPRAMEN
-#if defined(RCC_AHB4LPENR_SRAM4LPEN)
-#define LL_AHB4_GRP1_PERIPH_SRAM4          RCC_AHB4LPENR_SRAM4LPEN
-#define LL_AHB4_GRP1_PERIPH_D3SRAM1        LL_AHB4_GRP1_PERIPH_SRAM4
-#else
-#define LL_AHB4_GRP1_PERIPH_SRDSRAM        RCC_AHB4ENR_SRDSRAMEN
-#define LL_AHB4_GRP1_PERIPH_SRAM4          LL_AHB4_GRP1_PERIPH_SRDSRAM  /* for backward compatibility*/
-#define LL_AHB4_GRP1_PERIPH_D3SRAM1        LL_AHB4_GRP1_PERIPH_SRDSRAM  /* for backward compatibility*/
-#endif /* RCC_AHB4ENR_D3SRAM1EN */
-/**
-  * @}
-  */
-
-
-/** @defgroup BUS_LL_EC_APB3_GRP1_PERIPH  APB3 GRP1 PERIPH
-  * @{
-  */
-#if defined(LTDC)
-#define LL_APB3_GRP1_PERIPH_LTDC           RCC_APB3ENR_LTDCEN
-#endif /* LTDC */
-#if defined(DSI)
-#define LL_APB3_GRP1_PERIPH_DSI            RCC_APB3ENR_DSIEN
-#endif /* DSI */
-#define LL_APB3_GRP1_PERIPH_WWDG1          RCC_APB3ENR_WWDG1EN
-#if defined(RCC_APB3ENR_WWDGEN)
-#define LL_APB3_GRP1_PERIPH_WWDG           LL_APB3_GRP1_PERIPH_WWDG1   /* for backward compatibility*/
-#endif
-/**
-  * @}
-  */
-
-
-/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH  APB1 GRP1 PERIPH
-  * @{
-  */
-#define LL_APB1_GRP1_PERIPH_TIM2           RCC_APB1LENR_TIM2EN
-#define LL_APB1_GRP1_PERIPH_TIM3           RCC_APB1LENR_TIM3EN
-#define LL_APB1_GRP1_PERIPH_TIM4           RCC_APB1LENR_TIM4EN
-#define LL_APB1_GRP1_PERIPH_TIM5           RCC_APB1LENR_TIM5EN
-#define LL_APB1_GRP1_PERIPH_TIM6           RCC_APB1LENR_TIM6EN
-#define LL_APB1_GRP1_PERIPH_TIM7           RCC_APB1LENR_TIM7EN
-#define LL_APB1_GRP1_PERIPH_TIM12          RCC_APB1LENR_TIM12EN
-#define LL_APB1_GRP1_PERIPH_TIM13          RCC_APB1LENR_TIM13EN
-#define LL_APB1_GRP1_PERIPH_TIM14          RCC_APB1LENR_TIM14EN
-#define LL_APB1_GRP1_PERIPH_LPTIM1         RCC_APB1LENR_LPTIM1EN
-#if defined(DUAL_CORE)
-#define LL_APB1_GRP1_PERIPH_WWDG2          RCC_APB1LENR_WWDG2EN
-#endif /*DUAL_CORE*/
-#define LL_APB1_GRP1_PERIPH_SPI2           RCC_APB1LENR_SPI2EN
-#define LL_APB1_GRP1_PERIPH_SPI3           RCC_APB1LENR_SPI3EN
-#define LL_APB1_GRP1_PERIPH_SPDIFRX        RCC_APB1LENR_SPDIFRXEN
-#define LL_APB1_GRP1_PERIPH_USART2         RCC_APB1LENR_USART2EN
-#define LL_APB1_GRP1_PERIPH_USART3         RCC_APB1LENR_USART3EN
-#define LL_APB1_GRP1_PERIPH_UART4          RCC_APB1LENR_UART4EN
-#define LL_APB1_GRP1_PERIPH_UART5          RCC_APB1LENR_UART5EN
-#define LL_APB1_GRP1_PERIPH_I2C1           RCC_APB1LENR_I2C1EN
-#define LL_APB1_GRP1_PERIPH_I2C2           RCC_APB1LENR_I2C2EN
-#define LL_APB1_GRP1_PERIPH_I2C3           RCC_APB1LENR_I2C3EN
-#if defined(I2C5)
-#define LL_APB1_GRP1_PERIPH_I2C5           RCC_APB1LENR_I2C5EN
-#endif /* I2C5 */
-#if defined(RCC_APB1LENR_CECEN)
-#define LL_APB1_GRP1_PERIPH_CEC            RCC_APB1LENR_CECEN
-#else
-#define LL_APB1_GRP1_PERIPH_HDMICEC        RCC_APB1LENR_HDMICECEN
-#define LL_APB1_GRP1_PERIPH_CEC            LL_APB1_GRP1_PERIPH_HDMICEC   /* for backward compatibility*/
-#endif /* RCC_APB1LENR_CECEN */
-#define LL_APB1_GRP1_PERIPH_DAC12          RCC_APB1LENR_DAC12EN
-#define LL_APB1_GRP1_PERIPH_UART7          RCC_APB1LENR_UART7EN
-#define LL_APB1_GRP1_PERIPH_UART8          RCC_APB1LENR_UART8EN
-/**
-  * @}
-  */
-
-
-/** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH  APB1 GRP2 PERIPH
-  * @{
-  */
-#define LL_APB1_GRP2_PERIPH_CRS            RCC_APB1HENR_CRSEN
-#define LL_APB1_GRP2_PERIPH_SWPMI1         RCC_APB1HENR_SWPMIEN
-#define LL_APB1_GRP2_PERIPH_OPAMP          RCC_APB1HENR_OPAMPEN
-#define LL_APB1_GRP2_PERIPH_MDIOS          RCC_APB1HENR_MDIOSEN
-#define LL_APB1_GRP2_PERIPH_FDCAN          RCC_APB1HENR_FDCANEN
-#if defined(TIM23)
-#define LL_APB1_GRP2_PERIPH_TIM23          RCC_APB1HENR_TIM23EN
-#endif /* TIM23 */
-#if defined(TIM24)
-#define LL_APB1_GRP2_PERIPH_TIM24          RCC_APB1HENR_TIM24EN
-#endif /* TIM24 */
-/**
-  * @}
-  */
-
-
-/** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH  APB2 GRP1 PERIPH
-  * @{
-  */
-#define LL_APB2_GRP1_PERIPH_TIM1           RCC_APB2ENR_TIM1EN
-#define LL_APB2_GRP1_PERIPH_TIM8           RCC_APB2ENR_TIM8EN
-#define LL_APB2_GRP1_PERIPH_USART1         RCC_APB2ENR_USART1EN
-#define LL_APB2_GRP1_PERIPH_USART6         RCC_APB2ENR_USART6EN
-#if defined(UART9)
-#define LL_APB2_GRP1_PERIPH_UART9          RCC_APB2ENR_UART9EN
-#endif /* UART9 */
-#if defined(USART10)
-#define LL_APB2_GRP1_PERIPH_USART10        RCC_APB2ENR_USART10EN
-#endif /* USART10 */
-#define LL_APB2_GRP1_PERIPH_SPI1           RCC_APB2ENR_SPI1EN
-#define LL_APB2_GRP1_PERIPH_SPI4           RCC_APB2ENR_SPI4EN
-#define LL_APB2_GRP1_PERIPH_TIM15          RCC_APB2ENR_TIM15EN
-#define LL_APB2_GRP1_PERIPH_TIM16          RCC_APB2ENR_TIM16EN
-#define LL_APB2_GRP1_PERIPH_TIM17          RCC_APB2ENR_TIM17EN
-#define LL_APB2_GRP1_PERIPH_SPI5           RCC_APB2ENR_SPI5EN
-#define LL_APB2_GRP1_PERIPH_SAI1           RCC_APB2ENR_SAI1EN
-#if defined(SAI2)
-#define LL_APB2_GRP1_PERIPH_SAI2           RCC_APB2ENR_SAI2EN
-#endif /* SAI2 */
-#if defined(SAI3)
-#define LL_APB2_GRP1_PERIPH_SAI3           RCC_APB2ENR_SAI3EN
-#endif /* SAI3 */
-#define LL_APB2_GRP1_PERIPH_DFSDM1         RCC_APB2ENR_DFSDM1EN
-#if defined(HRTIM1)
-#define LL_APB2_GRP1_PERIPH_HRTIM          RCC_APB2ENR_HRTIMEN
-#endif /* HRTIM1 */
-/**
-  * @}
-  */
-
-
-/** @defgroup BUS_LL_EC_APB4_GRP1_PERIPH  APB4 GRP1 PERIPH
-  * @{
-  */
-#define LL_APB4_GRP1_PERIPH_SYSCFG         RCC_APB4ENR_SYSCFGEN
-#define LL_APB4_GRP1_PERIPH_LPUART1        RCC_APB4ENR_LPUART1EN
-#define LL_APB4_GRP1_PERIPH_SPI6           RCC_APB4ENR_SPI6EN
-#define LL_APB4_GRP1_PERIPH_I2C4           RCC_APB4ENR_I2C4EN
-#define LL_APB4_GRP1_PERIPH_LPTIM2         RCC_APB4ENR_LPTIM2EN
-#define LL_APB4_GRP1_PERIPH_LPTIM3         RCC_APB4ENR_LPTIM3EN
-#if defined(LPTIM4)
-#define LL_APB4_GRP1_PERIPH_LPTIM4         RCC_APB4ENR_LPTIM4EN
-#endif /* LPTIM4 */
-#if defined(LPTIM5)
-#define LL_APB4_GRP1_PERIPH_LPTIM5         RCC_APB4ENR_LPTIM5EN
-#endif /* LPTIM5 */
-#if defined(DAC2)
-#define LL_APB4_GRP1_PERIPH_DAC2           RCC_APB4ENR_DAC2EN
-#endif /* DAC2 */
-#define LL_APB4_GRP1_PERIPH_COMP12         RCC_APB4ENR_COMP12EN
-#define LL_APB4_GRP1_PERIPH_VREF           RCC_APB4ENR_VREFEN
-#define LL_APB4_GRP1_PERIPH_RTCAPB         RCC_APB4ENR_RTCAPBEN
-#if defined(SAI4)
-#define LL_APB4_GRP1_PERIPH_SAI4           RCC_APB4ENR_SAI4EN
-#endif /* SAI4 */
-#if defined(DTS)
-#define LL_APB4_GRP1_PERIPH_DTS            RCC_APB4ENR_DTSEN
-#endif /*DTS*/
-#if defined(DFSDM2_BASE)
-#define LL_APB4_GRP1_PERIPH_DFSDM2         RCC_APB4ENR_DFSDM2EN
-#endif /* DFSDM2_BASE */
-/**
-  * @}
-  */
-
-/** @defgroup BUS_LL_EC_CLKAM_PERIPH  CLKAM PERIPH
-  * @{
-  */
-#if defined(RCC_D3AMR_BDMAAMEN)
-#define LL_CLKAM_PERIPH_BDMA          RCC_D3AMR_BDMAAMEN
-#else
-#define LL_CLKAM_PERIPH_BDMA2         RCC_SRDAMR_BDMA2AMEN
-#define LL_CLKAM_PERIPH_BDMA   LL_CLKAM_PERIPH_BDMA2 /* for backward compatibility*/
-#endif /* RCC_D3AMR_BDMAAMEN */
-#if defined(RCC_SRDAMR_GPIOAMEN)
-#define LL_CLKAM_PERIPH_GPIO          RCC_SRDAMR_GPIOAMEN
-#endif /* RCC_SRDAMR_GPIOAMEN */
-#if defined(RCC_D3AMR_LPUART1AMEN)
-#define LL_CLKAM_PERIPH_LPUART1       RCC_D3AMR_LPUART1AMEN
-#else
-#define LL_CLKAM_PERIPH_LPUART1       RCC_SRDAMR_LPUART1AMEN
-#endif /* RCC_D3AMR_LPUART1AMEN */
-#if defined(RCC_D3AMR_SPI6AMEN)
-#define LL_CLKAM_PERIPH_SPI6          RCC_D3AMR_SPI6AMEN
-#else
-#define LL_CLKAM_PERIPH_SPI6          RCC_SRDAMR_SPI6AMEN
-#endif /* RCC_D3AMR_SPI6AMEN */
-#if defined(RCC_D3AMR_I2C4AMEN)
-#define LL_CLKAM_PERIPH_I2C4          RCC_D3AMR_I2C4AMEN
-#else
-#define LL_CLKAM_PERIPH_I2C4          RCC_SRDAMR_I2C4AMEN
-#endif /* RCC_D3AMR_I2C4AMEN */
-#if defined(RCC_D3AMR_LPTIM2AMEN)
-#define LL_CLKAM_PERIPH_LPTIM2        RCC_D3AMR_LPTIM2AMEN
-#else
-#define LL_CLKAM_PERIPH_LPTIM2        RCC_SRDAMR_LPTIM2AMEN
-#endif /* RCC_D3AMR_LPTIM2AMEN */
-#if defined(RCC_D3AMR_LPTIM3AMEN)
-#define LL_CLKAM_PERIPH_LPTIM3        RCC_D3AMR_LPTIM3AMEN
-#else
-#define LL_CLKAM_PERIPH_LPTIM3        RCC_SRDAMR_LPTIM3AMEN
-#endif /* RCC_D3AMR_LPTIM3AMEN */
-#if defined(RCC_D3AMR_LPTIM4AMEN)
-#define LL_CLKAM_PERIPH_LPTIM4        RCC_D3AMR_LPTIM4AMEN
-#endif /* RCC_D3AMR_LPTIM4AMEN */
-#if defined(RCC_D3AMR_LPTIM5AMEN)
-#define LL_CLKAM_PERIPH_LPTIM5        RCC_D3AMR_LPTIM5AMEN
-#endif /* RCC_D3AMR_LPTIM5AMEN */
-#if defined(DAC2)
-#define LL_CLKAM_PERIPH_DAC2          RCC_SRDAMR_DAC2AMEN
-#endif /* DAC2 */
-#if defined(RCC_D3AMR_COMP12AMEN)
-#define LL_CLKAM_PERIPH_COMP12        RCC_D3AMR_COMP12AMEN
-#else
-#define LL_CLKAM_PERIPH_COMP12        RCC_SRDAMR_COMP12AMEN
-#endif /* RCC_D3AMR_COMP12AMEN */
-#if defined(RCC_D3AMR_VREFAMEN)
-#define LL_CLKAM_PERIPH_VREF          RCC_D3AMR_VREFAMEN
-#else
-#define LL_CLKAM_PERIPH_VREF          RCC_SRDAMR_VREFAMEN
-#endif /* RCC_D3AMR_VREFAMEN */
-#if defined(RCC_D3AMR_RTCAMEN)
-#define LL_CLKAM_PERIPH_RTC           RCC_D3AMR_RTCAMEN
-#else
-#define LL_CLKAM_PERIPH_RTC           RCC_SRDAMR_RTCAMEN
-#endif /* RCC_D3AMR_RTCAMEN */
-#if defined(RCC_D3AMR_CRCAMEN)
-#define LL_CLKAM_PERIPH_CRC           RCC_D3AMR_CRCAMEN
-#endif /* RCC_D3AMR_CRCAMEN */
-#if defined(SAI4)
-#define LL_CLKAM_PERIPH_SAI4          RCC_D3AMR_SAI4AMEN
-#endif /* SAI4 */
-#if defined(ADC3)
-#define LL_CLKAM_PERIPH_ADC3          RCC_D3AMR_ADC3AMEN
-#endif /* ADC3 */
-#if defined(RCC_SRDAMR_DTSAMEN)
-#define LL_CLKAM_PERIPH_DTS           RCC_SRDAMR_DTSAMEN
-#endif /* RCC_SRDAMR_DTSAMEN */
-#if defined(RCC_D3AMR_DTSAMEN)
-#define LL_CLKAM_PERIPH_DTS           RCC_D3AMR_DTSAMEN
-#endif /* RCC_D3AMR_DTSAMEN */
-#if defined(DFSDM2_BASE)
-#define LL_CLKAM_PERIPH_DFSDM2        RCC_SRDAMR_DFSDM2AMEN
-#endif /* DFSDM2_BASE */
-#if defined(RCC_D3AMR_BKPRAMAMEN)
-#define LL_CLKAM_PERIPH_BKPRAM        RCC_D3AMR_BKPRAMAMEN
-#else
-#define LL_CLKAM_PERIPH_BKPRAM        RCC_SRDAMR_BKPRAMAMEN
-#endif /* RCC_D3AMR_BKPRAMAMEN */
-#if defined(RCC_D3AMR_SRAM4AMEN)
-#define LL_CLKAM_PERIPH_SRAM4         RCC_D3AMR_SRAM4AMEN
-#else
-#define LL_CLKAM_PERIPH_SRDSRAM       RCC_SRDAMR_SRDSRAMAMEN
-#define LL_CLKAM_PERIPH_SRAM4         LL_CLKAM_PERIPH_SRDSRAM
-#endif /* RCC_D3AMR_SRAM4AMEN */
-/**
-  * @}
-  */
-
-#if defined(RCC_CKGAENR_AXICKG)
-/** @defgroup BUS_LL_EC_CKGA_PERIPH  CKGA (AXI Clocks Gating) PERIPH
-  * @{
-  */
-#define LL_CKGA_PERIPH_AXI            RCC_CKGAENR_AXICKG
-#define LL_CKGA_PERIPH_AHB            RCC_CKGAENR_AHBCKG
-#define LL_CKGA_PERIPH_CPU            RCC_CKGAENR_CPUCKG
-#define LL_CKGA_PERIPH_SDMMC          RCC_CKGAENR_SDMMCCKG
-#define LL_CKGA_PERIPH_MDMA           RCC_CKGAENR_MDMACKG
-#define LL_CKGA_PERIPH_DMA2D          RCC_CKGAENR_DMA2DCKG
-#define LL_CKGA_PERIPH_LTDC           RCC_CKGAENR_LTDCCKG
-#define LL_CKGA_PERIPH_GFXMMUM        RCC_CKGAENR_GFXMMUMCKG
-#define LL_CKGA_PERIPH_AHB12          RCC_CKGAENR_AHB12CKG
-#define LL_CKGA_PERIPH_AHB34          RCC_CKGAENR_AHB34CKG
-#define LL_CKGA_PERIPH_FLIFT          RCC_CKGAENR_FLIFTCKG
-#define LL_CKGA_PERIPH_OCTOSPI2       RCC_CKGAENR_OCTOSPI2CKG
-#define LL_CKGA_PERIPH_FMC            RCC_CKGAENR_FMCCKG
-#define LL_CKGA_PERIPH_OCTOSPI1       RCC_CKGAENR_OCTOSPI1CKG
-#define LL_CKGA_PERIPH_AXIRAM1        RCC_CKGAENR_AXIRAM1CKG
-#define LL_CKGA_PERIPH_AXIRAM2        RCC_CKGAENR_AXIRAM2CKG
-#define LL_CKGA_PERIPH_AXIRAM3        RCC_CKGAENR_AXIRAM3CKG
-#define LL_CKGA_PERIPH_GFXMMUS        RCC_CKGAENR_GFXMMUSCKG
-#define LL_CKGA_PERIPH_ECCRAM         RCC_CKGAENR_ECCRAMCKG
-#define LL_CKGA_PERIPH_EXTI           RCC_CKGAENR_EXTICKG
-#define LL_CKGA_PERIPH_JTAG           RCC_CKGAENR_JTAGCKG
-/**
-  * @}
-  */
-#endif /* RCC_CKGAENR_AXICKG */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
-  * @{
-  */
-
-/** @defgroup BUS_LL_EF_AHB3 AHB3
-  * @{
-  */
-
-/**
-  * @brief  Enable AHB3 peripherals clock.
-  * @rmtoll AHB3ENR      MDMAEN        LL_AHB3_GRP1_EnableClock\n
-  *         AHB3ENR      DMA2DEN       LL_AHB3_GRP1_EnableClock\n
-  *         AHB3ENR      JPGDECEN      LL_AHB3_GRP1_EnableClock\n
-  *         AHB3ENR      FMCEN         LL_AHB3_GRP1_EnableClock\n
-  *         AHB3ENR      QSPIEN        LL_AHB3_GRP1_EnableClock\n  (*)
-  *         AHB3ENR      OSPI1EN       LL_AHB3_GRP1_EnableClock\n  (*)
-  *         AHB3ENR      OSPI2EN       LL_AHB3_GRP1_EnableClock\n  (*)
-  *         AHB3ENR      IOMNGREN      LL_AHB3_GRP1_EnableClock\n  (*)
-  *         AHB3ENR      OTFDEC1EN     LL_AHB3_GRP1_EnableClock\n  (*)
-  *         AHB3ENR      OTFDEC2EN     LL_AHB3_GRP1_EnableClock\n  (*)
-  *         AHB3ENR      GFXMMU        LL_AHB3_GRP1_EnableClock\n  (*)
-  *         AHB3ENR      SDMMC1EN      LL_AHB3_GRP1_EnableClock\n
-  *         AHB3ENR      FLASHEN       LL_AHB3_GRP1_EnableClock\n  (*)
-  *         AHB3ENR      DTCM1EN       LL_AHB3_GRP1_EnableClock\n  (*)
-  *         AHB3ENR      DTCM2EN       LL_AHB3_GRP1_EnableClock\n  (*)
-  *         AHB3ENR      ITCMEN        LL_AHB3_GRP1_EnableClock\n  (*)
-  *         AHB3ENR      AXISRAMEN     LL_AHB3_GRP1_EnableClock    (*)
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC->AHB3ENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->AHB3ENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Check if AHB3 peripheral clock is enabled or not
-  * @rmtoll AHB3ENR      MDMAEN        LL_AHB3_GRP1_IsEnabledClock\n
-  *         AHB3ENR      DMA2DEN       LL_AHB3_GRP1_IsEnabledClock\n
-  *         AHB3ENR      JPGDECEN      LL_AHB3_GRP1_IsEnabledClock\n
-  *         AHB3ENR      FMCEN         LL_AHB3_GRP1_IsEnabledClock\n
-  *         AHB3ENR      QSPIEN        LL_AHB3_GRP1_IsEnabledClock\n (*)
-  *         AHB3ENR      OSPI1EN       LL_AHB3_GRP1_IsEnabledClock\n (*)
-  *         AHB3ENR      OSPI2EN       LL_AHB3_GRP1_IsEnabledClock\n (*)
-  *         AHB3ENR      IOMNGREN      LL_AHB3_GRP1_IsEnabledClock\n (*)
-  *         AHB3ENR      OTFDEC1EN     LL_AHB3_GRP1_IsEnabledClock\n (*)
-  *         AHB3ENR      OTFDEC2EN     LL_AHB3_GRP1_IsEnabledClock\n (*)
-  *         AHB3ENR      GFXMMU        LL_AHB3_GRP1_IsEnabledClock\n (*)
-  *         AHB3ENR      SDMMC1EN      LL_AHB3_GRP1_IsEnabledClock\n
-  *         AHB3ENR      FLASHEN       LL_AHB3_GRP1_IsEnabledClock\n (*)
-  *         AHB3ENR      DTCM1EN       LL_AHB3_GRP1_IsEnabledClock\n (*)
-  *         AHB3ENR      DTCM2EN       LL_AHB3_GRP1_IsEnabledClock\n (*)
-  *         AHB3ENR      ITCMEN        LL_AHB3_GRP1_IsEnabledClock\n (*)
-  *         AHB3ENR      AXISRAMEN     LL_AHB3_GRP1_IsEnabledClock   (*)
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI    (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1   (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2   (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM  (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU  (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
-  *
-  *         (*) value not defined in all devices.
-  * @retval uint32_t
-*/
-__STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
-{
-  return ((READ_BIT(RCC->AHB3ENR, Periphs) == Periphs)?1U:0U);
-}
-
-/**
-  * @brief  Disable AHB3 peripherals clock.
-  * @rmtoll AHB3ENR      MDMAEN        LL_AHB3_GRP1_DisableClock\n
-  *         AHB3ENR      DMA2DEN       LL_AHB3_GRP1_DisableClock\n
-  *         AHB3ENR      JPGDECEN      LL_AHB3_GRP1_DisableClock\n
-  *         AHB3ENR      FMCEN         LL_AHB3_GRP1_DisableClock\n
-  *         AHB3ENR      QSPIEN        LL_AHB3_GRP1_DisableClock\n (*)
-  *         AHB3ENR      OSPI1EN       LL_AHB3_GRP1_DisableClock\n (*)
-  *         AHB3ENR      OSPI2EN       LL_AHB3_GRP1_DisableClock\n (*)
-  *         AHB3ENR      IOMNGREN      LL_AHB3_GRP1_DisableClock\n (*)
-  *         AHB3ENR      OTFDEC1EN     LL_AHB3_GRP1_DisableClock\n (*)
-  *         AHB3ENR      OTFDEC2EN     LL_AHB3_GRP1_DisableClock\n (*)
-  *         AHB3ENR      GFXMMU        LL_AHB3_GRP1_DisableClock\n (*)
-  *         AHB3ENR      SDMMC1EN      LL_AHB3_GRP1_DisableClock\n (*)
-  *         AHB3ENR      FLASHEN       LL_AHB3_GRP1_DisableClock\n (*)
-  *         AHB3ENR      DTCM1EN       LL_AHB3_GRP1_DisableClock\n (*)
-  *         AHB3ENR      DTCM2EN       LL_AHB3_GRP1_DisableClock\n (*)
-  *         AHB3ENR      ITCMEN        LL_AHB3_GRP1_DisableClock\n (*)
-  *         AHB3ENR      AXISRAMEN     LL_AHB3_GRP1_DisableClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI  (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1   (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2   (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM  (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU  (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->AHB3ENR, Periphs);
-}
-
-/**
-  * @brief  Force AHB3 peripherals reset.
-  * @rmtoll AHB3RSTR     MDMARST       LL_AHB3_GRP1_ForceReset\n
-  *         AHB3RSTR     DMA2DRST      LL_AHB3_GRP1_ForceReset\n
-  *         AHB3RSTR     JPGDECRST     LL_AHB3_GRP1_ForceReset\n
-  *         AHB3RSTR     FMCRST        LL_AHB3_GRP1_ForceReset\n 
-  *         AHB3RSTR     QSPIRST       LL_AHB3_GRP1_ForceReset\n (*)
-  *         AHB3RSTR     OSPI1RST      LL_AHB3_GRP1_ForceReset\n (*)
-  *         AHB3RSTR     OSPI2RST      LL_AHB3_GRP1_ForceReset\n (*)
-  *         AHB3RSTR     IOMNGRRST     LL_AHB3_GRP1_ForceReset\n (*)
-  *         AHB3RSTR     OTFDEC1RST    LL_AHB3_GRP1_ForceReset\n (*)
-  *         AHB3RSTR     OTFDEC2RST    LL_AHB3_GRP1_ForceReset\n (*)
-  *         AHB3RSTR     GFXMMURST     LL_AHB3_GRP1_ForceReset\n (*)
-  *         AHB3RSTR     SDMMC1RST     LL_AHB3_GRP1_ForceReset
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU  (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs)
-{
-  SET_BIT(RCC->AHB3RSTR, Periphs);
-}
-
-/**
-  * @brief  Release AHB3 peripherals reset.
-  * @rmtoll AHB3RSTR     MDMARST       LL_AHB3_GRP1_ReleaseReset\n
-  *         AHB3RSTR     DMA2DRST      LL_AHB3_GRP1_ReleaseReset\n
-  *         AHB3RSTR     JPGDECRST     LL_AHB3_GRP1_ReleaseReset\n
-  *         AHB3RSTR     FMCRST        LL_AHB3_GRP1_ReleaseReset\n
-  *         AHB3RSTR     QSPIRST       LL_AHB3_GRP1_ReleaseReset\n
-  *         AHB3RSTR     OSPI1RST      LL_AHB3_GRP1_ReleaseReset\n (*)
-  *         AHB3RSTR     OSPI2RST      LL_AHB3_GRP1_ReleaseReset\n (*)
-  *         AHB3RSTR     IOMNGRRST     LL_AHB3_GRP1_ReleaseReset\n (*)
-  *         AHB3RSTR     OTFDEC1RST    LL_AHB3_GRP1_ReleaseReset\n (*)
-  *         AHB3RSTR     OTFDEC2RST    LL_AHB3_GRP1_ReleaseReset\n (*)
-  *         AHB3RSTR     GFXMMURST     LL_AHB3_GRP1_ReleaseReset\n (*)
-  *         AHB3RSTR     SDMMC1RST     LL_AHB3_GRP1_ReleaseReset
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1    (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2    (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU  (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->AHB3RSTR, Periphs);
-}
-
-/**
-  * @brief  Enable AHB3 peripherals clock during Low Power (Sleep) mode.
-  * @rmtoll AHB3LPENR    MDMALPEN      LL_AHB3_GRP1_EnableClockSleep\n
-  *         AHB3LPENR    DMA2DLPEN     LL_AHB3_GRP1_EnableClockSleep\n
-  *         AHB3LPENR    JPGDECLPEN    LL_AHB3_GRP1_EnableClockSleep\n
-  *         AHB3LPENR    FMCLPEN       LL_AHB3_GRP1_EnableClockSleep\n
-  *         AHB3LPENR    QSPILPEN      LL_AHB3_GRP1_EnableClockSleep\n  (*)
-  *         AHB3LPENR    OSPI1LPEN     LL_AHB3_GRP1_EnableClockSleep\n  (*)
-  *         AHB3LPENR    OSPI2LPEN     LL_AHB3_GRP1_EnableClockSleep\n  (*)
-  *         AHB3LPENR    IOMNGRLPEN    LL_AHB3_GRP1_EnableClockSleep\n  (*)
-  *         AHB3LPENR    OTFDEC1LPEN   LL_AHB3_GRP1_EnableClockSleep\n  (*)
-  *         AHB3LPENR    OTFDEC1LPEN   LL_AHB3_GRP1_EnableClockSleep\n  (*)
-  *         AHB3LPENR    GFXMMULPEN    LL_AHB3_GRP1_EnableClockSleep\n  (*)
-  *         AHB3LPENR    SDMMC1LPEN    LL_AHB3_GRP1_EnableClockSleep\n
-  *         AHB3LPENR    FLASHLPEN     LL_AHB3_GRP1_EnableClockSleep\n
-  *         AHB3LPENR    DTCM1LPEN     LL_AHB3_GRP1_EnableClockSleep\n
-  *         AHB3LPENR    DTCM2LPEN     LL_AHB3_GRP1_EnableClockSleep\n
-  *         AHB3LPENR    ITCMLPEN      LL_AHB3_GRP1_EnableClockSleep\n
-  *         AHB3LPENR    AXISRAMLPEN   LL_AHB3_GRP1_EnableClockSleep
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI     (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1    (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2    (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU  (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_AHB3_GRP1_EnableClockSleep(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC->AHB3LPENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->AHB3LPENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Disable AHB3 peripherals clock during Low Power (Sleep) mode.
-  * @rmtoll AHB3LPENR    MDMALPEN      LL_AHB3_GRP1_DisableClockSleep\n
-  *         AHB3LPENR    DMA2DLPEN     LL_AHB3_GRP1_DisableClockSleep\n
-  *         AHB3LPENR    JPGDECLPEN    LL_AHB3_GRP1_DisableClockSleep\n
-  *         AHB3LPENR    FMCLPEN       LL_AHB3_GRP1_DisableClockSleep\n
-  *         AHB3LPENR    QSPILPEN      LL_AHB3_GRP1_DisableClockSleep\n
-  *         AHB3LPENR    OSPI1LPEN     LL_AHB3_GRP1_DisableClockSleep\n  (*)
-  *         AHB3LPENR    OSPI2LPEN     LL_AHB3_GRP1_DisableClockSleep\n  (*)
-  *         AHB3LPENR    IOMNGRLPEN    LL_AHB3_GRP1_DisableClockSleep\n  (*)
-  *         AHB3LPENR    OTFDEC1LPEN   LL_AHB3_GRP1_DisableClockSleep\n  (*)
-  *         AHB3LPENR    OTFDEC1LPEN   LL_AHB3_GRP1_DisableClockSleep\n  (*)
-  *         AHB3LPENR    GFXMMULPEN    LL_AHB3_GRP1_DisableClockSleep\n  (*)
-  *         AHB3LPENR    SDMMC1LPEN    LL_AHB3_GRP1_DisableClockSleep\n
-  *         AHB3LPENR    FLASHLPEN     LL_AHB3_GRP1_DisableClockSleep\n
-  *         AHB3LPENR    DTCM1LPEN     LL_AHB3_GRP1_DisableClockSleep\n
-  *         AHB3LPENR    DTCM2LPEN     LL_AHB3_GRP1_DisableClockSleep\n
-  *         AHB3LPENR    ITCMLPEN      LL_AHB3_GRP1_DisableClockSleep\n
-  *         AHB3LPENR    AXISRAMLPEN   LL_AHB3_GRP1_DisableClockSleep
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI     (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1    (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2    (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU  (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_AHB3_GRP1_DisableClockSleep(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->AHB3LPENR, Periphs);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup BUS_LL_EF_AHB1 AHB1
-  * @{
-  */
-
-/**
-  * @brief  Enable AHB1 peripherals clock.
-  * @rmtoll AHB1ENR      DMA1EN        LL_AHB1_GRP1_EnableClock\n
-  *         AHB1ENR      DMA2EN        LL_AHB1_GRP1_EnableClock\n
-  *         AHB1ENR      ADC12EN       LL_AHB1_GRP1_EnableClock\n
-  *         AHB1ENR      ARTEN         LL_AHB1_GRP1_EnableClock\n
-  *         AHB1ENR      CRCEN         LL_AHB1_GRP1_EnableClock\n (*)
-  *         AHB1ENR      ETH1MACEN     LL_AHB1_GRP1_EnableClock\n (*)
-  *         AHB1ENR      ETH1TXEN      LL_AHB1_GRP1_EnableClock\n (*)
-  *         AHB1ENR      ETH1RXEN      LL_AHB1_GRP1_EnableClock\n (*)
-  *         AHB1ENR      USB1OTGHSEN   LL_AHB1_GRP1_EnableClock\n
-  *         AHB1ENR      USB1OTGHSULPIEN  LL_AHB1_GRP1_EnableClock\n
-  *         AHB1ENR      USB2OTGHSEN   LL_AHB1_GRP1_EnableClock\n  (*)
-  *         AHB1ENR      USB2OTGHSULPIEN  LL_AHB1_GRP1_EnableClock (*)
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS  (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC->AHB1ENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->AHB1ENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Check if AHB1 peripheral clock is enabled or not
-  * @rmtoll AHB1ENR      DMA1EN        LL_AHB1_GRP1_IsEnabledClock\n
-  *         AHB1ENR      DMA2EN        LL_AHB1_GRP1_IsEnabledClock\n
-  *         AHB1ENR      ADC12EN       LL_AHB1_GRP1_IsEnabledClock\n
-  *         AHB1ENR      ARTEN         LL_AHB1_GRP1_IsEnabledClock\n (*)
-  *         AHB1ENR      CRCEN         LL_AHB1_GRP1_IsEnabledClock\n (*)
-  *         AHB1ENR      ETH1MACEN     LL_AHB1_GRP1_IsEnabledClock\n (*)
-  *         AHB1ENR      ETH1TXEN      LL_AHB1_GRP1_IsEnabledClock\n (*)
-  *         AHB1ENR      ETH1RXEN      LL_AHB1_GRP1_IsEnabledClock\n (*)
-  *         AHB1ENR      USB1OTGHSEN   LL_AHB1_GRP1_IsEnabledClock\n
-  *         AHB1ENR      USB1OTGHSULPIEN  LL_AHB1_GRP1_IsEnabledClock\n
-  *         AHB1ENR      USB2OTGHSEN   LL_AHB1_GRP1_IsEnabledClock\n  (*)
-  *         AHB1ENR      USB2OTGHSULPIEN  LL_AHB1_GRP1_IsEnabledClock (*)
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX  (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX  (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS     (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval uint32_t
-*/
-__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
-{
-  return ((READ_BIT(RCC->AHB1ENR, Periphs) == Periphs)?1U:0U);
-}
-
-/**
-  * @brief  Disable AHB1 peripherals clock.
-  * @rmtoll AHB1ENR      DMA1EN        LL_AHB1_GRP1_DisableClock\n
-  *         AHB1ENR      DMA2EN        LL_AHB1_GRP1_DisableClock\n
-  *         AHB1ENR      ADC12EN       LL_AHB1_GRP1_DisableClock\n
-  *         AHB1ENR      ARTEN         LL_AHB1_GRP1_DisableClock\n (*)
-  *         AHB1ENR      CRCEN         LL_AHB1_GRP1_DisableClock\n (*)
-  *         AHB1ENR      ETH1MACEN     LL_AHB1_GRP1_DisableClock\n (*)
-  *         AHB1ENR      ETH1TXEN      LL_AHB1_GRP1_DisableClock\n (*)
-  *         AHB1ENR      ETH1RXEN      LL_AHB1_GRP1_DisableClock\n (*)
-  *         AHB1ENR      USB1OTGHSEN   LL_AHB1_GRP1_DisableClock\n
-  *         AHB1ENR      USB1OTGHSULPIEN  LL_AHB1_GRP1_DisableClock\n
-  *         AHB1ENR      USB2OTGHSEN   LL_AHB1_GRP1_DisableClock\n  (*)
-  *         AHB1ENR      USB2OTGHSULPIEN  LL_AHB1_GRP1_DisableClock (*)
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX  (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX  (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS     (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->AHB1ENR, Periphs);
-}
-
-/**
-  * @brief  Force AHB1 peripherals reset.
-  * @rmtoll AHB1RSTR     DMA1RST       LL_AHB1_GRP1_ForceReset\n
-  *         AHB1RSTR     DMA2RST       LL_AHB1_GRP1_ForceReset\n
-  *         AHB1RSTR     ADC12RST      LL_AHB1_GRP1_ForceReset\n
-  *         AHB1RSTR     ARTRST        LL_AHB1_GRP1_ForceReset\n (*)
-  *         AHB1RSTR     CRCRST        LL_AHB1_GRP1_ForceReset\n (*)
-  *         AHB1RSTR     ETH1MACRST    LL_AHB1_GRP1_ForceReset\n (*)
-  *         AHB1RSTR     USB1OTGHSRST  LL_AHB1_GRP1_ForceReset\n
-  *         AHB1RSTR     USB2OTGHSRST  LL_AHB1_GRP1_ForceReset   (*)
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
-{
-  SET_BIT(RCC->AHB1RSTR, Periphs);
-}
-
-/**
-  * @brief  Release AHB1 peripherals reset.
-  * @rmtoll AHB1RSTR     DMA1RST       LL_AHB1_GRP1_ReleaseReset\n
-  *         AHB1RSTR     DMA2RST       LL_AHB1_GRP1_ReleaseReset\n
-  *         AHB1RSTR     ADC12RST      LL_AHB1_GRP1_ReleaseReset\n
-  *         AHB1RSTR     ARTRST        LL_AHB1_GRP1_ReleaseReset\n (*)
-  *         AHB1RSTR     CRCRST        LL_AHB1_GRP1_ReleaseReset\n (*)
-  *         AHB1RSTR     ETH1MACRST    LL_AHB1_GRP1_ReleaseReset\n (*)
-  *         AHB1RSTR     USB1OTGHSRST  LL_AHB1_GRP1_ReleaseReset\n
-  *         AHB1RSTR     USB2OTGHSRST  LL_AHB1_GRP1_ReleaseReset   (*)
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->AHB1RSTR, Periphs);
-}
-
-/**
-  * @brief  Enable AHB1 peripherals clock during Low Power (Sleep) mode.
-  * @rmtoll AHB1LPENR    DMA1LPEN      LL_AHB1_GRP1_EnableClockSleep\n
-  *         AHB1LPENR    DMA2LPEN      LL_AHB1_GRP1_EnableClockSleep\n
-  *         AHB1LPENR    ADC12LPEN     LL_AHB1_GRP1_EnableClockSleep\n
-  *         AHB1LPENR    ARTLPEN       LL_AHB1_GRP1_EnableClockSleep\n (*)
-  *         AHB1LPENR    CRCLPEN       LL_AHB1_GRP1_EnableClockSleep\n (*)
-  *         AHB1LPENR    ETH1MACLPEN   LL_AHB1_GRP1_EnableClockSleep\n (*)
-  *         AHB1LPENR    ETH1TXLPEN    LL_AHB1_GRP1_EnableClockSleep\n (*)
-  *         AHB1LPENR    ETH1RXLPEN    LL_AHB1_GRP1_EnableClockSleep\n
-  *         AHB1LPENR    USB1OTGHSLPEN  LL_AHB1_GRP1_EnableClockSleep\n
-  *         AHB1LPENR    USB1OTGHSULPILPEN  LL_AHB1_GRP1_EnableClockSleep\n
-  *         AHB1LPENR    USB2OTGHSLPEN  LL_AHB1_GRP1_EnableClockSleep\n   (*)
-  *         AHB1LPENR    USB2OTGHSULPILPEN  LL_AHB1_GRP1_EnableClockSleep (*)
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX  (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX  (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS     (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_AHB1_GRP1_EnableClockSleep(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC->AHB1LPENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->AHB1LPENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Disable AHB1 peripherals clock during Low Power (Sleep) mode.
-  * @rmtoll AHB1LPENR    DMA1LPEN      LL_AHB1_GRP1_DisableClockSleep\n
-  *         AHB1LPENR    DMA2LPEN      LL_AHB1_GRP1_DisableClockSleep\n
-  *         AHB1LPENR    ADC12LPEN     LL_AHB1_GRP1_DisableClockSleep\n
-  *         AHB1LPENR    ARTLPEN       LL_AHB1_GRP1_DisableClockSleep\n (*)
-  *         AHB1LPENR    CRCLPEN       LL_AHB1_GRP1_DisableClockSleep\n (*)
-  *         AHB1LPENR    ETH1MACLPEN   LL_AHB1_GRP1_DisableClockSleep\n (*)
-  *         AHB1LPENR    ETH1TXLPEN    LL_AHB1_GRP1_DisableClockSleep\n (*)
-  *         AHB1LPENR    ETH1RXLPEN    LL_AHB1_GRP1_DisableClockSleep\n (*)
-  *         AHB1LPENR    USB1OTGHSLPEN  LL_AHB1_GRP1_DisableClockSleep\n
-  *         AHB1LPENR    USB1OTGHSULPILPEN  LL_AHB1_GRP1_DisableClockSleep\n
-  *         AHB1LPENR    USB2OTGHSLPEN  LL_AHB1_GRP1_DisableClockSleep\n   (*)
-  *         AHB1LPENR    USB2OTGHSULPILPEN  LL_AHB1_GRP1_DisableClockSleep (*)
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX  (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX  (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS     (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_AHB1_GRP1_DisableClockSleep(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->AHB1LPENR, Periphs);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup BUS_LL_EF_AHB2 AHB2
-  * @{
-  */
-
-/**
-  * @brief  Enable AHB2 peripherals clock.
-  * @rmtoll AHB2ENR      DCMIEN        LL_AHB2_GRP1_EnableClock\n
-  *         AHB2ENR      HSEMEN        LL_AHB2_GRP1_EnableClock\n (*)
-  *         AHB2ENR      CRYPEN        LL_AHB2_GRP1_EnableClock\n (*)
-  *         AHB2ENR      HASHEN        LL_AHB2_GRP1_EnableClock\n (*)
-  *         AHB2ENR      RNGEN         LL_AHB2_GRP1_EnableClock\n
-  *         AHB2ENR      SDMMC2EN      LL_AHB2_GRP1_EnableClock\n
-  *         AHB2ENR      BDMA1EN       LL_AHB2_GRP1_EnableClock\n (*)
-  *         AHB2ENR      FMACEN        LL_AHB2_GRP1_EnableClock\n
-  *         AHB2ENR      CORDICEN      LL_AHB2_GRP1_EnableClock\n
-  *         AHB2ENR      D2SRAM1EN     LL_AHB2_GRP1_EnableClock\n
-  *         AHB2ENR      D2SRAM2EN     LL_AHB2_GRP1_EnableClock\n
-  *         AHB2ENR      D2SRAM3EN     LL_AHB2_GRP1_EnableClock   (*)
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1  (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_FMAC   (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC->AHB2ENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Check if AHB2 peripheral clock is enabled or not
-  * @rmtoll AHB2ENR      DCMIEN        LL_AHB2_GRP1_IsEnabledClock\n
-  *         AHB2ENR      HSEMEN        LL_AHB2_GRP1_IsEnabledClock\n (*)
-  *         AHB2ENR      CRYPEN        LL_AHB2_GRP1_IsEnabledClock\n (*)
-  *         AHB2ENR      HASHEN        LL_AHB2_GRP1_IsEnabledClock\n (*)
-  *         AHB2ENR      RNGEN         LL_AHB2_GRP1_IsEnabledClock\n
-  *         AHB2ENR      SDMMC2EN      LL_AHB2_GRP1_IsEnabledClock\n
-  *         AHB2ENR      BDMA1EN       LL_AHB2_GRP1_IsEnabledClock\n (*)
-  *         AHB2ENR      FMACEN        LL_AHB2_GRP1_IsEnabledClock\n
-  *         AHB2ENR      CORDICEN      LL_AHB2_GRP1_IsEnabledClock\n
-  *         AHB2ENR      D2SRAM1EN     LL_AHB2_GRP1_IsEnabledClock\n
-  *         AHB2ENR      D2SRAM2EN     LL_AHB2_GRP1_IsEnabledClock\n
-  *         AHB2ENR      D2SRAM3EN     LL_AHB2_GRP1_IsEnabledClock   (*)
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1  (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_FMAC   (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval uint32_t
-*/
-__STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
-{
-  return ((READ_BIT(RCC->AHB2ENR, Periphs) == Periphs)?1U:0U);
-}
-
-/**
-  * @brief  Disable AHB2 peripherals clock.
-  * @rmtoll AHB2ENR      DCMIEN        LL_AHB2_GRP1_DisableClock\n
-  *         AHB2ENR      HSEMEN        LL_AHB2_GRP1_DisableClock\n (*)
-  *         AHB2ENR      CRYPEN        LL_AHB2_GRP1_DisableClock\n (*)
-  *         AHB2ENR      HASHEN        LL_AHB2_GRP1_DisableClock\n (*)
-  *         AHB2ENR      RNGEN         LL_AHB2_GRP1_DisableClock\n
-  *         AHB2ENR      SDMMC2EN      LL_AHB2_GRP1_DisableClock\n
-  *         AHB2ENR      BDMA1EN       LL_AHB2_GRP1_DisableClock\n (*)
-  *         AHB2ENR      FMACEN        LL_AHB2_GRP1_DisableClock\n
-  *         AHB2ENR      CORDICEN      LL_AHB2_GRP1_DisableClock\n
-  *         AHB2ENR      D2SRAM1EN     LL_AHB2_GRP1_DisableClock\n
-  *         AHB2ENR      D2SRAM2EN     LL_AHB2_GRP1_DisableClock\n
-  *         AHB2ENR      D2SRAM3EN     LL_AHB2_GRP1_DisableClock   (*)
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1  (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_FMAC   (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->AHB2ENR, Periphs);
-}
-
-/**
-  * @brief  Force AHB2 peripherals reset.
-  * @rmtoll AHB2RSTR     DCMIRST       LL_AHB2_GRP1_ForceReset\n
-  *         AHB2RSTR     HSEMRST       LL_AHB2_GRP1_ForceReset\n (*)
-  *         AHB2RSTR     CRYPRST       LL_AHB2_GRP1_ForceReset\n (*)
-  *         AHB2RSTR     HASHRST       LL_AHB2_GRP1_ForceReset\n (*)
-  *         AHB2RSTR     RNGRST        LL_AHB2_GRP1_ForceReset\n
-  *         AHB2RSTR     SDMMC2RST     LL_AHB2_GRP1_ForceReset\n
-  *         AHB2RSTR     BDMA1RST      LL_AHB2_GRP1_ForceReset   (*)
-  *         AHB2RSTR     FMACRST       LL_AHB2_GRP1_ForceReset\n
-  *         AHB2RSTR     CORDICRST     LL_AHB2_GRP1_ForceReset 
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1  (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_FMAC   (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)
-{
-  SET_BIT(RCC->AHB2RSTR, Periphs);
-}
-
-/**
-  * @brief  Release AHB2 peripherals reset.
-  * @rmtoll AHB2RSTR     DCMIRST       LL_AHB2_GRP1_ReleaseReset\n
-  *         AHB2RSTR     HSEMRST       LL_AHB2_GRP1_ReleaseReset\n (*)
-  *         AHB2RSTR     CRYPRST       LL_AHB2_GRP1_ReleaseReset\n (*)
-  *         AHB2RSTR     HASHRST       LL_AHB2_GRP1_ReleaseReset\n (*)
-  *         AHB2RSTR     RNGRST        LL_AHB2_GRP1_ReleaseReset\n
-  *         AHB2RSTR     SDMMC2RST     LL_AHB2_GRP1_ReleaseReset\n
-  *         AHB2RSTR     BDMA1RST      LL_AHB2_GRP1_ReleaseReset   (*)
-  *         AHB2RSTR     FMACRST       LL_AHB2_GRP1_ReleaseReset\n
-  *         AHB2RSTR     CORDICRST     LL_AHB2_GRP1_ReleaseReset
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1  (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_FMAC   (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->AHB2RSTR, Periphs);
-}
-
-/**
-  * @brief  Enable AHB2 peripherals clock during Low Power (Sleep) mode.
-  * @rmtoll AHB2LPENR    DCMILPEN      LL_AHB2_GRP1_EnableClockSleep\n
-  *         AHB2LPENR    CRYPLPEN      LL_AHB2_GRP1_EnableClockSleep\n  (*)
-  *         AHB2LPENR    HASHLPEN      LL_AHB2_GRP1_EnableClockSleep\n  (*)
-  *         AHB2LPENR    RNGLPEN       LL_AHB2_GRP1_EnableClockSleep\n
-  *         AHB2LPENR    SDMMC2LPEN    LL_AHB2_GRP1_EnableClockSleep\n
-  *         AHB2LPENR    BDMA1LPEN     LL_AHB2_GRP1_EnableClockSleep\n (*)
-  *         AHB2LPENR    FMACLPEN      LL_AHB2_GRP1_EnableClockSleep\n
-  *         AHB2LPENR    CORDICLPEN    LL_AHB2_GRP1_EnableClockSleep\n
-  *         AHB2LPENR    D2SRAM1LPEN   LL_AHB2_GRP1_EnableClockSleep\n
-  *         AHB2LPENR    D2SRAM2LPEN   LL_AHB2_GRP1_EnableClockSleep\n
-  *         AHB2LPENR    D2SRAM3LPEN   LL_AHB2_GRP1_EnableClockSleep    (*)
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1  (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_FMAC   (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_AHB2_GRP1_EnableClockSleep(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC->AHB2LPENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->AHB2LPENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Disable AHB2 peripherals clock during Low Power (Sleep) mode.
-  * @rmtoll AHB2LPENR    DCMILPEN      LL_AHB2_GRP1_DisableClockSleep\n
-  *         AHB2LPENR    CRYPLPEN      LL_AHB2_GRP1_DisableClockSleep\n (*)
-  *         AHB2LPENR    HASHLPEN      LL_AHB2_GRP1_DisableClockSleep\n (*)
-  *         AHB2LPENR    RNGLPEN       LL_AHB2_GRP1_DisableClockSleep\n
-  *         AHB2LPENR    SDMMC2LPEN    LL_AHB2_GRP1_DisableClockSleep\n
-  *         AHB2LPENR    BDMA1LPEN     LL_AHB2_GRP1_DisableClockSleep\n (*)
-  *         AHB2LPENR    D2SRAM1LPEN   LL_AHB2_GRP1_DisableClockSleep\n
-  *         AHB2LPENR    D2SRAM2LPEN   LL_AHB2_GRP1_DisableClockSleep\n
-  *         AHB2LPENR    D2SRAM3LPEN   LL_AHB2_GRP1_DisableClockSleep   (*)
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1  (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_FMAC   (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_AHB2_GRP1_DisableClockSleep(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->AHB2LPENR, Periphs);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup BUS_LL_EF_AHB4 AHB4
-  * @{
-  */
-
-/**
-  * @brief  Enable AHB4 peripherals clock.
-  * @rmtoll AHB4ENR      GPIOAEN       LL_AHB4_GRP1_EnableClock\n
-  *         AHB4ENR      GPIOBEN       LL_AHB4_GRP1_EnableClock\n
-  *         AHB4ENR      GPIOCEN       LL_AHB4_GRP1_EnableClock\n
-  *         AHB4ENR      GPIODEN       LL_AHB4_GRP1_EnableClock\n
-  *         AHB4ENR      GPIOEEN       LL_AHB4_GRP1_EnableClock\n
-  *         AHB4ENR      GPIOFEN       LL_AHB4_GRP1_EnableClock\n
-  *         AHB4ENR      GPIOGEN       LL_AHB4_GRP1_EnableClock\n
-  *         AHB4ENR      GPIOHEN       LL_AHB4_GRP1_EnableClock\n
-  *         AHB4ENR      GPIOIEN       LL_AHB4_GRP1_EnableClock\n (*)
-  *         AHB4ENR      GPIOJEN       LL_AHB4_GRP1_EnableClock\n
-  *         AHB4ENR      GPIOKEN       LL_AHB4_GRP1_EnableClock\n
-  *         AHB4ENR      CRCEN         LL_AHB4_GRP1_EnableClock\n (*)
-  *         AHB4ENR      BDMAEN        LL_AHB4_GRP1_EnableClock\n
-  *         AHB4ENR      ADC3EN        LL_AHB4_GRP1_EnableClock\n (*)
-  *         AHB4ENR      HSEMEN        LL_AHB4_GRP1_EnableClock\n (*)
-  *         AHB4ENR      BKPRAMEN      LL_AHB4_GRP1_EnableClock\n
-  *         AHB4ENR      SRAM4EN       LL_AHB4_GRP1_EnableClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI  (*)
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC   (*)
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3  (*)
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM  (*)
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_AHB4_GRP1_EnableClock(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC->AHB4ENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->AHB4ENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Check if AHB4 peripheral clock is enabled or not
-  * @rmtoll AHB4ENR      GPIOAEN       LL_AHB4_GRP1_IsEnabledClock\n
-  *         AHB4ENR      GPIOBEN       LL_AHB4_GRP1_IsEnabledClock\n
-  *         AHB4ENR      GPIOCEN       LL_AHB4_GRP1_IsEnabledClock\n
-  *         AHB4ENR      GPIODEN       LL_AHB4_GRP1_IsEnabledClock\n
-  *         AHB4ENR      GPIOEEN       LL_AHB4_GRP1_IsEnabledClock\n
-  *         AHB4ENR      GPIOFEN       LL_AHB4_GRP1_IsEnabledClock\n
-  *         AHB4ENR      GPIOGEN       LL_AHB4_GRP1_IsEnabledClock\n
-  *         AHB4ENR      GPIOHEN       LL_AHB4_GRP1_IsEnabledClock\n
-  *         AHB4ENR      GPIOIEN       LL_AHB4_GRP1_IsEnabledClock\n (*)
-  *         AHB4ENR      GPIOJEN       LL_AHB4_GRP1_IsEnabledClock\n
-  *         AHB4ENR      GPIOKEN       LL_AHB4_GRP1_IsEnabledClock\n
-  *         AHB4ENR      CRCEN         LL_AHB4_GRP1_IsEnabledClock\n (*)
-  *         AHB4ENR      BDMAEN        LL_AHB4_GRP1_IsEnabledClock\n
-  *         AHB4ENR      ADC3EN        LL_AHB4_GRP1_IsEnabledClock\n (*)
-  *         AHB4ENR      HSEMEN        LL_AHB4_GRP1_IsEnabledClock\n (*)
-  *         AHB4ENR      BKPRAMEN      LL_AHB4_GRP1_IsEnabledClock\n
-  *         AHB4ENR      SRAM4EN       LL_AHB4_GRP1_IsEnabledClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI  (*)
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC   (*)
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM  (*)
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
-  *
-  *         (*) value not defined in all devices.
-  * @retval uint32_t
-*/
-__STATIC_INLINE uint32_t LL_AHB4_GRP1_IsEnabledClock(uint32_t Periphs)
-{
-  return ((READ_BIT(RCC->AHB4ENR, Periphs) == Periphs)?1U:0U);
-}
-
-/**
-  * @brief  Disable AHB4 peripherals clock.
-  * @rmtoll AHB4ENR      GPIOAEN       LL_AHB4_GRP1_DisableClock\n
-  *         AHB4ENR      GPIOBEN       LL_AHB4_GRP1_DisableClock\n
-  *         AHB4ENR      GPIOCEN       LL_AHB4_GRP1_DisableClock\n
-  *         AHB4ENR      GPIODEN       LL_AHB4_GRP1_DisableClock\n
-  *         AHB4ENR      GPIOEEN       LL_AHB4_GRP1_DisableClock\n
-  *         AHB4ENR      GPIOFEN       LL_AHB4_GRP1_DisableClock\n
-  *         AHB4ENR      GPIOGEN       LL_AHB4_GRP1_DisableClock\n
-  *         AHB4ENR      GPIOHEN       LL_AHB4_GRP1_DisableClock\n
-  *         AHB4ENR      GPIOIEN       LL_AHB4_GRP1_DisableClock\n  (*)
-  *         AHB4ENR      GPIOJEN       LL_AHB4_GRP1_DisableClock\n
-  *         AHB4ENR      GPIOKEN       LL_AHB4_GRP1_DisableClock\n
-  *         AHB4ENR      CRCEN         LL_AHB4_GRP1_DisableClock\n (*)
-  *         AHB4ENR      BDMAEN        LL_AHB4_GRP1_DisableClock\n
-  *         AHB4ENR      ADC3EN        LL_AHB4_GRP1_DisableClock\n (*)
-  *         AHB4ENR      HSEMEN        LL_AHB4_GRP1_DisableClock\n (*)
-  *         AHB4ENR      BKPRAMEN      LL_AHB4_GRP1_DisableClock\n
-  *         AHB4ENR      SRAM4EN       LL_AHB4_GRP1_DisableClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI  (*)
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC   (*)
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM  (*)
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_AHB4_GRP1_DisableClock(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->AHB4ENR, Periphs);
-}
-
-/**
-  * @brief  Force AHB4 peripherals reset.
-  * @rmtoll AHB4RSTR     GPIOARST      LL_AHB4_GRP1_ForceReset\n
-  *         AHB4RSTR     GPIOBRST      LL_AHB4_GRP1_ForceReset\n
-  *         AHB4RSTR     GPIOCRST      LL_AHB4_GRP1_ForceReset\n
-  *         AHB4RSTR     GPIODRST      LL_AHB4_GRP1_ForceReset\n
-  *         AHB4RSTR     GPIOERST      LL_AHB4_GRP1_ForceReset\n
-  *         AHB4RSTR     GPIOFRST      LL_AHB4_GRP1_ForceReset\n
-  *         AHB4RSTR     GPIOGRST      LL_AHB4_GRP1_ForceReset\n
-  *         AHB4RSTR     GPIOHRST      LL_AHB4_GRP1_ForceReset\n
-  *         AHB4RSTR     GPIOIRST      LL_AHB4_GRP1_ForceReset\n (*)
-  *         AHB4RSTR     GPIOJRST      LL_AHB4_GRP1_ForceReset\n
-  *         AHB4RSTR     GPIOKRST      LL_AHB4_GRP1_ForceReset\n
-  *         AHB4RSTR     CRCRST        LL_AHB4_GRP1_ForceReset\n (*)
-  *         AHB4RSTR     BDMARST       LL_AHB4_GRP1_ForceReset\n
-  *         AHB4RSTR     ADC3RST       LL_AHB4_GRP1_ForceReset\n (*)
-  *         AHB4RSTR     HSEMRST       LL_AHB4_GRP1_ForceReset   (*)
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI  (*)
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC   (*)
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM  (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_AHB4_GRP1_ForceReset(uint32_t Periphs)
-{
-  SET_BIT(RCC->AHB4RSTR, Periphs);
-}
-
-/**
-  * @brief  Release AHB4 peripherals reset.
-  * @rmtoll AHB4RSTR     GPIOARST      LL_AHB4_GRP1_ReleaseReset\n
-  *         AHB4RSTR     GPIOBRST      LL_AHB4_GRP1_ReleaseReset\n
-  *         AHB4RSTR     GPIOCRST      LL_AHB4_GRP1_ReleaseReset\n
-  *         AHB4RSTR     GPIODRST      LL_AHB4_GRP1_ReleaseReset\n
-  *         AHB4RSTR     GPIOERST      LL_AHB4_GRP1_ReleaseReset\n
-  *         AHB4RSTR     GPIOFRST      LL_AHB4_GRP1_ReleaseReset\n
-  *         AHB4RSTR     GPIOGRST      LL_AHB4_GRP1_ReleaseReset\n
-  *         AHB4RSTR     GPIOHRST      LL_AHB4_GRP1_ReleaseReset\n
-  *         AHB4RSTR     GPIOIRST      LL_AHB4_GRP1_ReleaseReset\n (*)
-  *         AHB4RSTR     GPIOJRST      LL_AHB4_GRP1_ReleaseReset\n
-  *         AHB4RSTR     GPIOKRST      LL_AHB4_GRP1_ReleaseReset\n
-  *         AHB4RSTR     CRCRST        LL_AHB4_GRP1_ReleaseReset\n (*)
-  *         AHB4RSTR     BDMARST       LL_AHB4_GRP1_ReleaseReset\n
-  *         AHB4RSTR     ADC3RST       LL_AHB4_GRP1_ReleaseReset\n (*)
-  *         AHB4RSTR     HSEMRST       LL_AHB4_GRP1_ReleaseReset   (*)
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI  (*)
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC   (*)
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM  (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_AHB4_GRP1_ReleaseReset(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->AHB4RSTR, Periphs);
-}
-
-/**
-  * @brief  Enable AHB4 peripherals clock during Low Power (Sleep) mode.
-  * @rmtoll AHB4LPENR    GPIOALPEN     LL_AHB4_GRP1_EnableClockSleep\n
-  *         AHB4LPENR    GPIOBLPEN     LL_AHB4_GRP1_EnableClockSleep\n
-  *         AHB4LPENR    GPIOCLPEN     LL_AHB4_GRP1_EnableClockSleep\n
-  *         AHB4LPENR    GPIODLPEN     LL_AHB4_GRP1_EnableClockSleep\n
-  *         AHB4LPENR    GPIOELPEN     LL_AHB4_GRP1_EnableClockSleep\n
-  *         AHB4LPENR    GPIOFLPEN     LL_AHB4_GRP1_EnableClockSleep\n
-  *         AHB4LPENR    GPIOGLPEN     LL_AHB4_GRP1_EnableClockSleep\n
-  *         AHB4LPENR    GPIOHLPEN     LL_AHB4_GRP1_EnableClockSleep\n
-  *         AHB4LPENR    GPIOILPEN     LL_AHB4_GRP1_EnableClockSleep\n (*)
-  *         AHB4LPENR    GPIOJLPEN     LL_AHB4_GRP1_EnableClockSleep\n
-  *         AHB4LPENR    GPIOKLPEN     LL_AHB4_GRP1_EnableClockSleep\n
-  *         AHB4LPENR    CRCLPEN       LL_AHB4_GRP1_EnableClockSleep\n (*)
-  *         AHB4LPENR    BDMALPEN      LL_AHB4_GRP1_EnableClockSleep\n
-  *         AHB4LPENR    ADC3LPEN      LL_AHB4_GRP1_EnableClockSleep\n (*)
-  *         AHB4LPENR    BKPRAMLPEN    LL_AHB4_GRP1_EnableClockSleep\n
-  *         AHB4LPENR    SRAM4LPEN     LL_AHB4_GRP1_EnableClockSleep
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI  (*)
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC   (*)
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
-  * @retval None
-*/
-__STATIC_INLINE void LL_AHB4_GRP1_EnableClockSleep(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC->AHB4LPENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->AHB4LPENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Disable AHB4 peripherals clock during Low Power (Sleep) mode.
-  * @rmtoll AHB4LPENR    GPIOALPEN     LL_AHB4_GRP1_DisableClockSleep\n
-  *         AHB4LPENR    GPIOBLPEN     LL_AHB4_GRP1_DisableClockSleep\n
-  *         AHB4LPENR    GPIOCLPEN     LL_AHB4_GRP1_DisableClockSleep\n
-  *         AHB4LPENR    GPIODLPEN     LL_AHB4_GRP1_DisableClockSleep\n
-  *         AHB4LPENR    GPIOELPEN     LL_AHB4_GRP1_DisableClockSleep\n
-  *         AHB4LPENR    GPIOFLPEN     LL_AHB4_GRP1_DisableClockSleep\n
-  *         AHB4LPENR    GPIOGLPEN     LL_AHB4_GRP1_DisableClockSleep\n
-  *         AHB4LPENR    GPIOHLPEN     LL_AHB4_GRP1_DisableClockSleep\n
-  *         AHB4LPENR    GPIOILPEN     LL_AHB4_GRP1_DisableClockSleep\n (*)
-  *         AHB4LPENR    GPIOJLPEN     LL_AHB4_GRP1_DisableClockSleep\n
-  *         AHB4LPENR    GPIOKLPEN     LL_AHB4_GRP1_DisableClockSleep\n
-  *         AHB4LPENR    CRCLPEN       LL_AHB4_GRP1_DisableClockSleep\n (*)
-  *         AHB4LPENR    BDMALPEN      LL_AHB4_GRP1_DisableClockSleep\n
-  *         AHB4LPENR    ADC3LPEN      LL_AHB4_GRP1_DisableClockSleep\n (*)
-  *         AHB4LPENR    BKPRAMLPEN    LL_AHB4_GRP1_DisableClockSleep\n
-  *         AHB4LPENR    SRAM4LPEN   LL_AHB4_GRP1_DisableClockSleep
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI  (*)
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC   (*)
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
-  * @retval None
-*/
-__STATIC_INLINE void LL_AHB4_GRP1_DisableClockSleep(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->AHB4LPENR, Periphs);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup BUS_LL_EF_APB3 APB3
-  * @{
-  */
-
-/**
-  * @brief  Enable APB3 peripherals clock.
-  * @rmtoll APB3ENR      LTDCEN        LL_APB3_GRP1_EnableClock\n (*)
-  *         APB3ENR      DSIEN         LL_APB3_GRP1_EnableClock\n (*)
-  *         APB3ENR      WWDG1EN       LL_APB3_GRP1_EnableClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
-  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
-  *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_APB3_GRP1_EnableClock(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC->APB3ENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->APB3ENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Check if APB3 peripheral clock is enabled or not
-  * @rmtoll APB3ENR      LTDCEN        LL_APB3_GRP1_IsEnabledClock\n (*)
-  *         APB3ENR      DSIEN         LL_APB3_GRP1_IsEnabledClock\n (*)
-  *         APB3ENR      WWDG1EN       LL_APB3_GRP1_IsEnabledClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
-  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
-  *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
-  *
-  *         (*) value not defined in all devices.
-  * @retval uint32_t
-*/
-__STATIC_INLINE uint32_t LL_APB3_GRP1_IsEnabledClock(uint32_t Periphs)
-{
-  return ((READ_BIT(RCC->APB3ENR, Periphs) == Periphs)?1U:0U);
-}
-
-/**
-  * @brief  Disable APB3 peripherals clock.
-  * @rmtoll APB3ENR      LTDCEN        LL_APB3_GRP1_DisableClock\n
-  *         APB3ENR      DSIEN         LL_APB3_GRP1_DisableClock\n
-  *         APB3ENR      WWDG1EN       LL_APB3_GRP1_DisableClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
-  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
-  *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_APB3_GRP1_DisableClock(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->APB3ENR, Periphs);
-}
-
-/**
-  * @brief  Force APB3 peripherals reset.
-  * @rmtoll APB3RSTR     LTDCRST       LL_APB3_GRP1_ForceReset\n (*)
-  *         APB3RSTR     DSIRST        LL_APB3_GRP1_ForceReset   (*)
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
-  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_APB3_GRP1_ForceReset(uint32_t Periphs)
-{
-  SET_BIT(RCC->APB3RSTR, Periphs);
-}
-
-/**
-  * @brief  Release APB3 peripherals reset.
-  * @rmtoll APB3RSTR     LTDCRST       LL_APB3_GRP1_ReleaseReset\n
-  *         APB3RSTR     DSIRST        LL_APB3_GRP1_ReleaseReset
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
-  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_APB3_GRP1_ReleaseReset(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->APB3RSTR, Periphs);
-}
-
-/**
-  * @brief  Enable APB3 peripherals clock during Low Power (Sleep) mode.
-  * @rmtoll APB3LPENR    LTDCLPEN      LL_APB3_GRP1_EnableClockSleep\n (*)
-  *         APB3LPENR    DSILPEN       LL_APB3_GRP1_EnableClockSleep\n (*)
-  *         APB3LPENR    WWDG1LPEN     LL_APB3_GRP1_EnableClockSleep
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
-  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
-  *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_APB3_GRP1_EnableClockSleep(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC->APB3LPENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->APB3LPENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Disable APB3 peripherals clock during Low Power (Sleep) mode.
-  * @rmtoll APB3LPENR    LTDCLPEN      LL_APB3_GRP1_DisableClockSleep\n (*)
-  *         APB3LPENR    DSILPEN       LL_APB3_GRP1_DisableClockSleep\n (*)
-  *         APB3LPENR    WWDG1LPEN     LL_APB3_GRP1_DisableClockSleep
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
-  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
-  *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_APB3_GRP1_DisableClockSleep(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->APB3LPENR, Periphs);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup BUS_LL_EF_APB1 APB1
-  * @{
-  */
-
-/**
-  * @brief  Enable APB1 peripherals clock.
-  * @rmtoll APB1LENR     TIM2EN        LL_APB1_GRP1_EnableClock\n
-  *         APB1LENR     TIM3EN        LL_APB1_GRP1_EnableClock\n
-  *         APB1LENR     TIM4EN        LL_APB1_GRP1_EnableClock\n
-  *         APB1LENR     TIM5EN        LL_APB1_GRP1_EnableClock\n
-  *         APB1LENR     TIM6EN        LL_APB1_GRP1_EnableClock\n
-  *         APB1LENR     TIM7EN        LL_APB1_GRP1_EnableClock\n
-  *         APB1LENR     TIM12EN       LL_APB1_GRP1_EnableClock\n
-  *         APB1LENR     TIM13EN       LL_APB1_GRP1_EnableClock\n
-  *         APB1LENR     TIM14EN       LL_APB1_GRP1_EnableClock\n
-  *         APB1LENR     LPTIM1EN      LL_APB1_GRP1_EnableClock\n
-  *         APB1LENR     WWDG2EN       LL_APB1_GRP1_EnableClock\n (*)
-  *         APB1LENR     SPI2EN        LL_APB1_GRP1_EnableClock\n
-  *         APB1LENR     SPI3EN        LL_APB1_GRP1_EnableClock\n
-  *         APB1LENR     SPDIFRXEN     LL_APB1_GRP1_EnableClock\n
-  *         APB1LENR     USART2EN      LL_APB1_GRP1_EnableClock\n
-  *         APB1LENR     USART3EN      LL_APB1_GRP1_EnableClock\n
-  *         APB1LENR     UART4EN       LL_APB1_GRP1_EnableClock\n
-  *         APB1LENR     UART5EN       LL_APB1_GRP1_EnableClock\n
-  *         APB1LENR     I2C1EN        LL_APB1_GRP1_EnableClock\n
-  *         APB1LENR     I2C2EN        LL_APB1_GRP1_EnableClock\n
-  *         APB1LENR     I2C3EN        LL_APB1_GRP1_EnableClock\n
-  *         APB1LENR     I2C5EN        LL_APB1_GRP1_EnableClock\n (*)
-  *         APB1LENR     CECEN         LL_APB1_GRP1_EnableClock\n
-  *         APB1LENR     DAC12EN       LL_APB1_GRP1_EnableClock\n
-  *         APB1LENR     UART7EN       LL_APB1_GRP1_EnableClock\n
-  *         APB1LENR     UART8EN       LL_APB1_GRP1_EnableClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C5 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
-  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC->APB1LENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->APB1LENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Check if APB1 peripheral clock is enabled or not
-  * @rmtoll APB1LENR     TIM2EN        LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1LENR     TIM3EN        LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1LENR     TIM4EN        LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1LENR     TIM5EN        LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1LENR     TIM6EN        LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1LENR     TIM7EN        LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1LENR     TIM12EN       LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1LENR     TIM13EN       LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1LENR     TIM14EN       LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1LENR     LPTIM1EN      LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1LENR     WWDG2EN       LL_APB1_GRP1_IsEnabledClock\n (*)
-  *         APB1LENR     SPI2EN        LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1LENR     SPI3EN        LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1LENR     SPDIFRXEN     LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1LENR     USART2EN      LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1LENR     USART3EN      LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1LENR     UART4EN       LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1LENR     UART5EN       LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1LENR     I2C1EN        LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1LENR     I2C2EN        LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1LENR     I2C3EN        LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1LENR     I2C5EN        LL_APB1_GRP1_IsEnabledClock\n (*)
-  *         APB1LENR     CECEN         LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1LENR     DAC12EN       LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1LENR     UART7EN       LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1LENR     UART8EN       LL_APB1_GRP1_IsEnabledClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C5 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
-  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
-  *
-  *         (*) value not defined in all devices.
-  * @retval uint32_t
-*/
-__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
-{
-  return ((READ_BIT(RCC->APB1LENR, Periphs) == Periphs)?1U:0U);
-}
-
-/**
-  * @brief  Disable APB1 peripherals clock.
-  * @rmtoll APB1LENR     TIM2EN        LL_APB1_GRP1_DisableClock\n
-  *         APB1LENR     TIM3EN        LL_APB1_GRP1_DisableClock\n
-  *         APB1LENR     TIM4EN        LL_APB1_GRP1_DisableClock\n
-  *         APB1LENR     TIM5EN        LL_APB1_GRP1_DisableClock\n
-  *         APB1LENR     TIM6EN        LL_APB1_GRP1_DisableClock\n
-  *         APB1LENR     TIM7EN        LL_APB1_GRP1_DisableClock\n
-  *         APB1LENR     TIM12EN       LL_APB1_GRP1_DisableClock\n
-  *         APB1LENR     TIM13EN       LL_APB1_GRP1_DisableClock\n
-  *         APB1LENR     TIM14EN       LL_APB1_GRP1_DisableClock\n
-  *         APB1LENR     LPTIM1EN      LL_APB1_GRP1_DisableClock\n
-  *         APB1LENR     WWDG2EN       LL_APB1_GRP1_DisableClock\n (*)
-  *         APB1LENR     SPI2EN        LL_APB1_GRP1_DisableClock\n
-  *         APB1LENR     SPI3EN        LL_APB1_GRP1_DisableClock\n
-  *         APB1LENR     SPDIFRXEN     LL_APB1_GRP1_DisableClock\n
-  *         APB1LENR     USART2EN      LL_APB1_GRP1_DisableClock\n
-  *         APB1LENR     USART3EN      LL_APB1_GRP1_DisableClock\n
-  *         APB1LENR     UART4EN       LL_APB1_GRP1_DisableClock\n
-  *         APB1LENR     UART5EN       LL_APB1_GRP1_DisableClock\n
-  *         APB1LENR     I2C1EN        LL_APB1_GRP1_DisableClock\n
-  *         APB1LENR     I2C2EN        LL_APB1_GRP1_DisableClock\n
-  *         APB1LENR     I2C3EN        LL_APB1_GRP1_DisableClock\n
-  *         APB1LENR     I2C5EN        LL_APB1_GRP1_DisableClock\n (*)
-  *         APB1LENR     CECEN         LL_APB1_GRP1_DisableClock\n
-  *         APB1LENR     DAC12EN       LL_APB1_GRP1_DisableClock\n
-  *         APB1LENR     UART7EN       LL_APB1_GRP1_DisableClock\n
-  *         APB1LENR     UART8EN       LL_APB1_GRP1_DisableClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C5 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
-  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->APB1LENR, Periphs);
-}
-
-/**
-  * @brief  Force APB1 peripherals reset.
-  * @rmtoll APB1LRSTR    TIM2RST       LL_APB1_GRP1_ForceReset\n
-  *         APB1LRSTR    TIM3RST       LL_APB1_GRP1_ForceReset\n
-  *         APB1LRSTR    TIM4RST       LL_APB1_GRP1_ForceReset\n
-  *         APB1LRSTR    TIM5RST       LL_APB1_GRP1_ForceReset\n
-  *         APB1LRSTR    TIM6RST       LL_APB1_GRP1_ForceReset\n
-  *         APB1LRSTR    TIM7RST       LL_APB1_GRP1_ForceReset\n
-  *         APB1LRSTR    TIM12RST      LL_APB1_GRP1_ForceReset\n
-  *         APB1LRSTR    TIM13RST      LL_APB1_GRP1_ForceReset\n
-  *         APB1LRSTR    TIM14RST      LL_APB1_GRP1_ForceReset\n
-  *         APB1LRSTR    LPTIM1RST     LL_APB1_GRP1_ForceReset\n
-  *         APB1LRSTR    SPI2RST       LL_APB1_GRP1_ForceReset\n
-  *         APB1LRSTR    SPI3RST       LL_APB1_GRP1_ForceReset\n
-  *         APB1LRSTR    SPDIFRXRST    LL_APB1_GRP1_ForceReset\n
-  *         APB1LRSTR    USART2RST     LL_APB1_GRP1_ForceReset\n
-  *         APB1LRSTR    USART3RST     LL_APB1_GRP1_ForceReset\n
-  *         APB1LRSTR    UART4RST      LL_APB1_GRP1_ForceReset\n
-  *         APB1LRSTR    UART5RST      LL_APB1_GRP1_ForceReset\n
-  *         APB1LRSTR    I2C1RST       LL_APB1_GRP1_ForceReset\n
-  *         APB1LRSTR    I2C2RST       LL_APB1_GRP1_ForceReset\n
-  *         APB1LRSTR    I2C3RST       LL_APB1_GRP1_ForceReset\n
-  *         APB1LRSTR    I2C5RST       LL_APB1_GRP5_ForceReset\n (*)
-  *         APB1LRSTR    CECRST        LL_APB1_GRP1_ForceReset\n
-  *         APB1LRSTR    DAC12RST      LL_APB1_GRP1_ForceReset\n
-  *         APB1LRSTR    UART7RST      LL_APB1_GRP1_ForceReset\n
-  *         APB1LRSTR    UART8RST      LL_APB1_GRP1_ForceReset
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C5 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
-  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
-{
-  SET_BIT(RCC->APB1LRSTR, Periphs);
-}
-
-/**
-  * @brief  Release APB1 peripherals reset.
-  * @rmtoll APB1LRSTR    TIM2RST       LL_APB1_GRP1_ReleaseReset\n
-  *         APB1LRSTR    TIM3RST       LL_APB1_GRP1_ReleaseReset\n
-  *         APB1LRSTR    TIM4RST       LL_APB1_GRP1_ReleaseReset\n
-  *         APB1LRSTR    TIM5RST       LL_APB1_GRP1_ReleaseReset\n
-  *         APB1LRSTR    TIM6RST       LL_APB1_GRP1_ReleaseReset\n
-  *         APB1LRSTR    TIM7RST       LL_APB1_GRP1_ReleaseReset\n
-  *         APB1LRSTR    TIM12RST      LL_APB1_GRP1_ReleaseReset\n
-  *         APB1LRSTR    TIM13RST      LL_APB1_GRP1_ReleaseReset\n
-  *         APB1LRSTR    TIM14RST      LL_APB1_GRP1_ReleaseReset\n
-  *         APB1LRSTR    LPTIM1RST     LL_APB1_GRP1_ReleaseReset\n
-  *         APB1LRSTR    SPI2RST       LL_APB1_GRP1_ReleaseReset\n
-  *         APB1LRSTR    SPI3RST       LL_APB1_GRP1_ReleaseReset\n
-  *         APB1LRSTR    SPDIFRXRST    LL_APB1_GRP1_ReleaseReset\n
-  *         APB1LRSTR    USART2RST     LL_APB1_GRP1_ReleaseReset\n
-  *         APB1LRSTR    USART3RST     LL_APB1_GRP1_ReleaseReset\n
-  *         APB1LRSTR    UART4RST      LL_APB1_GRP1_ReleaseReset\n
-  *         APB1LRSTR    UART5RST      LL_APB1_GRP1_ReleaseReset\n
-  *         APB1LRSTR    I2C1RST       LL_APB1_GRP1_ReleaseReset\n
-  *         APB1LRSTR    I2C2RST       LL_APB1_GRP1_ReleaseReset\n
-  *         APB1LRSTR    I2C3RST       LL_APB1_GRP1_ReleaseReset\n
-  *         APB1LRSTR    I2C5RST       LL_APB1_GRP1_ReleaseReset\n (*)
-  *         APB1LRSTR    CECRST        LL_APB1_GRP1_ReleaseReset\n
-  *         APB1LRSTR    DAC12RST      LL_APB1_GRP1_ReleaseReset\n
-  *         APB1LRSTR    UART7RST      LL_APB1_GRP1_ReleaseReset\n
-  *         APB1LRSTR    UART8RST      LL_APB1_GRP1_ReleaseReset
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C5 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
-  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->APB1LRSTR, Periphs);
-}
-
-/**
-  * @brief  Enable APB1 peripherals clock during Low Power (Sleep) mode.
-  * @rmtoll APB1LLPENR   TIM2LPEN      LL_APB1_GRP1_EnableClockSleep\n
-  *         APB1LLPENR   TIM3LPEN      LL_APB1_GRP1_EnableClockSleep\n
-  *         APB1LLPENR   TIM4LPEN      LL_APB1_GRP1_EnableClockSleep\n
-  *         APB1LLPENR   TIM5LPEN      LL_APB1_GRP1_EnableClockSleep\n
-  *         APB1LLPENR   TIM6LPEN      LL_APB1_GRP1_EnableClockSleep\n
-  *         APB1LLPENR   TIM7LPEN      LL_APB1_GRP1_EnableClockSleep\n
-  *         APB1LLPENR   TIM12LPEN     LL_APB1_GRP1_EnableClockSleep\n
-  *         APB1LLPENR   TIM13LPEN     LL_APB1_GRP1_EnableClockSleep\n
-  *         APB1LLPENR   TIM14LPEN     LL_APB1_GRP1_EnableClockSleep\n
-  *         APB1LLPENR   LPTIM1LPEN    LL_APB1_GRP1_EnableClockSleep\n
-  *         APB1LLPENR   WWDG2LPEN     LL_APB1_GRP1_EnableClockSleep\n (*)
-  *         APB1LLPENR   SPI2LPEN      LL_APB1_GRP1_EnableClockSleep\n
-  *         APB1LLPENR   SPI3LPEN      LL_APB1_GRP1_EnableClockSleep\n
-  *         APB1LLPENR   SPDIFRXLPEN   LL_APB1_GRP1_EnableClockSleep\n
-  *         APB1LLPENR   USART2LPEN    LL_APB1_GRP1_EnableClockSleep\n
-  *         APB1LLPENR   USART3LPEN    LL_APB1_GRP1_EnableClockSleep\n
-  *         APB1LLPENR   UART4LPEN     LL_APB1_GRP1_EnableClockSleep\n
-  *         APB1LLPENR   UART5LPEN     LL_APB1_GRP1_EnableClockSleep\n
-  *         APB1LLPENR   I2C1LPEN      LL_APB1_GRP1_EnableClockSleep\n
-  *         APB1LLPENR   I2C2LPEN      LL_APB1_GRP1_EnableClockSleep\n
-  *         APB1LLPENR   I2C3LPEN      LL_APB1_GRP1_EnableClockSleep\n
-  *         APB1LLPENR   I2C5LPEN      LL_APB1_GRP1_EnableClockSleep\n (*)
-  *         APB1LLPENR   CECLPEN       LL_APB1_GRP1_EnableClockSleep\n
-  *         APB1LLPENR   DAC12LPEN     LL_APB1_GRP1_EnableClockSleep\n
-  *         APB1LLPENR   UART7LPEN     LL_APB1_GRP1_EnableClockSleep\n
-  *         APB1LLPENR   UART8LPEN     LL_APB1_GRP1_EnableClockSleep
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C5 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
-  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_APB1_GRP1_EnableClockSleep(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC->APB1LLPENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->APB1LLPENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Disable APB1 peripherals clock during Low Power (Sleep) mode.
-  * @rmtoll APB1LLPENR   TIM2LPEN      LL_APB1_GRP1_DisableClockSleep\n
-  *         APB1LLPENR   TIM3LPEN      LL_APB1_GRP1_DisableClockSleep\n
-  *         APB1LLPENR   TIM4LPEN      LL_APB1_GRP1_DisableClockSleep\n
-  *         APB1LLPENR   TIM5LPEN      LL_APB1_GRP1_DisableClockSleep\n
-  *         APB1LLPENR   TIM6LPEN      LL_APB1_GRP1_DisableClockSleep\n
-  *         APB1LLPENR   TIM7LPEN      LL_APB1_GRP1_DisableClockSleep\n
-  *         APB1LLPENR   TIM12LPEN     LL_APB1_GRP1_DisableClockSleep\n
-  *         APB1LLPENR   TIM13LPEN     LL_APB1_GRP1_DisableClockSleep\n
-  *         APB1LLPENR   TIM14LPEN     LL_APB1_GRP1_DisableClockSleep\n
-  *         APB1LLPENR   LPTIM1LPEN    LL_APB1_GRP1_DisableClockSleep\n
-  *         APB1LLPENR   WWDG2LPEN     LL_APB1_GRP1_DisableClockSleep\n (*)
-  *         APB1LLPENR   SPI2LPEN      LL_APB1_GRP1_DisableClockSleep\n
-  *         APB1LLPENR   SPI3LPEN      LL_APB1_GRP1_DisableClockSleep\n
-  *         APB1LLPENR   SPDIFRXLPEN   LL_APB1_GRP1_DisableClockSleep\n
-  *         APB1LLPENR   USART2LPEN    LL_APB1_GRP1_DisableClockSleep\n
-  *         APB1LLPENR   USART3LPEN    LL_APB1_GRP1_DisableClockSleep\n
-  *         APB1LLPENR   UART4LPEN     LL_APB1_GRP1_DisableClockSleep\n
-  *         APB1LLPENR   UART5LPEN     LL_APB1_GRP1_DisableClockSleep\n
-  *         APB1LLPENR   I2C1LPEN      LL_APB1_GRP1_DisableClockSleep\n
-  *         APB1LLPENR   I2C2LPEN      LL_APB1_GRP1_DisableClockSleep\n
-  *         APB1LLPENR   I2C3LPEN      LL_APB1_GRP1_DisableClockSleep\n
-  *         APB1LLPENR   I2C5LPEN      LL_APB1_GRP1_DisableClockSleep\n (*)
-  *         APB1LLPENR   CECLPEN       LL_APB1_GRP1_DisableClockSleep\n
-  *         APB1LLPENR   DAC12LPEN     LL_APB1_GRP1_DisableClockSleep\n
-  *         APB1LLPENR   UART7LPEN     LL_APB1_GRP1_DisableClockSleep\n
-  *         APB1LLPENR   UART8LPEN     LL_APB1_GRP1_DisableClockSleep
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C5 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
-  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_APB1_GRP1_DisableClockSleep(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->APB1LLPENR, Periphs);
-}
-
-/**
-  * @brief  Enable APB1 peripherals clock.
-  * @rmtoll APB1HENR     CRSEN         LL_APB1_GRP2_EnableClock\n
-  *         APB1HENR     SWPMIEN       LL_APB1_GRP2_EnableClock\n
-  *         APB1HENR     OPAMPEN       LL_APB1_GRP2_EnableClock\n
-  *         APB1HENR     MDIOSEN       LL_APB1_GRP2_EnableClock\n
-  *         APB1HENR     FDCANEN       LL_APB1_GRP2_EnableClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
-  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
-  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
-  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
-  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
-  *         @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
-  *         @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC->APB1HENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->APB1HENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Check if APB1 peripheral clock is enabled or not
-  * @rmtoll APB1HENR     CRSEN         LL_APB1_GRP2_IsEnabledClock\n
-  *         APB1HENR     SWPMIEN       LL_APB1_GRP2_IsEnabledClock\n
-  *         APB1HENR     OPAMPEN       LL_APB1_GRP2_IsEnabledClock\n
-  *         APB1HENR     MDIOSEN       LL_APB1_GRP2_IsEnabledClock\n
-  *         APB1HENR     FDCANEN       LL_APB1_GRP2_IsEnabledClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
-  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
-  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
-  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
-  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
-  *         @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
-  *         @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval uint32_t
-*/
-__STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
-{
-  return ((READ_BIT(RCC->APB1HENR, Periphs) == Periphs)?1U:0U);
-}
-
-/**
-  * @brief  Disable APB1 peripherals clock.
-  * @rmtoll APB1HENR     CRSEN         LL_APB1_GRP2_DisableClock\n
-  *         APB1HENR     SWPMIEN       LL_APB1_GRP2_DisableClock\n
-  *         APB1HENR     OPAMPEN       LL_APB1_GRP2_DisableClock\n
-  *         APB1HENR     MDIOSEN       LL_APB1_GRP2_DisableClock\n
-  *         APB1HENR     FDCANEN       LL_APB1_GRP2_DisableClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
-  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
-  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
-  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
-  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
-  *         @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
-  *         @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->APB1HENR, Periphs);
-}
-
-/**
-  * @brief  Force APB1 peripherals reset.
-  * @rmtoll APB1HRSTR    CRSRST        LL_APB1_GRP2_ForceReset\n
-  *         APB1HRSTR    SWPMIRST      LL_APB1_GRP2_ForceReset\n
-  *         APB1HRSTR    OPAMPRST      LL_APB1_GRP2_ForceReset\n
-  *         APB1HRSTR    MDIOSRST      LL_APB1_GRP2_ForceReset\n
-  *         APB1HRSTR    FDCANRST      LL_APB1_GRP2_ForceReset
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
-  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
-  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
-  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
-  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
-  *         @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
-  *         @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs)
-{
-  SET_BIT(RCC->APB1HRSTR, Periphs);
-}
-
-/**
-  * @brief  Release APB1 peripherals reset.
-  * @rmtoll APB1HRSTR    CRSRST        LL_APB1_GRP2_ReleaseReset\n
-  *         APB1HRSTR    SWPMIRST      LL_APB1_GRP2_ReleaseReset\n
-  *         APB1HRSTR    OPAMPRST      LL_APB1_GRP2_ReleaseReset\n
-  *         APB1HRSTR    MDIOSRST      LL_APB1_GRP2_ReleaseReset\n
-  *         APB1HRSTR    FDCANRST      LL_APB1_GRP2_ReleaseReset
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
-  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
-  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
-  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
-  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
-  *         @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
-  *         @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->APB1HRSTR, Periphs);
-}
-
-/**
-  * @brief  Enable APB1 peripherals clock during Low Power (Sleep) mode.
-  * @rmtoll APB1HLPENR   CRSLPEN       LL_APB1_GRP2_EnableClockSleep\n
-  *         APB1HLPENR   SWPMILPEN     LL_APB1_GRP2_EnableClockSleep\n
-  *         APB1HLPENR   OPAMPLPEN     LL_APB1_GRP2_EnableClockSleep\n
-  *         APB1HLPENR   MDIOSLPEN     LL_APB1_GRP2_EnableClockSleep\n
-  *         APB1HLPENR   FDCANLPEN     LL_APB1_GRP2_EnableClockSleep
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
-  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
-  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
-  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
-  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
-  *         @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
-  *         @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_APB1_GRP2_EnableClockSleep(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC->APB1HLPENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->APB1HLPENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Disable APB1 peripherals clock during Low Power (Sleep) mode.
-  * @rmtoll APB1HLPENR   CRSLPEN       LL_APB1_GRP2_DisableClockSleep\n
-  *         APB1HLPENR   SWPMILPEN     LL_APB1_GRP2_DisableClockSleep\n
-  *         APB1HLPENR   OPAMPLPEN     LL_APB1_GRP2_DisableClockSleep\n
-  *         APB1HLPENR   MDIOSLPEN     LL_APB1_GRP2_DisableClockSleep\n
-  *         APB1HLPENR   FDCANLPEN     LL_APB1_GRP2_DisableClockSleep
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
-  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
-  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
-  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
-  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
-  *         @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
-  *         @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_APB1_GRP2_DisableClockSleep(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->APB1HLPENR, Periphs);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup BUS_LL_EF_APB2 APB2
-  * @{
-  */
-
-/**
-  * @brief  Enable APB2 peripherals clock.
-  * @rmtoll APB2ENR      TIM1EN        LL_APB2_GRP1_EnableClock\n
-  *         APB2ENR      TIM8EN        LL_APB2_GRP1_EnableClock\n
-  *         APB2ENR      USART1EN      LL_APB2_GRP1_EnableClock\n
-  *         APB2ENR      USART6EN      LL_APB2_GRP1_EnableClock\n
-  *         APB2ENR      UART9EN       LL_APB2_GRP1_EnableClock\n (*)
-  *         APB2ENR      USART10EN     LL_APB2_GRP1_EnableClock\n (*)
-  *         APB2ENR      SPI1EN        LL_APB2_GRP1_EnableClock\n
-  *         APB2ENR      SPI4EN        LL_APB2_GRP1_EnableClock\n
-  *         APB2ENR      TIM15EN       LL_APB2_GRP1_EnableClock\n
-  *         APB2ENR      TIM16EN       LL_APB2_GRP1_EnableClock\n
-  *         APB2ENR      TIM17EN       LL_APB2_GRP1_EnableClock\n
-  *         APB2ENR      SPI5EN        LL_APB2_GRP1_EnableClock\n
-  *         APB2ENR      SAI1EN        LL_APB2_GRP1_EnableClock\n
-  *         APB2ENR      SAI2EN        LL_APB2_GRP1_EnableClock\n
-  *         APB2ENR      SAI3EN        LL_APB2_GRP1_EnableClock\n (*)
-  *         APB2ENR      DFSDM1EN      LL_APB2_GRP1_EnableClock\n
-  *         APB2ENR      HRTIMEN       LL_APB2_GRP1_EnableClock   (*)
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
-  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9   (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2  (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC->APB2ENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Check if APB2 peripheral clock is enabled or not
-  * @rmtoll APB2ENR      TIM1EN        LL_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR      TIM8EN        LL_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR      USART1EN      LL_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR      USART6EN      LL_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR      UART9EN       LL_APB2_GRP1_IsEnabledClock\n (*)
-  *         APB2ENR      USART10EN     LL_APB2_GRP1_IsEnabledClock\n (*)
-  *         APB2ENR      SPI1EN        LL_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR      SPI4EN        LL_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR      TIM15EN       LL_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR      TIM16EN       LL_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR      TIM17EN       LL_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR      SPI5EN        LL_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR      SAI1EN        LL_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR      SAI2EN        LL_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR      SAI3EN        LL_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR      DFSDM1EN      LL_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR      HRTIMEN       LL_APB2_GRP1_IsEnabledClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
-  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9   (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2  (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval uint32_t
-*/
-__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
-{
-  return ((READ_BIT(RCC->APB2ENR, Periphs) == Periphs)?1U:0U);
-}
-
-/**
-  * @brief  Disable APB2 peripherals clock.
-  * @rmtoll APB2ENR      TIM1EN        LL_APB2_GRP1_DisableClock\n
-  *         APB2ENR      TIM8EN        LL_APB2_GRP1_DisableClock\n
-  *         APB2ENR      USART1EN      LL_APB2_GRP1_DisableClock\n
-  *         APB2ENR      USART6EN      LL_APB2_GRP1_DisableClock\n
-  *         APB2ENR      UART9EN       LL_APB2_GRP1_DisableClock\n (*)
-  *         APB2ENR      USART10EN     LL_APB2_GRP1_DisableClock\n (*)
-  *         APB2ENR      SPI1EN        LL_APB2_GRP1_DisableClock\n
-  *         APB2ENR      SPI4EN        LL_APB2_GRP1_DisableClock\n
-  *         APB2ENR      TIM15EN       LL_APB2_GRP1_DisableClock\n
-  *         APB2ENR      TIM16EN       LL_APB2_GRP1_DisableClock\n
-  *         APB2ENR      TIM17EN       LL_APB2_GRP1_DisableClock\n
-  *         APB2ENR      SPI5EN        LL_APB2_GRP1_DisableClock\n
-  *         APB2ENR      SAI1EN        LL_APB2_GRP1_DisableClock\n
-  *         APB2ENR      SAI2EN        LL_APB2_GRP1_DisableClock\n
-  *         APB2ENR      SAI3EN        LL_APB2_GRP1_DisableClock\n (*)
-  *         APB2ENR      DFSDM1EN      LL_APB2_GRP1_DisableClock\n
-  *         APB2ENR      HRTIMEN       LL_APB2_GRP1_DisableClock   (*)
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
-  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9   (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2  (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->APB2ENR, Periphs);
-}
-
-/**
-  * @brief  Force APB2 peripherals reset.
-  * @rmtoll APB2RSTR     TIM1RST       LL_APB2_GRP1_ForceReset\n
-  *         APB2RSTR     TIM8RST       LL_APB2_GRP1_ForceReset\n
-  *         APB2RSTR     USART1RST     LL_APB2_GRP1_ForceReset\n
-  *         APB2RSTR     USART6RST     LL_APB2_GRP1_ForceReset\n
-  *         APB2ENR      UART9RST      LL_APB2_GRP1_ForceReset\n (*)
-  *         APB2ENR      USART10RST    LL_APB2_GRP1_ForceReset\n (*)
-  *         APB2RSTR     SPI1RST       LL_APB2_GRP1_ForceReset\n
-  *         APB2RSTR     SPI4RST       LL_APB2_GRP1_ForceReset\n
-  *         APB2RSTR     TIM15RST      LL_APB2_GRP1_ForceReset\n
-  *         APB2RSTR     TIM16RST      LL_APB2_GRP1_ForceReset\n
-  *         APB2RSTR     TIM17RST      LL_APB2_GRP1_ForceReset\n
-  *         APB2RSTR     SPI5RST       LL_APB2_GRP1_ForceReset\n
-  *         APB2RSTR     SAI1RST       LL_APB2_GRP1_ForceReset\n
-  *         APB2RSTR     SAI2RST       LL_APB2_GRP1_ForceReset\n
-  *         APB2RSTR     SAI3RST       LL_APB2_GRP1_ForceReset\n (*)
-  *         APB2RSTR     DFSDM1RST     LL_APB2_GRP1_ForceReset\n
-  *         APB2RSTR     HRTIMRST      LL_APB2_GRP1_ForceReset   (*)
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
-  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9   (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2  (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
-{
-  SET_BIT(RCC->APB2RSTR, Periphs);
-}
-
-/**
-  * @brief  Release APB2 peripherals reset.
-  * @rmtoll APB2RSTR     TIM1RST       LL_APB2_GRP1_ReleaseReset\n
-  *         APB2RSTR     TIM8RST       LL_APB2_GRP1_ReleaseReset\n
-  *         APB2RSTR     USART1RST     LL_APB2_GRP1_ReleaseReset\n
-  *         APB2RSTR     USART6RST     LL_APB2_GRP1_ReleaseReset\n
-  *         APB2ENR      UART9RST      LL_APB2_GRP1_ReleaseReset\n (*)
-  *         APB2ENR      USART10RST    LL_APB2_GRP1_ReleaseReset\n (*)
-  *         APB2RSTR     SPI1RST       LL_APB2_GRP1_ReleaseReset\n
-  *         APB2RSTR     SPI4RST       LL_APB2_GRP1_ReleaseReset\n
-  *         APB2RSTR     TIM15RST      LL_APB2_GRP1_ReleaseReset\n
-  *         APB2RSTR     TIM16RST      LL_APB2_GRP1_ReleaseReset\n
-  *         APB2RSTR     TIM17RST      LL_APB2_GRP1_ReleaseReset\n
-  *         APB2RSTR     SPI5RST       LL_APB2_GRP1_ReleaseReset\n
-  *         APB2RSTR     SAI1RST       LL_APB2_GRP1_ReleaseReset\n
-  *         APB2RSTR     SAI2RST       LL_APB2_GRP1_ReleaseReset\n
-  *         APB2RSTR     SAI3RST       LL_APB2_GRP1_ReleaseReset\n (*)
-  *         APB2RSTR     DFSDM1RST     LL_APB2_GRP1_ReleaseReset\n
-  *         APB2RSTR     HRTIMRST      LL_APB2_GRP1_ReleaseReset   (*)
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
-  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9   (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2  (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->APB2RSTR, Periphs);
-}
-
-/**
-  * @brief  Enable APB2 peripherals clock during Low Power (Sleep) mode.
-  * @rmtoll APB2LPENR    TIM1LPEN      LL_APB2_GRP1_EnableClockSleep\n
-  *         APB2LPENR    TIM8LPEN      LL_APB2_GRP1_EnableClockSleep\n
-  *         APB2LPENR    USART1LPEN    LL_APB2_GRP1_EnableClockSleep\n
-  *         APB2LPENR    USART6LPEN    LL_APB2_GRP1_EnableClockSleep\n
-  *         APB2ENR      UART9LPEN     LL_APB2_GRP1_EnableClockSleep\n (*)
-  *         APB2ENR      USART10LPEN   LL_APB2_GRP1_EnableClockSleep\n (*)
-  *         APB2LPENR    SPI1LPEN      LL_APB2_GRP1_EnableClockSleep\n
-  *         APB2LPENR    SPI4LPEN      LL_APB2_GRP1_EnableClockSleep\n
-  *         APB2LPENR    TIM15LPEN     LL_APB2_GRP1_EnableClockSleep\n
-  *         APB2LPENR    TIM16LPEN     LL_APB2_GRP1_EnableClockSleep\n
-  *         APB2LPENR    TIM17LPEN     LL_APB2_GRP1_EnableClockSleep\n
-  *         APB2LPENR    SPI5LPEN      LL_APB2_GRP1_EnableClockSleep\n
-  *         APB2LPENR    SAI1LPEN      LL_APB2_GRP1_EnableClockSleep\n
-  *         APB2LPENR    SAI2LPEN      LL_APB2_GRP1_EnableClockSleep\n
-  *         APB2LPENR    SAI3LPEN      LL_APB2_GRP1_EnableClockSleep\n (*)
-  *         APB2LPENR    DFSDM1LPEN    LL_APB2_GRP1_EnableClockSleep\n
-  *         APB2LPENR    HRTIMLPEN     LL_APB2_GRP1_EnableClockSleep   (*)
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
-  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9   (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2  (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_APB2_GRP1_EnableClockSleep(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC->APB2LPENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->APB2LPENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Disable APB2 peripherals clock during Low Power (Sleep) mode.
-  * @rmtoll APB2LPENR    TIM1LPEN      LL_APB2_GRP1_DisableClockSleep\n
-  *         APB2LPENR    TIM8LPEN      LL_APB2_GRP1_DisableClockSleep\n
-  *         APB2LPENR    USART1LPEN    LL_APB2_GRP1_DisableClockSleep\n
-  *         APB2LPENR    USART6LPEN    LL_APB2_GRP1_DisableClockSleep\n
-  *         APB2ENR      UART9LPEN     LL_APB2_GRP1_DisableClockSleep\n (*)
-  *         APB2ENR      USART10LPEN   LL_APB2_GRP1_DisableClockSleep\n (*)
-  *         APB2LPENR    SPI1LPEN      LL_APB2_GRP1_DisableClockSleep\n
-  *         APB2LPENR    SPI4LPEN      LL_APB2_GRP1_DisableClockSleep\n
-  *         APB2LPENR    TIM15LPEN     LL_APB2_GRP1_DisableClockSleep\n
-  *         APB2LPENR    TIM16LPEN     LL_APB2_GRP1_DisableClockSleep\n
-  *         APB2LPENR    TIM17LPEN     LL_APB2_GRP1_DisableClockSleep\n
-  *         APB2LPENR    SPI5LPEN      LL_APB2_GRP1_DisableClockSleep\n
-  *         APB2LPENR    SAI1LPEN      LL_APB2_GRP1_DisableClockSleep\n
-  *         APB2LPENR    SAI2LPEN      LL_APB2_GRP1_DisableClockSleep\n
-  *         APB2LPENR    SAI3LPEN      LL_APB2_GRP1_DisableClockSleep\n (*)
-  *         APB2LPENR    DFSDM1LPEN    LL_APB2_GRP1_DisableClockSleep\n
-  *         APB2LPENR    HRTIMLPEN     LL_APB2_GRP1_DisableClockSleep   (*)
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
-  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9   (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2  (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_APB2_GRP1_DisableClockSleep(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->APB2LPENR, Periphs);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup BUS_LL_EF_APB4 APB4
-  * @{
-  */
-
-/**
-  * @brief  Enable APB4 peripherals clock.
-  * @rmtoll APB4ENR      SYSCFGEN      LL_APB4_GRP1_EnableClock\n
-  *         APB4ENR      LPUART1EN     LL_APB4_GRP1_EnableClock\n
-  *         APB4ENR      SPI6EN        LL_APB4_GRP1_EnableClock\n
-  *         APB4ENR      I2C4EN        LL_APB4_GRP1_EnableClock\n
-  *         APB4ENR      LPTIM2EN      LL_APB4_GRP1_EnableClock\n
-  *         APB4ENR      LPTIM3EN      LL_APB4_GRP1_EnableClock\n
-  *         APB4ENR      LPTIM4EN      LL_APB4_GRP1_EnableClock\n  (*)
-  *         APB4ENR      LPTIM5EN      LL_APB4_GRP1_EnableClock\n  (*)
-  *         APB4ENR      DAC2EN        LL_APB4_GRP1_EnableClock\n  (*)
-  *         APB4ENR      COMP12EN      LL_APB4_GRP1_EnableClock\n
-  *         APB4ENR      VREFEN        LL_APB4_GRP1_EnableClock\n
-  *         APB4ENR      RTCAPBEN      LL_APB4_GRP1_EnableClock\n
-  *         APB4ENR      SAI4EN        LL_APB4_GRP1_EnableClock\n  (*)
-  *         APB4ENR      DTSEN         LL_APB4_GRP1_EnableClock\n  (*)
-  *         APB4ENR      DFSDM2EN      LL_APB4_GRP1_EnableClock    (*)
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
-  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
-  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
-  *         @arg @ref LL_APB4_GRP1_PERIPH_DAC2   (*)
-  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
-  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
-  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
-  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
-  *         @arg @ref LL_APB4_GRP1_PERIPH_DTS    (*)
-  *         @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_APB4_GRP1_EnableClock(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC->APB4ENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->APB4ENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Check if APB4 peripheral clock is enabled or not
-  * @rmtoll APB4ENR      SYSCFGEN      LL_APB4_GRP1_IsEnabledClock\n
-  *         APB4ENR      LPUART1EN     LL_APB4_GRP1_IsEnabledClock\n
-  *         APB4ENR      SPI6EN        LL_APB4_GRP1_IsEnabledClock\n
-  *         APB4ENR      I2C4EN        LL_APB4_GRP1_IsEnabledClock\n
-  *         APB4ENR      LPTIM2EN      LL_APB4_GRP1_IsEnabledClock\n
-  *         APB4ENR      LPTIM3EN      LL_APB4_GRP1_IsEnabledClock\n
-  *         APB4ENR      LPTIM4EN      LL_APB4_GRP1_IsEnabledClock\n (*)
-  *         APB4ENR      LPTIM5EN      LL_APB4_GRP1_IsEnabledClock\n (*)
-  *         APB4ENR      DAC2EN        LL_APB4_GRP1_IsEnabledClock\n (*)
-  *         APB4ENR      COMP12EN      LL_APB4_GRP1_IsEnabledClock\n
-  *         APB4ENR      VREFEN        LL_APB4_GRP1_IsEnabledClock\n
-  *         APB4ENR      RTCAPBEN      LL_APB4_GRP1_IsEnabledClock\n
-  *         APB4ENR      SAI4EN        LL_APB4_GRP1_IsEnabledClock\n (*)
-  *         APB4ENR      DTSEN         LL_APB4_GRP1_IsEnabledClock\n (*)
-  *         APB4ENR      DFSDM2EN      LL_APB4_GRP1_IsEnabledClock   (*)
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
-  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
-  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
-  *         @arg @ref LL_APB4_GRP1_PERIPH_DAC2   (*)
-  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
-  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
-  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
-  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
-  *         @arg @ref LL_APB4_GRP1_PERIPH_DTS    (*)
-  *         @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval uint32_t
-*/
-__STATIC_INLINE uint32_t LL_APB4_GRP1_IsEnabledClock(uint32_t Periphs)
-{
-  return ((READ_BIT(RCC->APB4ENR, Periphs) == Periphs)?1U:0U);
-}
-
-/**
-  * @brief  Disable APB4 peripherals clock.
-  * @rmtoll APB4ENR      SYSCFGEN      LL_APB4_GRP1_DisableClock\n
-  *         APB4ENR      LPUART1EN     LL_APB4_GRP1_DisableClock\n
-  *         APB4ENR      SPI6EN        LL_APB4_GRP1_DisableClock\n
-  *         APB4ENR      I2C4EN        LL_APB4_GRP1_DisableClock\n
-  *         APB4ENR      LPTIM2EN      LL_APB4_GRP1_DisableClock\n
-  *         APB4ENR      LPTIM3EN      LL_APB4_GRP1_DisableClock\n
-  *         APB4ENR      LPTIM4EN      LL_APB4_GRP1_DisableClock\n  (*)
-  *         APB4ENR      LPTIM5EN      LL_APB4_GRP1_DisableClock\n  (*)
-  *         APB4ENR      DAC2EN        LL_APB4_GRP1_DisableClock\n  (*)
-  *         APB4ENR      COMP12EN      LL_APB4_GRP1_DisableClock\n
-  *         APB4ENR      VREFEN        LL_APB4_GRP1_DisableClock\n
-  *         APB4ENR      RTCAPBEN      LL_APB4_GRP1_DisableClock\n
-  *         APB4ENR      SAI4EN        LL_APB4_GRP1_DisableClock\n  (*)
-  *         APB4ENR      DTSEN         LL_APB4_GRP1_DisableClock\n  (*)
-  *         APB4ENR      DFSDM2EN      LL_APB4_GRP1_DisableClock    (*)
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
-  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
-  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
-  *         @arg @ref LL_APB4_GRP1_PERIPH_DAC2   (*)
-  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
-  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
-  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
-  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
-  *         @arg @ref LL_APB4_GRP1_PERIPH_DTS    (*)
-  *         @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_APB4_GRP1_DisableClock(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->APB4ENR, Periphs);
-}
-
-/**
-  * @brief  Force APB4 peripherals reset.
-  * @rmtoll APB4RSTR     SYSCFGRST     LL_APB4_GRP1_ForceReset\n
-  *         APB4RSTR     LPUART1RST    LL_APB4_GRP1_ForceReset\n
-  *         APB4RSTR     SPI6RST       LL_APB4_GRP1_ForceReset\n
-  *         APB4RSTR     I2C4RST       LL_APB4_GRP1_ForceReset\n
-  *         APB4RSTR     LPTIM2RST     LL_APB4_GRP1_ForceReset\n
-  *         APB4RSTR     LPTIM3RST     LL_APB4_GRP1_ForceReset\n
-  *         APB4RSTR     LPTIM4RST     LL_APB4_GRP1_ForceReset\n  (*)
-  *         APB4RSTR     LPTIM5RST     LL_APB4_GRP1_ForceReset\n  (*)
-  *         APB4RSTR     DAC2EN        LL_APB4_GRP1_ForceReset\n  (*)
-  *         APB4RSTR     COMP12RST     LL_APB4_GRP1_ForceReset\n
-  *         APB4RSTR     VREFRST       LL_APB4_GRP1_ForceReset\n
-  *         APB4RSTR     SAI4RST       LL_APB4_GRP1_ForceReset\n  (*)
-  *         APB4RSTR     DTSRST        LL_APB4_GRP1_ForceReset\n  (*)
-  *         APB4RSTR     DFSDM2RST     LL_APB4_GRP1_ForceReset    (*)
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
-  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
-  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
-  *         @arg @ref LL_APB4_GRP1_PERIPH_DAC2   (*)
-  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
-  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
-  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
-  *         @arg @ref LL_APB4_GRP1_PERIPH_DTS    (*)
-  *         @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_APB4_GRP1_ForceReset(uint32_t Periphs)
-{
-  SET_BIT(RCC->APB4RSTR, Periphs);
-}
-
-/**
-  * @brief  Release APB4 peripherals reset.
-  * @rmtoll APB4RSTR     SYSCFGRST     LL_APB4_GRP1_ReleaseReset\n
-  *         APB4RSTR     LPUART1RST    LL_APB4_GRP1_ReleaseReset\n
-  *         APB4RSTR     SPI6RST       LL_APB4_GRP1_ReleaseReset\n
-  *         APB4RSTR     I2C4RST       LL_APB4_GRP1_ReleaseReset\n
-  *         APB4RSTR     LPTIM2RST     LL_APB4_GRP1_ReleaseReset\n
-  *         APB4RSTR     LPTIM3RST     LL_APB4_GRP1_ReleaseReset\n
-  *         APB4RSTR     LPTIM4RST     LL_APB4_GRP1_ReleaseReset\n  (*)
-  *         APB4RSTR     LPTIM5RST     LL_APB4_GRP1_ReleaseReset\n  (*)
-  *         APB4RSTR     DAC2RST       LL_APB4_GRP1_ReleaseReset\n  (*)
-  *         APB4RSTR     COMP12RST     LL_APB4_GRP1_ReleaseReset\n
-  *         APB4RSTR     VREFRST       LL_APB4_GRP1_ReleaseReset\n
-  *         APB4RSTR     SAI4RST       LL_APB4_GRP1_ReleaseReset\n
-  *         APB4RSTR     DTSRST        LL_APB4_GRP1_ReleaseReset\n  (*)
-  *         APB4RSTR     DFSDM2RST     LL_APB4_GRP1_ReleaseReset    (*)
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
-  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
-  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
-  *         @arg @ref LL_APB4_GRP1_PERIPH_DAC2   (*)
-  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
-  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
-  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
-  *         @arg @ref LL_APB4_GRP1_PERIPH_DTS    (*)
-  *         @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_APB4_GRP1_ReleaseReset(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->APB4RSTR, Periphs);
-}
-
-/**
-  * @brief  Enable APB4 peripherals clock during Low Power (Sleep) mode.
-  * @rmtoll APB4LPENR    SYSCFGLPEN    LL_APB4_GRP1_EnableClockSleep\n
-  *         APB4LPENR    LPUART1LPEN   LL_APB4_GRP1_EnableClockSleep\n
-  *         APB4LPENR    SPI6LPEN      LL_APB4_GRP1_EnableClockSleep\n
-  *         APB4LPENR    I2C4LPEN      LL_APB4_GRP1_EnableClockSleep\n
-  *         APB4LPENR    LPTIM2LPEN    LL_APB4_GRP1_EnableClockSleep\n
-  *         APB4LPENR    LPTIM3LPEN    LL_APB4_GRP1_EnableClockSleep\n
-  *         APB4LPENR    LPTIM4LPEN    LL_APB4_GRP1_EnableClockSleep\n (*)
-  *         APB4LPENR    LPTIM5LPEN    LL_APB4_GRP1_EnableClockSleep\n (*)
-  *         APB4LPENR    DAC2LPEN      LL_APB4_GRP1_EnableClockSleep\n (*)
-  *         APB4LPENR    COMP12LPEN    LL_APB4_GRP1_EnableClockSleep\n
-  *         APB4LPENR    VREFLPEN      LL_APB4_GRP1_EnableClockSleep\n
-  *         APB4LPENR    RTCAPBLPEN    LL_APB4_GRP1_EnableClockSleep\n
-  *         APB4LPENR    SAI4LPEN      LL_APB4_GRP1_EnableClockSleep\n (*)
-  *         APB4LPENR    DTSLPEN       LL_APB4_GRP1_EnableClockSleep\n (*)
-  *         APB4LPENR    DFSDM2LPEN    LL_APB4_GRP1_EnableClockSleep   (*)
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
-  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
-  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
-  *         @arg @ref LL_APB4_GRP1_PERIPH_DAC2   (*)
-  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
-  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
-  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
-  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
-  *         @arg @ref LL_APB4_GRP1_PERIPH_DTS    (*)
-  *         @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_APB4_GRP1_EnableClockSleep(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC->APB4LPENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->APB4LPENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Disable APB4 peripherals clock during Low Power (Sleep) mode.
-  * @rmtoll APB4LPENR    SYSCFGLPEN    LL_APB4_GRP1_DisableClockSleep\n
-  *         APB4LPENR    LPUART1LPEN   LL_APB4_GRP1_DisableClockSleep\n
-  *         APB4LPENR    SPI6LPEN      LL_APB4_GRP1_DisableClockSleep\n
-  *         APB4LPENR    I2C4LPEN      LL_APB4_GRP1_DisableClockSleep\n
-  *         APB4LPENR    LPTIM2LPEN    LL_APB4_GRP1_DisableClockSleep\n
-  *         APB4LPENR    LPTIM3LPEN    LL_APB4_GRP1_DisableClockSleep\n
-  *         APB4LPENR    LPTIM4LPEN    LL_APB4_GRP1_DisableClockSleep\n (*)
-  *         APB4LPENR    LPTIM5LPEN    LL_APB4_GRP1_DisableClockSleep\n (*)
-  *         APB4LPENR    DAC2LPEN      LL_APB4_GRP1_DisableClockSleep\n (*)
-  *         APB4LPENR    COMP12LPEN    LL_APB4_GRP1_DisableClockSleep\n
-  *         APB4LPENR    VREFLPEN      LL_APB4_GRP1_DisableClockSleep\n
-  *         APB4LPENR    RTCAPBLPEN    LL_APB4_GRP1_DisableClockSleep\n
-  *         APB4LPENR    SAI4LPEN      LL_APB4_GRP1_DisableClockSleep\n (*)
-  *         APB4LPENR    DTSLPEN       LL_APB4_GRP1_DisableClockSleep\n (*)
-  *         APB4LPENR    DFSDM2LPEN    LL_APB4_GRP1_DisableClockSleep   (*)
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
-  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
-  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
-  *         @arg @ref LL_APB4_GRP1_PERIPH_DAC2   (*)
-  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
-  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
-  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
-  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
-  *         @arg @ref LL_APB4_GRP1_PERIPH_DTS    (*)
-  *         @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_APB4_GRP1_DisableClockSleep(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->APB4LPENR, Periphs);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup BUS_LL_EF_CLKAM CLKAM
-  * @{
-  */
-
-/**
-  * @brief  Enable peripherals clock for CLKAM Mode.
-  * @rmtoll D3AMR / SRDAMR         BDMA          LL_CLKAM_Enable\n
-  *         D3AMR / SRDAMR         LPUART1       LL_CLKAM_Enable\n
-  *         D3AMR / SRDAMR         SPI6          LL_CLKAM_Enable\n
-  *         D3AMR / SRDAMR         I2C4          LL_CLKAM_Enable\n
-  *         D3AMR / SRDAMR         LPTIM2        LL_CLKAM_Enable\n
-  *         D3AMR / SRDAMR         LPTIM3        LL_CLKAM_Enable\n
-  *         D3AMR / SRDAMR         LPTIM4        LL_CLKAM_Enable\n  (*)
-  *         D3AMR / SRDAMR         LPTIM5        LL_CLKAM_Enable\n  (*)
-  *         D3AMR / SRDAMR         DAC2          LL_CLKAM_Enable\n  (*)
-  *         D3AMR / SRDAMR         COMP12        LL_CLKAM_Enable\n
-  *         D3AMR / SRDAMR         VREF          LL_CLKAM_Enable\n
-  *         D3AMR / SRDAMR         RTC           LL_CLKAM_Enable\n
-  *         D3AMR / SRDAMR         CRC           LL_CLKAM_Enable\n
-  *         D3AMR / SRDAMR         SAI4          LL_CLKAM_Enable\n  (*)
-  *         D3AMR / SRDAMR         ADC3          LL_CLKAM_Enable\n  (*)
-  *         D3AMR / SRDAMR         DTS           LL_CLKAM_Enable\n  (*)
-  *         D3AMR / SRDAMR         DFSDM2        LL_CLKAM_Enable\n  (*)
-  *         D3AMR / SRDAMR         BKPRAM        LL_CLKAM_Enable\n
-  *         D3AMR / SRDAMR         SRAM4         LL_CLKAM_Enable
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_CLKAM_PERIPH_BDMA
-  *         @arg @ref LL_CLKAM_PERIPH_GPIO   (*)
-  *         @arg @ref LL_CLKAM_PERIPH_LPUART1
-  *         @arg @ref LL_CLKAM_PERIPH_SPI6
-  *         @arg @ref LL_CLKAM_PERIPH_I2C4
-  *         @arg @ref LL_CLKAM_PERIPH_LPTIM2
-  *         @arg @ref LL_CLKAM_PERIPH_LPTIM3
-  *         @arg @ref LL_CLKAM_PERIPH_LPTIM4 (*)
-  *         @arg @ref LL_CLKAM_PERIPH_LPTIM5 (*)
-  *         @arg @ref LL_CLKAM_PERIPH_DAC2   (*)
-  *         @arg @ref LL_CLKAM_PERIPH_COMP12
-  *         @arg @ref LL_CLKAM_PERIPH_VREF
-  *         @arg @ref LL_CLKAM_PERIPH_RTC
-  *         @arg @ref LL_CLKAM_PERIPH_CRC (*) 
-  *         @arg @ref LL_CLKAM_PERIPH_SAI4 (*)
-  *         @arg @ref LL_CLKAM_PERIPH_ADC3 (*)
-  *         @arg @ref LL_CLKAM_PERIPH_DTS    (*)
-  *         @arg @ref LL_CLKAM_PERIPH_DFSDM2 (*)
-  *         @arg @ref LL_CLKAM_PERIPH_BKPRAM
-  *         @arg @ref LL_CLKAM_PERIPH_SRAM4
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_CLKAM_Enable(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-
-#if defined(RCC_D3AMR_BDMAAMEN)
-  SET_BIT(RCC->D3AMR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->D3AMR, Periphs);
-#else
-  SET_BIT(RCC->SRDAMR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->SRDAMR, Periphs);
-#endif /* RCC_D3AMR_BDMAAMEN */
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Disable peripherals clock for CLKAM Mode.
-  * @rmtoll D3AMR / SRDAMR        BDMA          LL_CLKAM_Disable\n
-  *         D3AMR / SRDAMR        LPUART1       LL_CLKAM_Disable\n
-  *         D3AMR / SRDAMR        SPI6          LL_CLKAM_Disable\n
-  *         D3AMR / SRDAMR        I2C4          LL_CLKAM_Disable\n
-  *         D3AMR / SRDAMR        LPTIM2        LL_CLKAM_Disable\n
-  *         D3AMR / SRDAMR        LPTIM3        LL_CLKAM_Disable\n
-  *         D3AMR / SRDAMR        LPTIM4        LL_CLKAM_Disable\n (*)
-  *         D3AMR / SRDAMR        LPTIM5        LL_CLKAM_Disable\n (*)
-  *         D3AMR / SRDAMR        DAC2          LL_CLKAM_Disable\n (*)
-  *         D3AMR / SRDAMR        COMP12        LL_CLKAM_Disable\n
-  *         D3AMR / SRDAMR        VREF          LL_CLKAM_Disable\n
-  *         D3AMR / SRDAMR        RTC           LL_CLKAM_Disable\n
-  *         D3AMR / SRDAMR        CRC           LL_CLKAM_Disable\n
-  *         D3AMR / SRDAMR        SAI4          LL_CLKAM_Disable\n (*)
-  *         D3AMR / SRDAMR        ADC3          LL_CLKAM_Disable\n (*)
-  *         D3AMR / SRDAMR        DTS           LL_CLKAM_Disable\n (*)
-  *         D3AMR / SRDAMR        DFSDM2        LL_CLKAM_Disable\n (*)
-  *         D3AMR / SRDAMR        BKPRAM        LL_CLKAM_Disable\n
-  *         D3AMR / SRDAMR        SRAM4         LL_CLKAM_Disable
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_CLKAM_PERIPH_BDMA
-  *         @arg @ref LL_CLKAM_PERIPH_GPIO   (*)
-  *         @arg @ref LL_CLKAM_PERIPH_LPUART1
-  *         @arg @ref LL_CLKAM_PERIPH_SPI6
-  *         @arg @ref LL_CLKAM_PERIPH_I2C4
-  *         @arg @ref LL_CLKAM_PERIPH_LPTIM2
-  *         @arg @ref LL_CLKAM_PERIPH_LPTIM3
-  *         @arg @ref LL_CLKAM_PERIPH_LPTIM4 (*)
-  *         @arg @ref LL_CLKAM_PERIPH_LPTIM5 (*)
-  *         @arg @ref LL_CLKAM_PERIPH_DAC2   (*)
-  *         @arg @ref LL_CLKAM_PERIPH_COMP12
-  *         @arg @ref LL_CLKAM_PERIPH_VREF
-  *         @arg @ref LL_CLKAM_PERIPH_RTC
-  *         @arg @ref LL_CLKAM_PERIPH_CRC (*) 
-  *         @arg @ref LL_CLKAM_PERIPH_SAI4 (*)
-  *         @arg @ref LL_CLKAM_PERIPH_ADC3 (*)
-  *         @arg @ref LL_CLKAM_PERIPH_DTS    (*)
-  *         @arg @ref LL_CLKAM_PERIPH_DFSDM2  (*)
-  *         @arg @ref LL_CLKAM_PERIPH_BKPRAM
-  *         @arg @ref LL_CLKAM_PERIPH_SRAM4
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_CLKAM_Disable(uint32_t Periphs)
-{
-#if defined(RCC_D3AMR_BDMAAMEN)
-  CLEAR_BIT(RCC->D3AMR, Periphs);
-#else
-  CLEAR_BIT(RCC->SRDAMR, Periphs);
-#endif /* RCC_D3AMR_BDMAAMEN */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup BUS_LL_EF_CKGA CKGA
-  * @{
-  */
-
-#if defined(RCC_CKGAENR_AXICKG)
-
-
-/**
-  * @brief  Enable clock gating for AXI bus peripherals.
-  * @rmtoll
-  * @param :
-  * @retval None
-*/
-__STATIC_INLINE void LL_CKGA_Enable(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC->CKGAENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->CKGAENR, Periphs);
-  (void)tmpreg;
-}
-
-#endif /* RCC_CKGAENR_AXICKG */
-
-#if defined(RCC_CKGAENR_AXICKG)
-
-/**
-  * @brief  Disable  clock gating for AXI bus peripherals.
-  * @rmtoll
-  * @param :
-  * @retval None
-*/
-__STATIC_INLINE void LL_CKGA_Disable(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->CKGAENR, Periphs);
-}
-
-#endif /* RCC_CKGAENR_AXICKG */
-
-/**
-  * @}
-  */
-
-#if defined(DUAL_CORE)
-/** @addtogroup BUS_LL_EF_AHB3 AHB3
-  * @{
-  */
-
-/**
-  * @brief  Enable C1 AHB3 peripherals clock.
-  * @rmtoll AHB3ENR      MDMAEN        LL_C1_AHB3_GRP1_EnableClock\n
-  *         AHB3ENR      DMA2DEN       LL_C1_AHB3_GRP1_EnableClock\n
-  *         AHB3ENR      JPGDECEN      LL_C1_AHB3_GRP1_EnableClock\n
-  *         AHB3ENR      FMCEN         LL_C1_AHB3_GRP1_EnableClock\n
-  *         AHB3ENR      QSPIEN        LL_C1_AHB3_GRP1_EnableClock\n (*)
-  *         AHB3ENR      OSPI1EN       LL_C1_AHB3_GRP1_EnableClock\n (*)
-  *         AHB3ENR      OSPI2EN       LL_C1_AHB3_GRP1_EnableClock\n (*)
-  *         AHB3ENR      IOMNGREN      LL_C1_AHB3_GRP1_EnableClock\n (*)
-  *         AHB3ENR      OTFDEC1EN     LL_C1_AHB3_GRP1_EnableClock\n (*)
-  *         AHB3ENR      OTFDEC2EN     LL_C1_AHB3_GRP1_EnableClock\n (*)
-  *         AHB3ENR      GFXMMU        LL_C1_AHB3_GRP1_EnableClock\n (*)
-  *         AHB3ENR      SDMMC1EN      LL_C1_AHB3_GRP1_EnableClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI    (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1   (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2   (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM  (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU  (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_C1_AHB3_GRP1_EnableClock(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC_C1->AHB3ENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC_C1->AHB3ENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Check if C1 AHB3 peripheral clock is enabled or not
-  * @rmtoll AHB3ENR      MDMAEN        LL_C1_AHB3_GRP1_IsEnabledClock\n
-  *         AHB3ENR      DMA2DEN       LL_C1_AHB3_GRP1_IsEnabledClock\n
-  *         AHB3ENR      JPGDECEN      LL_C1_AHB3_GRP1_IsEnabledClock\n
-  *         AHB3ENR      FMCEN         LL_C1_AHB3_GRP1_IsEnabledClock\n
-  *         AHB3ENR      QSPIEN        LL_C1_AHB3_GRP1_IsEnabledClock\n (*)
-  *         AHB3ENR      OSPI1EN       LL_C1_AHB3_GRP1_IsEnabledClock\n (*)
-  *         AHB3ENR      OSPI2EN       LL_C1_AHB3_GRP1_IsEnabledClock\n (*)
-  *         AHB3ENR      IOMNGREN      LL_C1_AHB3_GRP1_IsEnabledClock\n (*)
-  *         AHB3ENR      OTFDEC1EN     LL_C1_AHB3_GRP1_IsEnabledClock\n (*)
-  *         AHB3ENR      OTFDEC2EN     LL_C1_AHB3_GRP1_IsEnabledClock\n (*)
-  *         AHB3ENR      GFXMMU        LL_C1_AHB3_GRP1_IsEnabledClock\n (*)
-  *         AHB3ENR      SDMMC1EN      LL_C1_AHB3_GRP1_IsEnabledClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI    (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1   (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2   (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM  (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU  (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
-  *
-  *         (*) value not defined in all devices.
-  * @retval uint32_t
-*/
-__STATIC_INLINE uint32_t LL_C1_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
-{
-  return ((READ_BIT(RCC_C1->AHB3ENR, Periphs) == Periphs)?1U:0U);
-}
-
-/**
-  * @brief  Disable C1 AHB3 peripherals clock.
-  * @rmtoll AHB3ENR      MDMAEN        LL_C1_AHB3_GRP1_DisableClock\n
-  *         AHB3ENR      DMA2DEN       LL_C1_AHB3_GRP1_DisableClock\n
-  *         AHB3ENR      JPGDECEN      LL_C1_AHB3_GRP1_DisableClock\n
-  *         AHB3ENR      FMCEN         LL_C1_AHB3_GRP1_DisableClock\n
-  *         AHB3ENR      QSPIEN        LL_C1_AHB3_GRP1_DisableClock\n (*)
-  *         AHB3ENR      OSPI1EN       LL_C1_AHB3_GRP1_DisableClock\n (*)
-  *         AHB3ENR      OSPI2EN       LL_C1_AHB3_GRP1_DisableClock\n (*)
-  *         AHB3ENR      IOMNGREN      LL_C1_AHB3_GRP1_DisableClock\n (*)
-  *         AHB3ENR      OTFDEC1EN     LL_C1_AHB3_GRP1_DisableClock\n (*)
-  *         AHB3ENR      OTFDEC2EN     LL_C1_AHB3_GRP1_DisableClock\n (*)
-  *         AHB3ENR      GFXMMU        LL_C1_AHB3_GRP1_DisableClock\n (*)
-  *         AHB3ENR      SDMMC1EN      LL_C1_AHB3_GRP1_DisableClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC  (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI    (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1   (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2   (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM  (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU  (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_C1_AHB3_GRP1_DisableClock(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC_C1->AHB3ENR, Periphs);
-}
-
-/**
-  * @brief  Enable C1 AHB3 peripherals clock during Low Power (Sleep) mode.
-  * @rmtoll AHB3LPENR    MDMALPEN      LL_C1_AHB3_GRP1_EnableClockSleep\n
-  *         AHB3LPENR    DMA2DLPEN     LL_C1_AHB3_GRP1_EnableClockSleep\n
-  *         AHB3LPENR    JPGDECLPEN    LL_C1_AHB3_GRP1_EnableClockSleep\n
-  *         AHB3LPENR    FMCLPEN       LL_C1_AHB3_GRP1_EnableClockSleep\n
-  *         AHB3LPENR    QSPILPEN      LL_C1_AHB3_GRP1_EnableClockSleep\n  (*)
-  *         AHB3LPENR    OSPI1LPEN     LL_C1_AHB3_GRP1_EnableClockSleep\n  (*)
-  *         AHB3LPENR    OSPI2LPEN     LL_C1_AHB3_GRP1_EnableClockSleep\n  (*)
-  *         AHB3LPENR    IOMNGRLPEN    LL_C1_AHB3_GRP1_EnableClockSleep\n  (*)
-  *         AHB3LPENR    OTFDEC1LPEN   LL_C1_AHB3_GRP1_EnableClockSleep\n  (*)
-  *         AHB3LPENR    OTFDEC1LPEN   LL_C1_AHB3_GRP1_EnableClockSleep\n  (*)
-  *         AHB3LPENR    GFXMMULPEN    LL_C1_AHB3_GRP1_EnableClockSleep\n  (*)
-  *         AHB3LPENR    SDMMC1LPEN    LL_C1_AHB3_GRP1_EnableClockSleep\n
-  *         AHB3LPENR    FLASHLPEN     LL_C1_AHB3_GRP1_EnableClockSleep\n
-  *         AHB3LPENR    DTCM1LPEN     LL_C1_AHB3_GRP1_EnableClockSleep\n
-  *         AHB3LPENR    DTCM2LPEN     LL_C1_AHB3_GRP1_EnableClockSleep\n
-  *         AHB3LPENR    ITCMLPEN      LL_C1_AHB3_GRP1_EnableClockSleep\n
-  *         AHB3LPENR    AXISRAMLPEN   LL_C1_AHB3_GRP1_EnableClockSleep
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC   (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI     (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1    (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2    (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU  (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_C1_AHB3_GRP1_EnableClockSleep(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC_C1->AHB3LPENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC_C1->AHB3LPENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Disable C1 AHB3 peripherals clock during Low Power (Sleep) mode.
-  * @rmtoll AHB3LPENR    MDMALPEN      LL_C1_AHB3_GRP1_DisableClockSleep\n
-  *         AHB3LPENR    DMA2DLPEN     LL_C1_AHB3_GRP1_DisableClockSleep\n
-  *         AHB3LPENR    JPGDECLPEN    LL_C1_AHB3_GRP1_DisableClockSleep\n
-  *         AHB3LPENR    FMCLPEN       LL_C1_AHB3_GRP1_DisableClockSleep\n
-  *         AHB3LPENR    QSPILPEN      LL_C1_AHB3_GRP1_DisableClockSleep\n  (*)
-  *         AHB3LPENR    OSPI1LPEN     LL_C1_AHB3_GRP1_DisableClockSleep\n  (*)
-  *         AHB3LPENR    OSPI2LPEN     LL_C1_AHB3_GRP1_DisableClockSleep\n  (*)
-  *         AHB3LPENR    IOMNGRLPEN    LL_C1_AHB3_GRP1_DisableClockSleep\n  (*)
-  *         AHB3LPENR    OTFDEC1LPEN   LL_C1_AHB3_GRP1_DisableClockSleep\n  (*)
-  *         AHB3LPENR    OTFDEC1LPEN   LL_C1_AHB3_GRP1_DisableClockSleep\n  (*)
-  *         AHB3LPENR    GFXMMULPEN    LL_C1_AHB3_GRP1_DisableClockSleep\n  (*)
-  *         AHB3LPENR    SDMMC1LPEN    LL_C1_AHB3_GRP1_DisableClockSleep\n
-  *         AHB3LPENR    FLASHLPEN     LL_C1_AHB3_GRP1_DisableClockSleep\n
-  *         AHB3LPENR    DTCM1LPEN     LL_C1_AHB3_GRP1_DisableClockSleep\n
-  *         AHB3LPENR    DTCM2LPEN     LL_C1_AHB3_GRP1_DisableClockSleep\n
-  *         AHB3LPENR    ITCMLPEN      LL_C1_AHB3_GRP1_DisableClockSleep\n
-  *         AHB3LPENR    AXISRAMLPEN   LL_C1_AHB3_GRP1_DisableClockSleep
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC   (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI     (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1    (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2    (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU  (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_C1_AHB3_GRP1_DisableClockSleep(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC_C1->AHB3LPENR, Periphs);
-}
-
-/**
-  * @}
-  */
-
-/** @addtogroup BUS_LL_EF_AHB1 AHB1
-  * @{
-  */
-
-/**
-  * @brief  Enable C1 AHB1 peripherals clock.
-  * @rmtoll AHB1ENR      DMA1EN        LL_C1_AHB1_GRP1_EnableClock\n
-  *         AHB1ENR      DMA2EN        LL_C1_AHB1_GRP1_EnableClock\n
-  *         AHB1ENR      ADC12EN       LL_C1_AHB1_GRP1_EnableClock\n
-  *         AHB1ENR      CRCEN         LL_C1_AHB1_GRP1_EnableClock\n  (*)
-  *         AHB1ENR      ARTEN         LL_C1_AHB1_GRP1_EnableClock\n  (*)
-  *         AHB1ENR      ETH1MACEN     LL_C1_AHB1_GRP1_EnableClock\n  (*)
-  *         AHB1ENR      ETH1TXEN      LL_C1_AHB1_GRP1_EnableClock\n  (*)
-  *         AHB1ENR      ETH1RXEN      LL_C1_AHB1_GRP1_EnableClock\n  (*)
-  *         AHB1ENR      USB1OTGHSEN   LL_C1_AHB1_GRP1_EnableClock\n
-  *         AHB1ENR      USB1OTGHSULPIEN  LL_C1_AHB1_GRP1_EnableClock\n
-  *         AHB1ENR      USB2OTGHSEN   LL_C1_AHB1_GRP1_EnableClock\n   (*)
-  *         AHB1ENR      USB2OTGHSULPIEN  LL_C1_AHB1_GRP1_EnableClock  (*)
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC  (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX   (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX   (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS     (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_C1_AHB1_GRP1_EnableClock(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC_C1->AHB1ENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC_C1->AHB1ENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Check if C1 AHB1 peripheral clock is enabled or not
-  * @rmtoll AHB1ENR      DMA1EN        LL_C1_AHB1_GRP1_IsEnabledClock\n
-  *         AHB1ENR      DMA2EN        LL_C1_AHB1_GRP1_IsEnabledClock\n
-  *         AHB1ENR      ADC12EN       LL_C1_AHB1_GRP1_IsEnabledClock\n
-  *         AHB1ENR      CRCEN         LL_C1_AHB1_GRP1_IsEnabledClock\n  (*)
-  *         AHB1ENR      ARTEN         LL_C1_AHB1_GRP1_IsEnabledClock\n  (*)
-  *         AHB1ENR      ETH1MACEN     LL_C1_AHB1_GRP1_IsEnabledClock\n  (*)
-  *         AHB1ENR      ETH1TXEN      LL_C1_AHB1_GRP1_IsEnabledClock\n  (*)
-  *         AHB1ENR      ETH1RXEN      LL_C1_AHB1_GRP1_IsEnabledClock\n  (*)
-  *         AHB1ENR      USB1OTGHSEN   LL_C1_AHB1_GRP1_IsEnabledClock\n
-  *         AHB1ENR      USB1OTGHSULPIEN  LL_C1_AHB1_GRP1_IsEnabledClock\n
-  *         AHB1ENR      USB2OTGHSEN   LL_C1_AHB1_GRP1_IsEnabledClock\n  (*)
-  *         AHB1ENR      USB2OTGHSULPIEN  LL_C1_AHB1_GRP1_IsEnabledClock (*)
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC  (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX   (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX   (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS     (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval uint32_t
-*/
-__STATIC_INLINE uint32_t LL_C1_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
-{
-  return ((READ_BIT(RCC_C1->AHB1ENR, Periphs) == Periphs)?1U:0U);
-}
-
-/**
-  * @brief  Disable C1 AHB1 peripherals clock.
-  * @rmtoll AHB1ENR      DMA1EN        LL_C1_AHB1_GRP1_DisableClock\n
-  *         AHB1ENR      DMA2EN        LL_C1_AHB1_GRP1_DisableClock\n
-  *         AHB1ENR      ADC12EN       LL_C1_AHB1_GRP1_DisableClock\n
-  *         AHB1ENR      CRCEN         LL_C1_AHB1_GRP1_DisableClock\n (*)
-  *         AHB1ENR      ARTEN         LL_C1_AHB1_GRP1_DisableClock\n (*)
-  *         AHB1ENR      ETH1MACEN     LL_C1_AHB1_GRP1_DisableClock\n (*)
-  *         AHB1ENR      ETH1TXEN      LL_C1_AHB1_GRP1_DisableClock\n (*)
-  *         AHB1ENR      ETH1RXEN      LL_C1_AHB1_GRP1_DisableClock\n (*)
-  *         AHB1ENR      USB1OTGHSEN   LL_C1_AHB1_GRP1_DisableClock\n
-  *         AHB1ENR      USB1OTGHSULPIEN  LL_C1_AHB1_GRP1_DisableClock\n
-  *         AHB1ENR      USB2OTGHSEN   LL_C1_AHB1_GRP1_DisableClock\n (*)
-  *         AHB1ENR      USB2OTGHSULPIEN  LL_C1_AHB1_GRP1_DisableClock (*)
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC  (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX   (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX   (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS     (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_C1_AHB1_GRP1_DisableClock(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC_C1->AHB1ENR, Periphs);
-}
-
-/**
-  * @brief  Enable C1 AHB1 peripherals clock during Low Power (Sleep) mode.
-  * @rmtoll AHB1LPENR    DMA1LPEN      LL_C1_AHB1_GRP1_EnableClockSleep\n
-  *         AHB1LPENR    DMA2LPEN      LL_C1_AHB1_GRP1_EnableClockSleep\n
-  *         AHB1LPENR    ADC12LPEN     LL_C1_AHB1_GRP1_EnableClockSleep\n
-  *         AHB1LPENR    CRCLPEN       LL_C1_AHB1_GRP1_EnableClockSleep\n (*)
-  *         AHB1LPENR    ARTLPEN       LL_C1_AHB1_GRP1_EnableClockSleep\n (*)
-  *         AHB1LPENR    ETH1MACLPEN   LL_C1_AHB1_GRP1_EnableClockSleep\n (*)
-  *         AHB1LPENR    ETH1TXLPEN    LL_C1_AHB1_GRP1_EnableClockSleep\n (*)
-  *         AHB1LPENR    ETH1RXLPEN    LL_C1_AHB1_GRP1_EnableClockSleep\n (*)
-  *         AHB1LPENR    USB1OTGHSLPEN  LL_C1_AHB1_GRP1_EnableClockSleep\n
-  *         AHB1LPENR    USB1OTGHSULPILPEN  LL_C1_AHB1_GRP1_EnableClockSleep\n
-  *         AHB1LPENR    USB2OTGHSLPEN  LL_C1_AHB1_GRP1_EnableClockSleep\n   (*)
-  *         AHB1LPENR    USB2OTGHSULPILPEN  LL_C1_AHB1_GRP1_EnableClockSleep (*)
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC  (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX   (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX   (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS     (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_C1_AHB1_GRP1_EnableClockSleep(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC_C1->AHB1LPENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC_C1->AHB1LPENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Disable C1 AHB1 peripherals clock during Low Power (Sleep) mode.
-  * @rmtoll AHB1LPENR    DMA1LPEN      LL_C1_AHB1_GRP1_DisableClockSleep\n
-  *         AHB1LPENR    DMA2LPEN      LL_C1_AHB1_GRP1_DisableClockSleep\n
-  *         AHB1LPENR    ADC12LPEN     LL_C1_AHB1_GRP1_DisableClockSleep\n
-  *         AHB1LPENR    CRCLPEN       LL_C1_AHB1_GRP1_DisableClockSleep\n (*)
-  *         AHB1LPENR    ARTLPEN       LL_C1_AHB1_GRP1_DisableClockSleep\n (*)
-  *         AHB1LPENR    ETH1MACLPEN   LL_C1_AHB1_GRP1_DisableClockSleep\n (*)
-  *         AHB1LPENR    ETH1TXLPEN    LL_C1_AHB1_GRP1_DisableClockSleep\n (*)
-  *         AHB1LPENR    ETH1RXLPEN    LL_C1_AHB1_GRP1_DisableClockSleep\n (*)
-  *         AHB1LPENR    USB1OTGHSLPEN  LL_C1_AHB1_GRP1_DisableClockSleep\n
-  *         AHB1LPENR    USB1OTGHSULPILPEN  LL_C1_AHB1_GRP1_DisableClockSleep\n
-  *         AHB1LPENR    USB2OTGHSLPEN  LL_C1_AHB1_GRP1_DisableClockSleep\n   (*)
-  *         AHB1LPENR    USB2OTGHSULPILPEN  LL_C1_AHB1_GRP1_DisableClockSleep (*)
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC  (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX   (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX   (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS     (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_C1_AHB1_GRP1_DisableClockSleep(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC_C1->AHB1LPENR, Periphs);
-}
-
-/**
-  * @}
-  */
-
-/** @addtogroup BUS_LL_EF_AHB2 AHB2
-  * @{
-  */
-
-/**
-  * @brief  Enable C1 AHB2 peripherals clock.
-  * @rmtoll AHB2ENR      DCMIEN        LL_C1_AHB2_GRP1_EnableClock\n
-  *         AHB2ENR      HSEMEN        LL_C1_AHB2_GRP1_EnableClock\n (*)
-  *         AHB2ENR      CRYPEN        LL_C1_AHB2_GRP1_EnableClock\n (*)
-  *         AHB2ENR      HASHEN        LL_C1_AHB2_GRP1_EnableClock\n (*)
-  *         AHB2ENR      RNGEN         LL_C1_AHB2_GRP1_EnableClock\n
-  *         AHB2ENR      SDMMC2EN      LL_C1_AHB2_GRP1_EnableClock\n
-  *         AHB2ENR      BDMA1EN       LL_C1_AHB2_GRP1_EnableClock\n (*)
-  *         AHB2ENR      D2SRAM1EN     LL_C1_AHB2_GRP1_EnableClock\n
-  *         AHB2ENR      D2SRAM2EN     LL_C1_AHB2_GRP1_EnableClock\n
-  *         AHB2ENR      D2SRAM3EN     LL_C1_AHB2_GRP1_EnableClock   (*)
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1  (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_C1_AHB2_GRP1_EnableClock(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC_C1->AHB2ENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC_C1->AHB2ENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Check if C1 AHB2 peripheral clock is enabled or not
-  * @rmtoll AHB2ENR      DCMIEN        LL_C1_AHB2_GRP1_IsEnabledClock\n
-  *         AHB2ENR      HSEMEN        LL_C1_AHB2_GRP1_IsEnabledClock\n (*)
-  *         AHB2ENR      CRYPEN        LL_C1_AHB2_GRP1_IsEnabledClock\n (*)
-  *         AHB2ENR      HASHEN        LL_C1_AHB2_GRP1_IsEnabledClock\n (*)
-  *         AHB2ENR      RNGEN         LL_C1_AHB2_GRP1_IsEnabledClock\n
-  *         AHB2ENR      SDMMC2EN      LL_C1_AHB2_GRP1_IsEnabledClock\n
-  *         AHB2ENR      BDMA1EN       LL_C1_AHB2_GRP1_IsEnabledClock\n (*)
-  *         AHB2ENR      D2SRAM1EN     LL_C1_AHB2_GRP1_IsEnabledClock\n
-  *         AHB2ENR      D2SRAM2EN     LL_C1_AHB2_GRP1_IsEnabledClock\n
-  *         AHB2ENR      D2SRAM3EN     LL_C1_AHB2_GRP1_IsEnabledClock   (*)
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1  (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval uint32_t
-*/
-__STATIC_INLINE uint32_t LL_C1_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
-{
-  return ((READ_BIT(RCC_C1->AHB2ENR, Periphs) == Periphs)?1U:0U);
-}
-
-/**
-  * @brief  Disable C1 AHB2 peripherals clock.
-  * @rmtoll AHB2ENR      DCMIEN        LL_C1_AHB2_GRP1_DisableClock\n
-  *         AHB2ENR      HSEMEN        LL_C1_AHB2_GRP1_DisableClock\n (*)
-  *         AHB2ENR      CRYPEN        LL_C1_AHB2_GRP1_DisableClock\n (*)
-  *         AHB2ENR      HASHEN        LL_C1_AHB2_GRP1_DisableClock\n (*)
-  *         AHB2ENR      RNGEN         LL_C1_AHB2_GRP1_DisableClock\n
-  *         AHB2ENR      SDMMC2EN      LL_C1_AHB2_GRP1_DisableClock\n
-  *         AHB2ENR      BDMA1EN       LL_C1_AHB2_GRP1_DisableClock\n (*)
-  *         AHB2ENR      D2SRAM1EN     LL_C1_AHB2_GRP1_DisableClock\n
-  *         AHB2ENR      D2SRAM2EN     LL_C1_AHB2_GRP1_DisableClock\n
-  *         AHB2ENR      D2SRAM3EN     LL_C1_AHB2_GRP1_DisableClock   (*)
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1  (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_C1_AHB2_GRP1_DisableClock(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC_C1->AHB2ENR, Periphs);
-}
-
-/**
-  * @brief  Enable C1 AHB2 peripherals clock during Low Power (Sleep) mode.
-  * @rmtoll AHB2LPENR    DCMILPEN      LL_C1_AHB2_GRP1_EnableClockSleep\n
-  *         AHB2LPENR    CRYPLPEN      LL_C1_AHB2_GRP1_EnableClockSleep\n (*)
-  *         AHB2LPENR    HASHLPEN      LL_C1_AHB2_GRP1_EnableClockSleep\n (*)
-  *         AHB2LPENR    RNGLPEN       LL_C1_AHB2_GRP1_EnableClockSleep\n
-  *         AHB2LPENR    SDMMC2LPEN    LL_C1_AHB2_GRP1_EnableClockSleep\n
-  *         AHB2LPENR    D2SRAM1LPEN   LL_C1_AHB2_GRP1_EnableClockSleep\n
-  *         AHB2LPENR    BDAM1LPEN     LL_C1_AHB2_GRP1_EnableClockSleep\n (*)
-  *         AHB2LPENR    D2SRAM2LPEN   LL_C1_AHB2_GRP1_EnableClockSleep\n
-  *         AHB2LPENR    D2SRAM3LPEN   LL_C1_AHB2_GRP1_EnableClockSleep   (*)
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_C1_AHB2_GRP1_EnableClockSleep(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC_C1->AHB2LPENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC_C1->AHB2LPENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Disable C1 AHB2 peripherals clock during Low Power (Sleep) mode.
-  * @rmtoll AHB2LPENR    DCMILPEN      LL_C1_AHB2_GRP1_DisableClockSleep\n
-  *         AHB2LPENR    CRYPLPEN      LL_C1_AHB2_GRP1_DisableClockSleep\n (*)
-  *         AHB2LPENR    HASHLPEN      LL_C1_AHB2_GRP1_DisableClockSleep\n (*)
-  *         AHB2LPENR    RNGLPEN       LL_C1_AHB2_GRP1_DisableClockSleep\n
-  *         AHB2LPENR    SDMMC2LPEN    LL_C1_AHB2_GRP1_DisableClockSleep\n
-  *         AHB2LPENR    BDAM1LPEN     LL_C1_AHB2_GRP1_DisableClockSleep\n (*)
-  *         AHB2LPENR    D2SRAM1LPEN   LL_C1_AHB2_GRP1_DisableClockSleep\n
-  *         AHB2LPENR    D2SRAM2LPEN   LL_C1_AHB2_GRP1_DisableClockSleep\n
-  *         AHB2LPENR    D2SRAM3LPEN   LL_C1_AHB2_GRP1_DisableClockSleep
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_C1_AHB2_GRP1_DisableClockSleep(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC_C1->AHB2LPENR, Periphs);
-}
-
-/**
-  * @}
-  */
-
-/** @addtogroup BUS_LL_EF_AHB4 AHB4
-  * @{
-  */
-
-/**
-  * @brief  Enable C1 AHB4 peripherals clock.
-  * @rmtoll AHB4ENR      GPIOAEN       LL_C1_AHB4_GRP1_EnableClock\n
-  *         AHB4ENR      GPIOBEN       LL_C1_AHB4_GRP1_EnableClock\n
-  *         AHB4ENR      GPIOCEN       LL_C1_AHB4_GRP1_EnableClock\n
-  *         AHB4ENR      GPIODEN       LL_C1_AHB4_GRP1_EnableClock\n
-  *         AHB4ENR      GPIOEEN       LL_C1_AHB4_GRP1_EnableClock\n
-  *         AHB4ENR      GPIOFEN       LL_C1_AHB4_GRP1_EnableClock\n
-  *         AHB4ENR      GPIOGEN       LL_C1_AHB4_GRP1_EnableClock\n
-  *         AHB4ENR      GPIOHEN       LL_C1_AHB4_GRP1_EnableClock\n
-  *         AHB4ENR      GPIOIEN       LL_C1_AHB4_GRP1_EnableClock\n
-  *         AHB4ENR      GPIOJEN       LL_C1_AHB4_GRP1_EnableClock\n
-  *         AHB4ENR      GPIOKEN       LL_C1_AHB4_GRP1_EnableClock\n
-  *         AHB4ENR      CRCEN         LL_C1_AHB4_GRP1_EnableClock\n (*)
-  *         AHB4ENR      BDMAEN        LL_C1_AHB4_GRP1_EnableClock\n
-  *         AHB4ENR      ADC3EN        LL_C1_AHB4_GRP1_EnableClock\n (*)
-  *         AHB4ENR      HSEMEN        LL_C1_AHB4_GRP1_EnableClock\n (*)
-  *         AHB4ENR      BKPRAMEN      LL_C1_AHB4_GRP1_EnableClock\n
-  *         AHB4ENR      SRAM4EN       LL_C1_AHB4_GRP1_EnableClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI  (*)
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC   (*)
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM  (*)
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_C1_AHB4_GRP1_EnableClock(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC_C1->AHB4ENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC_C1->AHB4ENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Check if C1 AHB4 peripheral clock is enabled or not
-  * @rmtoll AHB4ENR      GPIOAEN       LL_C1_AHB4_GRP1_IsEnabledClock\n
-  *         AHB4ENR      GPIOBEN       LL_C1_AHB4_GRP1_IsEnabledClock\n
-  *         AHB4ENR      GPIOCEN       LL_C1_AHB4_GRP1_IsEnabledClock\n
-  *         AHB4ENR      GPIODEN       LL_C1_AHB4_GRP1_IsEnabledClock\n
-  *         AHB4ENR      GPIOEEN       LL_C1_AHB4_GRP1_IsEnabledClock\n
-  *         AHB4ENR      GPIOFEN       LL_C1_AHB4_GRP1_IsEnabledClock\n
-  *         AHB4ENR      GPIOGEN       LL_C1_AHB4_GRP1_IsEnabledClock\n
-  *         AHB4ENR      GPIOHEN       LL_C1_AHB4_GRP1_IsEnabledClock\n
-  *         AHB4ENR      GPIOIEN       LL_C1_AHB4_GRP1_IsEnabledClock\n
-  *         AHB4ENR      GPIOJEN       LL_C1_AHB4_GRP1_IsEnabledClock\n
-  *         AHB4ENR      GPIOKEN       LL_C1_AHB4_GRP1_IsEnabledClock\n
-  *         AHB4ENR      CRCEN         LL_C1_AHB4_GRP1_IsEnabledClock\n (*)
-  *         AHB4ENR      BDMAEN        LL_C1_AHB4_GRP1_IsEnabledClock\n
-  *         AHB4ENR      ADC3EN        LL_C1_AHB4_GRP1_IsEnabledClock\n (*)
-  *         AHB4ENR      HSEMEN        LL_C1_AHB4_GRP1_IsEnabledClock\n (*)
-  *         AHB4ENR      BKPRAMEN      LL_C1_AHB4_GRP1_IsEnabledClock\n
-  *         AHB4ENR      SRAM4EN       LL_C1_AHB4_GRP1_IsEnabledClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI  (*)
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC   (*)
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM  (*)
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
-  *
-  *         (*) value not defined in all devices.
-  * @retval uint32_t
-*/
-__STATIC_INLINE uint32_t LL_C1_AHB4_GRP1_IsEnabledClock(uint32_t Periphs)
-{
-  return ((READ_BIT(RCC_C1->AHB4ENR, Periphs) == Periphs)?1U:0U);
-}
-
-/**
-  * @brief  Disable C1 AHB4 peripherals clock.
-  * @rmtoll AHB4ENR      GPIOAEN       LL_C1_AHB4_GRP1_DisableClock\n
-  *         AHB4ENR      GPIOBEN       LL_C1_AHB4_GRP1_DisableClock\n
-  *         AHB4ENR      GPIOCEN       LL_C1_AHB4_GRP1_DisableClock\n
-  *         AHB4ENR      GPIODEN       LL_C1_AHB4_GRP1_DisableClock\n
-  *         AHB4ENR      GPIOEEN       LL_C1_AHB4_GRP1_DisableClock\n
-  *         AHB4ENR      GPIOFEN       LL_C1_AHB4_GRP1_DisableClock\n
-  *         AHB4ENR      GPIOGEN       LL_C1_AHB4_GRP1_DisableClock\n
-  *         AHB4ENR      GPIOHEN       LL_C1_AHB4_GRP1_DisableClock\n
-  *         AHB4ENR      GPIOIEN       LL_C1_AHB4_GRP1_DisableClock\n
-  *         AHB4ENR      GPIOJEN       LL_C1_AHB4_GRP1_DisableClock\n
-  *         AHB4ENR      GPIOKEN       LL_C1_AHB4_GRP1_DisableClock\n
-  *         AHB4ENR      CRCEN         LL_C1_AHB4_GRP1_DisableClock\n (*)
-  *         AHB4ENR      BDMAEN        LL_C1_AHB4_GRP1_DisableClock\n
-  *         AHB4ENR      ADC3EN        LL_C1_AHB4_GRP1_DisableClock\n (*)
-  *         AHB4ENR      HSEMEN        LL_C1_AHB4_GRP1_DisableClock\n (*)
-  *         AHB4ENR      BKPRAMEN      LL_C1_AHB4_GRP1_DisableClock\n
-  *         AHB4ENR      SRAM4EN       LL_C1_AHB4_GRP1_DisableClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI  (*)
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC   (*)
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM  (*)
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_C1_AHB4_GRP1_DisableClock(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC_C1->AHB4ENR, Periphs);
-}
-
-/**
-  * @brief  Enable C1 AHB4 peripherals clock during Low Power (Sleep) mode.
-  * @rmtoll AHB4LPENR    GPIOALPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n
-  *         AHB4LPENR    GPIOBLPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n
-  *         AHB4LPENR    GPIOCLPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n
-  *         AHB4LPENR    GPIODLPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n
-  *         AHB4LPENR    GPIOELPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n
-  *         AHB4LPENR    GPIOFLPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n
-  *         AHB4LPENR    GPIOGLPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n
-  *         AHB4LPENR    GPIOHLPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n
-  *         AHB4LPENR    GPIOILPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n
-  *         AHB4LPENR    GPIOJLPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n
-  *         AHB4LPENR    GPIOKLPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n
-  *         AHB4LPENR    CRCLPEN       LL_C1_AHB4_GRP1_EnableClockSleep\n (*)
-  *         AHB4LPENR    BDMALPEN      LL_C1_AHB4_GRP1_EnableClockSleep\n
-  *         AHB4LPENR    ADC3LPEN      LL_C1_AHB4_GRP1_EnableClockSleep\n (*)
-  *         AHB4LPENR    BKPRAMLPEN    LL_C1_AHB4_GRP1_EnableClockSleep\n
-  *         AHB4LPENR    SRAM4LPEN     LL_C1_AHB4_GRP1_EnableClockSleep
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI  (*)
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC   (*)
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
-  * @retval None
-*/
-__STATIC_INLINE void LL_C1_AHB4_GRP1_EnableClockSleep(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC_C1->AHB4LPENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC_C1->AHB4LPENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Disable C1 AHB4 peripherals clock during Low Power (Sleep) mode.
-  * @rmtoll AHB4LPENR    GPIOALPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n
-  *         AHB4LPENR    GPIOBLPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n
-  *         AHB4LPENR    GPIOCLPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n
-  *         AHB4LPENR    GPIODLPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n
-  *         AHB4LPENR    GPIOELPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n
-  *         AHB4LPENR    GPIOFLPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n
-  *         AHB4LPENR    GPIOGLPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n
-  *         AHB4LPENR    GPIOHLPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n
-  *         AHB4LPENR    GPIOILPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n
-  *         AHB4LPENR    GPIOJLPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n
-  *         AHB4LPENR    GPIOKLPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n
-  *         AHB4LPENR    CRCLPEN       LL_C1_AHB4_GRP1_DisableClockSleep\n (*)
-  *         AHB4LPENR    BDMALPEN      LL_C1_AHB4_GRP1_DisableClockSleep\n
-  *         AHB4LPENR    ADC3LPEN      LL_C1_AHB4_GRP1_DisableClockSleep\n (*)
-  *         AHB4LPENR    BKPRAMLPEN    LL_C1_AHB4_GRP1_DisableClockSleep\n
-  *         AHB4LPENR    SRAM4LPEN     LL_C1_AHB4_GRP1_DisableClockSleep
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI  (*)
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC   (*)
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
-  * @retval None
-*/
-__STATIC_INLINE void LL_C1_AHB4_GRP1_DisableClockSleep(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC_C1->AHB4LPENR, Periphs);
-}
-
-/**
-  * @}
-  */
-
-/** @addtogroup BUS_LL_EF_APB3 APB3
-  * @{
-  */
-
-/**
-  * @brief  Enable C1 APB3 peripherals clock.
-  * @rmtoll APB3ENR      LTDCEN        LL_C1_APB3_GRP1_EnableClock\n (*)
-  *         APB3ENR      DSIEN         LL_C1_APB3_GRP1_EnableClock\n (*)
-  *         APB3ENR      WWDG1EN       LL_C1_APB3_GRP1_EnableClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
-  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
-  *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_C1_APB3_GRP1_EnableClock(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC_C1->APB3ENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC_C1->APB3ENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Check if C1 APB3 peripheral clock is enabled or not
-  * @rmtoll APB3ENR      LTDCEN        LL_C1_APB3_GRP1_IsEnabledClock\n (*)
-  *         APB3ENR      DSIEN         LL_C1_APB3_GRP1_IsEnabledClock\n (*)
-  *         APB3ENR      WWDG1EN       LL_C1_APB3_GRP1_IsEnabledClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
-  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
-  *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
-  *
-  *         (*) value not defined in all devices.
-  * @retval uint32_t
-*/
-__STATIC_INLINE uint32_t LL_C1_APB3_GRP1_IsEnabledClock(uint32_t Periphs)
-{
-  return ((READ_BIT(RCC_C1->APB3ENR, Periphs) == Periphs)?1U:0U);
-}
-
-/**
-  * @brief  Disable C1 APB3 peripherals clock.
-  * @rmtoll APB3ENR      LTDCEN        LL_C1_APB3_GRP1_DisableClock\n (*)
-  *         APB3ENR      DSIEN         LL_C1_APB3_GRP1_DisableClock\n (*)
-  *         APB3ENR      WWDG1EN       LL_C1_APB3_GRP1_DisableClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
-
-  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
-  *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_C1_APB3_GRP1_DisableClock(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC_C1->APB3ENR, Periphs);
-}
-
-/**
-  * @brief  Enable C1 APB3 peripherals clock during Low Power (Sleep) mode.
-  * @rmtoll APB3LPENR    LTDCLPEN      LL_C1_APB3_GRP1_EnableClockSleep\n (*)
-  *         APB3LPENR    DSILPEN       LL_C1_APB3_GRP1_EnableClockSleep\n (*)
-  *         APB3LPENR    WWDG1LPEN     LL_C1_APB3_GRP1_EnableClockSleep
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
-  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
-  *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_C1_APB3_GRP1_EnableClockSleep(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC_C1->APB3LPENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC_C1->APB3LPENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Disable C1 APB3 peripherals clock during Low Power (Sleep) mode.
-  * @rmtoll APB3LPENR    LTDCLPEN      LL_C1_APB3_GRP1_DisableClockSleep\n (*)
-  *         APB3LPENR    DSILPEN       LL_C1_APB3_GRP1_DisableClockSleep\n (*)
-  *         APB3LPENR    WWDG1LPEN     LL_C1_APB3_GRP1_DisableClockSleep
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
-  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
-  *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_C1_APB3_GRP1_DisableClockSleep(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC_C1->APB3LPENR, Periphs);
-}
-
-/**
-  * @}
-  */
-
-/** @addtogroup BUS_LL_EF_APB1 APB1
-  * @{
-  */
-
-/**
-  * @brief  Enable C1 APB1 peripherals clock.
-  * @rmtoll APB1LENR     TIM2EN        LL_C1_APB1_GRP1_EnableClock\n
-  *         APB1LENR     TIM3EN        LL_C1_APB1_GRP1_EnableClock\n
-  *         APB1LENR     TIM4EN        LL_C1_APB1_GRP1_EnableClock\n
-  *         APB1LENR     TIM5EN        LL_C1_APB1_GRP1_EnableClock\n
-  *         APB1LENR     TIM6EN        LL_C1_APB1_GRP1_EnableClock\n
-  *         APB1LENR     TIM7EN        LL_C1_APB1_GRP1_EnableClock\n
-  *         APB1LENR     TIM12EN       LL_C1_APB1_GRP1_EnableClock\n
-  *         APB1LENR     TIM13EN       LL_C1_APB1_GRP1_EnableClock\n
-  *         APB1LENR     TIM14EN       LL_C1_APB1_GRP1_EnableClock\n
-  *         APB1LENR     LPTIM1EN      LL_C1_APB1_GRP1_EnableClock\n
-  *         APB1LENR     WWDG2EN       LL_C1_APB1_GRP1_EnableClock\n (*)
-  *         APB1LENR     SPI2EN        LL_C1_APB1_GRP1_EnableClock\n
-  *         APB1LENR     SPI3EN        LL_C1_APB1_GRP1_EnableClock\n
-  *         APB1LENR     SPDIFRXEN     LL_C1_APB1_GRP1_EnableClock\n
-  *         APB1LENR     USART2EN      LL_C1_APB1_GRP1_EnableClock\n
-  *         APB1LENR     USART3EN      LL_C1_APB1_GRP1_EnableClock\n
-  *         APB1LENR     UART4EN       LL_C1_APB1_GRP1_EnableClock\n
-  *         APB1LENR     UART5EN       LL_C1_APB1_GRP1_EnableClock\n
-  *         APB1LENR     I2C1EN        LL_C1_APB1_GRP1_EnableClock\n
-  *         APB1LENR     I2C2EN        LL_C1_APB1_GRP1_EnableClock\n
-  *         APB1LENR     I2C3EN        LL_C1_APB1_GRP1_EnableClock\n
-  *         APB1LENR     CECEN         LL_C1_APB1_GRP1_EnableClock\n
-  *         APB1LENR     DAC12EN       LL_C1_APB1_GRP1_EnableClock\n
-  *         APB1LENR     UART7EN       LL_C1_APB1_GRP1_EnableClock\n
-  *         APB1LENR     UART8EN       LL_C1_APB1_GRP1_EnableClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
-  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_C1_APB1_GRP1_EnableClock(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC_C1->APB1LENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC_C1->APB1LENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Check if C1 APB1 peripheral clock is enabled or not
-  * @rmtoll APB1LENR     TIM2EN        LL_C1_APB1_GRP1_IsEnabledClock\n
-  *         APB1LENR     TIM3EN        LL_C1_APB1_GRP1_IsEnabledClock\n
-  *         APB1LENR     TIM4EN        LL_C1_APB1_GRP1_IsEnabledClock\n
-  *         APB1LENR     TIM5EN        LL_C1_APB1_GRP1_IsEnabledClock\n
-  *         APB1LENR     TIM6EN        LL_C1_APB1_GRP1_IsEnabledClock\n
-  *         APB1LENR     TIM7EN        LL_C1_APB1_GRP1_IsEnabledClock\n
-  *         APB1LENR     TIM12EN       LL_C1_APB1_GRP1_IsEnabledClock\n
-  *         APB1LENR     TIM13EN       LL_C1_APB1_GRP1_IsEnabledClock\n
-  *         APB1LENR     TIM14EN       LL_C1_APB1_GRP1_IsEnabledClock\n
-  *         APB1LENR     LPTIM1EN      LL_C1_APB1_GRP1_IsEnabledClock\n
-  *         APB1LENR     WWDG2EN       LL_C1_APB1_GRP1_IsEnabledClock\n (*)
-  *         APB1LENR     SPI2EN        LL_C1_APB1_GRP1_IsEnabledClock\n
-  *         APB1LENR     SPI3EN        LL_C1_APB1_GRP1_IsEnabledClock\n
-  *         APB1LENR     SPDIFRXEN     LL_C1_APB1_GRP1_IsEnabledClock\n
-  *         APB1LENR     USART2EN      LL_C1_APB1_GRP1_IsEnabledClock\n
-  *         APB1LENR     USART3EN      LL_C1_APB1_GRP1_IsEnabledClock\n
-  *         APB1LENR     UART4EN       LL_C1_APB1_GRP1_IsEnabledClock\n
-  *         APB1LENR     UART5EN       LL_C1_APB1_GRP1_IsEnabledClock\n
-  *         APB1LENR     I2C1EN        LL_C1_APB1_GRP1_IsEnabledClock\n
-  *         APB1LENR     I2C2EN        LL_C1_APB1_GRP1_IsEnabledClock\n
-  *         APB1LENR     I2C3EN        LL_C1_APB1_GRP1_IsEnabledClock\n
-  *         APB1LENR     CECEN         LL_C1_APB1_GRP1_IsEnabledClock\n
-  *         APB1LENR     DAC12EN       LL_C1_APB1_GRP1_IsEnabledClock\n
-  *         APB1LENR     UART7EN       LL_C1_APB1_GRP1_IsEnabledClock\n
-  *         APB1LENR     UART8EN       LL_C1_APB1_GRP1_IsEnabledClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
-  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
-  *
-  *         (*) value not defined in all devices.
-  * @retval uint32_t
-*/
-__STATIC_INLINE uint32_t LL_C1_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
-{
-  return ((READ_BIT(RCC_C1->APB1LENR, Periphs) == Periphs)?1U:0U);
-}
-
-/**
-  * @brief  Disable C1 APB1 peripherals clock.
-  * @rmtoll APB1LENR     TIM2EN        LL_C1_APB1_GRP1_DisableClock\n
-  *         APB1LENR     TIM3EN        LL_C1_APB1_GRP1_DisableClock\n
-  *         APB1LENR     TIM4EN        LL_C1_APB1_GRP1_DisableClock\n
-  *         APB1LENR     TIM5EN        LL_C1_APB1_GRP1_DisableClock\n
-  *         APB1LENR     TIM6EN        LL_C1_APB1_GRP1_DisableClock\n
-  *         APB1LENR     TIM7EN        LL_C1_APB1_GRP1_DisableClock\n
-  *         APB1LENR     TIM12EN       LL_C1_APB1_GRP1_DisableClock\n
-  *         APB1LENR     TIM13EN       LL_C1_APB1_GRP1_DisableClock\n
-  *         APB1LENR     TIM14EN       LL_C1_APB1_GRP1_DisableClock\n
-  *         APB1LENR     LPTIM1EN      LL_C1_APB1_GRP1_DisableClock\n
-  *         APB1LENR     WWDG2EN       LL_C1_APB1_GRP1_DisableClock\n (*)
-  *         APB1LENR     SPI2EN        LL_C1_APB1_GRP1_DisableClock\n
-  *         APB1LENR     SPI3EN        LL_C1_APB1_GRP1_DisableClock\n
-  *         APB1LENR     SPDIFRXEN     LL_C1_APB1_GRP1_DisableClock\n
-  *         APB1LENR     USART2EN      LL_C1_APB1_GRP1_DisableClock\n
-  *         APB1LENR     USART3EN      LL_C1_APB1_GRP1_DisableClock\n
-  *         APB1LENR     UART4EN       LL_C1_APB1_GRP1_DisableClock\n
-  *         APB1LENR     UART5EN       LL_C1_APB1_GRP1_DisableClock\n
-  *         APB1LENR     I2C1EN        LL_C1_APB1_GRP1_DisableClock\n
-  *         APB1LENR     I2C2EN        LL_C1_APB1_GRP1_DisableClock\n
-  *         APB1LENR     I2C3EN        LL_C1_APB1_GRP1_DisableClock\n
-  *         APB1LENR     CECEN         LL_C1_APB1_GRP1_DisableClock\n
-  *         APB1LENR     DAC12EN       LL_C1_APB1_GRP1_DisableClock\n
-  *         APB1LENR     UART7EN       LL_C1_APB1_GRP1_DisableClock\n
-  *         APB1LENR     UART8EN       LL_C1_APB1_GRP1_DisableClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
-  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
-  *
-  *         (*) value not defined in all devices.
-  * @retval uint32_t
-*/
-__STATIC_INLINE void LL_C1_APB1_GRP1_DisableClock(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC_C1->APB1LENR, Periphs);
-}
-
-/**
-  * @brief  Enable C1 APB1 peripherals clock during Low Power (Sleep) mode.
-  * @rmtoll APB1LLPENR   TIM2LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n
-  *         APB1LLPENR   TIM3LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n
-  *         APB1LLPENR   TIM4LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n
-  *         APB1LLPENR   TIM5LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n
-  *         APB1LLPENR   TIM6LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n
-  *         APB1LLPENR   TIM7LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n
-  *         APB1LLPENR   TIM12LPEN     LL_C1_APB1_GRP1_EnableClockSleep\n
-  *         APB1LLPENR   TIM13LPEN     LL_C1_APB1_GRP1_EnableClockSleep\n
-  *         APB1LLPENR   TIM14LPEN     LL_C1_APB1_GRP1_EnableClockSleep\n
-  *         APB1LLPENR   LPTIM1LPEN    LL_C1_APB1_GRP1_EnableClockSleep\n
-  *         APB1LLPENR   WWDG2LPEN     LL_C1_APB1_GRP1_EnableClockSleep\n (*)
-  *         APB1LLPENR   SPI2LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n
-  *         APB1LLPENR   SPI3LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n
-  *         APB1LLPENR   SPDIFRXLPEN   LL_C1_APB1_GRP1_EnableClockSleep\n
-  *         APB1LLPENR   USART2LPEN    LL_C1_APB1_GRP1_EnableClockSleep\n
-  *         APB1LLPENR   USART3LPEN    LL_C1_APB1_GRP1_EnableClockSleep\n
-  *         APB1LLPENR   UART4LPEN     LL_C1_APB1_GRP1_EnableClockSleep\n
-  *         APB1LLPENR   UART5LPEN     LL_C1_APB1_GRP1_EnableClockSleep\n
-  *         APB1LLPENR   I2C1LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n
-  *         APB1LLPENR   I2C2LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n
-  *         APB1LLPENR   I2C3LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n
-  *         APB1LLPENR   CECLPEN       LL_C1_APB1_GRP1_EnableClockSleep\n
-  *         APB1LLPENR   DAC12LPEN     LL_C1_APB1_GRP1_EnableClockSleep\n
-  *         APB1LLPENR   UART7LPEN     LL_C1_APB1_GRP1_EnableClockSleep\n
-  *         APB1LLPENR   UART8LPEN     LL_C1_APB1_GRP1_EnableClockSleep
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
-  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_C1_APB1_GRP1_EnableClockSleep(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC_C1->APB1LLPENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC_C1->APB1LLPENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Disable C1 APB1 peripherals clock during Low Power (Sleep) mode.
-  * @rmtoll APB1LLPENR   TIM2LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n
-  *         APB1LLPENR   TIM3LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n
-  *         APB1LLPENR   TIM4LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n
-  *         APB1LLPENR   TIM5LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n
-  *         APB1LLPENR   TIM6LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n
-  *         APB1LLPENR   TIM7LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n
-  *         APB1LLPENR   TIM12LPEN     LL_C1_APB1_GRP1_DisableClockSleep\n
-  *         APB1LLPENR   TIM13LPEN     LL_C1_APB1_GRP1_DisableClockSleep\n
-  *         APB1LLPENR   TIM14LPEN     LL_C1_APB1_GRP1_DisableClockSleep\n
-  *         APB1LLPENR   LPTIM1LPEN    LL_C1_APB1_GRP1_DisableClockSleep\n
-  *         APB1LLPENR   WWDG2LPEN     LL_C1_APB1_GRP1_DisableClockSleep\n (*)
-  *         APB1LLPENR   SPI2LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n
-  *         APB1LLPENR   SPI3LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n
-  *         APB1LLPENR   SPDIFRXLPEN   LL_C1_APB1_GRP1_DisableClockSleep\n
-  *         APB1LLPENR   USART2LPEN    LL_C1_APB1_GRP1_DisableClockSleep\n
-  *         APB1LLPENR   USART3LPEN    LL_C1_APB1_GRP1_DisableClockSleep\n
-  *         APB1LLPENR   UART4LPEN     LL_C1_APB1_GRP1_DisableClockSleep\n
-  *         APB1LLPENR   UART5LPEN     LL_C1_APB1_GRP1_DisableClockSleep\n
-  *         APB1LLPENR   I2C1LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n
-  *         APB1LLPENR   I2C2LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n
-  *         APB1LLPENR   I2C3LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n
-  *         APB1LLPENR   CECLPEN       LL_C1_APB1_GRP1_DisableClockSleep\n
-  *         APB1LLPENR   DAC12LPEN     LL_C1_APB1_GRP1_DisableClockSleep\n
-  *         APB1LLPENR   UART7LPEN     LL_C1_APB1_GRP1_DisableClockSleep\n
-  *         APB1LLPENR   UART8LPEN     LL_C1_APB1_GRP1_DisableClockSleep
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
-  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_C1_APB1_GRP1_DisableClockSleep(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC_C1->APB1LLPENR, Periphs);
-}
-
-/**
-  * @brief  Enable C1 APB1 peripherals clock.
-  * @rmtoll APB1HENR     CRSEN         LL_C1_APB1_GRP2_EnableClock\n
-  *         APB1HENR     SWPMIEN       LL_C1_APB1_GRP2_EnableClock\n
-  *         APB1HENR     OPAMPEN       LL_C1_APB1_GRP2_EnableClock\n
-  *         APB1HENR     MDIOSEN       LL_C1_APB1_GRP2_EnableClock\n
-  *         APB1HENR     FDCANEN       LL_C1_APB1_GRP2_EnableClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
-  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
-  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
-  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
-  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
-  *         @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
-  *         @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_C1_APB1_GRP2_EnableClock(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC_C1->APB1HENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC_C1->APB1HENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Check if C1 APB1 peripheral clock is enabled or not
-  * @rmtoll APB1HENR     CRSEN         LL_C1_APB1_GRP2_IsEnabledClock\n
-  *         APB1HENR     SWPMIEN       LL_C1_APB1_GRP2_IsEnabledClock\n
-  *         APB1HENR     OPAMPEN       LL_C1_APB1_GRP2_IsEnabledClock\n
-  *         APB1HENR     MDIOSEN       LL_C1_APB1_GRP2_IsEnabledClock\n
-  *         APB1HENR     FDCANEN       LL_C1_APB1_GRP2_IsEnabledClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
-  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
-  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
-  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
-  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
-  *         @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
-  *         @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval uint32_t
-*/
-__STATIC_INLINE uint32_t LL_C1_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
-{
-  return ((READ_BIT(RCC_C1->APB1HENR, Periphs) == Periphs)?1U:0U);
-}
-
-/**
-  * @brief  Disable C1 APB1 peripherals clock.
-  * @rmtoll APB1HENR     CRSEN         LL_C1_APB1_GRP2_DisableClock\n
-  *         APB1HENR     SWPMIEN       LL_C1_APB1_GRP2_DisableClock\n
-  *         APB1HENR     OPAMPEN       LL_C1_APB1_GRP2_DisableClock\n
-  *         APB1HENR     MDIOSEN       LL_C1_APB1_GRP2_DisableClock\n
-  *         APB1HENR     FDCANEN       LL_C1_APB1_GRP2_DisableClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
-  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
-  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
-  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
-  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
-  *         @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
-  *         @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_C1_APB1_GRP2_DisableClock(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC_C1->APB1HENR, Periphs);
-}
-
-/**
-  * @brief  Enable C1 APB1 peripherals clock during Low Power (Sleep) mode.
-  * @rmtoll APB1HLPENR   CRSLPEN       LL_C1_APB1_GRP2_EnableClockSleep\n
-  *         APB1HLPENR   SWPMILPEN     LL_C1_APB1_GRP2_EnableClockSleep\n
-  *         APB1HLPENR   OPAMPLPEN     LL_C1_APB1_GRP2_EnableClockSleep\n
-  *         APB1HLPENR   MDIOSLPEN     LL_C1_APB1_GRP2_EnableClockSleep\n
-  *         APB1HLPENR   FDCANLPEN     LL_C1_APB1_GRP2_EnableClockSleep
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
-  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
-  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
-  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
-  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
-  *         @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
-  *         @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_C1_APB1_GRP2_EnableClockSleep(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC_C1->APB1HLPENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC_C1->APB1HLPENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Disable C1 APB1 peripherals clock during Low Power (Sleep) mode.
-  * @rmtoll APB1HLPENR   CRSLPEN       LL_C1_APB1_GRP2_DisableClockSleep\n
-  *         APB1HLPENR   SWPMILPEN     LL_C1_APB1_GRP2_DisableClockSleep\n
-  *         APB1HLPENR   OPAMPLPEN     LL_C1_APB1_GRP2_DisableClockSleep\n
-  *         APB1HLPENR   MDIOSLPEN     LL_C1_APB1_GRP2_DisableClockSleep\n
-  *         APB1HLPENR   FDCANLPEN     LL_C1_APB1_GRP2_DisableClockSleep
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
-  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
-  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
-  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
-  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
-  *         @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
-  *         @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_C1_APB1_GRP2_DisableClockSleep(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC_C1->APB1HLPENR, Periphs);
-}
-
-/**
-  * @}
-  */
-
-/** @addtogroup BUS_LL_EF_APB2 APB2
-  * @{
-  */
-
-/**
-  * @brief  Enable C1 APB2 peripherals clock.
-  * @rmtoll APB2ENR      TIM1EN        LL_C1_APB2_GRP1_EnableClock\n
-  *         APB2ENR      TIM8EN        LL_C1_APB2_GRP1_EnableClock\n
-  *         APB2ENR      USART1EN      LL_C1_APB2_GRP1_EnableClock\n
-  *         APB2ENR      USART6EN      LL_C1_APB2_GRP1_EnableClock\n
-  *         APB2ENR      UART9EN       LL_C1_APB2_GRP1_EnableClock\n (*)
-  *         APB2ENR      USART10EN     LL_C1_APB2_GRP1_EnableClock\n (*)
-  *         APB2ENR      SPI1EN        LL_C1_APB2_GRP1_EnableClock\n
-  *         APB2ENR      SPI4EN        LL_C1_APB2_GRP1_EnableClock\n
-  *         APB2ENR      TIM15EN       LL_C1_APB2_GRP1_EnableClock\n
-  *         APB2ENR      TIM16EN       LL_C1_APB2_GRP1_EnableClock\n
-  *         APB2ENR      TIM17EN       LL_C1_APB2_GRP1_EnableClock\n
-  *         APB2ENR      SPI5EN        LL_C1_APB2_GRP1_EnableClock\n
-  *         APB2ENR      SAI1EN        LL_C1_APB2_GRP1_EnableClock\n
-  *         APB2ENR      SAI2EN        LL_C1_APB2_GRP1_EnableClock\n
-  *         APB2ENR      SAI3EN        LL_C1_APB2_GRP1_EnableClock\n (*)
-  *         APB2ENR      DFSDM1EN      LL_C1_APB2_GRP1_EnableClock\n
-  *         APB2ENR      HRTIMEN       LL_C1_APB2_GRP1_EnableClock   (*)
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
-  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9   (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2  (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_C1_APB2_GRP1_EnableClock(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC_C1->APB2ENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC_C1->APB2ENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Check if C1 APB2 peripheral clock is enabled or not
-  * @rmtoll APB2ENR      TIM1EN        LL_C1_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR      TIM8EN        LL_C1_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR      USART1EN      LL_C1_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR      USART6EN      LL_C1_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR      UART9EN       LL_C1_APB2_GRP1_IsEnabledClock\n (*)
-  *         APB2ENR      USART10EN     LL_C1_APB2_GRP1_IsEnabledClock\n (*)
-  *         APB2ENR      SPI1EN        LL_C1_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR      SPI4EN        LL_C1_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR      TIM15EN       LL_C1_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR      TIM16EN       LL_C1_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR      TIM17EN       LL_C1_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR      SPI5EN        LL_C1_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR      SAI1EN        LL_C1_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR      SAI2EN        LL_C1_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR      SAI3EN        LL_C1_APB2_GRP1_IsEnabledClock\n (*)
-  *         APB2ENR      DFSDM1EN      LL_C1_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR      HRTIMEN       LL_C1_APB2_GRP1_IsEnabledClock   (*)
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
-  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9   (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2  (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE uint32_t LL_C1_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
-{
-  return ((READ_BIT(RCC_C1->APB2ENR, Periphs) == Periphs)?1U:0U);
-}
-
-/**
-  * @brief  Disable C1 APB2 peripherals clock.
-  * @rmtoll APB2ENR      TIM1EN        LL_C1_APB2_GRP1_DisableClock\n
-  *         APB2ENR      TIM8EN        LL_C1_APB2_GRP1_DisableClock\n
-  *         APB2ENR      USART1EN      LL_C1_APB2_GRP1_DisableClock\n
-  *         APB2ENR      USART6EN      LL_C1_APB2_GRP1_DisableClock\n
-  *         APB2ENR      UART9EN       LL_C1_APB2_GRP1_DisableClock\n (*)
-  *         APB2ENR      USART10EN     LL_C1_APB2_GRP1_DisableClock\n (*)
-  *         APB2ENR      SPI1EN        LL_C1_APB2_GRP1_DisableClock\n
-  *         APB2ENR      SPI4EN        LL_C1_APB2_GRP1_DisableClock\n
-  *         APB2ENR      TIM15EN       LL_C1_APB2_GRP1_DisableClock\n
-  *         APB2ENR      TIM16EN       LL_C1_APB2_GRP1_DisableClock\n
-  *         APB2ENR      TIM17EN       LL_C1_APB2_GRP1_DisableClock\n
-  *         APB2ENR      SPI5EN        LL_C1_APB2_GRP1_DisableClock\n
-  *         APB2ENR      SAI1EN        LL_C1_APB2_GRP1_DisableClock\n
-  *         APB2ENR      SAI2EN        LL_C1_APB2_GRP1_DisableClock\n
-  *         APB2ENR      SAI3EN        LL_C1_APB2_GRP1_DisableClock\n  (*)
-  *         APB2ENR      DFSDM1EN      LL_C1_APB2_GRP1_DisableClock\n
-  *         APB2ENR      HRTIMEN       LL_C1_APB2_GRP1_DisableClock    (*)
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
-  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9   (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2  (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_C1_APB2_GRP1_DisableClock(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC_C1->APB2ENR, Periphs);
-}
-
-/**
-  * @brief  Enable C1 APB2 peripherals clock during Low Power (Sleep) mode.
-  * @rmtoll APB2LPENR    TIM1LPEN      LL_C1_APB2_GRP1_EnableClockSleep\n
-  *         APB2LPENR    TIM8LPEN      LL_C1_APB2_GRP1_EnableClockSleep\n
-  *         APB2LPENR    USART1LPEN    LL_C1_APB2_GRP1_EnableClockSleep\n
-  *         APB2LPENR    USART6LPEN    LL_C1_APB2_GRP1_EnableClockSleep\n
-  *         APB2ENR      UART9EN       LL_C1_APB2_GRP1_EnableClockSleep\n (*)
-  *         APB2ENR      USART10EN     LL_C1_APB2_GRP1_EnableClockSleep\n (*)
-  *         APB2LPENR    SPI1LPEN      LL_C1_APB2_GRP1_EnableClockSleep\n
-  *         APB2LPENR    SPI4LPEN      LL_C1_APB2_GRP1_EnableClockSleep\n
-  *         APB2LPENR    TIM15LPEN     LL_C1_APB2_GRP1_EnableClockSleep\n
-  *         APB2LPENR    TIM16LPEN     LL_C1_APB2_GRP1_EnableClockSleep\n
-  *         APB2LPENR    TIM17LPEN     LL_C1_APB2_GRP1_EnableClockSleep\n
-  *         APB2LPENR    SPI5LPEN      LL_C1_APB2_GRP1_EnableClockSleep\n
-  *         APB2LPENR    SAI1LPEN      LL_C1_APB2_GRP1_EnableClockSleep\n
-  *         APB2LPENR    SAI2LPEN      LL_C1_APB2_GRP1_EnableClockSleep\n
-  *         APB2LPENR    SAI3LPEN      LL_C1_APB2_GRP1_EnableClockSleep\n (*)
-  *         APB2LPENR    DFSDM1LPEN    LL_C1_APB2_GRP1_EnableClockSleep\n
-  *         APB2LPENR    HRTIMLPEN     LL_C1_APB2_GRP1_EnableClockSleep   (*)
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
-  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9   (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2  (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_C1_APB2_GRP1_EnableClockSleep(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC_C1->APB2LPENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC_C1->APB2LPENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Disable C1 APB2 peripherals clock during Low Power (Sleep) mode.
-  * @rmtoll APB2LPENR    TIM1LPEN      LL_C1_APB2_GRP1_DisableClockSleep\n
-  *         APB2LPENR    TIM8LPEN      LL_C1_APB2_GRP1_DisableClockSleep\n
-  *         APB2LPENR    USART1LPEN    LL_C1_APB2_GRP1_DisableClockSleep\n
-  *         APB2LPENR    UART9LPEN     LL_C1_APB2_GRP1_DisableClockSleep\n (*)
-  *         APB2LPENR    USART10LPEN   LL_C1_APB2_GRP1_DisableClockSleep\n (*)
-  *         APB2LPENR    USART6LPEN    LL_C1_APB2_GRP1_DisableClockSleep\n
-  *         APB2LPENR    SPI1LPEN      LL_C1_APB2_GRP1_DisableClockSleep\n
-  *         APB2LPENR    SPI4LPEN      LL_C1_APB2_GRP1_DisableClockSleep\n
-  *         APB2LPENR    TIM15LPEN     LL_C1_APB2_GRP1_DisableClockSleep\n
-  *         APB2LPENR    TIM16LPEN     LL_C1_APB2_GRP1_DisableClockSleep\n
-  *         APB2LPENR    TIM17LPEN     LL_C1_APB2_GRP1_DisableClockSleep\n
-  *         APB2LPENR    SPI5LPEN      LL_C1_APB2_GRP1_DisableClockSleep\n
-  *         APB2LPENR    SAI1LPEN      LL_C1_APB2_GRP1_DisableClockSleep\n
-  *         APB2LPENR    SAI2LPEN      LL_C1_APB2_GRP1_DisableClockSleep\n
-  *         APB2LPENR    SAI3LPEN      LL_C1_APB2_GRP1_DisableClockSleep\n (*)
-  *         APB2LPENR    DFSDM1LPEN    LL_C1_APB2_GRP1_DisableClockSleep\n
-  *         APB2LPENR    HRTIMLPEN     LL_C1_APB2_GRP1_DisableClockSleep   (*)
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
-  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9   (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2  (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_C1_APB2_GRP1_DisableClockSleep(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC_C1->APB2LPENR, Periphs);
-}
-
-/**
-  * @}
-  */
-
-/** @addtogroup BUS_LL_EF_APB4 APB4
-  * @{
-  */
-
-/**
-  * @brief  Enable C1 APB4 peripherals clock.
-  * @rmtoll APB4ENR      SYSCFGEN      LL_C1_APB4_GRP1_EnableClock\n
-  *         APB4ENR      LPUART1EN     LL_C1_APB4_GRP1_EnableClock\n
-  *         APB4ENR      SPI6EN        LL_C1_APB4_GRP1_EnableClock\n
-  *         APB4ENR      I2C4EN        LL_C1_APB4_GRP1_EnableClock\n
-  *         APB4ENR      LPTIM2EN      LL_C1_APB4_GRP1_EnableClock\n
-  *         APB4ENR      LPTIM3EN      LL_C1_APB4_GRP1_EnableClock\n
-  *         APB4ENR      LPTIM4EN      LL_C1_APB4_GRP1_EnableClock\n (*)
-  *         APB4ENR      LPTIM5EN      LL_C1_APB4_GRP1_EnableClock\n (*)
-  *         APB4ENR      DAC2EN        LL_C1_APB4_GRP1_EnableClock\n (*)
-  *         APB4ENR      COMP12EN      LL_C1_APB4_GRP1_EnableClock\n
-  *         APB4ENR      VREFEN        LL_C1_APB4_GRP1_EnableClock\n
-  *         APB4ENR      RTCAPBEN      LL_C1_APB4_GRP1_EnableClock\n
-  *         APB4ENR      SAI4EN        LL_C1_APB4_GRP1_EnableClock\n (*)
-  *         APB4ENR      DTSEN         LL_C1_APB4_GRP1_EnableClock\n (*)
-  *         APB4ENR      DFSDM2EN      LL_C1_APB4_GRP1_EnableClock   (*)
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
-  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
-  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
-  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
-  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
-  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
-  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
-  *         @arg @ref LL_APB4_GRP1_PERIPH_DTS    (*)
-  *         @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_C1_APB4_GRP1_EnableClock(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC_C1->APB4ENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC_C1->APB4ENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Check if C1 APB4 peripheral clock is enabled or not
-  * @rmtoll APB4ENR      SYSCFGEN      LL_C1_APB4_GRP1_IsEnabledClock\n
-  *         APB4ENR      LPUART1EN     LL_C1_APB4_GRP1_IsEnabledClock\n
-  *         APB4ENR      SPI6EN        LL_C1_APB4_GRP1_IsEnabledClock\n
-  *         APB4ENR      I2C4EN        LL_C1_APB4_GRP1_IsEnabledClock\n
-  *         APB4ENR      LPTIM2EN      LL_C1_APB4_GRP1_IsEnabledClock\n
-  *         APB4ENR      LPTIM3EN      LL_C1_APB4_GRP1_IsEnabledClock\n
-  *         APB4ENR      LPTIM4EN      LL_C1_APB4_GRP1_IsEnabledClock\n (*)
-  *         APB4ENR      LPTIM5EN      LL_C1_APB4_GRP1_IsEnabledClock\n (*)
-  *         APB4ENR      COMP12EN      LL_C1_APB4_GRP1_IsEnabledClock\n
-  *         APB4ENR      VREFEN        LL_C1_APB4_GRP1_IsEnabledClock\n
-  *         APB4ENR      RTCAPBEN      LL_C1_APB4_GRP1_IsEnabledClock\n
-  *         APB4ENR      SAI4EN        LL_C1_APB4_GRP1_IsEnabledClock\n (*)
-  *         APB4ENR      DTSEN         LL_C1_APB4_GRP1_IsEnabledClock\n (*)
-  *         APB4ENR      DFSDM2EN      LL_C1_APB4_GRP1_IsEnabledClock   (*)
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
-  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
-  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
-  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
-  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
-  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
-  *         @arg @ref LL_APB4_GRP1_PERIPH_DTS    (*)
-  *         @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval uint32_t
-*/
-__STATIC_INLINE uint32_t LL_C1_APB4_GRP1_IsEnabledClock(uint32_t Periphs)
-{
-  return ((READ_BIT(RCC_C1->APB4ENR, Periphs) == Periphs)?1U:0U);
-}
-
-/**
-  * @brief  Disable C1 APB4 peripherals clock.
-  * @rmtoll APB4ENR      SYSCFGEN      LL_C1_APB4_GRP1_DisableClock\n
-  *         APB4ENR      LPUART1EN     LL_C1_APB4_GRP1_DisableClock\n
-  *         APB4ENR      SPI6EN        LL_C1_APB4_GRP1_DisableClock\n
-  *         APB4ENR      I2C4EN        LL_C1_APB4_GRP1_DisableClock\n
-  *         APB4ENR      LPTIM2EN      LL_C1_APB4_GRP1_DisableClock\n
-  *         APB4ENR      LPTIM3EN      LL_C1_APB4_GRP1_DisableClock\n
-  *         APB4ENR      LPTIM4EN      LL_C1_APB4_GRP1_DisableClock\n (*)
-  *         APB4ENR      LPTIM5EN      LL_C1_APB4_GRP1_DisableClock\n (*)
-  *         APB4ENR      COMP12EN      LL_C1_APB4_GRP1_DisableClock\n
-  *         APB4ENR      VREFEN        LL_C1_APB4_GRP1_DisableClock\n
-  *         APB4ENR      RTCAPBEN      LL_C1_APB4_GRP1_DisableClock\n
-  *         APB4ENR      SAI4EN        LL_C1_APB4_GRP1_DisableClock\n (*)
-  *         APB4ENR      DTSEN         LL_C1_APB4_GRP1_DisableClock\n (*)
-  *         APB4ENR      DFSDM2EN      LL_C1_APB4_GRP1_DisableClock   (*)
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
-  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
-  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
-  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
-  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
-  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
-  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
-  *         @arg @ref LL_APB4_GRP1_PERIPH_DTS    (*)
-  *         @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_C1_APB4_GRP1_DisableClock(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC_C1->APB4ENR, Periphs);
-}
-
-/**
-  * @brief  Enable C1 APB4 peripherals clock during Low Power (Sleep) mode.
-  * @rmtoll APB4LPENR    SYSCFGLPEN    LL_C1_APB4_GRP1_EnableClockSleep\n
-  *         APB4LPENR    LPUART1LPEN   LL_C1_APB4_GRP1_EnableClockSleep\n
-  *         APB4LPENR    SPI6LPEN      LL_C1_APB4_GRP1_EnableClockSleep\n
-  *         APB4LPENR    I2C4LPEN      LL_C1_APB4_GRP1_EnableClockSleep\n
-  *         APB4LPENR    LPTIM2LPEN    LL_C1_APB4_GRP1_EnableClockSleep\n
-  *         APB4LPENR    LPTIM3LPEN    LL_C1_APB4_GRP1_EnableClockSleep\n (*)
-  *         APB4LPENR    LPTIM4LPEN    LL_C1_APB4_GRP1_EnableClockSleep\n (*)
-  *         APB4LPENR    LPTIM5LPEN    LL_C1_APB4_GRP1_EnableClockSleep\n
-  *         APB4LPENR    COMP12LPEN    LL_C1_APB4_GRP1_EnableClockSleep\n
-  *         APB4LPENR    VREFLPEN      LL_C1_APB4_GRP1_EnableClockSleep\n
-  *         APB4LPENR    RTCAPBLPEN    LL_C1_APB4_GRP1_EnableClockSleep\n
-  *         APB4LPENR    SAI4LPEN      LL_C1_APB4_GRP1_EnableClockSleep\n (*)
-  *         APB4ENR      DTSLPEN       LL_C1_APB4_GRP1_EnableClockSleep\n (*)
-  *         APB4ENR      DFSDM2LPEN    LL_C1_APB4_GRP1_EnableClockSleep   (*)
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
-  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
-  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
-  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
-  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
-  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
-  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
-  *         @arg @ref LL_APB4_GRP1_PERIPH_DTS    (*)
-  *         @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_C1_APB4_GRP1_EnableClockSleep(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC_C1->APB4LPENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC_C1->APB4LPENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Disable C1 APB4 peripherals clock during Low Power (Sleep) mode.
-  * @rmtoll APB4LPENR    SYSCFGLPEN    LL_C1_APB4_GRP1_DisableClockSleep\n
-  *         APB4LPENR    LPUART1LPEN   LL_C1_APB4_GRP1_DisableClockSleep\n
-  *         APB4LPENR    SPI6LPEN      LL_C1_APB4_GRP1_DisableClockSleep\n
-  *         APB4LPENR    I2C4LPEN      LL_C1_APB4_GRP1_DisableClockSleep\n
-  *         APB4LPENR    LPTIM2LPEN    LL_C1_APB4_GRP1_DisableClockSleep\n
-  *         APB4LPENR    LPTIM3LPEN    LL_C1_APB4_GRP1_DisableClockSleep\n
-  *         APB4LPENR    LPTIM4LPEN    LL_C1_APB4_GRP1_DisableClockSleep\n
-  *         APB4LPENR    LPTIM5LPEN    LL_C1_APB4_GRP1_DisableClockSleep\n
-  *         APB4LPENR    COMP12LPEN    LL_C1_APB4_GRP1_DisableClockSleep\n
-  *         APB4LPENR    VREFLPEN      LL_C1_APB4_GRP1_DisableClockSleep\n
-  *         APB4LPENR    RTCAPBLPEN    LL_C1_APB4_GRP1_DisableClockSleep\n
-  *         APB4LPENR    SAI4LPEN      LL_C1_APB4_GRP1_DisableClockSleep\n (*)
-  *         APB4ENR      DTSLPEN       LL_C1_APB4_GRP1_DisableClockSleep\n (*)
-  *         APB4ENR      DFSDM2LPEN    LL_C1_APB4_GRP1_DisableClockSleep   (*)
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
-  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
-  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
-  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
-  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
-  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
-  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
-  *         @arg @ref LL_APB4_GRP1_PERIPH_DTS    (*)
-  *         @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_C1_APB4_GRP1_DisableClockSleep(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC_C1->APB4LPENR, Periphs);
-}
-
-/**
-  * @}
-  */
-
-/** @addtogroup BUS_LL_EF_AHB3 AHB3
-  * @{
-  */
-
-/**
-  * @brief  Enable C2 AHB3 peripherals clock.
-  * @rmtoll AHB3ENR      MDMAEN        LL_C2_AHB3_GRP1_EnableClock\n
-  *         AHB3ENR      DMA2DEN       LL_C2_AHB3_GRP1_EnableClock\n
-  *         AHB3ENR      JPGDECEN      LL_C2_AHB3_GRP1_EnableClock\n
-  *         AHB3ENR      FMCEN         LL_C2_AHB3_GRP1_EnableClock\n
-  *         AHB3ENR      QSPIEN        LL_C2_AHB3_GRP1_EnableClock\n
-  *         AHB3ENR      SDMMC1EN      LL_C2_AHB3_GRP1_EnableClock\n
-  *         AHB3ENR      FLASHEN       LL_C2_AHB3_GRP1_EnableClock\n
-  *         AHB3ENR      DTCM1EN       LL_C2_AHB3_GRP1_EnableClock\n
-  *         AHB3ENR      DTCM2EN       LL_C2_AHB3_GRP1_EnableClock\n
-  *         AHB3ENR      ITCMEN        LL_C2_AHB3_GRP1_EnableClock\n
-  *         AHB3ENR      AXISRAMEN     LL_C2_AHB3_GRP1_EnableClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC  (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
-  * @retval None
-*/
-__STATIC_INLINE void LL_C2_AHB3_GRP1_EnableClock(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC_C2->AHB3ENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC_C2->AHB3ENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Check if C2 AHB3 peripheral clock is enabled or not
-  * @rmtoll AHB3ENR      MDMAEN        LL_C2_AHB3_GRP1_IsEnabledClock\n
-  *         AHB3ENR      DMA2DEN       LL_C2_AHB3_GRP1_IsEnabledClock\n
-  *         AHB3ENR      JPGDECEN      LL_C2_AHB3_GRP1_IsEnabledClock\n
-  *         AHB3ENR      FMCEN         LL_C2_AHB3_GRP1_IsEnabledClock\n
-  *         AHB3ENR      QSPIEN        LL_C2_AHB3_GRP1_IsEnabledClock\n
-  *         AHB3ENR      SDMMC1EN      LL_C2_AHB3_GRP1_IsEnabledClock\n
-  *         AHB3ENR      FLASHEN       LL_C2_AHB3_GRP1_IsEnabledClock\n
-  *         AHB3ENR      DTCM1EN       LL_C2_AHB3_GRP1_IsEnabledClock\n
-  *         AHB3ENR      DTCM2EN       LL_C2_AHB3_GRP1_IsEnabledClock\n
-  *         AHB3ENR      ITCMEN        LL_C2_AHB3_GRP1_IsEnabledClock\n
-  *         AHB3ENR      AXISRAMEN     LL_C2_AHB3_GRP1_IsEnabledClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC  (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI    (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
-  * @retval uint32_t
-*/
-__STATIC_INLINE uint32_t LL_C2_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
-{
-  return ((READ_BIT(RCC_C2->AHB3ENR, Periphs) == Periphs)?1U:0U);
-}
-
-/**
-  * @brief  Disable C2 AHB3 peripherals clock.
-  * @rmtoll AHB3ENR      MDMAEN        LL_C2_AHB3_GRP1_DisableClock\n
-  *         AHB3ENR      DMA2DEN       LL_C2_AHB3_GRP1_DisableClock\n
-  *         AHB3ENR      JPGDECEN      LL_C2_AHB3_GRP1_DisableClock\n
-  *         AHB3ENR      FMCEN         LL_C2_AHB3_GRP1_DisableClock\n
-  *         AHB3ENR      QSPIEN        LL_C2_AHB3_GRP1_DisableClock\n
-  *         AHB3ENR      SDMMC1EN      LL_C2_AHB3_GRP1_DisableClock\n
-  *         AHB3ENR      FLASHEN       LL_C2_AHB3_GRP1_DisableClock\n
-  *         AHB3ENR      DTCM1EN       LL_C2_AHB3_GRP1_DisableClock\n
-  *         AHB3ENR      DTCM2EN       LL_C2_AHB3_GRP1_DisableClock\n
-  *         AHB3ENR      ITCMEN        LL_C2_AHB3_GRP1_DisableClock\n
-  *         AHB3ENR      AXISRAMEN     LL_C2_AHB3_GRP1_DisableClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
-  * @retval None
-*/
-__STATIC_INLINE void LL_C2_AHB3_GRP1_DisableClock(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC_C2->AHB3ENR, Periphs);
-}
-
-/**
-  * @brief  Enable C2 AHB3 peripherals clock during Low Power (Sleep) mode.
-  * @rmtoll AHB3LPENR    MDMALPEN      LL_C2_AHB3_GRP1_EnableClockSleep\n
-  *         AHB3LPENR    DMA2DLPEN     LL_C2_AHB3_GRP1_EnableClockSleep\n
-  *         AHB3LPENR    JPGDECLPEN    LL_C2_AHB3_GRP1_EnableClockSleep\n
-  *         AHB3LPENR    FMCLPEN       LL_C2_AHB3_GRP1_EnableClockSleep\n
-  *         AHB3LPENR    QSPILPEN      LL_C2_AHB3_GRP1_EnableClockSleep\n
-  *         AHB3LPENR    SDMMC1LPEN    LL_C2_AHB3_GRP1_EnableClockSleep\n
-  *         AHB3LPENR    FLASHLPEN     LL_C2_AHB3_GRP1_EnableClockSleep\n
-  *         AHB3LPENR    DTCM1LPEN     LL_C2_AHB3_GRP1_EnableClockSleep\n
-  *         AHB3LPENR    DTCM2LPEN     LL_C2_AHB3_GRP1_EnableClockSleep\n
-  *         AHB3LPENR    ITCMLPEN      LL_C2_AHB3_GRP1_EnableClockSleep\n
-  *         AHB3LPENR    AXISRAMLPEN   LL_C2_AHB3_GRP1_EnableClockSleep
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC  (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
-  * @retval None
-*/
-__STATIC_INLINE void LL_C2_AHB3_GRP1_EnableClockSleep(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC_C2->AHB3LPENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC_C2->AHB3LPENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Disable C2 AHB3 peripherals clock during Low Power (Sleep) mode.
-  * @rmtoll AHB3LPENR    MDMALPEN      LL_C2_AHB3_GRP1_DisableClockSleep\n
-  *         AHB3LPENR    DMA2DLPEN     LL_C2_AHB3_GRP1_DisableClockSleep\n
-  *         AHB3LPENR    JPGDECLPEN    LL_C2_AHB3_GRP1_DisableClockSleep\n
-  *         AHB3LPENR    FMCLPEN       LL_C2_AHB3_GRP1_DisableClockSleep\n
-  *         AHB3LPENR    QSPILPEN      LL_C2_AHB3_GRP1_DisableClockSleep\n
-  *         AHB3LPENR    SDMMC1LPEN    LL_C2_AHB3_GRP1_DisableClockSleep\n
-  *         AHB3LPENR    FLASHLPEN     LL_C2_AHB3_GRP1_DisableClockSleep\n
-  *         AHB3LPENR    DTCM1LPEN     LL_C2_AHB3_GRP1_DisableClockSleep\n
-  *         AHB3LPENR    DTCM2LPEN     LL_C2_AHB3_GRP1_DisableClockSleep\n
-  *         AHB3LPENR    ITCMLPEN      LL_C2_AHB3_GRP1_DisableClockSleep\n
-  *         AHB3LPENR    AXISRAMLPEN   LL_C2_AHB3_GRP1_DisableClockSleep
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC  (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
-  * @retval None
-*/
-__STATIC_INLINE void LL_C2_AHB3_GRP1_DisableClockSleep(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC_C2->AHB3LPENR, Periphs);
-}
-
-/**
-  * @}
-  */
-
-/** @addtogroup BUS_LL_EF_AHB1 AHB1
-  * @{
-  */
-
-/**
-  * @brief  Enable C2 AHB1 peripherals clock.
-  * @rmtoll AHB1ENR      DMA1EN        LL_C2_AHB1_GRP1_EnableClock\n
-  *         AHB1ENR      DMA2EN        LL_C2_AHB1_GRP1_EnableClock\n
-  *         AHB1ENR      ADC12EN       LL_C2_AHB1_GRP1_EnableClock\n
-  *         AHB1ENR      ARTEN         LL_C2_AHB1_GRP1_EnableClock\n
-  *         AHB1ENR      ETH1MACEN     LL_C2_AHB1_GRP1_EnableClock\n
-  *         AHB1ENR      ETH1TXEN      LL_C2_AHB1_GRP1_EnableClock\n
-  *         AHB1ENR      ETH1RXEN      LL_C2_AHB1_GRP1_EnableClock\n
-  *         AHB1ENR      USB1OTGHSEN   LL_C2_AHB1_GRP1_EnableClock\n
-  *         AHB1ENR      USB1OTGHSULPIEN  LL_C2_AHB1_GRP1_EnableClock\n
-  *         AHB1ENR      USB2OTGHSEN   LL_C2_AHB1_GRP1_EnableClock\n
-  *         AHB1ENR      USB2OTGHSULPIEN  LL_C2_AHB1_GRP1_EnableClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX  (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX  (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS  (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
-  *
-  *         (*) value not defined in all devices.  
-  * @retval None
-*/
-__STATIC_INLINE void LL_C2_AHB1_GRP1_EnableClock(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC_C2->AHB1ENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC_C2->AHB1ENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Check if C2 AHB1 peripheral clock is enabled or not
-  * @rmtoll AHB1ENR      DMA1EN        LL_C2_AHB1_GRP1_IsEnabledClock\n
-  *         AHB1ENR      DMA2EN        LL_C2_AHB1_GRP1_IsEnabledClock\n
-  *         AHB1ENR      ADC12EN       LL_C2_AHB1_GRP1_IsEnabledClock\n
-  *         AHB1ENR      ARTEN         LL_C2_AHB1_GRP1_IsEnabledClock\n
-  *         AHB1ENR      ETH1MACEN     LL_C2_AHB1_GRP1_IsEnabledClock\n
-  *         AHB1ENR      ETH1TXEN      LL_C2_AHB1_GRP1_IsEnabledClock\n
-  *         AHB1ENR      ETH1RXEN      LL_C2_AHB1_GRP1_IsEnabledClock\n
-  *         AHB1ENR      USB1OTGHSEN   LL_C2_AHB1_GRP1_IsEnabledClock\n
-  *         AHB1ENR      USB1OTGHSULPIEN  LL_C2_AHB1_GRP1_IsEnabledClock\n
-  *         AHB1ENR      USB2OTGHSEN   LL_C2_AHB1_GRP1_IsEnabledClock\n
-  *         AHB1ENR      USB2OTGHSULPIEN  LL_C2_AHB1_GRP1_IsEnabledClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX  (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX  (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS     (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
-  *
-  *         (*) value not defined in all devices.  
-  * @retval uint32_t
-*/
-__STATIC_INLINE uint32_t LL_C2_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
-{
-  return ((READ_BIT(RCC_C2->AHB1ENR, Periphs) == Periphs)?1U:0U);
-}
-
-/**
-  * @brief  Disable C2 AHB1 peripherals clock.
-  * @rmtoll AHB1ENR      DMA1EN        LL_C2_AHB1_GRP1_DisableClock\n
-  *         AHB1ENR      DMA2EN        LL_C2_AHB1_GRP1_DisableClock\n
-  *         AHB1ENR      ADC12EN       LL_C2_AHB1_GRP1_DisableClock\n
-  *         AHB1ENR      ARTEN         LL_C2_AHB1_GRP1_DisableClock\n
-  *         AHB1ENR      ETH1MACEN     LL_C2_AHB1_GRP1_DisableClock\n
-  *         AHB1ENR      ETH1TXEN      LL_C2_AHB1_GRP1_DisableClock\n
-  *         AHB1ENR      ETH1RXEN      LL_C2_AHB1_GRP1_DisableClock\n
-  *         AHB1ENR      USB1OTGHSEN   LL_C2_AHB1_GRP1_DisableClock\n
-  *         AHB1ENR      USB1OTGHSULPIEN  LL_C2_AHB1_GRP1_DisableClock\n
-  *         AHB1ENR      USB2OTGHSEN   LL_C2_AHB1_GRP1_DisableClock\n
-  *         AHB1ENR      USB2OTGHSULPIEN  LL_C2_AHB1_GRP1_DisableClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC  (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX   (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX   (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS      (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI  (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_C2_AHB1_GRP1_DisableClock(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC_C2->AHB1ENR, Periphs);
-}
-
-/**
-  * @brief  Enable C2 AHB1 peripherals clock during Low Power (Sleep) mode.
-  * @rmtoll AHB1LPENR    DMA1LPEN      LL_C2_AHB1_GRP1_EnableClockSleep\n
-  *         AHB1LPENR    DMA2LPEN      LL_C2_AHB1_GRP1_EnableClockSleep\n
-  *         AHB1LPENR    ADC12LPEN     LL_C2_AHB1_GRP1_EnableClockSleep\n
-  *         AHB1LPENR    ARTLPEN       LL_C2_AHB1_GRP1_EnableClockSleep\n
-  *         AHB1LPENR    ETH1MACLPEN   LL_C2_AHB1_GRP1_EnableClockSleep\n
-  *         AHB1LPENR    ETH1TXLPEN    LL_C2_AHB1_GRP1_EnableClockSleep\n
-  *         AHB1LPENR    ETH1RXLPEN    LL_C2_AHB1_GRP1_EnableClockSleep\n
-  *         AHB1LPENR    USB1OTGHSLPEN  LL_C2_AHB1_GRP1_EnableClockSleep\n
-  *         AHB1LPENR    USB1OTGHSULPILPEN  LL_C2_AHB1_GRP1_EnableClockSleep\n
-  *         AHB1LPENR    USB2OTGHSLPEN  LL_C2_AHB1_GRP1_EnableClockSleep\n
-  *         AHB1LPENR    USB2OTGHSULPILPEN  LL_C2_AHB1_GRP1_EnableClockSleep
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC  (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX   (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX   (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS      (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI  (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_C2_AHB1_GRP1_EnableClockSleep(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC_C2->AHB1LPENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC_C2->AHB1LPENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Disable C2 AHB1 peripherals clock during Low Power (Sleep) mode.
-  * @rmtoll AHB1LPENR    DMA1LPEN      LL_C2_AHB1_GRP1_DisableClockSleep\n
-  *         AHB1LPENR    DMA2LPEN      LL_C2_AHB1_GRP1_DisableClockSleep\n
-  *         AHB1LPENR    ADC12LPEN     LL_C2_AHB1_GRP1_DisableClockSleep\n
-  *         AHB1LPENR    ARTLPEN       LL_C2_AHB1_GRP1_DisableClockSleep\n
-  *         AHB1LPENR    ETH1MACLPEN   LL_C2_AHB1_GRP1_DisableClockSleep\n
-  *         AHB1LPENR    ETH1TXLPEN    LL_C2_AHB1_GRP1_DisableClockSleep\n
-  *         AHB1LPENR    ETH1RXLPEN    LL_C2_AHB1_GRP1_DisableClockSleep\n
-  *         AHB1LPENR    USB1OTGHSLPEN  LL_C2_AHB1_GRP1_DisableClockSleep\n
-  *         AHB1LPENR    USB1OTGHSULPILPEN  LL_C2_AHB1_GRP1_DisableClockSleep\n
-  *         AHB1LPENR    USB2OTGHSLPEN  LL_C2_AHB1_GRP1_DisableClockSleep\n
-  *         AHB1LPENR    USB2OTGHSULPILPEN  LL_C2_AHB1_GRP1_DisableClockSleep
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC  (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX   (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX   (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS      (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI  (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_C2_AHB1_GRP1_DisableClockSleep(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC_C2->AHB1LPENR, Periphs);
-}
-
-/**
-  * @}
-  */
-
-/** @addtogroup BUS_LL_EF_AHB2 AHB2
-  * @{
-  */
-
-/**
-  * @brief  Enable C2 AHB2 peripherals clock.
-  * @rmtoll AHB2ENR      DCMIEN        LL_C2_AHB2_GRP1_EnableClock\n
-  *         AHB2ENR      CRYPEN        LL_C2_AHB2_GRP1_EnableClock\n
-  *         AHB2ENR      HASHEN        LL_C2_AHB2_GRP1_EnableClock\n
-  *         AHB2ENR      RNGEN         LL_C2_AHB2_GRP1_EnableClock\n
-  *         AHB2ENR      SDMMC2EN      LL_C2_AHB2_GRP1_EnableClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_C2_AHB2_GRP1_EnableClock(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC_C2->AHB2ENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC_C2->AHB2ENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Check if C2 AHB2 peripheral clock is enabled or not
-  * @rmtoll AHB2ENR      DCMIEN        LL_C2_AHB2_GRP1_IsEnabledClock\n
-  *         AHB2ENR      CRYPEN        LL_C2_AHB2_GRP1_IsEnabledClock\n
-  *         AHB2ENR      HASHEN        LL_C2_AHB2_GRP1_IsEnabledClock\n
-  *         AHB2ENR      RNGEN         LL_C2_AHB2_GRP1_IsEnabledClock\n
-  *         AHB2ENR      SDMMC2EN      LL_C2_AHB2_GRP1_IsEnabledClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
-  *
-  *         (*) value not defined in all devices.
-  * @retval uint32_t
-*/
-__STATIC_INLINE uint32_t LL_C2_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
-{
-  return ((READ_BIT(RCC_C2->AHB2ENR, Periphs) == Periphs)?1U:0U);
-}
-
-/**
-  * @brief  Disable C2 AHB2 peripherals clock.
-  * @rmtoll AHB2ENR      DCMIEN        LL_C2_AHB2_GRP1_DisableClock\n
-  *         AHB2ENR      CRYPEN        LL_C2_AHB2_GRP1_DisableClock\n
-  *         AHB2ENR      HASHEN        LL_C2_AHB2_GRP1_DisableClock\n
-  *         AHB2ENR      RNGEN         LL_C2_AHB2_GRP1_DisableClock\n
-  *         AHB2ENR      SDMMC2EN      LL_C2_AHB2_GRP1_DisableClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_C2_AHB2_GRP1_DisableClock(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC_C2->AHB2ENR, Periphs);
-}
-
-/**
-  * @brief  Enable C2 AHB2 peripherals clock during Low Power (Sleep) mode.
-  * @rmtoll AHB2LPENR    DCMILPEN      LL_C2_AHB2_GRP1_EnableClockSleep\n
-  *         AHB2LPENR    CRYPLPEN      LL_C2_AHB2_GRP1_EnableClockSleep\n
-  *         AHB2LPENR    HASHLPEN      LL_C2_AHB2_GRP1_EnableClockSleep\n
-  *         AHB2LPENR    RNGLPEN       LL_C2_AHB2_GRP1_EnableClockSleep\n
-  *         AHB2LPENR    SDMMC2LPEN    LL_C2_AHB2_GRP1_EnableClockSleep\n
-  *         AHB2LPENR    D2SRAM1LPEN   LL_C2_AHB2_GRP1_EnableClockSleep\n
-  *         AHB2LPENR    D2SRAM2LPEN   LL_C2_AHB2_GRP1_EnableClockSleep\n
-  *         AHB2LPENR    D2SRAM3LPEN   LL_C2_AHB2_GRP1_EnableClockSleep
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_C2_AHB2_GRP1_EnableClockSleep(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC_C2->AHB2LPENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC_C2->AHB2LPENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Disable C2 AHB2 peripherals clock during Low Power (Sleep) mode.
-  * @rmtoll AHB2LPENR    DCMILPEN      LL_C2_AHB2_GRP1_DisableClockSleep\n
-  *         AHB2LPENR    CRYPLPEN      LL_C2_AHB2_GRP1_DisableClockSleep\n
-  *         AHB2LPENR    HASHLPEN      LL_C2_AHB2_GRP1_DisableClockSleep\n
-  *         AHB2LPENR    RNGLPEN       LL_C2_AHB2_GRP1_DisableClockSleep\n
-  *         AHB2LPENR    SDMMC2LPEN    LL_C2_AHB2_GRP1_DisableClockSleep\n
-  *         AHB2LPENR    D2SRAM1LPEN   LL_C2_AHB2_GRP1_DisableClockSleep\n
-  *         AHB2LPENR    D2SRAM2LPEN   LL_C2_AHB2_GRP1_DisableClockSleep\n
-  *         AHB2LPENR    D2SRAM3LPEN   LL_C2_AHB2_GRP1_DisableClockSleep
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_C2_AHB2_GRP1_DisableClockSleep(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC_C2->AHB2LPENR, Periphs);
-}
-
-/**
-  * @}
-  */
-
-/** @addtogroup BUS_LL_EF_AHB4 AHB4
-  * @{
-  */
-
-/**
-  * @brief  Enable C2 AHB4 peripherals clock.
-  * @rmtoll AHB4ENR      GPIOAEN       LL_C2_AHB4_GRP1_EnableClock\n
-  *         AHB4ENR      GPIOBEN       LL_C2_AHB4_GRP1_EnableClock\n
-  *         AHB4ENR      GPIOCEN       LL_C2_AHB4_GRP1_EnableClock\n
-  *         AHB4ENR      GPIODEN       LL_C2_AHB4_GRP1_EnableClock\n
-  *         AHB4ENR      GPIOEEN       LL_C2_AHB4_GRP1_EnableClock\n
-  *         AHB4ENR      GPIOFEN       LL_C2_AHB4_GRP1_EnableClock\n
-  *         AHB4ENR      GPIOGEN       LL_C2_AHB4_GRP1_EnableClock\n
-  *         AHB4ENR      GPIOHEN       LL_C2_AHB4_GRP1_EnableClock\n
-  *         AHB4ENR      GPIOIEN       LL_C2_AHB4_GRP1_EnableClock\n
-  *         AHB4ENR      GPIOJEN       LL_C2_AHB4_GRP1_EnableClock\n
-  *         AHB4ENR      GPIOKEN       LL_C2_AHB4_GRP1_EnableClock\n
-  *         AHB4ENR      CRCEN         LL_C2_AHB4_GRP1_EnableClock\n
-  *         AHB4ENR      BDMAEN        LL_C2_AHB4_GRP1_EnableClock\n
-  *         AHB4ENR      ADC3EN        LL_C2_AHB4_GRP1_EnableClock\n
-  *         AHB4ENR      HSEMEN        LL_C2_AHB4_GRP1_EnableClock\n
-  *         AHB4ENR      BKPRAMEN      LL_C2_AHB4_GRP1_EnableClock\n
-  *         AHB4ENR      SRAM4EN     LL_C2_AHB4_GRP1_EnableClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI  (*)
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC   (*)
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM  (*)
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_C2_AHB4_GRP1_EnableClock(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC_C2->AHB4ENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC_C2->AHB4ENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Check if C2 AHB4 peripheral clock is enabled or not
-  * @rmtoll AHB4ENR      GPIOAEN       LL_C2_AHB4_GRP1_IsEnabledClock\n
-  *         AHB4ENR      GPIOBEN       LL_C2_AHB4_GRP1_IsEnabledClock\n
-  *         AHB4ENR      GPIOCEN       LL_C2_AHB4_GRP1_IsEnabledClock\n
-  *         AHB4ENR      GPIODEN       LL_C2_AHB4_GRP1_IsEnabledClock\n
-  *         AHB4ENR      GPIOEEN       LL_C2_AHB4_GRP1_IsEnabledClock\n
-  *         AHB4ENR      GPIOFEN       LL_C2_AHB4_GRP1_IsEnabledClock\n
-  *         AHB4ENR      GPIOGEN       LL_C2_AHB4_GRP1_IsEnabledClock\n
-  *         AHB4ENR      GPIOHEN       LL_C2_AHB4_GRP1_IsEnabledClock\n
-  *         AHB4ENR      GPIOIEN       LL_C2_AHB4_GRP1_IsEnabledClock\n
-  *         AHB4ENR      GPIOJEN       LL_C2_AHB4_GRP1_IsEnabledClock\n
-  *         AHB4ENR      GPIOKEN       LL_C2_AHB4_GRP1_IsEnabledClock\n
-  *         AHB4ENR      CRCEN         LL_C2_AHB4_GRP1_IsEnabledClock\n
-  *         AHB4ENR      BDMAEN        LL_C2_AHB4_GRP1_IsEnabledClock\n
-  *         AHB4ENR      ADC3EN        LL_C2_AHB4_GRP1_IsEnabledClock\n
-  *         AHB4ENR      HSEMEN        LL_C2_AHB4_GRP1_IsEnabledClock\n
-  *         AHB4ENR      BKPRAMEN      LL_C2_AHB4_GRP1_IsEnabledClock\n
-  *         AHB4ENR      SRAM4EN       LL_C2_AHB4_GRP1_IsEnabledClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI  (*)
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC   (*)
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM  (*)
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
-  *
-  *         (*) value not defined in all devices.
-  * @retval uint32_t
-*/
-__STATIC_INLINE uint32_t LL_C2_AHB4_GRP1_IsEnabledClock(uint32_t Periphs)
-{
-  return ((READ_BIT(RCC_C2->AHB4ENR, Periphs) == Periphs)?1U:0U);
-}
-
-/**
-  * @brief  Disable C2 AHB4 peripherals clock.
-  * @rmtoll AHB4ENR      GPIOAEN       LL_C2_AHB4_GRP1_DisableClock\n
-  *         AHB4ENR      GPIOBEN       LL_C2_AHB4_GRP1_DisableClock\n
-  *         AHB4ENR      GPIOCEN       LL_C2_AHB4_GRP1_DisableClock\n
-  *         AHB4ENR      GPIODEN       LL_C2_AHB4_GRP1_DisableClock\n
-  *         AHB4ENR      GPIOEEN       LL_C2_AHB4_GRP1_DisableClock\n
-  *         AHB4ENR      GPIOFEN       LL_C2_AHB4_GRP1_DisableClock\n
-  *         AHB4ENR      GPIOGEN       LL_C2_AHB4_GRP1_DisableClock\n
-  *         AHB4ENR      GPIOHEN       LL_C2_AHB4_GRP1_DisableClock\n
-  *         AHB4ENR      GPIOIEN       LL_C2_AHB4_GRP1_DisableClock\n
-  *         AHB4ENR      GPIOJEN       LL_C2_AHB4_GRP1_DisableClock\n
-  *         AHB4ENR      GPIOKEN       LL_C2_AHB4_GRP1_DisableClock\n
-  *         AHB4ENR      CRCEN         LL_C2_AHB4_GRP1_DisableClock\n
-  *         AHB4ENR      BDMAEN        LL_C2_AHB4_GRP1_DisableClock\n
-  *         AHB4ENR      ADC3EN        LL_C2_AHB4_GRP1_DisableClock\n
-  *         AHB4ENR      HSEMEN        LL_C2_AHB4_GRP1_DisableClock\n
-  *         AHB4ENR      BKPRAMEN      LL_C2_AHB4_GRP1_DisableClock\n
-  *         AHB4ENR      SRAM4EN       LL_C2_AHB4_GRP1_DisableClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI  (*)
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC   (*)
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM  (*)
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_C2_AHB4_GRP1_DisableClock(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC_C2->AHB4ENR, Periphs);
-}
-
-/**
-  * @brief  Enable C2 AHB4 peripherals clock during Low Power (Sleep) mode.
-  * @rmtoll AHB4LPENR    GPIOALPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n
-  *         AHB4LPENR    GPIOBLPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n
-  *         AHB4LPENR    GPIOCLPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n
-  *         AHB4LPENR    GPIODLPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n
-  *         AHB4LPENR    GPIOELPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n
-  *         AHB4LPENR    GPIOFLPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n
-  *         AHB4LPENR    GPIOGLPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n
-  *         AHB4LPENR    GPIOHLPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n
-  *         AHB4LPENR    GPIOILPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n
-  *         AHB4LPENR    GPIOJLPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n
-  *         AHB4LPENR    GPIOKLPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n
-  *         AHB4LPENR    CRCLPEN       LL_C2_AHB4_GRP1_EnableClockSleep\n
-  *         AHB4LPENR    BDMALPEN      LL_C2_AHB4_GRP1_EnableClockSleep\n
-  *         AHB4LPENR    ADC3LPEN      LL_C2_AHB4_GRP1_EnableClockSleep\n
-  *         AHB4LPENR    BKPRAMLPEN    LL_C2_AHB4_GRP1_EnableClockSleep\n
-  *         AHB4LPENR    SRAM4LPEN     LL_C2_AHB4_GRP1_EnableClockSleep
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI  (*)
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC   (*)
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
-  * @retval None
-*/
-__STATIC_INLINE void LL_C2_AHB4_GRP1_EnableClockSleep(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC_C2->AHB4LPENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC_C2->AHB4LPENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Disable C2 AHB4 peripherals clock during Low Power (Sleep) mode.
-  * @rmtoll AHB4LPENR    GPIOALPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n
-  *         AHB4LPENR    GPIOBLPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n
-  *         AHB4LPENR    GPIOCLPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n
-  *         AHB4LPENR    GPIODLPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n
-  *         AHB4LPENR    GPIOELPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n
-  *         AHB4LPENR    GPIOFLPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n
-  *         AHB4LPENR    GPIOGLPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n
-  *         AHB4LPENR    GPIOHLPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n
-  *         AHB4LPENR    GPIOILPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n
-  *         AHB4LPENR    GPIOJLPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n
-  *         AHB4LPENR    GPIOKLPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n
-  *         AHB4LPENR    CRCLPEN       LL_C2_AHB4_GRP1_DisableClockSleep\n
-  *         AHB4LPENR    BDMALPEN      LL_C2_AHB4_GRP1_DisableClockSleep\n
-  *         AHB4LPENR    ADC3LPEN      LL_C2_AHB4_GRP1_DisableClockSleep\n
-  *         AHB4LPENR    BKPRAMLPEN    LL_C2_AHB4_GRP1_DisableClockSleep\n
-  *         AHB4LPENR    SRAM4LPEN     LL_C2_AHB4_GRP1_DisableClockSleep
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI  (*)
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC   (*)
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
-  *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
-  * @retval None
-*/
-__STATIC_INLINE void LL_C2_AHB4_GRP1_DisableClockSleep(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC_C2->AHB4LPENR, Periphs);
-}
-
-/**
-  * @}
-  */
-
-/** @addtogroup BUS_LL_EF_APB3 APB3
-  * @{
-  */
-
-/**
-  * @brief  Enable C2 APB3 peripherals clock.
-  * @rmtoll APB3ENR      LTDCEN        LL_C2_APB3_GRP1_EnableClock\n
-  *         APB3ENR      DSIEN         LL_C2_APB3_GRP1_EnableClock\n
-  *         APB3ENR      WWDG1EN       LL_C2_APB3_GRP1_EnableClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
-  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
-  *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_C2_APB3_GRP1_EnableClock(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC_C2->APB3ENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC_C2->APB3ENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Check if C2 APB3 peripheral clock is enabled or not
-  * @rmtoll APB3ENR      LTDCEN        LL_C2_APB3_GRP1_IsEnabledClock\n
-  *         APB3ENR      DSIEN         LL_C2_APB3_GRP1_IsEnabledClock\n
-  *         APB3ENR      WWDG1EN       LL_C2_APB3_GRP1_IsEnabledClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
-  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
-  *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
-  *
-  *         (*) value not defined in all devices.
-  * @retval uint32_t
-*/
-__STATIC_INLINE uint32_t LL_C2_APB3_GRP1_IsEnabledClock(uint32_t Periphs)
-{
-  return ((READ_BIT(RCC_C2->APB3ENR, Periphs) == Periphs)?1U:0U);
-}
-
-/**
-  * @brief  Disable C2 APB3 peripherals clock.
-  * @rmtoll APB3ENR      LTDCEN        LL_C2_APB3_GRP1_DisableClock\n
-  *         APB3ENR      DSIEN         LL_C2_APB3_GRP1_DisableClock\n
-  *         APB3ENR      WWDG1EN       LL_C2_APB3_GRP1_DisableClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
-  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
-  *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_C2_APB3_GRP1_DisableClock(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC_C2->APB3ENR, Periphs);
-}
-
-/**
-  * @brief  Enable C2 APB3 peripherals clock during Low Power (Sleep) mode.
-  * @rmtoll APB3LPENR    LTDCLPEN      LL_C2_APB3_GRP1_EnableClockSleep\n
-  *         APB3LPENR    DSILPEN       LL_C2_APB3_GRP1_EnableClockSleep\n
-  *         APB3LPENR    WWDG1LPEN     LL_C2_APB3_GRP1_EnableClockSleep
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
-  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
-  *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_C2_APB3_GRP1_EnableClockSleep(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC_C2->APB3LPENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC_C2->APB3LPENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Disable C2 APB3 peripherals clock during Low Power (Sleep) mode.
-  * @rmtoll APB3LPENR    LTDCLPEN      LL_C2_APB3_GRP1_DisableClockSleep\n
-  *         APB3LPENR    DSILPEN       LL_C2_APB3_GRP1_DisableClockSleep\n
-  *         APB3LPENR    WWDG1LPEN     LL_C2_APB3_GRP1_DisableClockSleep
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
-  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
-  *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_C2_APB3_GRP1_DisableClockSleep(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC_C2->APB3LPENR, Periphs);
-}
-
-/**
-  * @}
-  */
-
-/** @addtogroup BUS_LL_EF_APB1 APB1
-  * @{
-  */
-
-/**
-  * @brief  Enable C2 APB1 peripherals clock.
-  * @rmtoll APB1LENR     TIM2EN        LL_C2_APB1_GRP1_EnableClock\n
-  *         APB1LENR     TIM3EN        LL_C2_APB1_GRP1_EnableClock\n
-  *         APB1LENR     TIM4EN        LL_C2_APB1_GRP1_EnableClock\n
-  *         APB1LENR     TIM5EN        LL_C2_APB1_GRP1_EnableClock\n
-  *         APB1LENR     TIM6EN        LL_C2_APB1_GRP1_EnableClock\n
-  *         APB1LENR     TIM7EN        LL_C2_APB1_GRP1_EnableClock\n
-  *         APB1LENR     TIM12EN       LL_C2_APB1_GRP1_EnableClock\n
-  *         APB1LENR     TIM13EN       LL_C2_APB1_GRP1_EnableClock\n
-  *         APB1LENR     TIM14EN       LL_C2_APB1_GRP1_EnableClock\n
-  *         APB1LENR     LPTIM1EN      LL_C2_APB1_GRP1_EnableClock\n
-  *         APB1LENR     WWDG2EN       LL_C2_APB1_GRP1_EnableClock\n
-  *         APB1LENR     SPI2EN        LL_C2_APB1_GRP1_EnableClock\n
-  *         APB1LENR     SPI3EN        LL_C2_APB1_GRP1_EnableClock\n
-  *         APB1LENR     SPDIFRXEN     LL_C2_APB1_GRP1_EnableClock\n
-  *         APB1LENR     USART2EN      LL_C2_APB1_GRP1_EnableClock\n
-  *         APB1LENR     USART3EN      LL_C2_APB1_GRP1_EnableClock\n
-  *         APB1LENR     UART4EN       LL_C2_APB1_GRP1_EnableClock\n
-  *         APB1LENR     UART5EN       LL_C2_APB1_GRP1_EnableClock\n
-  *         APB1LENR     I2C1EN        LL_C2_APB1_GRP1_EnableClock\n
-  *         APB1LENR     I2C2EN        LL_C2_APB1_GRP1_EnableClock\n
-  *         APB1LENR     I2C3EN        LL_C2_APB1_GRP1_EnableClock\n
-  *         APB1LENR     CECEN         LL_C2_APB1_GRP1_EnableClock\n
-  *         APB1LENR     DAC12EN       LL_C2_APB1_GRP1_EnableClock\n
-  *         APB1LENR     UART7EN       LL_C2_APB1_GRP1_EnableClock\n
-  *         APB1LENR     UART8EN       LL_C2_APB1_GRP1_EnableClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
-  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_C2_APB1_GRP1_EnableClock(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC_C2->APB1LENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC_C2->APB1LENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Check if C2 APB1 peripheral clock is enabled or not
-  * @rmtoll APB1LENR     TIM2EN        LL_C2_APB1_GRP1_IsEnabledClock\n
-  *         APB1LENR     TIM3EN        LL_C2_APB1_GRP1_IsEnabledClock\n
-  *         APB1LENR     TIM4EN        LL_C2_APB1_GRP1_IsEnabledClock\n
-  *         APB1LENR     TIM5EN        LL_C2_APB1_GRP1_IsEnabledClock\n
-  *         APB1LENR     TIM6EN        LL_C2_APB1_GRP1_IsEnabledClock\n
-  *         APB1LENR     TIM7EN        LL_C2_APB1_GRP1_IsEnabledClock\n
-  *         APB1LENR     TIM12EN       LL_C2_APB1_GRP1_IsEnabledClock\n
-  *         APB1LENR     TIM13EN       LL_C2_APB1_GRP1_IsEnabledClock\n
-  *         APB1LENR     TIM14EN       LL_C2_APB1_GRP1_IsEnabledClock\n
-  *         APB1LENR     LPTIM1EN      LL_C2_APB1_GRP1_IsEnabledClock\n
-  *         APB1LENR     WWDG2EN       LL_C2_APB1_GRP1_IsEnabledClock\n
-  *         APB1LENR     SPI2EN        LL_C2_APB1_GRP1_IsEnabledClock\n
-  *         APB1LENR     SPI3EN        LL_C2_APB1_GRP1_IsEnabledClock\n
-  *         APB1LENR     SPDIFRXEN     LL_C2_APB1_GRP1_IsEnabledClock\n
-  *         APB1LENR     USART2EN      LL_C2_APB1_GRP1_IsEnabledClock\n
-  *         APB1LENR     USART3EN      LL_C2_APB1_GRP1_IsEnabledClock\n
-  *         APB1LENR     UART4EN       LL_C2_APB1_GRP1_IsEnabledClock\n
-  *         APB1LENR     UART5EN       LL_C2_APB1_GRP1_IsEnabledClock\n
-  *         APB1LENR     I2C1EN        LL_C2_APB1_GRP1_IsEnabledClock\n
-  *         APB1LENR     I2C2EN        LL_C2_APB1_GRP1_IsEnabledClock\n
-  *         APB1LENR     I2C3EN        LL_C2_APB1_GRP1_IsEnabledClock\n
-  *         APB1LENR     CECEN         LL_C2_APB1_GRP1_IsEnabledClock\n
-  *         APB1LENR     DAC12EN       LL_C2_APB1_GRP1_IsEnabledClock\n
-  *         APB1LENR     UART7EN       LL_C2_APB1_GRP1_IsEnabledClock\n
-  *         APB1LENR     UART8EN       LL_C2_APB1_GRP1_IsEnabledClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
-  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
-  *
-  *         (*) value not defined in all devices.
-  * @retval uint32_t
-*/
-__STATIC_INLINE uint32_t LL_C2_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
-{
-  return ((READ_BIT(RCC_C2->APB1LENR, Periphs) == Periphs)?1U:0U);
-}
-
-/**
-  * @brief  Disable C2 APB1 peripherals clock.
-  * @rmtoll APB1LENR     TIM2EN        LL_C2_APB1_GRP1_DisableClock\n
-  *         APB1LENR     TIM3EN        LL_C2_APB1_GRP1_DisableClock\n
-  *         APB1LENR     TIM4EN        LL_C2_APB1_GRP1_DisableClock\n
-  *         APB1LENR     TIM5EN        LL_C2_APB1_GRP1_DisableClock\n
-  *         APB1LENR     TIM6EN        LL_C2_APB1_GRP1_DisableClock\n
-  *         APB1LENR     TIM7EN        LL_C2_APB1_GRP1_DisableClock\n
-  *         APB1LENR     TIM12EN       LL_C2_APB1_GRP1_DisableClock\n
-  *         APB1LENR     TIM13EN       LL_C2_APB1_GRP1_DisableClock\n
-  *         APB1LENR     TIM14EN       LL_C2_APB1_GRP1_DisableClock\n
-  *         APB1LENR     LPTIM1EN      LL_C2_APB1_GRP1_DisableClock\n
-  *         APB1LENR     WWDG2EN       LL_C2_APB1_GRP1_DisableClock\n
-  *         APB1LENR     SPI2EN        LL_C2_APB1_GRP1_DisableClock\n
-  *         APB1LENR     SPI3EN        LL_C2_APB1_GRP1_DisableClock\n
-  *         APB1LENR     SPDIFRXEN     LL_C2_APB1_GRP1_DisableClock\n
-  *         APB1LENR     USART2EN      LL_C2_APB1_GRP1_DisableClock\n
-  *         APB1LENR     USART3EN      LL_C2_APB1_GRP1_DisableClock\n
-  *         APB1LENR     UART4EN       LL_C2_APB1_GRP1_DisableClock\n
-  *         APB1LENR     UART5EN       LL_C2_APB1_GRP1_DisableClock\n
-  *         APB1LENR     I2C1EN        LL_C2_APB1_GRP1_DisableClock\n
-  *         APB1LENR     I2C2EN        LL_C2_APB1_GRP1_DisableClock\n
-  *         APB1LENR     I2C3EN        LL_C2_APB1_GRP1_DisableClock\n
-  *         APB1LENR     CECEN         LL_C2_APB1_GRP1_DisableClock\n
-  *         APB1LENR     DAC12EN       LL_C2_APB1_GRP1_DisableClock\n
-  *         APB1LENR     UART7EN       LL_C2_APB1_GRP1_DisableClock\n
-  *         APB1LENR     UART8EN       LL_C2_APB1_GRP1_DisableClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
-  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_C2_APB1_GRP1_DisableClock(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC_C2->APB1LENR, Periphs);
-}
-
-/**
-  * @brief  Enable C2 APB1 peripherals clock during Low Power (Sleep) mode.
-  * @rmtoll APB1LLPENR   TIM2LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n
-  *         APB1LLPENR   TIM3LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n
-  *         APB1LLPENR   TIM4LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n
-  *         APB1LLPENR   TIM5LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n
-  *         APB1LLPENR   TIM6LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n
-  *         APB1LLPENR   TIM7LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n
-  *         APB1LLPENR   TIM12LPEN     LL_C2_APB1_GRP1_EnableClockSleep\n
-  *         APB1LLPENR   TIM13LPEN     LL_C2_APB1_GRP1_EnableClockSleep\n
-  *         APB1LLPENR   TIM14LPEN     LL_C2_APB1_GRP1_EnableClockSleep\n
-  *         APB1LLPENR   LPTIM1LPEN    LL_C2_APB1_GRP1_EnableClockSleep\n
-  *         APB1LLPENR   WWDG2LPEN     LL_C2_APB1_GRP1_EnableClockSleep\n
-  *         APB1LLPENR   SPI2LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n
-  *         APB1LLPENR   SPI3LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n
-  *         APB1LLPENR   SPDIFRXLPEN   LL_C2_APB1_GRP1_EnableClockSleep\n
-  *         APB1LLPENR   USART2LPEN    LL_C2_APB1_GRP1_EnableClockSleep\n
-  *         APB1LLPENR   USART3LPEN    LL_C2_APB1_GRP1_EnableClockSleep\n
-  *         APB1LLPENR   UART4LPEN     LL_C2_APB1_GRP1_EnableClockSleep\n
-  *         APB1LLPENR   UART5LPEN     LL_C2_APB1_GRP1_EnableClockSleep\n
-  *         APB1LLPENR   I2C1LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n
-  *         APB1LLPENR   I2C2LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n
-  *         APB1LLPENR   I2C3LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n
-  *         APB1LLPENR   CECLPEN       LL_C2_APB1_GRP1_EnableClockSleep\n
-  *         APB1LLPENR   DAC12LPEN     LL_C2_APB1_GRP1_EnableClockSleep\n
-  *         APB1LLPENR   UART7LPEN     LL_C2_APB1_GRP1_EnableClockSleep\n
-  *         APB1LLPENR   UART8LPEN     LL_C2_APB1_GRP1_EnableClockSleep
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
-  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_C2_APB1_GRP1_EnableClockSleep(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC_C2->APB1LLPENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC_C2->APB1LLPENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Disable C2 APB1 peripherals clock during Low Power (Sleep) mode.
-  * @rmtoll APB1LLPENR   TIM2LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n
-  *         APB1LLPENR   TIM3LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n
-  *         APB1LLPENR   TIM4LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n
-  *         APB1LLPENR   TIM5LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n
-  *         APB1LLPENR   TIM6LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n
-  *         APB1LLPENR   TIM7LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n
-  *         APB1LLPENR   TIM12LPEN     LL_C2_APB1_GRP1_DisableClockSleep\n
-  *         APB1LLPENR   TIM13LPEN     LL_C2_APB1_GRP1_DisableClockSleep\n
-  *         APB1LLPENR   TIM14LPEN     LL_C2_APB1_GRP1_DisableClockSleep\n
-  *         APB1LLPENR   LPTIM1LPEN    LL_C2_APB1_GRP1_DisableClockSleep\n
-  *         APB1LLPENR   WWDG2LPEN     LL_C2_APB1_GRP1_DisableClockSleep\n
-  *         APB1LLPENR   SPI2LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n
-  *         APB1LLPENR   SPI3LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n
-  *         APB1LLPENR   SPDIFRXLPEN   LL_C2_APB1_GRP1_DisableClockSleep\n
-  *         APB1LLPENR   USART2LPEN    LL_C2_APB1_GRP1_DisableClockSleep\n
-  *         APB1LLPENR   USART3LPEN    LL_C2_APB1_GRP1_DisableClockSleep\n
-  *         APB1LLPENR   UART4LPEN     LL_C2_APB1_GRP1_DisableClockSleep\n
-  *         APB1LLPENR   UART5LPEN     LL_C2_APB1_GRP1_DisableClockSleep\n
-  *         APB1LLPENR   I2C1LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n
-  *         APB1LLPENR   I2C2LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n
-  *         APB1LLPENR   I2C3LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n
-  *         APB1LLPENR   CECLPEN       LL_C2_APB1_GRP1_DisableClockSleep\n
-  *         APB1LLPENR   DAC12LPEN     LL_C2_APB1_GRP1_DisableClockSleep\n
-  *         APB1LLPENR   UART7LPEN     LL_C2_APB1_GRP1_DisableClockSleep\n
-  *         APB1LLPENR   UART8LPEN     LL_C2_APB1_GRP1_DisableClockSleep
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
-  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_C2_APB1_GRP1_DisableClockSleep(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC_C2->APB1LLPENR, Periphs);
-}
-
-/**
-  * @brief  Enable C2 APB1 peripherals clock.
-  * @rmtoll APB1HENR     CRSEN         LL_C2_APB1_GRP2_EnableClock\n
-  *         APB1HENR     SWPMIEN       LL_C2_APB1_GRP2_EnableClock\n
-  *         APB1HENR     OPAMPEN       LL_C2_APB1_GRP2_EnableClock\n
-  *         APB1HENR     MDIOSEN       LL_C2_APB1_GRP2_EnableClock\n
-  *         APB1HENR     FDCANEN       LL_C2_APB1_GRP2_EnableClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
-  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
-  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
-  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
-  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
-  *         @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
-  *         @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_C2_APB1_GRP2_EnableClock(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC_C2->APB1HENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC_C2->APB1HENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Check if C2 APB1 peripheral clock is enabled or not
-  * @rmtoll APB1HENR     CRSEN         LL_C2_APB1_GRP2_IsEnabledClock\n
-  *         APB1HENR     SWPMIEN       LL_C2_APB1_GRP2_IsEnabledClock\n
-  *         APB1HENR     OPAMPEN       LL_C2_APB1_GRP2_IsEnabledClock\n
-  *         APB1HENR     MDIOSEN       LL_C2_APB1_GRP2_IsEnabledClock\n
-  *         APB1HENR     FDCANEN       LL_C2_APB1_GRP2_IsEnabledClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
-  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
-  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
-  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
-  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
-  *         @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
-  *         @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval uint32_t
-*/
-__STATIC_INLINE uint32_t LL_C2_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
-{
-  return ((READ_BIT(RCC_C2->APB1HENR, Periphs) == Periphs)?1U:0U);
-}
-
-/**
-  * @brief  Disable C2 APB1 peripherals clock.
-  * @rmtoll APB1HENR     CRSEN         LL_C2_APB1_GRP2_DisableClock\n
-  *         APB1HENR     SWPMIEN       LL_C2_APB1_GRP2_DisableClock\n
-  *         APB1HENR     OPAMPEN       LL_C2_APB1_GRP2_DisableClock\n
-  *         APB1HENR     MDIOSEN       LL_C2_APB1_GRP2_DisableClock\n
-  *         APB1HENR     FDCANEN       LL_C2_APB1_GRP2_DisableClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
-  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
-  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
-  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
-  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
-  *         @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
-  *         @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_C2_APB1_GRP2_DisableClock(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC_C2->APB1HENR, Periphs);
-}
-
-/**
-  * @brief  Enable C2 APB1 peripherals clock during Low Power (Sleep) mode.
-  * @rmtoll APB1HLPENR   CRSLPEN       LL_C2_APB1_GRP2_EnableClockSleep\n
-  *         APB1HLPENR   SWPMILPEN     LL_C2_APB1_GRP2_EnableClockSleep\n
-  *         APB1HLPENR   OPAMPLPEN     LL_C2_APB1_GRP2_EnableClockSleep\n
-  *         APB1HLPENR   MDIOSLPEN     LL_C2_APB1_GRP2_EnableClockSleep\n
-  *         APB1HLPENR   FDCANLPEN     LL_C2_APB1_GRP2_EnableClockSleep
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
-  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
-  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
-  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
-  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
-  *         @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
-  *         @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_C2_APB1_GRP2_EnableClockSleep(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC_C2->APB1HLPENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC_C2->APB1HLPENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Disable C2 APB1 peripherals clock during Low Power (Sleep) mode.
-  * @rmtoll APB1HLPENR   CRSLPEN       LL_C2_APB1_GRP2_DisableClockSleep\n
-  *         APB1HLPENR   SWPMILPEN     LL_C2_APB1_GRP2_DisableClockSleep\n
-  *         APB1HLPENR   OPAMPLPEN     LL_C2_APB1_GRP2_DisableClockSleep\n
-  *         APB1HLPENR   MDIOSLPEN     LL_C2_APB1_GRP2_DisableClockSleep\n
-  *         APB1HLPENR   FDCANLPEN     LL_C2_APB1_GRP2_DisableClockSleep
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
-  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
-  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
-  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
-  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
-  *         @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
-  *         @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_C2_APB1_GRP2_DisableClockSleep(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC_C2->APB1HLPENR, Periphs);
-}
-
-/**
-  * @}
-  */
-
-/** @addtogroup BUS_LL_EF_APB2 APB2
-  * @{
-  */
-
-/**
-  * @brief  Enable C2 APB2 peripherals clock.
-  * @rmtoll APB2ENR      TIM1EN        LL_C2_APB2_GRP1_EnableClock\n
-  *         APB2ENR      TIM8EN        LL_C2_APB2_GRP1_EnableClock\n
-  *         APB2ENR      USART1EN      LL_C2_APB2_GRP1_EnableClock\n
-  *         APB2ENR      USART6EN      LL_C2_APB2_GRP1_EnableClock\n
-  *         APB2ENR      SPI1EN        LL_C2_APB2_GRP1_EnableClock\n
-  *         APB2ENR      SPI4EN        LL_C2_APB2_GRP1_EnableClock\n
-  *         APB2ENR      TIM15EN       LL_C2_APB2_GRP1_EnableClock\n
-  *         APB2ENR      TIM16EN       LL_C2_APB2_GRP1_EnableClock\n
-  *         APB2ENR      TIM17EN       LL_C2_APB2_GRP1_EnableClock\n
-  *         APB2ENR      SPI5EN        LL_C2_APB2_GRP1_EnableClock\n
-  *         APB2ENR      SAI1EN        LL_C2_APB2_GRP1_EnableClock\n
-  *         APB2ENR      SAI2EN        LL_C2_APB2_GRP1_EnableClock\n
-  *         APB2ENR      SAI3EN        LL_C2_APB2_GRP1_EnableClock\n
-  *         APB2ENR      DFSDM1EN      LL_C2_APB2_GRP1_EnableClock\n
-  *         APB2ENR      HRTIMEN       LL_C2_APB2_GRP1_EnableClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2  (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
-  *
-  *         (*) value not defined in all devices.
-
-  * @retval None
-*/
-__STATIC_INLINE void LL_C2_APB2_GRP1_EnableClock(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC_C2->APB2ENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC_C2->APB2ENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Check if C2 APB2 peripheral clock is enabled or not
-  * @rmtoll APB2ENR      TIM1EN        LL_C2_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR      TIM8EN        LL_C2_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR      USART1EN      LL_C2_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR      USART6EN      LL_C2_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR      SPI1EN        LL_C2_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR      SPI4EN        LL_C2_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR      TIM15EN       LL_C2_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR      TIM16EN       LL_C2_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR      TIM17EN       LL_C2_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR      SPI5EN        LL_C2_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR      SAI1EN        LL_C2_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR      SAI2EN        LL_C2_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR      SAI3EN        LL_C2_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR      DFSDM1EN      LL_C2_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR      HRTIMEN       LL_C2_APB2_GRP1_IsEnabledClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2  (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval uint32_t
-*/
-__STATIC_INLINE uint32_t LL_C2_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
-{
-  return ((READ_BIT(RCC_C2->APB2ENR, Periphs) == Periphs)?1U:0U);
-}
-
-/**
-  * @brief  Disable C2 APB2 peripherals clock.
-  * @rmtoll APB2ENR      TIM1EN        LL_C2_APB2_GRP1_DisableClock\n
-  *         APB2ENR      TIM8EN        LL_C2_APB2_GRP1_DisableClock\n
-  *         APB2ENR      USART1EN      LL_C2_APB2_GRP1_DisableClock\n
-  *         APB2ENR      USART6EN      LL_C2_APB2_GRP1_DisableClock\n
-  *         APB2ENR      SPI1EN        LL_C2_APB2_GRP1_DisableClock\n
-  *         APB2ENR      SPI4EN        LL_C2_APB2_GRP1_DisableClock\n
-  *         APB2ENR      TIM15EN       LL_C2_APB2_GRP1_DisableClock\n
-  *         APB2ENR      TIM16EN       LL_C2_APB2_GRP1_DisableClock\n
-  *         APB2ENR      TIM17EN       LL_C2_APB2_GRP1_DisableClock\n
-  *         APB2ENR      SPI5EN        LL_C2_APB2_GRP1_DisableClock\n
-  *         APB2ENR      SAI1EN        LL_C2_APB2_GRP1_DisableClock\n
-  *         APB2ENR      SAI2EN        LL_C2_APB2_GRP1_DisableClock\n
-  *         APB2ENR      SAI3EN        LL_C2_APB2_GRP1_DisableClock\n
-  *         APB2ENR      DFSDM1EN      LL_C2_APB2_GRP1_DisableClock\n
-  *         APB2ENR      HRTIMEN       LL_C2_APB2_GRP1_DisableClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2  (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_C2_APB2_GRP1_DisableClock(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC_C2->APB2ENR, Periphs);
-}
-
-/**
-  * @brief  Enable C2 APB2 peripherals clock during Low Power (Sleep) mode.
-  * @rmtoll APB2LPENR    TIM1LPEN      LL_C2_APB2_GRP1_EnableClockSleep\n
-  *         APB2LPENR    TIM8LPEN      LL_C2_APB2_GRP1_EnableClockSleep\n
-  *         APB2LPENR    USART1LPEN    LL_C2_APB2_GRP1_EnableClockSleep\n
-  *         APB2LPENR    USART6LPEN    LL_C2_APB2_GRP1_EnableClockSleep\n
-  *         APB2LPENR    SPI1LPEN      LL_C2_APB2_GRP1_EnableClockSleep\n
-  *         APB2LPENR    SPI4LPEN      LL_C2_APB2_GRP1_EnableClockSleep\n
-  *         APB2LPENR    TIM15LPEN     LL_C2_APB2_GRP1_EnableClockSleep\n
-  *         APB2LPENR    TIM16LPEN     LL_C2_APB2_GRP1_EnableClockSleep\n
-  *         APB2LPENR    TIM17LPEN     LL_C2_APB2_GRP1_EnableClockSleep\n
-  *         APB2LPENR    SPI5LPEN      LL_C2_APB2_GRP1_EnableClockSleep\n
-  *         APB2LPENR    SAI1LPEN      LL_C2_APB2_GRP1_EnableClockSleep\n
-  *         APB2LPENR    SAI2LPEN      LL_C2_APB2_GRP1_EnableClockSleep\n
-  *         APB2LPENR    SAI3LPEN      LL_C2_APB2_GRP1_EnableClockSleep\n
-  *         APB2LPENR    DFSDM1LPEN    LL_C2_APB2_GRP1_EnableClockSleep\n
-  *         APB2LPENR    HRTIMLPEN     LL_C2_APB2_GRP1_EnableClockSleep
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2  (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_C2_APB2_GRP1_EnableClockSleep(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC_C2->APB2LPENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC_C2->APB2LPENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Disable C2 APB2 peripherals clock during Low Power (Sleep) mode.
-  * @rmtoll APB2LPENR    TIM1LPEN      LL_C2_APB2_GRP1_DisableClockSleep\n
-  *         APB2LPENR    TIM8LPEN      LL_C2_APB2_GRP1_DisableClockSleep\n
-  *         APB2LPENR    USART1LPEN    LL_C2_APB2_GRP1_DisableClockSleep\n
-  *         APB2LPENR    USART6LPEN    LL_C2_APB2_GRP1_DisableClockSleep\n
-  *         APB2LPENR    SPI1LPEN      LL_C2_APB2_GRP1_DisableClockSleep\n
-  *         APB2LPENR    SPI4LPEN      LL_C2_APB2_GRP1_DisableClockSleep\n
-  *         APB2LPENR    TIM15LPEN     LL_C2_APB2_GRP1_DisableClockSleep\n
-  *         APB2LPENR    TIM16LPEN     LL_C2_APB2_GRP1_DisableClockSleep\n
-  *         APB2LPENR    TIM17LPEN     LL_C2_APB2_GRP1_DisableClockSleep\n
-  *         APB2LPENR    SPI5LPEN      LL_C2_APB2_GRP1_DisableClockSleep\n
-  *         APB2LPENR    SAI1LPEN      LL_C2_APB2_GRP1_DisableClockSleep\n
-  *         APB2LPENR    SAI2LPEN      LL_C2_APB2_GRP1_DisableClockSleep\n
-  *         APB2LPENR    SAI3LPEN      LL_C2_APB2_GRP1_DisableClockSleep\n
-  *         APB2LPENR    DFSDM1LPEN    LL_C2_APB2_GRP1_DisableClockSleep\n
-  *         APB2LPENR    HRTIMLPEN     LL_C2_APB2_GRP1_DisableClockSleep
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2  (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_C2_APB2_GRP1_DisableClockSleep(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC_C2->APB2LPENR, Periphs);
-}
-
-/**
-  * @}
-  */
-
-/** @addtogroup BUS_LL_EF_APB4 APB4
-  * @{
-  */
-
-/**
-  * @brief  Enable C2 APB4 peripherals clock.
-  * @rmtoll APB4ENR      SYSCFGEN      LL_C2_APB4_GRP1_EnableClock\n
-  *         APB4ENR      LPUART1EN     LL_C2_APB4_GRP1_EnableClock\n
-  *         APB4ENR      SPI6EN        LL_C2_APB4_GRP1_EnableClock\n
-  *         APB4ENR      I2C4EN        LL_C2_APB4_GRP1_EnableClock\n
-  *         APB4ENR      LPTIM2EN      LL_C2_APB4_GRP1_EnableClock\n
-  *         APB4ENR      LPTIM3EN      LL_C2_APB4_GRP1_EnableClock\n
-  *         APB4ENR      LPTIM4EN      LL_C2_APB4_GRP1_EnableClock\n
-  *         APB4ENR      LPTIM5EN      LL_C2_APB4_GRP1_EnableClock\n
-  *         APB4ENR      COMP12EN      LL_C2_APB4_GRP1_EnableClock\n
-  *         APB4ENR      VREFEN        LL_C2_APB4_GRP1_EnableClock\n
-  *         APB4ENR      RTCAPBEN      LL_C2_APB4_GRP1_EnableClock\n
-  *         APB4ENR      SAI4EN        LL_C2_APB4_GRP1_EnableClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
-  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
-  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
-  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
-  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
-  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
-  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
-  *
-  *         (*) value not defined in all devices
-  * @retval None
-*/
-__STATIC_INLINE void LL_C2_APB4_GRP1_EnableClock(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC_C2->APB4ENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC_C2->APB4ENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Check if C2 APB4 peripheral clock is enabled or not
-  * @rmtoll APB4ENR      SYSCFGEN      LL_C2_APB4_GRP1_IsEnabledClock\n
-  *         APB4ENR      LPUART1EN     LL_C2_APB4_GRP1_IsEnabledClock\n
-  *         APB4ENR      SPI6EN        LL_C2_APB4_GRP1_IsEnabledClock\n
-  *         APB4ENR      I2C4EN        LL_C2_APB4_GRP1_IsEnabledClock\n
-  *         APB4ENR      LPTIM2EN      LL_C2_APB4_GRP1_IsEnabledClock\n
-  *         APB4ENR      LPTIM3EN      LL_C2_APB4_GRP1_IsEnabledClock\n
-  *         APB4ENR      LPTIM4EN      LL_C2_APB4_GRP1_IsEnabledClock\n
-  *         APB4ENR      LPTIM5EN      LL_C2_APB4_GRP1_IsEnabledClock\n
-  *         APB4ENR      COMP12EN      LL_C2_APB4_GRP1_IsEnabledClock\n
-  *         APB4ENR      VREFEN        LL_C2_APB4_GRP1_IsEnabledClock\n
-  *         APB4ENR      RTCAPBEN      LL_C2_APB4_GRP1_IsEnabledClock\n
-  *         APB4ENR      SAI4EN        LL_C2_APB4_GRP1_IsEnabledClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
-  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
-  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
-  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
-  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
-  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
-  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
-  *
-  *         (*) value not defined in all devices
-  * @retval uint32_t
-*/
-__STATIC_INLINE uint32_t LL_C2_APB4_GRP1_IsEnabledClock(uint32_t Periphs)
-{
-  return ((READ_BIT(RCC_C2->APB4ENR, Periphs) == Periphs)?1U:0U);
-}
-
-/**
-  * @brief  Disable C2 APB4 peripherals clock.
-  * @rmtoll APB4ENR      SYSCFGEN      LL_C2_APB4_GRP1_DisableClock\n
-  *         APB4ENR      LPUART1EN     LL_C2_APB4_GRP1_DisableClock\n
-  *         APB4ENR      SPI6EN        LL_C2_APB4_GRP1_DisableClock\n
-  *         APB4ENR      I2C4EN        LL_C2_APB4_GRP1_DisableClock\n
-  *         APB4ENR      LPTIM2EN      LL_C2_APB4_GRP1_DisableClock\n
-  *         APB4ENR      LPTIM3EN      LL_C2_APB4_GRP1_DisableClock\n
-  *         APB4ENR      LPTIM4EN      LL_C2_APB4_GRP1_DisableClock\n
-  *         APB4ENR      LPTIM5EN      LL_C2_APB4_GRP1_DisableClock\n
-  *         APB4ENR      COMP12EN      LL_C2_APB4_GRP1_DisableClock\n
-  *         APB4ENR      VREFEN        LL_C2_APB4_GRP1_DisableClock\n
-  *         APB4ENR      RTCAPBEN      LL_C2_APB4_GRP1_DisableClock\n
-  *         APB4ENR      SAI4EN        LL_C2_APB4_GRP1_DisableClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
-  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
-  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
-  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
-  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
-  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
-  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
-  *
-  *         (*) value not defined in all devices
-  * @retval None
-*/
-__STATIC_INLINE void LL_C2_APB4_GRP1_DisableClock(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC_C2->APB4ENR, Periphs);
-}
-
-/**
-  * @brief  Enable C2 APB4 peripherals clock during Low Power (Sleep) mode.
-  * @rmtoll APB4LPENR    SYSCFGLPEN    LL_C2_APB4_GRP1_EnableClockSleep\n
-  *         APB4LPENR    LPUART1LPEN   LL_C2_APB4_GRP1_EnableClockSleep\n
-  *         APB4LPENR    SPI6LPEN      LL_C2_APB4_GRP1_EnableClockSleep\n
-  *         APB4LPENR    I2C4LPEN      LL_C2_APB4_GRP1_EnableClockSleep\n
-  *         APB4LPENR    LPTIM2LPEN    LL_C2_APB4_GRP1_EnableClockSleep\n
-  *         APB4LPENR    LPTIM3LPEN    LL_C2_APB4_GRP1_EnableClockSleep\n
-  *         APB4LPENR    LPTIM4LPEN    LL_C2_APB4_GRP1_EnableClockSleep\n
-  *         APB4LPENR    LPTIM5LPEN    LL_C2_APB4_GRP1_EnableClockSleep\n
-  *         APB4LPENR    COMP12LPEN    LL_C2_APB4_GRP1_EnableClockSleep\n
-  *         APB4LPENR    VREFLPEN      LL_C2_APB4_GRP1_EnableClockSleep\n
-  *         APB4LPENR    RTCAPBLPEN    LL_C2_APB4_GRP1_EnableClockSleep\n
-  *         APB4LPENR    SAI4LPEN      LL_C2_APB4_GRP1_EnableClockSleep
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
-  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
-  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
-  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
-  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
-  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
-  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
-  *
-  *         (*) value not defined in all devices
-  * @retval None
-*/
-__STATIC_INLINE void LL_C2_APB4_GRP1_EnableClockSleep(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC_C2->APB4LPENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC_C2->APB4LPENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Disable C2 APB4 peripherals clock during Low Power (Sleep) mode.
-  * @rmtoll APB4LPENR    SYSCFGLPEN    LL_C2_APB4_GRP1_DisableClockSleep\n
-  *         APB4LPENR    LPUART1LPEN   LL_C2_APB4_GRP1_DisableClockSleep\n
-  *         APB4LPENR    SPI6LPEN      LL_C2_APB4_GRP1_DisableClockSleep\n
-  *         APB4LPENR    I2C4LPEN      LL_C2_APB4_GRP1_DisableClockSleep\n
-  *         APB4LPENR    LPTIM2LPEN    LL_C2_APB4_GRP1_DisableClockSleep\n
-  *         APB4LPENR    LPTIM3LPEN    LL_C2_APB4_GRP1_DisableClockSleep\n
-  *         APB4LPENR    LPTIM4LPEN    LL_C2_APB4_GRP1_DisableClockSleep\n
-  *         APB4LPENR    LPTIM5LPEN    LL_C2_APB4_GRP1_DisableClockSleep\n
-  *         APB4LPENR    COMP12LPEN    LL_C2_APB4_GRP1_DisableClockSleep\n
-  *         APB4LPENR    VREFLPEN      LL_C2_APB4_GRP1_DisableClockSleep\n
-  *         APB4LPENR    RTCAPBLPEN    LL_C2_APB4_GRP1_DisableClockSleep\n
-  *         APB4LPENR    SAI4LPEN      LL_C2_APB4_GRP1_DisableClockSleep
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
-  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
-  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
-  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
-  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
-  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
-  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
-  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
-  *
-  *         (*) value not defined in all devices
-  * @retval None
-*/
-__STATIC_INLINE void LL_C2_APB4_GRP1_DisableClockSleep(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC_C2->APB4LPENR, Periphs);
-}
-
-/**
-  * @}
-  */
-
-#endif /*DUAL_CORE*/
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* defined(RCC) */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32H7xx_LL_BUS_H */
-
-
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_ll_bus.h
+  * @author  MCD Application Team
+  * @brief   Header file of BUS LL module.
+
+  @verbatim
+                      ##### RCC Limitations #####
+  ==============================================================================
+    [..]
+      A delay between an RCC peripheral clock enable and the effective peripheral
+      enabling should be taken into account in order to manage the peripheral read/write
+      from/to registers.
+      (+) This delay depends on the peripheral mapping.
+        (++) AHB & APB peripherals, 1 dummy read is necessary
+
+    [..]
+      Workarounds:
+      (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
+          inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_LL_BUS_H
+#define STM32H7xx_LL_BUS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx.h"
+
+/** @addtogroup STM32H7xx_LL_Driver
+  * @{
+  */
+
+#if defined(RCC)
+
+/** @defgroup BUS_LL BUS
+  * @{
+  */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
+  * @{
+  */
+
+/** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH  AHB3 GRP1 PERIPH
+  * @{
+  */
+#define LL_AHB3_GRP1_PERIPH_MDMA           RCC_AHB3ENR_MDMAEN
+#define LL_AHB3_GRP1_PERIPH_DMA2D          RCC_AHB3ENR_DMA2DEN
+
+#if defined(JPEG)
+#define LL_AHB3_GRP1_PERIPH_JPGDEC         RCC_AHB3ENR_JPGDECEN
+#endif /* JPEG */
+
+#define LL_AHB3_GRP1_PERIPH_FMC            RCC_AHB3ENR_FMCEN
+#if defined(QUADSPI)
+#define LL_AHB3_GRP1_PERIPH_QSPI           RCC_AHB3ENR_QSPIEN
+#endif /* QUADSPI */
+#if defined(OCTOSPI1) || defined(OCTOSPI2)
+#define LL_AHB3_GRP1_PERIPH_OSPI1          RCC_AHB3ENR_OSPI1EN
+#define LL_AHB3_GRP1_PERIPH_OSPI2          RCC_AHB3ENR_OSPI2EN
+#endif /*(OCTOSPI1) || (OCTOSPI2)*/
+#if defined(OCTOSPIM)
+#define LL_AHB3_GRP1_PERIPH_OCTOSPIM       RCC_AHB3ENR_IOMNGREN
+#endif /* OCTOSPIM */
+#if defined(OTFDEC1) || defined(OTFDEC2)
+#define LL_AHB3_GRP1_PERIPH_OTFDEC1        RCC_AHB3ENR_OTFDEC1EN
+#define LL_AHB3_GRP1_PERIPH_OTFDEC2        RCC_AHB3ENR_OTFDEC2EN
+#endif /* (OTFDEC1) || (OTFDEC2) */
+#if defined(GFXMMU)
+#define LL_AHB3_GRP1_PERIPH_GFXMMU         RCC_AHB3ENR_GFXMMUEN
+#endif /* GFXMMU */
+#define LL_AHB3_GRP1_PERIPH_SDMMC1         RCC_AHB3ENR_SDMMC1EN
+#define LL_AHB3_GRP1_PERIPH_FLASH          RCC_AHB3LPENR_FLASHLPEN
+#define LL_AHB3_GRP1_PERIPH_DTCM1          RCC_AHB3LPENR_DTCM1LPEN
+#define LL_AHB3_GRP1_PERIPH_DTCM2          RCC_AHB3LPENR_DTCM2LPEN
+#define LL_AHB3_GRP1_PERIPH_ITCM           RCC_AHB3LPENR_ITCMLPEN
+#if defined(RCC_AHB3LPENR_AXISRAMLPEN)
+#define LL_AHB3_GRP1_PERIPH_AXISRAM        RCC_AHB3LPENR_AXISRAMLPEN
+#else
+#define LL_AHB3_GRP1_PERIPH_AXISRAM1       RCC_AHB3LPENR_AXISRAM1LPEN
+#define LL_AHB3_GRP1_PERIPH_AXISRAM        LL_AHB3_GRP1_PERIPH_AXISRAM1   /* for backward compatibility*/
+#endif /* RCC_AHB3LPENR_AXISRAMLPEN */
+#if defined(CD_AXISRAM2_BASE)
+#define LL_AHB3_GRP1_PERIPH_AXISRAM2       RCC_AHB3LPENR_AXISRAM2LPEN
+#endif /* CD_AXISRAM2_BASE */
+#if defined(CD_AXISRAM3_BASE)
+#define LL_AHB3_GRP1_PERIPH_AXISRAM3       RCC_AHB3LPENR_AXISRAM3LPEN
+#endif /* CD_AXISRAM3_BASE */
+/**
+  * @}
+  */
+
+
+/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH  AHB1 GRP1 PERIPH
+  * @{
+  */
+#define LL_AHB1_GRP1_PERIPH_DMA1           RCC_AHB1ENR_DMA1EN
+#define LL_AHB1_GRP1_PERIPH_DMA2           RCC_AHB1ENR_DMA2EN
+#define LL_AHB1_GRP1_PERIPH_ADC12          RCC_AHB1ENR_ADC12EN
+#if defined(DUAL_CORE)
+#define LL_AHB1_GRP1_PERIPH_ART            RCC_AHB1ENR_ARTEN
+#endif /* DUAL_CORE */
+#if defined(RCC_AHB1ENR_CRCEN)
+#define LL_AHB1_GRP1_PERIPH_CRC            RCC_AHB1ENR_CRCEN
+#endif /* RCC_AHB1ENR_CRCEN */
+#if defined(ETH)
+#define LL_AHB1_GRP1_PERIPH_ETH1MAC        RCC_AHB1ENR_ETH1MACEN
+#define LL_AHB1_GRP1_PERIPH_ETH1TX         RCC_AHB1ENR_ETH1TXEN
+#define LL_AHB1_GRP1_PERIPH_ETH1RX         RCC_AHB1ENR_ETH1RXEN
+#endif /* ETH */
+#define LL_AHB1_GRP1_PERIPH_USB1OTGHS      RCC_AHB1ENR_USB1OTGHSEN
+#define LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI  RCC_AHB1ENR_USB1OTGHSULPIEN
+#if defined(USB2_OTG_FS)
+#define LL_AHB1_GRP1_PERIPH_USB2OTGHS      RCC_AHB1ENR_USB2OTGHSEN
+#define LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI  RCC_AHB1ENR_USB2OTGHSULPIEN
+#endif /* USB2_OTG_FS */
+/**
+  * @}
+  */
+
+
+/** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH  AHB2 GRP1 PERIPH
+  * @{
+  */
+#define LL_AHB2_GRP1_PERIPH_DCMI           RCC_AHB2ENR_DCMIEN
+#if defined(HSEM) && defined(RCC_AHB2ENR_HSEMEN)
+#define LL_AHB2_GRP1_PERIPH_HSEM           RCC_AHB2ENR_HSEMEN
+#endif /* HSEM && RCC_AHB2ENR_HSEMEN */
+#if defined(CRYP)
+#define LL_AHB2_GRP1_PERIPH_CRYP           RCC_AHB2ENR_CRYPEN
+#endif /* CRYP */
+#if defined(HASH)
+#define LL_AHB2_GRP1_PERIPH_HASH           RCC_AHB2ENR_HASHEN
+#endif /* HASH */
+#define LL_AHB2_GRP1_PERIPH_RNG            RCC_AHB2ENR_RNGEN
+#define LL_AHB2_GRP1_PERIPH_SDMMC2         RCC_AHB2ENR_SDMMC2EN
+#if defined(FMAC)
+#define LL_AHB2_GRP1_PERIPH_FMAC           RCC_AHB2ENR_FMACEN
+#endif /* FMAC */
+#if defined(CORDIC)
+#define LL_AHB2_GRP1_PERIPH_CORDIC         RCC_AHB2ENR_CORDICEN
+#endif /* CORDIC */
+#if defined(BDMA1)
+#define LL_AHB2_GRP1_PERIPH_BDMA1          RCC_AHB2ENR_BDMA1EN
+#endif /* BDMA1 */
+#if defined(RCC_AHB2ENR_D2SRAM1EN)
+#define LL_AHB2_GRP1_PERIPH_D2SRAM1        RCC_AHB2ENR_D2SRAM1EN
+#else
+#define LL_AHB2_GRP1_PERIPH_AHBSRAM1       RCC_AHB2ENR_AHBSRAM1EN
+#define LL_AHB2_GRP1_PERIPH_D2SRAM1        LL_AHB2_GRP1_PERIPH_AHBSRAM1    /* for backward compatibility*/
+#endif /* RCC_AHB2ENR_D2SRAM1EN */
+#if defined(RCC_AHB2ENR_D2SRAM2EN)
+#define LL_AHB2_GRP1_PERIPH_D2SRAM2        RCC_AHB2ENR_D2SRAM2EN
+#else
+#define LL_AHB2_GRP1_PERIPH_AHBSRAM2       RCC_AHB2ENR_AHBSRAM2EN
+#define LL_AHB2_GRP1_PERIPH_D2SRAM2        LL_AHB2_GRP1_PERIPH_AHBSRAM2    /* for backward compatibility*/
+#endif /* RCC_AHB2ENR_D2SRAM2EN */
+#if defined(RCC_AHB2ENR_D2SRAM3EN)
+#define LL_AHB2_GRP1_PERIPH_D2SRAM3        RCC_AHB2ENR_D2SRAM3EN
+#endif /* RCC_AHB2ENR_D2SRAM3EN */
+/**
+  * @}
+  */
+
+
+/** @defgroup BUS_LL_EC_AHB4_GRP1_PERIPH  AHB4 GRP1 PERIPH
+  * @{
+  */
+#define LL_AHB4_GRP1_PERIPH_GPIOA          RCC_AHB4ENR_GPIOAEN
+#define LL_AHB4_GRP1_PERIPH_GPIOB          RCC_AHB4ENR_GPIOBEN
+#define LL_AHB4_GRP1_PERIPH_GPIOC          RCC_AHB4ENR_GPIOCEN
+#define LL_AHB4_GRP1_PERIPH_GPIOD          RCC_AHB4ENR_GPIODEN
+#define LL_AHB4_GRP1_PERIPH_GPIOE          RCC_AHB4ENR_GPIOEEN
+#define LL_AHB4_GRP1_PERIPH_GPIOF          RCC_AHB4ENR_GPIOFEN
+#define LL_AHB4_GRP1_PERIPH_GPIOG          RCC_AHB4ENR_GPIOGEN
+#define LL_AHB4_GRP1_PERIPH_GPIOH          RCC_AHB4ENR_GPIOHEN
+#if defined(GPIOI)
+#define LL_AHB4_GRP1_PERIPH_GPIOI          RCC_AHB4ENR_GPIOIEN
+#endif /* GPIOI */
+#define LL_AHB4_GRP1_PERIPH_GPIOJ          RCC_AHB4ENR_GPIOJEN
+#define LL_AHB4_GRP1_PERIPH_GPIOK          RCC_AHB4ENR_GPIOKEN
+#if defined(RCC_AHB4ENR_CRCEN)
+#define LL_AHB4_GRP1_PERIPH_CRC            RCC_AHB4ENR_CRCEN
+#endif /* RCC_AHB4ENR_CRCEN */
+#if defined(BDMA2)
+#define LL_AHB4_GRP1_PERIPH_BDMA2          RCC_AHB4ENR_BDMA2EN
+#define LL_AHB4_GRP1_PERIPH_BDMA           LL_AHB4_GRP1_PERIPH_BDMA2  /* for backward compatibility*/
+#else
+#define LL_AHB4_GRP1_PERIPH_BDMA           RCC_AHB4ENR_BDMAEN
+#endif /* BDMA2 */
+#if defined(ADC3)
+#define LL_AHB4_GRP1_PERIPH_ADC3           RCC_AHB4ENR_ADC3EN
+#endif /* ADC3 */
+#if defined(HSEM) && defined(RCC_AHB4ENR_HSEMEN)
+#define LL_AHB4_GRP1_PERIPH_HSEM           RCC_AHB4ENR_HSEMEN
+#endif /* HSEM && RCC_AHB4ENR_HSEMEN*/
+#define LL_AHB4_GRP1_PERIPH_BKPRAM         RCC_AHB4ENR_BKPRAMEN
+#if defined(RCC_AHB4LPENR_SRAM4LPEN)
+#define LL_AHB4_GRP1_PERIPH_SRAM4          RCC_AHB4LPENR_SRAM4LPEN
+#define LL_AHB4_GRP1_PERIPH_D3SRAM1        LL_AHB4_GRP1_PERIPH_SRAM4
+#else
+#define LL_AHB4_GRP1_PERIPH_SRDSRAM        RCC_AHB4ENR_SRDSRAMEN
+#define LL_AHB4_GRP1_PERIPH_SRAM4          LL_AHB4_GRP1_PERIPH_SRDSRAM  /* for backward compatibility*/
+#define LL_AHB4_GRP1_PERIPH_D3SRAM1        LL_AHB4_GRP1_PERIPH_SRDSRAM  /* for backward compatibility*/
+#endif /* RCC_AHB4ENR_D3SRAM1EN */
+/**
+  * @}
+  */
+
+
+/** @defgroup BUS_LL_EC_APB3_GRP1_PERIPH  APB3 GRP1 PERIPH
+  * @{
+  */
+#if defined(LTDC)
+#define LL_APB3_GRP1_PERIPH_LTDC           RCC_APB3ENR_LTDCEN
+#endif /* LTDC */
+#if defined(DSI)
+#define LL_APB3_GRP1_PERIPH_DSI            RCC_APB3ENR_DSIEN
+#endif /* DSI */
+#define LL_APB3_GRP1_PERIPH_WWDG1          RCC_APB3ENR_WWDG1EN
+#if defined(RCC_APB3ENR_WWDGEN)
+#define LL_APB3_GRP1_PERIPH_WWDG           LL_APB3_GRP1_PERIPH_WWDG1   /* for backward compatibility*/
+#endif
+/**
+  * @}
+  */
+
+
+/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH  APB1 GRP1 PERIPH
+  * @{
+  */
+#define LL_APB1_GRP1_PERIPH_TIM2           RCC_APB1LENR_TIM2EN
+#define LL_APB1_GRP1_PERIPH_TIM3           RCC_APB1LENR_TIM3EN
+#define LL_APB1_GRP1_PERIPH_TIM4           RCC_APB1LENR_TIM4EN
+#define LL_APB1_GRP1_PERIPH_TIM5           RCC_APB1LENR_TIM5EN
+#define LL_APB1_GRP1_PERIPH_TIM6           RCC_APB1LENR_TIM6EN
+#define LL_APB1_GRP1_PERIPH_TIM7           RCC_APB1LENR_TIM7EN
+#define LL_APB1_GRP1_PERIPH_TIM12          RCC_APB1LENR_TIM12EN
+#define LL_APB1_GRP1_PERIPH_TIM13          RCC_APB1LENR_TIM13EN
+#define LL_APB1_GRP1_PERIPH_TIM14          RCC_APB1LENR_TIM14EN
+#define LL_APB1_GRP1_PERIPH_LPTIM1         RCC_APB1LENR_LPTIM1EN
+#if defined(DUAL_CORE)
+#define LL_APB1_GRP1_PERIPH_WWDG2          RCC_APB1LENR_WWDG2EN
+#endif /*DUAL_CORE*/
+#define LL_APB1_GRP1_PERIPH_SPI2           RCC_APB1LENR_SPI2EN
+#define LL_APB1_GRP1_PERIPH_SPI3           RCC_APB1LENR_SPI3EN
+#define LL_APB1_GRP1_PERIPH_SPDIFRX        RCC_APB1LENR_SPDIFRXEN
+#define LL_APB1_GRP1_PERIPH_USART2         RCC_APB1LENR_USART2EN
+#define LL_APB1_GRP1_PERIPH_USART3         RCC_APB1LENR_USART3EN
+#define LL_APB1_GRP1_PERIPH_UART4          RCC_APB1LENR_UART4EN
+#define LL_APB1_GRP1_PERIPH_UART5          RCC_APB1LENR_UART5EN
+#define LL_APB1_GRP1_PERIPH_I2C1           RCC_APB1LENR_I2C1EN
+#define LL_APB1_GRP1_PERIPH_I2C2           RCC_APB1LENR_I2C2EN
+#define LL_APB1_GRP1_PERIPH_I2C3           RCC_APB1LENR_I2C3EN
+#if defined(I2C5)
+#define LL_APB1_GRP1_PERIPH_I2C5           RCC_APB1LENR_I2C5EN
+#endif /* I2C5 */
+#if defined(RCC_APB1LENR_CECEN)
+#define LL_APB1_GRP1_PERIPH_CEC            RCC_APB1LENR_CECEN
+#else
+#define LL_APB1_GRP1_PERIPH_HDMICEC        RCC_APB1LENR_HDMICECEN
+#define LL_APB1_GRP1_PERIPH_CEC            LL_APB1_GRP1_PERIPH_HDMICEC   /* for backward compatibility*/
+#endif /* RCC_APB1LENR_CECEN */
+#define LL_APB1_GRP1_PERIPH_DAC12          RCC_APB1LENR_DAC12EN
+#define LL_APB1_GRP1_PERIPH_UART7          RCC_APB1LENR_UART7EN
+#define LL_APB1_GRP1_PERIPH_UART8          RCC_APB1LENR_UART8EN
+/**
+  * @}
+  */
+
+
+/** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH  APB1 GRP2 PERIPH
+  * @{
+  */
+#define LL_APB1_GRP2_PERIPH_CRS            RCC_APB1HENR_CRSEN
+#define LL_APB1_GRP2_PERIPH_SWPMI1         RCC_APB1HENR_SWPMIEN
+#define LL_APB1_GRP2_PERIPH_OPAMP          RCC_APB1HENR_OPAMPEN
+#define LL_APB1_GRP2_PERIPH_MDIOS          RCC_APB1HENR_MDIOSEN
+#define LL_APB1_GRP2_PERIPH_FDCAN          RCC_APB1HENR_FDCANEN
+#if defined(TIM23)
+#define LL_APB1_GRP2_PERIPH_TIM23          RCC_APB1HENR_TIM23EN
+#endif /* TIM23 */
+#if defined(TIM24)
+#define LL_APB1_GRP2_PERIPH_TIM24          RCC_APB1HENR_TIM24EN
+#endif /* TIM24 */
+/**
+  * @}
+  */
+
+
+/** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH  APB2 GRP1 PERIPH
+  * @{
+  */
+#define LL_APB2_GRP1_PERIPH_TIM1           RCC_APB2ENR_TIM1EN
+#define LL_APB2_GRP1_PERIPH_TIM8           RCC_APB2ENR_TIM8EN
+#define LL_APB2_GRP1_PERIPH_USART1         RCC_APB2ENR_USART1EN
+#define LL_APB2_GRP1_PERIPH_USART6         RCC_APB2ENR_USART6EN
+#if defined(UART9)
+#define LL_APB2_GRP1_PERIPH_UART9          RCC_APB2ENR_UART9EN
+#endif /* UART9 */
+#if defined(USART10)
+#define LL_APB2_GRP1_PERIPH_USART10        RCC_APB2ENR_USART10EN
+#endif /* USART10 */
+#define LL_APB2_GRP1_PERIPH_SPI1           RCC_APB2ENR_SPI1EN
+#define LL_APB2_GRP1_PERIPH_SPI4           RCC_APB2ENR_SPI4EN
+#define LL_APB2_GRP1_PERIPH_TIM15          RCC_APB2ENR_TIM15EN
+#define LL_APB2_GRP1_PERIPH_TIM16          RCC_APB2ENR_TIM16EN
+#define LL_APB2_GRP1_PERIPH_TIM17          RCC_APB2ENR_TIM17EN
+#define LL_APB2_GRP1_PERIPH_SPI5           RCC_APB2ENR_SPI5EN
+#define LL_APB2_GRP1_PERIPH_SAI1           RCC_APB2ENR_SAI1EN
+#if defined(SAI2)
+#define LL_APB2_GRP1_PERIPH_SAI2           RCC_APB2ENR_SAI2EN
+#endif /* SAI2 */
+#if defined(SAI3)
+#define LL_APB2_GRP1_PERIPH_SAI3           RCC_APB2ENR_SAI3EN
+#endif /* SAI3 */
+#define LL_APB2_GRP1_PERIPH_DFSDM1         RCC_APB2ENR_DFSDM1EN
+#if defined(HRTIM1)
+#define LL_APB2_GRP1_PERIPH_HRTIM          RCC_APB2ENR_HRTIMEN
+#endif /* HRTIM1 */
+/**
+  * @}
+  */
+
+
+/** @defgroup BUS_LL_EC_APB4_GRP1_PERIPH  APB4 GRP1 PERIPH
+  * @{
+  */
+#define LL_APB4_GRP1_PERIPH_SYSCFG         RCC_APB4ENR_SYSCFGEN
+#define LL_APB4_GRP1_PERIPH_LPUART1        RCC_APB4ENR_LPUART1EN
+#define LL_APB4_GRP1_PERIPH_SPI6           RCC_APB4ENR_SPI6EN
+#define LL_APB4_GRP1_PERIPH_I2C4           RCC_APB4ENR_I2C4EN
+#define LL_APB4_GRP1_PERIPH_LPTIM2         RCC_APB4ENR_LPTIM2EN
+#define LL_APB4_GRP1_PERIPH_LPTIM3         RCC_APB4ENR_LPTIM3EN
+#if defined(LPTIM4)
+#define LL_APB4_GRP1_PERIPH_LPTIM4         RCC_APB4ENR_LPTIM4EN
+#endif /* LPTIM4 */
+#if defined(LPTIM5)
+#define LL_APB4_GRP1_PERIPH_LPTIM5         RCC_APB4ENR_LPTIM5EN
+#endif /* LPTIM5 */
+#if defined(DAC2)
+#define LL_APB4_GRP1_PERIPH_DAC2           RCC_APB4ENR_DAC2EN
+#endif /* DAC2 */
+#define LL_APB4_GRP1_PERIPH_COMP12         RCC_APB4ENR_COMP12EN
+#define LL_APB4_GRP1_PERIPH_VREF           RCC_APB4ENR_VREFEN
+#define LL_APB4_GRP1_PERIPH_RTCAPB         RCC_APB4ENR_RTCAPBEN
+#if defined(SAI4)
+#define LL_APB4_GRP1_PERIPH_SAI4           RCC_APB4ENR_SAI4EN
+#endif /* SAI4 */
+#if defined(DTS)
+#define LL_APB4_GRP1_PERIPH_DTS            RCC_APB4ENR_DTSEN
+#endif /*DTS*/
+#if defined(DFSDM2_BASE)
+#define LL_APB4_GRP1_PERIPH_DFSDM2         RCC_APB4ENR_DFSDM2EN
+#endif /* DFSDM2_BASE */
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EC_CLKAM_PERIPH  CLKAM PERIPH
+  * @{
+  */
+#if defined(RCC_D3AMR_BDMAAMEN)
+#define LL_CLKAM_PERIPH_BDMA          RCC_D3AMR_BDMAAMEN
+#else
+#define LL_CLKAM_PERIPH_BDMA2         RCC_SRDAMR_BDMA2AMEN
+#define LL_CLKAM_PERIPH_BDMA   LL_CLKAM_PERIPH_BDMA2 /* for backward compatibility*/
+#endif /* RCC_D3AMR_BDMAAMEN */
+#if defined(RCC_SRDAMR_GPIOAMEN)
+#define LL_CLKAM_PERIPH_GPIO          RCC_SRDAMR_GPIOAMEN
+#endif /* RCC_SRDAMR_GPIOAMEN */
+#if defined(RCC_D3AMR_LPUART1AMEN)
+#define LL_CLKAM_PERIPH_LPUART1       RCC_D3AMR_LPUART1AMEN
+#else
+#define LL_CLKAM_PERIPH_LPUART1       RCC_SRDAMR_LPUART1AMEN
+#endif /* RCC_D3AMR_LPUART1AMEN */
+#if defined(RCC_D3AMR_SPI6AMEN)
+#define LL_CLKAM_PERIPH_SPI6          RCC_D3AMR_SPI6AMEN
+#else
+#define LL_CLKAM_PERIPH_SPI6          RCC_SRDAMR_SPI6AMEN
+#endif /* RCC_D3AMR_SPI6AMEN */
+#if defined(RCC_D3AMR_I2C4AMEN)
+#define LL_CLKAM_PERIPH_I2C4          RCC_D3AMR_I2C4AMEN
+#else
+#define LL_CLKAM_PERIPH_I2C4          RCC_SRDAMR_I2C4AMEN
+#endif /* RCC_D3AMR_I2C4AMEN */
+#if defined(RCC_D3AMR_LPTIM2AMEN)
+#define LL_CLKAM_PERIPH_LPTIM2        RCC_D3AMR_LPTIM2AMEN
+#else
+#define LL_CLKAM_PERIPH_LPTIM2        RCC_SRDAMR_LPTIM2AMEN
+#endif /* RCC_D3AMR_LPTIM2AMEN */
+#if defined(RCC_D3AMR_LPTIM3AMEN)
+#define LL_CLKAM_PERIPH_LPTIM3        RCC_D3AMR_LPTIM3AMEN
+#else
+#define LL_CLKAM_PERIPH_LPTIM3        RCC_SRDAMR_LPTIM3AMEN
+#endif /* RCC_D3AMR_LPTIM3AMEN */
+#if defined(RCC_D3AMR_LPTIM4AMEN)
+#define LL_CLKAM_PERIPH_LPTIM4        RCC_D3AMR_LPTIM4AMEN
+#endif /* RCC_D3AMR_LPTIM4AMEN */
+#if defined(RCC_D3AMR_LPTIM5AMEN)
+#define LL_CLKAM_PERIPH_LPTIM5        RCC_D3AMR_LPTIM5AMEN
+#endif /* RCC_D3AMR_LPTIM5AMEN */
+#if defined(DAC2)
+#define LL_CLKAM_PERIPH_DAC2          RCC_SRDAMR_DAC2AMEN
+#endif /* DAC2 */
+#if defined(RCC_D3AMR_COMP12AMEN)
+#define LL_CLKAM_PERIPH_COMP12        RCC_D3AMR_COMP12AMEN
+#else
+#define LL_CLKAM_PERIPH_COMP12        RCC_SRDAMR_COMP12AMEN
+#endif /* RCC_D3AMR_COMP12AMEN */
+#if defined(RCC_D3AMR_VREFAMEN)
+#define LL_CLKAM_PERIPH_VREF          RCC_D3AMR_VREFAMEN
+#else
+#define LL_CLKAM_PERIPH_VREF          RCC_SRDAMR_VREFAMEN
+#endif /* RCC_D3AMR_VREFAMEN */
+#if defined(RCC_D3AMR_RTCAMEN)
+#define LL_CLKAM_PERIPH_RTC           RCC_D3AMR_RTCAMEN
+#else
+#define LL_CLKAM_PERIPH_RTC           RCC_SRDAMR_RTCAMEN
+#endif /* RCC_D3AMR_RTCAMEN */
+#if defined(RCC_D3AMR_CRCAMEN)
+#define LL_CLKAM_PERIPH_CRC           RCC_D3AMR_CRCAMEN
+#endif /* RCC_D3AMR_CRCAMEN */
+#if defined(SAI4)
+#define LL_CLKAM_PERIPH_SAI4          RCC_D3AMR_SAI4AMEN
+#endif /* SAI4 */
+#if defined(ADC3)
+#define LL_CLKAM_PERIPH_ADC3          RCC_D3AMR_ADC3AMEN
+#endif /* ADC3 */
+#if defined(RCC_SRDAMR_DTSAMEN)
+#define LL_CLKAM_PERIPH_DTS           RCC_SRDAMR_DTSAMEN
+#endif /* RCC_SRDAMR_DTSAMEN */
+#if defined(RCC_D3AMR_DTSAMEN)
+#define LL_CLKAM_PERIPH_DTS           RCC_D3AMR_DTSAMEN
+#endif /* RCC_D3AMR_DTSAMEN */
+#if defined(DFSDM2_BASE)
+#define LL_CLKAM_PERIPH_DFSDM2        RCC_SRDAMR_DFSDM2AMEN
+#endif /* DFSDM2_BASE */
+#if defined(RCC_D3AMR_BKPRAMAMEN)
+#define LL_CLKAM_PERIPH_BKPRAM        RCC_D3AMR_BKPRAMAMEN
+#else
+#define LL_CLKAM_PERIPH_BKPRAM        RCC_SRDAMR_BKPRAMAMEN
+#endif /* RCC_D3AMR_BKPRAMAMEN */
+#if defined(RCC_D3AMR_SRAM4AMEN)
+#define LL_CLKAM_PERIPH_SRAM4         RCC_D3AMR_SRAM4AMEN
+#else
+#define LL_CLKAM_PERIPH_SRDSRAM       RCC_SRDAMR_SRDSRAMAMEN
+#define LL_CLKAM_PERIPH_SRAM4         LL_CLKAM_PERIPH_SRDSRAM
+#endif /* RCC_D3AMR_SRAM4AMEN */
+/**
+  * @}
+  */
+
+#if defined(RCC_CKGAENR_AXICKG)
+/** @defgroup BUS_LL_EC_CKGA_PERIPH  CKGA (AXI Clocks Gating) PERIPH
+  * @{
+  */
+#define LL_CKGA_PERIPH_AXI            RCC_CKGAENR_AXICKG
+#define LL_CKGA_PERIPH_AHB            RCC_CKGAENR_AHBCKG
+#define LL_CKGA_PERIPH_CPU            RCC_CKGAENR_CPUCKG
+#define LL_CKGA_PERIPH_SDMMC          RCC_CKGAENR_SDMMCCKG
+#define LL_CKGA_PERIPH_MDMA           RCC_CKGAENR_MDMACKG
+#define LL_CKGA_PERIPH_DMA2D          RCC_CKGAENR_DMA2DCKG
+#define LL_CKGA_PERIPH_LTDC           RCC_CKGAENR_LTDCCKG
+#define LL_CKGA_PERIPH_GFXMMUM        RCC_CKGAENR_GFXMMUMCKG
+#define LL_CKGA_PERIPH_AHB12          RCC_CKGAENR_AHB12CKG
+#define LL_CKGA_PERIPH_AHB34          RCC_CKGAENR_AHB34CKG
+#define LL_CKGA_PERIPH_FLIFT          RCC_CKGAENR_FLIFTCKG
+#define LL_CKGA_PERIPH_OCTOSPI2       RCC_CKGAENR_OCTOSPI2CKG
+#define LL_CKGA_PERIPH_FMC            RCC_CKGAENR_FMCCKG
+#define LL_CKGA_PERIPH_OCTOSPI1       RCC_CKGAENR_OCTOSPI1CKG
+#define LL_CKGA_PERIPH_AXIRAM1        RCC_CKGAENR_AXIRAM1CKG
+#define LL_CKGA_PERIPH_AXIRAM2        RCC_CKGAENR_AXIRAM2CKG
+#define LL_CKGA_PERIPH_AXIRAM3        RCC_CKGAENR_AXIRAM3CKG
+#define LL_CKGA_PERIPH_GFXMMUS        RCC_CKGAENR_GFXMMUSCKG
+#define LL_CKGA_PERIPH_ECCRAM         RCC_CKGAENR_ECCRAMCKG
+#define LL_CKGA_PERIPH_EXTI           RCC_CKGAENR_EXTICKG
+#define LL_CKGA_PERIPH_JTAG           RCC_CKGAENR_JTAGCKG
+/**
+  * @}
+  */
+#endif /* RCC_CKGAENR_AXICKG */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
+  * @{
+  */
+
+/** @defgroup BUS_LL_EF_AHB3 AHB3
+  * @{
+  */
+
+/**
+  * @brief  Enable AHB3 peripherals clock.
+  * @rmtoll AHB3ENR      MDMAEN        LL_AHB3_GRP1_EnableClock\n
+  *         AHB3ENR      DMA2DEN       LL_AHB3_GRP1_EnableClock\n
+  *         AHB3ENR      JPGDECEN      LL_AHB3_GRP1_EnableClock\n
+  *         AHB3ENR      FMCEN         LL_AHB3_GRP1_EnableClock\n
+  *         AHB3ENR      QSPIEN        LL_AHB3_GRP1_EnableClock\n  (*)
+  *         AHB3ENR      OSPI1EN       LL_AHB3_GRP1_EnableClock\n  (*)
+  *         AHB3ENR      OSPI2EN       LL_AHB3_GRP1_EnableClock\n  (*)
+  *         AHB3ENR      IOMNGREN      LL_AHB3_GRP1_EnableClock\n  (*)
+  *         AHB3ENR      OTFDEC1EN     LL_AHB3_GRP1_EnableClock\n  (*)
+  *         AHB3ENR      OTFDEC2EN     LL_AHB3_GRP1_EnableClock\n  (*)
+  *         AHB3ENR      GFXMMU        LL_AHB3_GRP1_EnableClock\n  (*)
+  *         AHB3ENR      SDMMC1EN      LL_AHB3_GRP1_EnableClock\n
+  *         AHB3ENR      FLASHEN       LL_AHB3_GRP1_EnableClock\n  (*)
+  *         AHB3ENR      DTCM1EN       LL_AHB3_GRP1_EnableClock\n  (*)
+  *         AHB3ENR      DTCM2EN       LL_AHB3_GRP1_EnableClock\n  (*)
+  *         AHB3ENR      ITCMEN        LL_AHB3_GRP1_EnableClock\n  (*)
+  *         AHB3ENR      AXISRAMEN     LL_AHB3_GRP1_EnableClock    (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->AHB3ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->AHB3ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if AHB3 peripheral clock is enabled or not
+  * @rmtoll AHB3ENR      MDMAEN        LL_AHB3_GRP1_IsEnabledClock\n
+  *         AHB3ENR      DMA2DEN       LL_AHB3_GRP1_IsEnabledClock\n
+  *         AHB3ENR      JPGDECEN      LL_AHB3_GRP1_IsEnabledClock\n
+  *         AHB3ENR      FMCEN         LL_AHB3_GRP1_IsEnabledClock\n
+  *         AHB3ENR      QSPIEN        LL_AHB3_GRP1_IsEnabledClock\n (*)
+  *         AHB3ENR      OSPI1EN       LL_AHB3_GRP1_IsEnabledClock\n (*)
+  *         AHB3ENR      OSPI2EN       LL_AHB3_GRP1_IsEnabledClock\n (*)
+  *         AHB3ENR      IOMNGREN      LL_AHB3_GRP1_IsEnabledClock\n (*)
+  *         AHB3ENR      OTFDEC1EN     LL_AHB3_GRP1_IsEnabledClock\n (*)
+  *         AHB3ENR      OTFDEC2EN     LL_AHB3_GRP1_IsEnabledClock\n (*)
+  *         AHB3ENR      GFXMMU        LL_AHB3_GRP1_IsEnabledClock\n (*)
+  *         AHB3ENR      SDMMC1EN      LL_AHB3_GRP1_IsEnabledClock\n
+  *         AHB3ENR      FLASHEN       LL_AHB3_GRP1_IsEnabledClock\n (*)
+  *         AHB3ENR      DTCM1EN       LL_AHB3_GRP1_IsEnabledClock\n (*)
+  *         AHB3ENR      DTCM2EN       LL_AHB3_GRP1_IsEnabledClock\n (*)
+  *         AHB3ENR      ITCMEN        LL_AHB3_GRP1_IsEnabledClock\n (*)
+  *         AHB3ENR      AXISRAMEN     LL_AHB3_GRP1_IsEnabledClock   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI    (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1   (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2   (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM  (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU  (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
+  *
+  *         (*) value not defined in all devices.
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC->AHB3ENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable AHB3 peripherals clock.
+  * @rmtoll AHB3ENR      MDMAEN        LL_AHB3_GRP1_DisableClock\n
+  *         AHB3ENR      DMA2DEN       LL_AHB3_GRP1_DisableClock\n
+  *         AHB3ENR      JPGDECEN      LL_AHB3_GRP1_DisableClock\n
+  *         AHB3ENR      FMCEN         LL_AHB3_GRP1_DisableClock\n
+  *         AHB3ENR      QSPIEN        LL_AHB3_GRP1_DisableClock\n (*)
+  *         AHB3ENR      OSPI1EN       LL_AHB3_GRP1_DisableClock\n (*)
+  *         AHB3ENR      OSPI2EN       LL_AHB3_GRP1_DisableClock\n (*)
+  *         AHB3ENR      IOMNGREN      LL_AHB3_GRP1_DisableClock\n (*)
+  *         AHB3ENR      OTFDEC1EN     LL_AHB3_GRP1_DisableClock\n (*)
+  *         AHB3ENR      OTFDEC2EN     LL_AHB3_GRP1_DisableClock\n (*)
+  *         AHB3ENR      GFXMMU        LL_AHB3_GRP1_DisableClock\n (*)
+  *         AHB3ENR      SDMMC1EN      LL_AHB3_GRP1_DisableClock\n (*)
+  *         AHB3ENR      FLASHEN       LL_AHB3_GRP1_DisableClock\n (*)
+  *         AHB3ENR      DTCM1EN       LL_AHB3_GRP1_DisableClock\n (*)
+  *         AHB3ENR      DTCM2EN       LL_AHB3_GRP1_DisableClock\n (*)
+  *         AHB3ENR      ITCMEN        LL_AHB3_GRP1_DisableClock\n (*)
+  *         AHB3ENR      AXISRAMEN     LL_AHB3_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI  (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1   (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2   (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM  (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU  (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB3ENR, Periphs);
+}
+
+/**
+  * @brief  Force AHB3 peripherals reset.
+  * @rmtoll AHB3RSTR     MDMARST       LL_AHB3_GRP1_ForceReset\n
+  *         AHB3RSTR     DMA2DRST      LL_AHB3_GRP1_ForceReset\n
+  *         AHB3RSTR     JPGDECRST     LL_AHB3_GRP1_ForceReset\n
+  *         AHB3RSTR     FMCRST        LL_AHB3_GRP1_ForceReset\n 
+  *         AHB3RSTR     QSPIRST       LL_AHB3_GRP1_ForceReset\n (*)
+  *         AHB3RSTR     OSPI1RST      LL_AHB3_GRP1_ForceReset\n (*)
+  *         AHB3RSTR     OSPI2RST      LL_AHB3_GRP1_ForceReset\n (*)
+  *         AHB3RSTR     IOMNGRRST     LL_AHB3_GRP1_ForceReset\n (*)
+  *         AHB3RSTR     OTFDEC1RST    LL_AHB3_GRP1_ForceReset\n (*)
+  *         AHB3RSTR     OTFDEC2RST    LL_AHB3_GRP1_ForceReset\n (*)
+  *         AHB3RSTR     GFXMMURST     LL_AHB3_GRP1_ForceReset\n (*)
+  *         AHB3RSTR     SDMMC1RST     LL_AHB3_GRP1_ForceReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU  (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs)
+{
+  SET_BIT(RCC->AHB3RSTR, Periphs);
+}
+
+/**
+  * @brief  Release AHB3 peripherals reset.
+  * @rmtoll AHB3RSTR     MDMARST       LL_AHB3_GRP1_ReleaseReset\n
+  *         AHB3RSTR     DMA2DRST      LL_AHB3_GRP1_ReleaseReset\n
+  *         AHB3RSTR     JPGDECRST     LL_AHB3_GRP1_ReleaseReset\n
+  *         AHB3RSTR     FMCRST        LL_AHB3_GRP1_ReleaseReset\n
+  *         AHB3RSTR     QSPIRST       LL_AHB3_GRP1_ReleaseReset\n
+  *         AHB3RSTR     OSPI1RST      LL_AHB3_GRP1_ReleaseReset\n (*)
+  *         AHB3RSTR     OSPI2RST      LL_AHB3_GRP1_ReleaseReset\n (*)
+  *         AHB3RSTR     IOMNGRRST     LL_AHB3_GRP1_ReleaseReset\n (*)
+  *         AHB3RSTR     OTFDEC1RST    LL_AHB3_GRP1_ReleaseReset\n (*)
+  *         AHB3RSTR     OTFDEC2RST    LL_AHB3_GRP1_ReleaseReset\n (*)
+  *         AHB3RSTR     GFXMMURST     LL_AHB3_GRP1_ReleaseReset\n (*)
+  *         AHB3RSTR     SDMMC1RST     LL_AHB3_GRP1_ReleaseReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1    (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2    (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU  (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB3RSTR, Periphs);
+}
+
+/**
+  * @brief  Enable AHB3 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll AHB3LPENR    MDMALPEN      LL_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    DMA2DLPEN     LL_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    JPGDECLPEN    LL_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    FMCLPEN       LL_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    QSPILPEN      LL_AHB3_GRP1_EnableClockSleep\n  (*)
+  *         AHB3LPENR    OSPI1LPEN     LL_AHB3_GRP1_EnableClockSleep\n  (*)
+  *         AHB3LPENR    OSPI2LPEN     LL_AHB3_GRP1_EnableClockSleep\n  (*)
+  *         AHB3LPENR    IOMNGRLPEN    LL_AHB3_GRP1_EnableClockSleep\n  (*)
+  *         AHB3LPENR    OTFDEC1LPEN   LL_AHB3_GRP1_EnableClockSleep\n  (*)
+  *         AHB3LPENR    OTFDEC1LPEN   LL_AHB3_GRP1_EnableClockSleep\n  (*)
+  *         AHB3LPENR    GFXMMULPEN    LL_AHB3_GRP1_EnableClockSleep\n  (*)
+  *         AHB3LPENR    SDMMC1LPEN    LL_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    FLASHLPEN     LL_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    DTCM1LPEN     LL_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    DTCM2LPEN     LL_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    ITCMLPEN      LL_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    AXISRAMLPEN   LL_AHB3_GRP1_EnableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI     (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1    (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2    (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU  (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB3_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->AHB3LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->AHB3LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable AHB3 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll AHB3LPENR    MDMALPEN      LL_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    DMA2DLPEN     LL_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    JPGDECLPEN    LL_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    FMCLPEN       LL_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    QSPILPEN      LL_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    OSPI1LPEN     LL_AHB3_GRP1_DisableClockSleep\n  (*)
+  *         AHB3LPENR    OSPI2LPEN     LL_AHB3_GRP1_DisableClockSleep\n  (*)
+  *         AHB3LPENR    IOMNGRLPEN    LL_AHB3_GRP1_DisableClockSleep\n  (*)
+  *         AHB3LPENR    OTFDEC1LPEN   LL_AHB3_GRP1_DisableClockSleep\n  (*)
+  *         AHB3LPENR    OTFDEC1LPEN   LL_AHB3_GRP1_DisableClockSleep\n  (*)
+  *         AHB3LPENR    GFXMMULPEN    LL_AHB3_GRP1_DisableClockSleep\n  (*)
+  *         AHB3LPENR    SDMMC1LPEN    LL_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    FLASHLPEN     LL_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    DTCM1LPEN     LL_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    DTCM2LPEN     LL_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    ITCMLPEN      LL_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    AXISRAMLPEN   LL_AHB3_GRP1_DisableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI     (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1    (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2    (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU  (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB3_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB3LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_AHB1 AHB1
+  * @{
+  */
+
+/**
+  * @brief  Enable AHB1 peripherals clock.
+  * @rmtoll AHB1ENR      DMA1EN        LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      DMA2EN        LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      ADC12EN       LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      ARTEN         LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      CRCEN         LL_AHB1_GRP1_EnableClock\n (*)
+  *         AHB1ENR      ETH1MACEN     LL_AHB1_GRP1_EnableClock\n (*)
+  *         AHB1ENR      ETH1TXEN      LL_AHB1_GRP1_EnableClock\n (*)
+  *         AHB1ENR      ETH1RXEN      LL_AHB1_GRP1_EnableClock\n (*)
+  *         AHB1ENR      USB1OTGHSEN   LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      USB1OTGHSULPIEN  LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      USB2OTGHSEN   LL_AHB1_GRP1_EnableClock\n  (*)
+  *         AHB1ENR      USB2OTGHSULPIEN  LL_AHB1_GRP1_EnableClock (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS  (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->AHB1ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->AHB1ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if AHB1 peripheral clock is enabled or not
+  * @rmtoll AHB1ENR      DMA1EN        LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      DMA2EN        LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      ADC12EN       LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      ARTEN         LL_AHB1_GRP1_IsEnabledClock\n (*)
+  *         AHB1ENR      CRCEN         LL_AHB1_GRP1_IsEnabledClock\n (*)
+  *         AHB1ENR      ETH1MACEN     LL_AHB1_GRP1_IsEnabledClock\n (*)
+  *         AHB1ENR      ETH1TXEN      LL_AHB1_GRP1_IsEnabledClock\n (*)
+  *         AHB1ENR      ETH1RXEN      LL_AHB1_GRP1_IsEnabledClock\n (*)
+  *         AHB1ENR      USB1OTGHSEN   LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      USB1OTGHSULPIEN  LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      USB2OTGHSEN   LL_AHB1_GRP1_IsEnabledClock\n  (*)
+  *         AHB1ENR      USB2OTGHSULPIEN  LL_AHB1_GRP1_IsEnabledClock (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX  (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX  (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS     (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC->AHB1ENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable AHB1 peripherals clock.
+  * @rmtoll AHB1ENR      DMA1EN        LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      DMA2EN        LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      ADC12EN       LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      ARTEN         LL_AHB1_GRP1_DisableClock\n (*)
+  *         AHB1ENR      CRCEN         LL_AHB1_GRP1_DisableClock\n (*)
+  *         AHB1ENR      ETH1MACEN     LL_AHB1_GRP1_DisableClock\n (*)
+  *         AHB1ENR      ETH1TXEN      LL_AHB1_GRP1_DisableClock\n (*)
+  *         AHB1ENR      ETH1RXEN      LL_AHB1_GRP1_DisableClock\n (*)
+  *         AHB1ENR      USB1OTGHSEN   LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      USB1OTGHSULPIEN  LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      USB2OTGHSEN   LL_AHB1_GRP1_DisableClock\n  (*)
+  *         AHB1ENR      USB2OTGHSULPIEN  LL_AHB1_GRP1_DisableClock (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX  (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX  (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS     (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB1ENR, Periphs);
+}
+
+/**
+  * @brief  Force AHB1 peripherals reset.
+  * @rmtoll AHB1RSTR     DMA1RST       LL_AHB1_GRP1_ForceReset\n
+  *         AHB1RSTR     DMA2RST       LL_AHB1_GRP1_ForceReset\n
+  *         AHB1RSTR     ADC12RST      LL_AHB1_GRP1_ForceReset\n
+  *         AHB1RSTR     ARTRST        LL_AHB1_GRP1_ForceReset\n (*)
+  *         AHB1RSTR     CRCRST        LL_AHB1_GRP1_ForceReset\n (*)
+  *         AHB1RSTR     ETH1MACRST    LL_AHB1_GRP1_ForceReset\n (*)
+  *         AHB1RSTR     USB1OTGHSRST  LL_AHB1_GRP1_ForceReset\n
+  *         AHB1RSTR     USB2OTGHSRST  LL_AHB1_GRP1_ForceReset   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
+{
+  SET_BIT(RCC->AHB1RSTR, Periphs);
+}
+
+/**
+  * @brief  Release AHB1 peripherals reset.
+  * @rmtoll AHB1RSTR     DMA1RST       LL_AHB1_GRP1_ReleaseReset\n
+  *         AHB1RSTR     DMA2RST       LL_AHB1_GRP1_ReleaseReset\n
+  *         AHB1RSTR     ADC12RST      LL_AHB1_GRP1_ReleaseReset\n
+  *         AHB1RSTR     ARTRST        LL_AHB1_GRP1_ReleaseReset\n (*)
+  *         AHB1RSTR     CRCRST        LL_AHB1_GRP1_ReleaseReset\n (*)
+  *         AHB1RSTR     ETH1MACRST    LL_AHB1_GRP1_ReleaseReset\n (*)
+  *         AHB1RSTR     USB1OTGHSRST  LL_AHB1_GRP1_ReleaseReset\n
+  *         AHB1RSTR     USB2OTGHSRST  LL_AHB1_GRP1_ReleaseReset   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB1RSTR, Periphs);
+}
+
+/**
+  * @brief  Enable AHB1 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll AHB1LPENR    DMA1LPEN      LL_AHB1_GRP1_EnableClockSleep\n
+  *         AHB1LPENR    DMA2LPEN      LL_AHB1_GRP1_EnableClockSleep\n
+  *         AHB1LPENR    ADC12LPEN     LL_AHB1_GRP1_EnableClockSleep\n
+  *         AHB1LPENR    ARTLPEN       LL_AHB1_GRP1_EnableClockSleep\n (*)
+  *         AHB1LPENR    CRCLPEN       LL_AHB1_GRP1_EnableClockSleep\n (*)
+  *         AHB1LPENR    ETH1MACLPEN   LL_AHB1_GRP1_EnableClockSleep\n (*)
+  *         AHB1LPENR    ETH1TXLPEN    LL_AHB1_GRP1_EnableClockSleep\n (*)
+  *         AHB1LPENR    ETH1RXLPEN    LL_AHB1_GRP1_EnableClockSleep\n
+  *         AHB1LPENR    USB1OTGHSLPEN  LL_AHB1_GRP1_EnableClockSleep\n
+  *         AHB1LPENR    USB1OTGHSULPILPEN  LL_AHB1_GRP1_EnableClockSleep\n
+  *         AHB1LPENR    USB2OTGHSLPEN  LL_AHB1_GRP1_EnableClockSleep\n   (*)
+  *         AHB1LPENR    USB2OTGHSULPILPEN  LL_AHB1_GRP1_EnableClockSleep (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX  (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX  (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS     (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->AHB1LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->AHB1LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable AHB1 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll AHB1LPENR    DMA1LPEN      LL_AHB1_GRP1_DisableClockSleep\n
+  *         AHB1LPENR    DMA2LPEN      LL_AHB1_GRP1_DisableClockSleep\n
+  *         AHB1LPENR    ADC12LPEN     LL_AHB1_GRP1_DisableClockSleep\n
+  *         AHB1LPENR    ARTLPEN       LL_AHB1_GRP1_DisableClockSleep\n (*)
+  *         AHB1LPENR    CRCLPEN       LL_AHB1_GRP1_DisableClockSleep\n (*)
+  *         AHB1LPENR    ETH1MACLPEN   LL_AHB1_GRP1_DisableClockSleep\n (*)
+  *         AHB1LPENR    ETH1TXLPEN    LL_AHB1_GRP1_DisableClockSleep\n (*)
+  *         AHB1LPENR    ETH1RXLPEN    LL_AHB1_GRP1_DisableClockSleep\n (*)
+  *         AHB1LPENR    USB1OTGHSLPEN  LL_AHB1_GRP1_DisableClockSleep\n
+  *         AHB1LPENR    USB1OTGHSULPILPEN  LL_AHB1_GRP1_DisableClockSleep\n
+  *         AHB1LPENR    USB2OTGHSLPEN  LL_AHB1_GRP1_DisableClockSleep\n   (*)
+  *         AHB1LPENR    USB2OTGHSULPILPEN  LL_AHB1_GRP1_DisableClockSleep (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX  (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX  (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS     (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB1LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_AHB2 AHB2
+  * @{
+  */
+
+/**
+  * @brief  Enable AHB2 peripherals clock.
+  * @rmtoll AHB2ENR      DCMIEN        LL_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      HSEMEN        LL_AHB2_GRP1_EnableClock\n (*)
+  *         AHB2ENR      CRYPEN        LL_AHB2_GRP1_EnableClock\n (*)
+  *         AHB2ENR      HASHEN        LL_AHB2_GRP1_EnableClock\n (*)
+  *         AHB2ENR      RNGEN         LL_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      SDMMC2EN      LL_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      BDMA1EN       LL_AHB2_GRP1_EnableClock\n (*)
+  *         AHB2ENR      FMACEN        LL_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      CORDICEN      LL_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      D2SRAM1EN     LL_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      D2SRAM2EN     LL_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      D2SRAM3EN     LL_AHB2_GRP1_EnableClock   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1  (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_FMAC   (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->AHB2ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if AHB2 peripheral clock is enabled or not
+  * @rmtoll AHB2ENR      DCMIEN        LL_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      HSEMEN        LL_AHB2_GRP1_IsEnabledClock\n (*)
+  *         AHB2ENR      CRYPEN        LL_AHB2_GRP1_IsEnabledClock\n (*)
+  *         AHB2ENR      HASHEN        LL_AHB2_GRP1_IsEnabledClock\n (*)
+  *         AHB2ENR      RNGEN         LL_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      SDMMC2EN      LL_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      BDMA1EN       LL_AHB2_GRP1_IsEnabledClock\n (*)
+  *         AHB2ENR      FMACEN        LL_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      CORDICEN      LL_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      D2SRAM1EN     LL_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      D2SRAM2EN     LL_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      D2SRAM3EN     LL_AHB2_GRP1_IsEnabledClock   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1  (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_FMAC   (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC->AHB2ENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable AHB2 peripherals clock.
+  * @rmtoll AHB2ENR      DCMIEN        LL_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      HSEMEN        LL_AHB2_GRP1_DisableClock\n (*)
+  *         AHB2ENR      CRYPEN        LL_AHB2_GRP1_DisableClock\n (*)
+  *         AHB2ENR      HASHEN        LL_AHB2_GRP1_DisableClock\n (*)
+  *         AHB2ENR      RNGEN         LL_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      SDMMC2EN      LL_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      BDMA1EN       LL_AHB2_GRP1_DisableClock\n (*)
+  *         AHB2ENR      FMACEN        LL_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      CORDICEN      LL_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      D2SRAM1EN     LL_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      D2SRAM2EN     LL_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      D2SRAM3EN     LL_AHB2_GRP1_DisableClock   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1  (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_FMAC   (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB2ENR, Periphs);
+}
+
+/**
+  * @brief  Force AHB2 peripherals reset.
+  * @rmtoll AHB2RSTR     DCMIRST       LL_AHB2_GRP1_ForceReset\n
+  *         AHB2RSTR     HSEMRST       LL_AHB2_GRP1_ForceReset\n (*)
+  *         AHB2RSTR     CRYPRST       LL_AHB2_GRP1_ForceReset\n (*)
+  *         AHB2RSTR     HASHRST       LL_AHB2_GRP1_ForceReset\n (*)
+  *         AHB2RSTR     RNGRST        LL_AHB2_GRP1_ForceReset\n
+  *         AHB2RSTR     SDMMC2RST     LL_AHB2_GRP1_ForceReset\n
+  *         AHB2RSTR     BDMA1RST      LL_AHB2_GRP1_ForceReset   (*)
+  *         AHB2RSTR     FMACRST       LL_AHB2_GRP1_ForceReset\n
+  *         AHB2RSTR     CORDICRST     LL_AHB2_GRP1_ForceReset 
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1  (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_FMAC   (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)
+{
+  SET_BIT(RCC->AHB2RSTR, Periphs);
+}
+
+/**
+  * @brief  Release AHB2 peripherals reset.
+  * @rmtoll AHB2RSTR     DCMIRST       LL_AHB2_GRP1_ReleaseReset\n
+  *         AHB2RSTR     HSEMRST       LL_AHB2_GRP1_ReleaseReset\n (*)
+  *         AHB2RSTR     CRYPRST       LL_AHB2_GRP1_ReleaseReset\n (*)
+  *         AHB2RSTR     HASHRST       LL_AHB2_GRP1_ReleaseReset\n (*)
+  *         AHB2RSTR     RNGRST        LL_AHB2_GRP1_ReleaseReset\n
+  *         AHB2RSTR     SDMMC2RST     LL_AHB2_GRP1_ReleaseReset\n
+  *         AHB2RSTR     BDMA1RST      LL_AHB2_GRP1_ReleaseReset   (*)
+  *         AHB2RSTR     FMACRST       LL_AHB2_GRP1_ReleaseReset\n
+  *         AHB2RSTR     CORDICRST     LL_AHB2_GRP1_ReleaseReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1  (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_FMAC   (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB2RSTR, Periphs);
+}
+
+/**
+  * @brief  Enable AHB2 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll AHB2LPENR    DCMILPEN      LL_AHB2_GRP1_EnableClockSleep\n
+  *         AHB2LPENR    CRYPLPEN      LL_AHB2_GRP1_EnableClockSleep\n  (*)
+  *         AHB2LPENR    HASHLPEN      LL_AHB2_GRP1_EnableClockSleep\n  (*)
+  *         AHB2LPENR    RNGLPEN       LL_AHB2_GRP1_EnableClockSleep\n
+  *         AHB2LPENR    SDMMC2LPEN    LL_AHB2_GRP1_EnableClockSleep\n
+  *         AHB2LPENR    BDMA1LPEN     LL_AHB2_GRP1_EnableClockSleep\n (*)
+  *         AHB2LPENR    FMACLPEN      LL_AHB2_GRP1_EnableClockSleep\n
+  *         AHB2LPENR    CORDICLPEN    LL_AHB2_GRP1_EnableClockSleep\n
+  *         AHB2LPENR    D2SRAM1LPEN   LL_AHB2_GRP1_EnableClockSleep\n
+  *         AHB2LPENR    D2SRAM2LPEN   LL_AHB2_GRP1_EnableClockSleep\n
+  *         AHB2LPENR    D2SRAM3LPEN   LL_AHB2_GRP1_EnableClockSleep    (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1  (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_FMAC   (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB2_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->AHB2LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->AHB2LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable AHB2 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll AHB2LPENR    DCMILPEN      LL_AHB2_GRP1_DisableClockSleep\n
+  *         AHB2LPENR    CRYPLPEN      LL_AHB2_GRP1_DisableClockSleep\n (*)
+  *         AHB2LPENR    HASHLPEN      LL_AHB2_GRP1_DisableClockSleep\n (*)
+  *         AHB2LPENR    RNGLPEN       LL_AHB2_GRP1_DisableClockSleep\n
+  *         AHB2LPENR    SDMMC2LPEN    LL_AHB2_GRP1_DisableClockSleep\n
+  *         AHB2LPENR    BDMA1LPEN     LL_AHB2_GRP1_DisableClockSleep\n (*)
+  *         AHB2LPENR    D2SRAM1LPEN   LL_AHB2_GRP1_DisableClockSleep\n
+  *         AHB2LPENR    D2SRAM2LPEN   LL_AHB2_GRP1_DisableClockSleep\n
+  *         AHB2LPENR    D2SRAM3LPEN   LL_AHB2_GRP1_DisableClockSleep   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1  (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_FMAC   (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB2_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB2LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_AHB4 AHB4
+  * @{
+  */
+
+/**
+  * @brief  Enable AHB4 peripherals clock.
+  * @rmtoll AHB4ENR      GPIOAEN       LL_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOBEN       LL_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOCEN       LL_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIODEN       LL_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOEEN       LL_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOFEN       LL_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOGEN       LL_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOHEN       LL_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOIEN       LL_AHB4_GRP1_EnableClock\n (*)
+  *         AHB4ENR      GPIOJEN       LL_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOKEN       LL_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      CRCEN         LL_AHB4_GRP1_EnableClock\n (*)
+  *         AHB4ENR      BDMAEN        LL_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      ADC3EN        LL_AHB4_GRP1_EnableClock\n (*)
+  *         AHB4ENR      HSEMEN        LL_AHB4_GRP1_EnableClock\n (*)
+  *         AHB4ENR      BKPRAMEN      LL_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      SRAM4EN       LL_AHB4_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI  (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC   (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3  (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM  (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB4_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->AHB4ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->AHB4ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if AHB4 peripheral clock is enabled or not
+  * @rmtoll AHB4ENR      GPIOAEN       LL_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOBEN       LL_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOCEN       LL_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIODEN       LL_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOEEN       LL_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOFEN       LL_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOGEN       LL_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOHEN       LL_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOIEN       LL_AHB4_GRP1_IsEnabledClock\n (*)
+  *         AHB4ENR      GPIOJEN       LL_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOKEN       LL_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      CRCEN         LL_AHB4_GRP1_IsEnabledClock\n (*)
+  *         AHB4ENR      BDMAEN        LL_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      ADC3EN        LL_AHB4_GRP1_IsEnabledClock\n (*)
+  *         AHB4ENR      HSEMEN        LL_AHB4_GRP1_IsEnabledClock\n (*)
+  *         AHB4ENR      BKPRAMEN      LL_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      SRAM4EN       LL_AHB4_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI  (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC   (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM  (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
+  *
+  *         (*) value not defined in all devices.
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_AHB4_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC->AHB4ENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable AHB4 peripherals clock.
+  * @rmtoll AHB4ENR      GPIOAEN       LL_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOBEN       LL_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOCEN       LL_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIODEN       LL_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOEEN       LL_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOFEN       LL_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOGEN       LL_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOHEN       LL_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOIEN       LL_AHB4_GRP1_DisableClock\n  (*)
+  *         AHB4ENR      GPIOJEN       LL_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOKEN       LL_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      CRCEN         LL_AHB4_GRP1_DisableClock\n (*)
+  *         AHB4ENR      BDMAEN        LL_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      ADC3EN        LL_AHB4_GRP1_DisableClock\n (*)
+  *         AHB4ENR      HSEMEN        LL_AHB4_GRP1_DisableClock\n (*)
+  *         AHB4ENR      BKPRAMEN      LL_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      SRAM4EN       LL_AHB4_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI  (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC   (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM  (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB4_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB4ENR, Periphs);
+}
+
+/**
+  * @brief  Force AHB4 peripherals reset.
+  * @rmtoll AHB4RSTR     GPIOARST      LL_AHB4_GRP1_ForceReset\n
+  *         AHB4RSTR     GPIOBRST      LL_AHB4_GRP1_ForceReset\n
+  *         AHB4RSTR     GPIOCRST      LL_AHB4_GRP1_ForceReset\n
+  *         AHB4RSTR     GPIODRST      LL_AHB4_GRP1_ForceReset\n
+  *         AHB4RSTR     GPIOERST      LL_AHB4_GRP1_ForceReset\n
+  *         AHB4RSTR     GPIOFRST      LL_AHB4_GRP1_ForceReset\n
+  *         AHB4RSTR     GPIOGRST      LL_AHB4_GRP1_ForceReset\n
+  *         AHB4RSTR     GPIOHRST      LL_AHB4_GRP1_ForceReset\n
+  *         AHB4RSTR     GPIOIRST      LL_AHB4_GRP1_ForceReset\n (*)
+  *         AHB4RSTR     GPIOJRST      LL_AHB4_GRP1_ForceReset\n
+  *         AHB4RSTR     GPIOKRST      LL_AHB4_GRP1_ForceReset\n
+  *         AHB4RSTR     CRCRST        LL_AHB4_GRP1_ForceReset\n (*)
+  *         AHB4RSTR     BDMARST       LL_AHB4_GRP1_ForceReset\n
+  *         AHB4RSTR     ADC3RST       LL_AHB4_GRP1_ForceReset\n (*)
+  *         AHB4RSTR     HSEMRST       LL_AHB4_GRP1_ForceReset   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI  (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC   (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM  (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB4_GRP1_ForceReset(uint32_t Periphs)
+{
+  SET_BIT(RCC->AHB4RSTR, Periphs);
+}
+
+/**
+  * @brief  Release AHB4 peripherals reset.
+  * @rmtoll AHB4RSTR     GPIOARST      LL_AHB4_GRP1_ReleaseReset\n
+  *         AHB4RSTR     GPIOBRST      LL_AHB4_GRP1_ReleaseReset\n
+  *         AHB4RSTR     GPIOCRST      LL_AHB4_GRP1_ReleaseReset\n
+  *         AHB4RSTR     GPIODRST      LL_AHB4_GRP1_ReleaseReset\n
+  *         AHB4RSTR     GPIOERST      LL_AHB4_GRP1_ReleaseReset\n
+  *         AHB4RSTR     GPIOFRST      LL_AHB4_GRP1_ReleaseReset\n
+  *         AHB4RSTR     GPIOGRST      LL_AHB4_GRP1_ReleaseReset\n
+  *         AHB4RSTR     GPIOHRST      LL_AHB4_GRP1_ReleaseReset\n
+  *         AHB4RSTR     GPIOIRST      LL_AHB4_GRP1_ReleaseReset\n (*)
+  *         AHB4RSTR     GPIOJRST      LL_AHB4_GRP1_ReleaseReset\n
+  *         AHB4RSTR     GPIOKRST      LL_AHB4_GRP1_ReleaseReset\n
+  *         AHB4RSTR     CRCRST        LL_AHB4_GRP1_ReleaseReset\n (*)
+  *         AHB4RSTR     BDMARST       LL_AHB4_GRP1_ReleaseReset\n
+  *         AHB4RSTR     ADC3RST       LL_AHB4_GRP1_ReleaseReset\n (*)
+  *         AHB4RSTR     HSEMRST       LL_AHB4_GRP1_ReleaseReset   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI  (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC   (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM  (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB4_GRP1_ReleaseReset(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB4RSTR, Periphs);
+}
+
+/**
+  * @brief  Enable AHB4 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll AHB4LPENR    GPIOALPEN     LL_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOBLPEN     LL_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOCLPEN     LL_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIODLPEN     LL_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOELPEN     LL_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOFLPEN     LL_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOGLPEN     LL_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOHLPEN     LL_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOILPEN     LL_AHB4_GRP1_EnableClockSleep\n (*)
+  *         AHB4LPENR    GPIOJLPEN     LL_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOKLPEN     LL_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    CRCLPEN       LL_AHB4_GRP1_EnableClockSleep\n (*)
+  *         AHB4LPENR    BDMALPEN      LL_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    ADC3LPEN      LL_AHB4_GRP1_EnableClockSleep\n (*)
+  *         AHB4LPENR    BKPRAMLPEN    LL_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    SRAM4LPEN     LL_AHB4_GRP1_EnableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI  (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC   (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB4_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->AHB4LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->AHB4LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable AHB4 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll AHB4LPENR    GPIOALPEN     LL_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOBLPEN     LL_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOCLPEN     LL_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIODLPEN     LL_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOELPEN     LL_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOFLPEN     LL_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOGLPEN     LL_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOHLPEN     LL_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOILPEN     LL_AHB4_GRP1_DisableClockSleep\n (*)
+  *         AHB4LPENR    GPIOJLPEN     LL_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOKLPEN     LL_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    CRCLPEN       LL_AHB4_GRP1_DisableClockSleep\n (*)
+  *         AHB4LPENR    BDMALPEN      LL_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    ADC3LPEN      LL_AHB4_GRP1_DisableClockSleep\n (*)
+  *         AHB4LPENR    BKPRAMLPEN    LL_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    SRAM4LPEN   LL_AHB4_GRP1_DisableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI  (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC   (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB4_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB4LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_APB3 APB3
+  * @{
+  */
+
+/**
+  * @brief  Enable APB3 peripherals clock.
+  * @rmtoll APB3ENR      LTDCEN        LL_APB3_GRP1_EnableClock\n (*)
+  *         APB3ENR      DSIEN         LL_APB3_GRP1_EnableClock\n (*)
+  *         APB3ENR      WWDG1EN       LL_APB3_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB3_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->APB3ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->APB3ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if APB3 peripheral clock is enabled or not
+  * @rmtoll APB3ENR      LTDCEN        LL_APB3_GRP1_IsEnabledClock\n (*)
+  *         APB3ENR      DSIEN         LL_APB3_GRP1_IsEnabledClock\n (*)
+  *         APB3ENR      WWDG1EN       LL_APB3_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
+  *
+  *         (*) value not defined in all devices.
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_APB3_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC->APB3ENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable APB3 peripherals clock.
+  * @rmtoll APB3ENR      LTDCEN        LL_APB3_GRP1_DisableClock\n
+  *         APB3ENR      DSIEN         LL_APB3_GRP1_DisableClock\n
+  *         APB3ENR      WWDG1EN       LL_APB3_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB3_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB3ENR, Periphs);
+}
+
+/**
+  * @brief  Force APB3 peripherals reset.
+  * @rmtoll APB3RSTR     LTDCRST       LL_APB3_GRP1_ForceReset\n (*)
+  *         APB3RSTR     DSIRST        LL_APB3_GRP1_ForceReset   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB3_GRP1_ForceReset(uint32_t Periphs)
+{
+  SET_BIT(RCC->APB3RSTR, Periphs);
+}
+
+/**
+  * @brief  Release APB3 peripherals reset.
+  * @rmtoll APB3RSTR     LTDCRST       LL_APB3_GRP1_ReleaseReset\n
+  *         APB3RSTR     DSIRST        LL_APB3_GRP1_ReleaseReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB3_GRP1_ReleaseReset(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB3RSTR, Periphs);
+}
+
+/**
+  * @brief  Enable APB3 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB3LPENR    LTDCLPEN      LL_APB3_GRP1_EnableClockSleep\n (*)
+  *         APB3LPENR    DSILPEN       LL_APB3_GRP1_EnableClockSleep\n (*)
+  *         APB3LPENR    WWDG1LPEN     LL_APB3_GRP1_EnableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB3_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->APB3LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->APB3LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable APB3 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB3LPENR    LTDCLPEN      LL_APB3_GRP1_DisableClockSleep\n (*)
+  *         APB3LPENR    DSILPEN       LL_APB3_GRP1_DisableClockSleep\n (*)
+  *         APB3LPENR    WWDG1LPEN     LL_APB3_GRP1_DisableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB3_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB3LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_APB1 APB1
+  * @{
+  */
+
+/**
+  * @brief  Enable APB1 peripherals clock.
+  * @rmtoll APB1LENR     TIM2EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1LENR     TIM3EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1LENR     TIM4EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1LENR     TIM5EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1LENR     TIM6EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1LENR     TIM7EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1LENR     TIM12EN       LL_APB1_GRP1_EnableClock\n
+  *         APB1LENR     TIM13EN       LL_APB1_GRP1_EnableClock\n
+  *         APB1LENR     TIM14EN       LL_APB1_GRP1_EnableClock\n
+  *         APB1LENR     LPTIM1EN      LL_APB1_GRP1_EnableClock\n
+  *         APB1LENR     WWDG2EN       LL_APB1_GRP1_EnableClock\n (*)
+  *         APB1LENR     SPI2EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1LENR     SPI3EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1LENR     SPDIFRXEN     LL_APB1_GRP1_EnableClock\n
+  *         APB1LENR     USART2EN      LL_APB1_GRP1_EnableClock\n
+  *         APB1LENR     USART3EN      LL_APB1_GRP1_EnableClock\n
+  *         APB1LENR     UART4EN       LL_APB1_GRP1_EnableClock\n
+  *         APB1LENR     UART5EN       LL_APB1_GRP1_EnableClock\n
+  *         APB1LENR     I2C1EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1LENR     I2C2EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1LENR     I2C3EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1LENR     I2C5EN        LL_APB1_GRP1_EnableClock\n (*)
+  *         APB1LENR     CECEN         LL_APB1_GRP1_EnableClock\n
+  *         APB1LENR     DAC12EN       LL_APB1_GRP1_EnableClock\n
+  *         APB1LENR     UART7EN       LL_APB1_GRP1_EnableClock\n
+  *         APB1LENR     UART8EN       LL_APB1_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C5 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->APB1LENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->APB1LENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if APB1 peripheral clock is enabled or not
+  * @rmtoll APB1LENR     TIM2EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     TIM3EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     TIM4EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     TIM5EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     TIM6EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     TIM7EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     TIM12EN       LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     TIM13EN       LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     TIM14EN       LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     LPTIM1EN      LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     WWDG2EN       LL_APB1_GRP1_IsEnabledClock\n (*)
+  *         APB1LENR     SPI2EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     SPI3EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     SPDIFRXEN     LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     USART2EN      LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     USART3EN      LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     UART4EN       LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     UART5EN       LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     I2C1EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     I2C2EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     I2C3EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     I2C5EN        LL_APB1_GRP1_IsEnabledClock\n (*)
+  *         APB1LENR     CECEN         LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     DAC12EN       LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     UART7EN       LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     UART8EN       LL_APB1_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C5 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+  *
+  *         (*) value not defined in all devices.
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC->APB1LENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable APB1 peripherals clock.
+  * @rmtoll APB1LENR     TIM2EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1LENR     TIM3EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1LENR     TIM4EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1LENR     TIM5EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1LENR     TIM6EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1LENR     TIM7EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1LENR     TIM12EN       LL_APB1_GRP1_DisableClock\n
+  *         APB1LENR     TIM13EN       LL_APB1_GRP1_DisableClock\n
+  *         APB1LENR     TIM14EN       LL_APB1_GRP1_DisableClock\n
+  *         APB1LENR     LPTIM1EN      LL_APB1_GRP1_DisableClock\n
+  *         APB1LENR     WWDG2EN       LL_APB1_GRP1_DisableClock\n (*)
+  *         APB1LENR     SPI2EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1LENR     SPI3EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1LENR     SPDIFRXEN     LL_APB1_GRP1_DisableClock\n
+  *         APB1LENR     USART2EN      LL_APB1_GRP1_DisableClock\n
+  *         APB1LENR     USART3EN      LL_APB1_GRP1_DisableClock\n
+  *         APB1LENR     UART4EN       LL_APB1_GRP1_DisableClock\n
+  *         APB1LENR     UART5EN       LL_APB1_GRP1_DisableClock\n
+  *         APB1LENR     I2C1EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1LENR     I2C2EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1LENR     I2C3EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1LENR     I2C5EN        LL_APB1_GRP1_DisableClock\n (*)
+  *         APB1LENR     CECEN         LL_APB1_GRP1_DisableClock\n
+  *         APB1LENR     DAC12EN       LL_APB1_GRP1_DisableClock\n
+  *         APB1LENR     UART7EN       LL_APB1_GRP1_DisableClock\n
+  *         APB1LENR     UART8EN       LL_APB1_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C5 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB1LENR, Periphs);
+}
+
+/**
+  * @brief  Force APB1 peripherals reset.
+  * @rmtoll APB1LRSTR    TIM2RST       LL_APB1_GRP1_ForceReset\n
+  *         APB1LRSTR    TIM3RST       LL_APB1_GRP1_ForceReset\n
+  *         APB1LRSTR    TIM4RST       LL_APB1_GRP1_ForceReset\n
+  *         APB1LRSTR    TIM5RST       LL_APB1_GRP1_ForceReset\n
+  *         APB1LRSTR    TIM6RST       LL_APB1_GRP1_ForceReset\n
+  *         APB1LRSTR    TIM7RST       LL_APB1_GRP1_ForceReset\n
+  *         APB1LRSTR    TIM12RST      LL_APB1_GRP1_ForceReset\n
+  *         APB1LRSTR    TIM13RST      LL_APB1_GRP1_ForceReset\n
+  *         APB1LRSTR    TIM14RST      LL_APB1_GRP1_ForceReset\n
+  *         APB1LRSTR    LPTIM1RST     LL_APB1_GRP1_ForceReset\n
+  *         APB1LRSTR    SPI2RST       LL_APB1_GRP1_ForceReset\n
+  *         APB1LRSTR    SPI3RST       LL_APB1_GRP1_ForceReset\n
+  *         APB1LRSTR    SPDIFRXRST    LL_APB1_GRP1_ForceReset\n
+  *         APB1LRSTR    USART2RST     LL_APB1_GRP1_ForceReset\n
+  *         APB1LRSTR    USART3RST     LL_APB1_GRP1_ForceReset\n
+  *         APB1LRSTR    UART4RST      LL_APB1_GRP1_ForceReset\n
+  *         APB1LRSTR    UART5RST      LL_APB1_GRP1_ForceReset\n
+  *         APB1LRSTR    I2C1RST       LL_APB1_GRP1_ForceReset\n
+  *         APB1LRSTR    I2C2RST       LL_APB1_GRP1_ForceReset\n
+  *         APB1LRSTR    I2C3RST       LL_APB1_GRP1_ForceReset\n
+  *         APB1LRSTR    I2C5RST       LL_APB1_GRP5_ForceReset\n (*)
+  *         APB1LRSTR    CECRST        LL_APB1_GRP1_ForceReset\n
+  *         APB1LRSTR    DAC12RST      LL_APB1_GRP1_ForceReset\n
+  *         APB1LRSTR    UART7RST      LL_APB1_GRP1_ForceReset\n
+  *         APB1LRSTR    UART8RST      LL_APB1_GRP1_ForceReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C5 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
+{
+  SET_BIT(RCC->APB1LRSTR, Periphs);
+}
+
+/**
+  * @brief  Release APB1 peripherals reset.
+  * @rmtoll APB1LRSTR    TIM2RST       LL_APB1_GRP1_ReleaseReset\n
+  *         APB1LRSTR    TIM3RST       LL_APB1_GRP1_ReleaseReset\n
+  *         APB1LRSTR    TIM4RST       LL_APB1_GRP1_ReleaseReset\n
+  *         APB1LRSTR    TIM5RST       LL_APB1_GRP1_ReleaseReset\n
+  *         APB1LRSTR    TIM6RST       LL_APB1_GRP1_ReleaseReset\n
+  *         APB1LRSTR    TIM7RST       LL_APB1_GRP1_ReleaseReset\n
+  *         APB1LRSTR    TIM12RST      LL_APB1_GRP1_ReleaseReset\n
+  *         APB1LRSTR    TIM13RST      LL_APB1_GRP1_ReleaseReset\n
+  *         APB1LRSTR    TIM14RST      LL_APB1_GRP1_ReleaseReset\n
+  *         APB1LRSTR    LPTIM1RST     LL_APB1_GRP1_ReleaseReset\n
+  *         APB1LRSTR    SPI2RST       LL_APB1_GRP1_ReleaseReset\n
+  *         APB1LRSTR    SPI3RST       LL_APB1_GRP1_ReleaseReset\n
+  *         APB1LRSTR    SPDIFRXRST    LL_APB1_GRP1_ReleaseReset\n
+  *         APB1LRSTR    USART2RST     LL_APB1_GRP1_ReleaseReset\n
+  *         APB1LRSTR    USART3RST     LL_APB1_GRP1_ReleaseReset\n
+  *         APB1LRSTR    UART4RST      LL_APB1_GRP1_ReleaseReset\n
+  *         APB1LRSTR    UART5RST      LL_APB1_GRP1_ReleaseReset\n
+  *         APB1LRSTR    I2C1RST       LL_APB1_GRP1_ReleaseReset\n
+  *         APB1LRSTR    I2C2RST       LL_APB1_GRP1_ReleaseReset\n
+  *         APB1LRSTR    I2C3RST       LL_APB1_GRP1_ReleaseReset\n
+  *         APB1LRSTR    I2C5RST       LL_APB1_GRP1_ReleaseReset\n (*)
+  *         APB1LRSTR    CECRST        LL_APB1_GRP1_ReleaseReset\n
+  *         APB1LRSTR    DAC12RST      LL_APB1_GRP1_ReleaseReset\n
+  *         APB1LRSTR    UART7RST      LL_APB1_GRP1_ReleaseReset\n
+  *         APB1LRSTR    UART8RST      LL_APB1_GRP1_ReleaseReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C5 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB1LRSTR, Periphs);
+}
+
+/**
+  * @brief  Enable APB1 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB1LLPENR   TIM2LPEN      LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   TIM3LPEN      LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   TIM4LPEN      LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   TIM5LPEN      LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   TIM6LPEN      LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   TIM7LPEN      LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   TIM12LPEN     LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   TIM13LPEN     LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   TIM14LPEN     LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   LPTIM1LPEN    LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   WWDG2LPEN     LL_APB1_GRP1_EnableClockSleep\n (*)
+  *         APB1LLPENR   SPI2LPEN      LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   SPI3LPEN      LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   SPDIFRXLPEN   LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   USART2LPEN    LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   USART3LPEN    LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   UART4LPEN     LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   UART5LPEN     LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   I2C1LPEN      LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   I2C2LPEN      LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   I2C3LPEN      LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   I2C5LPEN      LL_APB1_GRP1_EnableClockSleep\n (*)
+  *         APB1LLPENR   CECLPEN       LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   DAC12LPEN     LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   UART7LPEN     LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   UART8LPEN     LL_APB1_GRP1_EnableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C5 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->APB1LLPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->APB1LLPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable APB1 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB1LLPENR   TIM2LPEN      LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   TIM3LPEN      LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   TIM4LPEN      LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   TIM5LPEN      LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   TIM6LPEN      LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   TIM7LPEN      LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   TIM12LPEN     LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   TIM13LPEN     LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   TIM14LPEN     LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   LPTIM1LPEN    LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   WWDG2LPEN     LL_APB1_GRP1_DisableClockSleep\n (*)
+  *         APB1LLPENR   SPI2LPEN      LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   SPI3LPEN      LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   SPDIFRXLPEN   LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   USART2LPEN    LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   USART3LPEN    LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   UART4LPEN     LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   UART5LPEN     LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   I2C1LPEN      LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   I2C2LPEN      LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   I2C3LPEN      LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   I2C5LPEN      LL_APB1_GRP1_DisableClockSleep\n (*)
+  *         APB1LLPENR   CECLPEN       LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   DAC12LPEN     LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   UART7LPEN     LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   UART8LPEN     LL_APB1_GRP1_DisableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C5 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB1LLPENR, Periphs);
+}
+
+/**
+  * @brief  Enable APB1 peripherals clock.
+  * @rmtoll APB1HENR     CRSEN         LL_APB1_GRP2_EnableClock\n
+  *         APB1HENR     SWPMIEN       LL_APB1_GRP2_EnableClock\n
+  *         APB1HENR     OPAMPEN       LL_APB1_GRP2_EnableClock\n
+  *         APB1HENR     MDIOSEN       LL_APB1_GRP2_EnableClock\n
+  *         APB1HENR     FDCANEN       LL_APB1_GRP2_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
+  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+  *         @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
+  *         @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->APB1HENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->APB1HENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if APB1 peripheral clock is enabled or not
+  * @rmtoll APB1HENR     CRSEN         LL_APB1_GRP2_IsEnabledClock\n
+  *         APB1HENR     SWPMIEN       LL_APB1_GRP2_IsEnabledClock\n
+  *         APB1HENR     OPAMPEN       LL_APB1_GRP2_IsEnabledClock\n
+  *         APB1HENR     MDIOSEN       LL_APB1_GRP2_IsEnabledClock\n
+  *         APB1HENR     FDCANEN       LL_APB1_GRP2_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
+  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+  *         @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
+  *         @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC->APB1HENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable APB1 peripherals clock.
+  * @rmtoll APB1HENR     CRSEN         LL_APB1_GRP2_DisableClock\n
+  *         APB1HENR     SWPMIEN       LL_APB1_GRP2_DisableClock\n
+  *         APB1HENR     OPAMPEN       LL_APB1_GRP2_DisableClock\n
+  *         APB1HENR     MDIOSEN       LL_APB1_GRP2_DisableClock\n
+  *         APB1HENR     FDCANEN       LL_APB1_GRP2_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
+  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+  *         @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
+  *         @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB1HENR, Periphs);
+}
+
+/**
+  * @brief  Force APB1 peripherals reset.
+  * @rmtoll APB1HRSTR    CRSRST        LL_APB1_GRP2_ForceReset\n
+  *         APB1HRSTR    SWPMIRST      LL_APB1_GRP2_ForceReset\n
+  *         APB1HRSTR    OPAMPRST      LL_APB1_GRP2_ForceReset\n
+  *         APB1HRSTR    MDIOSRST      LL_APB1_GRP2_ForceReset\n
+  *         APB1HRSTR    FDCANRST      LL_APB1_GRP2_ForceReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
+  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+  *         @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
+  *         @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs)
+{
+  SET_BIT(RCC->APB1HRSTR, Periphs);
+}
+
+/**
+  * @brief  Release APB1 peripherals reset.
+  * @rmtoll APB1HRSTR    CRSRST        LL_APB1_GRP2_ReleaseReset\n
+  *         APB1HRSTR    SWPMIRST      LL_APB1_GRP2_ReleaseReset\n
+  *         APB1HRSTR    OPAMPRST      LL_APB1_GRP2_ReleaseReset\n
+  *         APB1HRSTR    MDIOSRST      LL_APB1_GRP2_ReleaseReset\n
+  *         APB1HRSTR    FDCANRST      LL_APB1_GRP2_ReleaseReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
+  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+  *         @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
+  *         @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB1HRSTR, Periphs);
+}
+
+/**
+  * @brief  Enable APB1 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB1HLPENR   CRSLPEN       LL_APB1_GRP2_EnableClockSleep\n
+  *         APB1HLPENR   SWPMILPEN     LL_APB1_GRP2_EnableClockSleep\n
+  *         APB1HLPENR   OPAMPLPEN     LL_APB1_GRP2_EnableClockSleep\n
+  *         APB1HLPENR   MDIOSLPEN     LL_APB1_GRP2_EnableClockSleep\n
+  *         APB1HLPENR   FDCANLPEN     LL_APB1_GRP2_EnableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
+  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+  *         @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
+  *         @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP2_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->APB1HLPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->APB1HLPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable APB1 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB1HLPENR   CRSLPEN       LL_APB1_GRP2_DisableClockSleep\n
+  *         APB1HLPENR   SWPMILPEN     LL_APB1_GRP2_DisableClockSleep\n
+  *         APB1HLPENR   OPAMPLPEN     LL_APB1_GRP2_DisableClockSleep\n
+  *         APB1HLPENR   MDIOSLPEN     LL_APB1_GRP2_DisableClockSleep\n
+  *         APB1HLPENR   FDCANLPEN     LL_APB1_GRP2_DisableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
+  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+  *         @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
+  *         @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP2_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB1HLPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_APB2 APB2
+  * @{
+  */
+
+/**
+  * @brief  Enable APB2 peripherals clock.
+  * @rmtoll APB2ENR      TIM1EN        LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR      TIM8EN        LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR      USART1EN      LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR      USART6EN      LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR      UART9EN       LL_APB2_GRP1_EnableClock\n (*)
+  *         APB2ENR      USART10EN     LL_APB2_GRP1_EnableClock\n (*)
+  *         APB2ENR      SPI1EN        LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR      SPI4EN        LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR      TIM15EN       LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR      TIM16EN       LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR      TIM17EN       LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR      SPI5EN        LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR      SAI1EN        LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR      SAI2EN        LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR      SAI3EN        LL_APB2_GRP1_EnableClock\n (*)
+  *         APB2ENR      DFSDM1EN      LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR      HRTIMEN       LL_APB2_GRP1_EnableClock   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9   (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2  (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->APB2ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if APB2 peripheral clock is enabled or not
+  * @rmtoll APB2ENR      TIM1EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      TIM8EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      USART1EN      LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      USART6EN      LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      UART9EN       LL_APB2_GRP1_IsEnabledClock\n (*)
+  *         APB2ENR      USART10EN     LL_APB2_GRP1_IsEnabledClock\n (*)
+  *         APB2ENR      SPI1EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      SPI4EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      TIM15EN       LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      TIM16EN       LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      TIM17EN       LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      SPI5EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      SAI1EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      SAI2EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      SAI3EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      DFSDM1EN      LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      HRTIMEN       LL_APB2_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9   (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2  (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC->APB2ENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable APB2 peripherals clock.
+  * @rmtoll APB2ENR      TIM1EN        LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR      TIM8EN        LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR      USART1EN      LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR      USART6EN      LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR      UART9EN       LL_APB2_GRP1_DisableClock\n (*)
+  *         APB2ENR      USART10EN     LL_APB2_GRP1_DisableClock\n (*)
+  *         APB2ENR      SPI1EN        LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR      SPI4EN        LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR      TIM15EN       LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR      TIM16EN       LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR      TIM17EN       LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR      SPI5EN        LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR      SAI1EN        LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR      SAI2EN        LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR      SAI3EN        LL_APB2_GRP1_DisableClock\n (*)
+  *         APB2ENR      DFSDM1EN      LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR      HRTIMEN       LL_APB2_GRP1_DisableClock   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9   (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2  (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB2ENR, Periphs);
+}
+
+/**
+  * @brief  Force APB2 peripherals reset.
+  * @rmtoll APB2RSTR     TIM1RST       LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     TIM8RST       LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     USART1RST     LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     USART6RST     LL_APB2_GRP1_ForceReset\n
+  *         APB2ENR      UART9RST      LL_APB2_GRP1_ForceReset\n (*)
+  *         APB2ENR      USART10RST    LL_APB2_GRP1_ForceReset\n (*)
+  *         APB2RSTR     SPI1RST       LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     SPI4RST       LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     TIM15RST      LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     TIM16RST      LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     TIM17RST      LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     SPI5RST       LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     SAI1RST       LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     SAI2RST       LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     SAI3RST       LL_APB2_GRP1_ForceReset\n (*)
+  *         APB2RSTR     DFSDM1RST     LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     HRTIMRST      LL_APB2_GRP1_ForceReset   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9   (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2  (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
+{
+  SET_BIT(RCC->APB2RSTR, Periphs);
+}
+
+/**
+  * @brief  Release APB2 peripherals reset.
+  * @rmtoll APB2RSTR     TIM1RST       LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     TIM8RST       LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     USART1RST     LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     USART6RST     LL_APB2_GRP1_ReleaseReset\n
+  *         APB2ENR      UART9RST      LL_APB2_GRP1_ReleaseReset\n (*)
+  *         APB2ENR      USART10RST    LL_APB2_GRP1_ReleaseReset\n (*)
+  *         APB2RSTR     SPI1RST       LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     SPI4RST       LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     TIM15RST      LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     TIM16RST      LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     TIM17RST      LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     SPI5RST       LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     SAI1RST       LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     SAI2RST       LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     SAI3RST       LL_APB2_GRP1_ReleaseReset\n (*)
+  *         APB2RSTR     DFSDM1RST     LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     HRTIMRST      LL_APB2_GRP1_ReleaseReset   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9   (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2  (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB2RSTR, Periphs);
+}
+
+/**
+  * @brief  Enable APB2 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB2LPENR    TIM1LPEN      LL_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    TIM8LPEN      LL_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    USART1LPEN    LL_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    USART6LPEN    LL_APB2_GRP1_EnableClockSleep\n
+  *         APB2ENR      UART9LPEN     LL_APB2_GRP1_EnableClockSleep\n (*)
+  *         APB2ENR      USART10LPEN   LL_APB2_GRP1_EnableClockSleep\n (*)
+  *         APB2LPENR    SPI1LPEN      LL_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    SPI4LPEN      LL_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    TIM15LPEN     LL_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    TIM16LPEN     LL_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    TIM17LPEN     LL_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    SPI5LPEN      LL_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    SAI1LPEN      LL_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    SAI2LPEN      LL_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    SAI3LPEN      LL_APB2_GRP1_EnableClockSleep\n (*)
+  *         APB2LPENR    DFSDM1LPEN    LL_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    HRTIMLPEN     LL_APB2_GRP1_EnableClockSleep   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9   (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2  (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->APB2LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->APB2LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable APB2 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB2LPENR    TIM1LPEN      LL_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    TIM8LPEN      LL_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    USART1LPEN    LL_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    USART6LPEN    LL_APB2_GRP1_DisableClockSleep\n
+  *         APB2ENR      UART9LPEN     LL_APB2_GRP1_DisableClockSleep\n (*)
+  *         APB2ENR      USART10LPEN   LL_APB2_GRP1_DisableClockSleep\n (*)
+  *         APB2LPENR    SPI1LPEN      LL_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    SPI4LPEN      LL_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    TIM15LPEN     LL_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    TIM16LPEN     LL_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    TIM17LPEN     LL_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    SPI5LPEN      LL_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    SAI1LPEN      LL_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    SAI2LPEN      LL_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    SAI3LPEN      LL_APB2_GRP1_DisableClockSleep\n (*)
+  *         APB2LPENR    DFSDM1LPEN    LL_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    HRTIMLPEN     LL_APB2_GRP1_DisableClockSleep   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9   (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2  (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB2LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_APB4 APB4
+  * @{
+  */
+
+/**
+  * @brief  Enable APB4 peripherals clock.
+  * @rmtoll APB4ENR      SYSCFGEN      LL_APB4_GRP1_EnableClock\n
+  *         APB4ENR      LPUART1EN     LL_APB4_GRP1_EnableClock\n
+  *         APB4ENR      SPI6EN        LL_APB4_GRP1_EnableClock\n
+  *         APB4ENR      I2C4EN        LL_APB4_GRP1_EnableClock\n
+  *         APB4ENR      LPTIM2EN      LL_APB4_GRP1_EnableClock\n
+  *         APB4ENR      LPTIM3EN      LL_APB4_GRP1_EnableClock\n
+  *         APB4ENR      LPTIM4EN      LL_APB4_GRP1_EnableClock\n  (*)
+  *         APB4ENR      LPTIM5EN      LL_APB4_GRP1_EnableClock\n  (*)
+  *         APB4ENR      DAC2EN        LL_APB4_GRP1_EnableClock\n  (*)
+  *         APB4ENR      COMP12EN      LL_APB4_GRP1_EnableClock\n
+  *         APB4ENR      VREFEN        LL_APB4_GRP1_EnableClock\n
+  *         APB4ENR      RTCAPBEN      LL_APB4_GRP1_EnableClock\n
+  *         APB4ENR      SAI4EN        LL_APB4_GRP1_EnableClock\n  (*)
+  *         APB4ENR      DTSEN         LL_APB4_GRP1_EnableClock\n  (*)
+  *         APB4ENR      DFSDM2EN      LL_APB4_GRP1_EnableClock    (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DAC2   (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
+  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DTS    (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB4_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->APB4ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->APB4ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if APB4 peripheral clock is enabled or not
+  * @rmtoll APB4ENR      SYSCFGEN      LL_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      LPUART1EN     LL_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      SPI6EN        LL_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      I2C4EN        LL_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      LPTIM2EN      LL_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      LPTIM3EN      LL_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      LPTIM4EN      LL_APB4_GRP1_IsEnabledClock\n (*)
+  *         APB4ENR      LPTIM5EN      LL_APB4_GRP1_IsEnabledClock\n (*)
+  *         APB4ENR      DAC2EN        LL_APB4_GRP1_IsEnabledClock\n (*)
+  *         APB4ENR      COMP12EN      LL_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      VREFEN        LL_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      RTCAPBEN      LL_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      SAI4EN        LL_APB4_GRP1_IsEnabledClock\n (*)
+  *         APB4ENR      DTSEN         LL_APB4_GRP1_IsEnabledClock\n (*)
+  *         APB4ENR      DFSDM2EN      LL_APB4_GRP1_IsEnabledClock   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DAC2   (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
+  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DTS    (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_APB4_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC->APB4ENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable APB4 peripherals clock.
+  * @rmtoll APB4ENR      SYSCFGEN      LL_APB4_GRP1_DisableClock\n
+  *         APB4ENR      LPUART1EN     LL_APB4_GRP1_DisableClock\n
+  *         APB4ENR      SPI6EN        LL_APB4_GRP1_DisableClock\n
+  *         APB4ENR      I2C4EN        LL_APB4_GRP1_DisableClock\n
+  *         APB4ENR      LPTIM2EN      LL_APB4_GRP1_DisableClock\n
+  *         APB4ENR      LPTIM3EN      LL_APB4_GRP1_DisableClock\n
+  *         APB4ENR      LPTIM4EN      LL_APB4_GRP1_DisableClock\n  (*)
+  *         APB4ENR      LPTIM5EN      LL_APB4_GRP1_DisableClock\n  (*)
+  *         APB4ENR      DAC2EN        LL_APB4_GRP1_DisableClock\n  (*)
+  *         APB4ENR      COMP12EN      LL_APB4_GRP1_DisableClock\n
+  *         APB4ENR      VREFEN        LL_APB4_GRP1_DisableClock\n
+  *         APB4ENR      RTCAPBEN      LL_APB4_GRP1_DisableClock\n
+  *         APB4ENR      SAI4EN        LL_APB4_GRP1_DisableClock\n  (*)
+  *         APB4ENR      DTSEN         LL_APB4_GRP1_DisableClock\n  (*)
+  *         APB4ENR      DFSDM2EN      LL_APB4_GRP1_DisableClock    (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DAC2   (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
+  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DTS    (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB4_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB4ENR, Periphs);
+}
+
+/**
+  * @brief  Force APB4 peripherals reset.
+  * @rmtoll APB4RSTR     SYSCFGRST     LL_APB4_GRP1_ForceReset\n
+  *         APB4RSTR     LPUART1RST    LL_APB4_GRP1_ForceReset\n
+  *         APB4RSTR     SPI6RST       LL_APB4_GRP1_ForceReset\n
+  *         APB4RSTR     I2C4RST       LL_APB4_GRP1_ForceReset\n
+  *         APB4RSTR     LPTIM2RST     LL_APB4_GRP1_ForceReset\n
+  *         APB4RSTR     LPTIM3RST     LL_APB4_GRP1_ForceReset\n
+  *         APB4RSTR     LPTIM4RST     LL_APB4_GRP1_ForceReset\n  (*)
+  *         APB4RSTR     LPTIM5RST     LL_APB4_GRP1_ForceReset\n  (*)
+  *         APB4RSTR     DAC2EN        LL_APB4_GRP1_ForceReset\n  (*)
+  *         APB4RSTR     COMP12RST     LL_APB4_GRP1_ForceReset\n
+  *         APB4RSTR     VREFRST       LL_APB4_GRP1_ForceReset\n
+  *         APB4RSTR     SAI4RST       LL_APB4_GRP1_ForceReset\n  (*)
+  *         APB4RSTR     DTSRST        LL_APB4_GRP1_ForceReset\n  (*)
+  *         APB4RSTR     DFSDM2RST     LL_APB4_GRP1_ForceReset    (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DAC2   (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DTS    (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB4_GRP1_ForceReset(uint32_t Periphs)
+{
+  SET_BIT(RCC->APB4RSTR, Periphs);
+}
+
+/**
+  * @brief  Release APB4 peripherals reset.
+  * @rmtoll APB4RSTR     SYSCFGRST     LL_APB4_GRP1_ReleaseReset\n
+  *         APB4RSTR     LPUART1RST    LL_APB4_GRP1_ReleaseReset\n
+  *         APB4RSTR     SPI6RST       LL_APB4_GRP1_ReleaseReset\n
+  *         APB4RSTR     I2C4RST       LL_APB4_GRP1_ReleaseReset\n
+  *         APB4RSTR     LPTIM2RST     LL_APB4_GRP1_ReleaseReset\n
+  *         APB4RSTR     LPTIM3RST     LL_APB4_GRP1_ReleaseReset\n
+  *         APB4RSTR     LPTIM4RST     LL_APB4_GRP1_ReleaseReset\n  (*)
+  *         APB4RSTR     LPTIM5RST     LL_APB4_GRP1_ReleaseReset\n  (*)
+  *         APB4RSTR     DAC2RST       LL_APB4_GRP1_ReleaseReset\n  (*)
+  *         APB4RSTR     COMP12RST     LL_APB4_GRP1_ReleaseReset\n
+  *         APB4RSTR     VREFRST       LL_APB4_GRP1_ReleaseReset\n
+  *         APB4RSTR     SAI4RST       LL_APB4_GRP1_ReleaseReset\n
+  *         APB4RSTR     DTSRST        LL_APB4_GRP1_ReleaseReset\n  (*)
+  *         APB4RSTR     DFSDM2RST     LL_APB4_GRP1_ReleaseReset    (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DAC2   (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DTS    (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB4_GRP1_ReleaseReset(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB4RSTR, Periphs);
+}
+
+/**
+  * @brief  Enable APB4 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB4LPENR    SYSCFGLPEN    LL_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    LPUART1LPEN   LL_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    SPI6LPEN      LL_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    I2C4LPEN      LL_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    LPTIM2LPEN    LL_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    LPTIM3LPEN    LL_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    LPTIM4LPEN    LL_APB4_GRP1_EnableClockSleep\n (*)
+  *         APB4LPENR    LPTIM5LPEN    LL_APB4_GRP1_EnableClockSleep\n (*)
+  *         APB4LPENR    DAC2LPEN      LL_APB4_GRP1_EnableClockSleep\n (*)
+  *         APB4LPENR    COMP12LPEN    LL_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    VREFLPEN      LL_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    RTCAPBLPEN    LL_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    SAI4LPEN      LL_APB4_GRP1_EnableClockSleep\n (*)
+  *         APB4LPENR    DTSLPEN       LL_APB4_GRP1_EnableClockSleep\n (*)
+  *         APB4LPENR    DFSDM2LPEN    LL_APB4_GRP1_EnableClockSleep   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DAC2   (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
+  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DTS    (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB4_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->APB4LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->APB4LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable APB4 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB4LPENR    SYSCFGLPEN    LL_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    LPUART1LPEN   LL_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    SPI6LPEN      LL_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    I2C4LPEN      LL_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    LPTIM2LPEN    LL_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    LPTIM3LPEN    LL_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    LPTIM4LPEN    LL_APB4_GRP1_DisableClockSleep\n (*)
+  *         APB4LPENR    LPTIM5LPEN    LL_APB4_GRP1_DisableClockSleep\n (*)
+  *         APB4LPENR    DAC2LPEN      LL_APB4_GRP1_DisableClockSleep\n (*)
+  *         APB4LPENR    COMP12LPEN    LL_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    VREFLPEN      LL_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    RTCAPBLPEN    LL_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    SAI4LPEN      LL_APB4_GRP1_DisableClockSleep\n (*)
+  *         APB4LPENR    DTSLPEN       LL_APB4_GRP1_DisableClockSleep\n (*)
+  *         APB4LPENR    DFSDM2LPEN    LL_APB4_GRP1_DisableClockSleep   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DAC2   (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
+  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DTS    (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB4_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB4LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_CLKAM CLKAM
+  * @{
+  */
+
+/**
+  * @brief  Enable peripherals clock for CLKAM Mode.
+  * @rmtoll D3AMR / SRDAMR         BDMA          LL_CLKAM_Enable\n
+  *         D3AMR / SRDAMR         LPUART1       LL_CLKAM_Enable\n
+  *         D3AMR / SRDAMR         SPI6          LL_CLKAM_Enable\n
+  *         D3AMR / SRDAMR         I2C4          LL_CLKAM_Enable\n
+  *         D3AMR / SRDAMR         LPTIM2        LL_CLKAM_Enable\n
+  *         D3AMR / SRDAMR         LPTIM3        LL_CLKAM_Enable\n
+  *         D3AMR / SRDAMR         LPTIM4        LL_CLKAM_Enable\n  (*)
+  *         D3AMR / SRDAMR         LPTIM5        LL_CLKAM_Enable\n  (*)
+  *         D3AMR / SRDAMR         DAC2          LL_CLKAM_Enable\n  (*)
+  *         D3AMR / SRDAMR         COMP12        LL_CLKAM_Enable\n
+  *         D3AMR / SRDAMR         VREF          LL_CLKAM_Enable\n
+  *         D3AMR / SRDAMR         RTC           LL_CLKAM_Enable\n
+  *         D3AMR / SRDAMR         CRC           LL_CLKAM_Enable\n
+  *         D3AMR / SRDAMR         SAI4          LL_CLKAM_Enable\n  (*)
+  *         D3AMR / SRDAMR         ADC3          LL_CLKAM_Enable\n  (*)
+  *         D3AMR / SRDAMR         DTS           LL_CLKAM_Enable\n  (*)
+  *         D3AMR / SRDAMR         DFSDM2        LL_CLKAM_Enable\n  (*)
+  *         D3AMR / SRDAMR         BKPRAM        LL_CLKAM_Enable\n
+  *         D3AMR / SRDAMR         SRAM4         LL_CLKAM_Enable
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_CLKAM_PERIPH_BDMA
+  *         @arg @ref LL_CLKAM_PERIPH_GPIO   (*)
+  *         @arg @ref LL_CLKAM_PERIPH_LPUART1
+  *         @arg @ref LL_CLKAM_PERIPH_SPI6
+  *         @arg @ref LL_CLKAM_PERIPH_I2C4
+  *         @arg @ref LL_CLKAM_PERIPH_LPTIM2
+  *         @arg @ref LL_CLKAM_PERIPH_LPTIM3
+  *         @arg @ref LL_CLKAM_PERIPH_LPTIM4 (*)
+  *         @arg @ref LL_CLKAM_PERIPH_LPTIM5 (*)
+  *         @arg @ref LL_CLKAM_PERIPH_DAC2   (*)
+  *         @arg @ref LL_CLKAM_PERIPH_COMP12
+  *         @arg @ref LL_CLKAM_PERIPH_VREF
+  *         @arg @ref LL_CLKAM_PERIPH_RTC
+  *         @arg @ref LL_CLKAM_PERIPH_CRC (*) 
+  *         @arg @ref LL_CLKAM_PERIPH_SAI4 (*)
+  *         @arg @ref LL_CLKAM_PERIPH_ADC3 (*)
+  *         @arg @ref LL_CLKAM_PERIPH_DTS    (*)
+  *         @arg @ref LL_CLKAM_PERIPH_DFSDM2 (*)
+  *         @arg @ref LL_CLKAM_PERIPH_BKPRAM
+  *         @arg @ref LL_CLKAM_PERIPH_SRAM4
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_CLKAM_Enable(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+
+#if defined(RCC_D3AMR_BDMAAMEN)
+  SET_BIT(RCC->D3AMR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->D3AMR, Periphs);
+#else
+  SET_BIT(RCC->SRDAMR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->SRDAMR, Periphs);
+#endif /* RCC_D3AMR_BDMAAMEN */
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable peripherals clock for CLKAM Mode.
+  * @rmtoll D3AMR / SRDAMR        BDMA          LL_CLKAM_Disable\n
+  *         D3AMR / SRDAMR        LPUART1       LL_CLKAM_Disable\n
+  *         D3AMR / SRDAMR        SPI6          LL_CLKAM_Disable\n
+  *         D3AMR / SRDAMR        I2C4          LL_CLKAM_Disable\n
+  *         D3AMR / SRDAMR        LPTIM2        LL_CLKAM_Disable\n
+  *         D3AMR / SRDAMR        LPTIM3        LL_CLKAM_Disable\n
+  *         D3AMR / SRDAMR        LPTIM4        LL_CLKAM_Disable\n (*)
+  *         D3AMR / SRDAMR        LPTIM5        LL_CLKAM_Disable\n (*)
+  *         D3AMR / SRDAMR        DAC2          LL_CLKAM_Disable\n (*)
+  *         D3AMR / SRDAMR        COMP12        LL_CLKAM_Disable\n
+  *         D3AMR / SRDAMR        VREF          LL_CLKAM_Disable\n
+  *         D3AMR / SRDAMR        RTC           LL_CLKAM_Disable\n
+  *         D3AMR / SRDAMR        CRC           LL_CLKAM_Disable\n
+  *         D3AMR / SRDAMR        SAI4          LL_CLKAM_Disable\n (*)
+  *         D3AMR / SRDAMR        ADC3          LL_CLKAM_Disable\n (*)
+  *         D3AMR / SRDAMR        DTS           LL_CLKAM_Disable\n (*)
+  *         D3AMR / SRDAMR        DFSDM2        LL_CLKAM_Disable\n (*)
+  *         D3AMR / SRDAMR        BKPRAM        LL_CLKAM_Disable\n
+  *         D3AMR / SRDAMR        SRAM4         LL_CLKAM_Disable
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_CLKAM_PERIPH_BDMA
+  *         @arg @ref LL_CLKAM_PERIPH_GPIO   (*)
+  *         @arg @ref LL_CLKAM_PERIPH_LPUART1
+  *         @arg @ref LL_CLKAM_PERIPH_SPI6
+  *         @arg @ref LL_CLKAM_PERIPH_I2C4
+  *         @arg @ref LL_CLKAM_PERIPH_LPTIM2
+  *         @arg @ref LL_CLKAM_PERIPH_LPTIM3
+  *         @arg @ref LL_CLKAM_PERIPH_LPTIM4 (*)
+  *         @arg @ref LL_CLKAM_PERIPH_LPTIM5 (*)
+  *         @arg @ref LL_CLKAM_PERIPH_DAC2   (*)
+  *         @arg @ref LL_CLKAM_PERIPH_COMP12
+  *         @arg @ref LL_CLKAM_PERIPH_VREF
+  *         @arg @ref LL_CLKAM_PERIPH_RTC
+  *         @arg @ref LL_CLKAM_PERIPH_CRC (*) 
+  *         @arg @ref LL_CLKAM_PERIPH_SAI4 (*)
+  *         @arg @ref LL_CLKAM_PERIPH_ADC3 (*)
+  *         @arg @ref LL_CLKAM_PERIPH_DTS    (*)
+  *         @arg @ref LL_CLKAM_PERIPH_DFSDM2  (*)
+  *         @arg @ref LL_CLKAM_PERIPH_BKPRAM
+  *         @arg @ref LL_CLKAM_PERIPH_SRAM4
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_CLKAM_Disable(uint32_t Periphs)
+{
+#if defined(RCC_D3AMR_BDMAAMEN)
+  CLEAR_BIT(RCC->D3AMR, Periphs);
+#else
+  CLEAR_BIT(RCC->SRDAMR, Periphs);
+#endif /* RCC_D3AMR_BDMAAMEN */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_CKGA CKGA
+  * @{
+  */
+
+#if defined(RCC_CKGAENR_AXICKG)
+
+
+/**
+  * @brief  Enable clock gating for AXI bus peripherals.
+  * @rmtoll
+  * @param :
+  * @retval None
+*/
+__STATIC_INLINE void LL_CKGA_Enable(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->CKGAENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->CKGAENR, Periphs);
+  (void)tmpreg;
+}
+
+#endif /* RCC_CKGAENR_AXICKG */
+
+#if defined(RCC_CKGAENR_AXICKG)
+
+/**
+  * @brief  Disable  clock gating for AXI bus peripherals.
+  * @rmtoll
+  * @param :
+  * @retval None
+*/
+__STATIC_INLINE void LL_CKGA_Disable(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->CKGAENR, Periphs);
+}
+
+#endif /* RCC_CKGAENR_AXICKG */
+
+/**
+  * @}
+  */
+
+#if defined(DUAL_CORE)
+/** @addtogroup BUS_LL_EF_AHB3 AHB3
+  * @{
+  */
+
+/**
+  * @brief  Enable C1 AHB3 peripherals clock.
+  * @rmtoll AHB3ENR      MDMAEN        LL_C1_AHB3_GRP1_EnableClock\n
+  *         AHB3ENR      DMA2DEN       LL_C1_AHB3_GRP1_EnableClock\n
+  *         AHB3ENR      JPGDECEN      LL_C1_AHB3_GRP1_EnableClock\n
+  *         AHB3ENR      FMCEN         LL_C1_AHB3_GRP1_EnableClock\n
+  *         AHB3ENR      QSPIEN        LL_C1_AHB3_GRP1_EnableClock\n (*)
+  *         AHB3ENR      OSPI1EN       LL_C1_AHB3_GRP1_EnableClock\n (*)
+  *         AHB3ENR      OSPI2EN       LL_C1_AHB3_GRP1_EnableClock\n (*)
+  *         AHB3ENR      IOMNGREN      LL_C1_AHB3_GRP1_EnableClock\n (*)
+  *         AHB3ENR      OTFDEC1EN     LL_C1_AHB3_GRP1_EnableClock\n (*)
+  *         AHB3ENR      OTFDEC2EN     LL_C1_AHB3_GRP1_EnableClock\n (*)
+  *         AHB3ENR      GFXMMU        LL_C1_AHB3_GRP1_EnableClock\n (*)
+  *         AHB3ENR      SDMMC1EN      LL_C1_AHB3_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI    (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1   (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2   (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM  (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU  (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_AHB3_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C1->AHB3ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C1->AHB3ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if C1 AHB3 peripheral clock is enabled or not
+  * @rmtoll AHB3ENR      MDMAEN        LL_C1_AHB3_GRP1_IsEnabledClock\n
+  *         AHB3ENR      DMA2DEN       LL_C1_AHB3_GRP1_IsEnabledClock\n
+  *         AHB3ENR      JPGDECEN      LL_C1_AHB3_GRP1_IsEnabledClock\n
+  *         AHB3ENR      FMCEN         LL_C1_AHB3_GRP1_IsEnabledClock\n
+  *         AHB3ENR      QSPIEN        LL_C1_AHB3_GRP1_IsEnabledClock\n (*)
+  *         AHB3ENR      OSPI1EN       LL_C1_AHB3_GRP1_IsEnabledClock\n (*)
+  *         AHB3ENR      OSPI2EN       LL_C1_AHB3_GRP1_IsEnabledClock\n (*)
+  *         AHB3ENR      IOMNGREN      LL_C1_AHB3_GRP1_IsEnabledClock\n (*)
+  *         AHB3ENR      OTFDEC1EN     LL_C1_AHB3_GRP1_IsEnabledClock\n (*)
+  *         AHB3ENR      OTFDEC2EN     LL_C1_AHB3_GRP1_IsEnabledClock\n (*)
+  *         AHB3ENR      GFXMMU        LL_C1_AHB3_GRP1_IsEnabledClock\n (*)
+  *         AHB3ENR      SDMMC1EN      LL_C1_AHB3_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI    (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1   (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2   (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM  (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU  (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
+  *
+  *         (*) value not defined in all devices.
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_C1_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC_C1->AHB3ENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable C1 AHB3 peripherals clock.
+  * @rmtoll AHB3ENR      MDMAEN        LL_C1_AHB3_GRP1_DisableClock\n
+  *         AHB3ENR      DMA2DEN       LL_C1_AHB3_GRP1_DisableClock\n
+  *         AHB3ENR      JPGDECEN      LL_C1_AHB3_GRP1_DisableClock\n
+  *         AHB3ENR      FMCEN         LL_C1_AHB3_GRP1_DisableClock\n
+  *         AHB3ENR      QSPIEN        LL_C1_AHB3_GRP1_DisableClock\n (*)
+  *         AHB3ENR      OSPI1EN       LL_C1_AHB3_GRP1_DisableClock\n (*)
+  *         AHB3ENR      OSPI2EN       LL_C1_AHB3_GRP1_DisableClock\n (*)
+  *         AHB3ENR      IOMNGREN      LL_C1_AHB3_GRP1_DisableClock\n (*)
+  *         AHB3ENR      OTFDEC1EN     LL_C1_AHB3_GRP1_DisableClock\n (*)
+  *         AHB3ENR      OTFDEC2EN     LL_C1_AHB3_GRP1_DisableClock\n (*)
+  *         AHB3ENR      GFXMMU        LL_C1_AHB3_GRP1_DisableClock\n (*)
+  *         AHB3ENR      SDMMC1EN      LL_C1_AHB3_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC  (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI    (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1   (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2   (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM  (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU  (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_AHB3_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C1->AHB3ENR, Periphs);
+}
+
+/**
+  * @brief  Enable C1 AHB3 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll AHB3LPENR    MDMALPEN      LL_C1_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    DMA2DLPEN     LL_C1_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    JPGDECLPEN    LL_C1_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    FMCLPEN       LL_C1_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    QSPILPEN      LL_C1_AHB3_GRP1_EnableClockSleep\n  (*)
+  *         AHB3LPENR    OSPI1LPEN     LL_C1_AHB3_GRP1_EnableClockSleep\n  (*)
+  *         AHB3LPENR    OSPI2LPEN     LL_C1_AHB3_GRP1_EnableClockSleep\n  (*)
+  *         AHB3LPENR    IOMNGRLPEN    LL_C1_AHB3_GRP1_EnableClockSleep\n  (*)
+  *         AHB3LPENR    OTFDEC1LPEN   LL_C1_AHB3_GRP1_EnableClockSleep\n  (*)
+  *         AHB3LPENR    OTFDEC1LPEN   LL_C1_AHB3_GRP1_EnableClockSleep\n  (*)
+  *         AHB3LPENR    GFXMMULPEN    LL_C1_AHB3_GRP1_EnableClockSleep\n  (*)
+  *         AHB3LPENR    SDMMC1LPEN    LL_C1_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    FLASHLPEN     LL_C1_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    DTCM1LPEN     LL_C1_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    DTCM2LPEN     LL_C1_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    ITCMLPEN      LL_C1_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    AXISRAMLPEN   LL_C1_AHB3_GRP1_EnableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC   (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI     (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1    (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2    (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU  (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_AHB3_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C1->AHB3LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C1->AHB3LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable C1 AHB3 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll AHB3LPENR    MDMALPEN      LL_C1_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    DMA2DLPEN     LL_C1_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    JPGDECLPEN    LL_C1_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    FMCLPEN       LL_C1_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    QSPILPEN      LL_C1_AHB3_GRP1_DisableClockSleep\n  (*)
+  *         AHB3LPENR    OSPI1LPEN     LL_C1_AHB3_GRP1_DisableClockSleep\n  (*)
+  *         AHB3LPENR    OSPI2LPEN     LL_C1_AHB3_GRP1_DisableClockSleep\n  (*)
+  *         AHB3LPENR    IOMNGRLPEN    LL_C1_AHB3_GRP1_DisableClockSleep\n  (*)
+  *         AHB3LPENR    OTFDEC1LPEN   LL_C1_AHB3_GRP1_DisableClockSleep\n  (*)
+  *         AHB3LPENR    OTFDEC1LPEN   LL_C1_AHB3_GRP1_DisableClockSleep\n  (*)
+  *         AHB3LPENR    GFXMMULPEN    LL_C1_AHB3_GRP1_DisableClockSleep\n  (*)
+  *         AHB3LPENR    SDMMC1LPEN    LL_C1_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    FLASHLPEN     LL_C1_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    DTCM1LPEN     LL_C1_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    DTCM2LPEN     LL_C1_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    ITCMLPEN      LL_C1_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    AXISRAMLPEN   LL_C1_AHB3_GRP1_DisableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC   (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI     (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1    (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2    (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU  (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_AHB3_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C1->AHB3LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup BUS_LL_EF_AHB1 AHB1
+  * @{
+  */
+
+/**
+  * @brief  Enable C1 AHB1 peripherals clock.
+  * @rmtoll AHB1ENR      DMA1EN        LL_C1_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      DMA2EN        LL_C1_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      ADC12EN       LL_C1_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      CRCEN         LL_C1_AHB1_GRP1_EnableClock\n  (*)
+  *         AHB1ENR      ARTEN         LL_C1_AHB1_GRP1_EnableClock\n  (*)
+  *         AHB1ENR      ETH1MACEN     LL_C1_AHB1_GRP1_EnableClock\n  (*)
+  *         AHB1ENR      ETH1TXEN      LL_C1_AHB1_GRP1_EnableClock\n  (*)
+  *         AHB1ENR      ETH1RXEN      LL_C1_AHB1_GRP1_EnableClock\n  (*)
+  *         AHB1ENR      USB1OTGHSEN   LL_C1_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      USB1OTGHSULPIEN  LL_C1_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      USB2OTGHSEN   LL_C1_AHB1_GRP1_EnableClock\n   (*)
+  *         AHB1ENR      USB2OTGHSULPIEN  LL_C1_AHB1_GRP1_EnableClock  (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC  (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX   (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX   (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS     (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_AHB1_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C1->AHB1ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C1->AHB1ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if C1 AHB1 peripheral clock is enabled or not
+  * @rmtoll AHB1ENR      DMA1EN        LL_C1_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      DMA2EN        LL_C1_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      ADC12EN       LL_C1_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      CRCEN         LL_C1_AHB1_GRP1_IsEnabledClock\n  (*)
+  *         AHB1ENR      ARTEN         LL_C1_AHB1_GRP1_IsEnabledClock\n  (*)
+  *         AHB1ENR      ETH1MACEN     LL_C1_AHB1_GRP1_IsEnabledClock\n  (*)
+  *         AHB1ENR      ETH1TXEN      LL_C1_AHB1_GRP1_IsEnabledClock\n  (*)
+  *         AHB1ENR      ETH1RXEN      LL_C1_AHB1_GRP1_IsEnabledClock\n  (*)
+  *         AHB1ENR      USB1OTGHSEN   LL_C1_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      USB1OTGHSULPIEN  LL_C1_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      USB2OTGHSEN   LL_C1_AHB1_GRP1_IsEnabledClock\n  (*)
+  *         AHB1ENR      USB2OTGHSULPIEN  LL_C1_AHB1_GRP1_IsEnabledClock (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC  (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX   (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX   (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS     (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_C1_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC_C1->AHB1ENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable C1 AHB1 peripherals clock.
+  * @rmtoll AHB1ENR      DMA1EN        LL_C1_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      DMA2EN        LL_C1_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      ADC12EN       LL_C1_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      CRCEN         LL_C1_AHB1_GRP1_DisableClock\n (*)
+  *         AHB1ENR      ARTEN         LL_C1_AHB1_GRP1_DisableClock\n (*)
+  *         AHB1ENR      ETH1MACEN     LL_C1_AHB1_GRP1_DisableClock\n (*)
+  *         AHB1ENR      ETH1TXEN      LL_C1_AHB1_GRP1_DisableClock\n (*)
+  *         AHB1ENR      ETH1RXEN      LL_C1_AHB1_GRP1_DisableClock\n (*)
+  *         AHB1ENR      USB1OTGHSEN   LL_C1_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      USB1OTGHSULPIEN  LL_C1_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      USB2OTGHSEN   LL_C1_AHB1_GRP1_DisableClock\n (*)
+  *         AHB1ENR      USB2OTGHSULPIEN  LL_C1_AHB1_GRP1_DisableClock (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC  (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX   (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX   (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS     (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_AHB1_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C1->AHB1ENR, Periphs);
+}
+
+/**
+  * @brief  Enable C1 AHB1 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll AHB1LPENR    DMA1LPEN      LL_C1_AHB1_GRP1_EnableClockSleep\n
+  *         AHB1LPENR    DMA2LPEN      LL_C1_AHB1_GRP1_EnableClockSleep\n
+  *         AHB1LPENR    ADC12LPEN     LL_C1_AHB1_GRP1_EnableClockSleep\n
+  *         AHB1LPENR    CRCLPEN       LL_C1_AHB1_GRP1_EnableClockSleep\n (*)
+  *         AHB1LPENR    ARTLPEN       LL_C1_AHB1_GRP1_EnableClockSleep\n (*)
+  *         AHB1LPENR    ETH1MACLPEN   LL_C1_AHB1_GRP1_EnableClockSleep\n (*)
+  *         AHB1LPENR    ETH1TXLPEN    LL_C1_AHB1_GRP1_EnableClockSleep\n (*)
+  *         AHB1LPENR    ETH1RXLPEN    LL_C1_AHB1_GRP1_EnableClockSleep\n (*)
+  *         AHB1LPENR    USB1OTGHSLPEN  LL_C1_AHB1_GRP1_EnableClockSleep\n
+  *         AHB1LPENR    USB1OTGHSULPILPEN  LL_C1_AHB1_GRP1_EnableClockSleep\n
+  *         AHB1LPENR    USB2OTGHSLPEN  LL_C1_AHB1_GRP1_EnableClockSleep\n   (*)
+  *         AHB1LPENR    USB2OTGHSULPILPEN  LL_C1_AHB1_GRP1_EnableClockSleep (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC  (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX   (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX   (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS     (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_AHB1_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C1->AHB1LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C1->AHB1LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable C1 AHB1 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll AHB1LPENR    DMA1LPEN      LL_C1_AHB1_GRP1_DisableClockSleep\n
+  *         AHB1LPENR    DMA2LPEN      LL_C1_AHB1_GRP1_DisableClockSleep\n
+  *         AHB1LPENR    ADC12LPEN     LL_C1_AHB1_GRP1_DisableClockSleep\n
+  *         AHB1LPENR    CRCLPEN       LL_C1_AHB1_GRP1_DisableClockSleep\n (*)
+  *         AHB1LPENR    ARTLPEN       LL_C1_AHB1_GRP1_DisableClockSleep\n (*)
+  *         AHB1LPENR    ETH1MACLPEN   LL_C1_AHB1_GRP1_DisableClockSleep\n (*)
+  *         AHB1LPENR    ETH1TXLPEN    LL_C1_AHB1_GRP1_DisableClockSleep\n (*)
+  *         AHB1LPENR    ETH1RXLPEN    LL_C1_AHB1_GRP1_DisableClockSleep\n (*)
+  *         AHB1LPENR    USB1OTGHSLPEN  LL_C1_AHB1_GRP1_DisableClockSleep\n
+  *         AHB1LPENR    USB1OTGHSULPILPEN  LL_C1_AHB1_GRP1_DisableClockSleep\n
+  *         AHB1LPENR    USB2OTGHSLPEN  LL_C1_AHB1_GRP1_DisableClockSleep\n   (*)
+  *         AHB1LPENR    USB2OTGHSULPILPEN  LL_C1_AHB1_GRP1_DisableClockSleep (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC  (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX   (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX   (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS     (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_AHB1_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C1->AHB1LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup BUS_LL_EF_AHB2 AHB2
+  * @{
+  */
+
+/**
+  * @brief  Enable C1 AHB2 peripherals clock.
+  * @rmtoll AHB2ENR      DCMIEN        LL_C1_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      HSEMEN        LL_C1_AHB2_GRP1_EnableClock\n (*)
+  *         AHB2ENR      CRYPEN        LL_C1_AHB2_GRP1_EnableClock\n (*)
+  *         AHB2ENR      HASHEN        LL_C1_AHB2_GRP1_EnableClock\n (*)
+  *         AHB2ENR      RNGEN         LL_C1_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      SDMMC2EN      LL_C1_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      BDMA1EN       LL_C1_AHB2_GRP1_EnableClock\n (*)
+  *         AHB2ENR      D2SRAM1EN     LL_C1_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      D2SRAM2EN     LL_C1_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      D2SRAM3EN     LL_C1_AHB2_GRP1_EnableClock   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1  (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_AHB2_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C1->AHB2ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C1->AHB2ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if C1 AHB2 peripheral clock is enabled or not
+  * @rmtoll AHB2ENR      DCMIEN        LL_C1_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      HSEMEN        LL_C1_AHB2_GRP1_IsEnabledClock\n (*)
+  *         AHB2ENR      CRYPEN        LL_C1_AHB2_GRP1_IsEnabledClock\n (*)
+  *         AHB2ENR      HASHEN        LL_C1_AHB2_GRP1_IsEnabledClock\n (*)
+  *         AHB2ENR      RNGEN         LL_C1_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      SDMMC2EN      LL_C1_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      BDMA1EN       LL_C1_AHB2_GRP1_IsEnabledClock\n (*)
+  *         AHB2ENR      D2SRAM1EN     LL_C1_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      D2SRAM2EN     LL_C1_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      D2SRAM3EN     LL_C1_AHB2_GRP1_IsEnabledClock   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1  (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_C1_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC_C1->AHB2ENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable C1 AHB2 peripherals clock.
+  * @rmtoll AHB2ENR      DCMIEN        LL_C1_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      HSEMEN        LL_C1_AHB2_GRP1_DisableClock\n (*)
+  *         AHB2ENR      CRYPEN        LL_C1_AHB2_GRP1_DisableClock\n (*)
+  *         AHB2ENR      HASHEN        LL_C1_AHB2_GRP1_DisableClock\n (*)
+  *         AHB2ENR      RNGEN         LL_C1_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      SDMMC2EN      LL_C1_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      BDMA1EN       LL_C1_AHB2_GRP1_DisableClock\n (*)
+  *         AHB2ENR      D2SRAM1EN     LL_C1_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      D2SRAM2EN     LL_C1_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      D2SRAM3EN     LL_C1_AHB2_GRP1_DisableClock   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1  (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_AHB2_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C1->AHB2ENR, Periphs);
+}
+
+/**
+  * @brief  Enable C1 AHB2 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll AHB2LPENR    DCMILPEN      LL_C1_AHB2_GRP1_EnableClockSleep\n
+  *         AHB2LPENR    CRYPLPEN      LL_C1_AHB2_GRP1_EnableClockSleep\n (*)
+  *         AHB2LPENR    HASHLPEN      LL_C1_AHB2_GRP1_EnableClockSleep\n (*)
+  *         AHB2LPENR    RNGLPEN       LL_C1_AHB2_GRP1_EnableClockSleep\n
+  *         AHB2LPENR    SDMMC2LPEN    LL_C1_AHB2_GRP1_EnableClockSleep\n
+  *         AHB2LPENR    D2SRAM1LPEN   LL_C1_AHB2_GRP1_EnableClockSleep\n
+  *         AHB2LPENR    BDAM1LPEN     LL_C1_AHB2_GRP1_EnableClockSleep\n (*)
+  *         AHB2LPENR    D2SRAM2LPEN   LL_C1_AHB2_GRP1_EnableClockSleep\n
+  *         AHB2LPENR    D2SRAM3LPEN   LL_C1_AHB2_GRP1_EnableClockSleep   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_AHB2_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C1->AHB2LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C1->AHB2LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable C1 AHB2 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll AHB2LPENR    DCMILPEN      LL_C1_AHB2_GRP1_DisableClockSleep\n
+  *         AHB2LPENR    CRYPLPEN      LL_C1_AHB2_GRP1_DisableClockSleep\n (*)
+  *         AHB2LPENR    HASHLPEN      LL_C1_AHB2_GRP1_DisableClockSleep\n (*)
+  *         AHB2LPENR    RNGLPEN       LL_C1_AHB2_GRP1_DisableClockSleep\n
+  *         AHB2LPENR    SDMMC2LPEN    LL_C1_AHB2_GRP1_DisableClockSleep\n
+  *         AHB2LPENR    BDAM1LPEN     LL_C1_AHB2_GRP1_DisableClockSleep\n (*)
+  *         AHB2LPENR    D2SRAM1LPEN   LL_C1_AHB2_GRP1_DisableClockSleep\n
+  *         AHB2LPENR    D2SRAM2LPEN   LL_C1_AHB2_GRP1_DisableClockSleep\n
+  *         AHB2LPENR    D2SRAM3LPEN   LL_C1_AHB2_GRP1_DisableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_AHB2_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C1->AHB2LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup BUS_LL_EF_AHB4 AHB4
+  * @{
+  */
+
+/**
+  * @brief  Enable C1 AHB4 peripherals clock.
+  * @rmtoll AHB4ENR      GPIOAEN       LL_C1_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOBEN       LL_C1_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOCEN       LL_C1_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIODEN       LL_C1_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOEEN       LL_C1_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOFEN       LL_C1_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOGEN       LL_C1_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOHEN       LL_C1_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOIEN       LL_C1_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOJEN       LL_C1_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOKEN       LL_C1_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      CRCEN         LL_C1_AHB4_GRP1_EnableClock\n (*)
+  *         AHB4ENR      BDMAEN        LL_C1_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      ADC3EN        LL_C1_AHB4_GRP1_EnableClock\n (*)
+  *         AHB4ENR      HSEMEN        LL_C1_AHB4_GRP1_EnableClock\n (*)
+  *         AHB4ENR      BKPRAMEN      LL_C1_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      SRAM4EN       LL_C1_AHB4_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI  (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC   (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM  (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_AHB4_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C1->AHB4ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C1->AHB4ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if C1 AHB4 peripheral clock is enabled or not
+  * @rmtoll AHB4ENR      GPIOAEN       LL_C1_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOBEN       LL_C1_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOCEN       LL_C1_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIODEN       LL_C1_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOEEN       LL_C1_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOFEN       LL_C1_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOGEN       LL_C1_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOHEN       LL_C1_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOIEN       LL_C1_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOJEN       LL_C1_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOKEN       LL_C1_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      CRCEN         LL_C1_AHB4_GRP1_IsEnabledClock\n (*)
+  *         AHB4ENR      BDMAEN        LL_C1_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      ADC3EN        LL_C1_AHB4_GRP1_IsEnabledClock\n (*)
+  *         AHB4ENR      HSEMEN        LL_C1_AHB4_GRP1_IsEnabledClock\n (*)
+  *         AHB4ENR      BKPRAMEN      LL_C1_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      SRAM4EN       LL_C1_AHB4_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI  (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC   (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM  (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
+  *
+  *         (*) value not defined in all devices.
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_C1_AHB4_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC_C1->AHB4ENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable C1 AHB4 peripherals clock.
+  * @rmtoll AHB4ENR      GPIOAEN       LL_C1_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOBEN       LL_C1_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOCEN       LL_C1_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIODEN       LL_C1_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOEEN       LL_C1_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOFEN       LL_C1_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOGEN       LL_C1_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOHEN       LL_C1_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOIEN       LL_C1_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOJEN       LL_C1_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOKEN       LL_C1_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      CRCEN         LL_C1_AHB4_GRP1_DisableClock\n (*)
+  *         AHB4ENR      BDMAEN        LL_C1_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      ADC3EN        LL_C1_AHB4_GRP1_DisableClock\n (*)
+  *         AHB4ENR      HSEMEN        LL_C1_AHB4_GRP1_DisableClock\n (*)
+  *         AHB4ENR      BKPRAMEN      LL_C1_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      SRAM4EN       LL_C1_AHB4_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI  (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC   (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM  (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_AHB4_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C1->AHB4ENR, Periphs);
+}
+
+/**
+  * @brief  Enable C1 AHB4 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll AHB4LPENR    GPIOALPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOBLPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOCLPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIODLPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOELPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOFLPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOGLPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOHLPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOILPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOJLPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOKLPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    CRCLPEN       LL_C1_AHB4_GRP1_EnableClockSleep\n (*)
+  *         AHB4LPENR    BDMALPEN      LL_C1_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    ADC3LPEN      LL_C1_AHB4_GRP1_EnableClockSleep\n (*)
+  *         AHB4LPENR    BKPRAMLPEN    LL_C1_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    SRAM4LPEN     LL_C1_AHB4_GRP1_EnableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI  (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC   (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_AHB4_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C1->AHB4LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C1->AHB4LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable C1 AHB4 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll AHB4LPENR    GPIOALPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOBLPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOCLPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIODLPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOELPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOFLPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOGLPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOHLPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOILPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOJLPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOKLPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    CRCLPEN       LL_C1_AHB4_GRP1_DisableClockSleep\n (*)
+  *         AHB4LPENR    BDMALPEN      LL_C1_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    ADC3LPEN      LL_C1_AHB4_GRP1_DisableClockSleep\n (*)
+  *         AHB4LPENR    BKPRAMLPEN    LL_C1_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    SRAM4LPEN     LL_C1_AHB4_GRP1_DisableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI  (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC   (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_AHB4_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C1->AHB4LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup BUS_LL_EF_APB3 APB3
+  * @{
+  */
+
+/**
+  * @brief  Enable C1 APB3 peripherals clock.
+  * @rmtoll APB3ENR      LTDCEN        LL_C1_APB3_GRP1_EnableClock\n (*)
+  *         APB3ENR      DSIEN         LL_C1_APB3_GRP1_EnableClock\n (*)
+  *         APB3ENR      WWDG1EN       LL_C1_APB3_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_APB3_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C1->APB3ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C1->APB3ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if C1 APB3 peripheral clock is enabled or not
+  * @rmtoll APB3ENR      LTDCEN        LL_C1_APB3_GRP1_IsEnabledClock\n (*)
+  *         APB3ENR      DSIEN         LL_C1_APB3_GRP1_IsEnabledClock\n (*)
+  *         APB3ENR      WWDG1EN       LL_C1_APB3_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
+  *
+  *         (*) value not defined in all devices.
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_C1_APB3_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC_C1->APB3ENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable C1 APB3 peripherals clock.
+  * @rmtoll APB3ENR      LTDCEN        LL_C1_APB3_GRP1_DisableClock\n (*)
+  *         APB3ENR      DSIEN         LL_C1_APB3_GRP1_DisableClock\n (*)
+  *         APB3ENR      WWDG1EN       LL_C1_APB3_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
+
+  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_APB3_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C1->APB3ENR, Periphs);
+}
+
+/**
+  * @brief  Enable C1 APB3 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB3LPENR    LTDCLPEN      LL_C1_APB3_GRP1_EnableClockSleep\n (*)
+  *         APB3LPENR    DSILPEN       LL_C1_APB3_GRP1_EnableClockSleep\n (*)
+  *         APB3LPENR    WWDG1LPEN     LL_C1_APB3_GRP1_EnableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_APB3_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C1->APB3LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C1->APB3LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable C1 APB3 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB3LPENR    LTDCLPEN      LL_C1_APB3_GRP1_DisableClockSleep\n (*)
+  *         APB3LPENR    DSILPEN       LL_C1_APB3_GRP1_DisableClockSleep\n (*)
+  *         APB3LPENR    WWDG1LPEN     LL_C1_APB3_GRP1_DisableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_APB3_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C1->APB3LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup BUS_LL_EF_APB1 APB1
+  * @{
+  */
+
+/**
+  * @brief  Enable C1 APB1 peripherals clock.
+  * @rmtoll APB1LENR     TIM2EN        LL_C1_APB1_GRP1_EnableClock\n
+  *         APB1LENR     TIM3EN        LL_C1_APB1_GRP1_EnableClock\n
+  *         APB1LENR     TIM4EN        LL_C1_APB1_GRP1_EnableClock\n
+  *         APB1LENR     TIM5EN        LL_C1_APB1_GRP1_EnableClock\n
+  *         APB1LENR     TIM6EN        LL_C1_APB1_GRP1_EnableClock\n
+  *         APB1LENR     TIM7EN        LL_C1_APB1_GRP1_EnableClock\n
+  *         APB1LENR     TIM12EN       LL_C1_APB1_GRP1_EnableClock\n
+  *         APB1LENR     TIM13EN       LL_C1_APB1_GRP1_EnableClock\n
+  *         APB1LENR     TIM14EN       LL_C1_APB1_GRP1_EnableClock\n
+  *         APB1LENR     LPTIM1EN      LL_C1_APB1_GRP1_EnableClock\n
+  *         APB1LENR     WWDG2EN       LL_C1_APB1_GRP1_EnableClock\n (*)
+  *         APB1LENR     SPI2EN        LL_C1_APB1_GRP1_EnableClock\n
+  *         APB1LENR     SPI3EN        LL_C1_APB1_GRP1_EnableClock\n
+  *         APB1LENR     SPDIFRXEN     LL_C1_APB1_GRP1_EnableClock\n
+  *         APB1LENR     USART2EN      LL_C1_APB1_GRP1_EnableClock\n
+  *         APB1LENR     USART3EN      LL_C1_APB1_GRP1_EnableClock\n
+  *         APB1LENR     UART4EN       LL_C1_APB1_GRP1_EnableClock\n
+  *         APB1LENR     UART5EN       LL_C1_APB1_GRP1_EnableClock\n
+  *         APB1LENR     I2C1EN        LL_C1_APB1_GRP1_EnableClock\n
+  *         APB1LENR     I2C2EN        LL_C1_APB1_GRP1_EnableClock\n
+  *         APB1LENR     I2C3EN        LL_C1_APB1_GRP1_EnableClock\n
+  *         APB1LENR     CECEN         LL_C1_APB1_GRP1_EnableClock\n
+  *         APB1LENR     DAC12EN       LL_C1_APB1_GRP1_EnableClock\n
+  *         APB1LENR     UART7EN       LL_C1_APB1_GRP1_EnableClock\n
+  *         APB1LENR     UART8EN       LL_C1_APB1_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_APB1_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C1->APB1LENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C1->APB1LENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if C1 APB1 peripheral clock is enabled or not
+  * @rmtoll APB1LENR     TIM2EN        LL_C1_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     TIM3EN        LL_C1_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     TIM4EN        LL_C1_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     TIM5EN        LL_C1_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     TIM6EN        LL_C1_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     TIM7EN        LL_C1_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     TIM12EN       LL_C1_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     TIM13EN       LL_C1_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     TIM14EN       LL_C1_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     LPTIM1EN      LL_C1_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     WWDG2EN       LL_C1_APB1_GRP1_IsEnabledClock\n (*)
+  *         APB1LENR     SPI2EN        LL_C1_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     SPI3EN        LL_C1_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     SPDIFRXEN     LL_C1_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     USART2EN      LL_C1_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     USART3EN      LL_C1_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     UART4EN       LL_C1_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     UART5EN       LL_C1_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     I2C1EN        LL_C1_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     I2C2EN        LL_C1_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     I2C3EN        LL_C1_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     CECEN         LL_C1_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     DAC12EN       LL_C1_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     UART7EN       LL_C1_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     UART8EN       LL_C1_APB1_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+  *
+  *         (*) value not defined in all devices.
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_C1_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC_C1->APB1LENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable C1 APB1 peripherals clock.
+  * @rmtoll APB1LENR     TIM2EN        LL_C1_APB1_GRP1_DisableClock\n
+  *         APB1LENR     TIM3EN        LL_C1_APB1_GRP1_DisableClock\n
+  *         APB1LENR     TIM4EN        LL_C1_APB1_GRP1_DisableClock\n
+  *         APB1LENR     TIM5EN        LL_C1_APB1_GRP1_DisableClock\n
+  *         APB1LENR     TIM6EN        LL_C1_APB1_GRP1_DisableClock\n
+  *         APB1LENR     TIM7EN        LL_C1_APB1_GRP1_DisableClock\n
+  *         APB1LENR     TIM12EN       LL_C1_APB1_GRP1_DisableClock\n
+  *         APB1LENR     TIM13EN       LL_C1_APB1_GRP1_DisableClock\n
+  *         APB1LENR     TIM14EN       LL_C1_APB1_GRP1_DisableClock\n
+  *         APB1LENR     LPTIM1EN      LL_C1_APB1_GRP1_DisableClock\n
+  *         APB1LENR     WWDG2EN       LL_C1_APB1_GRP1_DisableClock\n (*)
+  *         APB1LENR     SPI2EN        LL_C1_APB1_GRP1_DisableClock\n
+  *         APB1LENR     SPI3EN        LL_C1_APB1_GRP1_DisableClock\n
+  *         APB1LENR     SPDIFRXEN     LL_C1_APB1_GRP1_DisableClock\n
+  *         APB1LENR     USART2EN      LL_C1_APB1_GRP1_DisableClock\n
+  *         APB1LENR     USART3EN      LL_C1_APB1_GRP1_DisableClock\n
+  *         APB1LENR     UART4EN       LL_C1_APB1_GRP1_DisableClock\n
+  *         APB1LENR     UART5EN       LL_C1_APB1_GRP1_DisableClock\n
+  *         APB1LENR     I2C1EN        LL_C1_APB1_GRP1_DisableClock\n
+  *         APB1LENR     I2C2EN        LL_C1_APB1_GRP1_DisableClock\n
+  *         APB1LENR     I2C3EN        LL_C1_APB1_GRP1_DisableClock\n
+  *         APB1LENR     CECEN         LL_C1_APB1_GRP1_DisableClock\n
+  *         APB1LENR     DAC12EN       LL_C1_APB1_GRP1_DisableClock\n
+  *         APB1LENR     UART7EN       LL_C1_APB1_GRP1_DisableClock\n
+  *         APB1LENR     UART8EN       LL_C1_APB1_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+  *
+  *         (*) value not defined in all devices.
+  * @retval uint32_t
+*/
+__STATIC_INLINE void LL_C1_APB1_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C1->APB1LENR, Periphs);
+}
+
+/**
+  * @brief  Enable C1 APB1 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB1LLPENR   TIM2LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   TIM3LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   TIM4LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   TIM5LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   TIM6LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   TIM7LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   TIM12LPEN     LL_C1_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   TIM13LPEN     LL_C1_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   TIM14LPEN     LL_C1_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   LPTIM1LPEN    LL_C1_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   WWDG2LPEN     LL_C1_APB1_GRP1_EnableClockSleep\n (*)
+  *         APB1LLPENR   SPI2LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   SPI3LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   SPDIFRXLPEN   LL_C1_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   USART2LPEN    LL_C1_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   USART3LPEN    LL_C1_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   UART4LPEN     LL_C1_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   UART5LPEN     LL_C1_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   I2C1LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   I2C2LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   I2C3LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   CECLPEN       LL_C1_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   DAC12LPEN     LL_C1_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   UART7LPEN     LL_C1_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   UART8LPEN     LL_C1_APB1_GRP1_EnableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_APB1_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C1->APB1LLPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C1->APB1LLPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable C1 APB1 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB1LLPENR   TIM2LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   TIM3LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   TIM4LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   TIM5LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   TIM6LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   TIM7LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   TIM12LPEN     LL_C1_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   TIM13LPEN     LL_C1_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   TIM14LPEN     LL_C1_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   LPTIM1LPEN    LL_C1_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   WWDG2LPEN     LL_C1_APB1_GRP1_DisableClockSleep\n (*)
+  *         APB1LLPENR   SPI2LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   SPI3LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   SPDIFRXLPEN   LL_C1_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   USART2LPEN    LL_C1_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   USART3LPEN    LL_C1_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   UART4LPEN     LL_C1_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   UART5LPEN     LL_C1_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   I2C1LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   I2C2LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   I2C3LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   CECLPEN       LL_C1_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   DAC12LPEN     LL_C1_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   UART7LPEN     LL_C1_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   UART8LPEN     LL_C1_APB1_GRP1_DisableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_APB1_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C1->APB1LLPENR, Periphs);
+}
+
+/**
+  * @brief  Enable C1 APB1 peripherals clock.
+  * @rmtoll APB1HENR     CRSEN         LL_C1_APB1_GRP2_EnableClock\n
+  *         APB1HENR     SWPMIEN       LL_C1_APB1_GRP2_EnableClock\n
+  *         APB1HENR     OPAMPEN       LL_C1_APB1_GRP2_EnableClock\n
+  *         APB1HENR     MDIOSEN       LL_C1_APB1_GRP2_EnableClock\n
+  *         APB1HENR     FDCANEN       LL_C1_APB1_GRP2_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
+  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+  *         @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
+  *         @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_APB1_GRP2_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C1->APB1HENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C1->APB1HENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if C1 APB1 peripheral clock is enabled or not
+  * @rmtoll APB1HENR     CRSEN         LL_C1_APB1_GRP2_IsEnabledClock\n
+  *         APB1HENR     SWPMIEN       LL_C1_APB1_GRP2_IsEnabledClock\n
+  *         APB1HENR     OPAMPEN       LL_C1_APB1_GRP2_IsEnabledClock\n
+  *         APB1HENR     MDIOSEN       LL_C1_APB1_GRP2_IsEnabledClock\n
+  *         APB1HENR     FDCANEN       LL_C1_APB1_GRP2_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
+  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+  *         @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
+  *         @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_C1_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC_C1->APB1HENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable C1 APB1 peripherals clock.
+  * @rmtoll APB1HENR     CRSEN         LL_C1_APB1_GRP2_DisableClock\n
+  *         APB1HENR     SWPMIEN       LL_C1_APB1_GRP2_DisableClock\n
+  *         APB1HENR     OPAMPEN       LL_C1_APB1_GRP2_DisableClock\n
+  *         APB1HENR     MDIOSEN       LL_C1_APB1_GRP2_DisableClock\n
+  *         APB1HENR     FDCANEN       LL_C1_APB1_GRP2_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
+  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+  *         @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
+  *         @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_APB1_GRP2_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C1->APB1HENR, Periphs);
+}
+
+/**
+  * @brief  Enable C1 APB1 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB1HLPENR   CRSLPEN       LL_C1_APB1_GRP2_EnableClockSleep\n
+  *         APB1HLPENR   SWPMILPEN     LL_C1_APB1_GRP2_EnableClockSleep\n
+  *         APB1HLPENR   OPAMPLPEN     LL_C1_APB1_GRP2_EnableClockSleep\n
+  *         APB1HLPENR   MDIOSLPEN     LL_C1_APB1_GRP2_EnableClockSleep\n
+  *         APB1HLPENR   FDCANLPEN     LL_C1_APB1_GRP2_EnableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
+  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+  *         @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
+  *         @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_APB1_GRP2_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C1->APB1HLPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C1->APB1HLPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable C1 APB1 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB1HLPENR   CRSLPEN       LL_C1_APB1_GRP2_DisableClockSleep\n
+  *         APB1HLPENR   SWPMILPEN     LL_C1_APB1_GRP2_DisableClockSleep\n
+  *         APB1HLPENR   OPAMPLPEN     LL_C1_APB1_GRP2_DisableClockSleep\n
+  *         APB1HLPENR   MDIOSLPEN     LL_C1_APB1_GRP2_DisableClockSleep\n
+  *         APB1HLPENR   FDCANLPEN     LL_C1_APB1_GRP2_DisableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
+  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+  *         @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
+  *         @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_APB1_GRP2_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C1->APB1HLPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup BUS_LL_EF_APB2 APB2
+  * @{
+  */
+
+/**
+  * @brief  Enable C1 APB2 peripherals clock.
+  * @rmtoll APB2ENR      TIM1EN        LL_C1_APB2_GRP1_EnableClock\n
+  *         APB2ENR      TIM8EN        LL_C1_APB2_GRP1_EnableClock\n
+  *         APB2ENR      USART1EN      LL_C1_APB2_GRP1_EnableClock\n
+  *         APB2ENR      USART6EN      LL_C1_APB2_GRP1_EnableClock\n
+  *         APB2ENR      UART9EN       LL_C1_APB2_GRP1_EnableClock\n (*)
+  *         APB2ENR      USART10EN     LL_C1_APB2_GRP1_EnableClock\n (*)
+  *         APB2ENR      SPI1EN        LL_C1_APB2_GRP1_EnableClock\n
+  *         APB2ENR      SPI4EN        LL_C1_APB2_GRP1_EnableClock\n
+  *         APB2ENR      TIM15EN       LL_C1_APB2_GRP1_EnableClock\n
+  *         APB2ENR      TIM16EN       LL_C1_APB2_GRP1_EnableClock\n
+  *         APB2ENR      TIM17EN       LL_C1_APB2_GRP1_EnableClock\n
+  *         APB2ENR      SPI5EN        LL_C1_APB2_GRP1_EnableClock\n
+  *         APB2ENR      SAI1EN        LL_C1_APB2_GRP1_EnableClock\n
+  *         APB2ENR      SAI2EN        LL_C1_APB2_GRP1_EnableClock\n
+  *         APB2ENR      SAI3EN        LL_C1_APB2_GRP1_EnableClock\n (*)
+  *         APB2ENR      DFSDM1EN      LL_C1_APB2_GRP1_EnableClock\n
+  *         APB2ENR      HRTIMEN       LL_C1_APB2_GRP1_EnableClock   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9   (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2  (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_APB2_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C1->APB2ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C1->APB2ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if C1 APB2 peripheral clock is enabled or not
+  * @rmtoll APB2ENR      TIM1EN        LL_C1_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      TIM8EN        LL_C1_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      USART1EN      LL_C1_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      USART6EN      LL_C1_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      UART9EN       LL_C1_APB2_GRP1_IsEnabledClock\n (*)
+  *         APB2ENR      USART10EN     LL_C1_APB2_GRP1_IsEnabledClock\n (*)
+  *         APB2ENR      SPI1EN        LL_C1_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      SPI4EN        LL_C1_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      TIM15EN       LL_C1_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      TIM16EN       LL_C1_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      TIM17EN       LL_C1_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      SPI5EN        LL_C1_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      SAI1EN        LL_C1_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      SAI2EN        LL_C1_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      SAI3EN        LL_C1_APB2_GRP1_IsEnabledClock\n (*)
+  *         APB2ENR      DFSDM1EN      LL_C1_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      HRTIMEN       LL_C1_APB2_GRP1_IsEnabledClock   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9   (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2  (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE uint32_t LL_C1_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC_C1->APB2ENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable C1 APB2 peripherals clock.
+  * @rmtoll APB2ENR      TIM1EN        LL_C1_APB2_GRP1_DisableClock\n
+  *         APB2ENR      TIM8EN        LL_C1_APB2_GRP1_DisableClock\n
+  *         APB2ENR      USART1EN      LL_C1_APB2_GRP1_DisableClock\n
+  *         APB2ENR      USART6EN      LL_C1_APB2_GRP1_DisableClock\n
+  *         APB2ENR      UART9EN       LL_C1_APB2_GRP1_DisableClock\n (*)
+  *         APB2ENR      USART10EN     LL_C1_APB2_GRP1_DisableClock\n (*)
+  *         APB2ENR      SPI1EN        LL_C1_APB2_GRP1_DisableClock\n
+  *         APB2ENR      SPI4EN        LL_C1_APB2_GRP1_DisableClock\n
+  *         APB2ENR      TIM15EN       LL_C1_APB2_GRP1_DisableClock\n
+  *         APB2ENR      TIM16EN       LL_C1_APB2_GRP1_DisableClock\n
+  *         APB2ENR      TIM17EN       LL_C1_APB2_GRP1_DisableClock\n
+  *         APB2ENR      SPI5EN        LL_C1_APB2_GRP1_DisableClock\n
+  *         APB2ENR      SAI1EN        LL_C1_APB2_GRP1_DisableClock\n
+  *         APB2ENR      SAI2EN        LL_C1_APB2_GRP1_DisableClock\n
+  *         APB2ENR      SAI3EN        LL_C1_APB2_GRP1_DisableClock\n  (*)
+  *         APB2ENR      DFSDM1EN      LL_C1_APB2_GRP1_DisableClock\n
+  *         APB2ENR      HRTIMEN       LL_C1_APB2_GRP1_DisableClock    (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9   (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2  (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_APB2_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C1->APB2ENR, Periphs);
+}
+
+/**
+  * @brief  Enable C1 APB2 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB2LPENR    TIM1LPEN      LL_C1_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    TIM8LPEN      LL_C1_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    USART1LPEN    LL_C1_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    USART6LPEN    LL_C1_APB2_GRP1_EnableClockSleep\n
+  *         APB2ENR      UART9EN       LL_C1_APB2_GRP1_EnableClockSleep\n (*)
+  *         APB2ENR      USART10EN     LL_C1_APB2_GRP1_EnableClockSleep\n (*)
+  *         APB2LPENR    SPI1LPEN      LL_C1_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    SPI4LPEN      LL_C1_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    TIM15LPEN     LL_C1_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    TIM16LPEN     LL_C1_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    TIM17LPEN     LL_C1_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    SPI5LPEN      LL_C1_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    SAI1LPEN      LL_C1_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    SAI2LPEN      LL_C1_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    SAI3LPEN      LL_C1_APB2_GRP1_EnableClockSleep\n (*)
+  *         APB2LPENR    DFSDM1LPEN    LL_C1_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    HRTIMLPEN     LL_C1_APB2_GRP1_EnableClockSleep   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9   (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2  (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_APB2_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C1->APB2LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C1->APB2LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable C1 APB2 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB2LPENR    TIM1LPEN      LL_C1_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    TIM8LPEN      LL_C1_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    USART1LPEN    LL_C1_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    UART9LPEN     LL_C1_APB2_GRP1_DisableClockSleep\n (*)
+  *         APB2LPENR    USART10LPEN   LL_C1_APB2_GRP1_DisableClockSleep\n (*)
+  *         APB2LPENR    USART6LPEN    LL_C1_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    SPI1LPEN      LL_C1_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    SPI4LPEN      LL_C1_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    TIM15LPEN     LL_C1_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    TIM16LPEN     LL_C1_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    TIM17LPEN     LL_C1_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    SPI5LPEN      LL_C1_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    SAI1LPEN      LL_C1_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    SAI2LPEN      LL_C1_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    SAI3LPEN      LL_C1_APB2_GRP1_DisableClockSleep\n (*)
+  *         APB2LPENR    DFSDM1LPEN    LL_C1_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    HRTIMLPEN     LL_C1_APB2_GRP1_DisableClockSleep   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9   (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2  (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_APB2_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C1->APB2LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup BUS_LL_EF_APB4 APB4
+  * @{
+  */
+
+/**
+  * @brief  Enable C1 APB4 peripherals clock.
+  * @rmtoll APB4ENR      SYSCFGEN      LL_C1_APB4_GRP1_EnableClock\n
+  *         APB4ENR      LPUART1EN     LL_C1_APB4_GRP1_EnableClock\n
+  *         APB4ENR      SPI6EN        LL_C1_APB4_GRP1_EnableClock\n
+  *         APB4ENR      I2C4EN        LL_C1_APB4_GRP1_EnableClock\n
+  *         APB4ENR      LPTIM2EN      LL_C1_APB4_GRP1_EnableClock\n
+  *         APB4ENR      LPTIM3EN      LL_C1_APB4_GRP1_EnableClock\n
+  *         APB4ENR      LPTIM4EN      LL_C1_APB4_GRP1_EnableClock\n (*)
+  *         APB4ENR      LPTIM5EN      LL_C1_APB4_GRP1_EnableClock\n (*)
+  *         APB4ENR      DAC2EN        LL_C1_APB4_GRP1_EnableClock\n (*)
+  *         APB4ENR      COMP12EN      LL_C1_APB4_GRP1_EnableClock\n
+  *         APB4ENR      VREFEN        LL_C1_APB4_GRP1_EnableClock\n
+  *         APB4ENR      RTCAPBEN      LL_C1_APB4_GRP1_EnableClock\n
+  *         APB4ENR      SAI4EN        LL_C1_APB4_GRP1_EnableClock\n (*)
+  *         APB4ENR      DTSEN         LL_C1_APB4_GRP1_EnableClock\n (*)
+  *         APB4ENR      DFSDM2EN      LL_C1_APB4_GRP1_EnableClock   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
+  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DTS    (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_APB4_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C1->APB4ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C1->APB4ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if C1 APB4 peripheral clock is enabled or not
+  * @rmtoll APB4ENR      SYSCFGEN      LL_C1_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      LPUART1EN     LL_C1_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      SPI6EN        LL_C1_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      I2C4EN        LL_C1_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      LPTIM2EN      LL_C1_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      LPTIM3EN      LL_C1_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      LPTIM4EN      LL_C1_APB4_GRP1_IsEnabledClock\n (*)
+  *         APB4ENR      LPTIM5EN      LL_C1_APB4_GRP1_IsEnabledClock\n (*)
+  *         APB4ENR      COMP12EN      LL_C1_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      VREFEN        LL_C1_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      RTCAPBEN      LL_C1_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      SAI4EN        LL_C1_APB4_GRP1_IsEnabledClock\n (*)
+  *         APB4ENR      DTSEN         LL_C1_APB4_GRP1_IsEnabledClock\n (*)
+  *         APB4ENR      DFSDM2EN      LL_C1_APB4_GRP1_IsEnabledClock   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DTS    (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_C1_APB4_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC_C1->APB4ENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable C1 APB4 peripherals clock.
+  * @rmtoll APB4ENR      SYSCFGEN      LL_C1_APB4_GRP1_DisableClock\n
+  *         APB4ENR      LPUART1EN     LL_C1_APB4_GRP1_DisableClock\n
+  *         APB4ENR      SPI6EN        LL_C1_APB4_GRP1_DisableClock\n
+  *         APB4ENR      I2C4EN        LL_C1_APB4_GRP1_DisableClock\n
+  *         APB4ENR      LPTIM2EN      LL_C1_APB4_GRP1_DisableClock\n
+  *         APB4ENR      LPTIM3EN      LL_C1_APB4_GRP1_DisableClock\n
+  *         APB4ENR      LPTIM4EN      LL_C1_APB4_GRP1_DisableClock\n (*)
+  *         APB4ENR      LPTIM5EN      LL_C1_APB4_GRP1_DisableClock\n (*)
+  *         APB4ENR      COMP12EN      LL_C1_APB4_GRP1_DisableClock\n
+  *         APB4ENR      VREFEN        LL_C1_APB4_GRP1_DisableClock\n
+  *         APB4ENR      RTCAPBEN      LL_C1_APB4_GRP1_DisableClock\n
+  *         APB4ENR      SAI4EN        LL_C1_APB4_GRP1_DisableClock\n (*)
+  *         APB4ENR      DTSEN         LL_C1_APB4_GRP1_DisableClock\n (*)
+  *         APB4ENR      DFSDM2EN      LL_C1_APB4_GRP1_DisableClock   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
+  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DTS    (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_APB4_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C1->APB4ENR, Periphs);
+}
+
+/**
+  * @brief  Enable C1 APB4 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB4LPENR    SYSCFGLPEN    LL_C1_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    LPUART1LPEN   LL_C1_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    SPI6LPEN      LL_C1_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    I2C4LPEN      LL_C1_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    LPTIM2LPEN    LL_C1_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    LPTIM3LPEN    LL_C1_APB4_GRP1_EnableClockSleep\n (*)
+  *         APB4LPENR    LPTIM4LPEN    LL_C1_APB4_GRP1_EnableClockSleep\n (*)
+  *         APB4LPENR    LPTIM5LPEN    LL_C1_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    COMP12LPEN    LL_C1_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    VREFLPEN      LL_C1_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    RTCAPBLPEN    LL_C1_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    SAI4LPEN      LL_C1_APB4_GRP1_EnableClockSleep\n (*)
+  *         APB4ENR      DTSLPEN       LL_C1_APB4_GRP1_EnableClockSleep\n (*)
+  *         APB4ENR      DFSDM2LPEN    LL_C1_APB4_GRP1_EnableClockSleep   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
+  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DTS    (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_APB4_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C1->APB4LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C1->APB4LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable C1 APB4 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB4LPENR    SYSCFGLPEN    LL_C1_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    LPUART1LPEN   LL_C1_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    SPI6LPEN      LL_C1_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    I2C4LPEN      LL_C1_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    LPTIM2LPEN    LL_C1_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    LPTIM3LPEN    LL_C1_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    LPTIM4LPEN    LL_C1_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    LPTIM5LPEN    LL_C1_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    COMP12LPEN    LL_C1_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    VREFLPEN      LL_C1_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    RTCAPBLPEN    LL_C1_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    SAI4LPEN      LL_C1_APB4_GRP1_DisableClockSleep\n (*)
+  *         APB4ENR      DTSLPEN       LL_C1_APB4_GRP1_DisableClockSleep\n (*)
+  *         APB4ENR      DFSDM2LPEN    LL_C1_APB4_GRP1_DisableClockSleep   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
+  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DTS    (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_APB4_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C1->APB4LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup BUS_LL_EF_AHB3 AHB3
+  * @{
+  */
+
+/**
+  * @brief  Enable C2 AHB3 peripherals clock.
+  * @rmtoll AHB3ENR      MDMAEN        LL_C2_AHB3_GRP1_EnableClock\n
+  *         AHB3ENR      DMA2DEN       LL_C2_AHB3_GRP1_EnableClock\n
+  *         AHB3ENR      JPGDECEN      LL_C2_AHB3_GRP1_EnableClock\n
+  *         AHB3ENR      FMCEN         LL_C2_AHB3_GRP1_EnableClock\n
+  *         AHB3ENR      QSPIEN        LL_C2_AHB3_GRP1_EnableClock\n
+  *         AHB3ENR      SDMMC1EN      LL_C2_AHB3_GRP1_EnableClock\n
+  *         AHB3ENR      FLASHEN       LL_C2_AHB3_GRP1_EnableClock\n
+  *         AHB3ENR      DTCM1EN       LL_C2_AHB3_GRP1_EnableClock\n
+  *         AHB3ENR      DTCM2EN       LL_C2_AHB3_GRP1_EnableClock\n
+  *         AHB3ENR      ITCMEN        LL_C2_AHB3_GRP1_EnableClock\n
+  *         AHB3ENR      AXISRAMEN     LL_C2_AHB3_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC  (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_AHB3_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C2->AHB3ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C2->AHB3ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if C2 AHB3 peripheral clock is enabled or not
+  * @rmtoll AHB3ENR      MDMAEN        LL_C2_AHB3_GRP1_IsEnabledClock\n
+  *         AHB3ENR      DMA2DEN       LL_C2_AHB3_GRP1_IsEnabledClock\n
+  *         AHB3ENR      JPGDECEN      LL_C2_AHB3_GRP1_IsEnabledClock\n
+  *         AHB3ENR      FMCEN         LL_C2_AHB3_GRP1_IsEnabledClock\n
+  *         AHB3ENR      QSPIEN        LL_C2_AHB3_GRP1_IsEnabledClock\n
+  *         AHB3ENR      SDMMC1EN      LL_C2_AHB3_GRP1_IsEnabledClock\n
+  *         AHB3ENR      FLASHEN       LL_C2_AHB3_GRP1_IsEnabledClock\n
+  *         AHB3ENR      DTCM1EN       LL_C2_AHB3_GRP1_IsEnabledClock\n
+  *         AHB3ENR      DTCM2EN       LL_C2_AHB3_GRP1_IsEnabledClock\n
+  *         AHB3ENR      ITCMEN        LL_C2_AHB3_GRP1_IsEnabledClock\n
+  *         AHB3ENR      AXISRAMEN     LL_C2_AHB3_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC  (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI    (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_C2_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC_C2->AHB3ENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable C2 AHB3 peripherals clock.
+  * @rmtoll AHB3ENR      MDMAEN        LL_C2_AHB3_GRP1_DisableClock\n
+  *         AHB3ENR      DMA2DEN       LL_C2_AHB3_GRP1_DisableClock\n
+  *         AHB3ENR      JPGDECEN      LL_C2_AHB3_GRP1_DisableClock\n
+  *         AHB3ENR      FMCEN         LL_C2_AHB3_GRP1_DisableClock\n
+  *         AHB3ENR      QSPIEN        LL_C2_AHB3_GRP1_DisableClock\n
+  *         AHB3ENR      SDMMC1EN      LL_C2_AHB3_GRP1_DisableClock\n
+  *         AHB3ENR      FLASHEN       LL_C2_AHB3_GRP1_DisableClock\n
+  *         AHB3ENR      DTCM1EN       LL_C2_AHB3_GRP1_DisableClock\n
+  *         AHB3ENR      DTCM2EN       LL_C2_AHB3_GRP1_DisableClock\n
+  *         AHB3ENR      ITCMEN        LL_C2_AHB3_GRP1_DisableClock\n
+  *         AHB3ENR      AXISRAMEN     LL_C2_AHB3_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_AHB3_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C2->AHB3ENR, Periphs);
+}
+
+/**
+  * @brief  Enable C2 AHB3 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll AHB3LPENR    MDMALPEN      LL_C2_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    DMA2DLPEN     LL_C2_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    JPGDECLPEN    LL_C2_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    FMCLPEN       LL_C2_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    QSPILPEN      LL_C2_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    SDMMC1LPEN    LL_C2_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    FLASHLPEN     LL_C2_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    DTCM1LPEN     LL_C2_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    DTCM2LPEN     LL_C2_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    ITCMLPEN      LL_C2_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    AXISRAMLPEN   LL_C2_AHB3_GRP1_EnableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC  (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_AHB3_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C2->AHB3LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C2->AHB3LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable C2 AHB3 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll AHB3LPENR    MDMALPEN      LL_C2_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    DMA2DLPEN     LL_C2_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    JPGDECLPEN    LL_C2_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    FMCLPEN       LL_C2_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    QSPILPEN      LL_C2_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    SDMMC1LPEN    LL_C2_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    FLASHLPEN     LL_C2_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    DTCM1LPEN     LL_C2_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    DTCM2LPEN     LL_C2_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    ITCMLPEN      LL_C2_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    AXISRAMLPEN   LL_C2_AHB3_GRP1_DisableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC  (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_AHB3_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C2->AHB3LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup BUS_LL_EF_AHB1 AHB1
+  * @{
+  */
+
+/**
+  * @brief  Enable C2 AHB1 peripherals clock.
+  * @rmtoll AHB1ENR      DMA1EN        LL_C2_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      DMA2EN        LL_C2_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      ADC12EN       LL_C2_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      ARTEN         LL_C2_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      ETH1MACEN     LL_C2_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      ETH1TXEN      LL_C2_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      ETH1RXEN      LL_C2_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      USB1OTGHSEN   LL_C2_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      USB1OTGHSULPIEN  LL_C2_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      USB2OTGHSEN   LL_C2_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      USB2OTGHSULPIEN  LL_C2_AHB1_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX  (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX  (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS  (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
+  *
+  *         (*) value not defined in all devices.  
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_AHB1_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C2->AHB1ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C2->AHB1ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if C2 AHB1 peripheral clock is enabled or not
+  * @rmtoll AHB1ENR      DMA1EN        LL_C2_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      DMA2EN        LL_C2_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      ADC12EN       LL_C2_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      ARTEN         LL_C2_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      ETH1MACEN     LL_C2_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      ETH1TXEN      LL_C2_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      ETH1RXEN      LL_C2_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      USB1OTGHSEN   LL_C2_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      USB1OTGHSULPIEN  LL_C2_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      USB2OTGHSEN   LL_C2_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      USB2OTGHSULPIEN  LL_C2_AHB1_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX  (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX  (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS     (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
+  *
+  *         (*) value not defined in all devices.  
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_C2_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC_C2->AHB1ENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable C2 AHB1 peripherals clock.
+  * @rmtoll AHB1ENR      DMA1EN        LL_C2_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      DMA2EN        LL_C2_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      ADC12EN       LL_C2_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      ARTEN         LL_C2_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      ETH1MACEN     LL_C2_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      ETH1TXEN      LL_C2_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      ETH1RXEN      LL_C2_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      USB1OTGHSEN   LL_C2_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      USB1OTGHSULPIEN  LL_C2_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      USB2OTGHSEN   LL_C2_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      USB2OTGHSULPIEN  LL_C2_AHB1_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC  (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX   (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX   (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS      (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI  (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_AHB1_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C2->AHB1ENR, Periphs);
+}
+
+/**
+  * @brief  Enable C2 AHB1 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll AHB1LPENR    DMA1LPEN      LL_C2_AHB1_GRP1_EnableClockSleep\n
+  *         AHB1LPENR    DMA2LPEN      LL_C2_AHB1_GRP1_EnableClockSleep\n
+  *         AHB1LPENR    ADC12LPEN     LL_C2_AHB1_GRP1_EnableClockSleep\n
+  *         AHB1LPENR    ARTLPEN       LL_C2_AHB1_GRP1_EnableClockSleep\n
+  *         AHB1LPENR    ETH1MACLPEN   LL_C2_AHB1_GRP1_EnableClockSleep\n
+  *         AHB1LPENR    ETH1TXLPEN    LL_C2_AHB1_GRP1_EnableClockSleep\n
+  *         AHB1LPENR    ETH1RXLPEN    LL_C2_AHB1_GRP1_EnableClockSleep\n
+  *         AHB1LPENR    USB1OTGHSLPEN  LL_C2_AHB1_GRP1_EnableClockSleep\n
+  *         AHB1LPENR    USB1OTGHSULPILPEN  LL_C2_AHB1_GRP1_EnableClockSleep\n
+  *         AHB1LPENR    USB2OTGHSLPEN  LL_C2_AHB1_GRP1_EnableClockSleep\n
+  *         AHB1LPENR    USB2OTGHSULPILPEN  LL_C2_AHB1_GRP1_EnableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC  (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX   (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX   (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS      (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI  (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_AHB1_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C2->AHB1LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C2->AHB1LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable C2 AHB1 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll AHB1LPENR    DMA1LPEN      LL_C2_AHB1_GRP1_DisableClockSleep\n
+  *         AHB1LPENR    DMA2LPEN      LL_C2_AHB1_GRP1_DisableClockSleep\n
+  *         AHB1LPENR    ADC12LPEN     LL_C2_AHB1_GRP1_DisableClockSleep\n
+  *         AHB1LPENR    ARTLPEN       LL_C2_AHB1_GRP1_DisableClockSleep\n
+  *         AHB1LPENR    ETH1MACLPEN   LL_C2_AHB1_GRP1_DisableClockSleep\n
+  *         AHB1LPENR    ETH1TXLPEN    LL_C2_AHB1_GRP1_DisableClockSleep\n
+  *         AHB1LPENR    ETH1RXLPEN    LL_C2_AHB1_GRP1_DisableClockSleep\n
+  *         AHB1LPENR    USB1OTGHSLPEN  LL_C2_AHB1_GRP1_DisableClockSleep\n
+  *         AHB1LPENR    USB1OTGHSULPILPEN  LL_C2_AHB1_GRP1_DisableClockSleep\n
+  *         AHB1LPENR    USB2OTGHSLPEN  LL_C2_AHB1_GRP1_DisableClockSleep\n
+  *         AHB1LPENR    USB2OTGHSULPILPEN  LL_C2_AHB1_GRP1_DisableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC  (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX   (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX   (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS      (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI  (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_AHB1_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C2->AHB1LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup BUS_LL_EF_AHB2 AHB2
+  * @{
+  */
+
+/**
+  * @brief  Enable C2 AHB2 peripherals clock.
+  * @rmtoll AHB2ENR      DCMIEN        LL_C2_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      CRYPEN        LL_C2_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      HASHEN        LL_C2_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      RNGEN         LL_C2_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      SDMMC2EN      LL_C2_AHB2_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_AHB2_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C2->AHB2ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C2->AHB2ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if C2 AHB2 peripheral clock is enabled or not
+  * @rmtoll AHB2ENR      DCMIEN        LL_C2_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      CRYPEN        LL_C2_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      HASHEN        LL_C2_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      RNGEN         LL_C2_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      SDMMC2EN      LL_C2_AHB2_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
+  *
+  *         (*) value not defined in all devices.
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_C2_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC_C2->AHB2ENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable C2 AHB2 peripherals clock.
+  * @rmtoll AHB2ENR      DCMIEN        LL_C2_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      CRYPEN        LL_C2_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      HASHEN        LL_C2_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      RNGEN         LL_C2_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      SDMMC2EN      LL_C2_AHB2_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_AHB2_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C2->AHB2ENR, Periphs);
+}
+
+/**
+  * @brief  Enable C2 AHB2 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll AHB2LPENR    DCMILPEN      LL_C2_AHB2_GRP1_EnableClockSleep\n
+  *         AHB2LPENR    CRYPLPEN      LL_C2_AHB2_GRP1_EnableClockSleep\n
+  *         AHB2LPENR    HASHLPEN      LL_C2_AHB2_GRP1_EnableClockSleep\n
+  *         AHB2LPENR    RNGLPEN       LL_C2_AHB2_GRP1_EnableClockSleep\n
+  *         AHB2LPENR    SDMMC2LPEN    LL_C2_AHB2_GRP1_EnableClockSleep\n
+  *         AHB2LPENR    D2SRAM1LPEN   LL_C2_AHB2_GRP1_EnableClockSleep\n
+  *         AHB2LPENR    D2SRAM2LPEN   LL_C2_AHB2_GRP1_EnableClockSleep\n
+  *         AHB2LPENR    D2SRAM3LPEN   LL_C2_AHB2_GRP1_EnableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_AHB2_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C2->AHB2LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C2->AHB2LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable C2 AHB2 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll AHB2LPENR    DCMILPEN      LL_C2_AHB2_GRP1_DisableClockSleep\n
+  *         AHB2LPENR    CRYPLPEN      LL_C2_AHB2_GRP1_DisableClockSleep\n
+  *         AHB2LPENR    HASHLPEN      LL_C2_AHB2_GRP1_DisableClockSleep\n
+  *         AHB2LPENR    RNGLPEN       LL_C2_AHB2_GRP1_DisableClockSleep\n
+  *         AHB2LPENR    SDMMC2LPEN    LL_C2_AHB2_GRP1_DisableClockSleep\n
+  *         AHB2LPENR    D2SRAM1LPEN   LL_C2_AHB2_GRP1_DisableClockSleep\n
+  *         AHB2LPENR    D2SRAM2LPEN   LL_C2_AHB2_GRP1_DisableClockSleep\n
+  *         AHB2LPENR    D2SRAM3LPEN   LL_C2_AHB2_GRP1_DisableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_AHB2_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C2->AHB2LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup BUS_LL_EF_AHB4 AHB4
+  * @{
+  */
+
+/**
+  * @brief  Enable C2 AHB4 peripherals clock.
+  * @rmtoll AHB4ENR      GPIOAEN       LL_C2_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOBEN       LL_C2_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOCEN       LL_C2_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIODEN       LL_C2_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOEEN       LL_C2_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOFEN       LL_C2_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOGEN       LL_C2_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOHEN       LL_C2_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOIEN       LL_C2_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOJEN       LL_C2_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOKEN       LL_C2_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      CRCEN         LL_C2_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      BDMAEN        LL_C2_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      ADC3EN        LL_C2_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      HSEMEN        LL_C2_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      BKPRAMEN      LL_C2_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      SRAM4EN     LL_C2_AHB4_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI  (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC   (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM  (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_AHB4_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C2->AHB4ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C2->AHB4ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if C2 AHB4 peripheral clock is enabled or not
+  * @rmtoll AHB4ENR      GPIOAEN       LL_C2_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOBEN       LL_C2_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOCEN       LL_C2_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIODEN       LL_C2_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOEEN       LL_C2_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOFEN       LL_C2_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOGEN       LL_C2_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOHEN       LL_C2_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOIEN       LL_C2_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOJEN       LL_C2_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOKEN       LL_C2_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      CRCEN         LL_C2_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      BDMAEN        LL_C2_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      ADC3EN        LL_C2_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      HSEMEN        LL_C2_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      BKPRAMEN      LL_C2_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      SRAM4EN       LL_C2_AHB4_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI  (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC   (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM  (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
+  *
+  *         (*) value not defined in all devices.
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_C2_AHB4_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC_C2->AHB4ENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable C2 AHB4 peripherals clock.
+  * @rmtoll AHB4ENR      GPIOAEN       LL_C2_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOBEN       LL_C2_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOCEN       LL_C2_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIODEN       LL_C2_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOEEN       LL_C2_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOFEN       LL_C2_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOGEN       LL_C2_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOHEN       LL_C2_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOIEN       LL_C2_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOJEN       LL_C2_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOKEN       LL_C2_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      CRCEN         LL_C2_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      BDMAEN        LL_C2_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      ADC3EN        LL_C2_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      HSEMEN        LL_C2_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      BKPRAMEN      LL_C2_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      SRAM4EN       LL_C2_AHB4_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI  (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC   (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM  (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_AHB4_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C2->AHB4ENR, Periphs);
+}
+
+/**
+  * @brief  Enable C2 AHB4 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll AHB4LPENR    GPIOALPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOBLPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOCLPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIODLPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOELPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOFLPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOGLPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOHLPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOILPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOJLPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOKLPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    CRCLPEN       LL_C2_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    BDMALPEN      LL_C2_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    ADC3LPEN      LL_C2_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    BKPRAMLPEN    LL_C2_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    SRAM4LPEN     LL_C2_AHB4_GRP1_EnableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI  (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC   (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_AHB4_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C2->AHB4LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C2->AHB4LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable C2 AHB4 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll AHB4LPENR    GPIOALPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOBLPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOCLPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIODLPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOELPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOFLPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOGLPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOHLPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOILPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOJLPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOKLPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    CRCLPEN       LL_C2_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    BDMALPEN      LL_C2_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    ADC3LPEN      LL_C2_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    BKPRAMLPEN    LL_C2_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    SRAM4LPEN     LL_C2_AHB4_GRP1_DisableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI  (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC   (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_AHB4_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C2->AHB4LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup BUS_LL_EF_APB3 APB3
+  * @{
+  */
+
+/**
+  * @brief  Enable C2 APB3 peripherals clock.
+  * @rmtoll APB3ENR      LTDCEN        LL_C2_APB3_GRP1_EnableClock\n
+  *         APB3ENR      DSIEN         LL_C2_APB3_GRP1_EnableClock\n
+  *         APB3ENR      WWDG1EN       LL_C2_APB3_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_APB3_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C2->APB3ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C2->APB3ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if C2 APB3 peripheral clock is enabled or not
+  * @rmtoll APB3ENR      LTDCEN        LL_C2_APB3_GRP1_IsEnabledClock\n
+  *         APB3ENR      DSIEN         LL_C2_APB3_GRP1_IsEnabledClock\n
+  *         APB3ENR      WWDG1EN       LL_C2_APB3_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
+  *
+  *         (*) value not defined in all devices.
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_C2_APB3_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC_C2->APB3ENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable C2 APB3 peripherals clock.
+  * @rmtoll APB3ENR      LTDCEN        LL_C2_APB3_GRP1_DisableClock\n
+  *         APB3ENR      DSIEN         LL_C2_APB3_GRP1_DisableClock\n
+  *         APB3ENR      WWDG1EN       LL_C2_APB3_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_APB3_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C2->APB3ENR, Periphs);
+}
+
+/**
+  * @brief  Enable C2 APB3 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB3LPENR    LTDCLPEN      LL_C2_APB3_GRP1_EnableClockSleep\n
+  *         APB3LPENR    DSILPEN       LL_C2_APB3_GRP1_EnableClockSleep\n
+  *         APB3LPENR    WWDG1LPEN     LL_C2_APB3_GRP1_EnableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_APB3_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C2->APB3LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C2->APB3LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable C2 APB3 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB3LPENR    LTDCLPEN      LL_C2_APB3_GRP1_DisableClockSleep\n
+  *         APB3LPENR    DSILPEN       LL_C2_APB3_GRP1_DisableClockSleep\n
+  *         APB3LPENR    WWDG1LPEN     LL_C2_APB3_GRP1_DisableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_APB3_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C2->APB3LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup BUS_LL_EF_APB1 APB1
+  * @{
+  */
+
+/**
+  * @brief  Enable C2 APB1 peripherals clock.
+  * @rmtoll APB1LENR     TIM2EN        LL_C2_APB1_GRP1_EnableClock\n
+  *         APB1LENR     TIM3EN        LL_C2_APB1_GRP1_EnableClock\n
+  *         APB1LENR     TIM4EN        LL_C2_APB1_GRP1_EnableClock\n
+  *         APB1LENR     TIM5EN        LL_C2_APB1_GRP1_EnableClock\n
+  *         APB1LENR     TIM6EN        LL_C2_APB1_GRP1_EnableClock\n
+  *         APB1LENR     TIM7EN        LL_C2_APB1_GRP1_EnableClock\n
+  *         APB1LENR     TIM12EN       LL_C2_APB1_GRP1_EnableClock\n
+  *         APB1LENR     TIM13EN       LL_C2_APB1_GRP1_EnableClock\n
+  *         APB1LENR     TIM14EN       LL_C2_APB1_GRP1_EnableClock\n
+  *         APB1LENR     LPTIM1EN      LL_C2_APB1_GRP1_EnableClock\n
+  *         APB1LENR     WWDG2EN       LL_C2_APB1_GRP1_EnableClock\n
+  *         APB1LENR     SPI2EN        LL_C2_APB1_GRP1_EnableClock\n
+  *         APB1LENR     SPI3EN        LL_C2_APB1_GRP1_EnableClock\n
+  *         APB1LENR     SPDIFRXEN     LL_C2_APB1_GRP1_EnableClock\n
+  *         APB1LENR     USART2EN      LL_C2_APB1_GRP1_EnableClock\n
+  *         APB1LENR     USART3EN      LL_C2_APB1_GRP1_EnableClock\n
+  *         APB1LENR     UART4EN       LL_C2_APB1_GRP1_EnableClock\n
+  *         APB1LENR     UART5EN       LL_C2_APB1_GRP1_EnableClock\n
+  *         APB1LENR     I2C1EN        LL_C2_APB1_GRP1_EnableClock\n
+  *         APB1LENR     I2C2EN        LL_C2_APB1_GRP1_EnableClock\n
+  *         APB1LENR     I2C3EN        LL_C2_APB1_GRP1_EnableClock\n
+  *         APB1LENR     CECEN         LL_C2_APB1_GRP1_EnableClock\n
+  *         APB1LENR     DAC12EN       LL_C2_APB1_GRP1_EnableClock\n
+  *         APB1LENR     UART7EN       LL_C2_APB1_GRP1_EnableClock\n
+  *         APB1LENR     UART8EN       LL_C2_APB1_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_APB1_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C2->APB1LENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C2->APB1LENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if C2 APB1 peripheral clock is enabled or not
+  * @rmtoll APB1LENR     TIM2EN        LL_C2_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     TIM3EN        LL_C2_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     TIM4EN        LL_C2_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     TIM5EN        LL_C2_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     TIM6EN        LL_C2_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     TIM7EN        LL_C2_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     TIM12EN       LL_C2_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     TIM13EN       LL_C2_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     TIM14EN       LL_C2_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     LPTIM1EN      LL_C2_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     WWDG2EN       LL_C2_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     SPI2EN        LL_C2_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     SPI3EN        LL_C2_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     SPDIFRXEN     LL_C2_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     USART2EN      LL_C2_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     USART3EN      LL_C2_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     UART4EN       LL_C2_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     UART5EN       LL_C2_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     I2C1EN        LL_C2_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     I2C2EN        LL_C2_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     I2C3EN        LL_C2_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     CECEN         LL_C2_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     DAC12EN       LL_C2_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     UART7EN       LL_C2_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     UART8EN       LL_C2_APB1_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+  *
+  *         (*) value not defined in all devices.
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_C2_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC_C2->APB1LENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable C2 APB1 peripherals clock.
+  * @rmtoll APB1LENR     TIM2EN        LL_C2_APB1_GRP1_DisableClock\n
+  *         APB1LENR     TIM3EN        LL_C2_APB1_GRP1_DisableClock\n
+  *         APB1LENR     TIM4EN        LL_C2_APB1_GRP1_DisableClock\n
+  *         APB1LENR     TIM5EN        LL_C2_APB1_GRP1_DisableClock\n
+  *         APB1LENR     TIM6EN        LL_C2_APB1_GRP1_DisableClock\n
+  *         APB1LENR     TIM7EN        LL_C2_APB1_GRP1_DisableClock\n
+  *         APB1LENR     TIM12EN       LL_C2_APB1_GRP1_DisableClock\n
+  *         APB1LENR     TIM13EN       LL_C2_APB1_GRP1_DisableClock\n
+  *         APB1LENR     TIM14EN       LL_C2_APB1_GRP1_DisableClock\n
+  *         APB1LENR     LPTIM1EN      LL_C2_APB1_GRP1_DisableClock\n
+  *         APB1LENR     WWDG2EN       LL_C2_APB1_GRP1_DisableClock\n
+  *         APB1LENR     SPI2EN        LL_C2_APB1_GRP1_DisableClock\n
+  *         APB1LENR     SPI3EN        LL_C2_APB1_GRP1_DisableClock\n
+  *         APB1LENR     SPDIFRXEN     LL_C2_APB1_GRP1_DisableClock\n
+  *         APB1LENR     USART2EN      LL_C2_APB1_GRP1_DisableClock\n
+  *         APB1LENR     USART3EN      LL_C2_APB1_GRP1_DisableClock\n
+  *         APB1LENR     UART4EN       LL_C2_APB1_GRP1_DisableClock\n
+  *         APB1LENR     UART5EN       LL_C2_APB1_GRP1_DisableClock\n
+  *         APB1LENR     I2C1EN        LL_C2_APB1_GRP1_DisableClock\n
+  *         APB1LENR     I2C2EN        LL_C2_APB1_GRP1_DisableClock\n
+  *         APB1LENR     I2C3EN        LL_C2_APB1_GRP1_DisableClock\n
+  *         APB1LENR     CECEN         LL_C2_APB1_GRP1_DisableClock\n
+  *         APB1LENR     DAC12EN       LL_C2_APB1_GRP1_DisableClock\n
+  *         APB1LENR     UART7EN       LL_C2_APB1_GRP1_DisableClock\n
+  *         APB1LENR     UART8EN       LL_C2_APB1_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_APB1_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C2->APB1LENR, Periphs);
+}
+
+/**
+  * @brief  Enable C2 APB1 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB1LLPENR   TIM2LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   TIM3LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   TIM4LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   TIM5LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   TIM6LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   TIM7LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   TIM12LPEN     LL_C2_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   TIM13LPEN     LL_C2_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   TIM14LPEN     LL_C2_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   LPTIM1LPEN    LL_C2_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   WWDG2LPEN     LL_C2_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   SPI2LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   SPI3LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   SPDIFRXLPEN   LL_C2_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   USART2LPEN    LL_C2_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   USART3LPEN    LL_C2_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   UART4LPEN     LL_C2_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   UART5LPEN     LL_C2_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   I2C1LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   I2C2LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   I2C3LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   CECLPEN       LL_C2_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   DAC12LPEN     LL_C2_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   UART7LPEN     LL_C2_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   UART8LPEN     LL_C2_APB1_GRP1_EnableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_APB1_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C2->APB1LLPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C2->APB1LLPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable C2 APB1 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB1LLPENR   TIM2LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   TIM3LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   TIM4LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   TIM5LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   TIM6LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   TIM7LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   TIM12LPEN     LL_C2_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   TIM13LPEN     LL_C2_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   TIM14LPEN     LL_C2_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   LPTIM1LPEN    LL_C2_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   WWDG2LPEN     LL_C2_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   SPI2LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   SPI3LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   SPDIFRXLPEN   LL_C2_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   USART2LPEN    LL_C2_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   USART3LPEN    LL_C2_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   UART4LPEN     LL_C2_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   UART5LPEN     LL_C2_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   I2C1LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   I2C2LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   I2C3LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   CECLPEN       LL_C2_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   DAC12LPEN     LL_C2_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   UART7LPEN     LL_C2_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   UART8LPEN     LL_C2_APB1_GRP1_DisableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_APB1_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C2->APB1LLPENR, Periphs);
+}
+
+/**
+  * @brief  Enable C2 APB1 peripherals clock.
+  * @rmtoll APB1HENR     CRSEN         LL_C2_APB1_GRP2_EnableClock\n
+  *         APB1HENR     SWPMIEN       LL_C2_APB1_GRP2_EnableClock\n
+  *         APB1HENR     OPAMPEN       LL_C2_APB1_GRP2_EnableClock\n
+  *         APB1HENR     MDIOSEN       LL_C2_APB1_GRP2_EnableClock\n
+  *         APB1HENR     FDCANEN       LL_C2_APB1_GRP2_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
+  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+  *         @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
+  *         @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_APB1_GRP2_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C2->APB1HENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C2->APB1HENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if C2 APB1 peripheral clock is enabled or not
+  * @rmtoll APB1HENR     CRSEN         LL_C2_APB1_GRP2_IsEnabledClock\n
+  *         APB1HENR     SWPMIEN       LL_C2_APB1_GRP2_IsEnabledClock\n
+  *         APB1HENR     OPAMPEN       LL_C2_APB1_GRP2_IsEnabledClock\n
+  *         APB1HENR     MDIOSEN       LL_C2_APB1_GRP2_IsEnabledClock\n
+  *         APB1HENR     FDCANEN       LL_C2_APB1_GRP2_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
+  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+  *         @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
+  *         @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_C2_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC_C2->APB1HENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable C2 APB1 peripherals clock.
+  * @rmtoll APB1HENR     CRSEN         LL_C2_APB1_GRP2_DisableClock\n
+  *         APB1HENR     SWPMIEN       LL_C2_APB1_GRP2_DisableClock\n
+  *         APB1HENR     OPAMPEN       LL_C2_APB1_GRP2_DisableClock\n
+  *         APB1HENR     MDIOSEN       LL_C2_APB1_GRP2_DisableClock\n
+  *         APB1HENR     FDCANEN       LL_C2_APB1_GRP2_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
+  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+  *         @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
+  *         @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_APB1_GRP2_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C2->APB1HENR, Periphs);
+}
+
+/**
+  * @brief  Enable C2 APB1 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB1HLPENR   CRSLPEN       LL_C2_APB1_GRP2_EnableClockSleep\n
+  *         APB1HLPENR   SWPMILPEN     LL_C2_APB1_GRP2_EnableClockSleep\n
+  *         APB1HLPENR   OPAMPLPEN     LL_C2_APB1_GRP2_EnableClockSleep\n
+  *         APB1HLPENR   MDIOSLPEN     LL_C2_APB1_GRP2_EnableClockSleep\n
+  *         APB1HLPENR   FDCANLPEN     LL_C2_APB1_GRP2_EnableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
+  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+  *         @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
+  *         @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_APB1_GRP2_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C2->APB1HLPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C2->APB1HLPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable C2 APB1 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB1HLPENR   CRSLPEN       LL_C2_APB1_GRP2_DisableClockSleep\n
+  *         APB1HLPENR   SWPMILPEN     LL_C2_APB1_GRP2_DisableClockSleep\n
+  *         APB1HLPENR   OPAMPLPEN     LL_C2_APB1_GRP2_DisableClockSleep\n
+  *         APB1HLPENR   MDIOSLPEN     LL_C2_APB1_GRP2_DisableClockSleep\n
+  *         APB1HLPENR   FDCANLPEN     LL_C2_APB1_GRP2_DisableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
+  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+  *         @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
+  *         @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_APB1_GRP2_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C2->APB1HLPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup BUS_LL_EF_APB2 APB2
+  * @{
+  */
+
+/**
+  * @brief  Enable C2 APB2 peripherals clock.
+  * @rmtoll APB2ENR      TIM1EN        LL_C2_APB2_GRP1_EnableClock\n
+  *         APB2ENR      TIM8EN        LL_C2_APB2_GRP1_EnableClock\n
+  *         APB2ENR      USART1EN      LL_C2_APB2_GRP1_EnableClock\n
+  *         APB2ENR      USART6EN      LL_C2_APB2_GRP1_EnableClock\n
+  *         APB2ENR      SPI1EN        LL_C2_APB2_GRP1_EnableClock\n
+  *         APB2ENR      SPI4EN        LL_C2_APB2_GRP1_EnableClock\n
+  *         APB2ENR      TIM15EN       LL_C2_APB2_GRP1_EnableClock\n
+  *         APB2ENR      TIM16EN       LL_C2_APB2_GRP1_EnableClock\n
+  *         APB2ENR      TIM17EN       LL_C2_APB2_GRP1_EnableClock\n
+  *         APB2ENR      SPI5EN        LL_C2_APB2_GRP1_EnableClock\n
+  *         APB2ENR      SAI1EN        LL_C2_APB2_GRP1_EnableClock\n
+  *         APB2ENR      SAI2EN        LL_C2_APB2_GRP1_EnableClock\n
+  *         APB2ENR      SAI3EN        LL_C2_APB2_GRP1_EnableClock\n
+  *         APB2ENR      DFSDM1EN      LL_C2_APB2_GRP1_EnableClock\n
+  *         APB2ENR      HRTIMEN       LL_C2_APB2_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2  (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
+  *
+  *         (*) value not defined in all devices.
+
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_APB2_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C2->APB2ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C2->APB2ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if C2 APB2 peripheral clock is enabled or not
+  * @rmtoll APB2ENR      TIM1EN        LL_C2_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      TIM8EN        LL_C2_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      USART1EN      LL_C2_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      USART6EN      LL_C2_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      SPI1EN        LL_C2_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      SPI4EN        LL_C2_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      TIM15EN       LL_C2_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      TIM16EN       LL_C2_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      TIM17EN       LL_C2_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      SPI5EN        LL_C2_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      SAI1EN        LL_C2_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      SAI2EN        LL_C2_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      SAI3EN        LL_C2_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      DFSDM1EN      LL_C2_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      HRTIMEN       LL_C2_APB2_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2  (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_C2_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC_C2->APB2ENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable C2 APB2 peripherals clock.
+  * @rmtoll APB2ENR      TIM1EN        LL_C2_APB2_GRP1_DisableClock\n
+  *         APB2ENR      TIM8EN        LL_C2_APB2_GRP1_DisableClock\n
+  *         APB2ENR      USART1EN      LL_C2_APB2_GRP1_DisableClock\n
+  *         APB2ENR      USART6EN      LL_C2_APB2_GRP1_DisableClock\n
+  *         APB2ENR      SPI1EN        LL_C2_APB2_GRP1_DisableClock\n
+  *         APB2ENR      SPI4EN        LL_C2_APB2_GRP1_DisableClock\n
+  *         APB2ENR      TIM15EN       LL_C2_APB2_GRP1_DisableClock\n
+  *         APB2ENR      TIM16EN       LL_C2_APB2_GRP1_DisableClock\n
+  *         APB2ENR      TIM17EN       LL_C2_APB2_GRP1_DisableClock\n
+  *         APB2ENR      SPI5EN        LL_C2_APB2_GRP1_DisableClock\n
+  *         APB2ENR      SAI1EN        LL_C2_APB2_GRP1_DisableClock\n
+  *         APB2ENR      SAI2EN        LL_C2_APB2_GRP1_DisableClock\n
+  *         APB2ENR      SAI3EN        LL_C2_APB2_GRP1_DisableClock\n
+  *         APB2ENR      DFSDM1EN      LL_C2_APB2_GRP1_DisableClock\n
+  *         APB2ENR      HRTIMEN       LL_C2_APB2_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2  (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_APB2_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C2->APB2ENR, Periphs);
+}
+
+/**
+  * @brief  Enable C2 APB2 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB2LPENR    TIM1LPEN      LL_C2_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    TIM8LPEN      LL_C2_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    USART1LPEN    LL_C2_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    USART6LPEN    LL_C2_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    SPI1LPEN      LL_C2_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    SPI4LPEN      LL_C2_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    TIM15LPEN     LL_C2_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    TIM16LPEN     LL_C2_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    TIM17LPEN     LL_C2_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    SPI5LPEN      LL_C2_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    SAI1LPEN      LL_C2_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    SAI2LPEN      LL_C2_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    SAI3LPEN      LL_C2_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    DFSDM1LPEN    LL_C2_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    HRTIMLPEN     LL_C2_APB2_GRP1_EnableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2  (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_APB2_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C2->APB2LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C2->APB2LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable C2 APB2 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB2LPENR    TIM1LPEN      LL_C2_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    TIM8LPEN      LL_C2_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    USART1LPEN    LL_C2_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    USART6LPEN    LL_C2_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    SPI1LPEN      LL_C2_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    SPI4LPEN      LL_C2_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    TIM15LPEN     LL_C2_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    TIM16LPEN     LL_C2_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    TIM17LPEN     LL_C2_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    SPI5LPEN      LL_C2_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    SAI1LPEN      LL_C2_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    SAI2LPEN      LL_C2_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    SAI3LPEN      LL_C2_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    DFSDM1LPEN    LL_C2_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    HRTIMLPEN     LL_C2_APB2_GRP1_DisableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2  (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_APB2_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C2->APB2LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup BUS_LL_EF_APB4 APB4
+  * @{
+  */
+
+/**
+  * @brief  Enable C2 APB4 peripherals clock.
+  * @rmtoll APB4ENR      SYSCFGEN      LL_C2_APB4_GRP1_EnableClock\n
+  *         APB4ENR      LPUART1EN     LL_C2_APB4_GRP1_EnableClock\n
+  *         APB4ENR      SPI6EN        LL_C2_APB4_GRP1_EnableClock\n
+  *         APB4ENR      I2C4EN        LL_C2_APB4_GRP1_EnableClock\n
+  *         APB4ENR      LPTIM2EN      LL_C2_APB4_GRP1_EnableClock\n
+  *         APB4ENR      LPTIM3EN      LL_C2_APB4_GRP1_EnableClock\n
+  *         APB4ENR      LPTIM4EN      LL_C2_APB4_GRP1_EnableClock\n
+  *         APB4ENR      LPTIM5EN      LL_C2_APB4_GRP1_EnableClock\n
+  *         APB4ENR      COMP12EN      LL_C2_APB4_GRP1_EnableClock\n
+  *         APB4ENR      VREFEN        LL_C2_APB4_GRP1_EnableClock\n
+  *         APB4ENR      RTCAPBEN      LL_C2_APB4_GRP1_EnableClock\n
+  *         APB4ENR      SAI4EN        LL_C2_APB4_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
+  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
+  *
+  *         (*) value not defined in all devices
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_APB4_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C2->APB4ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C2->APB4ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if C2 APB4 peripheral clock is enabled or not
+  * @rmtoll APB4ENR      SYSCFGEN      LL_C2_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      LPUART1EN     LL_C2_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      SPI6EN        LL_C2_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      I2C4EN        LL_C2_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      LPTIM2EN      LL_C2_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      LPTIM3EN      LL_C2_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      LPTIM4EN      LL_C2_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      LPTIM5EN      LL_C2_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      COMP12EN      LL_C2_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      VREFEN        LL_C2_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      RTCAPBEN      LL_C2_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      SAI4EN        LL_C2_APB4_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
+  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
+  *
+  *         (*) value not defined in all devices
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_C2_APB4_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC_C2->APB4ENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable C2 APB4 peripherals clock.
+  * @rmtoll APB4ENR      SYSCFGEN      LL_C2_APB4_GRP1_DisableClock\n
+  *         APB4ENR      LPUART1EN     LL_C2_APB4_GRP1_DisableClock\n
+  *         APB4ENR      SPI6EN        LL_C2_APB4_GRP1_DisableClock\n
+  *         APB4ENR      I2C4EN        LL_C2_APB4_GRP1_DisableClock\n
+  *         APB4ENR      LPTIM2EN      LL_C2_APB4_GRP1_DisableClock\n
+  *         APB4ENR      LPTIM3EN      LL_C2_APB4_GRP1_DisableClock\n
+  *         APB4ENR      LPTIM4EN      LL_C2_APB4_GRP1_DisableClock\n
+  *         APB4ENR      LPTIM5EN      LL_C2_APB4_GRP1_DisableClock\n
+  *         APB4ENR      COMP12EN      LL_C2_APB4_GRP1_DisableClock\n
+  *         APB4ENR      VREFEN        LL_C2_APB4_GRP1_DisableClock\n
+  *         APB4ENR      RTCAPBEN      LL_C2_APB4_GRP1_DisableClock\n
+  *         APB4ENR      SAI4EN        LL_C2_APB4_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
+  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
+  *
+  *         (*) value not defined in all devices
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_APB4_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C2->APB4ENR, Periphs);
+}
+
+/**
+  * @brief  Enable C2 APB4 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB4LPENR    SYSCFGLPEN    LL_C2_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    LPUART1LPEN   LL_C2_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    SPI6LPEN      LL_C2_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    I2C4LPEN      LL_C2_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    LPTIM2LPEN    LL_C2_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    LPTIM3LPEN    LL_C2_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    LPTIM4LPEN    LL_C2_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    LPTIM5LPEN    LL_C2_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    COMP12LPEN    LL_C2_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    VREFLPEN      LL_C2_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    RTCAPBLPEN    LL_C2_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    SAI4LPEN      LL_C2_APB4_GRP1_EnableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
+  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
+  *
+  *         (*) value not defined in all devices
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_APB4_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C2->APB4LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C2->APB4LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable C2 APB4 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB4LPENR    SYSCFGLPEN    LL_C2_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    LPUART1LPEN   LL_C2_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    SPI6LPEN      LL_C2_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    I2C4LPEN      LL_C2_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    LPTIM2LPEN    LL_C2_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    LPTIM3LPEN    LL_C2_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    LPTIM4LPEN    LL_C2_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    LPTIM5LPEN    LL_C2_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    COMP12LPEN    LL_C2_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    VREFLPEN      LL_C2_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    RTCAPBLPEN    LL_C2_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    SAI4LPEN      LL_C2_APB4_GRP1_DisableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
+  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
+  *
+  *         (*) value not defined in all devices
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_APB4_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C2->APB4LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+#endif /*DUAL_CORE*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined(RCC) */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_LL_BUS_H */
+
+
diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_cortex.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_cortex.h
index 4917f651..d9b13b6c 100644
--- a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_cortex.h
+++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_cortex.h
@@ -1,667 +1,667 @@
-/**
-  ******************************************************************************
-  * @file    stm32h7xx_ll_cortex.h
-  * @author  MCD Application Team
-  * @brief   Header file of CORTEX LL module.
-  @verbatim
-  ==============================================================================
-                     ##### How to use this driver #####
-  ==============================================================================
-    [..]
-    The LL CORTEX driver contains a set of generic APIs that can be
-    used by user:
-      (+) SYSTICK configuration used by LL_mDelay and LL_Init1msTick
-          functions
-      (+) Low power mode configuration (SCB register of Cortex-MCU)
-      (+) MPU API to configure and enable regions
-      (+) API to access to MCU info (CPUID register)
-      (+) API to enable fault handler (SHCSR accesses)
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file in
-  * the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32H7xx_LL_CORTEX_H
-#define STM32H7xx_LL_CORTEX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx.h"
-
-/** @addtogroup STM32H7xx_LL_Driver
-  * @{
-  */
-
-/** @defgroup CORTEX_LL CORTEX
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-
-/* Private macros ------------------------------------------------------------*/
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
-  * @{
-  */
-
-/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
-  * @{
-  */
-#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8     0x00000000UL                /*!< AHB clock divided by 8 selected as SysTick clock source.*/
-#define LL_SYSTICK_CLKSOURCE_HCLK          SysTick_CTRL_CLKSOURCE_Msk  /*!< AHB clock selected as SysTick clock source. */
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
-  * @{
-  */
-#define LL_HANDLER_FAULT_USG               SCB_SHCSR_USGFAULTENA_Msk              /*!< Usage fault */
-#define LL_HANDLER_FAULT_BUS               SCB_SHCSR_BUSFAULTENA_Msk              /*!< Bus fault */
-#define LL_HANDLER_FAULT_MEM               SCB_SHCSR_MEMFAULTENA_Msk              /*!< Memory management fault */
-/**
-  * @}
-  */
-
-#if __MPU_PRESENT
-
-/** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
-  * @{
-  */
-#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE     0x00000000UL                                      /*!< Disable NMI and privileged SW access */
-#define LL_MPU_CTRL_HARDFAULT_NMI          MPU_CTRL_HFNMIENA_Msk                             /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
-#define LL_MPU_CTRL_PRIVILEGED_DEFAULT     MPU_CTRL_PRIVDEFENA_Msk                           /*!< Enable privileged software access to default memory map */
-#define LL_MPU_CTRL_HFNMI_PRIVDEF          (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_LL_EC_REGION MPU Region Number
-  * @{
-  */
-#define LL_MPU_REGION_NUMBER0              0x00UL /*!< REGION Number 0  */
-#define LL_MPU_REGION_NUMBER1              0x01UL /*!< REGION Number 1  */
-#define LL_MPU_REGION_NUMBER2              0x02UL /*!< REGION Number 2  */
-#define LL_MPU_REGION_NUMBER3              0x03UL /*!< REGION Number 3  */
-#define LL_MPU_REGION_NUMBER4              0x04UL /*!< REGION Number 4  */
-#define LL_MPU_REGION_NUMBER5              0x05UL /*!< REGION Number 5  */
-#define LL_MPU_REGION_NUMBER6              0x06UL /*!< REGION Number 6  */
-#define LL_MPU_REGION_NUMBER7              0x07UL /*!< REGION Number 7  */
-#if !defined(CORE_CM4)
-#define LL_MPU_REGION_NUMBER8              0x08UL /*!< REGION Number 8  */
-#define LL_MPU_REGION_NUMBER9              0x09UL /*!< REGION Number 9  */
-#define LL_MPU_REGION_NUMBER10             0x0AUL /*!< REGION Number 10 */
-#define LL_MPU_REGION_NUMBER11             0x0BUL /*!< REGION Number 11 */
-#define LL_MPU_REGION_NUMBER12             0x0CUL /*!< REGION Number 12 */
-#define LL_MPU_REGION_NUMBER13             0x0DUL /*!< REGION Number 13 */
-#define LL_MPU_REGION_NUMBER14             0x0EUL /*!< REGION Number 14 */
-#define LL_MPU_REGION_NUMBER15             0x0FUL /*!< REGION Number 15 */
-#endif /* !defined(CORE_CM4) */
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
-  * @{
-  */
-#define LL_MPU_REGION_SIZE_32B             (0x04UL << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_64B             (0x05UL << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_128B            (0x06UL << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_256B            (0x07UL << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_512B            (0x08UL << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_1KB             (0x09UL << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_2KB             (0x0AUL << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_4KB             (0x0BUL << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_8KB             (0x0CUL << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_16KB            (0x0DUL << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_32KB            (0x0EUL << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_64KB            (0x0FUL << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_128KB           (0x10UL << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_256KB           (0x11UL << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_512KB           (0x12UL << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_1MB             (0x13UL << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_2MB             (0x14UL << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_4MB             (0x15UL << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_8MB             (0x16UL << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_16MB            (0x17UL << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_32MB            (0x18UL << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_64MB            (0x19UL << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_128MB           (0x1AUL << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_256MB           (0x1BUL << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_512MB           (0x1CUL << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_1GB             (0x1DUL << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_2GB             (0x1EUL << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_4GB             (0x1FUL << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
-  * @{
-  */
-#define LL_MPU_REGION_NO_ACCESS            (0x00UL << MPU_RASR_AP_Pos) /*!< No access*/
-#define LL_MPU_REGION_PRIV_RW              (0x01UL << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/
-#define LL_MPU_REGION_PRIV_RW_URO          (0x02UL << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */
-#define LL_MPU_REGION_FULL_ACCESS          (0x03UL << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */
-#define LL_MPU_REGION_PRIV_RO              (0x05UL << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/
-#define LL_MPU_REGION_PRIV_RO_URO          (0x06UL << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
-  * @{
-  */
-#define LL_MPU_TEX_LEVEL0                  (0x00UL << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
-#define LL_MPU_TEX_LEVEL1                  (0x01UL << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
-#define LL_MPU_TEX_LEVEL2                  (0x02UL << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
-#define LL_MPU_TEX_LEVEL4                  (0x04UL << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
-  * @{
-  */
-#define LL_MPU_INSTRUCTION_ACCESS_ENABLE   0x00UL            /*!< Instruction fetches enabled */
-#define LL_MPU_INSTRUCTION_ACCESS_DISABLE  MPU_RASR_XN_Msk  /*!< Instruction fetches disabled*/
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
-  * @{
-  */
-#define LL_MPU_ACCESS_SHAREABLE            MPU_RASR_S_Msk   /*!< Shareable memory attribute */
-#define LL_MPU_ACCESS_NOT_SHAREABLE        0x00UL           /*!< Not Shareable memory attribute */
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
-  * @{
-  */
-#define LL_MPU_ACCESS_CACHEABLE            MPU_RASR_C_Msk   /*!< Cacheable memory attribute */
-#define LL_MPU_ACCESS_NOT_CACHEABLE        0x00UL           /*!< Not Cacheable memory attribute */
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
-  * @{
-  */
-#define LL_MPU_ACCESS_BUFFERABLE           MPU_RASR_B_Msk   /*!< Bufferable memory attribute */
-#define LL_MPU_ACCESS_NOT_BUFFERABLE       0x00UL           /*!< Not Bufferable memory attribute */
-/**
-  * @}
-  */
-#endif /* __MPU_PRESENT */
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
-  * @{
-  */
-
-/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
-  * @{
-  */
-
-/**
-  * @brief  This function checks if the Systick counter flag is active or not.
-  * @note   It can be used in timeout function on application side.
-  * @rmtoll STK_CTRL     COUNTFLAG     LL_SYSTICK_IsActiveCounterFlag
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
-{
-  return (((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Configures the SysTick clock source
-  * @rmtoll STK_CTRL     CLKSOURCE     LL_SYSTICK_SetClkSource
-  * @param  Source This parameter can be one of the following values:
-  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
-  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
-{
-  MODIFY_REG(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK, Source);
-}
-
-/**
-  * @brief  Get the SysTick clock source
-  * @rmtoll STK_CTRL     CLKSOURCE     LL_SYSTICK_GetClkSource
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
-  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
-  */
-__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
-{
-  return (uint32_t)(READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK));
-}
-
-/**
-  * @brief  Enable SysTick exception request
-  * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_EnableIT
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSTICK_EnableIT(void)
-{
-  SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
-}
-
-/**
-  * @brief  Disable SysTick exception request
-  * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_DisableIT
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSTICK_DisableIT(void)
-{
-  CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
-}
-
-/**
-  * @brief  Checks if the SYSTICK interrupt is enabled or disabled.
-  * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_IsEnabledIT
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
-{
-  return ((READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
-  * @{
-  */
-
-/**
-  * @brief  Processor uses sleep as its low power mode
-  * @rmtoll SCB_SCR      SLEEPDEEP     LL_LPM_EnableSleep
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPM_EnableSleep(void)
-{
-  /* Clear SLEEPDEEP bit of Cortex System Control Register */
-  CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
-}
-
-/**
-  * @brief  Processor uses deep sleep as its low power mode
-  * @rmtoll SCB_SCR      SLEEPDEEP     LL_LPM_EnableDeepSleep
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
-{
-  /* Set SLEEPDEEP bit of Cortex System Control Register */
-  SET_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
-}
-
-/**
-  * @brief  Configures sleep-on-exit when returning from Handler mode to Thread mode.
-  * @note   Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
-  *         empty main application.
-  * @rmtoll SCB_SCR      SLEEPONEXIT   LL_LPM_EnableSleepOnExit
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
-{
-  /* Set SLEEPONEXIT bit of Cortex System Control Register */
-  SET_BIT(SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk);
-}
-
-/**
-  * @brief  Do not sleep when returning to Thread mode.
-  * @rmtoll SCB_SCR      SLEEPONEXIT   LL_LPM_DisableSleepOnExit
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
-{
-  /* Clear SLEEPONEXIT bit of Cortex System Control Register */
-  CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk);
-}
-
-/**
-  * @brief  Enabled events and all interrupts, including disabled interrupts, can wakeup the
-  *         processor.
-  * @rmtoll SCB_SCR      SEVEONPEND    LL_LPM_EnableEventOnPend
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
-{
-  /* Set SEVEONPEND bit of Cortex System Control Register */
-  SET_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk);
-}
-
-/**
-  * @brief  Only enabled interrupts or events can wakeup the processor, disabled interrupts are
-  *         excluded
-  * @rmtoll SCB_SCR      SEVEONPEND    LL_LPM_DisableEventOnPend
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
-{
-  /* Clear SEVEONPEND bit of Cortex System Control Register */
-  CLEAR_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_LL_EF_HANDLER HANDLER
-  * @{
-  */
-
-/**
-  * @brief  Enable a fault in System handler control register (SHCSR)
-  * @rmtoll SCB_SHCSR    MEMFAULTENA   LL_HANDLER_EnableFault
-  * @param  Fault This parameter can be a combination of the following values:
-  *         @arg @ref LL_HANDLER_FAULT_USG
-  *         @arg @ref LL_HANDLER_FAULT_BUS
-  *         @arg @ref LL_HANDLER_FAULT_MEM
-  * @retval None
-  */
-__STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
-{
-  /* Enable the system handler fault */
-  SET_BIT(SCB->SHCSR, Fault);
-}
-
-/**
-  * @brief  Disable a fault in System handler control register (SHCSR)
-  * @rmtoll SCB_SHCSR    MEMFAULTENA   LL_HANDLER_DisableFault
-  * @param  Fault This parameter can be a combination of the following values:
-  *         @arg @ref LL_HANDLER_FAULT_USG
-  *         @arg @ref LL_HANDLER_FAULT_BUS
-  *         @arg @ref LL_HANDLER_FAULT_MEM
-  * @retval None
-  */
-__STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
-{
-  /* Disable the system handler fault */
-  CLEAR_BIT(SCB->SHCSR, Fault);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
-  * @{
-  */
-
-/**
-  * @brief  Get Implementer code
-  * @rmtoll SCB_CPUID    IMPLEMENTER   LL_CPUID_GetImplementer
-  * @retval Value should be equal to 0x41 for ARM
-  */
-__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
-{
-  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
-}
-
-/**
-  * @brief  Get Variant number (The r value in the rnpn product revision identifier)
-  * @rmtoll SCB_CPUID    VARIANT       LL_CPUID_GetVariant
-  * @retval Value between 0 and 255 (0x0: revision 0)
-  */
-__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
-{
-  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
-}
-
-/**
-  * @brief  Get Constant number
-  * @rmtoll SCB_CPUID    ARCHITECTURE  LL_CPUID_GetConstant
-  * @retval Value should be equal to 0xF for Cortex-M7 and Cortex-M4 devices
-  */
-__STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)
-{
-  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
-}
-
-/**
-  * @brief  Get Part number
-  * @rmtoll SCB_CPUID    PARTNO        LL_CPUID_GetParNo
-  * @retval Value should be equal to 0xC27 for Cortex-M7 and equal to 0xC24 for Cortex-M4
-  */
-__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
-{
-  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
-}
-
-/**
-  * @brief  Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
-  * @rmtoll SCB_CPUID    REVISION      LL_CPUID_GetRevision
-  * @retval Value between 0 and 255 (0x1: patch 1)
-  */
-__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
-{
-  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
-}
-
-/**
-  * @}
-  */
-
-#if __MPU_PRESENT
-/** @defgroup CORTEX_LL_EF_MPU MPU
-  * @{
-  */
-
-/**
-  * @brief  Enable MPU with input options
-  * @rmtoll MPU_CTRL     ENABLE        LL_MPU_Enable
-  * @param  Options This parameter can be one of the following values:
-  *         @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
-  *         @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
-  *         @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
-  *         @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
-  * @retval None
-  */
-__STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
-{
-  /* Enable the MPU*/
-  WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
-  /* Ensure MPU settings take effects */
-  __DSB();
-  /* Sequence instruction fetches using update settings */
-  __ISB();
-}
-
-/**
-  * @brief  Disable MPU
-  * @rmtoll MPU_CTRL     ENABLE        LL_MPU_Disable
-  * @retval None
-  */
-__STATIC_INLINE void LL_MPU_Disable(void)
-{
-  /* Make sure outstanding transfers are done */
-  __DMB();
-  /* Disable MPU*/
-  WRITE_REG(MPU->CTRL, 0U);
-}
-
-/**
-  * @brief  Check if MPU is enabled or not
-  * @rmtoll MPU_CTRL     ENABLE        LL_MPU_IsEnabled
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
-{
-  return ((READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable a MPU region
-  * @rmtoll MPU_RASR     ENABLE        LL_MPU_EnableRegion
-  * @param  Region This parameter can be one of the following values:
-  *         @arg @ref LL_MPU_REGION_NUMBER0
-  *         @arg @ref LL_MPU_REGION_NUMBER1
-  *         @arg @ref LL_MPU_REGION_NUMBER2
-  *         @arg @ref LL_MPU_REGION_NUMBER3
-  *         @arg @ref LL_MPU_REGION_NUMBER4
-  *         @arg @ref LL_MPU_REGION_NUMBER5
-  *         @arg @ref LL_MPU_REGION_NUMBER6
-  *         @arg @ref LL_MPU_REGION_NUMBER7
-  *         @arg @ref LL_MPU_REGION_NUMBER8
-  *         @arg @ref LL_MPU_REGION_NUMBER9
-  *         @arg @ref LL_MPU_REGION_NUMBER10
-  *         @arg @ref LL_MPU_REGION_NUMBER11
-  *         @arg @ref LL_MPU_REGION_NUMBER12
-  *         @arg @ref LL_MPU_REGION_NUMBER13
-  *         @arg @ref LL_MPU_REGION_NUMBER14
-  *         @arg @ref LL_MPU_REGION_NUMBER15
-  * @note   For cortex-M4 only 8 regions are available i.e only values from LL_MPU_REGION_NUMBER0 to LL_MPU_REGION_NUMBER7 are possible.
-  * @retval None
-  */
-__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
-{
-  /* Set Region number */
-  WRITE_REG(MPU->RNR, Region);
-  /* Enable the MPU region */
-  SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
-}
-
-/**
-  * @brief  Configure and enable a region
-  * @rmtoll MPU_RNR      REGION        LL_MPU_ConfigRegion\n
-  *         MPU_RBAR     REGION        LL_MPU_ConfigRegion\n
-  *         MPU_RBAR     ADDR          LL_MPU_ConfigRegion\n
-  *         MPU_RASR     XN            LL_MPU_ConfigRegion\n
-  *         MPU_RASR     AP            LL_MPU_ConfigRegion\n
-  *         MPU_RASR     S             LL_MPU_ConfigRegion\n
-  *         MPU_RASR     C             LL_MPU_ConfigRegion\n
-  *         MPU_RASR     B             LL_MPU_ConfigRegion\n
-  *         MPU_RASR     SIZE          LL_MPU_ConfigRegion
-  * @param  Region This parameter can be one of the following values:
-  *         @arg @ref LL_MPU_REGION_NUMBER0
-  *         @arg @ref LL_MPU_REGION_NUMBER1
-  *         @arg @ref LL_MPU_REGION_NUMBER2
-  *         @arg @ref LL_MPU_REGION_NUMBER3
-  *         @arg @ref LL_MPU_REGION_NUMBER4
-  *         @arg @ref LL_MPU_REGION_NUMBER5
-  *         @arg @ref LL_MPU_REGION_NUMBER6
-  *         @arg @ref LL_MPU_REGION_NUMBER7
-  *         @arg @ref LL_MPU_REGION_NUMBER8
-  *         @arg @ref LL_MPU_REGION_NUMBER9
-  *         @arg @ref LL_MPU_REGION_NUMBER10
-  *         @arg @ref LL_MPU_REGION_NUMBER11
-  *         @arg @ref LL_MPU_REGION_NUMBER12
-  *         @arg @ref LL_MPU_REGION_NUMBER13
-  *         @arg @ref LL_MPU_REGION_NUMBER14
-  *         @arg @ref LL_MPU_REGION_NUMBER15
-  * @param  Address Value of region base address
-  * @param  SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
-  * @param  Attributes This parameter can be a combination of the following values:
-  *         @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
-  *           or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
-  *           or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
-  *           or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
-  *           or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
-  *           or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
-  *         @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
-  *           or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
-  *         @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
-  *         @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or  @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
-  *         @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
-  *         @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
-  *         @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
-  * @note   For cortex-M4 only 8 regions are available i.e only values from LL_MPU_REGION_NUMBER0 to LL_MPU_REGION_NUMBER7 are possible.
-  * @retval None
-  */
-__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
-{
-  /* Set Region number */
-  WRITE_REG(MPU->RNR, Region);
-  /* Set base address */
-  WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
-  /* Configure MPU */
-  WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | (SubRegionDisable << MPU_RASR_SRD_Pos)));
-}
-
-/**
-  * @brief  Disable a region
-  * @rmtoll MPU_RNR      REGION        LL_MPU_DisableRegion\n
-  *         MPU_RASR     ENABLE        LL_MPU_DisableRegion
-  * @param  Region This parameter can be one of the following values:
-  *         @arg @ref LL_MPU_REGION_NUMBER0
-  *         @arg @ref LL_MPU_REGION_NUMBER1
-  *         @arg @ref LL_MPU_REGION_NUMBER2
-  *         @arg @ref LL_MPU_REGION_NUMBER3
-  *         @arg @ref LL_MPU_REGION_NUMBER4
-  *         @arg @ref LL_MPU_REGION_NUMBER5
-  *         @arg @ref LL_MPU_REGION_NUMBER6
-  *         @arg @ref LL_MPU_REGION_NUMBER7
-  *         @arg @ref LL_MPU_REGION_NUMBER8
-  *         @arg @ref LL_MPU_REGION_NUMBER9
-  *         @arg @ref LL_MPU_REGION_NUMBER10
-  *         @arg @ref LL_MPU_REGION_NUMBER11
-  *         @arg @ref LL_MPU_REGION_NUMBER12
-  *         @arg @ref LL_MPU_REGION_NUMBER13
-  *         @arg @ref LL_MPU_REGION_NUMBER14
-  *         @arg @ref LL_MPU_REGION_NUMBER15
-  * @note   For cortex-M4 only 8 regions are available i.e only values from LL_MPU_REGION_NUMBER0 to LL_MPU_REGION_NUMBER7 are possible.
-  * @retval None
-  */
-__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
-{
-  /* Set Region number */
-  WRITE_REG(MPU->RNR, Region);
-  /* Disable the MPU region */
-  CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
-}
-
-/**
-  * @}
-  */
-
-#endif /* __MPU_PRESENT */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32H7xx_LL_CORTEX_H */
-
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_ll_cortex.h
+  * @author  MCD Application Team
+  * @brief   Header file of CORTEX LL module.
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    The LL CORTEX driver contains a set of generic APIs that can be
+    used by user:
+      (+) SYSTICK configuration used by LL_mDelay and LL_Init1msTick
+          functions
+      (+) Low power mode configuration (SCB register of Cortex-MCU)
+      (+) MPU API to configure and enable regions
+      (+) API to access to MCU info (CPUID register)
+      (+) API to enable fault handler (SHCSR accesses)
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_LL_CORTEX_H
+#define STM32H7xx_LL_CORTEX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx.h"
+
+/** @addtogroup STM32H7xx_LL_Driver
+  * @{
+  */
+
+/** @defgroup CORTEX_LL CORTEX
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
+  * @{
+  */
+
+/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
+  * @{
+  */
+#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8     0x00000000UL                /*!< AHB clock divided by 8 selected as SysTick clock source.*/
+#define LL_SYSTICK_CLKSOURCE_HCLK          SysTick_CTRL_CLKSOURCE_Msk  /*!< AHB clock selected as SysTick clock source. */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
+  * @{
+  */
+#define LL_HANDLER_FAULT_USG               SCB_SHCSR_USGFAULTENA_Msk              /*!< Usage fault */
+#define LL_HANDLER_FAULT_BUS               SCB_SHCSR_BUSFAULTENA_Msk              /*!< Bus fault */
+#define LL_HANDLER_FAULT_MEM               SCB_SHCSR_MEMFAULTENA_Msk              /*!< Memory management fault */
+/**
+  * @}
+  */
+
+#if __MPU_PRESENT
+
+/** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
+  * @{
+  */
+#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE     0x00000000UL                                      /*!< Disable NMI and privileged SW access */
+#define LL_MPU_CTRL_HARDFAULT_NMI          MPU_CTRL_HFNMIENA_Msk                             /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
+#define LL_MPU_CTRL_PRIVILEGED_DEFAULT     MPU_CTRL_PRIVDEFENA_Msk                           /*!< Enable privileged software access to default memory map */
+#define LL_MPU_CTRL_HFNMI_PRIVDEF          (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_REGION MPU Region Number
+  * @{
+  */
+#define LL_MPU_REGION_NUMBER0              0x00UL /*!< REGION Number 0  */
+#define LL_MPU_REGION_NUMBER1              0x01UL /*!< REGION Number 1  */
+#define LL_MPU_REGION_NUMBER2              0x02UL /*!< REGION Number 2  */
+#define LL_MPU_REGION_NUMBER3              0x03UL /*!< REGION Number 3  */
+#define LL_MPU_REGION_NUMBER4              0x04UL /*!< REGION Number 4  */
+#define LL_MPU_REGION_NUMBER5              0x05UL /*!< REGION Number 5  */
+#define LL_MPU_REGION_NUMBER6              0x06UL /*!< REGION Number 6  */
+#define LL_MPU_REGION_NUMBER7              0x07UL /*!< REGION Number 7  */
+#if !defined(CORE_CM4)
+#define LL_MPU_REGION_NUMBER8              0x08UL /*!< REGION Number 8  */
+#define LL_MPU_REGION_NUMBER9              0x09UL /*!< REGION Number 9  */
+#define LL_MPU_REGION_NUMBER10             0x0AUL /*!< REGION Number 10 */
+#define LL_MPU_REGION_NUMBER11             0x0BUL /*!< REGION Number 11 */
+#define LL_MPU_REGION_NUMBER12             0x0CUL /*!< REGION Number 12 */
+#define LL_MPU_REGION_NUMBER13             0x0DUL /*!< REGION Number 13 */
+#define LL_MPU_REGION_NUMBER14             0x0EUL /*!< REGION Number 14 */
+#define LL_MPU_REGION_NUMBER15             0x0FUL /*!< REGION Number 15 */
+#endif /* !defined(CORE_CM4) */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
+  * @{
+  */
+#define LL_MPU_REGION_SIZE_32B             (0x04UL << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_64B             (0x05UL << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_128B            (0x06UL << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_256B            (0x07UL << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_512B            (0x08UL << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_1KB             (0x09UL << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_2KB             (0x0AUL << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_4KB             (0x0BUL << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_8KB             (0x0CUL << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_16KB            (0x0DUL << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_32KB            (0x0EUL << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_64KB            (0x0FUL << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_128KB           (0x10UL << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_256KB           (0x11UL << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_512KB           (0x12UL << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_1MB             (0x13UL << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_2MB             (0x14UL << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_4MB             (0x15UL << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_8MB             (0x16UL << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_16MB            (0x17UL << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_32MB            (0x18UL << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_64MB            (0x19UL << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_128MB           (0x1AUL << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_256MB           (0x1BUL << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_512MB           (0x1CUL << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_1GB             (0x1DUL << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_2GB             (0x1EUL << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_4GB             (0x1FUL << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
+  * @{
+  */
+#define LL_MPU_REGION_NO_ACCESS            (0x00UL << MPU_RASR_AP_Pos) /*!< No access*/
+#define LL_MPU_REGION_PRIV_RW              (0x01UL << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/
+#define LL_MPU_REGION_PRIV_RW_URO          (0x02UL << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */
+#define LL_MPU_REGION_FULL_ACCESS          (0x03UL << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */
+#define LL_MPU_REGION_PRIV_RO              (0x05UL << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/
+#define LL_MPU_REGION_PRIV_RO_URO          (0x06UL << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
+  * @{
+  */
+#define LL_MPU_TEX_LEVEL0                  (0x00UL << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
+#define LL_MPU_TEX_LEVEL1                  (0x01UL << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
+#define LL_MPU_TEX_LEVEL2                  (0x02UL << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
+#define LL_MPU_TEX_LEVEL4                  (0x04UL << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
+  * @{
+  */
+#define LL_MPU_INSTRUCTION_ACCESS_ENABLE   0x00UL            /*!< Instruction fetches enabled */
+#define LL_MPU_INSTRUCTION_ACCESS_DISABLE  MPU_RASR_XN_Msk  /*!< Instruction fetches disabled*/
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
+  * @{
+  */
+#define LL_MPU_ACCESS_SHAREABLE            MPU_RASR_S_Msk   /*!< Shareable memory attribute */
+#define LL_MPU_ACCESS_NOT_SHAREABLE        0x00UL           /*!< Not Shareable memory attribute */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
+  * @{
+  */
+#define LL_MPU_ACCESS_CACHEABLE            MPU_RASR_C_Msk   /*!< Cacheable memory attribute */
+#define LL_MPU_ACCESS_NOT_CACHEABLE        0x00UL           /*!< Not Cacheable memory attribute */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
+  * @{
+  */
+#define LL_MPU_ACCESS_BUFFERABLE           MPU_RASR_B_Msk   /*!< Bufferable memory attribute */
+#define LL_MPU_ACCESS_NOT_BUFFERABLE       0x00UL           /*!< Not Bufferable memory attribute */
+/**
+  * @}
+  */
+#endif /* __MPU_PRESENT */
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
+  * @{
+  */
+
+/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
+  * @{
+  */
+
+/**
+  * @brief  This function checks if the Systick counter flag is active or not.
+  * @note   It can be used in timeout function on application side.
+  * @rmtoll STK_CTRL     COUNTFLAG     LL_SYSTICK_IsActiveCounterFlag
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
+{
+  return (((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Configures the SysTick clock source
+  * @rmtoll STK_CTRL     CLKSOURCE     LL_SYSTICK_SetClkSource
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
+  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
+{
+  MODIFY_REG(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK, Source);
+}
+
+/**
+  * @brief  Get the SysTick clock source
+  * @rmtoll STK_CTRL     CLKSOURCE     LL_SYSTICK_GetClkSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
+  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
+  */
+__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
+{
+  return (uint32_t)(READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK));
+}
+
+/**
+  * @brief  Enable SysTick exception request
+  * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_EnableIT
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSTICK_EnableIT(void)
+{
+  SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
+}
+
+/**
+  * @brief  Disable SysTick exception request
+  * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_DisableIT
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSTICK_DisableIT(void)
+{
+  CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
+}
+
+/**
+  * @brief  Checks if the SYSTICK interrupt is enabled or disabled.
+  * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_IsEnabledIT
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
+{
+  return ((READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
+  * @{
+  */
+
+/**
+  * @brief  Processor uses sleep as its low power mode
+  * @rmtoll SCB_SCR      SLEEPDEEP     LL_LPM_EnableSleep
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPM_EnableSleep(void)
+{
+  /* Clear SLEEPDEEP bit of Cortex System Control Register */
+  CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
+}
+
+/**
+  * @brief  Processor uses deep sleep as its low power mode
+  * @rmtoll SCB_SCR      SLEEPDEEP     LL_LPM_EnableDeepSleep
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
+{
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  SET_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
+}
+
+/**
+  * @brief  Configures sleep-on-exit when returning from Handler mode to Thread mode.
+  * @note   Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
+  *         empty main application.
+  * @rmtoll SCB_SCR      SLEEPONEXIT   LL_LPM_EnableSleepOnExit
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
+{
+  /* Set SLEEPONEXIT bit of Cortex System Control Register */
+  SET_BIT(SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk);
+}
+
+/**
+  * @brief  Do not sleep when returning to Thread mode.
+  * @rmtoll SCB_SCR      SLEEPONEXIT   LL_LPM_DisableSleepOnExit
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
+{
+  /* Clear SLEEPONEXIT bit of Cortex System Control Register */
+  CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk);
+}
+
+/**
+  * @brief  Enabled events and all interrupts, including disabled interrupts, can wakeup the
+  *         processor.
+  * @rmtoll SCB_SCR      SEVEONPEND    LL_LPM_EnableEventOnPend
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
+{
+  /* Set SEVEONPEND bit of Cortex System Control Register */
+  SET_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk);
+}
+
+/**
+  * @brief  Only enabled interrupts or events can wakeup the processor, disabled interrupts are
+  *         excluded
+  * @rmtoll SCB_SCR      SEVEONPEND    LL_LPM_DisableEventOnPend
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
+{
+  /* Clear SEVEONPEND bit of Cortex System Control Register */
+  CLEAR_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EF_HANDLER HANDLER
+  * @{
+  */
+
+/**
+  * @brief  Enable a fault in System handler control register (SHCSR)
+  * @rmtoll SCB_SHCSR    MEMFAULTENA   LL_HANDLER_EnableFault
+  * @param  Fault This parameter can be a combination of the following values:
+  *         @arg @ref LL_HANDLER_FAULT_USG
+  *         @arg @ref LL_HANDLER_FAULT_BUS
+  *         @arg @ref LL_HANDLER_FAULT_MEM
+  * @retval None
+  */
+__STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
+{
+  /* Enable the system handler fault */
+  SET_BIT(SCB->SHCSR, Fault);
+}
+
+/**
+  * @brief  Disable a fault in System handler control register (SHCSR)
+  * @rmtoll SCB_SHCSR    MEMFAULTENA   LL_HANDLER_DisableFault
+  * @param  Fault This parameter can be a combination of the following values:
+  *         @arg @ref LL_HANDLER_FAULT_USG
+  *         @arg @ref LL_HANDLER_FAULT_BUS
+  *         @arg @ref LL_HANDLER_FAULT_MEM
+  * @retval None
+  */
+__STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
+{
+  /* Disable the system handler fault */
+  CLEAR_BIT(SCB->SHCSR, Fault);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
+  * @{
+  */
+
+/**
+  * @brief  Get Implementer code
+  * @rmtoll SCB_CPUID    IMPLEMENTER   LL_CPUID_GetImplementer
+  * @retval Value should be equal to 0x41 for ARM
+  */
+__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
+{
+  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
+}
+
+/**
+  * @brief  Get Variant number (The r value in the rnpn product revision identifier)
+  * @rmtoll SCB_CPUID    VARIANT       LL_CPUID_GetVariant
+  * @retval Value between 0 and 255 (0x0: revision 0)
+  */
+__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
+{
+  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
+}
+
+/**
+  * @brief  Get Constant number
+  * @rmtoll SCB_CPUID    ARCHITECTURE  LL_CPUID_GetConstant
+  * @retval Value should be equal to 0xF for Cortex-M7 and Cortex-M4 devices
+  */
+__STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)
+{
+  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
+}
+
+/**
+  * @brief  Get Part number
+  * @rmtoll SCB_CPUID    PARTNO        LL_CPUID_GetParNo
+  * @retval Value should be equal to 0xC27 for Cortex-M7 and equal to 0xC24 for Cortex-M4
+  */
+__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
+{
+  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
+}
+
+/**
+  * @brief  Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
+  * @rmtoll SCB_CPUID    REVISION      LL_CPUID_GetRevision
+  * @retval Value between 0 and 255 (0x1: patch 1)
+  */
+__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
+{
+  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
+}
+
+/**
+  * @}
+  */
+
+#if __MPU_PRESENT
+/** @defgroup CORTEX_LL_EF_MPU MPU
+  * @{
+  */
+
+/**
+  * @brief  Enable MPU with input options
+  * @rmtoll MPU_CTRL     ENABLE        LL_MPU_Enable
+  * @param  Options This parameter can be one of the following values:
+  *         @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
+  *         @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
+  *         @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
+  *         @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
+  * @retval None
+  */
+__STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
+{
+  /* Enable the MPU*/
+  WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
+  /* Ensure MPU settings take effects */
+  __DSB();
+  /* Sequence instruction fetches using update settings */
+  __ISB();
+}
+
+/**
+  * @brief  Disable MPU
+  * @rmtoll MPU_CTRL     ENABLE        LL_MPU_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_MPU_Disable(void)
+{
+  /* Make sure outstanding transfers are done */
+  __DMB();
+  /* Disable MPU*/
+  WRITE_REG(MPU->CTRL, 0U);
+}
+
+/**
+  * @brief  Check if MPU is enabled or not
+  * @rmtoll MPU_CTRL     ENABLE        LL_MPU_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
+{
+  return ((READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable a MPU region
+  * @rmtoll MPU_RASR     ENABLE        LL_MPU_EnableRegion
+  * @param  Region This parameter can be one of the following values:
+  *         @arg @ref LL_MPU_REGION_NUMBER0
+  *         @arg @ref LL_MPU_REGION_NUMBER1
+  *         @arg @ref LL_MPU_REGION_NUMBER2
+  *         @arg @ref LL_MPU_REGION_NUMBER3
+  *         @arg @ref LL_MPU_REGION_NUMBER4
+  *         @arg @ref LL_MPU_REGION_NUMBER5
+  *         @arg @ref LL_MPU_REGION_NUMBER6
+  *         @arg @ref LL_MPU_REGION_NUMBER7
+  *         @arg @ref LL_MPU_REGION_NUMBER8
+  *         @arg @ref LL_MPU_REGION_NUMBER9
+  *         @arg @ref LL_MPU_REGION_NUMBER10
+  *         @arg @ref LL_MPU_REGION_NUMBER11
+  *         @arg @ref LL_MPU_REGION_NUMBER12
+  *         @arg @ref LL_MPU_REGION_NUMBER13
+  *         @arg @ref LL_MPU_REGION_NUMBER14
+  *         @arg @ref LL_MPU_REGION_NUMBER15
+  * @note   For cortex-M4 only 8 regions are available i.e only values from LL_MPU_REGION_NUMBER0 to LL_MPU_REGION_NUMBER7 are possible.
+  * @retval None
+  */
+__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
+{
+  /* Set Region number */
+  WRITE_REG(MPU->RNR, Region);
+  /* Enable the MPU region */
+  SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
+}
+
+/**
+  * @brief  Configure and enable a region
+  * @rmtoll MPU_RNR      REGION        LL_MPU_ConfigRegion\n
+  *         MPU_RBAR     REGION        LL_MPU_ConfigRegion\n
+  *         MPU_RBAR     ADDR          LL_MPU_ConfigRegion\n
+  *         MPU_RASR     XN            LL_MPU_ConfigRegion\n
+  *         MPU_RASR     AP            LL_MPU_ConfigRegion\n
+  *         MPU_RASR     S             LL_MPU_ConfigRegion\n
+  *         MPU_RASR     C             LL_MPU_ConfigRegion\n
+  *         MPU_RASR     B             LL_MPU_ConfigRegion\n
+  *         MPU_RASR     SIZE          LL_MPU_ConfigRegion
+  * @param  Region This parameter can be one of the following values:
+  *         @arg @ref LL_MPU_REGION_NUMBER0
+  *         @arg @ref LL_MPU_REGION_NUMBER1
+  *         @arg @ref LL_MPU_REGION_NUMBER2
+  *         @arg @ref LL_MPU_REGION_NUMBER3
+  *         @arg @ref LL_MPU_REGION_NUMBER4
+  *         @arg @ref LL_MPU_REGION_NUMBER5
+  *         @arg @ref LL_MPU_REGION_NUMBER6
+  *         @arg @ref LL_MPU_REGION_NUMBER7
+  *         @arg @ref LL_MPU_REGION_NUMBER8
+  *         @arg @ref LL_MPU_REGION_NUMBER9
+  *         @arg @ref LL_MPU_REGION_NUMBER10
+  *         @arg @ref LL_MPU_REGION_NUMBER11
+  *         @arg @ref LL_MPU_REGION_NUMBER12
+  *         @arg @ref LL_MPU_REGION_NUMBER13
+  *         @arg @ref LL_MPU_REGION_NUMBER14
+  *         @arg @ref LL_MPU_REGION_NUMBER15
+  * @param  Address Value of region base address
+  * @param  SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
+  * @param  Attributes This parameter can be a combination of the following values:
+  *         @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
+  *           or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
+  *           or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
+  *           or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
+  *           or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
+  *           or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
+  *         @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
+  *           or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
+  *         @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
+  *         @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or  @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
+  *         @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
+  *         @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
+  *         @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
+  * @note   For cortex-M4 only 8 regions are available i.e only values from LL_MPU_REGION_NUMBER0 to LL_MPU_REGION_NUMBER7 are possible.
+  * @retval None
+  */
+__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
+{
+  /* Set Region number */
+  WRITE_REG(MPU->RNR, Region);
+  /* Set base address */
+  WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
+  /* Configure MPU */
+  WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | (SubRegionDisable << MPU_RASR_SRD_Pos)));
+}
+
+/**
+  * @brief  Disable a region
+  * @rmtoll MPU_RNR      REGION        LL_MPU_DisableRegion\n
+  *         MPU_RASR     ENABLE        LL_MPU_DisableRegion
+  * @param  Region This parameter can be one of the following values:
+  *         @arg @ref LL_MPU_REGION_NUMBER0
+  *         @arg @ref LL_MPU_REGION_NUMBER1
+  *         @arg @ref LL_MPU_REGION_NUMBER2
+  *         @arg @ref LL_MPU_REGION_NUMBER3
+  *         @arg @ref LL_MPU_REGION_NUMBER4
+  *         @arg @ref LL_MPU_REGION_NUMBER5
+  *         @arg @ref LL_MPU_REGION_NUMBER6
+  *         @arg @ref LL_MPU_REGION_NUMBER7
+  *         @arg @ref LL_MPU_REGION_NUMBER8
+  *         @arg @ref LL_MPU_REGION_NUMBER9
+  *         @arg @ref LL_MPU_REGION_NUMBER10
+  *         @arg @ref LL_MPU_REGION_NUMBER11
+  *         @arg @ref LL_MPU_REGION_NUMBER12
+  *         @arg @ref LL_MPU_REGION_NUMBER13
+  *         @arg @ref LL_MPU_REGION_NUMBER14
+  *         @arg @ref LL_MPU_REGION_NUMBER15
+  * @note   For cortex-M4 only 8 regions are available i.e only values from LL_MPU_REGION_NUMBER0 to LL_MPU_REGION_NUMBER7 are possible.
+  * @retval None
+  */
+__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
+{
+  /* Set Region number */
+  WRITE_REG(MPU->RNR, Region);
+  /* Disable the MPU region */
+  CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
+}
+
+/**
+  * @}
+  */
+
+#endif /* __MPU_PRESENT */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_LL_CORTEX_H */
+
diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_crs.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_crs.h
index 86ce8478..0b2206fc 100644
--- a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_crs.h
+++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_crs.h
@@ -1,780 +1,780 @@
-/**
-  ******************************************************************************
-  * @file    stm32h7xx_ll_crs.h
-  * @author  MCD Application Team
-  * @brief   Header file of CRS LL module.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32H7xx_LL_CRS_H
-#define STM32H7xx_LL_CRS_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx.h"
-
-/** @addtogroup STM32H7xx_LL_Driver
-  * @{
-  */
-
-#if defined(CRS)
-
-/** @defgroup CRS_LL CRS
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup CRS_LL_Exported_Constants CRS Exported Constants
-  * @{
-  */
-
-/** @defgroup CRS_LL_EC_GET_FLAG Get Flags Defines
-  * @brief    Flags defines which can be used with LL_CRS_ReadReg function
-  * @{
-  */
-#define LL_CRS_ISR_SYNCOKF                 CRS_ISR_SYNCOKF
-#define LL_CRS_ISR_SYNCWARNF               CRS_ISR_SYNCWARNF
-#define LL_CRS_ISR_ERRF                    CRS_ISR_ERRF
-#define LL_CRS_ISR_ESYNCF                  CRS_ISR_ESYNCF
-#define LL_CRS_ISR_SYNCERR                 CRS_ISR_SYNCERR
-#define LL_CRS_ISR_SYNCMISS                CRS_ISR_SYNCMISS
-#define LL_CRS_ISR_TRIMOVF                 CRS_ISR_TRIMOVF
-/**
-  * @}
-  */
-
-/** @defgroup CRS_LL_EC_IT IT Defines
-  * @brief    IT defines which can be used with LL_CRS_ReadReg and  LL_CRS_WriteReg functions
-  * @{
-  */
-#define LL_CRS_CR_SYNCOKIE                 CRS_CR_SYNCOKIE
-#define LL_CRS_CR_SYNCWARNIE               CRS_CR_SYNCWARNIE
-#define LL_CRS_CR_ERRIE                    CRS_CR_ERRIE
-#define LL_CRS_CR_ESYNCIE                  CRS_CR_ESYNCIE
-/**
-  * @}
-  */
-
-/** @defgroup CRS_LL_EC_SYNC_DIV Synchronization Signal Divider
-  * @{
-  */
-#define LL_CRS_SYNC_DIV_1                  0x00000000U                               /*!< Synchro Signal not divided (default) */
-#define LL_CRS_SYNC_DIV_2                  CRS_CFGR_SYNCDIV_0                        /*!< Synchro Signal divided by 2 */
-#define LL_CRS_SYNC_DIV_4                  CRS_CFGR_SYNCDIV_1                        /*!< Synchro Signal divided by 4 */
-#define LL_CRS_SYNC_DIV_8                  (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
-#define LL_CRS_SYNC_DIV_16                 CRS_CFGR_SYNCDIV_2                        /*!< Synchro Signal divided by 16 */
-#define LL_CRS_SYNC_DIV_32                 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
-#define LL_CRS_SYNC_DIV_64                 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
-#define LL_CRS_SYNC_DIV_128                CRS_CFGR_SYNCDIV                          /*!< Synchro Signal divided by 128 */
-/**
-  * @}
-  */
-
-/** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source
-  * @{
-  */
-#define LL_CRS_SYNC_SOURCE_GPIO            0x00000000U             /*!< Synchro Signal source GPIO */
-#define LL_CRS_SYNC_SOURCE_LSE             CRS_CFGR_SYNCSRC_0      /*!< Synchro Signal source LSE */
-#define LL_CRS_SYNC_SOURCE_USB             CRS_CFGR_SYNCSRC_1      /*!< Synchro Signal source USB SOF (default)*/
-/**
-  * @}
-  */
-
-/** @defgroup CRS_LL_EC_SYNC_POLARITY Synchronization Signal Polarity
-  * @{
-  */
-#define LL_CRS_SYNC_POLARITY_RISING        0x00000000U           /*!< Synchro Active on rising edge (default) */
-#define LL_CRS_SYNC_POLARITY_FALLING       CRS_CFGR_SYNCPOL      /*!< Synchro Active on falling edge */
-/**
-  * @}
-  */
-
-/** @defgroup CRS_LL_EC_FREQERRORDIR Frequency Error Direction
-  * @{
-  */
-#define LL_CRS_FREQ_ERROR_DIR_UP           0x00000000U         /*!< Upcounting direction, the actual frequency is above the target */
-#define LL_CRS_FREQ_ERROR_DIR_DOWN         CRS_ISR_FEDIR       /*!< Downcounting direction, the actual frequency is below the target */
-/**
-  * @}
-  */
-
-/** @defgroup CRS_LL_EC_DEFAULTVALUES Default Values
-  * @{
-  */
-/**
-  * @brief Reset value of the RELOAD field
-  * @note The reset value of the RELOAD field corresponds to a target frequency of 48 MHz
-  *       and a synchronization signal frequency of 1 kHz (SOF signal from USB)
-  */
-#define LL_CRS_RELOADVALUE_DEFAULT         0x0000BB7FU
-
-/**
-  * @brief Reset value of Frequency error limit.
-  */
-#define LL_CRS_ERRORLIMIT_DEFAULT          0x00000022U
-
-/**
-  * @brief Reset value of the HSI48 Calibration field
-  * @note The default value is 64, which corresponds to the middle of the trimming interval.
-  *       The trimming step is specified in the product datasheet.
-  *       A higher TRIM value corresponds to a higher output frequency.
-  */
-#define LL_CRS_HSI48CALIBRATION_DEFAULT    0x00000020U
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup CRS_LL_Exported_Macros CRS Exported Macros
-  * @{
-  */
-
-/** @defgroup CRS_LL_EM_WRITE_READ Common Write and read registers Macros
-  * @{
-  */
-
-/**
-  * @brief  Write a value in CRS register
-  * @param  __INSTANCE__ CRS Instance
-  * @param  __REG__ Register to be written
-  * @param  __VALUE__ Value to be written in the register
-  * @retval None
-  */
-#define LL_CRS_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
-  * @brief  Read a value in CRS register
-  * @param  __INSTANCE__ CRS Instance
-  * @param  __REG__ Register to be read
-  * @retval Register value
-  */
-#define LL_CRS_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
-  * @}
-  */
-
-/** @defgroup CRS_LL_EM_Exported_Macros_Calculate_Reload Exported_Macros_Calculate_Reload
-  * @{
-  */
-
-/**
-  * @brief  Macro to calculate reload value to be set in CRS register according to target and sync frequencies
-  * @note   The RELOAD value should be selected according to the ratio between
-  *         the target frequency and the frequency of the synchronization source after
-  *         prescaling. It is then decreased by one in order to reach the expected
-  *         synchronization on the zero value. The formula is the following:
-  *              RELOAD = (fTARGET / fSYNC) -1
-  * @param  __FTARGET__ Target frequency (value in Hz)
-  * @param  __FSYNC__ Synchronization signal frequency (value in Hz)
-  * @retval Reload value (in Hz)
-  */
-#define __LL_CRS_CALC_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup CRS_LL_Exported_Functions CRS Exported Functions
-  * @{
-  */
-
-/** @defgroup CRS_LL_EF_Configuration Configuration
-  * @{
-  */
-
-/**
-  * @brief  Enable Frequency error counter
-  * @note When this bit is set, the CRS_CFGR register is write-protected and cannot be modified
-  * @rmtoll CR           CEN           LL_CRS_EnableFreqErrorCounter
-  * @retval None
-  */
-__STATIC_INLINE void LL_CRS_EnableFreqErrorCounter(void)
-{
-  SET_BIT(CRS->CR, CRS_CR_CEN);
-}
-
-/**
-  * @brief  Disable Frequency error counter
-  * @rmtoll CR           CEN           LL_CRS_DisableFreqErrorCounter
-  * @retval None
-  */
-__STATIC_INLINE void LL_CRS_DisableFreqErrorCounter(void)
-{
-  CLEAR_BIT(CRS->CR, CRS_CR_CEN);
-}
-
-/**
-  * @brief  Check if Frequency error counter is enabled or not
-  * @rmtoll CR           CEN           LL_CRS_IsEnabledFreqErrorCounter
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_CRS_IsEnabledFreqErrorCounter(void)
-{
-  return ((READ_BIT(CRS->CR, CRS_CR_CEN) == (CRS_CR_CEN)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable Automatic trimming counter
-  * @rmtoll CR           AUTOTRIMEN    LL_CRS_EnableAutoTrimming
-  * @retval None
-  */
-__STATIC_INLINE void LL_CRS_EnableAutoTrimming(void)
-{
-  SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
-}
-
-/**
-  * @brief  Disable Automatic trimming counter
-  * @rmtoll CR           AUTOTRIMEN    LL_CRS_DisableAutoTrimming
-  * @retval None
-  */
-__STATIC_INLINE void LL_CRS_DisableAutoTrimming(void)
-{
-  CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
-}
-
-/**
-  * @brief  Check if Automatic trimming is enabled or not
-  * @rmtoll CR           AUTOTRIMEN    LL_CRS_IsEnabledAutoTrimming
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming(void)
-{
-  return ((READ_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) == (CRS_CR_AUTOTRIMEN)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Set HSI48 oscillator smooth trimming
-  * @note   When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only
-  * @rmtoll CR           TRIM          LL_CRS_SetHSI48SmoothTrimming
-  * @param  Value a number between Min_Data = 0 and Max_Data = 127
-  * @note   Default value can be set thanks to @ref LL_CRS_HSI48CALIBRATION_DEFAULT
-  * @retval None
-  */
-__STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value)
-{
-  MODIFY_REG(CRS->CR, CRS_CR_TRIM, Value << CRS_CR_TRIM_Pos);
-}
-
-/**
-  * @brief  Get HSI48 oscillator smooth trimming
-  * @rmtoll CR           TRIM          LL_CRS_GetHSI48SmoothTrimming
-  * @retval a number between Min_Data = 0 and Max_Data = 127
-  */
-__STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming(void)
-{
-  return (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos);
-}
-
-/**
-  * @brief  Set counter reload value
-  * @rmtoll CFGR         RELOAD        LL_CRS_SetReloadCounter
-  * @param  Value a number between Min_Data = 0 and Max_Data = 0xFFFF
-  * @note   Default value can be set thanks to @ref LL_CRS_RELOADVALUE_DEFAULT
-  *         Otherwise it can be calculated in using macro @ref __LL_CRS_CALC_CALCULATE_RELOADVALUE (_FTARGET_, _FSYNC_)
-  * @retval None
-  */
-__STATIC_INLINE void LL_CRS_SetReloadCounter(uint32_t Value)
-{
-  MODIFY_REG(CRS->CFGR, CRS_CFGR_RELOAD, Value);
-}
-
-/**
-  * @brief  Get counter reload value
-  * @rmtoll CFGR         RELOAD        LL_CRS_GetReloadCounter
-  * @retval a number between Min_Data = 0 and Max_Data = 0xFFFF
-  */
-__STATIC_INLINE uint32_t LL_CRS_GetReloadCounter(void)
-{
-  return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
-}
-
-/**
-  * @brief  Set frequency error limit
-  * @rmtoll CFGR         FELIM         LL_CRS_SetFreqErrorLimit
-  * @param  Value a number between Min_Data = 0 and Max_Data = 255
-  * @note   Default value can be set thanks to @ref LL_CRS_ERRORLIMIT_DEFAULT
-  * @retval None
-  */
-__STATIC_INLINE void LL_CRS_SetFreqErrorLimit(uint32_t Value)
-{
-  MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_CFGR_FELIM_Pos);
-}
-
-/**
-  * @brief  Get frequency error limit
-  * @rmtoll CFGR         FELIM         LL_CRS_GetFreqErrorLimit
-  * @retval A number between Min_Data = 0 and Max_Data = 255
-  */
-__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorLimit(void)
-{
-  return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_CFGR_FELIM_Pos);
-}
-
-/**
-  * @brief  Set division factor for SYNC signal
-  * @rmtoll CFGR         SYNCDIV       LL_CRS_SetSyncDivider
-  * @param  Divider This parameter can be one of the following values:
-  *         @arg @ref LL_CRS_SYNC_DIV_1
-  *         @arg @ref LL_CRS_SYNC_DIV_2
-  *         @arg @ref LL_CRS_SYNC_DIV_4
-  *         @arg @ref LL_CRS_SYNC_DIV_8
-  *         @arg @ref LL_CRS_SYNC_DIV_16
-  *         @arg @ref LL_CRS_SYNC_DIV_32
-  *         @arg @ref LL_CRS_SYNC_DIV_64
-  *         @arg @ref LL_CRS_SYNC_DIV_128
-  * @retval None
-  */
-__STATIC_INLINE void LL_CRS_SetSyncDivider(uint32_t Divider)
-{
-  MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCDIV, Divider);
-}
-
-/**
-  * @brief  Get division factor for SYNC signal
-  * @rmtoll CFGR         SYNCDIV       LL_CRS_GetSyncDivider
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_CRS_SYNC_DIV_1
-  *         @arg @ref LL_CRS_SYNC_DIV_2
-  *         @arg @ref LL_CRS_SYNC_DIV_4
-  *         @arg @ref LL_CRS_SYNC_DIV_8
-  *         @arg @ref LL_CRS_SYNC_DIV_16
-  *         @arg @ref LL_CRS_SYNC_DIV_32
-  *         @arg @ref LL_CRS_SYNC_DIV_64
-  *         @arg @ref LL_CRS_SYNC_DIV_128
-  */
-__STATIC_INLINE uint32_t LL_CRS_GetSyncDivider(void)
-{
-  return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCDIV));
-}
-
-/**
-  * @brief  Set SYNC signal source
-  * @rmtoll CFGR         SYNCSRC       LL_CRS_SetSyncSignalSource
-  * @param  Source This parameter can be one of the following values:
-  *         @arg @ref LL_CRS_SYNC_SOURCE_GPIO
-  *         @arg @ref LL_CRS_SYNC_SOURCE_LSE
-  *         @arg @ref LL_CRS_SYNC_SOURCE_USB
-  * @retval None
-  */
-__STATIC_INLINE void LL_CRS_SetSyncSignalSource(uint32_t Source)
-{
-  MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCSRC, Source);
-}
-
-/**
-  * @brief  Get SYNC signal source
-  * @rmtoll CFGR         SYNCSRC       LL_CRS_GetSyncSignalSource
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_CRS_SYNC_SOURCE_GPIO
-  *         @arg @ref LL_CRS_SYNC_SOURCE_LSE
-  *         @arg @ref LL_CRS_SYNC_SOURCE_USB
-  */
-__STATIC_INLINE uint32_t LL_CRS_GetSyncSignalSource(void)
-{
-  return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCSRC));
-}
-
-/**
-  * @brief  Set input polarity for the SYNC signal source
-  * @rmtoll CFGR         SYNCPOL       LL_CRS_SetSyncPolarity
-  * @param  Polarity This parameter can be one of the following values:
-  *         @arg @ref LL_CRS_SYNC_POLARITY_RISING
-  *         @arg @ref LL_CRS_SYNC_POLARITY_FALLING
-  * @retval None
-  */
-__STATIC_INLINE void LL_CRS_SetSyncPolarity(uint32_t Polarity)
-{
-  MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCPOL, Polarity);
-}
-
-/**
-  * @brief  Get input polarity for the SYNC signal source
-  * @rmtoll CFGR         SYNCPOL       LL_CRS_GetSyncPolarity
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_CRS_SYNC_POLARITY_RISING
-  *         @arg @ref LL_CRS_SYNC_POLARITY_FALLING
-  */
-__STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void)
-{
-  return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCPOL));
-}
-
-/**
-  * @brief  Configure CRS for the synchronization
-  * @rmtoll CR           TRIM          LL_CRS_ConfigSynchronization\n
-  *         CFGR         RELOAD        LL_CRS_ConfigSynchronization\n
-  *         CFGR         FELIM         LL_CRS_ConfigSynchronization\n
-  *         CFGR         SYNCDIV       LL_CRS_ConfigSynchronization\n
-  *         CFGR         SYNCSRC       LL_CRS_ConfigSynchronization\n
-  *         CFGR         SYNCPOL       LL_CRS_ConfigSynchronization
-  * @param  HSI48CalibrationValue a number between Min_Data = 0 and Max_Data = 63
-  * @param  ErrorLimitValue a number between Min_Data = 0 and Max_Data = 0xFFFF
-  * @param  ReloadValue a number between Min_Data = 0 and Max_Data = 255
-  * @param  Settings This parameter can be a combination of the following values:
-  *         @arg @ref LL_CRS_SYNC_DIV_1 or @ref LL_CRS_SYNC_DIV_2 or @ref LL_CRS_SYNC_DIV_4 or @ref LL_CRS_SYNC_DIV_8
-  *              or @ref LL_CRS_SYNC_DIV_16 or @ref LL_CRS_SYNC_DIV_32 or @ref LL_CRS_SYNC_DIV_64 or @ref LL_CRS_SYNC_DIV_128
-  *         @arg @ref LL_CRS_SYNC_SOURCE_GPIO or @ref LL_CRS_SYNC_SOURCE_LSE or @ref LL_CRS_SYNC_SOURCE_USB
-  *         @arg @ref LL_CRS_SYNC_POLARITY_RISING or @ref LL_CRS_SYNC_POLARITY_FALLING
-  * @retval None
-  */
-__STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue, uint32_t ReloadValue, uint32_t Settings)
-{
-  MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue);
-  MODIFY_REG(CRS->CFGR,
-             CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL,
-             ReloadValue | (ErrorLimitValue << CRS_CFGR_FELIM_Pos) | Settings);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup CRS_LL_EF_CRS_Management CRS_Management
-  * @{
-  */
-
-/**
-  * @brief  Generate software SYNC event
-  * @rmtoll CR           SWSYNC        LL_CRS_GenerateEvent_SWSYNC
-  * @retval None
-  */
-__STATIC_INLINE void LL_CRS_GenerateEvent_SWSYNC(void)
-{
-  SET_BIT(CRS->CR, CRS_CR_SWSYNC);
-}
-
-/**
-  * @brief  Get the frequency error direction latched in the time of the last
-  * SYNC event
-  * @rmtoll ISR          FEDIR         LL_CRS_GetFreqErrorDirection
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_CRS_FREQ_ERROR_DIR_UP
-  *         @arg @ref LL_CRS_FREQ_ERROR_DIR_DOWN
-  */
-__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorDirection(void)
-{
-  return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
-}
-
-/**
-  * @brief  Get the frequency error counter value latched in the time of the last SYNC event
-  * @rmtoll ISR          FECAP         LL_CRS_GetFreqErrorCapture
-  * @retval A number between Min_Data = 0x0000 and Max_Data = 0xFFFF
-  */
-__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorCapture(void)
-{
-  return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup CRS_LL_EF_FLAG_Management FLAG_Management
-  * @{
-  */
-
-/**
-  * @brief  Check if SYNC event OK signal occurred or not
-  * @rmtoll ISR          SYNCOKF       LL_CRS_IsActiveFlag_SYNCOK
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCOK(void)
-{
-  return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCOKF) == (CRS_ISR_SYNCOKF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if SYNC warning signal occurred or not
-  * @rmtoll ISR          SYNCWARNF     LL_CRS_IsActiveFlag_SYNCWARN
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCWARN(void)
-{
-  return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCWARNF) == (CRS_ISR_SYNCWARNF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if Synchronization or trimming error signal occurred or not
-  * @rmtoll ISR          ERRF          LL_CRS_IsActiveFlag_ERR
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ERR(void)
-{
-  return ((READ_BIT(CRS->ISR, CRS_ISR_ERRF) == (CRS_ISR_ERRF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if Expected SYNC signal occurred or not
-  * @rmtoll ISR          ESYNCF        LL_CRS_IsActiveFlag_ESYNC
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ESYNC(void)
-{
-  return ((READ_BIT(CRS->ISR, CRS_ISR_ESYNCF) == (CRS_ISR_ESYNCF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if SYNC error signal occurred or not
-  * @rmtoll ISR          SYNCERR       LL_CRS_IsActiveFlag_SYNCERR
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCERR(void)
-{
-  return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCERR) == (CRS_ISR_SYNCERR)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if SYNC missed error signal occurred or not
-  * @rmtoll ISR          SYNCMISS      LL_CRS_IsActiveFlag_SYNCMISS
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCMISS(void)
-{
-  return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCMISS) == (CRS_ISR_SYNCMISS)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if Trimming overflow or underflow occurred or not
-  * @rmtoll ISR          TRIMOVF       LL_CRS_IsActiveFlag_TRIMOVF
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_TRIMOVF(void)
-{
-  return ((READ_BIT(CRS->ISR, CRS_ISR_TRIMOVF) == (CRS_ISR_TRIMOVF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear the SYNC event OK flag
-  * @rmtoll ICR          SYNCOKC       LL_CRS_ClearFlag_SYNCOK
-  * @retval None
-  */
-__STATIC_INLINE void LL_CRS_ClearFlag_SYNCOK(void)
-{
-  WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
-}
-
-/**
-  * @brief  Clear the  SYNC warning flag
-  * @rmtoll ICR          SYNCWARNC     LL_CRS_ClearFlag_SYNCWARN
-  * @retval None
-  */
-__STATIC_INLINE void LL_CRS_ClearFlag_SYNCWARN(void)
-{
-  WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
-}
-
-/**
-  * @brief  Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also
-  * the ERR flag
-  * @rmtoll ICR          ERRC          LL_CRS_ClearFlag_ERR
-  * @retval None
-  */
-__STATIC_INLINE void LL_CRS_ClearFlag_ERR(void)
-{
-  WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
-}
-
-/**
-  * @brief  Clear Expected SYNC flag
-  * @rmtoll ICR          ESYNCC        LL_CRS_ClearFlag_ESYNC
-  * @retval None
-  */
-__STATIC_INLINE void LL_CRS_ClearFlag_ESYNC(void)
-{
-  WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup CRS_LL_EF_IT_Management IT_Management
-  * @{
-  */
-
-/**
-  * @brief  Enable SYNC event OK interrupt
-  * @rmtoll CR           SYNCOKIE      LL_CRS_EnableIT_SYNCOK
-  * @retval None
-  */
-__STATIC_INLINE void LL_CRS_EnableIT_SYNCOK(void)
-{
-  SET_BIT(CRS->CR, CRS_CR_SYNCOKIE);
-}
-
-/**
-  * @brief  Disable SYNC event OK interrupt
-  * @rmtoll CR           SYNCOKIE      LL_CRS_DisableIT_SYNCOK
-  * @retval None
-  */
-__STATIC_INLINE void LL_CRS_DisableIT_SYNCOK(void)
-{
-  CLEAR_BIT(CRS->CR, CRS_CR_SYNCOKIE);
-}
-
-/**
-  * @brief  Check if SYNC event OK interrupt is enabled or not
-  * @rmtoll CR           SYNCOKIE      LL_CRS_IsEnabledIT_SYNCOK
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCOK(void)
-{
-  return ((READ_BIT(CRS->CR, CRS_CR_SYNCOKIE) == (CRS_CR_SYNCOKIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable SYNC warning interrupt
-  * @rmtoll CR           SYNCWARNIE    LL_CRS_EnableIT_SYNCWARN
-  * @retval None
-  */
-__STATIC_INLINE void LL_CRS_EnableIT_SYNCWARN(void)
-{
-  SET_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
-}
-
-/**
-  * @brief  Disable SYNC warning interrupt
-  * @rmtoll CR           SYNCWARNIE    LL_CRS_DisableIT_SYNCWARN
-  * @retval None
-  */
-__STATIC_INLINE void LL_CRS_DisableIT_SYNCWARN(void)
-{
-  CLEAR_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
-}
-
-/**
-  * @brief  Check if SYNC warning interrupt is enabled or not
-  * @rmtoll CR           SYNCWARNIE    LL_CRS_IsEnabledIT_SYNCWARN
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCWARN(void)
-{
-  return ((READ_BIT(CRS->CR, CRS_CR_SYNCWARNIE) == (CRS_CR_SYNCWARNIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable Synchronization or trimming error interrupt
-  * @rmtoll CR           ERRIE         LL_CRS_EnableIT_ERR
-  * @retval None
-  */
-__STATIC_INLINE void LL_CRS_EnableIT_ERR(void)
-{
-  SET_BIT(CRS->CR, CRS_CR_ERRIE);
-}
-
-/**
-  * @brief  Disable Synchronization or trimming error interrupt
-  * @rmtoll CR           ERRIE         LL_CRS_DisableIT_ERR
-  * @retval None
-  */
-__STATIC_INLINE void LL_CRS_DisableIT_ERR(void)
-{
-  CLEAR_BIT(CRS->CR, CRS_CR_ERRIE);
-}
-
-/**
-  * @brief  Check if Synchronization or trimming error interrupt is enabled or not
-  * @rmtoll CR           ERRIE         LL_CRS_IsEnabledIT_ERR
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ERR(void)
-{
-  return ((READ_BIT(CRS->CR, CRS_CR_ERRIE) == (CRS_CR_ERRIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable Expected SYNC interrupt
-  * @rmtoll CR           ESYNCIE       LL_CRS_EnableIT_ESYNC
-  * @retval None
-  */
-__STATIC_INLINE void LL_CRS_EnableIT_ESYNC(void)
-{
-  SET_BIT(CRS->CR, CRS_CR_ESYNCIE);
-}
-
-/**
-  * @brief  Disable Expected SYNC interrupt
-  * @rmtoll CR           ESYNCIE       LL_CRS_DisableIT_ESYNC
-  * @retval None
-  */
-__STATIC_INLINE void LL_CRS_DisableIT_ESYNC(void)
-{
-  CLEAR_BIT(CRS->CR, CRS_CR_ESYNCIE);
-}
-
-/**
-  * @brief  Check if Expected SYNC interrupt is enabled or not
-  * @rmtoll CR           ESYNCIE       LL_CRS_IsEnabledIT_ESYNC
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ESYNC(void)
-{
-  return ((READ_BIT(CRS->CR, CRS_CR_ESYNCIE) == (CRS_CR_ESYNCIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup CRS_LL_EF_Init Initialization and de-initialization functions
-  * @{
-  */
-
-ErrorStatus LL_CRS_DeInit(void);
-
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* defined(CRS) */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32H7xx_LL_CRS_H */
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_ll_crs.h
+  * @author  MCD Application Team
+  * @brief   Header file of CRS LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_LL_CRS_H
+#define STM32H7xx_LL_CRS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx.h"
+
+/** @addtogroup STM32H7xx_LL_Driver
+  * @{
+  */
+
+#if defined(CRS)
+
+/** @defgroup CRS_LL CRS
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CRS_LL_Exported_Constants CRS Exported Constants
+  * @{
+  */
+
+/** @defgroup CRS_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_CRS_ReadReg function
+  * @{
+  */
+#define LL_CRS_ISR_SYNCOKF                 CRS_ISR_SYNCOKF
+#define LL_CRS_ISR_SYNCWARNF               CRS_ISR_SYNCWARNF
+#define LL_CRS_ISR_ERRF                    CRS_ISR_ERRF
+#define LL_CRS_ISR_ESYNCF                  CRS_ISR_ESYNCF
+#define LL_CRS_ISR_SYNCERR                 CRS_ISR_SYNCERR
+#define LL_CRS_ISR_SYNCMISS                CRS_ISR_SYNCMISS
+#define LL_CRS_ISR_TRIMOVF                 CRS_ISR_TRIMOVF
+/**
+  * @}
+  */
+
+/** @defgroup CRS_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_CRS_ReadReg and  LL_CRS_WriteReg functions
+  * @{
+  */
+#define LL_CRS_CR_SYNCOKIE                 CRS_CR_SYNCOKIE
+#define LL_CRS_CR_SYNCWARNIE               CRS_CR_SYNCWARNIE
+#define LL_CRS_CR_ERRIE                    CRS_CR_ERRIE
+#define LL_CRS_CR_ESYNCIE                  CRS_CR_ESYNCIE
+/**
+  * @}
+  */
+
+/** @defgroup CRS_LL_EC_SYNC_DIV Synchronization Signal Divider
+  * @{
+  */
+#define LL_CRS_SYNC_DIV_1                  0x00000000U                               /*!< Synchro Signal not divided (default) */
+#define LL_CRS_SYNC_DIV_2                  CRS_CFGR_SYNCDIV_0                        /*!< Synchro Signal divided by 2 */
+#define LL_CRS_SYNC_DIV_4                  CRS_CFGR_SYNCDIV_1                        /*!< Synchro Signal divided by 4 */
+#define LL_CRS_SYNC_DIV_8                  (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
+#define LL_CRS_SYNC_DIV_16                 CRS_CFGR_SYNCDIV_2                        /*!< Synchro Signal divided by 16 */
+#define LL_CRS_SYNC_DIV_32                 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
+#define LL_CRS_SYNC_DIV_64                 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
+#define LL_CRS_SYNC_DIV_128                CRS_CFGR_SYNCDIV                          /*!< Synchro Signal divided by 128 */
+/**
+  * @}
+  */
+
+/** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source
+  * @{
+  */
+#define LL_CRS_SYNC_SOURCE_GPIO            0x00000000U             /*!< Synchro Signal source GPIO */
+#define LL_CRS_SYNC_SOURCE_LSE             CRS_CFGR_SYNCSRC_0      /*!< Synchro Signal source LSE */
+#define LL_CRS_SYNC_SOURCE_USB             CRS_CFGR_SYNCSRC_1      /*!< Synchro Signal source USB SOF (default)*/
+/**
+  * @}
+  */
+
+/** @defgroup CRS_LL_EC_SYNC_POLARITY Synchronization Signal Polarity
+  * @{
+  */
+#define LL_CRS_SYNC_POLARITY_RISING        0x00000000U           /*!< Synchro Active on rising edge (default) */
+#define LL_CRS_SYNC_POLARITY_FALLING       CRS_CFGR_SYNCPOL      /*!< Synchro Active on falling edge */
+/**
+  * @}
+  */
+
+/** @defgroup CRS_LL_EC_FREQERRORDIR Frequency Error Direction
+  * @{
+  */
+#define LL_CRS_FREQ_ERROR_DIR_UP           0x00000000U         /*!< Upcounting direction, the actual frequency is above the target */
+#define LL_CRS_FREQ_ERROR_DIR_DOWN         CRS_ISR_FEDIR       /*!< Downcounting direction, the actual frequency is below the target */
+/**
+  * @}
+  */
+
+/** @defgroup CRS_LL_EC_DEFAULTVALUES Default Values
+  * @{
+  */
+/**
+  * @brief Reset value of the RELOAD field
+  * @note The reset value of the RELOAD field corresponds to a target frequency of 48 MHz
+  *       and a synchronization signal frequency of 1 kHz (SOF signal from USB)
+  */
+#define LL_CRS_RELOADVALUE_DEFAULT         0x0000BB7FU
+
+/**
+  * @brief Reset value of Frequency error limit.
+  */
+#define LL_CRS_ERRORLIMIT_DEFAULT          0x00000022U
+
+/**
+  * @brief Reset value of the HSI48 Calibration field
+  * @note The default value is 64, which corresponds to the middle of the trimming interval.
+  *       The trimming step is specified in the product datasheet.
+  *       A higher TRIM value corresponds to a higher output frequency.
+  */
+#define LL_CRS_HSI48CALIBRATION_DEFAULT    0x00000020U
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup CRS_LL_Exported_Macros CRS Exported Macros
+  * @{
+  */
+
+/** @defgroup CRS_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in CRS register
+  * @param  __INSTANCE__ CRS Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_CRS_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in CRS register
+  * @param  __INSTANCE__ CRS Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_CRS_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/** @defgroup CRS_LL_EM_Exported_Macros_Calculate_Reload Exported_Macros_Calculate_Reload
+  * @{
+  */
+
+/**
+  * @brief  Macro to calculate reload value to be set in CRS register according to target and sync frequencies
+  * @note   The RELOAD value should be selected according to the ratio between
+  *         the target frequency and the frequency of the synchronization source after
+  *         prescaling. It is then decreased by one in order to reach the expected
+  *         synchronization on the zero value. The formula is the following:
+  *              RELOAD = (fTARGET / fSYNC) -1
+  * @param  __FTARGET__ Target frequency (value in Hz)
+  * @param  __FSYNC__ Synchronization signal frequency (value in Hz)
+  * @retval Reload value (in Hz)
+  */
+#define __LL_CRS_CALC_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CRS_LL_Exported_Functions CRS Exported Functions
+  * @{
+  */
+
+/** @defgroup CRS_LL_EF_Configuration Configuration
+  * @{
+  */
+
+/**
+  * @brief  Enable Frequency error counter
+  * @note When this bit is set, the CRS_CFGR register is write-protected and cannot be modified
+  * @rmtoll CR           CEN           LL_CRS_EnableFreqErrorCounter
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_EnableFreqErrorCounter(void)
+{
+  SET_BIT(CRS->CR, CRS_CR_CEN);
+}
+
+/**
+  * @brief  Disable Frequency error counter
+  * @rmtoll CR           CEN           LL_CRS_DisableFreqErrorCounter
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_DisableFreqErrorCounter(void)
+{
+  CLEAR_BIT(CRS->CR, CRS_CR_CEN);
+}
+
+/**
+  * @brief  Check if Frequency error counter is enabled or not
+  * @rmtoll CR           CEN           LL_CRS_IsEnabledFreqErrorCounter
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsEnabledFreqErrorCounter(void)
+{
+  return ((READ_BIT(CRS->CR, CRS_CR_CEN) == (CRS_CR_CEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Automatic trimming counter
+  * @rmtoll CR           AUTOTRIMEN    LL_CRS_EnableAutoTrimming
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_EnableAutoTrimming(void)
+{
+  SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
+}
+
+/**
+  * @brief  Disable Automatic trimming counter
+  * @rmtoll CR           AUTOTRIMEN    LL_CRS_DisableAutoTrimming
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_DisableAutoTrimming(void)
+{
+  CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
+}
+
+/**
+  * @brief  Check if Automatic trimming is enabled or not
+  * @rmtoll CR           AUTOTRIMEN    LL_CRS_IsEnabledAutoTrimming
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming(void)
+{
+  return ((READ_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) == (CRS_CR_AUTOTRIMEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set HSI48 oscillator smooth trimming
+  * @note   When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only
+  * @rmtoll CR           TRIM          LL_CRS_SetHSI48SmoothTrimming
+  * @param  Value a number between Min_Data = 0 and Max_Data = 127
+  * @note   Default value can be set thanks to @ref LL_CRS_HSI48CALIBRATION_DEFAULT
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value)
+{
+  MODIFY_REG(CRS->CR, CRS_CR_TRIM, Value << CRS_CR_TRIM_Pos);
+}
+
+/**
+  * @brief  Get HSI48 oscillator smooth trimming
+  * @rmtoll CR           TRIM          LL_CRS_GetHSI48SmoothTrimming
+  * @retval a number between Min_Data = 0 and Max_Data = 127
+  */
+__STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming(void)
+{
+  return (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos);
+}
+
+/**
+  * @brief  Set counter reload value
+  * @rmtoll CFGR         RELOAD        LL_CRS_SetReloadCounter
+  * @param  Value a number between Min_Data = 0 and Max_Data = 0xFFFF
+  * @note   Default value can be set thanks to @ref LL_CRS_RELOADVALUE_DEFAULT
+  *         Otherwise it can be calculated in using macro @ref __LL_CRS_CALC_CALCULATE_RELOADVALUE (_FTARGET_, _FSYNC_)
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_SetReloadCounter(uint32_t Value)
+{
+  MODIFY_REG(CRS->CFGR, CRS_CFGR_RELOAD, Value);
+}
+
+/**
+  * @brief  Get counter reload value
+  * @rmtoll CFGR         RELOAD        LL_CRS_GetReloadCounter
+  * @retval a number between Min_Data = 0 and Max_Data = 0xFFFF
+  */
+__STATIC_INLINE uint32_t LL_CRS_GetReloadCounter(void)
+{
+  return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
+}
+
+/**
+  * @brief  Set frequency error limit
+  * @rmtoll CFGR         FELIM         LL_CRS_SetFreqErrorLimit
+  * @param  Value a number between Min_Data = 0 and Max_Data = 255
+  * @note   Default value can be set thanks to @ref LL_CRS_ERRORLIMIT_DEFAULT
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_SetFreqErrorLimit(uint32_t Value)
+{
+  MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_CFGR_FELIM_Pos);
+}
+
+/**
+  * @brief  Get frequency error limit
+  * @rmtoll CFGR         FELIM         LL_CRS_GetFreqErrorLimit
+  * @retval A number between Min_Data = 0 and Max_Data = 255
+  */
+__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorLimit(void)
+{
+  return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_CFGR_FELIM_Pos);
+}
+
+/**
+  * @brief  Set division factor for SYNC signal
+  * @rmtoll CFGR         SYNCDIV       LL_CRS_SetSyncDivider
+  * @param  Divider This parameter can be one of the following values:
+  *         @arg @ref LL_CRS_SYNC_DIV_1
+  *         @arg @ref LL_CRS_SYNC_DIV_2
+  *         @arg @ref LL_CRS_SYNC_DIV_4
+  *         @arg @ref LL_CRS_SYNC_DIV_8
+  *         @arg @ref LL_CRS_SYNC_DIV_16
+  *         @arg @ref LL_CRS_SYNC_DIV_32
+  *         @arg @ref LL_CRS_SYNC_DIV_64
+  *         @arg @ref LL_CRS_SYNC_DIV_128
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_SetSyncDivider(uint32_t Divider)
+{
+  MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCDIV, Divider);
+}
+
+/**
+  * @brief  Get division factor for SYNC signal
+  * @rmtoll CFGR         SYNCDIV       LL_CRS_GetSyncDivider
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_CRS_SYNC_DIV_1
+  *         @arg @ref LL_CRS_SYNC_DIV_2
+  *         @arg @ref LL_CRS_SYNC_DIV_4
+  *         @arg @ref LL_CRS_SYNC_DIV_8
+  *         @arg @ref LL_CRS_SYNC_DIV_16
+  *         @arg @ref LL_CRS_SYNC_DIV_32
+  *         @arg @ref LL_CRS_SYNC_DIV_64
+  *         @arg @ref LL_CRS_SYNC_DIV_128
+  */
+__STATIC_INLINE uint32_t LL_CRS_GetSyncDivider(void)
+{
+  return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCDIV));
+}
+
+/**
+  * @brief  Set SYNC signal source
+  * @rmtoll CFGR         SYNCSRC       LL_CRS_SetSyncSignalSource
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_CRS_SYNC_SOURCE_GPIO
+  *         @arg @ref LL_CRS_SYNC_SOURCE_LSE
+  *         @arg @ref LL_CRS_SYNC_SOURCE_USB
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_SetSyncSignalSource(uint32_t Source)
+{
+  MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCSRC, Source);
+}
+
+/**
+  * @brief  Get SYNC signal source
+  * @rmtoll CFGR         SYNCSRC       LL_CRS_GetSyncSignalSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_CRS_SYNC_SOURCE_GPIO
+  *         @arg @ref LL_CRS_SYNC_SOURCE_LSE
+  *         @arg @ref LL_CRS_SYNC_SOURCE_USB
+  */
+__STATIC_INLINE uint32_t LL_CRS_GetSyncSignalSource(void)
+{
+  return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCSRC));
+}
+
+/**
+  * @brief  Set input polarity for the SYNC signal source
+  * @rmtoll CFGR         SYNCPOL       LL_CRS_SetSyncPolarity
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_CRS_SYNC_POLARITY_RISING
+  *         @arg @ref LL_CRS_SYNC_POLARITY_FALLING
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_SetSyncPolarity(uint32_t Polarity)
+{
+  MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCPOL, Polarity);
+}
+
+/**
+  * @brief  Get input polarity for the SYNC signal source
+  * @rmtoll CFGR         SYNCPOL       LL_CRS_GetSyncPolarity
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_CRS_SYNC_POLARITY_RISING
+  *         @arg @ref LL_CRS_SYNC_POLARITY_FALLING
+  */
+__STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void)
+{
+  return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCPOL));
+}
+
+/**
+  * @brief  Configure CRS for the synchronization
+  * @rmtoll CR           TRIM          LL_CRS_ConfigSynchronization\n
+  *         CFGR         RELOAD        LL_CRS_ConfigSynchronization\n
+  *         CFGR         FELIM         LL_CRS_ConfigSynchronization\n
+  *         CFGR         SYNCDIV       LL_CRS_ConfigSynchronization\n
+  *         CFGR         SYNCSRC       LL_CRS_ConfigSynchronization\n
+  *         CFGR         SYNCPOL       LL_CRS_ConfigSynchronization
+  * @param  HSI48CalibrationValue a number between Min_Data = 0 and Max_Data = 63
+  * @param  ErrorLimitValue a number between Min_Data = 0 and Max_Data = 0xFFFF
+  * @param  ReloadValue a number between Min_Data = 0 and Max_Data = 255
+  * @param  Settings This parameter can be a combination of the following values:
+  *         @arg @ref LL_CRS_SYNC_DIV_1 or @ref LL_CRS_SYNC_DIV_2 or @ref LL_CRS_SYNC_DIV_4 or @ref LL_CRS_SYNC_DIV_8
+  *              or @ref LL_CRS_SYNC_DIV_16 or @ref LL_CRS_SYNC_DIV_32 or @ref LL_CRS_SYNC_DIV_64 or @ref LL_CRS_SYNC_DIV_128
+  *         @arg @ref LL_CRS_SYNC_SOURCE_GPIO or @ref LL_CRS_SYNC_SOURCE_LSE or @ref LL_CRS_SYNC_SOURCE_USB
+  *         @arg @ref LL_CRS_SYNC_POLARITY_RISING or @ref LL_CRS_SYNC_POLARITY_FALLING
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue, uint32_t ReloadValue, uint32_t Settings)
+{
+  MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue);
+  MODIFY_REG(CRS->CFGR,
+             CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL,
+             ReloadValue | (ErrorLimitValue << CRS_CFGR_FELIM_Pos) | Settings);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CRS_LL_EF_CRS_Management CRS_Management
+  * @{
+  */
+
+/**
+  * @brief  Generate software SYNC event
+  * @rmtoll CR           SWSYNC        LL_CRS_GenerateEvent_SWSYNC
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_GenerateEvent_SWSYNC(void)
+{
+  SET_BIT(CRS->CR, CRS_CR_SWSYNC);
+}
+
+/**
+  * @brief  Get the frequency error direction latched in the time of the last
+  * SYNC event
+  * @rmtoll ISR          FEDIR         LL_CRS_GetFreqErrorDirection
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_CRS_FREQ_ERROR_DIR_UP
+  *         @arg @ref LL_CRS_FREQ_ERROR_DIR_DOWN
+  */
+__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorDirection(void)
+{
+  return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
+}
+
+/**
+  * @brief  Get the frequency error counter value latched in the time of the last SYNC event
+  * @rmtoll ISR          FECAP         LL_CRS_GetFreqErrorCapture
+  * @retval A number between Min_Data = 0x0000 and Max_Data = 0xFFFF
+  */
+__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorCapture(void)
+{
+  return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CRS_LL_EF_FLAG_Management FLAG_Management
+  * @{
+  */
+
+/**
+  * @brief  Check if SYNC event OK signal occurred or not
+  * @rmtoll ISR          SYNCOKF       LL_CRS_IsActiveFlag_SYNCOK
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCOK(void)
+{
+  return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCOKF) == (CRS_ISR_SYNCOKF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if SYNC warning signal occurred or not
+  * @rmtoll ISR          SYNCWARNF     LL_CRS_IsActiveFlag_SYNCWARN
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCWARN(void)
+{
+  return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCWARNF) == (CRS_ISR_SYNCWARNF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if Synchronization or trimming error signal occurred or not
+  * @rmtoll ISR          ERRF          LL_CRS_IsActiveFlag_ERR
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ERR(void)
+{
+  return ((READ_BIT(CRS->ISR, CRS_ISR_ERRF) == (CRS_ISR_ERRF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if Expected SYNC signal occurred or not
+  * @rmtoll ISR          ESYNCF        LL_CRS_IsActiveFlag_ESYNC
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ESYNC(void)
+{
+  return ((READ_BIT(CRS->ISR, CRS_ISR_ESYNCF) == (CRS_ISR_ESYNCF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if SYNC error signal occurred or not
+  * @rmtoll ISR          SYNCERR       LL_CRS_IsActiveFlag_SYNCERR
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCERR(void)
+{
+  return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCERR) == (CRS_ISR_SYNCERR)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if SYNC missed error signal occurred or not
+  * @rmtoll ISR          SYNCMISS      LL_CRS_IsActiveFlag_SYNCMISS
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCMISS(void)
+{
+  return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCMISS) == (CRS_ISR_SYNCMISS)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if Trimming overflow or underflow occurred or not
+  * @rmtoll ISR          TRIMOVF       LL_CRS_IsActiveFlag_TRIMOVF
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_TRIMOVF(void)
+{
+  return ((READ_BIT(CRS->ISR, CRS_ISR_TRIMOVF) == (CRS_ISR_TRIMOVF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the SYNC event OK flag
+  * @rmtoll ICR          SYNCOKC       LL_CRS_ClearFlag_SYNCOK
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_ClearFlag_SYNCOK(void)
+{
+  WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
+}
+
+/**
+  * @brief  Clear the  SYNC warning flag
+  * @rmtoll ICR          SYNCWARNC     LL_CRS_ClearFlag_SYNCWARN
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_ClearFlag_SYNCWARN(void)
+{
+  WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
+}
+
+/**
+  * @brief  Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also
+  * the ERR flag
+  * @rmtoll ICR          ERRC          LL_CRS_ClearFlag_ERR
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_ClearFlag_ERR(void)
+{
+  WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
+}
+
+/**
+  * @brief  Clear Expected SYNC flag
+  * @rmtoll ICR          ESYNCC        LL_CRS_ClearFlag_ESYNC
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_ClearFlag_ESYNC(void)
+{
+  WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CRS_LL_EF_IT_Management IT_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable SYNC event OK interrupt
+  * @rmtoll CR           SYNCOKIE      LL_CRS_EnableIT_SYNCOK
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_EnableIT_SYNCOK(void)
+{
+  SET_BIT(CRS->CR, CRS_CR_SYNCOKIE);
+}
+
+/**
+  * @brief  Disable SYNC event OK interrupt
+  * @rmtoll CR           SYNCOKIE      LL_CRS_DisableIT_SYNCOK
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_DisableIT_SYNCOK(void)
+{
+  CLEAR_BIT(CRS->CR, CRS_CR_SYNCOKIE);
+}
+
+/**
+  * @brief  Check if SYNC event OK interrupt is enabled or not
+  * @rmtoll CR           SYNCOKIE      LL_CRS_IsEnabledIT_SYNCOK
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCOK(void)
+{
+  return ((READ_BIT(CRS->CR, CRS_CR_SYNCOKIE) == (CRS_CR_SYNCOKIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable SYNC warning interrupt
+  * @rmtoll CR           SYNCWARNIE    LL_CRS_EnableIT_SYNCWARN
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_EnableIT_SYNCWARN(void)
+{
+  SET_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
+}
+
+/**
+  * @brief  Disable SYNC warning interrupt
+  * @rmtoll CR           SYNCWARNIE    LL_CRS_DisableIT_SYNCWARN
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_DisableIT_SYNCWARN(void)
+{
+  CLEAR_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
+}
+
+/**
+  * @brief  Check if SYNC warning interrupt is enabled or not
+  * @rmtoll CR           SYNCWARNIE    LL_CRS_IsEnabledIT_SYNCWARN
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCWARN(void)
+{
+  return ((READ_BIT(CRS->CR, CRS_CR_SYNCWARNIE) == (CRS_CR_SYNCWARNIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Synchronization or trimming error interrupt
+  * @rmtoll CR           ERRIE         LL_CRS_EnableIT_ERR
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_EnableIT_ERR(void)
+{
+  SET_BIT(CRS->CR, CRS_CR_ERRIE);
+}
+
+/**
+  * @brief  Disable Synchronization or trimming error interrupt
+  * @rmtoll CR           ERRIE         LL_CRS_DisableIT_ERR
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_DisableIT_ERR(void)
+{
+  CLEAR_BIT(CRS->CR, CRS_CR_ERRIE);
+}
+
+/**
+  * @brief  Check if Synchronization or trimming error interrupt is enabled or not
+  * @rmtoll CR           ERRIE         LL_CRS_IsEnabledIT_ERR
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ERR(void)
+{
+  return ((READ_BIT(CRS->CR, CRS_CR_ERRIE) == (CRS_CR_ERRIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Expected SYNC interrupt
+  * @rmtoll CR           ESYNCIE       LL_CRS_EnableIT_ESYNC
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_EnableIT_ESYNC(void)
+{
+  SET_BIT(CRS->CR, CRS_CR_ESYNCIE);
+}
+
+/**
+  * @brief  Disable Expected SYNC interrupt
+  * @rmtoll CR           ESYNCIE       LL_CRS_DisableIT_ESYNC
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_DisableIT_ESYNC(void)
+{
+  CLEAR_BIT(CRS->CR, CRS_CR_ESYNCIE);
+}
+
+/**
+  * @brief  Check if Expected SYNC interrupt is enabled or not
+  * @rmtoll CR           ESYNCIE       LL_CRS_IsEnabledIT_ESYNC
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ESYNC(void)
+{
+  return ((READ_BIT(CRS->CR, CRS_CR_ESYNCIE) == (CRS_CR_ESYNCIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup CRS_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+
+ErrorStatus LL_CRS_DeInit(void);
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined(CRS) */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_LL_CRS_H */
diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dma.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dma.h
index 4d18318b..61f4cf5a 100644
--- a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dma.h
+++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dma.h
@@ -1,3282 +1,3282 @@
-/**
-  ******************************************************************************
-  * @file    stm32h7xx_ll_dma.h
-  * @author  MCD Application Team
-  * @brief   Header file of DMA LL module.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32H7xx_LL_DMA_H
-#define STM32H7xx_LL_DMA_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx.h"
-#include "stm32h7xx_ll_dmamux.h"
-
-/** @addtogroup STM32H7xx_LL_Driver
-  * @{
-  */
-
-#if defined (DMA1) || defined (DMA2)
-
-/** @defgroup DMA_LL DMA
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup DMA_LL_Private_Variables DMA Private Variables
-  * @{
-  */
-/* Array used to get the DMA stream register offset versus stream index LL_DMA_STREAM_x */
-static const uint8_t LL_DMA_STR_OFFSET_TAB[] =
-{
-  (uint8_t)(DMA1_Stream0_BASE - DMA1_BASE),
-  (uint8_t)(DMA1_Stream1_BASE - DMA1_BASE),
-  (uint8_t)(DMA1_Stream2_BASE - DMA1_BASE),
-  (uint8_t)(DMA1_Stream3_BASE - DMA1_BASE),
-  (uint8_t)(DMA1_Stream4_BASE - DMA1_BASE),
-  (uint8_t)(DMA1_Stream5_BASE - DMA1_BASE),
-  (uint8_t)(DMA1_Stream6_BASE - DMA1_BASE),
-  (uint8_t)(DMA1_Stream7_BASE - DMA1_BASE)
-};
-
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-
-/**
-  * @brief  Helper macro to convert DMA Instance DMAx into DMAMUX channel
-  * @note   DMAMUX channel 0 to 7 are mapped to DMA1 stream 0 to 7.
-  *         DMAMUX channel 8 to 15 are mapped to DMA2 stream 0 to 7.
-  * @param  __DMA_INSTANCE__ DMAx
-  * @retval Channel_Offset (LL_DMAMUX_CHANNEL_8 or 0).
-  */
-#define LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(__DMA_INSTANCE__)   \
-(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) ? 0UL : 8UL)
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
-  * @{
-  */
-typedef struct
-{
-  uint32_t PeriphOrM2MSrcAddress;  /*!< Specifies the peripheral base address for DMA transfer
-                                        or as Source base address in case of memory to memory transfer direction.
-
-                                        This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
-
-  uint32_t MemoryOrM2MDstAddress;  /*!< Specifies the memory base address for DMA transfer
-                                        or as Destination base address in case of memory to memory transfer direction.
-
-                                        This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
-
-  uint32_t Direction;              /*!< Specifies if the data will be transferred from memory to peripheral,
-                                        from memory to memory or from peripheral to memory.
-                                        This parameter can be a value of @ref DMA_LL_EC_DIRECTION
-
-                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
-
-  uint32_t Mode;                   /*!< Specifies the normal or circular operation mode.
-                                        This parameter can be a value of @ref DMA_LL_EC_MODE
-                                        @note The circular buffer mode cannot be used if the memory to memory
-                                              data transfer direction is configured on the selected Stream
-
-                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
-
-  uint32_t PeriphOrM2MSrcIncMode;  /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
-                                        is incremented or not.
-                                        This parameter can be a value of @ref DMA_LL_EC_PERIPH
-
-                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
-
-  uint32_t MemoryOrM2MDstIncMode;  /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
-                                        is incremented or not.
-                                        This parameter can be a value of @ref DMA_LL_EC_MEMORY
-
-                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
-
-  uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
-                                        in case of memory to memory transfer direction.
-                                        This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
-
-                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
-
-  uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
-                                        in case of memory to memory transfer direction.
-                                        This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
-
-                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
-
-  uint32_t NbData;                 /*!< Specifies the number of data to transfer, in data unit.
-                                        The data unit is equal to the source buffer configuration set in PeripheralSize
-                                        or MemorySize parameters depending in the transfer direction.
-                                        This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
-
-                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
-
-  uint32_t PeriphRequest;          /*!< Specifies the peripheral request.
-                                        This parameter can be a value of @ref DMAMUX1_Request_selection
-
-                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */
-
-  uint32_t Priority;               /*!< Specifies the channel priority level.
-                                        This parameter can be a value of @ref DMA_LL_EC_PRIORITY
-
-                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetStreamPriorityLevel(). */
-
-  uint32_t FIFOMode;               /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
-                                        This parameter can be a value of @ref DMA_LL_FIFOMODE
-                                        @note The Direct mode (FIFO mode disabled) cannot be used if the
-                                        memory-to-memory data transfer is configured on the selected stream
-
-                                        This feature can be modified afterwards using unitary functions @ref LL_DMA_EnableFifoMode() or @ref LL_DMA_EnableFifoMode() . */
-
-  uint32_t FIFOThreshold;          /*!< Specifies the FIFO threshold level.
-                                        This parameter can be a value of @ref DMA_LL_EC_FIFOTHRESHOLD
-
-                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetFIFOThreshold(). */
-
-  uint32_t MemBurst;               /*!< Specifies the Burst transfer configuration for the memory transfers.
-                                        It specifies the amount of data to be transferred in a single non interruptible
-                                        transaction.
-                                        This parameter can be a value of @ref DMA_LL_EC_MBURST
-                                        @note The burst mode is possible only if the address Increment mode is enabled.
-
-                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryBurstxfer(). */
-
-  uint32_t PeriphBurst;            /*!< Specifies the Burst transfer configuration for the peripheral transfers.
-                                        It specifies the amount of data to be transferred in a single non interruptible
-                                        transaction.
-                                        This parameter can be a value of @ref DMA_LL_EC_PBURST
-                                        @note The burst mode is possible only if the address Increment mode is enabled.
-
-                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphBurstxfer(). */
-
-} LL_DMA_InitTypeDef;
-/**
-  * @}
-  */
-#endif /*USE_FULL_LL_DRIVER*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
-  * @{
-  */
-
-/** @defgroup DMA_LL_EC_STREAM STREAM
-  * @{
-  */
-#define LL_DMA_STREAM_0                   0x00000000U
-#define LL_DMA_STREAM_1                   0x00000001U
-#define LL_DMA_STREAM_2                   0x00000002U
-#define LL_DMA_STREAM_3                   0x00000003U
-#define LL_DMA_STREAM_4                   0x00000004U
-#define LL_DMA_STREAM_5                   0x00000005U
-#define LL_DMA_STREAM_6                   0x00000006U
-#define LL_DMA_STREAM_7                   0x00000007U
-#define LL_DMA_STREAM_ALL                 0xFFFF0000U
-/**
-  * @}
-  */
-
-
-/** @defgroup DMA_LL_EC_DIRECTION DIRECTION
-  * @{
-  */
-#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U               /*!< Peripheral to memory direction */
-#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_SxCR_DIR_0            /*!< Memory to peripheral direction */
-#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_SxCR_DIR_1            /*!< Memory to memory direction     */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_LL_EC_MODE MODE
-  * @{
-  */
-#define LL_DMA_MODE_NORMAL                0x00000000U               /*!< Normal Mode                  */
-#define LL_DMA_MODE_CIRCULAR              DMA_SxCR_CIRC             /*!< Circular Mode                */
-#define LL_DMA_MODE_PFCTRL                DMA_SxCR_PFCTRL           /*!< Peripheral flow control mode */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_LL_EC_DOUBLEBUFFER_MODE DOUBLE BUFFER MODE
-  * @{
-  */
-#define LL_DMA_DOUBLEBUFFER_MODE_DISABLE  0x00000000U               /*!< Disable double buffering mode */
-#define LL_DMA_DOUBLEBUFFER_MODE_ENABLE   DMA_SxCR_DBM              /*!< Enable double buffering mode  */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_LL_EC_PERIPH PERIPH
-  * @{
-  */
-#define LL_DMA_PERIPH_NOINCREMENT         0x00000000U               /*!< Peripheral increment mode Disable */
-#define LL_DMA_PERIPH_INCREMENT           DMA_SxCR_PINC             /*!< Peripheral increment mode Enable  */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_LL_EC_MEMORY MEMORY
-  * @{
-  */
-#define LL_DMA_MEMORY_NOINCREMENT         0x00000000U               /*!< Memory increment mode Disable */
-#define LL_DMA_MEMORY_INCREMENT           DMA_SxCR_MINC             /*!< Memory increment mode Enable  */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_LL_EC_PDATAALIGN PDATAALIGN
-  * @{
-  */
-#define LL_DMA_PDATAALIGN_BYTE            0x00000000U               /*!< Peripheral data alignment : Byte     */
-#define LL_DMA_PDATAALIGN_HALFWORD        DMA_SxCR_PSIZE_0          /*!< Peripheral data alignment : HalfWord */
-#define LL_DMA_PDATAALIGN_WORD            DMA_SxCR_PSIZE_1          /*!< Peripheral data alignment : Word     */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_LL_EC_MDATAALIGN MDATAALIGN
-  * @{
-  */
-#define LL_DMA_MDATAALIGN_BYTE            0x00000000U               /*!< Memory data alignment : Byte     */
-#define LL_DMA_MDATAALIGN_HALFWORD        DMA_SxCR_MSIZE_0          /*!< Memory data alignment : HalfWord */
-#define LL_DMA_MDATAALIGN_WORD            DMA_SxCR_MSIZE_1          /*!< Memory data alignment : Word     */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_LL_EC_OFFSETSIZE OFFSETSIZE
-  * @{
-  */
-#define LL_DMA_OFFSETSIZE_PSIZE           0x00000000U               /*!< Peripheral increment offset size is linked to the PSIZE           */
-#define LL_DMA_OFFSETSIZE_FIXEDTO4        DMA_SxCR_PINCOS           /*!< Peripheral increment offset size is fixed to 4 (32-bit alignment) */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_LL_EC_PRIORITY PRIORITY
-  * @{
-  */
-#define LL_DMA_PRIORITY_LOW               0x00000000U               /*!< Priority level : Low       */
-#define LL_DMA_PRIORITY_MEDIUM            DMA_SxCR_PL_0             /*!< Priority level : Medium    */
-#define LL_DMA_PRIORITY_HIGH              DMA_SxCR_PL_1             /*!< Priority level : High      */
-#define LL_DMA_PRIORITY_VERYHIGH          DMA_SxCR_PL               /*!< Priority level : Very_High */
-/**
-  * @}
-  */
-
-
-/** @defgroup DMA_LL_EC_MBURST MBURST
-  * @{
-  */
-#define LL_DMA_MBURST_SINGLE              0x00000000U                             /*!< Memory burst single transfer configuration      */
-#define LL_DMA_MBURST_INC4                DMA_SxCR_MBURST_0                       /*!< Memory burst of 4 beats transfer configuration  */
-#define LL_DMA_MBURST_INC8                DMA_SxCR_MBURST_1                       /*!< Memory burst of 8 beats transfer configuration  */
-#define LL_DMA_MBURST_INC16               (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1) /*!< Memory burst of 16 beats transfer configuration */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_LL_EC_PBURST PBURST
-  * @{
-  */
-#define LL_DMA_PBURST_SINGLE              0x00000000U                             /*!< Peripheral burst single transfer configuration      */
-#define LL_DMA_PBURST_INC4                DMA_SxCR_PBURST_0                       /*!< Peripheral burst of 4 beats transfer configuration  */
-#define LL_DMA_PBURST_INC8                DMA_SxCR_PBURST_1                       /*!< Peripheral burst of 8 beats transfer configuration  */
-#define LL_DMA_PBURST_INC16               (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1) /*!< Peripheral burst of 16 beats transfer configuration */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_LL_FIFOMODE DMA_LL_FIFOMODE
-  * @{
-  */
-#define LL_DMA_FIFOMODE_DISABLE           0x00000000U                             /*!< FIFO mode disable (direct mode is enabled) */
-#define LL_DMA_FIFOMODE_ENABLE            DMA_SxFCR_DMDIS                         /*!< FIFO mode enable                           */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_LL_EC_FIFOSTATUS_0 FIFOSTATUS 0
-  * @{
-  */
-#define LL_DMA_FIFOSTATUS_0_25            0x00000000U                             /*!< 0 < fifo_level < 1/4    */
-#define LL_DMA_FIFOSTATUS_25_50           DMA_SxFCR_FS_0                          /*!< 1/4 < fifo_level < 1/2  */
-#define LL_DMA_FIFOSTATUS_50_75           DMA_SxFCR_FS_1                          /*!< 1/2 < fifo_level < 3/4  */
-#define LL_DMA_FIFOSTATUS_75_100          (DMA_SxFCR_FS_1 | DMA_SxFCR_FS_0)       /*!< 3/4 < fifo_level < full */
-#define LL_DMA_FIFOSTATUS_EMPTY           DMA_SxFCR_FS_2                          /*!< FIFO is empty           */
-#define LL_DMA_FIFOSTATUS_FULL            (DMA_SxFCR_FS_2 | DMA_SxFCR_FS_0)       /*!< FIFO is full            */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_LL_EC_FIFOTHRESHOLD FIFOTHRESHOLD
-  * @{
-  */
-#define LL_DMA_FIFOTHRESHOLD_1_4          0x00000000U                             /*!< FIFO threshold 1 quart full configuration  */
-#define LL_DMA_FIFOTHRESHOLD_1_2          DMA_SxFCR_FTH_0                         /*!< FIFO threshold half full configuration     */
-#define LL_DMA_FIFOTHRESHOLD_3_4          DMA_SxFCR_FTH_1                         /*!< FIFO threshold 3 quarts full configuration */
-#define LL_DMA_FIFOTHRESHOLD_FULL         DMA_SxFCR_FTH                           /*!< FIFO threshold full configuration          */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM
-  * @{
-  */
-#define LL_DMA_CURRENTTARGETMEM0          0x00000000U                             /*!< Set CurrentTarget Memory to Memory 0  */
-#define LL_DMA_CURRENTTARGETMEM1          DMA_SxCR_CT                             /*!< Set CurrentTarget Memory to Memory 1  */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
-  * @{
-  */
-
-/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
-  * @{
-  */
-/**
-  * @brief  Write a value in DMA register
-  * @param  __INSTANCE__ DMA Instance
-  * @param  __REG__ Register to be written
-  * @param  __VALUE__ Value to be written in the register
-  * @retval None
-  */
-#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
-
-/**
-  * @brief  Read a value in DMA register
-  * @param  __INSTANCE__ DMA Instance
-  * @param  __REG__ Register to be read
-  * @retval Register value
-  */
-#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
-  * @}
-  */
-
-/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxStreamy
-  * @{
-  */
-/**
-  * @brief  Convert DMAx_Streamy into DMAx
-  * @param  __STREAM_INSTANCE__ DMAx_Streamy
-  * @retval DMAx
-  */
-#define __LL_DMA_GET_INSTANCE(__STREAM_INSTANCE__)   \
-(((uint32_t)(__STREAM_INSTANCE__) > ((uint32_t)DMA1_Stream7)) ?  DMA2 : DMA1)
-
-/**
-  * @brief  Convert DMAx_Streamy into LL_DMA_STREAM_y
-  * @param  __STREAM_INSTANCE__ DMAx_Streamy
-  * @retval LL_DMA_STREAM_y
-  */
-#define __LL_DMA_GET_STREAM(__STREAM_INSTANCE__)   \
-(((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream0)) ? LL_DMA_STREAM_0 : \
- ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream0)) ? LL_DMA_STREAM_0 : \
- ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream1)) ? LL_DMA_STREAM_1 : \
- ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream1)) ? LL_DMA_STREAM_1 : \
- ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream2)) ? LL_DMA_STREAM_2 : \
- ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream2)) ? LL_DMA_STREAM_2 : \
- ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream3)) ? LL_DMA_STREAM_3 : \
- ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream3)) ? LL_DMA_STREAM_3 : \
- ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream4)) ? LL_DMA_STREAM_4 : \
- ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream4)) ? LL_DMA_STREAM_4 : \
- ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream5)) ? LL_DMA_STREAM_5 : \
- ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream5)) ? LL_DMA_STREAM_5 : \
- ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream6)) ? LL_DMA_STREAM_6 : \
- ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream6)) ? LL_DMA_STREAM_6 : \
- LL_DMA_STREAM_7)
-
-/**
-  * @brief  Convert DMA Instance DMAx and LL_DMA_STREAM_y into DMAx_Streamy
-  * @param  __DMA_INSTANCE__ DMAx
-  * @param  __STREAM__ LL_DMA_STREAM_y
-  * @retval DMAx_Streamy
-  */
-#define __LL_DMA_GET_STREAM_INSTANCE(__DMA_INSTANCE__, __STREAM__)   \
-((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA1_Stream0 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA2_Stream0 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA1_Stream1 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA2_Stream1 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA1_Stream2 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA2_Stream2 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA1_Stream3 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA2_Stream3 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA1_Stream4 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA2_Stream4 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA1_Stream5 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA2_Stream5 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA1_Stream6 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA2_Stream6 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_7))) ? DMA1_Stream7 : \
- DMA2_Stream7)
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
- * @{
- */
-
-/** @defgroup DMA_LL_EF_Configuration Configuration
-  * @{
-  */
-/**
-  * @brief Enable DMA stream.
-  * @rmtoll CR          EN            LL_DMA_EnableStream
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_EnableStream(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-
-  SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_EN);
-}
-
-/**
-  * @brief Disable DMA stream.
-  * @rmtoll CR          EN            LL_DMA_DisableStream
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_DisableStream(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-
-  CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_EN);
-}
-
-/**
-  * @brief Check if DMA stream is enabled or disabled.
-  * @rmtoll CR          EN            LL_DMA_IsEnabledStream
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-
-  return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_EN) == (DMA_SxCR_EN)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Configure all parameters linked to DMA transfer.
-  * @rmtoll CR          DIR           LL_DMA_ConfigTransfer\n
-  *         CR          CIRC          LL_DMA_ConfigTransfer\n
-  *         CR          PINC          LL_DMA_ConfigTransfer\n
-  *         CR          MINC          LL_DMA_ConfigTransfer\n
-  *         CR          PSIZE         LL_DMA_ConfigTransfer\n
-  *         CR          MSIZE         LL_DMA_ConfigTransfer\n
-  *         CR          PL            LL_DMA_ConfigTransfer\n
-  *         CR          PFCTRL        LL_DMA_ConfigTransfer
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @param  Configuration This parameter must be a combination of all the following values:
-  *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
-  *         @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR  or @ref LL_DMA_MODE_PFCTRL
-  *         @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
-  *         @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
-  *         @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
-  *         @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
-  *         @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
-  *@retval None
-  */
-__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configuration)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-
-  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR,
-             DMA_SxCR_DIR | DMA_SxCR_CIRC | DMA_SxCR_PINC | DMA_SxCR_MINC | DMA_SxCR_PSIZE | DMA_SxCR_MSIZE | DMA_SxCR_PL | DMA_SxCR_PFCTRL,
-             Configuration);
-}
-
-/**
-  * @brief Set Data transfer direction (read from peripheral or from memory).
-  * @rmtoll CR          DIR           LL_DMA_SetDataTransferDirection
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @param  Direction This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
-  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
-  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t  Direction)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-
-  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DIR, Direction);
-}
-
-/**
-  * @brief Get Data transfer direction (read from peripheral or from memory).
-  * @rmtoll CR          DIR           LL_DMA_GetDataTransferDirection
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
-  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
-  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-
-  return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DIR));
-}
-
-/**
-  * @brief Set DMA mode normal, circular or peripheral flow control.
-  * @rmtoll CR          CIRC           LL_DMA_SetMode\n
-  *         CR          PFCTRL         LL_DMA_SetMode
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @param  Mode This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_MODE_NORMAL
-  *         @arg @ref LL_DMA_MODE_CIRCULAR
-  *         @arg @ref LL_DMA_MODE_PFCTRL
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mode)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-
-  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL, Mode);
-}
-
-/**
-  * @brief Get DMA mode normal, circular or peripheral flow control.
-  * @rmtoll CR          CIRC           LL_DMA_GetMode\n
-  *         CR          PFCTRL         LL_DMA_GetMode
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DMA_MODE_NORMAL
-  *         @arg @ref LL_DMA_MODE_CIRCULAR
-  *         @arg @ref LL_DMA_MODE_PFCTRL
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-
-  return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL));
-}
-
-/**
-  * @brief Set Peripheral increment mode.
-  * @rmtoll CR          PINC           LL_DMA_SetPeriphIncMode
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @param  IncrementMode This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_PERIPH_NOINCREMENT
-  *         @arg @ref LL_DMA_PERIPH_INCREMENT
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-
-  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINC, IncrementMode);
-}
-
-/**
-  * @brief Get Peripheral increment mode.
-  * @rmtoll CR          PINC           LL_DMA_GetPeriphIncMode
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DMA_PERIPH_NOINCREMENT
-  *         @arg @ref LL_DMA_PERIPH_INCREMENT
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-
-  return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINC));
-}
-
-/**
-  * @brief Set Memory increment mode.
-  * @rmtoll CR          MINC           LL_DMA_SetMemoryIncMode
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @param  IncrementMode This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_MEMORY_NOINCREMENT
-  *         @arg @ref LL_DMA_MEMORY_INCREMENT
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-
-  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MINC, IncrementMode);
-}
-
-/**
-  * @brief Get Memory increment mode.
-  * @rmtoll CR          MINC           LL_DMA_GetMemoryIncMode
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DMA_MEMORY_NOINCREMENT
-  *         @arg @ref LL_DMA_MEMORY_INCREMENT
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-
-  return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MINC));
-}
-
-/**
-  * @brief Set Peripheral size.
-  * @rmtoll CR          PSIZE           LL_DMA_SetPeriphSize
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @param  Size This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_PDATAALIGN_BYTE
-  *         @arg @ref LL_DMA_PDATAALIGN_HALFWORD
-  *         @arg @ref LL_DMA_PDATAALIGN_WORD
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t  Size)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-
-  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PSIZE, Size);
-}
-
-/**
-  * @brief Get Peripheral size.
-  * @rmtoll CR          PSIZE           LL_DMA_GetPeriphSize
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DMA_PDATAALIGN_BYTE
-  *         @arg @ref LL_DMA_PDATAALIGN_HALFWORD
-  *         @arg @ref LL_DMA_PDATAALIGN_WORD
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-
-  return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PSIZE));
-}
-
-/**
-  * @brief Set Memory size.
-  * @rmtoll CR          MSIZE           LL_DMA_SetMemorySize
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @param  Size This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_MDATAALIGN_BYTE
-  *         @arg @ref LL_DMA_MDATAALIGN_HALFWORD
-  *         @arg @ref LL_DMA_MDATAALIGN_WORD
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t  Size)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-
-  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MSIZE, Size);
-}
-
-/**
-  * @brief Get Memory size.
-  * @rmtoll CR          MSIZE           LL_DMA_GetMemorySize
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DMA_MDATAALIGN_BYTE
-  *         @arg @ref LL_DMA_MDATAALIGN_HALFWORD
-  *         @arg @ref LL_DMA_MDATAALIGN_WORD
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-
-  return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MSIZE));
-}
-
-/**
-  * @brief Set Peripheral increment offset size.
-  * @rmtoll CR          PINCOS           LL_DMA_SetIncOffsetSize
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @param  OffsetSize This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_OFFSETSIZE_PSIZE
-  *         @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t OffsetSize)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-
-  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINCOS, OffsetSize);
-}
-
-/**
-  * @brief Get Peripheral increment offset size.
-  * @rmtoll CR          PINCOS           LL_DMA_GetIncOffsetSize
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DMA_OFFSETSIZE_PSIZE
-  *         @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-
-  return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINCOS));
-}
-
-/**
-  * @brief Set Stream priority level.
-  * @rmtoll CR          PL           LL_DMA_SetStreamPriorityLevel
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @param  Priority This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_PRIORITY_LOW
-  *         @arg @ref LL_DMA_PRIORITY_MEDIUM
-  *         @arg @ref LL_DMA_PRIORITY_HIGH
-  *         @arg @ref LL_DMA_PRIORITY_VERYHIGH
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t  Priority)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-
-  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PL, Priority);
-}
-
-/**
-  * @brief Get Stream priority level.
-  * @rmtoll CR          PL           LL_DMA_GetStreamPriorityLevel
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DMA_PRIORITY_LOW
-  *         @arg @ref LL_DMA_PRIORITY_MEDIUM
-  *         @arg @ref LL_DMA_PRIORITY_HIGH
-  *         @arg @ref LL_DMA_PRIORITY_VERYHIGH
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-
-  return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PL));
-}
-
-/**
-  * @brief Enable DMA stream bufferable transfer.
-  * @rmtoll CR          TRBUFF            LL_DMA_EnableBufferableTransfer
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_EnableBufferableTransfer(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-
-  SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TRBUFF);
-}
-
-/**
-  * @brief Disable DMA stream bufferable transfer.
-  * @rmtoll CR          TRBUFF            LL_DMA_DisableBufferableTransfer
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_DisableBufferableTransfer(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-
-  CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TRBUFF);
-}
-
-/**
-  * @brief Set Number of data to transfer.
-  * @rmtoll NDTR          NDT           LL_DMA_SetDataLength
-  * @note   This action has no effect if
-  *         stream is enabled.
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @param  NbData Between 0 to 0xFFFFFFFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t NbData)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-
-  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->NDTR, DMA_SxNDT, NbData);
-}
-
-/**
-  * @brief Get Number of data to transfer.
-  * @rmtoll NDTR          NDT           LL_DMA_GetDataLength
-  * @note   Once the stream is enabled, the return value indicate the
-  *         remaining bytes to be transmitted.
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval Between 0 to 0xFFFFFFFF
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-
-  return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->NDTR, DMA_SxNDT));
-}
-/**
-  * @brief  Set DMA request for DMA Streams on DMAMUX Channel x.
-  * @note   DMAMUX channel 0 to 7 are mapped to DMA1 stream 0 to 7.
-  *         DMAMUX channel 8 to 15 are mapped to DMA2 stream 0 to 7.
-  * @rmtoll CxCR         DMAREQ_ID     LL_DMA_SetPeriphRequest
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @param  Request This parameter can be one of the following values:
-  *         @arg @ref LL_DMAMUX1_REQ_MEM2MEM
-  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR0
-  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR1
-  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR2
-  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR3
-  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR4
-  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR5
-  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR6
-  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR7
-  *         @arg @ref LL_DMAMUX1_REQ_ADC1
-  *         @arg @ref LL_DMAMUX1_REQ_ADC2
-  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH1
-  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH2
-  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH3
-  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH4
-  *         @arg @ref LL_DMAMUX1_REQ_TIM1_UP
-  *         @arg @ref LL_DMAMUX1_REQ_TIM1_TRIG
-  *         @arg @ref LL_DMAMUX1_REQ_TIM1_COM
-  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH1
-  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH2
-  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH3
-  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH4
-  *         @arg @ref LL_DMAMUX1_REQ_TIM2_UP
-  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH1
-  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH2
-  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH3
-  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH4
-  *         @arg @ref LL_DMAMUX1_REQ_TIM3_UP
-  *         @arg @ref LL_DMAMUX1_REQ_TIM3_TRIG
-  *         @arg @ref LL_DMAMUX1_REQ_TIM4_CH1
-  *         @arg @ref LL_DMAMUX1_REQ_TIM4_CH2
-  *         @arg @ref LL_DMAMUX1_REQ_TIM4_CH3
-  *         @arg @ref LL_DMAMUX1_REQ_TIM4_UP
-  *         @arg @ref LL_DMAMUX1_REQ_I2C1_RX
-  *         @arg @ref LL_DMAMUX1_REQ_I2C1_TX
-  *         @arg @ref LL_DMAMUX1_REQ_I2C2_RX
-  *         @arg @ref LL_DMAMUX1_REQ_I2C2_TX
-  *         @arg @ref LL_DMAMUX1_REQ_SPI1_RX
-  *         @arg @ref LL_DMAMUX1_REQ_SPI1_TX
-  *         @arg @ref LL_DMAMUX1_REQ_SPI2_RX
-  *         @arg @ref LL_DMAMUX1_REQ_SPI2_TX
-  *         @arg @ref LL_DMAMUX1_REQ_USART1_RX
-  *         @arg @ref LL_DMAMUX1_REQ_USART1_TX
-  *         @arg @ref LL_DMAMUX1_REQ_USART2_RX
-  *         @arg @ref LL_DMAMUX1_REQ_USART2_TX
-  *         @arg @ref LL_DMAMUX1_REQ_USART3_RX
-  *         @arg @ref LL_DMAMUX1_REQ_USART3_TX
-  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH1
-  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH2
-  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH3
-  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH4
-  *         @arg @ref LL_DMAMUX1_REQ_TIM8_UP
-  *         @arg @ref LL_DMAMUX1_REQ_TIM8_TRIG
-  *         @arg @ref LL_DMAMUX1_REQ_TIM8_COM
-  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH1
-  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH2
-  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH3
-  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH4
-  *         @arg @ref LL_DMAMUX1_REQ_TIM5_UP
-  *         @arg @ref LL_DMAMUX1_REQ_TIM5_TRIG
-  *         @arg @ref LL_DMAMUX1_REQ_SPI3_RX
-  *         @arg @ref LL_DMAMUX1_REQ_SPI3_TX
-  *         @arg @ref LL_DMAMUX1_REQ_UART4_RX
-  *         @arg @ref LL_DMAMUX1_REQ_UART4_TX
-  *         @arg @ref LL_DMAMUX1_REQ_UART5_RX
-  *         @arg @ref LL_DMAMUX1_REQ_UART5_TX
-  *         @arg @ref LL_DMAMUX1_REQ_DAC1_CH1
-  *         @arg @ref LL_DMAMUX1_REQ_DAC1_CH2
-  *         @arg @ref LL_DMAMUX1_REQ_TIM6_UP
-  *         @arg @ref LL_DMAMUX1_REQ_TIM7_UP
-  *         @arg @ref LL_DMAMUX1_REQ_USART6_RX
-  *         @arg @ref LL_DMAMUX1_REQ_USART6_TX
-  *         @arg @ref LL_DMAMUX1_REQ_I2C3_RX
-  *         @arg @ref LL_DMAMUX1_REQ_I2C3_TX
-  *         @arg @ref LL_DMAMUX1_REQ_DCMI_PSSI (*)
-  *         @arg @ref LL_DMAMUX1_REQ_CRYP_IN
-  *         @arg @ref LL_DMAMUX1_REQ_CRYP_OUT
-  *         @arg @ref LL_DMAMUX1_REQ_HASH_IN
-  *         @arg @ref LL_DMAMUX1_REQ_UART7_RX
-  *         @arg @ref LL_DMAMUX1_REQ_UART7_TX
-  *         @arg @ref LL_DMAMUX1_REQ_UART8_RX
-  *         @arg @ref LL_DMAMUX1_REQ_UART8_TX
-  *         @arg @ref LL_DMAMUX1_REQ_SPI4_RX
-  *         @arg @ref LL_DMAMUX1_REQ_SPI4_TX
-  *         @arg @ref LL_DMAMUX1_REQ_SPI5_RX
-  *         @arg @ref LL_DMAMUX1_REQ_SPI5_TX
-  *         @arg @ref LL_DMAMUX1_REQ_SAI1_A
-  *         @arg @ref LL_DMAMUX1_REQ_SAI1_B
-  *         @arg @ref LL_DMAMUX1_REQ_SAI2_A (*)
-  *         @arg @ref LL_DMAMUX1_REQ_SAI2_B (*)
-  *         @arg @ref LL_DMAMUX1_REQ_SWPMI_RX
-  *         @arg @ref LL_DMAMUX1_REQ_SWPMI_TX
-  *         @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_DT
-  *         @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_CS
-  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_MASTER (*)
-  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_A (*)
-  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_B (*)
-  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_C (*)
-  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_D (*)
-  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_E (*)
-  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT0
-  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT1
-  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT2
-  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT3
-  *         @arg @ref LL_DMAMUX1_REQ_TIM15_CH1
-  *         @arg @ref LL_DMAMUX1_REQ_TIM15_UP
-  *         @arg @ref LL_DMAMUX1_REQ_TIM15_TRIG
-  *         @arg @ref LL_DMAMUX1_REQ_TIM15_COM
-  *         @arg @ref LL_DMAMUX1_REQ_TIM16_CH1
-  *         @arg @ref LL_DMAMUX1_REQ_TIM16_UP
-  *         @arg @ref LL_DMAMUX1_REQ_TIM17_CH1
-  *         @arg @ref LL_DMAMUX1_REQ_TIM17_UP
-  *         @arg @ref LL_DMAMUX1_REQ_SAI3_A (*)
-  *         @arg @ref LL_DMAMUX1_REQ_SAI3_B (*)
-  *         @arg @ref LL_DMAMUX1_REQ_ADC3 (*)
-  *         @arg @ref LL_DMAMUX1_REQ_UART9_RX (*)
-  *         @arg @ref LL_DMAMUX1_REQ_UART9_TX (*)
-  *         @arg @ref LL_DMAMUX1_REQ_USART10_RX (*)
-  *         @arg @ref LL_DMAMUX1_REQ_USART10_TX (*)
-  *         @arg @ref LL_DMAMUX1_REQ_FMAC_READ  (*)
-  *         @arg @ref LL_DMAMUX1_REQ_FMAC_WRITE (*)
-  *         @arg @ref LL_DMAMUX1_REQ_CORDIC_READ (*)
-  *         @arg @ref LL_DMAMUX1_REQ_CORDIC_WRITE(*)
-  *         @arg @ref LL_DMAMUX1_REQ_I2C5_RX     (*)
-  *         @arg @ref LL_DMAMUX1_REQ_I2C5_TX     (*)
-  *         @arg @ref LL_DMAMUX1_REQ_TIM23_CH1   (*)
-  *         @arg @ref LL_DMAMUX1_REQ_TIM23_CH2   (*)
-  *         @arg @ref LL_DMAMUX1_REQ_TIM23_CH3   (*)
-  *         @arg @ref LL_DMAMUX1_REQ_TIM23_CH4   (*)
-  *         @arg @ref LL_DMAMUX1_REQ_TIM23_UP    (*)
-  *         @arg @ref LL_DMAMUX1_REQ_TIM23_TRIG  (*)
-  *         @arg @ref LL_DMAMUX1_REQ_TIM24_CH1   (*)
-  *         @arg @ref LL_DMAMUX1_REQ_TIM24_CH2   (*)
-  *         @arg @ref LL_DMAMUX1_REQ_TIM24_CH3   (*)
-  *         @arg @ref LL_DMAMUX1_REQ_TIM24_CH4   (*)
-  *         @arg @ref LL_DMAMUX1_REQ_TIM24_UP    (*)
-  *         @arg @ref LL_DMAMUX1_REQ_TIM24_TRIG  (*)
-  *
-  * @note   (*) Availability depends on devices.
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Request)
-{
-  MODIFY_REG(((DMAMUX_Channel_TypeDef *)(uint32_t)((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE * (Stream)) + (uint32_t)(DMAMUX_CCR_SIZE * LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(DMAx))))->CCR, DMAMUX_CxCR_DMAREQ_ID, Request);
-}
-
-/**
-  * @brief  Get DMA request for DMA Channels on DMAMUX Channel x.
-  * @note   DMAMUX channel 0 to 7 are mapped to DMA1 stream 0 to 7.
-  *         DMAMUX channel 8 to 15 are mapped to DMA2 stream 0 to 7.
-  * @rmtoll CxCR         DMAREQ_ID     LL_DMA_GetPeriphRequest
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DMAMUX1_REQ_MEM2MEM
-  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR0
-  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR1
-  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR2
-  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR3
-  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR4
-  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR5
-  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR6
-  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR7
-  *         @arg @ref LL_DMAMUX1_REQ_ADC1
-  *         @arg @ref LL_DMAMUX1_REQ_ADC2
-  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH1
-  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH2
-  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH3
-  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH4
-  *         @arg @ref LL_DMAMUX1_REQ_TIM1_UP
-  *         @arg @ref LL_DMAMUX1_REQ_TIM1_TRIG
-  *         @arg @ref LL_DMAMUX1_REQ_TIM1_COM
-  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH1
-  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH2
-  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH3
-  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH4
-  *         @arg @ref LL_DMAMUX1_REQ_TIM2_UP
-  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH1
-  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH2
-  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH3
-  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH4
-  *         @arg @ref LL_DMAMUX1_REQ_TIM3_UP
-  *         @arg @ref LL_DMAMUX1_REQ_TIM3_TRIG
-  *         @arg @ref LL_DMAMUX1_REQ_TIM4_CH1
-  *         @arg @ref LL_DMAMUX1_REQ_TIM4_CH2
-  *         @arg @ref LL_DMAMUX1_REQ_TIM4_CH3
-  *         @arg @ref LL_DMAMUX1_REQ_TIM4_UP
-  *         @arg @ref LL_DMAMUX1_REQ_I2C1_RX
-  *         @arg @ref LL_DMAMUX1_REQ_I2C1_TX
-  *         @arg @ref LL_DMAMUX1_REQ_I2C2_RX
-  *         @arg @ref LL_DMAMUX1_REQ_I2C2_TX
-  *         @arg @ref LL_DMAMUX1_REQ_SPI1_RX
-  *         @arg @ref LL_DMAMUX1_REQ_SPI1_TX
-  *         @arg @ref LL_DMAMUX1_REQ_SPI2_RX
-  *         @arg @ref LL_DMAMUX1_REQ_SPI2_TX
-  *         @arg @ref LL_DMAMUX1_REQ_USART1_RX
-  *         @arg @ref LL_DMAMUX1_REQ_USART1_TX
-  *         @arg @ref LL_DMAMUX1_REQ_USART2_RX
-  *         @arg @ref LL_DMAMUX1_REQ_USART2_TX
-  *         @arg @ref LL_DMAMUX1_REQ_USART3_RX
-  *         @arg @ref LL_DMAMUX1_REQ_USART3_TX
-  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH1
-  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH2
-  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH3
-  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH4
-  *         @arg @ref LL_DMAMUX1_REQ_TIM8_UP
-  *         @arg @ref LL_DMAMUX1_REQ_TIM8_TRIG
-  *         @arg @ref LL_DMAMUX1_REQ_TIM8_COM
-  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH1
-  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH2
-  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH3
-  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH4
-  *         @arg @ref LL_DMAMUX1_REQ_TIM5_UP
-  *         @arg @ref LL_DMAMUX1_REQ_TIM5_TRIG
-  *         @arg @ref LL_DMAMUX1_REQ_SPI3_RX
-  *         @arg @ref LL_DMAMUX1_REQ_SPI3_TX
-  *         @arg @ref LL_DMAMUX1_REQ_UART4_RX
-  *         @arg @ref LL_DMAMUX1_REQ_UART4_TX
-  *         @arg @ref LL_DMAMUX1_REQ_UART5_RX
-  *         @arg @ref LL_DMAMUX1_REQ_UART5_TX
-  *         @arg @ref LL_DMAMUX1_REQ_DAC1_CH1
-  *         @arg @ref LL_DMAMUX1_REQ_DAC1_CH2
-  *         @arg @ref LL_DMAMUX1_REQ_TIM6_UP
-  *         @arg @ref LL_DMAMUX1_REQ_TIM7_UP
-  *         @arg @ref LL_DMAMUX1_REQ_USART6_RX
-  *         @arg @ref LL_DMAMUX1_REQ_USART6_TX
-  *         @arg @ref LL_DMAMUX1_REQ_I2C3_RX
-  *         @arg @ref LL_DMAMUX1_REQ_I2C3_TX
-  *         @arg @ref LL_DMAMUX1_REQ_DCMI_PSSI (*)
-  *         @arg @ref LL_DMAMUX1_REQ_CRYP_IN
-  *         @arg @ref LL_DMAMUX1_REQ_CRYP_OUT
-  *         @arg @ref LL_DMAMUX1_REQ_HASH_IN
-  *         @arg @ref LL_DMAMUX1_REQ_UART7_RX
-  *         @arg @ref LL_DMAMUX1_REQ_UART7_TX
-  *         @arg @ref LL_DMAMUX1_REQ_UART8_RX
-  *         @arg @ref LL_DMAMUX1_REQ_UART8_TX
-  *         @arg @ref LL_DMAMUX1_REQ_SPI4_RX
-  *         @arg @ref LL_DMAMUX1_REQ_SPI4_TX
-  *         @arg @ref LL_DMAMUX1_REQ_SPI5_RX
-  *         @arg @ref LL_DMAMUX1_REQ_SPI5_TX
-  *         @arg @ref LL_DMAMUX1_REQ_SAI1_A
-  *         @arg @ref LL_DMAMUX1_REQ_SAI1_B
-  *         @arg @ref LL_DMAMUX1_REQ_SAI2_A (*)
-  *         @arg @ref LL_DMAMUX1_REQ_SAI2_B (*)
-  *         @arg @ref LL_DMAMUX1_REQ_SWPMI_RX
-  *         @arg @ref LL_DMAMUX1_REQ_SWPMI_TX
-  *         @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_DT
-  *         @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_CS
-  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_MASTER (*)
-  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_A (*)
-  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_B (*)
-  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_C (*)
-  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_D (*)
-  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_E (*)
-  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT0
-  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT1
-  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT2
-  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT3
-  *         @arg @ref LL_DMAMUX1_REQ_TIM15_CH1
-  *         @arg @ref LL_DMAMUX1_REQ_TIM15_UP
-  *         @arg @ref LL_DMAMUX1_REQ_TIM15_TRIG
-  *         @arg @ref LL_DMAMUX1_REQ_TIM15_COM
-  *         @arg @ref LL_DMAMUX1_REQ_TIM16_CH1
-  *         @arg @ref LL_DMAMUX1_REQ_TIM16_UP
-  *         @arg @ref LL_DMAMUX1_REQ_TIM17_CH1
-  *         @arg @ref LL_DMAMUX1_REQ_TIM17_UP
-  *         @arg @ref LL_DMAMUX1_REQ_SAI3_A (*)
-  *         @arg @ref LL_DMAMUX1_REQ_SAI3_B (*)
-  *         @arg @ref LL_DMAMUX1_REQ_ADC3 (*)
-  *         @arg @ref LL_DMAMUX1_REQ_UART9_RX (*)
-  *         @arg @ref LL_DMAMUX1_REQ_UART9_TX (*)
-  *         @arg @ref LL_DMAMUX1_REQ_USART10_RX (*)
-  *         @arg @ref LL_DMAMUX1_REQ_USART10_TX (*)
-  *         @arg @ref LL_DMAMUX1_REQ_FMAC_READ  (*)
-  *         @arg @ref LL_DMAMUX1_REQ_FMAC_WRITE (*)
-  *         @arg @ref LL_DMAMUX1_REQ_CORDIC_READ (*)
-  *         @arg @ref LL_DMAMUX1_REQ_CORDIC_WRITE(*)
-  *         @arg @ref LL_DMAMUX1_REQ_I2C5_RX     (*)
-  *         @arg @ref LL_DMAMUX1_REQ_I2C5_TX     (*)
-  *         @arg @ref LL_DMAMUX1_REQ_TIM23_CH1   (*)
-  *         @arg @ref LL_DMAMUX1_REQ_TIM23_CH2   (*)
-  *         @arg @ref LL_DMAMUX1_REQ_TIM23_CH3   (*)
-  *         @arg @ref LL_DMAMUX1_REQ_TIM23_CH4   (*)
-  *         @arg @ref LL_DMAMUX1_REQ_TIM23_UP    (*)
-  *         @arg @ref LL_DMAMUX1_REQ_TIM23_TRIG  (*)
-  *         @arg @ref LL_DMAMUX1_REQ_TIM24_CH1   (*)
-  *         @arg @ref LL_DMAMUX1_REQ_TIM24_CH2   (*)
-  *         @arg @ref LL_DMAMUX1_REQ_TIM24_CH3   (*)
-  *         @arg @ref LL_DMAMUX1_REQ_TIM24_CH4   (*)
-  *         @arg @ref LL_DMAMUX1_REQ_TIM24_UP    (*)
-  *         @arg @ref LL_DMAMUX1_REQ_TIM24_TRIG  (*)
-  *
-  * @note   (*) Availability depends on devices.
-  */
-__STATIC_INLINE  uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  return (READ_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE * (Stream)) + (uint32_t)(DMAMUX_CCR_SIZE * LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(DMAx)))))->CCR, DMAMUX_CxCR_DMAREQ_ID));
-}
-
-/**
-  * @brief Set Memory burst transfer configuration.
-  * @rmtoll CR          MBURST           LL_DMA_SetMemoryBurstxfer
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @param  Mburst This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_MBURST_SINGLE
-  *         @arg @ref LL_DMA_MBURST_INC4
-  *         @arg @ref LL_DMA_MBURST_INC8
-  *         @arg @ref LL_DMA_MBURST_INC16
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mburst)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-
-  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MBURST, Mburst);
-}
-
-/**
-  * @brief Get Memory burst transfer configuration.
-  * @rmtoll CR          MBURST           LL_DMA_GetMemoryBurstxfer
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DMA_MBURST_SINGLE
-  *         @arg @ref LL_DMA_MBURST_INC4
-  *         @arg @ref LL_DMA_MBURST_INC8
-  *         @arg @ref LL_DMA_MBURST_INC16
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-
-  return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MBURST));
-}
-
-/**
-  * @brief Set  Peripheral burst transfer configuration.
-  * @rmtoll CR          PBURST           LL_DMA_SetPeriphBurstxfer
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @param  Pburst This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_PBURST_SINGLE
-  *         @arg @ref LL_DMA_PBURST_INC4
-  *         @arg @ref LL_DMA_PBURST_INC8
-  *         @arg @ref LL_DMA_PBURST_INC16
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pburst)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-
-  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PBURST, Pburst);
-}
-
-/**
-  * @brief Get Peripheral burst transfer configuration.
-  * @rmtoll CR          PBURST           LL_DMA_GetPeriphBurstxfer
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DMA_PBURST_SINGLE
-  *         @arg @ref LL_DMA_PBURST_INC4
-  *         @arg @ref LL_DMA_PBURST_INC8
-  *         @arg @ref LL_DMA_PBURST_INC16
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-
-  return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PBURST));
-}
-
-/**
-  * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
-  * @rmtoll CR          CT           LL_DMA_SetCurrentTargetMem
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @param CurrentMemory This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CURRENTTARGETMEM0
-  *         @arg @ref LL_DMA_CURRENTTARGETMEM1
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t CurrentMemory)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-
-  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CT, CurrentMemory);
-}
-
-/**
-  * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
-  * @rmtoll CR          CT           LL_DMA_GetCurrentTargetMem
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DMA_CURRENTTARGETMEM0
-  *         @arg @ref LL_DMA_CURRENTTARGETMEM1
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-
-  return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CT));
-}
-
-/**
-  * @brief Enable the double buffer mode.
-  * @rmtoll CR          DBM           LL_DMA_EnableDoubleBufferMode
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-
-  SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DBM);
-}
-
-/**
-  * @brief Disable the double buffer mode.
-  * @rmtoll CR          DBM           LL_DMA_DisableDoubleBufferMode
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-
-  CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DBM);
-}
-
-/**
-  * @brief Get FIFO status.
-  * @rmtoll FCR          FS          LL_DMA_GetFIFOStatus
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DMA_FIFOSTATUS_0_25
-  *         @arg @ref LL_DMA_FIFOSTATUS_25_50
-  *         @arg @ref LL_DMA_FIFOSTATUS_50_75
-  *         @arg @ref LL_DMA_FIFOSTATUS_75_100
-  *         @arg @ref LL_DMA_FIFOSTATUS_EMPTY
-  *         @arg @ref LL_DMA_FIFOSTATUS_FULL
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-
-  return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FS));
-}
-
-/**
-  * @brief Disable Fifo mode.
-  * @rmtoll FCR          DMDIS          LL_DMA_DisableFifoMode
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_DisableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-
-  CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_DMDIS);
-}
-
-/**
-  * @brief Enable Fifo mode.
-  * @rmtoll FCR          DMDIS          LL_DMA_EnableFifoMode
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_EnableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-
-  SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_DMDIS);
-}
-
-/**
-  * @brief Select FIFO threshold.
-  * @rmtoll FCR         FTH          LL_DMA_SetFIFOThreshold
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @param  Threshold This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
-  *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
-  *         @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
-  *         @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Threshold)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-
-  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FTH, Threshold);
-}
-
-/**
-  * @brief Get FIFO threshold.
-  * @rmtoll FCR         FTH          LL_DMA_GetFIFOThreshold
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
-  *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
-  *         @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
-  *         @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-
-  return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FTH));
-}
-
-/**
-  * @brief Configure the FIFO .
-  * @rmtoll FCR         FTH          LL_DMA_ConfigFifo\n
-  *         FCR         DMDIS        LL_DMA_ConfigFifo
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @param  FifoMode This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_FIFOMODE_ENABLE
-  *         @arg @ref LL_DMA_FIFOMODE_DISABLE
-  * @param  FifoThreshold This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
-  *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
-  *         @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
-  *         @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint32_t FifoThreshold)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-
-  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FTH | DMA_SxFCR_DMDIS, FifoMode | FifoThreshold);
-}
-
-/**
-  * @brief Configure the Source and Destination addresses.
-  * @note   This API must not be called when the DMA stream is enabled.
-  * @rmtoll M0AR        M0A         LL_DMA_ConfigAddresses\n
-  *         PAR         PA          LL_DMA_ConfigAddresses
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @param  SrcAddress Between 0 to 0xFFFFFFFF
-  * @param  DstAddress Between 0 to 0xFFFFFFFF
-  * @param  Direction This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
-  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
-  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-
-  /* Direction Memory to Periph */
-  if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
-  {
-    WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, SrcAddress);
-    WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, DstAddress);
-  }
-  /* Direction Periph to Memory and Memory to Memory */
-  else
-  {
-    WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, SrcAddress);
-    WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, DstAddress);
-  }
-}
-
-/**
-  * @brief  Set the Memory address.
-  * @rmtoll M0AR        M0A         LL_DMA_SetMemoryAddress
-  * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
-  * @note   This API must not be called when the DMA stream is enabled.
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @param  MemoryAddress Between 0 to 0xFFFFFFFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-
-  WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, MemoryAddress);
-}
-
-/**
-  * @brief  Set the Peripheral address.
-  * @rmtoll PAR        PA         LL_DMA_SetPeriphAddress
-  * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
-  * @note   This API must not be called when the DMA stream is enabled.
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @param  PeriphAddress Between 0 to 0xFFFFFFFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t PeriphAddress)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-
-  WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, PeriphAddress);
-}
-
-/**
-  * @brief  Get the Memory address.
-  * @rmtoll M0AR        M0A         LL_DMA_GetMemoryAddress
-  * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval Between 0 to 0xFFFFFFFF
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-
-  return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR));
-}
-
-/**
-  * @brief  Get the Peripheral address.
-  * @rmtoll PAR        PA         LL_DMA_GetPeriphAddress
-  * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval Between 0 to 0xFFFFFFFF
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-
-  return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR));
-}
-
-/**
-  * @brief  Set the Memory to Memory Source address.
-  * @rmtoll PAR        PA         LL_DMA_SetM2MSrcAddress
-  * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
-  * @note   This API must not be called when the DMA stream is enabled.
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @param  MemoryAddress Between 0 to 0xFFFFFFFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-
-  WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, MemoryAddress);
-}
-
-/**
-  * @brief  Set the Memory to Memory Destination address.
-  * @rmtoll M0AR        M0A         LL_DMA_SetM2MDstAddress
-  * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
-  * @note   This API must not be called when the DMA stream is enabled.
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @param  MemoryAddress Between 0 to 0xFFFFFFFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-
-  WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, MemoryAddress);
-}
-
-/**
-  * @brief  Get the Memory to Memory Source address.
-  * @rmtoll PAR        PA         LL_DMA_GetM2MSrcAddress
-  * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval Between 0 to 0xFFFFFFFF
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-
-  return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR));
-}
-
-/**
-  * @brief  Get the Memory to Memory Destination address.
-  * @rmtoll M0AR        M0A         LL_DMA_GetM2MDstAddress
-  * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval Between 0 to 0xFFFFFFFF
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-
-  return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR));
-}
-
-/**
-  * @brief Set Memory 1 address (used in case of Double buffer mode).
-  * @rmtoll M1AR        M1A         LL_DMA_SetMemory1Address
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @param  Address Between 0 to 0xFFFFFFFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Address)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-
-  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M1AR, DMA_SxM1AR_M1A, Address);
-}
-
-/**
-  * @brief Get Memory 1 address (used in case of Double buffer mode).
-  * @rmtoll M1AR        M1A         LL_DMA_GetMemory1Address
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval Between 0 to 0xFFFFFFFF
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-
-  return (((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M1AR);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
-  * @{
-  */
-
-/**
-  * @brief Get Stream 0 half transfer flag.
-  * @rmtoll LISR  HTIF0    LL_DMA_IsActiveFlag_HT0
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT0(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF0) == (DMA_LISR_HTIF0)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief Get Stream 1 half transfer flag.
-  * @rmtoll LISR  HTIF1    LL_DMA_IsActiveFlag_HT1
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF1) == (DMA_LISR_HTIF1)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief Get Stream 2 half transfer flag.
-  * @rmtoll LISR  HTIF2    LL_DMA_IsActiveFlag_HT2
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF2) == (DMA_LISR_HTIF2)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief Get Stream 3 half transfer flag.
-  * @rmtoll LISR  HTIF3    LL_DMA_IsActiveFlag_HT3
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF3) == (DMA_LISR_HTIF3)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief Get Stream 4 half transfer flag.
-  * @rmtoll HISR  HTIF4    LL_DMA_IsActiveFlag_HT4
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF4) == (DMA_HISR_HTIF4)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief Get Stream 5 half transfer flag.
-  * @rmtoll HISR  HTIF0    LL_DMA_IsActiveFlag_HT5
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF5) == (DMA_HISR_HTIF5)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief Get Stream 6 half transfer flag.
-  * @rmtoll HISR  HTIF6    LL_DMA_IsActiveFlag_HT6
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF6) == (DMA_HISR_HTIF6)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief Get Stream 7 half transfer flag.
-  * @rmtoll HISR  HTIF7    LL_DMA_IsActiveFlag_HT7
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF7) == (DMA_HISR_HTIF7)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief Get Stream 0 transfer complete flag.
-  * @rmtoll LISR  TCIF0    LL_DMA_IsActiveFlag_TC0
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC0(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF0) == (DMA_LISR_TCIF0)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief Get Stream 1 transfer complete flag.
-  * @rmtoll LISR  TCIF1    LL_DMA_IsActiveFlag_TC1
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF1) == (DMA_LISR_TCIF1)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief Get Stream 2 transfer complete flag.
-  * @rmtoll LISR  TCIF2    LL_DMA_IsActiveFlag_TC2
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF2) == (DMA_LISR_TCIF2)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief Get Stream 3 transfer complete flag.
-  * @rmtoll LISR  TCIF3    LL_DMA_IsActiveFlag_TC3
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF3) == (DMA_LISR_TCIF3)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief Get Stream 4 transfer complete flag.
-  * @rmtoll HISR  TCIF4    LL_DMA_IsActiveFlag_TC4
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF4) == (DMA_HISR_TCIF4)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief Get Stream 5 transfer complete flag.
-  * @rmtoll HISR  TCIF0    LL_DMA_IsActiveFlag_TC5
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF5) == (DMA_HISR_TCIF5)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief Get Stream 6 transfer complete flag.
-  * @rmtoll HISR  TCIF6    LL_DMA_IsActiveFlag_TC6
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF6) == (DMA_HISR_TCIF6)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief Get Stream 7 transfer complete flag.
-  * @rmtoll HISR  TCIF7    LL_DMA_IsActiveFlag_TC7
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF7) == (DMA_HISR_TCIF7)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief Get Stream 0 transfer error flag.
-  * @rmtoll LISR  TEIF0    LL_DMA_IsActiveFlag_TE0
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE0(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF0) == (DMA_LISR_TEIF0)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief Get Stream 1 transfer error flag.
-  * @rmtoll LISR  TEIF1    LL_DMA_IsActiveFlag_TE1
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF1) == (DMA_LISR_TEIF1)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief Get Stream 2 transfer error flag.
-  * @rmtoll LISR  TEIF2    LL_DMA_IsActiveFlag_TE2
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF2) == (DMA_LISR_TEIF2)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief Get Stream 3 transfer error flag.
-  * @rmtoll LISR  TEIF3    LL_DMA_IsActiveFlag_TE3
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF3) == (DMA_LISR_TEIF3)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief Get Stream 4 transfer error flag.
-  * @rmtoll HISR  TEIF4    LL_DMA_IsActiveFlag_TE4
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF4) == (DMA_HISR_TEIF4)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief Get Stream 5 transfer error flag.
-  * @rmtoll HISR  TEIF0    LL_DMA_IsActiveFlag_TE5
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF5) == (DMA_HISR_TEIF5)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief Get Stream 6 transfer error flag.
-  * @rmtoll HISR  TEIF6    LL_DMA_IsActiveFlag_TE6
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF6) == (DMA_HISR_TEIF6)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief Get Stream 7 transfer error flag.
-  * @rmtoll HISR  TEIF7    LL_DMA_IsActiveFlag_TE7
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF7) == (DMA_HISR_TEIF7)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief Get Stream 0 direct mode error flag.
-  * @rmtoll LISR  DMEIF0    LL_DMA_IsActiveFlag_DME0
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME0(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF0) == (DMA_LISR_DMEIF0)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief Get Stream 1 direct mode error flag.
-  * @rmtoll LISR  DMEIF1    LL_DMA_IsActiveFlag_DME1
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME1(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF1) == (DMA_LISR_DMEIF1)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief Get Stream 2 direct mode error flag.
-  * @rmtoll LISR  DMEIF2    LL_DMA_IsActiveFlag_DME2
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME2(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF2) == (DMA_LISR_DMEIF2)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief Get Stream 3 direct mode error flag.
-  * @rmtoll LISR  DMEIF3    LL_DMA_IsActiveFlag_DME3
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME3(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF3) == (DMA_LISR_DMEIF3)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief Get Stream 4 direct mode error flag.
-  * @rmtoll HISR  DMEIF4    LL_DMA_IsActiveFlag_DME4
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME4(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF4) == (DMA_HISR_DMEIF4)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief Get Stream 5 direct mode error flag.
-  * @rmtoll HISR  DMEIF0    LL_DMA_IsActiveFlag_DME5
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME5(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF5) == (DMA_HISR_DMEIF5)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief Get Stream 6 direct mode error flag.
-  * @rmtoll HISR  DMEIF6    LL_DMA_IsActiveFlag_DME6
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME6(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF6) == (DMA_HISR_DMEIF6)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief Get Stream 7 direct mode error flag.
-  * @rmtoll HISR  DMEIF7    LL_DMA_IsActiveFlag_DME7
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME7(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF7) == (DMA_HISR_DMEIF7)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief Get Stream 0 FIFO error flag.
-  * @rmtoll LISR  FEIF0    LL_DMA_IsActiveFlag_FE0
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE0(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF0) == (DMA_LISR_FEIF0)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief Get Stream 1 FIFO error flag.
-  * @rmtoll LISR  FEIF1    LL_DMA_IsActiveFlag_FE1
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE1(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF1) == (DMA_LISR_FEIF1)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief Get Stream 2 FIFO error flag.
-  * @rmtoll LISR  FEIF2    LL_DMA_IsActiveFlag_FE2
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE2(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF2) == (DMA_LISR_FEIF2)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief Get Stream 3 FIFO error flag.
-  * @rmtoll LISR  FEIF3    LL_DMA_IsActiveFlag_FE3
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE3(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF3) == (DMA_LISR_FEIF3)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief Get Stream 4 FIFO error flag.
-  * @rmtoll HISR  FEIF4    LL_DMA_IsActiveFlag_FE4
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE4(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF4) == (DMA_HISR_FEIF4)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief Get Stream 5 FIFO error flag.
-  * @rmtoll HISR  FEIF0    LL_DMA_IsActiveFlag_FE5
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE5(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF5) == (DMA_HISR_FEIF5)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief Get Stream 6 FIFO error flag.
-  * @rmtoll HISR  FEIF6    LL_DMA_IsActiveFlag_FE6
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE6(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF6) == (DMA_HISR_FEIF6)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief Get Stream 7 FIFO error flag.
-  * @rmtoll HISR  FEIF7    LL_DMA_IsActiveFlag_FE7
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE7(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF7) == (DMA_HISR_FEIF7)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief Clear Stream 0 half transfer flag.
-  * @rmtoll LIFCR  CHTIF0    LL_DMA_ClearFlag_HT0
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_HT0(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CHTIF0);
-}
-
-/**
-  * @brief Clear Stream 1 half transfer flag.
-  * @rmtoll LIFCR  CHTIF1    LL_DMA_ClearFlag_HT1
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CHTIF1);
-}
-
-/**
-  * @brief Clear Stream 2 half transfer flag.
-  * @rmtoll LIFCR  CHTIF2    LL_DMA_ClearFlag_HT2
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CHTIF2);
-}
-
-/**
-  * @brief Clear Stream 3 half transfer flag.
-  * @rmtoll LIFCR  CHTIF3    LL_DMA_ClearFlag_HT3
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CHTIF3);
-}
-
-/**
-  * @brief Clear Stream 4 half transfer flag.
-  * @rmtoll HIFCR  CHTIF4    LL_DMA_ClearFlag_HT4
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CHTIF4);
-}
-
-/**
-  * @brief Clear Stream 5 half transfer flag.
-  * @rmtoll HIFCR  CHTIF5    LL_DMA_ClearFlag_HT5
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CHTIF5);
-}
-
-/**
-  * @brief Clear Stream 6 half transfer flag.
-  * @rmtoll HIFCR  CHTIF6    LL_DMA_ClearFlag_HT6
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CHTIF6);
-}
-
-/**
-  * @brief Clear Stream 7 half transfer flag.
-  * @rmtoll HIFCR  CHTIF7    LL_DMA_ClearFlag_HT7
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CHTIF7);
-}
-
-/**
-  * @brief Clear Stream 0 transfer complete flag.
-  * @rmtoll LIFCR  CTCIF0    LL_DMA_ClearFlag_TC0
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_TC0(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTCIF0);
-}
-
-/**
-  * @brief Clear Stream 1 transfer complete flag.
-  * @rmtoll LIFCR  CTCIF1    LL_DMA_ClearFlag_TC1
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTCIF1);
-}
-
-/**
-  * @brief Clear Stream 2 transfer complete flag.
-  * @rmtoll LIFCR  CTCIF2    LL_DMA_ClearFlag_TC2
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTCIF2);
-}
-
-/**
-  * @brief Clear Stream 3 transfer complete flag.
-  * @rmtoll LIFCR  CTCIF3    LL_DMA_ClearFlag_TC3
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTCIF3);
-}
-
-/**
-  * @brief Clear Stream 4 transfer complete flag.
-  * @rmtoll HIFCR  CTCIF4    LL_DMA_ClearFlag_TC4
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTCIF4);
-}
-
-/**
-  * @brief Clear Stream 5 transfer complete flag.
-  * @rmtoll HIFCR  CTCIF5    LL_DMA_ClearFlag_TC5
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTCIF5);
-}
-
-/**
-  * @brief Clear Stream 6 transfer complete flag.
-  * @rmtoll HIFCR  CTCIF6    LL_DMA_ClearFlag_TC6
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTCIF6);
-}
-
-/**
-  * @brief Clear Stream 7 transfer complete flag.
-  * @rmtoll HIFCR  CTCIF7    LL_DMA_ClearFlag_TC7
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTCIF7);
-}
-
-/**
-  * @brief Clear Stream 0 transfer error flag.
-  * @rmtoll LIFCR  CTEIF0    LL_DMA_ClearFlag_TE0
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_TE0(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTEIF0);
-}
-
-/**
-  * @brief Clear Stream 1 transfer error flag.
-  * @rmtoll LIFCR  CTEIF1    LL_DMA_ClearFlag_TE1
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTEIF1);
-}
-
-/**
-  * @brief Clear Stream 2 transfer error flag.
-  * @rmtoll LIFCR  CTEIF2    LL_DMA_ClearFlag_TE2
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTEIF2);
-}
-
-/**
-  * @brief Clear Stream 3 transfer error flag.
-  * @rmtoll LIFCR  CTEIF3    LL_DMA_ClearFlag_TE3
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTEIF3);
-}
-
-/**
-  * @brief Clear Stream 4 transfer error flag.
-  * @rmtoll HIFCR  CTEIF4    LL_DMA_ClearFlag_TE4
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTEIF4);
-}
-
-/**
-  * @brief Clear Stream 5 transfer error flag.
-  * @rmtoll HIFCR  CTEIF5    LL_DMA_ClearFlag_TE5
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTEIF5);
-}
-
-/**
-  * @brief Clear Stream 6 transfer error flag.
-  * @rmtoll HIFCR  CTEIF6    LL_DMA_ClearFlag_TE6
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTEIF6);
-}
-
-/**
-  * @brief Clear Stream 7 transfer error flag.
-  * @rmtoll HIFCR  CTEIF7    LL_DMA_ClearFlag_TE7
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTEIF7);
-}
-
-/**
-  * @brief Clear Stream 0 direct mode error flag.
-  * @rmtoll LIFCR  CDMEIF0    LL_DMA_ClearFlag_DME0
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_DME0(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CDMEIF0);
-}
-
-/**
-  * @brief Clear Stream 1 direct mode error flag.
-  * @rmtoll LIFCR  CDMEIF1    LL_DMA_ClearFlag_DME1
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_DME1(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CDMEIF1);
-}
-
-/**
-  * @brief Clear Stream 2 direct mode error flag.
-  * @rmtoll LIFCR  CDMEIF2    LL_DMA_ClearFlag_DME2
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_DME2(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CDMEIF2);
-}
-
-/**
-  * @brief Clear Stream 3 direct mode error flag.
-  * @rmtoll LIFCR  CDMEIF3    LL_DMA_ClearFlag_DME3
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_DME3(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CDMEIF3);
-}
-
-/**
-  * @brief Clear Stream 4 direct mode error flag.
-  * @rmtoll HIFCR  CDMEIF4    LL_DMA_ClearFlag_DME4
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_DME4(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CDMEIF4);
-}
-
-/**
-  * @brief Clear Stream 5 direct mode error flag.
-  * @rmtoll HIFCR  CDMEIF5    LL_DMA_ClearFlag_DME5
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_DME5(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CDMEIF5);
-}
-
-/**
-  * @brief Clear Stream 6 direct mode error flag.
-  * @rmtoll HIFCR  CDMEIF6    LL_DMA_ClearFlag_DME6
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_DME6(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CDMEIF6);
-}
-
-/**
-  * @brief Clear Stream 7 direct mode error flag.
-  * @rmtoll HIFCR  CDMEIF7    LL_DMA_ClearFlag_DME7
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_DME7(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CDMEIF7);
-}
-
-/**
-  * @brief Clear Stream 0 FIFO error flag.
-  * @rmtoll LIFCR  CFEIF0    LL_DMA_ClearFlag_FE0
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_FE0(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CFEIF0);
-}
-
-/**
-  * @brief Clear Stream 1 FIFO error flag.
-  * @rmtoll LIFCR  CFEIF1    LL_DMA_ClearFlag_FE1
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_FE1(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CFEIF1);
-}
-
-/**
-  * @brief Clear Stream 2 FIFO error flag.
-  * @rmtoll LIFCR  CFEIF2    LL_DMA_ClearFlag_FE2
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_FE2(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CFEIF2);
-}
-
-/**
-  * @brief Clear Stream 3 FIFO error flag.
-  * @rmtoll LIFCR  CFEIF3    LL_DMA_ClearFlag_FE3
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_FE3(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CFEIF3);
-}
-
-/**
-  * @brief Clear Stream 4 FIFO error flag.
-  * @rmtoll HIFCR  CFEIF4    LL_DMA_ClearFlag_FE4
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_FE4(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CFEIF4);
-}
-
-/**
-  * @brief Clear Stream 5 FIFO error flag.
-  * @rmtoll HIFCR  CFEIF5    LL_DMA_ClearFlag_FE5
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_FE5(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CFEIF5);
-}
-
-/**
-  * @brief Clear Stream 6 FIFO error flag.
-  * @rmtoll HIFCR  CFEIF6    LL_DMA_ClearFlag_FE6
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_FE6(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CFEIF6);
-}
-
-/**
-  * @brief Clear Stream 7 FIFO error flag.
-  * @rmtoll HIFCR  CFEIF7    LL_DMA_ClearFlag_FE7
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_FE7(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CFEIF7);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup DMA_LL_EF_IT_Management IT_Management
-  * @{
-  */
-
-/**
-  * @brief Enable Half transfer interrupt.
-  * @rmtoll CR        HTIE         LL_DMA_EnableIT_HT
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-
-  SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_HTIE);
-}
-
-/**
-  * @brief Enable Transfer error interrupt.
-  * @rmtoll CR        TEIE         LL_DMA_EnableIT_TE
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-
-  SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TEIE);
-}
-
-/**
-  * @brief Enable Transfer complete interrupt.
-  * @rmtoll CR        TCIE         LL_DMA_EnableIT_TC
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-
-  SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TCIE);
-}
-
-/**
-  * @brief Enable Direct mode error interrupt.
-  * @rmtoll CR        DMEIE         LL_DMA_EnableIT_DME
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_EnableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-
-  SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DMEIE);
-}
-
-/**
-  * @brief Enable FIFO error interrupt.
-  * @rmtoll FCR        FEIE         LL_DMA_EnableIT_FE
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_EnableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-
-  SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FEIE);
-}
-
-/**
-  * @brief Disable Half transfer interrupt.
-  * @rmtoll CR        HTIE         LL_DMA_DisableIT_HT
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-
-  CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_HTIE);
-}
-
-/**
-  * @brief Disable Transfer error interrupt.
-  * @rmtoll CR        TEIE         LL_DMA_DisableIT_TE
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-
-  CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TEIE);
-}
-
-/**
-  * @brief Disable Transfer complete interrupt.
-  * @rmtoll CR        TCIE         LL_DMA_DisableIT_TC
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-
-  CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TCIE);
-}
-
-/**
-  * @brief Disable Direct mode error interrupt.
-  * @rmtoll CR        DMEIE         LL_DMA_DisableIT_DME
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_DisableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-
-  CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DMEIE);
-}
-
-/**
-  * @brief Disable FIFO error interrupt.
-  * @rmtoll FCR        FEIE         LL_DMA_DisableIT_FE
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_DisableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-
-  CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FEIE);
-}
-
-/**
-  * @brief Check if Half transfer interrup is enabled.
-  * @rmtoll CR        HTIE         LL_DMA_IsEnabledIT_HT
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-
-  return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_HTIE) == DMA_SxCR_HTIE) ? 1UL : 0UL);
-}
-
-/**
-  * @brief Check if Transfer error nterrup is enabled.
-  * @rmtoll CR        TEIE         LL_DMA_IsEnabledIT_TE
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-
-  return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TEIE) == DMA_SxCR_TEIE) ? 1UL : 0UL);
-}
-
-/**
-  * @brief Check if Transfer complete interrup is enabled.
-  * @rmtoll CR        TCIE         LL_DMA_IsEnabledIT_TC
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-
-  return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TCIE) == DMA_SxCR_TCIE) ? 1UL : 0UL);
-}
-
-/**
-  * @brief Check if Direct mode error interrupt is enabled.
-  * @rmtoll CR        DMEIE         LL_DMA_IsEnabledIT_DME
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-
-  return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DMEIE) == DMA_SxCR_DMEIE) ? 1UL : 0UL);
-}
-
-/**
-  * @brief Check if FIFO error interrup is enabled.
-  * @rmtoll FCR        FEIE         LL_DMA_IsEnabledIT_FE
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-
-  return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FEIE) == DMA_SxFCR_FEIE) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
-  * @{
-  */
-
-uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct);
-uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream);
-void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
-
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* DMA1 || DMA2 */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32H7xx_LL_DMA_H */
-
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_ll_dma.h
+  * @author  MCD Application Team
+  * @brief   Header file of DMA LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_LL_DMA_H
+#define STM32H7xx_LL_DMA_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx.h"
+#include "stm32h7xx_ll_dmamux.h"
+
+/** @addtogroup STM32H7xx_LL_Driver
+  * @{
+  */
+
+#if defined (DMA1) || defined (DMA2)
+
+/** @defgroup DMA_LL DMA
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup DMA_LL_Private_Variables DMA Private Variables
+  * @{
+  */
+/* Array used to get the DMA stream register offset versus stream index LL_DMA_STREAM_x */
+static const uint8_t LL_DMA_STR_OFFSET_TAB[] =
+{
+  (uint8_t)(DMA1_Stream0_BASE - DMA1_BASE),
+  (uint8_t)(DMA1_Stream1_BASE - DMA1_BASE),
+  (uint8_t)(DMA1_Stream2_BASE - DMA1_BASE),
+  (uint8_t)(DMA1_Stream3_BASE - DMA1_BASE),
+  (uint8_t)(DMA1_Stream4_BASE - DMA1_BASE),
+  (uint8_t)(DMA1_Stream5_BASE - DMA1_BASE),
+  (uint8_t)(DMA1_Stream6_BASE - DMA1_BASE),
+  (uint8_t)(DMA1_Stream7_BASE - DMA1_BASE)
+};
+
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+
+/**
+  * @brief  Helper macro to convert DMA Instance DMAx into DMAMUX channel
+  * @note   DMAMUX channel 0 to 7 are mapped to DMA1 stream 0 to 7.
+  *         DMAMUX channel 8 to 15 are mapped to DMA2 stream 0 to 7.
+  * @param  __DMA_INSTANCE__ DMAx
+  * @retval Channel_Offset (LL_DMAMUX_CHANNEL_8 or 0).
+  */
+#define LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(__DMA_INSTANCE__)   \
+(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) ? 0UL : 8UL)
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
+  * @{
+  */
+typedef struct
+{
+  uint32_t PeriphOrM2MSrcAddress;  /*!< Specifies the peripheral base address for DMA transfer
+                                        or as Source base address in case of memory to memory transfer direction.
+
+                                        This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
+
+  uint32_t MemoryOrM2MDstAddress;  /*!< Specifies the memory base address for DMA transfer
+                                        or as Destination base address in case of memory to memory transfer direction.
+
+                                        This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
+
+  uint32_t Direction;              /*!< Specifies if the data will be transferred from memory to peripheral,
+                                        from memory to memory or from peripheral to memory.
+                                        This parameter can be a value of @ref DMA_LL_EC_DIRECTION
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
+
+  uint32_t Mode;                   /*!< Specifies the normal or circular operation mode.
+                                        This parameter can be a value of @ref DMA_LL_EC_MODE
+                                        @note The circular buffer mode cannot be used if the memory to memory
+                                              data transfer direction is configured on the selected Stream
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
+
+  uint32_t PeriphOrM2MSrcIncMode;  /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
+                                        is incremented or not.
+                                        This parameter can be a value of @ref DMA_LL_EC_PERIPH
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
+
+  uint32_t MemoryOrM2MDstIncMode;  /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
+                                        is incremented or not.
+                                        This parameter can be a value of @ref DMA_LL_EC_MEMORY
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
+
+  uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
+                                        in case of memory to memory transfer direction.
+                                        This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
+
+  uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
+                                        in case of memory to memory transfer direction.
+                                        This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
+
+  uint32_t NbData;                 /*!< Specifies the number of data to transfer, in data unit.
+                                        The data unit is equal to the source buffer configuration set in PeripheralSize
+                                        or MemorySize parameters depending in the transfer direction.
+                                        This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
+
+  uint32_t PeriphRequest;          /*!< Specifies the peripheral request.
+                                        This parameter can be a value of @ref DMAMUX1_Request_selection
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */
+
+  uint32_t Priority;               /*!< Specifies the channel priority level.
+                                        This parameter can be a value of @ref DMA_LL_EC_PRIORITY
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetStreamPriorityLevel(). */
+
+  uint32_t FIFOMode;               /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
+                                        This parameter can be a value of @ref DMA_LL_FIFOMODE
+                                        @note The Direct mode (FIFO mode disabled) cannot be used if the
+                                        memory-to-memory data transfer is configured on the selected stream
+
+                                        This feature can be modified afterwards using unitary functions @ref LL_DMA_EnableFifoMode() or @ref LL_DMA_EnableFifoMode() . */
+
+  uint32_t FIFOThreshold;          /*!< Specifies the FIFO threshold level.
+                                        This parameter can be a value of @ref DMA_LL_EC_FIFOTHRESHOLD
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetFIFOThreshold(). */
+
+  uint32_t MemBurst;               /*!< Specifies the Burst transfer configuration for the memory transfers.
+                                        It specifies the amount of data to be transferred in a single non interruptible
+                                        transaction.
+                                        This parameter can be a value of @ref DMA_LL_EC_MBURST
+                                        @note The burst mode is possible only if the address Increment mode is enabled.
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryBurstxfer(). */
+
+  uint32_t PeriphBurst;            /*!< Specifies the Burst transfer configuration for the peripheral transfers.
+                                        It specifies the amount of data to be transferred in a single non interruptible
+                                        transaction.
+                                        This parameter can be a value of @ref DMA_LL_EC_PBURST
+                                        @note The burst mode is possible only if the address Increment mode is enabled.
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphBurstxfer(). */
+
+} LL_DMA_InitTypeDef;
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
+  * @{
+  */
+
+/** @defgroup DMA_LL_EC_STREAM STREAM
+  * @{
+  */
+#define LL_DMA_STREAM_0                   0x00000000U
+#define LL_DMA_STREAM_1                   0x00000001U
+#define LL_DMA_STREAM_2                   0x00000002U
+#define LL_DMA_STREAM_3                   0x00000003U
+#define LL_DMA_STREAM_4                   0x00000004U
+#define LL_DMA_STREAM_5                   0x00000005U
+#define LL_DMA_STREAM_6                   0x00000006U
+#define LL_DMA_STREAM_7                   0x00000007U
+#define LL_DMA_STREAM_ALL                 0xFFFF0000U
+/**
+  * @}
+  */
+
+
+/** @defgroup DMA_LL_EC_DIRECTION DIRECTION
+  * @{
+  */
+#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U               /*!< Peripheral to memory direction */
+#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_SxCR_DIR_0            /*!< Memory to peripheral direction */
+#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_SxCR_DIR_1            /*!< Memory to memory direction     */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_MODE MODE
+  * @{
+  */
+#define LL_DMA_MODE_NORMAL                0x00000000U               /*!< Normal Mode                  */
+#define LL_DMA_MODE_CIRCULAR              DMA_SxCR_CIRC             /*!< Circular Mode                */
+#define LL_DMA_MODE_PFCTRL                DMA_SxCR_PFCTRL           /*!< Peripheral flow control mode */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_DOUBLEBUFFER_MODE DOUBLE BUFFER MODE
+  * @{
+  */
+#define LL_DMA_DOUBLEBUFFER_MODE_DISABLE  0x00000000U               /*!< Disable double buffering mode */
+#define LL_DMA_DOUBLEBUFFER_MODE_ENABLE   DMA_SxCR_DBM              /*!< Enable double buffering mode  */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_PERIPH PERIPH
+  * @{
+  */
+#define LL_DMA_PERIPH_NOINCREMENT         0x00000000U               /*!< Peripheral increment mode Disable */
+#define LL_DMA_PERIPH_INCREMENT           DMA_SxCR_PINC             /*!< Peripheral increment mode Enable  */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_MEMORY MEMORY
+  * @{
+  */
+#define LL_DMA_MEMORY_NOINCREMENT         0x00000000U               /*!< Memory increment mode Disable */
+#define LL_DMA_MEMORY_INCREMENT           DMA_SxCR_MINC             /*!< Memory increment mode Enable  */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_PDATAALIGN PDATAALIGN
+  * @{
+  */
+#define LL_DMA_PDATAALIGN_BYTE            0x00000000U               /*!< Peripheral data alignment : Byte     */
+#define LL_DMA_PDATAALIGN_HALFWORD        DMA_SxCR_PSIZE_0          /*!< Peripheral data alignment : HalfWord */
+#define LL_DMA_PDATAALIGN_WORD            DMA_SxCR_PSIZE_1          /*!< Peripheral data alignment : Word     */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_MDATAALIGN MDATAALIGN
+  * @{
+  */
+#define LL_DMA_MDATAALIGN_BYTE            0x00000000U               /*!< Memory data alignment : Byte     */
+#define LL_DMA_MDATAALIGN_HALFWORD        DMA_SxCR_MSIZE_0          /*!< Memory data alignment : HalfWord */
+#define LL_DMA_MDATAALIGN_WORD            DMA_SxCR_MSIZE_1          /*!< Memory data alignment : Word     */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_OFFSETSIZE OFFSETSIZE
+  * @{
+  */
+#define LL_DMA_OFFSETSIZE_PSIZE           0x00000000U               /*!< Peripheral increment offset size is linked to the PSIZE           */
+#define LL_DMA_OFFSETSIZE_FIXEDTO4        DMA_SxCR_PINCOS           /*!< Peripheral increment offset size is fixed to 4 (32-bit alignment) */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_PRIORITY PRIORITY
+  * @{
+  */
+#define LL_DMA_PRIORITY_LOW               0x00000000U               /*!< Priority level : Low       */
+#define LL_DMA_PRIORITY_MEDIUM            DMA_SxCR_PL_0             /*!< Priority level : Medium    */
+#define LL_DMA_PRIORITY_HIGH              DMA_SxCR_PL_1             /*!< Priority level : High      */
+#define LL_DMA_PRIORITY_VERYHIGH          DMA_SxCR_PL               /*!< Priority level : Very_High */
+/**
+  * @}
+  */
+
+
+/** @defgroup DMA_LL_EC_MBURST MBURST
+  * @{
+  */
+#define LL_DMA_MBURST_SINGLE              0x00000000U                             /*!< Memory burst single transfer configuration      */
+#define LL_DMA_MBURST_INC4                DMA_SxCR_MBURST_0                       /*!< Memory burst of 4 beats transfer configuration  */
+#define LL_DMA_MBURST_INC8                DMA_SxCR_MBURST_1                       /*!< Memory burst of 8 beats transfer configuration  */
+#define LL_DMA_MBURST_INC16               (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1) /*!< Memory burst of 16 beats transfer configuration */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_PBURST PBURST
+  * @{
+  */
+#define LL_DMA_PBURST_SINGLE              0x00000000U                             /*!< Peripheral burst single transfer configuration      */
+#define LL_DMA_PBURST_INC4                DMA_SxCR_PBURST_0                       /*!< Peripheral burst of 4 beats transfer configuration  */
+#define LL_DMA_PBURST_INC8                DMA_SxCR_PBURST_1                       /*!< Peripheral burst of 8 beats transfer configuration  */
+#define LL_DMA_PBURST_INC16               (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1) /*!< Peripheral burst of 16 beats transfer configuration */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_FIFOMODE DMA_LL_FIFOMODE
+  * @{
+  */
+#define LL_DMA_FIFOMODE_DISABLE           0x00000000U                             /*!< FIFO mode disable (direct mode is enabled) */
+#define LL_DMA_FIFOMODE_ENABLE            DMA_SxFCR_DMDIS                         /*!< FIFO mode enable                           */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_FIFOSTATUS_0 FIFOSTATUS 0
+  * @{
+  */
+#define LL_DMA_FIFOSTATUS_0_25            0x00000000U                             /*!< 0 < fifo_level < 1/4    */
+#define LL_DMA_FIFOSTATUS_25_50           DMA_SxFCR_FS_0                          /*!< 1/4 < fifo_level < 1/2  */
+#define LL_DMA_FIFOSTATUS_50_75           DMA_SxFCR_FS_1                          /*!< 1/2 < fifo_level < 3/4  */
+#define LL_DMA_FIFOSTATUS_75_100          (DMA_SxFCR_FS_1 | DMA_SxFCR_FS_0)       /*!< 3/4 < fifo_level < full */
+#define LL_DMA_FIFOSTATUS_EMPTY           DMA_SxFCR_FS_2                          /*!< FIFO is empty           */
+#define LL_DMA_FIFOSTATUS_FULL            (DMA_SxFCR_FS_2 | DMA_SxFCR_FS_0)       /*!< FIFO is full            */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_FIFOTHRESHOLD FIFOTHRESHOLD
+  * @{
+  */
+#define LL_DMA_FIFOTHRESHOLD_1_4          0x00000000U                             /*!< FIFO threshold 1 quart full configuration  */
+#define LL_DMA_FIFOTHRESHOLD_1_2          DMA_SxFCR_FTH_0                         /*!< FIFO threshold half full configuration     */
+#define LL_DMA_FIFOTHRESHOLD_3_4          DMA_SxFCR_FTH_1                         /*!< FIFO threshold 3 quarts full configuration */
+#define LL_DMA_FIFOTHRESHOLD_FULL         DMA_SxFCR_FTH                           /*!< FIFO threshold full configuration          */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM
+  * @{
+  */
+#define LL_DMA_CURRENTTARGETMEM0          0x00000000U                             /*!< Set CurrentTarget Memory to Memory 0  */
+#define LL_DMA_CURRENTTARGETMEM1          DMA_SxCR_CT                             /*!< Set CurrentTarget Memory to Memory 1  */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
+  * @{
+  */
+
+/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
+  * @{
+  */
+/**
+  * @brief  Write a value in DMA register
+  * @param  __INSTANCE__ DMA Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in DMA register
+  * @param  __INSTANCE__ DMA Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxStreamy
+  * @{
+  */
+/**
+  * @brief  Convert DMAx_Streamy into DMAx
+  * @param  __STREAM_INSTANCE__ DMAx_Streamy
+  * @retval DMAx
+  */
+#define __LL_DMA_GET_INSTANCE(__STREAM_INSTANCE__)   \
+(((uint32_t)(__STREAM_INSTANCE__) > ((uint32_t)DMA1_Stream7)) ?  DMA2 : DMA1)
+
+/**
+  * @brief  Convert DMAx_Streamy into LL_DMA_STREAM_y
+  * @param  __STREAM_INSTANCE__ DMAx_Streamy
+  * @retval LL_DMA_STREAM_y
+  */
+#define __LL_DMA_GET_STREAM(__STREAM_INSTANCE__)   \
+(((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream0)) ? LL_DMA_STREAM_0 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream0)) ? LL_DMA_STREAM_0 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream1)) ? LL_DMA_STREAM_1 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream1)) ? LL_DMA_STREAM_1 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream2)) ? LL_DMA_STREAM_2 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream2)) ? LL_DMA_STREAM_2 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream3)) ? LL_DMA_STREAM_3 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream3)) ? LL_DMA_STREAM_3 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream4)) ? LL_DMA_STREAM_4 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream4)) ? LL_DMA_STREAM_4 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream5)) ? LL_DMA_STREAM_5 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream5)) ? LL_DMA_STREAM_5 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream6)) ? LL_DMA_STREAM_6 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream6)) ? LL_DMA_STREAM_6 : \
+ LL_DMA_STREAM_7)
+
+/**
+  * @brief  Convert DMA Instance DMAx and LL_DMA_STREAM_y into DMAx_Streamy
+  * @param  __DMA_INSTANCE__ DMAx
+  * @param  __STREAM__ LL_DMA_STREAM_y
+  * @retval DMAx_Streamy
+  */
+#define __LL_DMA_GET_STREAM_INSTANCE(__DMA_INSTANCE__, __STREAM__)   \
+((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA1_Stream0 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA2_Stream0 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA1_Stream1 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA2_Stream1 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA1_Stream2 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA2_Stream2 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA1_Stream3 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA2_Stream3 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA1_Stream4 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA2_Stream4 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA1_Stream5 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA2_Stream5 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA1_Stream6 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA2_Stream6 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_7))) ? DMA1_Stream7 : \
+ DMA2_Stream7)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
+ * @{
+ */
+
+/** @defgroup DMA_LL_EF_Configuration Configuration
+  * @{
+  */
+/**
+  * @brief Enable DMA stream.
+  * @rmtoll CR          EN            LL_DMA_EnableStream
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_EnableStream(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_EN);
+}
+
+/**
+  * @brief Disable DMA stream.
+  * @rmtoll CR          EN            LL_DMA_DisableStream
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_DisableStream(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_EN);
+}
+
+/**
+  * @brief Check if DMA stream is enabled or disabled.
+  * @rmtoll CR          EN            LL_DMA_IsEnabledStream
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_EN) == (DMA_SxCR_EN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Configure all parameters linked to DMA transfer.
+  * @rmtoll CR          DIR           LL_DMA_ConfigTransfer\n
+  *         CR          CIRC          LL_DMA_ConfigTransfer\n
+  *         CR          PINC          LL_DMA_ConfigTransfer\n
+  *         CR          MINC          LL_DMA_ConfigTransfer\n
+  *         CR          PSIZE         LL_DMA_ConfigTransfer\n
+  *         CR          MSIZE         LL_DMA_ConfigTransfer\n
+  *         CR          PL            LL_DMA_ConfigTransfer\n
+  *         CR          PFCTRL        LL_DMA_ConfigTransfer
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  Configuration This parameter must be a combination of all the following values:
+  *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+  *         @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR  or @ref LL_DMA_MODE_PFCTRL
+  *         @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
+  *         @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
+  *         @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
+  *         @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
+  *         @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
+  *@retval None
+  */
+__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configuration)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR,
+             DMA_SxCR_DIR | DMA_SxCR_CIRC | DMA_SxCR_PINC | DMA_SxCR_MINC | DMA_SxCR_PSIZE | DMA_SxCR_MSIZE | DMA_SxCR_PL | DMA_SxCR_PFCTRL,
+             Configuration);
+}
+
+/**
+  * @brief Set Data transfer direction (read from peripheral or from memory).
+  * @rmtoll CR          DIR           LL_DMA_SetDataTransferDirection
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  Direction This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
+  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
+  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t  Direction)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DIR, Direction);
+}
+
+/**
+  * @brief Get Data transfer direction (read from peripheral or from memory).
+  * @rmtoll CR          DIR           LL_DMA_GetDataTransferDirection
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
+  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
+  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DIR));
+}
+
+/**
+  * @brief Set DMA mode normal, circular or peripheral flow control.
+  * @rmtoll CR          CIRC           LL_DMA_SetMode\n
+  *         CR          PFCTRL         LL_DMA_SetMode
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  Mode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_MODE_NORMAL
+  *         @arg @ref LL_DMA_MODE_CIRCULAR
+  *         @arg @ref LL_DMA_MODE_PFCTRL
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mode)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL, Mode);
+}
+
+/**
+  * @brief Get DMA mode normal, circular or peripheral flow control.
+  * @rmtoll CR          CIRC           LL_DMA_GetMode\n
+  *         CR          PFCTRL         LL_DMA_GetMode
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_MODE_NORMAL
+  *         @arg @ref LL_DMA_MODE_CIRCULAR
+  *         @arg @ref LL_DMA_MODE_PFCTRL
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL));
+}
+
+/**
+  * @brief Set Peripheral increment mode.
+  * @rmtoll CR          PINC           LL_DMA_SetPeriphIncMode
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  IncrementMode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_PERIPH_NOINCREMENT
+  *         @arg @ref LL_DMA_PERIPH_INCREMENT
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINC, IncrementMode);
+}
+
+/**
+  * @brief Get Peripheral increment mode.
+  * @rmtoll CR          PINC           LL_DMA_GetPeriphIncMode
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_PERIPH_NOINCREMENT
+  *         @arg @ref LL_DMA_PERIPH_INCREMENT
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINC));
+}
+
+/**
+  * @brief Set Memory increment mode.
+  * @rmtoll CR          MINC           LL_DMA_SetMemoryIncMode
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  IncrementMode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_MEMORY_NOINCREMENT
+  *         @arg @ref LL_DMA_MEMORY_INCREMENT
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MINC, IncrementMode);
+}
+
+/**
+  * @brief Get Memory increment mode.
+  * @rmtoll CR          MINC           LL_DMA_GetMemoryIncMode
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_MEMORY_NOINCREMENT
+  *         @arg @ref LL_DMA_MEMORY_INCREMENT
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MINC));
+}
+
+/**
+  * @brief Set Peripheral size.
+  * @rmtoll CR          PSIZE           LL_DMA_SetPeriphSize
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  Size This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_PDATAALIGN_BYTE
+  *         @arg @ref LL_DMA_PDATAALIGN_HALFWORD
+  *         @arg @ref LL_DMA_PDATAALIGN_WORD
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t  Size)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PSIZE, Size);
+}
+
+/**
+  * @brief Get Peripheral size.
+  * @rmtoll CR          PSIZE           LL_DMA_GetPeriphSize
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_PDATAALIGN_BYTE
+  *         @arg @ref LL_DMA_PDATAALIGN_HALFWORD
+  *         @arg @ref LL_DMA_PDATAALIGN_WORD
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PSIZE));
+}
+
+/**
+  * @brief Set Memory size.
+  * @rmtoll CR          MSIZE           LL_DMA_SetMemorySize
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  Size This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_MDATAALIGN_BYTE
+  *         @arg @ref LL_DMA_MDATAALIGN_HALFWORD
+  *         @arg @ref LL_DMA_MDATAALIGN_WORD
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t  Size)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MSIZE, Size);
+}
+
+/**
+  * @brief Get Memory size.
+  * @rmtoll CR          MSIZE           LL_DMA_GetMemorySize
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_MDATAALIGN_BYTE
+  *         @arg @ref LL_DMA_MDATAALIGN_HALFWORD
+  *         @arg @ref LL_DMA_MDATAALIGN_WORD
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MSIZE));
+}
+
+/**
+  * @brief Set Peripheral increment offset size.
+  * @rmtoll CR          PINCOS           LL_DMA_SetIncOffsetSize
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  OffsetSize This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_OFFSETSIZE_PSIZE
+  *         @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t OffsetSize)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINCOS, OffsetSize);
+}
+
+/**
+  * @brief Get Peripheral increment offset size.
+  * @rmtoll CR          PINCOS           LL_DMA_GetIncOffsetSize
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_OFFSETSIZE_PSIZE
+  *         @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINCOS));
+}
+
+/**
+  * @brief Set Stream priority level.
+  * @rmtoll CR          PL           LL_DMA_SetStreamPriorityLevel
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  Priority This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_PRIORITY_LOW
+  *         @arg @ref LL_DMA_PRIORITY_MEDIUM
+  *         @arg @ref LL_DMA_PRIORITY_HIGH
+  *         @arg @ref LL_DMA_PRIORITY_VERYHIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t  Priority)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PL, Priority);
+}
+
+/**
+  * @brief Get Stream priority level.
+  * @rmtoll CR          PL           LL_DMA_GetStreamPriorityLevel
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_PRIORITY_LOW
+  *         @arg @ref LL_DMA_PRIORITY_MEDIUM
+  *         @arg @ref LL_DMA_PRIORITY_HIGH
+  *         @arg @ref LL_DMA_PRIORITY_VERYHIGH
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PL));
+}
+
+/**
+  * @brief Enable DMA stream bufferable transfer.
+  * @rmtoll CR          TRBUFF            LL_DMA_EnableBufferableTransfer
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_EnableBufferableTransfer(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TRBUFF);
+}
+
+/**
+  * @brief Disable DMA stream bufferable transfer.
+  * @rmtoll CR          TRBUFF            LL_DMA_DisableBufferableTransfer
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_DisableBufferableTransfer(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TRBUFF);
+}
+
+/**
+  * @brief Set Number of data to transfer.
+  * @rmtoll NDTR          NDT           LL_DMA_SetDataLength
+  * @note   This action has no effect if
+  *         stream is enabled.
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  NbData Between 0 to 0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t NbData)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->NDTR, DMA_SxNDT, NbData);
+}
+
+/**
+  * @brief Get Number of data to transfer.
+  * @rmtoll NDTR          NDT           LL_DMA_GetDataLength
+  * @note   Once the stream is enabled, the return value indicate the
+  *         remaining bytes to be transmitted.
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Between 0 to 0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->NDTR, DMA_SxNDT));
+}
+/**
+  * @brief  Set DMA request for DMA Streams on DMAMUX Channel x.
+  * @note   DMAMUX channel 0 to 7 are mapped to DMA1 stream 0 to 7.
+  *         DMAMUX channel 8 to 15 are mapped to DMA2 stream 0 to 7.
+  * @rmtoll CxCR         DMAREQ_ID     LL_DMA_SetPeriphRequest
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  Request This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX1_REQ_MEM2MEM
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR0
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR1
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR2
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR3
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR4
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR5
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR6
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR7
+  *         @arg @ref LL_DMAMUX1_REQ_ADC1
+  *         @arg @ref LL_DMAMUX1_REQ_ADC2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH4
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_TRIG
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_COM
+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH4
+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH4
+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_TRIG
+  *         @arg @ref LL_DMAMUX1_REQ_TIM4_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM4_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM4_CH3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM4_UP
+  *         @arg @ref LL_DMAMUX1_REQ_I2C1_RX
+  *         @arg @ref LL_DMAMUX1_REQ_I2C1_TX
+  *         @arg @ref LL_DMAMUX1_REQ_I2C2_RX
+  *         @arg @ref LL_DMAMUX1_REQ_I2C2_TX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI1_RX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI1_TX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI2_RX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI2_TX
+  *         @arg @ref LL_DMAMUX1_REQ_USART1_RX
+  *         @arg @ref LL_DMAMUX1_REQ_USART1_TX
+  *         @arg @ref LL_DMAMUX1_REQ_USART2_RX
+  *         @arg @ref LL_DMAMUX1_REQ_USART2_TX
+  *         @arg @ref LL_DMAMUX1_REQ_USART3_RX
+  *         @arg @ref LL_DMAMUX1_REQ_USART3_TX
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH4
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_TRIG
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_COM
+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH4
+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_TRIG
+  *         @arg @ref LL_DMAMUX1_REQ_SPI3_RX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI3_TX
+  *         @arg @ref LL_DMAMUX1_REQ_UART4_RX
+  *         @arg @ref LL_DMAMUX1_REQ_UART4_TX
+  *         @arg @ref LL_DMAMUX1_REQ_UART5_RX
+  *         @arg @ref LL_DMAMUX1_REQ_UART5_TX
+  *         @arg @ref LL_DMAMUX1_REQ_DAC1_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_DAC1_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM6_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM7_UP
+  *         @arg @ref LL_DMAMUX1_REQ_USART6_RX
+  *         @arg @ref LL_DMAMUX1_REQ_USART6_TX
+  *         @arg @ref LL_DMAMUX1_REQ_I2C3_RX
+  *         @arg @ref LL_DMAMUX1_REQ_I2C3_TX
+  *         @arg @ref LL_DMAMUX1_REQ_DCMI_PSSI (*)
+  *         @arg @ref LL_DMAMUX1_REQ_CRYP_IN
+  *         @arg @ref LL_DMAMUX1_REQ_CRYP_OUT
+  *         @arg @ref LL_DMAMUX1_REQ_HASH_IN
+  *         @arg @ref LL_DMAMUX1_REQ_UART7_RX
+  *         @arg @ref LL_DMAMUX1_REQ_UART7_TX
+  *         @arg @ref LL_DMAMUX1_REQ_UART8_RX
+  *         @arg @ref LL_DMAMUX1_REQ_UART8_TX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI4_RX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI4_TX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI5_RX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI5_TX
+  *         @arg @ref LL_DMAMUX1_REQ_SAI1_A
+  *         @arg @ref LL_DMAMUX1_REQ_SAI1_B
+  *         @arg @ref LL_DMAMUX1_REQ_SAI2_A (*)
+  *         @arg @ref LL_DMAMUX1_REQ_SAI2_B (*)
+  *         @arg @ref LL_DMAMUX1_REQ_SWPMI_RX
+  *         @arg @ref LL_DMAMUX1_REQ_SWPMI_TX
+  *         @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_DT
+  *         @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_CS
+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_MASTER (*)
+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_A (*)
+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_B (*)
+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_C (*)
+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_D (*)
+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_E (*)
+  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT0
+  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT1
+  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT2
+  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM15_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM15_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM15_TRIG
+  *         @arg @ref LL_DMAMUX1_REQ_TIM15_COM
+  *         @arg @ref LL_DMAMUX1_REQ_TIM16_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM16_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM17_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM17_UP
+  *         @arg @ref LL_DMAMUX1_REQ_SAI3_A (*)
+  *         @arg @ref LL_DMAMUX1_REQ_SAI3_B (*)
+  *         @arg @ref LL_DMAMUX1_REQ_ADC3 (*)
+  *         @arg @ref LL_DMAMUX1_REQ_UART9_RX (*)
+  *         @arg @ref LL_DMAMUX1_REQ_UART9_TX (*)
+  *         @arg @ref LL_DMAMUX1_REQ_USART10_RX (*)
+  *         @arg @ref LL_DMAMUX1_REQ_USART10_TX (*)
+  *         @arg @ref LL_DMAMUX1_REQ_FMAC_READ  (*)
+  *         @arg @ref LL_DMAMUX1_REQ_FMAC_WRITE (*)
+  *         @arg @ref LL_DMAMUX1_REQ_CORDIC_READ (*)
+  *         @arg @ref LL_DMAMUX1_REQ_CORDIC_WRITE(*)
+  *         @arg @ref LL_DMAMUX1_REQ_I2C5_RX     (*)
+  *         @arg @ref LL_DMAMUX1_REQ_I2C5_TX     (*)
+  *         @arg @ref LL_DMAMUX1_REQ_TIM23_CH1   (*)
+  *         @arg @ref LL_DMAMUX1_REQ_TIM23_CH2   (*)
+  *         @arg @ref LL_DMAMUX1_REQ_TIM23_CH3   (*)
+  *         @arg @ref LL_DMAMUX1_REQ_TIM23_CH4   (*)
+  *         @arg @ref LL_DMAMUX1_REQ_TIM23_UP    (*)
+  *         @arg @ref LL_DMAMUX1_REQ_TIM23_TRIG  (*)
+  *         @arg @ref LL_DMAMUX1_REQ_TIM24_CH1   (*)
+  *         @arg @ref LL_DMAMUX1_REQ_TIM24_CH2   (*)
+  *         @arg @ref LL_DMAMUX1_REQ_TIM24_CH3   (*)
+  *         @arg @ref LL_DMAMUX1_REQ_TIM24_CH4   (*)
+  *         @arg @ref LL_DMAMUX1_REQ_TIM24_UP    (*)
+  *         @arg @ref LL_DMAMUX1_REQ_TIM24_TRIG  (*)
+  *
+  * @note   (*) Availability depends on devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Request)
+{
+  MODIFY_REG(((DMAMUX_Channel_TypeDef *)(uint32_t)((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE * (Stream)) + (uint32_t)(DMAMUX_CCR_SIZE * LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(DMAx))))->CCR, DMAMUX_CxCR_DMAREQ_ID, Request);
+}
+
+/**
+  * @brief  Get DMA request for DMA Channels on DMAMUX Channel x.
+  * @note   DMAMUX channel 0 to 7 are mapped to DMA1 stream 0 to 7.
+  *         DMAMUX channel 8 to 15 are mapped to DMA2 stream 0 to 7.
+  * @rmtoll CxCR         DMAREQ_ID     LL_DMA_GetPeriphRequest
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMAMUX1_REQ_MEM2MEM
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR0
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR1
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR2
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR3
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR4
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR5
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR6
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR7
+  *         @arg @ref LL_DMAMUX1_REQ_ADC1
+  *         @arg @ref LL_DMAMUX1_REQ_ADC2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH4
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_TRIG
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_COM
+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH4
+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH4
+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_TRIG
+  *         @arg @ref LL_DMAMUX1_REQ_TIM4_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM4_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM4_CH3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM4_UP
+  *         @arg @ref LL_DMAMUX1_REQ_I2C1_RX
+  *         @arg @ref LL_DMAMUX1_REQ_I2C1_TX
+  *         @arg @ref LL_DMAMUX1_REQ_I2C2_RX
+  *         @arg @ref LL_DMAMUX1_REQ_I2C2_TX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI1_RX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI1_TX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI2_RX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI2_TX
+  *         @arg @ref LL_DMAMUX1_REQ_USART1_RX
+  *         @arg @ref LL_DMAMUX1_REQ_USART1_TX
+  *         @arg @ref LL_DMAMUX1_REQ_USART2_RX
+  *         @arg @ref LL_DMAMUX1_REQ_USART2_TX
+  *         @arg @ref LL_DMAMUX1_REQ_USART3_RX
+  *         @arg @ref LL_DMAMUX1_REQ_USART3_TX
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH4
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_TRIG
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_COM
+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH4
+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_TRIG
+  *         @arg @ref LL_DMAMUX1_REQ_SPI3_RX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI3_TX
+  *         @arg @ref LL_DMAMUX1_REQ_UART4_RX
+  *         @arg @ref LL_DMAMUX1_REQ_UART4_TX
+  *         @arg @ref LL_DMAMUX1_REQ_UART5_RX
+  *         @arg @ref LL_DMAMUX1_REQ_UART5_TX
+  *         @arg @ref LL_DMAMUX1_REQ_DAC1_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_DAC1_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM6_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM7_UP
+  *         @arg @ref LL_DMAMUX1_REQ_USART6_RX
+  *         @arg @ref LL_DMAMUX1_REQ_USART6_TX
+  *         @arg @ref LL_DMAMUX1_REQ_I2C3_RX
+  *         @arg @ref LL_DMAMUX1_REQ_I2C3_TX
+  *         @arg @ref LL_DMAMUX1_REQ_DCMI_PSSI (*)
+  *         @arg @ref LL_DMAMUX1_REQ_CRYP_IN
+  *         @arg @ref LL_DMAMUX1_REQ_CRYP_OUT
+  *         @arg @ref LL_DMAMUX1_REQ_HASH_IN
+  *         @arg @ref LL_DMAMUX1_REQ_UART7_RX
+  *         @arg @ref LL_DMAMUX1_REQ_UART7_TX
+  *         @arg @ref LL_DMAMUX1_REQ_UART8_RX
+  *         @arg @ref LL_DMAMUX1_REQ_UART8_TX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI4_RX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI4_TX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI5_RX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI5_TX
+  *         @arg @ref LL_DMAMUX1_REQ_SAI1_A
+  *         @arg @ref LL_DMAMUX1_REQ_SAI1_B
+  *         @arg @ref LL_DMAMUX1_REQ_SAI2_A (*)
+  *         @arg @ref LL_DMAMUX1_REQ_SAI2_B (*)
+  *         @arg @ref LL_DMAMUX1_REQ_SWPMI_RX
+  *         @arg @ref LL_DMAMUX1_REQ_SWPMI_TX
+  *         @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_DT
+  *         @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_CS
+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_MASTER (*)
+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_A (*)
+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_B (*)
+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_C (*)
+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_D (*)
+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_E (*)
+  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT0
+  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT1
+  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT2
+  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM15_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM15_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM15_TRIG
+  *         @arg @ref LL_DMAMUX1_REQ_TIM15_COM
+  *         @arg @ref LL_DMAMUX1_REQ_TIM16_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM16_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM17_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM17_UP
+  *         @arg @ref LL_DMAMUX1_REQ_SAI3_A (*)
+  *         @arg @ref LL_DMAMUX1_REQ_SAI3_B (*)
+  *         @arg @ref LL_DMAMUX1_REQ_ADC3 (*)
+  *         @arg @ref LL_DMAMUX1_REQ_UART9_RX (*)
+  *         @arg @ref LL_DMAMUX1_REQ_UART9_TX (*)
+  *         @arg @ref LL_DMAMUX1_REQ_USART10_RX (*)
+  *         @arg @ref LL_DMAMUX1_REQ_USART10_TX (*)
+  *         @arg @ref LL_DMAMUX1_REQ_FMAC_READ  (*)
+  *         @arg @ref LL_DMAMUX1_REQ_FMAC_WRITE (*)
+  *         @arg @ref LL_DMAMUX1_REQ_CORDIC_READ (*)
+  *         @arg @ref LL_DMAMUX1_REQ_CORDIC_WRITE(*)
+  *         @arg @ref LL_DMAMUX1_REQ_I2C5_RX     (*)
+  *         @arg @ref LL_DMAMUX1_REQ_I2C5_TX     (*)
+  *         @arg @ref LL_DMAMUX1_REQ_TIM23_CH1   (*)
+  *         @arg @ref LL_DMAMUX1_REQ_TIM23_CH2   (*)
+  *         @arg @ref LL_DMAMUX1_REQ_TIM23_CH3   (*)
+  *         @arg @ref LL_DMAMUX1_REQ_TIM23_CH4   (*)
+  *         @arg @ref LL_DMAMUX1_REQ_TIM23_UP    (*)
+  *         @arg @ref LL_DMAMUX1_REQ_TIM23_TRIG  (*)
+  *         @arg @ref LL_DMAMUX1_REQ_TIM24_CH1   (*)
+  *         @arg @ref LL_DMAMUX1_REQ_TIM24_CH2   (*)
+  *         @arg @ref LL_DMAMUX1_REQ_TIM24_CH3   (*)
+  *         @arg @ref LL_DMAMUX1_REQ_TIM24_CH4   (*)
+  *         @arg @ref LL_DMAMUX1_REQ_TIM24_UP    (*)
+  *         @arg @ref LL_DMAMUX1_REQ_TIM24_TRIG  (*)
+  *
+  * @note   (*) Availability depends on devices.
+  */
+__STATIC_INLINE  uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  return (READ_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE * (Stream)) + (uint32_t)(DMAMUX_CCR_SIZE * LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(DMAx)))))->CCR, DMAMUX_CxCR_DMAREQ_ID));
+}
+
+/**
+  * @brief Set Memory burst transfer configuration.
+  * @rmtoll CR          MBURST           LL_DMA_SetMemoryBurstxfer
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  Mburst This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_MBURST_SINGLE
+  *         @arg @ref LL_DMA_MBURST_INC4
+  *         @arg @ref LL_DMA_MBURST_INC8
+  *         @arg @ref LL_DMA_MBURST_INC16
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mburst)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MBURST, Mburst);
+}
+
+/**
+  * @brief Get Memory burst transfer configuration.
+  * @rmtoll CR          MBURST           LL_DMA_GetMemoryBurstxfer
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_MBURST_SINGLE
+  *         @arg @ref LL_DMA_MBURST_INC4
+  *         @arg @ref LL_DMA_MBURST_INC8
+  *         @arg @ref LL_DMA_MBURST_INC16
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MBURST));
+}
+
+/**
+  * @brief Set  Peripheral burst transfer configuration.
+  * @rmtoll CR          PBURST           LL_DMA_SetPeriphBurstxfer
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  Pburst This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_PBURST_SINGLE
+  *         @arg @ref LL_DMA_PBURST_INC4
+  *         @arg @ref LL_DMA_PBURST_INC8
+  *         @arg @ref LL_DMA_PBURST_INC16
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pburst)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PBURST, Pburst);
+}
+
+/**
+  * @brief Get Peripheral burst transfer configuration.
+  * @rmtoll CR          PBURST           LL_DMA_GetPeriphBurstxfer
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_PBURST_SINGLE
+  *         @arg @ref LL_DMA_PBURST_INC4
+  *         @arg @ref LL_DMA_PBURST_INC8
+  *         @arg @ref LL_DMA_PBURST_INC16
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PBURST));
+}
+
+/**
+  * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
+  * @rmtoll CR          CT           LL_DMA_SetCurrentTargetMem
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param CurrentMemory This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CURRENTTARGETMEM0
+  *         @arg @ref LL_DMA_CURRENTTARGETMEM1
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t CurrentMemory)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CT, CurrentMemory);
+}
+
+/**
+  * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
+  * @rmtoll CR          CT           LL_DMA_GetCurrentTargetMem
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_CURRENTTARGETMEM0
+  *         @arg @ref LL_DMA_CURRENTTARGETMEM1
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CT));
+}
+
+/**
+  * @brief Enable the double buffer mode.
+  * @rmtoll CR          DBM           LL_DMA_EnableDoubleBufferMode
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DBM);
+}
+
+/**
+  * @brief Disable the double buffer mode.
+  * @rmtoll CR          DBM           LL_DMA_DisableDoubleBufferMode
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DBM);
+}
+
+/**
+  * @brief Get FIFO status.
+  * @rmtoll FCR          FS          LL_DMA_GetFIFOStatus
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_FIFOSTATUS_0_25
+  *         @arg @ref LL_DMA_FIFOSTATUS_25_50
+  *         @arg @ref LL_DMA_FIFOSTATUS_50_75
+  *         @arg @ref LL_DMA_FIFOSTATUS_75_100
+  *         @arg @ref LL_DMA_FIFOSTATUS_EMPTY
+  *         @arg @ref LL_DMA_FIFOSTATUS_FULL
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FS));
+}
+
+/**
+  * @brief Disable Fifo mode.
+  * @rmtoll FCR          DMDIS          LL_DMA_DisableFifoMode
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_DisableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_DMDIS);
+}
+
+/**
+  * @brief Enable Fifo mode.
+  * @rmtoll FCR          DMDIS          LL_DMA_EnableFifoMode
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_EnableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_DMDIS);
+}
+
+/**
+  * @brief Select FIFO threshold.
+  * @rmtoll FCR         FTH          LL_DMA_SetFIFOThreshold
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  Threshold This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Threshold)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FTH, Threshold);
+}
+
+/**
+  * @brief Get FIFO threshold.
+  * @rmtoll FCR         FTH          LL_DMA_GetFIFOThreshold
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FTH));
+}
+
+/**
+  * @brief Configure the FIFO .
+  * @rmtoll FCR         FTH          LL_DMA_ConfigFifo\n
+  *         FCR         DMDIS        LL_DMA_ConfigFifo
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  FifoMode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_FIFOMODE_ENABLE
+  *         @arg @ref LL_DMA_FIFOMODE_DISABLE
+  * @param  FifoThreshold This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint32_t FifoThreshold)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FTH | DMA_SxFCR_DMDIS, FifoMode | FifoThreshold);
+}
+
+/**
+  * @brief Configure the Source and Destination addresses.
+  * @note   This API must not be called when the DMA stream is enabled.
+  * @rmtoll M0AR        M0A         LL_DMA_ConfigAddresses\n
+  *         PAR         PA          LL_DMA_ConfigAddresses
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  SrcAddress Between 0 to 0xFFFFFFFF
+  * @param  DstAddress Between 0 to 0xFFFFFFFF
+  * @param  Direction This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
+  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
+  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  /* Direction Memory to Periph */
+  if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
+  {
+    WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, SrcAddress);
+    WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, DstAddress);
+  }
+  /* Direction Periph to Memory and Memory to Memory */
+  else
+  {
+    WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, SrcAddress);
+    WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, DstAddress);
+  }
+}
+
+/**
+  * @brief  Set the Memory address.
+  * @rmtoll M0AR        M0A         LL_DMA_SetMemoryAddress
+  * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
+  * @note   This API must not be called when the DMA stream is enabled.
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  MemoryAddress Between 0 to 0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, MemoryAddress);
+}
+
+/**
+  * @brief  Set the Peripheral address.
+  * @rmtoll PAR        PA         LL_DMA_SetPeriphAddress
+  * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
+  * @note   This API must not be called when the DMA stream is enabled.
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  PeriphAddress Between 0 to 0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t PeriphAddress)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, PeriphAddress);
+}
+
+/**
+  * @brief  Get the Memory address.
+  * @rmtoll M0AR        M0A         LL_DMA_GetMemoryAddress
+  * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Between 0 to 0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR));
+}
+
+/**
+  * @brief  Get the Peripheral address.
+  * @rmtoll PAR        PA         LL_DMA_GetPeriphAddress
+  * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Between 0 to 0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR));
+}
+
+/**
+  * @brief  Set the Memory to Memory Source address.
+  * @rmtoll PAR        PA         LL_DMA_SetM2MSrcAddress
+  * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+  * @note   This API must not be called when the DMA stream is enabled.
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  MemoryAddress Between 0 to 0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, MemoryAddress);
+}
+
+/**
+  * @brief  Set the Memory to Memory Destination address.
+  * @rmtoll M0AR        M0A         LL_DMA_SetM2MDstAddress
+  * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+  * @note   This API must not be called when the DMA stream is enabled.
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  MemoryAddress Between 0 to 0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, MemoryAddress);
+}
+
+/**
+  * @brief  Get the Memory to Memory Source address.
+  * @rmtoll PAR        PA         LL_DMA_GetM2MSrcAddress
+  * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Between 0 to 0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR));
+}
+
+/**
+  * @brief  Get the Memory to Memory Destination address.
+  * @rmtoll M0AR        M0A         LL_DMA_GetM2MDstAddress
+  * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Between 0 to 0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR));
+}
+
+/**
+  * @brief Set Memory 1 address (used in case of Double buffer mode).
+  * @rmtoll M1AR        M1A         LL_DMA_SetMemory1Address
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  Address Between 0 to 0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Address)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M1AR, DMA_SxM1AR_M1A, Address);
+}
+
+/**
+  * @brief Get Memory 1 address (used in case of Double buffer mode).
+  * @rmtoll M1AR        M1A         LL_DMA_GetMemory1Address
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Between 0 to 0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return (((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M1AR);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
+  * @{
+  */
+
+/**
+  * @brief Get Stream 0 half transfer flag.
+  * @rmtoll LISR  HTIF0    LL_DMA_IsActiveFlag_HT0
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT0(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF0) == (DMA_LISR_HTIF0)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 1 half transfer flag.
+  * @rmtoll LISR  HTIF1    LL_DMA_IsActiveFlag_HT1
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF1) == (DMA_LISR_HTIF1)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 2 half transfer flag.
+  * @rmtoll LISR  HTIF2    LL_DMA_IsActiveFlag_HT2
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF2) == (DMA_LISR_HTIF2)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 3 half transfer flag.
+  * @rmtoll LISR  HTIF3    LL_DMA_IsActiveFlag_HT3
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF3) == (DMA_LISR_HTIF3)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 4 half transfer flag.
+  * @rmtoll HISR  HTIF4    LL_DMA_IsActiveFlag_HT4
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF4) == (DMA_HISR_HTIF4)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 5 half transfer flag.
+  * @rmtoll HISR  HTIF0    LL_DMA_IsActiveFlag_HT5
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF5) == (DMA_HISR_HTIF5)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 6 half transfer flag.
+  * @rmtoll HISR  HTIF6    LL_DMA_IsActiveFlag_HT6
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF6) == (DMA_HISR_HTIF6)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 7 half transfer flag.
+  * @rmtoll HISR  HTIF7    LL_DMA_IsActiveFlag_HT7
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF7) == (DMA_HISR_HTIF7)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 0 transfer complete flag.
+  * @rmtoll LISR  TCIF0    LL_DMA_IsActiveFlag_TC0
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC0(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF0) == (DMA_LISR_TCIF0)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 1 transfer complete flag.
+  * @rmtoll LISR  TCIF1    LL_DMA_IsActiveFlag_TC1
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF1) == (DMA_LISR_TCIF1)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 2 transfer complete flag.
+  * @rmtoll LISR  TCIF2    LL_DMA_IsActiveFlag_TC2
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF2) == (DMA_LISR_TCIF2)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 3 transfer complete flag.
+  * @rmtoll LISR  TCIF3    LL_DMA_IsActiveFlag_TC3
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF3) == (DMA_LISR_TCIF3)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 4 transfer complete flag.
+  * @rmtoll HISR  TCIF4    LL_DMA_IsActiveFlag_TC4
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF4) == (DMA_HISR_TCIF4)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 5 transfer complete flag.
+  * @rmtoll HISR  TCIF0    LL_DMA_IsActiveFlag_TC5
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF5) == (DMA_HISR_TCIF5)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 6 transfer complete flag.
+  * @rmtoll HISR  TCIF6    LL_DMA_IsActiveFlag_TC6
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF6) == (DMA_HISR_TCIF6)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 7 transfer complete flag.
+  * @rmtoll HISR  TCIF7    LL_DMA_IsActiveFlag_TC7
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF7) == (DMA_HISR_TCIF7)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 0 transfer error flag.
+  * @rmtoll LISR  TEIF0    LL_DMA_IsActiveFlag_TE0
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE0(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF0) == (DMA_LISR_TEIF0)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 1 transfer error flag.
+  * @rmtoll LISR  TEIF1    LL_DMA_IsActiveFlag_TE1
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF1) == (DMA_LISR_TEIF1)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 2 transfer error flag.
+  * @rmtoll LISR  TEIF2    LL_DMA_IsActiveFlag_TE2
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF2) == (DMA_LISR_TEIF2)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 3 transfer error flag.
+  * @rmtoll LISR  TEIF3    LL_DMA_IsActiveFlag_TE3
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF3) == (DMA_LISR_TEIF3)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 4 transfer error flag.
+  * @rmtoll HISR  TEIF4    LL_DMA_IsActiveFlag_TE4
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF4) == (DMA_HISR_TEIF4)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 5 transfer error flag.
+  * @rmtoll HISR  TEIF0    LL_DMA_IsActiveFlag_TE5
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF5) == (DMA_HISR_TEIF5)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 6 transfer error flag.
+  * @rmtoll HISR  TEIF6    LL_DMA_IsActiveFlag_TE6
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF6) == (DMA_HISR_TEIF6)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 7 transfer error flag.
+  * @rmtoll HISR  TEIF7    LL_DMA_IsActiveFlag_TE7
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF7) == (DMA_HISR_TEIF7)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 0 direct mode error flag.
+  * @rmtoll LISR  DMEIF0    LL_DMA_IsActiveFlag_DME0
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME0(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF0) == (DMA_LISR_DMEIF0)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 1 direct mode error flag.
+  * @rmtoll LISR  DMEIF1    LL_DMA_IsActiveFlag_DME1
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME1(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF1) == (DMA_LISR_DMEIF1)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 2 direct mode error flag.
+  * @rmtoll LISR  DMEIF2    LL_DMA_IsActiveFlag_DME2
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME2(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF2) == (DMA_LISR_DMEIF2)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 3 direct mode error flag.
+  * @rmtoll LISR  DMEIF3    LL_DMA_IsActiveFlag_DME3
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME3(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF3) == (DMA_LISR_DMEIF3)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 4 direct mode error flag.
+  * @rmtoll HISR  DMEIF4    LL_DMA_IsActiveFlag_DME4
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME4(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF4) == (DMA_HISR_DMEIF4)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 5 direct mode error flag.
+  * @rmtoll HISR  DMEIF0    LL_DMA_IsActiveFlag_DME5
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME5(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF5) == (DMA_HISR_DMEIF5)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 6 direct mode error flag.
+  * @rmtoll HISR  DMEIF6    LL_DMA_IsActiveFlag_DME6
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME6(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF6) == (DMA_HISR_DMEIF6)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 7 direct mode error flag.
+  * @rmtoll HISR  DMEIF7    LL_DMA_IsActiveFlag_DME7
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME7(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF7) == (DMA_HISR_DMEIF7)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 0 FIFO error flag.
+  * @rmtoll LISR  FEIF0    LL_DMA_IsActiveFlag_FE0
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE0(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF0) == (DMA_LISR_FEIF0)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 1 FIFO error flag.
+  * @rmtoll LISR  FEIF1    LL_DMA_IsActiveFlag_FE1
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE1(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF1) == (DMA_LISR_FEIF1)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 2 FIFO error flag.
+  * @rmtoll LISR  FEIF2    LL_DMA_IsActiveFlag_FE2
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE2(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF2) == (DMA_LISR_FEIF2)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 3 FIFO error flag.
+  * @rmtoll LISR  FEIF3    LL_DMA_IsActiveFlag_FE3
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE3(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF3) == (DMA_LISR_FEIF3)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 4 FIFO error flag.
+  * @rmtoll HISR  FEIF4    LL_DMA_IsActiveFlag_FE4
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE4(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF4) == (DMA_HISR_FEIF4)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 5 FIFO error flag.
+  * @rmtoll HISR  FEIF0    LL_DMA_IsActiveFlag_FE5
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE5(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF5) == (DMA_HISR_FEIF5)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 6 FIFO error flag.
+  * @rmtoll HISR  FEIF6    LL_DMA_IsActiveFlag_FE6
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE6(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF6) == (DMA_HISR_FEIF6)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 7 FIFO error flag.
+  * @rmtoll HISR  FEIF7    LL_DMA_IsActiveFlag_FE7
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE7(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF7) == (DMA_HISR_FEIF7)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Clear Stream 0 half transfer flag.
+  * @rmtoll LIFCR  CHTIF0    LL_DMA_ClearFlag_HT0
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT0(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CHTIF0);
+}
+
+/**
+  * @brief Clear Stream 1 half transfer flag.
+  * @rmtoll LIFCR  CHTIF1    LL_DMA_ClearFlag_HT1
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CHTIF1);
+}
+
+/**
+  * @brief Clear Stream 2 half transfer flag.
+  * @rmtoll LIFCR  CHTIF2    LL_DMA_ClearFlag_HT2
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CHTIF2);
+}
+
+/**
+  * @brief Clear Stream 3 half transfer flag.
+  * @rmtoll LIFCR  CHTIF3    LL_DMA_ClearFlag_HT3
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CHTIF3);
+}
+
+/**
+  * @brief Clear Stream 4 half transfer flag.
+  * @rmtoll HIFCR  CHTIF4    LL_DMA_ClearFlag_HT4
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CHTIF4);
+}
+
+/**
+  * @brief Clear Stream 5 half transfer flag.
+  * @rmtoll HIFCR  CHTIF5    LL_DMA_ClearFlag_HT5
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CHTIF5);
+}
+
+/**
+  * @brief Clear Stream 6 half transfer flag.
+  * @rmtoll HIFCR  CHTIF6    LL_DMA_ClearFlag_HT6
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CHTIF6);
+}
+
+/**
+  * @brief Clear Stream 7 half transfer flag.
+  * @rmtoll HIFCR  CHTIF7    LL_DMA_ClearFlag_HT7
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CHTIF7);
+}
+
+/**
+  * @brief Clear Stream 0 transfer complete flag.
+  * @rmtoll LIFCR  CTCIF0    LL_DMA_ClearFlag_TC0
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC0(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTCIF0);
+}
+
+/**
+  * @brief Clear Stream 1 transfer complete flag.
+  * @rmtoll LIFCR  CTCIF1    LL_DMA_ClearFlag_TC1
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTCIF1);
+}
+
+/**
+  * @brief Clear Stream 2 transfer complete flag.
+  * @rmtoll LIFCR  CTCIF2    LL_DMA_ClearFlag_TC2
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTCIF2);
+}
+
+/**
+  * @brief Clear Stream 3 transfer complete flag.
+  * @rmtoll LIFCR  CTCIF3    LL_DMA_ClearFlag_TC3
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTCIF3);
+}
+
+/**
+  * @brief Clear Stream 4 transfer complete flag.
+  * @rmtoll HIFCR  CTCIF4    LL_DMA_ClearFlag_TC4
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTCIF4);
+}
+
+/**
+  * @brief Clear Stream 5 transfer complete flag.
+  * @rmtoll HIFCR  CTCIF5    LL_DMA_ClearFlag_TC5
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTCIF5);
+}
+
+/**
+  * @brief Clear Stream 6 transfer complete flag.
+  * @rmtoll HIFCR  CTCIF6    LL_DMA_ClearFlag_TC6
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTCIF6);
+}
+
+/**
+  * @brief Clear Stream 7 transfer complete flag.
+  * @rmtoll HIFCR  CTCIF7    LL_DMA_ClearFlag_TC7
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTCIF7);
+}
+
+/**
+  * @brief Clear Stream 0 transfer error flag.
+  * @rmtoll LIFCR  CTEIF0    LL_DMA_ClearFlag_TE0
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE0(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTEIF0);
+}
+
+/**
+  * @brief Clear Stream 1 transfer error flag.
+  * @rmtoll LIFCR  CTEIF1    LL_DMA_ClearFlag_TE1
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTEIF1);
+}
+
+/**
+  * @brief Clear Stream 2 transfer error flag.
+  * @rmtoll LIFCR  CTEIF2    LL_DMA_ClearFlag_TE2
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTEIF2);
+}
+
+/**
+  * @brief Clear Stream 3 transfer error flag.
+  * @rmtoll LIFCR  CTEIF3    LL_DMA_ClearFlag_TE3
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTEIF3);
+}
+
+/**
+  * @brief Clear Stream 4 transfer error flag.
+  * @rmtoll HIFCR  CTEIF4    LL_DMA_ClearFlag_TE4
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTEIF4);
+}
+
+/**
+  * @brief Clear Stream 5 transfer error flag.
+  * @rmtoll HIFCR  CTEIF5    LL_DMA_ClearFlag_TE5
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTEIF5);
+}
+
+/**
+  * @brief Clear Stream 6 transfer error flag.
+  * @rmtoll HIFCR  CTEIF6    LL_DMA_ClearFlag_TE6
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTEIF6);
+}
+
+/**
+  * @brief Clear Stream 7 transfer error flag.
+  * @rmtoll HIFCR  CTEIF7    LL_DMA_ClearFlag_TE7
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTEIF7);
+}
+
+/**
+  * @brief Clear Stream 0 direct mode error flag.
+  * @rmtoll LIFCR  CDMEIF0    LL_DMA_ClearFlag_DME0
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_DME0(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CDMEIF0);
+}
+
+/**
+  * @brief Clear Stream 1 direct mode error flag.
+  * @rmtoll LIFCR  CDMEIF1    LL_DMA_ClearFlag_DME1
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_DME1(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CDMEIF1);
+}
+
+/**
+  * @brief Clear Stream 2 direct mode error flag.
+  * @rmtoll LIFCR  CDMEIF2    LL_DMA_ClearFlag_DME2
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_DME2(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CDMEIF2);
+}
+
+/**
+  * @brief Clear Stream 3 direct mode error flag.
+  * @rmtoll LIFCR  CDMEIF3    LL_DMA_ClearFlag_DME3
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_DME3(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CDMEIF3);
+}
+
+/**
+  * @brief Clear Stream 4 direct mode error flag.
+  * @rmtoll HIFCR  CDMEIF4    LL_DMA_ClearFlag_DME4
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_DME4(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CDMEIF4);
+}
+
+/**
+  * @brief Clear Stream 5 direct mode error flag.
+  * @rmtoll HIFCR  CDMEIF5    LL_DMA_ClearFlag_DME5
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_DME5(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CDMEIF5);
+}
+
+/**
+  * @brief Clear Stream 6 direct mode error flag.
+  * @rmtoll HIFCR  CDMEIF6    LL_DMA_ClearFlag_DME6
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_DME6(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CDMEIF6);
+}
+
+/**
+  * @brief Clear Stream 7 direct mode error flag.
+  * @rmtoll HIFCR  CDMEIF7    LL_DMA_ClearFlag_DME7
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_DME7(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CDMEIF7);
+}
+
+/**
+  * @brief Clear Stream 0 FIFO error flag.
+  * @rmtoll LIFCR  CFEIF0    LL_DMA_ClearFlag_FE0
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_FE0(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CFEIF0);
+}
+
+/**
+  * @brief Clear Stream 1 FIFO error flag.
+  * @rmtoll LIFCR  CFEIF1    LL_DMA_ClearFlag_FE1
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_FE1(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CFEIF1);
+}
+
+/**
+  * @brief Clear Stream 2 FIFO error flag.
+  * @rmtoll LIFCR  CFEIF2    LL_DMA_ClearFlag_FE2
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_FE2(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CFEIF2);
+}
+
+/**
+  * @brief Clear Stream 3 FIFO error flag.
+  * @rmtoll LIFCR  CFEIF3    LL_DMA_ClearFlag_FE3
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_FE3(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CFEIF3);
+}
+
+/**
+  * @brief Clear Stream 4 FIFO error flag.
+  * @rmtoll HIFCR  CFEIF4    LL_DMA_ClearFlag_FE4
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_FE4(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CFEIF4);
+}
+
+/**
+  * @brief Clear Stream 5 FIFO error flag.
+  * @rmtoll HIFCR  CFEIF5    LL_DMA_ClearFlag_FE5
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_FE5(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CFEIF5);
+}
+
+/**
+  * @brief Clear Stream 6 FIFO error flag.
+  * @rmtoll HIFCR  CFEIF6    LL_DMA_ClearFlag_FE6
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_FE6(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CFEIF6);
+}
+
+/**
+  * @brief Clear Stream 7 FIFO error flag.
+  * @rmtoll HIFCR  CFEIF7    LL_DMA_ClearFlag_FE7
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_FE7(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CFEIF7);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EF_IT_Management IT_Management
+  * @{
+  */
+
+/**
+  * @brief Enable Half transfer interrupt.
+  * @rmtoll CR        HTIE         LL_DMA_EnableIT_HT
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_HTIE);
+}
+
+/**
+  * @brief Enable Transfer error interrupt.
+  * @rmtoll CR        TEIE         LL_DMA_EnableIT_TE
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TEIE);
+}
+
+/**
+  * @brief Enable Transfer complete interrupt.
+  * @rmtoll CR        TCIE         LL_DMA_EnableIT_TC
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TCIE);
+}
+
+/**
+  * @brief Enable Direct mode error interrupt.
+  * @rmtoll CR        DMEIE         LL_DMA_EnableIT_DME
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_EnableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DMEIE);
+}
+
+/**
+  * @brief Enable FIFO error interrupt.
+  * @rmtoll FCR        FEIE         LL_DMA_EnableIT_FE
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_EnableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FEIE);
+}
+
+/**
+  * @brief Disable Half transfer interrupt.
+  * @rmtoll CR        HTIE         LL_DMA_DisableIT_HT
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_HTIE);
+}
+
+/**
+  * @brief Disable Transfer error interrupt.
+  * @rmtoll CR        TEIE         LL_DMA_DisableIT_TE
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TEIE);
+}
+
+/**
+  * @brief Disable Transfer complete interrupt.
+  * @rmtoll CR        TCIE         LL_DMA_DisableIT_TC
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TCIE);
+}
+
+/**
+  * @brief Disable Direct mode error interrupt.
+  * @rmtoll CR        DMEIE         LL_DMA_DisableIT_DME
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_DisableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DMEIE);
+}
+
+/**
+  * @brief Disable FIFO error interrupt.
+  * @rmtoll FCR        FEIE         LL_DMA_DisableIT_FE
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_DisableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FEIE);
+}
+
+/**
+  * @brief Check if Half transfer interrup is enabled.
+  * @rmtoll CR        HTIE         LL_DMA_IsEnabledIT_HT
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_HTIE) == DMA_SxCR_HTIE) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Check if Transfer error nterrup is enabled.
+  * @rmtoll CR        TEIE         LL_DMA_IsEnabledIT_TE
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TEIE) == DMA_SxCR_TEIE) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Check if Transfer complete interrup is enabled.
+  * @rmtoll CR        TCIE         LL_DMA_IsEnabledIT_TC
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TCIE) == DMA_SxCR_TCIE) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Check if Direct mode error interrupt is enabled.
+  * @rmtoll CR        DMEIE         LL_DMA_IsEnabledIT_DME
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DMEIE) == DMA_SxCR_DMEIE) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Check if FIFO error interrup is enabled.
+  * @rmtoll FCR        FEIE         LL_DMA_IsEnabledIT_FE
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FEIE) == DMA_SxFCR_FEIE) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+
+uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct);
+uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream);
+void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* DMA1 || DMA2 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32H7xx_LL_DMA_H */
+
diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dmamux.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dmamux.h
index bf4cffa0..448389fc 100644
--- a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dmamux.h
+++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dmamux.h
@@ -1,2436 +1,2436 @@
-/**
-  ******************************************************************************
-  * @file    stm32h7xx_ll_dmamux.h
-  * @author  MCD Application Team
-  * @brief   Header file of DMAMUX LL module.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32H7xx_LL_DMAMUX_H
-#define STM32H7xx_LL_DMAMUX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx.h"
-
-/** @addtogroup STM32H7xx_LL_Driver
-  * @{
-  */
-
-#if defined (DMAMUX1) || defined (DMAMUX2)
-
-/** @defgroup DMAMUX_LL DMAMUX
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup DMAMUX_LL_Private_Constants DMAMUX Private Constants
-  * @{
-  */
-/* Define used to get DMAMUX CCR register size */
-#define DMAMUX_CCR_SIZE                   0x00000004U
-
-/* Define used to get DMAMUX RGCR register size */
-#define DMAMUX_RGCR_SIZE                  0x00000004U
-
-/* Define used to get DMAMUX RequestGenerator offset */
-#define DMAMUX_REQ_GEN_OFFSET             (DMAMUX1_RequestGenerator0_BASE - DMAMUX1_BASE)
-/* Define used to get DMAMUX Channel Status offset */
-#define DMAMUX_CH_STATUS_OFFSET           (DMAMUX1_ChannelStatus_BASE - DMAMUX1_BASE)
-/* Define used to get DMAMUX RequestGenerator status offset */
-#define DMAMUX_REQ_GEN_STATUS_OFFSET      (DMAMUX1_RequestGenStatus_BASE - DMAMUX1_BASE)
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup DMAMUX_LL_Exported_Constants DMAMUX Exported Constants
-  * @{
-  */
-/** @defgroup DMAMUX_LL_EC_CLEAR_FLAG Clear Flags Defines
-  * @brief    Flags defines which can be used with LL_DMAMUX_WriteReg function
-  * @{
-  */
-#define LL_DMAMUX_CFR_CSOF0               DMAMUX_CFR_CSOF0       /*!< Synchronization Event Overrun Flag Channel 0   */
-#define LL_DMAMUX_CFR_CSOF1               DMAMUX_CFR_CSOF1       /*!< Synchronization Event Overrun Flag Channel 1   */
-#define LL_DMAMUX_CFR_CSOF2               DMAMUX_CFR_CSOF2       /*!< Synchronization Event Overrun Flag Channel 2   */
-#define LL_DMAMUX_CFR_CSOF3               DMAMUX_CFR_CSOF3       /*!< Synchronization Event Overrun Flag Channel 3   */
-#define LL_DMAMUX_CFR_CSOF4               DMAMUX_CFR_CSOF4       /*!< Synchronization Event Overrun Flag Channel 4   */
-#define LL_DMAMUX_CFR_CSOF5               DMAMUX_CFR_CSOF5       /*!< Synchronization Event Overrun Flag Channel 5   */
-#define LL_DMAMUX_CFR_CSOF6               DMAMUX_CFR_CSOF6       /*!< Synchronization Event Overrun Flag Channel 6   */
-#define LL_DMAMUX_CFR_CSOF7               DMAMUX_CFR_CSOF7       /*!< Synchronization Event Overrun Flag Channel 7   */
-#define LL_DMAMUX_CFR_CSOF8               DMAMUX_CFR_CSOF8       /*!< Synchronization Event Overrun Flag Channel 8   */
-#define LL_DMAMUX_CFR_CSOF9               DMAMUX_CFR_CSOF9       /*!< Synchronization Event Overrun Flag Channel 9   */
-#define LL_DMAMUX_CFR_CSOF10              DMAMUX_CFR_CSOF10      /*!< Synchronization Event Overrun Flag Channel 10  */
-#define LL_DMAMUX_CFR_CSOF11              DMAMUX_CFR_CSOF11      /*!< Synchronization Event Overrun Flag Channel 11  */
-#define LL_DMAMUX_CFR_CSOF12              DMAMUX_CFR_CSOF12      /*!< Synchronization Event Overrun Flag Channel 12  */
-#define LL_DMAMUX_CFR_CSOF13              DMAMUX_CFR_CSOF13      /*!< Synchronization Event Overrun Flag Channel 13  */
-#define LL_DMAMUX_CFR_CSOF14              DMAMUX_CFR_CSOF14      /*!< Synchronization Event Overrun Flag Channel 14  */
-#define LL_DMAMUX_CFR_CSOF15              DMAMUX_CFR_CSOF15      /*!< Synchronization Event Overrun Flag Channel 15  */
-#define LL_DMAMUX_RGCFR_RGCOF0            DMAMUX_RGCFR_COF0      /*!< Request Generator 0 Trigger Event Overrun Flag */
-#define LL_DMAMUX_RGCFR_RGCOF1            DMAMUX_RGCFR_COF1      /*!< Request Generator 1 Trigger Event Overrun Flag */
-#define LL_DMAMUX_RGCFR_RGCOF2            DMAMUX_RGCFR_COF2      /*!< Request Generator 2 Trigger Event Overrun Flag */
-#define LL_DMAMUX_RGCFR_RGCOF3            DMAMUX_RGCFR_COF3      /*!< Request Generator 3 Trigger Event Overrun Flag */
-#define LL_DMAMUX_RGCFR_RGCOF4            DMAMUX_RGCFR_COF4      /*!< Request Generator 4 Trigger Event Overrun Flag */
-#define LL_DMAMUX_RGCFR_RGCOF5            DMAMUX_RGCFR_COF5      /*!< Request Generator 5 Trigger Event Overrun Flag */
-#define LL_DMAMUX_RGCFR_RGCOF6            DMAMUX_RGCFR_COF6      /*!< Request Generator 6 Trigger Event Overrun Flag */
-#define LL_DMAMUX_RGCFR_RGCOF7            DMAMUX_RGCFR_COF7      /*!< Request Generator 7 Trigger Event Overrun Flag */
-/**
-  * @}
-  */
-
-/** @defgroup DMAMUX_LL_EC_GET_FLAG Get Flags Defines
-  * @brief    Flags defines which can be used with LL_DMAMUX_ReadReg function
-  * @{
-  */
-#define LL_DMAMUX_CSR_SOF0                DMAMUX_CSR_SOF0       /*!< Synchronization Event Overrun Flag Channel 0   */
-#define LL_DMAMUX_CSR_SOF1                DMAMUX_CSR_SOF1       /*!< Synchronization Event Overrun Flag Channel 1   */
-#define LL_DMAMUX_CSR_SOF2                DMAMUX_CSR_SOF2       /*!< Synchronization Event Overrun Flag Channel 2   */
-#define LL_DMAMUX_CSR_SOF3                DMAMUX_CSR_SOF3       /*!< Synchronization Event Overrun Flag Channel 3   */
-#define LL_DMAMUX_CSR_SOF4                DMAMUX_CSR_SOF4       /*!< Synchronization Event Overrun Flag Channel 4   */
-#define LL_DMAMUX_CSR_SOF5                DMAMUX_CSR_SOF5       /*!< Synchronization Event Overrun Flag Channel 5   */
-#define LL_DMAMUX_CSR_SOF6                DMAMUX_CSR_SOF6       /*!< Synchronization Event Overrun Flag Channel 6   */
-#define LL_DMAMUX_CSR_SOF7                DMAMUX_CSR_SOF7       /*!< Synchronization Event Overrun Flag Channel 7   */
-#define LL_DMAMUX_CSR_SOF8                DMAMUX_CSR_SOF8       /*!< Synchronization Event Overrun Flag Channel 8   */
-#define LL_DMAMUX_CSR_SOF9                DMAMUX_CSR_SOF9       /*!< Synchronization Event Overrun Flag Channel 9   */
-#define LL_DMAMUX_CSR_SOF10               DMAMUX_CSR_SOF10      /*!< Synchronization Event Overrun Flag Channel 10  */
-#define LL_DMAMUX_CSR_SOF11               DMAMUX_CSR_SOF11      /*!< Synchronization Event Overrun Flag Channel 11  */
-#define LL_DMAMUX_CSR_SOF12               DMAMUX_CSR_SOF12      /*!< Synchronization Event Overrun Flag Channel 12  */
-#define LL_DMAMUX_CSR_SOF13               DMAMUX_CSR_SOF13      /*!< Synchronization Event Overrun Flag Channel 13  */
-#define LL_DMAMUX_CSR_SOF14               DMAMUX_CSR_SOF14      /*!< Synchronization Event Overrun Flag Channel 14  */
-#define LL_DMAMUX_CSR_SOF15               DMAMUX_CSR_SOF15      /*!< Synchronization Event Overrun Flag Channel 15  */
-#define LL_DMAMUX_RGSR_RGOF0              DMAMUX_RGSR_OF0       /*!< Request Generator 0 Trigger Event Overrun Flag */
-#define LL_DMAMUX_RGSR_RGOF1              DMAMUX_RGSR_OF1       /*!< Request Generator 1 Trigger Event Overrun Flag */
-#define LL_DMAMUX_RGSR_RGOF2              DMAMUX_RGSR_OF2       /*!< Request Generator 2 Trigger Event Overrun Flag */
-#define LL_DMAMUX_RGSR_RGOF3              DMAMUX_RGSR_OF3       /*!< Request Generator 3 Trigger Event Overrun Flag */
-#define LL_DMAMUX_RGSR_RGOF4              DMAMUX_RGSR_OF4       /*!< Request Generator 4 Trigger Event Overrun Flag */
-#define LL_DMAMUX_RGSR_RGOF5              DMAMUX_RGSR_OF5       /*!< Request Generator 5 Trigger Event Overrun Flag */
-#define LL_DMAMUX_RGSR_RGOF6              DMAMUX_RGSR_OF6       /*!< Request Generator 6 Trigger Event Overrun Flag */
-#define LL_DMAMUX_RGSR_RGOF7              DMAMUX_RGSR_OF7       /*!< Request Generator 7 Trigger Event Overrun Flag */
-/**
-  * @}
-  */
-
-/** @defgroup DMAMUX_LL_EC_IT IT Defines
-  * @brief    IT defines which can be used with LL_DMA_ReadReg and  LL_DMAMUX_WriteReg functions
-  * @{
-  */
-#define LL_DMAMUX_CCR_SOIE                DMAMUX_CxCR_SOIE          /*!< Synchronization Event Overrun Interrupt               */
-#define LL_DMAMUX_RGCR_RGOIE              DMAMUX_RGxCR_OIE          /*!< Request Generation Trigger Event Overrun Interrupt    */
-/**
-  * @}
-  */
-
-/** @defgroup DMAMUX1_Request_selection DMAMUX1 Request selection
-  * @brief    DMAMUX1 Request selection
-  * @{
-  */
-/* DMAMUX1 requests */
-#define LL_DMAMUX1_REQ_MEM2MEM          0U   /*!< memory to memory transfer       */
-#define LL_DMAMUX1_REQ_GENERATOR0       1U   /*!< DMAMUX1 request generator 0     */
-#define LL_DMAMUX1_REQ_GENERATOR1       2U   /*!< DMAMUX1 request generator 1     */
-#define LL_DMAMUX1_REQ_GENERATOR2       3U   /*!< DMAMUX1 request generator 2     */
-#define LL_DMAMUX1_REQ_GENERATOR3       4U   /*!< DMAMUX1 request generator 3     */
-#define LL_DMAMUX1_REQ_GENERATOR4       5U   /*!< DMAMUX1 request generator 4     */
-#define LL_DMAMUX1_REQ_GENERATOR5       6U   /*!< DMAMUX1 request generator 5     */
-#define LL_DMAMUX1_REQ_GENERATOR6       7U   /*!< DMAMUX1 request generator 6     */
-#define LL_DMAMUX1_REQ_GENERATOR7       8U   /*!< DMAMUX1 request generator 7     */
-#define LL_DMAMUX1_REQ_ADC1             9U   /*!< DMAMUX1 ADC1 request            */
-#define LL_DMAMUX1_REQ_ADC2             10U  /*!< DMAMUX1 ADC2 request            */
-#define LL_DMAMUX1_REQ_TIM1_CH1         11U  /*!< DMAMUX1 TIM1 CH1 request        */
-#define LL_DMAMUX1_REQ_TIM1_CH2         12U  /*!< DMAMUX1 TIM1 CH2 request        */
-#define LL_DMAMUX1_REQ_TIM1_CH3         13U  /*!< DMAMUX1 TIM1 CH3 request        */
-#define LL_DMAMUX1_REQ_TIM1_CH4         14U  /*!< DMAMUX1 TIM1 CH4 request        */
-#define LL_DMAMUX1_REQ_TIM1_UP          15U  /*!< DMAMUX1 TIM1 UP request         */
-#define LL_DMAMUX1_REQ_TIM1_TRIG        16U  /*!< DMAMUX1 TIM1 TRIG request       */
-#define LL_DMAMUX1_REQ_TIM1_COM         17U  /*!< DMAMUX1 TIM1 COM request        */
-#define LL_DMAMUX1_REQ_TIM2_CH1         18U  /*!< DMAMUX1 TIM2 CH1 request        */
-#define LL_DMAMUX1_REQ_TIM2_CH2         19U  /*!< DMAMUX1 TIM2 CH2 request        */
-#define LL_DMAMUX1_REQ_TIM2_CH3         20U  /*!< DMAMUX1 TIM2 CH3 request        */
-#define LL_DMAMUX1_REQ_TIM2_CH4         21U  /*!< DMAMUX1 TIM2 CH4 request        */
-#define LL_DMAMUX1_REQ_TIM2_UP          22U  /*!< DMAMUX1 TIM2 UP request         */
-#define LL_DMAMUX1_REQ_TIM3_CH1         23U  /*!< DMAMUX1 TIM3 CH1 request        */
-#define LL_DMAMUX1_REQ_TIM3_CH2         24U  /*!< DMAMUX1 TIM3 CH2 request        */
-#define LL_DMAMUX1_REQ_TIM3_CH3         25U  /*!< DMAMUX1 TIM3 CH3 request        */
-#define LL_DMAMUX1_REQ_TIM3_CH4         26U  /*!< DMAMUX1 TIM3 CH4 request        */
-#define LL_DMAMUX1_REQ_TIM3_UP          27U  /*!< DMAMUX1 TIM3 UP request         */
-#define LL_DMAMUX1_REQ_TIM3_TRIG        28U  /*!< DMAMUX1 TIM3 TRIG request       */
-#define LL_DMAMUX1_REQ_TIM4_CH1         29U  /*!< DMAMUX1 TIM4 CH1 request        */
-#define LL_DMAMUX1_REQ_TIM4_CH2         30U  /*!< DMAMUX1 TIM4 CH2 request        */
-#define LL_DMAMUX1_REQ_TIM4_CH3         31U  /*!< DMAMUX1 TIM4 CH3 request        */
-#define LL_DMAMUX1_REQ_TIM4_UP          32U  /*!< DMAMUX1 TIM4 UP request         */
-#define LL_DMAMUX1_REQ_I2C1_RX          33U  /*!< DMAMUX1 I2C1 RX request         */
-#define LL_DMAMUX1_REQ_I2C1_TX          34U  /*!< DMAMUX1 I2C1 TX request         */
-#define LL_DMAMUX1_REQ_I2C2_RX          35U  /*!< DMAMUX1 I2C2 RX request         */
-#define LL_DMAMUX1_REQ_I2C2_TX          36U  /*!< DMAMUX1 I2C2 TX request         */
-#define LL_DMAMUX1_REQ_SPI1_RX          37U  /*!< DMAMUX1 SPI1 RX request         */
-#define LL_DMAMUX1_REQ_SPI1_TX          38U  /*!< DMAMUX1 SPI1 TX request         */
-#define LL_DMAMUX1_REQ_SPI2_RX          39U  /*!< DMAMUX1 SPI2 RX request         */
-#define LL_DMAMUX1_REQ_SPI2_TX          40U  /*!< DMAMUX1 SPI2 TX request         */
-#define LL_DMAMUX1_REQ_USART1_RX        41U  /*!< DMAMUX1 USART1 RX request       */
-#define LL_DMAMUX1_REQ_USART1_TX        42U  /*!< DMAMUX1 USART1 TX request       */
-#define LL_DMAMUX1_REQ_USART2_RX        43U  /*!< DMAMUX1 USART2 RX request       */
-#define LL_DMAMUX1_REQ_USART2_TX        44U  /*!< DMAMUX1 USART2 TX request       */
-#define LL_DMAMUX1_REQ_USART3_RX        45U  /*!< DMAMUX1 USART3 RX request       */
-#define LL_DMAMUX1_REQ_USART3_TX        46U  /*!< DMAMUX1 USART3 TX request       */
-#define LL_DMAMUX1_REQ_TIM8_CH1         47U  /*!< DMAMUX1 TIM8 CH1 request        */
-#define LL_DMAMUX1_REQ_TIM8_CH2         48U  /*!< DMAMUX1 TIM8 CH2 request        */
-#define LL_DMAMUX1_REQ_TIM8_CH3         49U  /*!< DMAMUX1 TIM8 CH3 request        */
-#define LL_DMAMUX1_REQ_TIM8_CH4         50U  /*!< DMAMUX1 TIM8 CH4 request        */
-#define LL_DMAMUX1_REQ_TIM8_UP          51U  /*!< DMAMUX1 TIM8 UP request         */
-#define LL_DMAMUX1_REQ_TIM8_TRIG        52U  /*!< DMAMUX1 TIM8 TRIG request       */
-#define LL_DMAMUX1_REQ_TIM8_COM         53U  /*!< DMAMUX1 TIM8 COM request        */
-#define LL_DMAMUX1_REQ_TIM5_CH1         55U  /*!< DMAMUX1 TIM5 CH1 request        */
-#define LL_DMAMUX1_REQ_TIM5_CH2         56U  /*!< DMAMUX1 TIM5 CH2 request        */
-#define LL_DMAMUX1_REQ_TIM5_CH3         57U  /*!< DMAMUX1 TIM5 CH3 request        */
-#define LL_DMAMUX1_REQ_TIM5_CH4         58U  /*!< DMAMUX1 TIM5 CH4 request        */
-#define LL_DMAMUX1_REQ_TIM5_UP          59U  /*!< DMAMUX1 TIM5 UP request         */
-#define LL_DMAMUX1_REQ_TIM5_TRIG        60U  /*!< DMAMUX1 TIM5 TRIG request       */
-#define LL_DMAMUX1_REQ_SPI3_RX          61U  /*!< DMAMUX1 SPI3 RX request         */
-#define LL_DMAMUX1_REQ_SPI3_TX          62U  /*!< DMAMUX1 SPI3 TX request         */
-#define LL_DMAMUX1_REQ_UART4_RX         63U  /*!< DMAMUX1 UART4 RX request        */
-#define LL_DMAMUX1_REQ_UART4_TX         64U  /*!< DMAMUX1 UART4 TX request        */
-#define LL_DMAMUX1_REQ_UART5_RX         65U  /*!< DMAMUX1 UART5 RX request        */
-#define LL_DMAMUX1_REQ_UART5_TX         66U  /*!< DMAMUX1 UART5 TX request        */
-#define LL_DMAMUX1_REQ_DAC1_CH1         67U  /*!< DMAMUX1 DAC1 Channel 1 request  */
-#define LL_DMAMUX1_REQ_DAC1_CH2         68U  /*!< DMAMUX1 DAC1 Channel 2 request  */
-#define LL_DMAMUX1_REQ_TIM6_UP          69U  /*!< DMAMUX1 TIM6 UP request         */
-#define LL_DMAMUX1_REQ_TIM7_UP          70U  /*!< DMAMUX1 TIM7 UP request         */
-#define LL_DMAMUX1_REQ_USART6_RX        71U  /*!< DMAMUX1 USART6 RX request       */
-#define LL_DMAMUX1_REQ_USART6_TX        72U  /*!< DMAMUX1 USART6 TX request       */
-#define LL_DMAMUX1_REQ_I2C3_RX          73U  /*!< DMAMUX1 I2C3 RX request         */
-#define LL_DMAMUX1_REQ_I2C3_TX          74U  /*!< DMAMUX1 I2C3 TX request         */
-#if defined (PSSI)
-#define LL_DMAMUX1_REQ_DCMI_PSSI        75U  /*!< DMAMUX1 DCMI/PSSI request       */
-#define LL_DMAMUX1_REQ_DCMI             LL_DMAMUX1_REQ_DCMI_PSSI /* Legacy define */
-#else
-#define LL_DMAMUX1_REQ_DCMI             75U  /*!< DMAMUX1 DCMI request            */
-#endif /* PSSI */
-#define LL_DMAMUX1_REQ_CRYP_IN          76U  /*!< DMAMUX1 CRYP IN request         */
-#define LL_DMAMUX1_REQ_CRYP_OUT         77U  /*!< DMAMUX1 CRYP OUT request        */
-#define LL_DMAMUX1_REQ_HASH_IN          78U  /*!< DMAMUX1 HASH IN request         */
-#define LL_DMAMUX1_REQ_UART7_RX         79U  /*!< DMAMUX1 UART7 RX request        */
-#define LL_DMAMUX1_REQ_UART7_TX         80U  /*!< DMAMUX1 UART7 TX request        */
-#define LL_DMAMUX1_REQ_UART8_RX         81U  /*!< DMAMUX1 UART8 RX request        */
-#define LL_DMAMUX1_REQ_UART8_TX         82U  /*!< DMAMUX1 UART8 TX request        */
-#define LL_DMAMUX1_REQ_SPI4_RX          83U  /*!< DMAMUX1 SPI4 RX request         */
-#define LL_DMAMUX1_REQ_SPI4_TX          84U  /*!< DMAMUX1 SPI4 TX request         */
-#define LL_DMAMUX1_REQ_SPI5_RX          85U  /*!< DMAMUX1 SPI5 RX request         */
-#define LL_DMAMUX1_REQ_SPI5_TX          86U  /*!< DMAMUX1 SPI5 TX request         */
-#define LL_DMAMUX1_REQ_SAI1_A           87U  /*!< DMAMUX1 SAI1 A request          */
-#define LL_DMAMUX1_REQ_SAI1_B           88U  /*!< DMAMUX1 SAI1 B request          */
-#if defined(SAI2)
-#define LL_DMAMUX1_REQ_SAI2_A           89U  /*!< DMAMUX1 SAI2 A request          */
-#define LL_DMAMUX1_REQ_SAI2_B           90U  /*!< DMAMUX1 SAI2 B request          */
-#endif /* SAI2 */
-#define LL_DMAMUX1_REQ_SWPMI_RX         91U  /*!< DMAMUX1 SWPMI RX request        */
-#define LL_DMAMUX1_REQ_SWPMI_TX         92U  /*!< DMAMUX1 SWPMI TX request        */
-#define LL_DMAMUX1_REQ_SPDIF_RX_DT      93U  /*!< DMAMUX1 SPDIF RXDT request      */
-#define LL_DMAMUX1_REQ_SPDIF_RX_CS      94U  /*!< DMAMUX1 SPDIF RXCS request      */
-#if defined (HRTIM1)
-#define LL_DMAMUX1_REQ_HRTIM_MASTER     95U  /*!< DMAMUX1 HRTIM1 Master request 1 */
-#define LL_DMAMUX1_REQ_HRTIM_TIMER_A    96U  /*!< DMAMUX1 HRTIM1 Timer A request 2 */
-#define LL_DMAMUX1_REQ_HRTIM_TIMER_B    97U  /*!< DMAMUX1 HRTIM1 Timer B request 3 */
-#define LL_DMAMUX1_REQ_HRTIM_TIMER_C    98U  /*!< DMAMUX1 HRTIM1 Timer C request 4 */
-#define LL_DMAMUX1_REQ_HRTIM_TIMER_D    99U  /*!< DMAMUX1 HRTIM1 Timer D request 5 */
-#define LL_DMAMUX1_REQ_HRTIM_TIMER_E   100U  /*!< DMAMUX1 HRTIM1 Timer E request 6 */
-#endif /* HRTIM1 */
-#define LL_DMAMUX1_REQ_DFSDM1_FLT0     101U  /*!< DMAMUX1 DFSDM1 Filter0 request  */
-#define LL_DMAMUX1_REQ_DFSDM1_FLT1     102U  /*!< DMAMUX1 DFSDM1 Filter1 request  */
-#define LL_DMAMUX1_REQ_DFSDM1_FLT2     103U  /*!< DMAMUX1 DFSDM1 Filter2 request  */
-#define LL_DMAMUX1_REQ_DFSDM1_FLT3     104U  /*!< DMAMUX1 DFSDM1 Filter3 request  */
-#define LL_DMAMUX1_REQ_TIM15_CH1       105U  /*!< DMAMUX1 TIM15 CH1 request       */
-#define LL_DMAMUX1_REQ_TIM15_UP        106U  /*!< DMAMUX1 TIM15 UP request        */
-#define LL_DMAMUX1_REQ_TIM15_TRIG      107U  /*!< DMAMUX1 TIM15 TRIG request      */
-#define LL_DMAMUX1_REQ_TIM15_COM       108U  /*!< DMAMUX1 TIM15 COM request       */
-#define LL_DMAMUX1_REQ_TIM16_CH1       109U  /*!< DMAMUX1 TIM16 CH1 request       */
-#define LL_DMAMUX1_REQ_TIM16_UP        110U  /*!< DMAMUX1 TIM16 UP request        */
-#define LL_DMAMUX1_REQ_TIM17_CH1       111U  /*!< DMAMUX1 TIM17 CH1 request       */
-#define LL_DMAMUX1_REQ_TIM17_UP        112U  /*!< DMAMUX1 TIM17 UP request        */
-#if defined (SAI3)
-#define LL_DMAMUX1_REQ_SAI3_A          113U  /*!< DMAMUX1 SAI3 A request          */
-#define LL_DMAMUX1_REQ_SAI3_B          114U  /*!< DMAMUX1 SAI3 B request          */
-#endif /* SAI3 */
-#if defined (ADC3)
-#define LL_DMAMUX1_REQ_ADC3            115U  /*!< DMAMUX1 ADC3  request           */
-#endif /* ADC3 */
-#if defined (UART9)
-#define LL_DMAMUX1_REQ_UART9_RX        116U  /*!< DMAMUX1 UART9 RX request        */
-#define LL_DMAMUX1_REQ_UART9_TX        117U  /*!< DMAMUX1 UART9 TX request        */
-#endif /* UART9 */
-#if defined (USART10)
-#define LL_DMAMUX1_REQ_USART10_RX      118U  /*!< DMAMUX1 USART10 RX request      */
-#define LL_DMAMUX1_REQ_USART10_TX      119U  /*!< DMAMUX1 USART10 TX request      */
-#endif /* USART10 */
-#if defined(FMAC)
-#define LL_DMAMUX1_REQ_FMAC_READ       120U  /*!< DMAMUX1 FMAC Read request       */
-#define LL_DMAMUX1_REQ_FMAC_WRITE      121U  /*!< DMAMUX1 FMAC Write request      */
-#endif /* FMAC */
-#if defined(CORDIC)
-#define LL_DMAMUX1_REQ_CORDIC_READ     122U  /*!< DMAMUX1 CORDIC Read request     */
-#define LL_DMAMUX1_REQ_CORDIC_WRITE    123U  /*!< DMAMUX1 CORDIC Write request    */
-#endif /* CORDIC */
-#if defined(I2C5)
-#define LL_DMAMUX1_REQ_I2C5_RX         124U  /*!< DMAMUX1 I2C5 RX request         */
-#define LL_DMAMUX1_REQ_I2C5_TX         125U  /*!< DMAMUX1 I2C5 TX request         */
-#endif /* I2C5 */
-#if defined(TIM23)
-#define LL_DMAMUX1_REQ_TIM23_CH1       126U  /*!< DMAMUX1 TIM23 CH1 request  */
-#define LL_DMAMUX1_REQ_TIM23_CH2       127U  /*!< DMAMUX1 TIM23 CH2 request  */
-#define LL_DMAMUX1_REQ_TIM23_CH3       128U  /*!< DMAMUX1 TIM23 CH3 request  */
-#define LL_DMAMUX1_REQ_TIM23_CH4       129U  /*!< DMAMUX1 TIM23 CH4 request  */
-#define LL_DMAMUX1_REQ_TIM23_UP        130U  /*!< DMAMUX1 TIM23 UP request   */
-#define LL_DMAMUX1_REQ_TIM23_TRIG      131U  /*!< DMAMUX1 TIM23 TRIG request */
-#endif /* TIM23 */
-#if defined(TIM24)
-#define LL_DMAMUX1_REQ_TIM24_CH1       132U  /*!< DMAMUX1 TIM24 CH1 request  */
-#define LL_DMAMUX1_REQ_TIM24_CH2       133U  /*!< DMAMUX1 TIM24 CH2 request  */
-#define LL_DMAMUX1_REQ_TIM24_CH3       134U  /*!< DMAMUX1 TIM24 CH3 request  */
-#define LL_DMAMUX1_REQ_TIM24_CH4       135U  /*!< DMAMUX1 TIM24 CH4 request  */
-#define LL_DMAMUX1_REQ_TIM24_UP        136U  /*!< DMAMUX1 TIM24 UP request   */
-#define LL_DMAMUX1_REQ_TIM24_TRIG      137U  /*!< DMAMUX1 TIM24 TRIG request */
-#endif /* TIM24 */
-/**
-  * @}
-  */
-
-/** @defgroup DMAMUX2_Request_selection DMAMUX2 Request selection
-  * @brief    DMAMUX2 Request selection
-  * @{
-  */
-/* DMAMUX2 requests */
-#define LL_DMAMUX2_REQ_MEM2MEM          0U  /*!< memory to memory transfer        */
-#define LL_DMAMUX2_REQ_GENERATOR0       1U  /*!< DMAMUX2 request generator 0      */
-#define LL_DMAMUX2_REQ_GENERATOR1       2U  /*!< DMAMUX2 request generator 1      */
-#define LL_DMAMUX2_REQ_GENERATOR2       3U  /*!< DMAMUX2 request generator 2      */
-#define LL_DMAMUX2_REQ_GENERATOR3       4U  /*!< DMAMUX2 request generator 3      */
-#define LL_DMAMUX2_REQ_GENERATOR4       5U  /*!< DMAMUX2 request generator 4      */
-#define LL_DMAMUX2_REQ_GENERATOR5       6U  /*!< DMAMUX2 request generator 5      */
-#define LL_DMAMUX2_REQ_GENERATOR6       7U  /*!< DMAMUX2 request generator 6      */
-#define LL_DMAMUX2_REQ_GENERATOR7       8U  /*!< DMAMUX2 request generator 7      */
-#define LL_DMAMUX2_REQ_LPUART1_RX       9U  /*!< DMAMUX2 LP_UART1_RX request      */
-#define LL_DMAMUX2_REQ_LPUART1_TX      10U  /*!< DMAMUX2 LP_UART1_TX request      */
-#define LL_DMAMUX2_REQ_SPI6_RX         11U  /*!< DMAMUX2 SPI6 RX request          */
-#define LL_DMAMUX2_REQ_SPI6_TX         12U  /*!< DMAMUX2 SPI6 TX request          */
-#define LL_DMAMUX2_REQ_I2C4_RX         13U  /*!< DMAMUX2 I2C4 RX request          */
-#define LL_DMAMUX2_REQ_I2C4_TX         14U  /*!< DMAMUX2 I2C4 TX request          */
-#if defined (SAI4)
-#define LL_DMAMUX2_REQ_SAI4_A          15U  /*!< DMAMUX2 SAI4 A request           */
-#define LL_DMAMUX2_REQ_SAI4_B          16U  /*!< DMAMUX2 SAI4 B request           */
-#endif /* SAI4 */
-#if defined (ADC3)
-#define LL_DMAMUX2_REQ_ADC3            17U  /*!< DMAMUX2 ADC3 request             */
-#endif /* ADC3 */
-#if defined (DAC2)
-#define LL_DMAMUX2_REQ_DAC2_CH1        17U  /*!< DMAMUX2 DAC2 CH1 request         */
-#endif /* DAC2 */
-#if defined (DFSDM2_Channel0)
-#define LL_DMAMUX2_REQ_DFSDM2_FLT0     18U  /*!< DMAMUX2 DFSDM2 Filter0 request   */
-#endif /* DFSDM2_Channel0 */
-/**
-  * @}
-  */
-
-
-/** @defgroup DMAMUX_LL_EC_CHANNEL DMAMUX Channel
-  * @{
-  */
-#define LL_DMAMUX_CHANNEL_0     0x00000000U  /*!< DMAMUX1 Channel 0  connected to DMA1 Channel 0 , DMAMUX2 Channel 0 connected to BDMA Channel 0 */
-#define LL_DMAMUX_CHANNEL_1     0x00000001U  /*!< DMAMUX1 Channel 1  connected to DMA1 Channel 1 , DMAMUX2 Channel 1 connected to BDMA Channel 1 */
-#define LL_DMAMUX_CHANNEL_2     0x00000002U  /*!< DMAMUX1 Channel 2  connected to DMA1 Channel 2 , DMAMUX2 Channel 2 connected to BDMA Channel 2 */
-#define LL_DMAMUX_CHANNEL_3     0x00000003U  /*!< DMAMUX1 Channel 3  connected to DMA1 Channel 3 , DMAMUX2 Channel 3 connected to BDMA Channel 3 */
-#define LL_DMAMUX_CHANNEL_4     0x00000004U  /*!< DMAMUX1 Channel 4  connected to DMA1 Channel 4 , DMAMUX2 Channel 4 connected to BDMA Channel 4 */
-#define LL_DMAMUX_CHANNEL_5     0x00000005U  /*!< DMAMUX1 Channel 5  connected to DMA1 Channel 5 , DMAMUX2 Channel 5 connected to BDMA Channel 5 */
-#define LL_DMAMUX_CHANNEL_6     0x00000006U  /*!< DMAMUX1 Channel 6  connected to DMA1 Channel 6 , DMAMUX2 Channel 6 connected to BDMA Channel 6 */
-#define LL_DMAMUX_CHANNEL_7     0x00000007U  /*!< DMAMUX1 Channel 7  connected to DMA1 Channel 7 , DMAMUX2 Channel 7 connected to BDMA Channel 7 */
-#define LL_DMAMUX_CHANNEL_8     0x00000008U  /*!< DMAMUX1 Channel 8  connected to DMA2 Channel 0 */
-#define LL_DMAMUX_CHANNEL_9     0x00000009U  /*!< DMAMUX1 Channel 9  connected to DMA2 Channel 1 */
-#define LL_DMAMUX_CHANNEL_10    0x0000000AU  /*!< DMAMUX1 Channel 10 connected to DMA2 Channel 2 */
-#define LL_DMAMUX_CHANNEL_11    0x0000000BU  /*!< DMAMUX1 Channel 11 connected to DMA2 Channel 3 */
-#define LL_DMAMUX_CHANNEL_12    0x0000000CU  /*!< DMAMUX1 Channel 12 connected to DMA2 Channel 4 */
-#define LL_DMAMUX_CHANNEL_13    0x0000000DU  /*!< DMAMUX1 Channel 13 connected to DMA2 Channel 5 */
-#define LL_DMAMUX_CHANNEL_14    0x0000000EU  /*!< DMAMUX1 Channel 14 connected to DMA2 Channel 6 */
-#define LL_DMAMUX_CHANNEL_15    0x0000000FU  /*!< DMAMUX1 Channel 15 connected to DMA2 Channel 7 */
-/**
-  * @}
-  */
-
-/** @defgroup DMAMUX_LL_EC_SYNC_NO Synchronization Signal Polarity
-  * @{
-  */
-#define LL_DMAMUX_SYNC_NO_EVENT            0x00000000U                               /*!< All requests are blocked                            */
-#define LL_DMAMUX_SYNC_POL_RISING          DMAMUX_CxCR_SPOL_0                        /*!< Synchronization on event on rising edge             */
-#define LL_DMAMUX_SYNC_POL_FALLING         DMAMUX_CxCR_SPOL_1                        /*!< Synchronization on event on falling edge            */
-#define LL_DMAMUX_SYNC_POL_RISING_FALLING  (DMAMUX_CxCR_SPOL_0 | DMAMUX_CxCR_SPOL_1) /*!< Synchronization on event on rising and falling edge */
-/**
-  * @}
-  */
-
-/** @defgroup DMAMUX_LL_EC_SYNC_EVT Synchronization Signal Event
-  * @{
-  */
-#define LL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT   0x00000000U   /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel0 Event */
-#define LL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT   0x01000000U   /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel1 Event */
-#define LL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT   0x02000000U   /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel2 Event */
-#define LL_DMAMUX1_SYNC_LPTIM1_OUT        0x03000000U   /*!< DMAMUX1 synchronization Signal is LPTIM1 OUT             */
-#define LL_DMAMUX1_SYNC_LPTIM2_OUT        0x04000000U   /*!< DMAMUX1 synchronization Signal is LPTIM2 OUT             */
-#define LL_DMAMUX1_SYNC_LPTIM3_OUT        0x05000000U   /*!< DMAMUX1 synchronization Signal is LPTIM3 OUT             */
-#define LL_DMAMUX1_SYNC_EXTI0             0x06000000U   /*!< DMAMUX1 synchronization Signal is EXTI0 IT               */
-#define LL_DMAMUX1_SYNC_TIM12_TRGO        0x07000000U   /*!< DMAMUX1 synchronization Signal is TIM12 TRGO             */
-
-#define LL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT   0x00000000U   /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel0 Event */
-#define LL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT   0x01000000U   /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel1 Event */
-#define LL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT   0x02000000U   /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel2 Event */
-#define LL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT   0x03000000U   /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel3 Event */
-#define LL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT   0x04000000U   /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel4 Event */
-#define LL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT   0x05000000U   /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel5 Event */
-#define LL_DMAMUX2_SYNC_LPUART1_RX_WKUP   0x06000000U   /*!< DMAMUX2 synchronization Signal is LPUART1 RX Wakeup      */
-#define LL_DMAMUX2_SYNC_LPUART1_TX_WKUP   0x07000000U   /*!< DMAMUX2 synchronization Signal is LPUART1 TX Wakeup      */
-#define LL_DMAMUX2_SYNC_LPTIM2_OUT        0x08000000U   /*!< DMAMUX2 synchronization Signal is LPTIM2 output          */
-#define LL_DMAMUX2_SYNC_LPTIM3_OUT        0x09000000U   /*!< DMAMUX2 synchronization Signal is LPTIM3 output          */
-#define LL_DMAMUX2_SYNC_I2C4_WKUP         0x0A000000U   /*!< DMAMUX2 synchronization Signal is I2C4 Wakeup            */
-#define LL_DMAMUX2_SYNC_SPI6_WKUP         0x0B000000U   /*!< DMAMUX2 synchronization Signal is SPI6 Wakeup            */
-#define LL_DMAMUX2_SYNC_COMP1_OUT         0x0C000000U   /*!< DMAMUX2 synchronization Signal is Comparator 1 output    */
-#define LL_DMAMUX2_SYNC_RTC_WKUP          0x0D000000U   /*!< DMAMUX2 synchronization Signal is RTC Wakeup             */
-#define LL_DMAMUX2_SYNC_EXTI0             0x0E000000U   /*!< DMAMUX2 synchronization Signal is EXTI0 IT               */
-#define LL_DMAMUX2_SYNC_EXTI2             0x0F000000U   /*!< DMAMUX2 synchronization Signal is EXTI2 IT               */
-
-/**
-  * @}
-  */
-
-/** @defgroup DMAMUX_LL_EC_REQUEST_GENERATOR Request Generator Channel
-  * @{
-  */
-#define LL_DMAMUX_REQ_GEN_0           0x00000000U
-#define LL_DMAMUX_REQ_GEN_1           0x00000001U
-#define LL_DMAMUX_REQ_GEN_2           0x00000002U
-#define LL_DMAMUX_REQ_GEN_3           0x00000003U
-#define LL_DMAMUX_REQ_GEN_4           0x00000004U
-#define LL_DMAMUX_REQ_GEN_5           0x00000005U
-#define LL_DMAMUX_REQ_GEN_6           0x00000006U
-#define LL_DMAMUX_REQ_GEN_7           0x00000007U
-/**
-  * @}
-  */
-
-/** @defgroup DMAMUX_LL_EC_REQUEST_GEN_POLARITY External Request Signal Generation Polarity
-  * @{
-  */
-#define LL_DMAMUX_REQ_GEN_NO_EVENT             0x00000000U                                  /*!< No external DMA request  generation                        */
-#define LL_DMAMUX_REQ_GEN_POL_RISING           DMAMUX_RGxCR_GPOL_0                          /*!< External DMA request generation on event on rising edge    */
-#define LL_DMAMUX_REQ_GEN_POL_FALLING          DMAMUX_RGxCR_GPOL_1                          /*!< External DMA request generation on event on falling edge   */
-#define LL_DMAMUX_REQ_GEN_POL_RISING_FALLING   (DMAMUX_RGxCR_GPOL_0 | DMAMUX_RGxCR_GPOL_1)  /*!< External DMA request generation on rising and falling edge */
-/**
-  * @}
-  */
-
-/** @defgroup DMAMUX_LL_EC_REQUEST_GEN External Request Signal Generation
-  * @{
-  */
-#define LL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT   0U   /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel0 Event        */
-#define LL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT   1U   /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel1 Event        */
-#define LL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT   2U   /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel2 Event        */
-#define LL_DMAMUX1_REQ_GEN_LPTIM1_OUT        3U   /*!< DMAMUX1 Request generator Signal is LPTIM1 OUT                    */
-#define LL_DMAMUX1_REQ_GEN_LPTIM2_OUT        4U   /*!< DMAMUX1 Request generator Signal is LPTIM2 OUT                    */
-#define LL_DMAMUX1_REQ_GEN_LPTIM3_OUT        5U   /*!< DMAMUX1 Request generator Signal is LPTIM3 OUT                    */
-#define LL_DMAMUX1_REQ_GEN_EXTI0             6U   /*!< DMAMUX1 Request generator Signal is EXTI0 IT                      */
-#define LL_DMAMUX1_REQ_GEN_TIM12_TRGO        7U   /*!< DMAMUX1 Request generator Signal is TIM12 TRGO                    */
-
-#define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT   0U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel0 Event        */
-#define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT   1U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel1 Event        */
-#define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT   2U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel2 Event        */
-#define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT   3U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel3 Event        */
-#define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT   4U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel4 Event        */
-#define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT   5U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel5 Event        */
-#define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT   6U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel6 Event        */
-#define LL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP   7U   /*!< DMAMUX2 Request generator Signal is LPUART1 RX Wakeup             */
-#define LL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP   8U   /*!< DMAMUX2 Request generator Signal is LPUART1 TX Wakeup             */
-#define LL_DMAMUX2_REQ_GEN_LPTIM2_WKUP       9U   /*!< DMAMUX2 Request generator Signal is LPTIM2 Wakeup                 */
-#define LL_DMAMUX2_REQ_GEN_LPTIM2_OUT       10U   /*!< DMAMUX2 Request generator Signal is LPTIM2 OUT                    */
-#define LL_DMAMUX2_REQ_GEN_LPTIM3_WKUP      11U   /*!< DMAMUX2 Request generator Signal is LPTIM3 Wakeup                 */
-#define LL_DMAMUX2_REQ_GEN_LPTIM3_OUT       12U   /*!< DMAMUX2 Request generator Signal is LPTIM3 OUT                    */
-#if defined (LPTIM4)
-#define LL_DMAMUX2_REQ_GEN_LPTIM4_WKUP      13U   /*!< DMAMUX2 Request generator Signal is LPTIM4 Wakeup                 */
-#endif /* LPTIM4 */
-#if defined (LPTIM5)
-#define LL_DMAMUX2_REQ_GEN_LPTIM5_WKUP      14U   /*!< DMAMUX2 Request generator Signal is LPTIM5 Wakeup                 */
-#endif /* LPTIM5 */
-#define LL_DMAMUX2_REQ_GEN_I2C4_WKUP        15U   /*!< DMAMUX2 Request generator Signal is I2C4 Wakeup                   */
-#define LL_DMAMUX2_REQ_GEN_SPI6_WKUP        16U   /*!< DMAMUX2 Request generator Signal is SPI6 Wakeup                   */
-#define LL_DMAMUX2_REQ_GEN_COMP1_OUT        17U   /*!< DMAMUX2 Request generator Signal is Comparator 1 output           */
-#define LL_DMAMUX2_REQ_GEN_COMP2_OUT        18U   /*!< DMAMUX2 Request generator Signal is Comparator 2 output           */
-#define LL_DMAMUX2_REQ_GEN_RTC_WKUP         19U   /*!< DMAMUX2 Request generator Signal is RTC Wakeup                    */
-#define LL_DMAMUX2_REQ_GEN_EXTI0            20U   /*!< DMAMUX2 Request generator Signal is EXTI0                         */
-#define LL_DMAMUX2_REQ_GEN_EXTI2            21U   /*!< DMAMUX2 Request generator Signal is EXTI2                         */
-#define LL_DMAMUX2_REQ_GEN_I2C4_IT_EVT      22U   /*!< DMAMUX2 Request generator Signal is I2C4 IT Event                 */
-#define LL_DMAMUX2_REQ_GEN_SPI6_IT          23U   /*!< DMAMUX2 Request generator Signal is SPI6 IT                       */
-#define LL_DMAMUX2_REQ_GEN_LPUART1_TX_IT    24U   /*!< DMAMUX2 Request generator Signal is LPUART1 Tx IT                 */
-#define LL_DMAMUX2_REQ_GEN_LPUART1_RX_IT    25U   /*!< DMAMUX2 Request generator Signal is LPUART1 Rx IT                 */
-#if defined (ADC3)
-#define LL_DMAMUX2_REQ_GEN_ADC3_IT          26U   /*!< DMAMUX2 Request generator Signal is ADC3 IT                       */
-#define LL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT    27U   /*!< DMAMUX2 Request generator Signal is ADC3 Analog Watchdog 1 output */
-#endif /* ADC3 */
-#define LL_DMAMUX2_REQ_GEN_BDMA_CH0_IT      28U   /*!< DMAMUX2 Request generator Signal is BDMA Channel 0 IT             */
-#define LL_DMAMUX2_REQ_GEN_BDMA_CH1_IT      29U   /*!< DMAMUX2 Request generator Signal is BDMA Channel 1 IT             */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup DMAMUX_LL_Exported_Macros DMAMUX Exported Macros
-  * @{
-  */
-
-/** @defgroup DMAMUX_LL_EM_WRITE_READ Common Write and read registers macros
-  * @{
-  */
-/**
-  * @brief  Write a value in DMAMUX register
-  * @param  __INSTANCE__ DMAMUX Instance
-  * @param  __REG__ Register to be written
-  * @param  __VALUE__ Value to be written in the register
-  * @retval None
-  */
-#define LL_DMAMUX_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
-  * @brief  Read a value in DMAMUX register
-  * @param  __INSTANCE__ DMAMUX Instance
-  * @param  __REG__ Register to be read
-  * @retval Register value
-  */
-#define LL_DMAMUX_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup DMAMUX_LL_Exported_Functions DMAMUX Exported Functions
- * @{
- */
-
-/** @defgroup DMAMUX_LL_EF_Configuration Configuration
-  * @{
-  */
-/**
-  * @brief  Set DMAMUX request ID for DMAMUX Channel x.
-  * @note   DMAMUX1 channel 0 to 7 are mapped to DMA1 channel 0 to 7.
-  *         DMAMUX1 channel 8 to 15 are mapped to DMA2 channel 0 to 7.
-  *         DMAMUX2 channel 0 to 7 are mapped to  BDMA channel 0 to 7.
-  * @rmtoll CxCR         DMAREQ_ID     LL_DMAMUX_SetRequestID
-  * @param  DMAMUXx DMAMUXx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMAMUX_CHANNEL_0
-  *         @arg @ref LL_DMAMUX_CHANNEL_1
-  *         @arg @ref LL_DMAMUX_CHANNEL_2
-  *         @arg @ref LL_DMAMUX_CHANNEL_3
-  *         @arg @ref LL_DMAMUX_CHANNEL_4
-  *         @arg @ref LL_DMAMUX_CHANNEL_5
-  *         @arg @ref LL_DMAMUX_CHANNEL_6
-  *         @arg @ref LL_DMAMUX_CHANNEL_7
-  *         @arg @ref LL_DMAMUX_CHANNEL_8
-  *         @arg @ref LL_DMAMUX_CHANNEL_9
-  *         @arg @ref LL_DMAMUX_CHANNEL_10
-  *         @arg @ref LL_DMAMUX_CHANNEL_11
-  *         @arg @ref LL_DMAMUX_CHANNEL_12
-  *         @arg @ref LL_DMAMUX_CHANNEL_13
-  *         @arg @ref LL_DMAMUX_CHANNEL_14
-  *         @arg @ref LL_DMAMUX_CHANNEL_15
-  * @param  Request This parameter can be one of the following values:
-  *         @arg @ref LL_DMAMUX1_REQ_MEM2MEM
-  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR0
-  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR1
-  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR2
-  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR3
-  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR4
-  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR5
-  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR6
-  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR7
-  *         @arg @ref LL_DMAMUX1_REQ_ADC1
-  *         @arg @ref LL_DMAMUX1_REQ_ADC2
-  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH1
-  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH2
-  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH3
-  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH4
-  *         @arg @ref LL_DMAMUX1_REQ_TIM1_UP
-  *         @arg @ref LL_DMAMUX1_REQ_TIM1_TRIG
-  *         @arg @ref LL_DMAMUX1_REQ_TIM1_COM
-  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH1
-  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH2
-  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH3
-  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH4
-  *         @arg @ref LL_DMAMUX1_REQ_TIM2_UP
-  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH1
-  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH2
-  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH3
-  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH4
-  *         @arg @ref LL_DMAMUX1_REQ_TIM3_UP
-  *         @arg @ref LL_DMAMUX1_REQ_TIM3_TRIG
-  *         @arg @ref LL_DMAMUX1_REQ_TIM4_CH1
-  *         @arg @ref LL_DMAMUX1_REQ_TIM4_CH2
-  *         @arg @ref LL_DMAMUX1_REQ_TIM4_CH3
-  *         @arg @ref LL_DMAMUX1_REQ_TIM4_UP
-  *         @arg @ref LL_DMAMUX1_REQ_I2C1_RX
-  *         @arg @ref LL_DMAMUX1_REQ_I2C1_TX
-  *         @arg @ref LL_DMAMUX1_REQ_I2C2_RX
-  *         @arg @ref LL_DMAMUX1_REQ_I2C2_TX
-  *         @arg @ref LL_DMAMUX1_REQ_SPI1_RX
-  *         @arg @ref LL_DMAMUX1_REQ_SPI1_TX
-  *         @arg @ref LL_DMAMUX1_REQ_SPI2_RX
-  *         @arg @ref LL_DMAMUX1_REQ_SPI2_TX
-  *         @arg @ref LL_DMAMUX1_REQ_USART1_RX
-  *         @arg @ref LL_DMAMUX1_REQ_USART1_TX
-  *         @arg @ref LL_DMAMUX1_REQ_USART2_RX
-  *         @arg @ref LL_DMAMUX1_REQ_USART2_TX
-  *         @arg @ref LL_DMAMUX1_REQ_USART3_RX
-  *         @arg @ref LL_DMAMUX1_REQ_USART3_TX
-  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH1
-  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH2
-  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH3
-  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH4
-  *         @arg @ref LL_DMAMUX1_REQ_TIM8_UP
-  *         @arg @ref LL_DMAMUX1_REQ_TIM8_TRIG
-  *         @arg @ref LL_DMAMUX1_REQ_TIM8_COM
-  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH1
-  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH2
-  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH3
-  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH4
-  *         @arg @ref LL_DMAMUX1_REQ_TIM5_UP
-  *         @arg @ref LL_DMAMUX1_REQ_TIM5_TRIG
-  *         @arg @ref LL_DMAMUX1_REQ_SPI3_RX
-  *         @arg @ref LL_DMAMUX1_REQ_SPI3_TX
-  *         @arg @ref LL_DMAMUX1_REQ_UART4_RX
-  *         @arg @ref LL_DMAMUX1_REQ_UART4_TX
-  *         @arg @ref LL_DMAMUX1_REQ_UART5_RX
-  *         @arg @ref LL_DMAMUX1_REQ_UART5_TX
-  *         @arg @ref LL_DMAMUX1_REQ_DAC1_CH1
-  *         @arg @ref LL_DMAMUX1_REQ_DAC1_CH2
-  *         @arg @ref LL_DMAMUX1_REQ_TIM6_UP
-  *         @arg @ref LL_DMAMUX1_REQ_TIM7_UP
-  *         @arg @ref LL_DMAMUX1_REQ_USART6_RX
-  *         @arg @ref LL_DMAMUX1_REQ_USART6_TX
-  *         @arg @ref LL_DMAMUX1_REQ_I2C3_RX
-  *         @arg @ref LL_DMAMUX1_REQ_I2C3_TX
-  *         @arg @ref LL_DMAMUX1_REQ_DCMI_PSSI (*)
-  *         @arg @ref LL_DMAMUX1_REQ_CRYP_IN
-  *         @arg @ref LL_DMAMUX1_REQ_CRYP_OUT
-  *         @arg @ref LL_DMAMUX1_REQ_HASH_IN
-  *         @arg @ref LL_DMAMUX1_REQ_UART7_RX
-  *         @arg @ref LL_DMAMUX1_REQ_UART7_TX
-  *         @arg @ref LL_DMAMUX1_REQ_UART8_RX
-  *         @arg @ref LL_DMAMUX1_REQ_UART8_TX
-  *         @arg @ref LL_DMAMUX1_REQ_SPI4_RX
-  *         @arg @ref LL_DMAMUX1_REQ_SPI4_TX
-  *         @arg @ref LL_DMAMUX1_REQ_SPI5_RX
-  *         @arg @ref LL_DMAMUX1_REQ_SPI5_TX
-  *         @arg @ref LL_DMAMUX1_REQ_SAI1_A
-  *         @arg @ref LL_DMAMUX1_REQ_SAI1_B
-  *         @arg @ref LL_DMAMUX1_REQ_SAI2_A (*)
-  *         @arg @ref LL_DMAMUX1_REQ_SAI2_B (*)
-  *         @arg @ref LL_DMAMUX1_REQ_SWPMI_RX
-  *         @arg @ref LL_DMAMUX1_REQ_SWPMI_TX
-  *         @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_DT
-  *         @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_CS
-  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_MASTER (*)
-  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_A (*)
-  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_B (*)
-  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_C (*)
-  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_D (*)
-  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_E (*)
-  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT0
-  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT1
-  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT2
-  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT3
-  *         @arg @ref LL_DMAMUX1_REQ_TIM15_CH1
-  *         @arg @ref LL_DMAMUX1_REQ_TIM15_UP
-  *         @arg @ref LL_DMAMUX1_REQ_TIM15_TRIG
-  *         @arg @ref LL_DMAMUX1_REQ_TIM15_COM
-  *         @arg @ref LL_DMAMUX1_REQ_TIM16_CH1
-  *         @arg @ref LL_DMAMUX1_REQ_TIM16_UP
-  *         @arg @ref LL_DMAMUX1_REQ_TIM17_CH1
-  *         @arg @ref LL_DMAMUX1_REQ_TIM17_UP
-  *         @arg @ref LL_DMAMUX1_REQ_SAI3_A (*)
-  *         @arg @ref LL_DMAMUX1_REQ_SAI3_B (*)
-  *         @arg @ref LL_DMAMUX1_REQ_ADC3 (*)
-  *         @arg @ref LL_DMAMUX1_REQ_UART9_RX (*)
-  *         @arg @ref LL_DMAMUX1_REQ_UART9_TX (*)
-  *         @arg @ref LL_DMAMUX1_REQ_USART10_RX (*)
-  *         @arg @ref LL_DMAMUX1_REQ_USART10_TX (*)
-  *         @arg @ref LL_DMAMUX1_REQ_FMAC_READ  (*)
-  *         @arg @ref LL_DMAMUX1_REQ_FMAC_WRITE (*)
-  *         @arg @ref LL_DMAMUX1_REQ_CORDIC_READ (*)
-  *         @arg @ref LL_DMAMUX1_REQ_CORDIC_WRITE(*)
-  *         @arg @ref LL_DMAMUX1_REQ_I2C5_RX     (*)
-  *         @arg @ref LL_DMAMUX1_REQ_I2C5_TX     (*)
-  *         @arg @ref LL_DMAMUX1_REQ_TIM23_CH1   (*)
-  *         @arg @ref LL_DMAMUX1_REQ_TIM23_CH2   (*)
-  *         @arg @ref LL_DMAMUX1_REQ_TIM23_CH3   (*)
-  *         @arg @ref LL_DMAMUX1_REQ_TIM23_CH4   (*)
-  *         @arg @ref LL_DMAMUX1_REQ_TIM23_UP    (*)
-  *         @arg @ref LL_DMAMUX1_REQ_TIM23_TRIG  (*)
-  *         @arg @ref LL_DMAMUX1_REQ_TIM24_CH1   (*)
-  *         @arg @ref LL_DMAMUX1_REQ_TIM24_CH2   (*)
-  *         @arg @ref LL_DMAMUX1_REQ_TIM24_CH3   (*)
-  *         @arg @ref LL_DMAMUX1_REQ_TIM24_CH4   (*)
-  *         @arg @ref LL_DMAMUX1_REQ_TIM24_UP    (*)
-  *         @arg @ref LL_DMAMUX1_REQ_TIM24_TRIG  (*)
-  *         @arg @ref LL_DMAMUX2_REQ_MEM2MEM
-  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR0
-  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR1
-  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR2
-  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR3
-  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR4
-  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR5
-  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR6
-  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR7
-  *         @arg @ref LL_DMAMUX2_REQ_LPUART1_RX
-  *         @arg @ref LL_DMAMUX2_REQ_LPUART1_TX
-  *         @arg @ref LL_DMAMUX2_REQ_SPI6_RX
-  *         @arg @ref LL_DMAMUX2_REQ_SPI6_TX
-  *         @arg @ref LL_DMAMUX2_REQ_I2C4_RX
-  *         @arg @ref LL_DMAMUX2_REQ_I2C4_TX
-  *         @arg @ref LL_DMAMUX2_REQ_SAI4_A (*)
-  *         @arg @ref LL_DMAMUX2_REQ_SAI4_B (*)
-  *         @arg @ref LL_DMAMUX2_REQ_ADC3 (*)
-  *         @arg @ref LL_DMAMUX2_REQ_DAC2_CH1 (*)
-  *         @arg @ref LL_DMAMUX2_REQ_DFSDM2_FLT0 (*)
-  *
-  * @note   (*) Availability depends on devices.
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMAMUX_SetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Request)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  MODIFY_REG(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_DMAREQ_ID, Request);
-}
-
-/**
-  * @brief  Get DMAMUX request ID for DMAMUX Channel x.
-  * @note   DMAMUX1 channel 0 to 7  are mapped to DMA1 channel 0 to 7.
-  *         DMAMUX1 channel 8 to 15 are mapped to DMA2 channel 0 to 7.
-  *         DMAMUX2 channel 0 to 7  are mapped to BDMA channel 0 to 7.
-  * @rmtoll CxCR         DMAREQ_ID     LL_DMAMUX_GetRequestID
-  * @param  DMAMUXx DMAMUXx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMAMUX_CHANNEL_0
-  *         @arg @ref LL_DMAMUX_CHANNEL_1
-  *         @arg @ref LL_DMAMUX_CHANNEL_2
-  *         @arg @ref LL_DMAMUX_CHANNEL_3
-  *         @arg @ref LL_DMAMUX_CHANNEL_4
-  *         @arg @ref LL_DMAMUX_CHANNEL_5
-  *         @arg @ref LL_DMAMUX_CHANNEL_6
-  *         @arg @ref LL_DMAMUX_CHANNEL_7
-  *         @arg @ref LL_DMAMUX_CHANNEL_8
-  *         @arg @ref LL_DMAMUX_CHANNEL_9
-  *         @arg @ref LL_DMAMUX_CHANNEL_10
-  *         @arg @ref LL_DMAMUX_CHANNEL_11
-  *         @arg @ref LL_DMAMUX_CHANNEL_12
-  *         @arg @ref LL_DMAMUX_CHANNEL_13
-  *         @arg @ref LL_DMAMUX_CHANNEL_14
-  *         @arg @ref LL_DMAMUX_CHANNEL_15
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DMAMUX1_REQ_MEM2MEM
-  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR0
-  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR1
-  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR2
-  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR3
-  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR4
-  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR5
-  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR6
-  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR7
-  *         @arg @ref LL_DMAMUX1_REQ_ADC1
-  *         @arg @ref LL_DMAMUX1_REQ_ADC2
-  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH1
-  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH2
-  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH3
-  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH4
-  *         @arg @ref LL_DMAMUX1_REQ_TIM1_UP
-  *         @arg @ref LL_DMAMUX1_REQ_TIM1_TRIG
-  *         @arg @ref LL_DMAMUX1_REQ_TIM1_COM
-  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH1
-  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH2
-  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH3
-  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH4
-  *         @arg @ref LL_DMAMUX1_REQ_TIM2_UP
-  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH1
-  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH2
-  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH3
-  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH4
-  *         @arg @ref LL_DMAMUX1_REQ_TIM3_UP
-  *         @arg @ref LL_DMAMUX1_REQ_TIM3_TRIG
-  *         @arg @ref LL_DMAMUX1_REQ_TIM4_CH1
-  *         @arg @ref LL_DMAMUX1_REQ_TIM4_CH2
-  *         @arg @ref LL_DMAMUX1_REQ_TIM4_CH3
-  *         @arg @ref LL_DMAMUX1_REQ_TIM4_UP
-  *         @arg @ref LL_DMAMUX1_REQ_I2C1_RX
-  *         @arg @ref LL_DMAMUX1_REQ_I2C1_TX
-  *         @arg @ref LL_DMAMUX1_REQ_I2C2_RX
-  *         @arg @ref LL_DMAMUX1_REQ_I2C2_TX
-  *         @arg @ref LL_DMAMUX1_REQ_SPI1_RX
-  *         @arg @ref LL_DMAMUX1_REQ_SPI1_TX
-  *         @arg @ref LL_DMAMUX1_REQ_SPI2_RX
-  *         @arg @ref LL_DMAMUX1_REQ_SPI2_TX
-  *         @arg @ref LL_DMAMUX1_REQ_USART1_RX
-  *         @arg @ref LL_DMAMUX1_REQ_USART1_TX
-  *         @arg @ref LL_DMAMUX1_REQ_USART2_RX
-  *         @arg @ref LL_DMAMUX1_REQ_USART2_TX
-  *         @arg @ref LL_DMAMUX1_REQ_USART3_RX
-  *         @arg @ref LL_DMAMUX1_REQ_USART3_TX
-  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH1
-  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH2
-  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH3
-  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH4
-  *         @arg @ref LL_DMAMUX1_REQ_TIM8_UP
-  *         @arg @ref LL_DMAMUX1_REQ_TIM8_TRIG
-  *         @arg @ref LL_DMAMUX1_REQ_TIM8_COM
-  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH1
-  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH2
-  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH3
-  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH4
-  *         @arg @ref LL_DMAMUX1_REQ_TIM5_UP
-  *         @arg @ref LL_DMAMUX1_REQ_TIM5_TRIG
-  *         @arg @ref LL_DMAMUX1_REQ_SPI3_RX
-  *         @arg @ref LL_DMAMUX1_REQ_SPI3_TX
-  *         @arg @ref LL_DMAMUX1_REQ_UART4_RX
-  *         @arg @ref LL_DMAMUX1_REQ_UART4_TX
-  *         @arg @ref LL_DMAMUX1_REQ_UART5_RX
-  *         @arg @ref LL_DMAMUX1_REQ_UART5_TX
-  *         @arg @ref LL_DMAMUX1_REQ_DAC1_CH1
-  *         @arg @ref LL_DMAMUX1_REQ_DAC1_CH2
-  *         @arg @ref LL_DMAMUX1_REQ_TIM6_UP
-  *         @arg @ref LL_DMAMUX1_REQ_TIM7_UP
-  *         @arg @ref LL_DMAMUX1_REQ_USART6_RX
-  *         @arg @ref LL_DMAMUX1_REQ_USART6_TX
-  *         @arg @ref LL_DMAMUX1_REQ_I2C3_RX
-  *         @arg @ref LL_DMAMUX1_REQ_I2C3_TX
-  *         @arg @ref LL_DMAMUX1_REQ_DCMI_PSSI (*)
-  *         @arg @ref LL_DMAMUX1_REQ_CRYP_IN
-  *         @arg @ref LL_DMAMUX1_REQ_CRYP_OUT
-  *         @arg @ref LL_DMAMUX1_REQ_HASH_IN
-  *         @arg @ref LL_DMAMUX1_REQ_UART7_RX
-  *         @arg @ref LL_DMAMUX1_REQ_UART7_TX
-  *         @arg @ref LL_DMAMUX1_REQ_UART8_RX
-  *         @arg @ref LL_DMAMUX1_REQ_UART8_TX
-  *         @arg @ref LL_DMAMUX1_REQ_SPI4_RX
-  *         @arg @ref LL_DMAMUX1_REQ_SPI4_TX
-  *         @arg @ref LL_DMAMUX1_REQ_SPI5_RX
-  *         @arg @ref LL_DMAMUX1_REQ_SPI5_TX
-  *         @arg @ref LL_DMAMUX1_REQ_SAI1_A
-  *         @arg @ref LL_DMAMUX1_REQ_SAI1_B
-  *         @arg @ref LL_DMAMUX1_REQ_SAI2_A (*)
-  *         @arg @ref LL_DMAMUX1_REQ_SAI2_B (*)
-  *         @arg @ref LL_DMAMUX1_REQ_SWPMI_RX
-  *         @arg @ref LL_DMAMUX1_REQ_SWPMI_TX
-  *         @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_DT
-  *         @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_CS
-  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_MASTER (*)
-  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_A (*)
-  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_B (*)
-  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_C (*)
-  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_D (*)
-  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_E (*)
-  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT0
-  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT1
-  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT2
-  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT3
-  *         @arg @ref LL_DMAMUX1_REQ_TIM15_CH1
-  *         @arg @ref LL_DMAMUX1_REQ_TIM15_UP
-  *         @arg @ref LL_DMAMUX1_REQ_TIM15_TRIG
-  *         @arg @ref LL_DMAMUX1_REQ_TIM15_COM
-  *         @arg @ref LL_DMAMUX1_REQ_TIM16_CH1
-  *         @arg @ref LL_DMAMUX1_REQ_TIM16_UP
-  *         @arg @ref LL_DMAMUX1_REQ_TIM17_CH1
-  *         @arg @ref LL_DMAMUX1_REQ_TIM17_UP
-  *         @arg @ref LL_DMAMUX1_REQ_SAI3_A (*)
-  *         @arg @ref LL_DMAMUX1_REQ_SAI3_B (*)
-  *         @arg @ref LL_DMAMUX1_REQ_ADC3 (*)
-  *         @arg @ref LL_DMAMUX1_REQ_UART9_RX (*)
-  *         @arg @ref LL_DMAMUX1_REQ_UART9_TX (*)
-  *         @arg @ref LL_DMAMUX1_REQ_USART10_RX (*)
-  *         @arg @ref LL_DMAMUX1_REQ_USART10_TX (*)
-  *         @arg @ref LL_DMAMUX1_REQ_FMAC_READ  (*)
-  *         @arg @ref LL_DMAMUX1_REQ_FMAC_WRITE (*)
-  *         @arg @ref LL_DMAMUX1_REQ_CORDIC_READ (*)
-  *         @arg @ref LL_DMAMUX1_REQ_CORDIC_WRITE(*)
-  *         @arg @ref LL_DMAMUX1_REQ_I2C5_RX     (*)
-  *         @arg @ref LL_DMAMUX1_REQ_I2C5_TX     (*)
-  *         @arg @ref LL_DMAMUX1_REQ_TIM23_CH1   (*)
-  *         @arg @ref LL_DMAMUX1_REQ_TIM23_CH2   (*)
-  *         @arg @ref LL_DMAMUX1_REQ_TIM23_CH3   (*)
-  *         @arg @ref LL_DMAMUX1_REQ_TIM23_CH4   (*)
-  *         @arg @ref LL_DMAMUX1_REQ_TIM23_UP    (*)
-  *         @arg @ref LL_DMAMUX1_REQ_TIM23_TRIG  (*)
-  *         @arg @ref LL_DMAMUX1_REQ_TIM24_CH1   (*)
-  *         @arg @ref LL_DMAMUX1_REQ_TIM24_CH2   (*)
-  *         @arg @ref LL_DMAMUX1_REQ_TIM24_CH3   (*)
-  *         @arg @ref LL_DMAMUX1_REQ_TIM24_CH4   (*)
-  *         @arg @ref LL_DMAMUX1_REQ_TIM24_UP    (*)
-  *         @arg @ref LL_DMAMUX1_REQ_TIM24_TRIG  (*)
-  *         @arg @ref LL_DMAMUX2_REQ_MEM2MEM
-  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR0
-  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR1
-  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR2
-  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR3
-  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR4
-  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR5
-  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR6
-  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR7
-  *         @arg @ref LL_DMAMUX2_REQ_LPUART1_RX
-  *         @arg @ref LL_DMAMUX2_REQ_LPUART1_TX
-  *         @arg @ref LL_DMAMUX2_REQ_SPI6_RX
-  *         @arg @ref LL_DMAMUX2_REQ_SPI6_TX
-  *         @arg @ref LL_DMAMUX2_REQ_I2C4_RX
-  *         @arg @ref LL_DMAMUX2_REQ_I2C4_TX
-  *         @arg @ref LL_DMAMUX2_REQ_SAI4_A (*)
-  *         @arg @ref LL_DMAMUX2_REQ_SAI4_B (*)
-  *         @arg @ref LL_DMAMUX2_REQ_ADC3 (*)
-  *         @arg @ref LL_DMAMUX2_REQ_DAC2_CH1 (*)
-  *         @arg @ref LL_DMAMUX2_REQ_DFSDM2_FLT0 (*)
-  *
-  * @note   (*) Availability depends on devices.
-  * @retval None
-  */
-__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_DMAREQ_ID));
-}
-
-/**
-  * @brief  Set the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event.
-  * @rmtoll CxCR         NBREQ         LL_DMAMUX_SetSyncRequestNb
-  * @param  DMAMUXx DMAMUXx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMAMUX_CHANNEL_0
-  *         @arg @ref LL_DMAMUX_CHANNEL_1
-  *         @arg @ref LL_DMAMUX_CHANNEL_2
-  *         @arg @ref LL_DMAMUX_CHANNEL_3
-  *         @arg @ref LL_DMAMUX_CHANNEL_4
-  *         @arg @ref LL_DMAMUX_CHANNEL_5
-  *         @arg @ref LL_DMAMUX_CHANNEL_6
-  *         @arg @ref LL_DMAMUX_CHANNEL_7
-  *         @arg @ref LL_DMAMUX_CHANNEL_8
-  *         @arg @ref LL_DMAMUX_CHANNEL_9
-  *         @arg @ref LL_DMAMUX_CHANNEL_10
-  *         @arg @ref LL_DMAMUX_CHANNEL_11
-  *         @arg @ref LL_DMAMUX_CHANNEL_12
-  *         @arg @ref LL_DMAMUX_CHANNEL_13
-  *         @arg @ref LL_DMAMUX_CHANNEL_14
-  *         @arg @ref LL_DMAMUX_CHANNEL_15
-  * @param  RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32.
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t RequestNb)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  MODIFY_REG(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_NBREQ, (RequestNb - 1U) << DMAMUX_CxCR_NBREQ_Pos);
-}
-
-/**
-  * @brief  Get the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event.
-  * @rmtoll CxCR         NBREQ         LL_DMAMUX_GetSyncRequestNb
-  * @param  DMAMUXx DMAMUXx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMAMUX_CHANNEL_0
-  *         @arg @ref LL_DMAMUX_CHANNEL_1
-  *         @arg @ref LL_DMAMUX_CHANNEL_2
-  *         @arg @ref LL_DMAMUX_CHANNEL_3
-  *         @arg @ref LL_DMAMUX_CHANNEL_4
-  *         @arg @ref LL_DMAMUX_CHANNEL_5
-  *         @arg @ref LL_DMAMUX_CHANNEL_6
-  *         @arg @ref LL_DMAMUX_CHANNEL_7
-  *         @arg @ref LL_DMAMUX_CHANNEL_8
-  *         @arg @ref LL_DMAMUX_CHANNEL_9
-  *         @arg @ref LL_DMAMUX_CHANNEL_10
-  *         @arg @ref LL_DMAMUX_CHANNEL_11
-  *         @arg @ref LL_DMAMUX_CHANNEL_12
-  *         @arg @ref LL_DMAMUX_CHANNEL_13
-  *         @arg @ref LL_DMAMUX_CHANNEL_14
-  *         @arg @ref LL_DMAMUX_CHANNEL_15
-  * @retval Between Min_Data = 1 and Max_Data = 32
-  */
-__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  return (uint32_t)((READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_NBREQ) >> DMAMUX_CxCR_NBREQ_Pos) + 1U);
-}
-
-/**
-  * @brief  Set the polarity of the signal on which the DMA request is synchronized.
-  * @rmtoll CxCR         SPOL          LL_DMAMUX_SetSyncPolarity
-  * @param  DMAMUXx DMAMUXx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMAMUX_CHANNEL_0
-  *         @arg @ref LL_DMAMUX_CHANNEL_1
-  *         @arg @ref LL_DMAMUX_CHANNEL_2
-  *         @arg @ref LL_DMAMUX_CHANNEL_3
-  *         @arg @ref LL_DMAMUX_CHANNEL_4
-  *         @arg @ref LL_DMAMUX_CHANNEL_5
-  *         @arg @ref LL_DMAMUX_CHANNEL_6
-  *         @arg @ref LL_DMAMUX_CHANNEL_7
-  *         @arg @ref LL_DMAMUX_CHANNEL_8
-  *         @arg @ref LL_DMAMUX_CHANNEL_9
-  *         @arg @ref LL_DMAMUX_CHANNEL_10
-  *         @arg @ref LL_DMAMUX_CHANNEL_11
-  *         @arg @ref LL_DMAMUX_CHANNEL_12
-  *         @arg @ref LL_DMAMUX_CHANNEL_13
-  *         @arg @ref LL_DMAMUX_CHANNEL_14
-  *         @arg @ref LL_DMAMUX_CHANNEL_15
-  * @param  Polarity This parameter can be one of the following values:
-  *         @arg @ref LL_DMAMUX_SYNC_NO_EVENT
-  *         @arg @ref LL_DMAMUX_SYNC_POL_RISING
-  *         @arg @ref LL_DMAMUX_SYNC_POL_FALLING
-  *         @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Polarity)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  MODIFY_REG(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SPOL, Polarity);
-}
-
-/**
-  * @brief  Get the polarity of the signal on which the DMA request is synchronized.
-  * @rmtoll CxCR         SPOL          LL_DMAMUX_GetSyncPolarity
-  * @param  DMAMUXx DMAMUXx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMAMUX_CHANNEL_0
-  *         @arg @ref LL_DMAMUX_CHANNEL_1
-  *         @arg @ref LL_DMAMUX_CHANNEL_2
-  *         @arg @ref LL_DMAMUX_CHANNEL_3
-  *         @arg @ref LL_DMAMUX_CHANNEL_4
-  *         @arg @ref LL_DMAMUX_CHANNEL_5
-  *         @arg @ref LL_DMAMUX_CHANNEL_6
-  *         @arg @ref LL_DMAMUX_CHANNEL_7
-  *         @arg @ref LL_DMAMUX_CHANNEL_8
-  *         @arg @ref LL_DMAMUX_CHANNEL_9
-  *         @arg @ref LL_DMAMUX_CHANNEL_10
-  *         @arg @ref LL_DMAMUX_CHANNEL_11
-  *         @arg @ref LL_DMAMUX_CHANNEL_12
-  *         @arg @ref LL_DMAMUX_CHANNEL_13
-  *         @arg @ref LL_DMAMUX_CHANNEL_14
-  *         @arg @ref LL_DMAMUX_CHANNEL_15
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DMAMUX_SYNC_NO_EVENT
-  *         @arg @ref LL_DMAMUX_SYNC_POL_RISING
-  *         @arg @ref LL_DMAMUX_SYNC_POL_FALLING
-  *         @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING
-  */
-__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SPOL));
-}
-
-/**
-  * @brief  Enable the Event Generation on DMAMUX channel x.
-  * @rmtoll CxCR         EGE           LL_DMAMUX_EnableEventGeneration
-  * @param  DMAMUXx DMAMUXx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMAMUX_CHANNEL_0
-  *         @arg @ref LL_DMAMUX_CHANNEL_1
-  *         @arg @ref LL_DMAMUX_CHANNEL_2
-  *         @arg @ref LL_DMAMUX_CHANNEL_3
-  *         @arg @ref LL_DMAMUX_CHANNEL_4
-  *         @arg @ref LL_DMAMUX_CHANNEL_5
-  *         @arg @ref LL_DMAMUX_CHANNEL_6
-  *         @arg @ref LL_DMAMUX_CHANNEL_7
-  *         @arg @ref LL_DMAMUX_CHANNEL_8
-  *         @arg @ref LL_DMAMUX_CHANNEL_9
-  *         @arg @ref LL_DMAMUX_CHANNEL_10
-  *         @arg @ref LL_DMAMUX_CHANNEL_11
-  *         @arg @ref LL_DMAMUX_CHANNEL_12
-  *         @arg @ref LL_DMAMUX_CHANNEL_13
-  *         @arg @ref LL_DMAMUX_CHANNEL_14
-  *         @arg @ref LL_DMAMUX_CHANNEL_15
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  SET_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_EGE);
-}
-
-/**
-  * @brief  Disable the Event Generation on DMAMUX channel x.
-  * @rmtoll CxCR         EGE           LL_DMAMUX_DisableEventGeneration
-  * @param  DMAMUXx DMAMUXx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMAMUX_CHANNEL_0
-  *         @arg @ref LL_DMAMUX_CHANNEL_1
-  *         @arg @ref LL_DMAMUX_CHANNEL_2
-  *         @arg @ref LL_DMAMUX_CHANNEL_3
-  *         @arg @ref LL_DMAMUX_CHANNEL_4
-  *         @arg @ref LL_DMAMUX_CHANNEL_5
-  *         @arg @ref LL_DMAMUX_CHANNEL_6
-  *         @arg @ref LL_DMAMUX_CHANNEL_7
-  *         @arg @ref LL_DMAMUX_CHANNEL_8
-  *         @arg @ref LL_DMAMUX_CHANNEL_9
-  *         @arg @ref LL_DMAMUX_CHANNEL_10
-  *         @arg @ref LL_DMAMUX_CHANNEL_11
-  *         @arg @ref LL_DMAMUX_CHANNEL_12
-  *         @arg @ref LL_DMAMUX_CHANNEL_13
-  *         @arg @ref LL_DMAMUX_CHANNEL_14
-  *         @arg @ref LL_DMAMUX_CHANNEL_15
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  CLEAR_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_EGE);
-}
-
-/**
-  * @brief  Check if the Event Generation on DMAMUX channel x is enabled or disabled.
-  * @rmtoll CxCR         EGE           LL_DMAMUX_IsEnabledEventGeneration
-  * @param  DMAMUXx DMAMUXx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMAMUX_CHANNEL_0
-  *         @arg @ref LL_DMAMUX_CHANNEL_1
-  *         @arg @ref LL_DMAMUX_CHANNEL_2
-  *         @arg @ref LL_DMAMUX_CHANNEL_3
-  *         @arg @ref LL_DMAMUX_CHANNEL_4
-  *         @arg @ref LL_DMAMUX_CHANNEL_5
-  *         @arg @ref LL_DMAMUX_CHANNEL_6
-  *         @arg @ref LL_DMAMUX_CHANNEL_7
-  *         @arg @ref LL_DMAMUX_CHANNEL_8
-  *         @arg @ref LL_DMAMUX_CHANNEL_9
-  *         @arg @ref LL_DMAMUX_CHANNEL_10
-  *         @arg @ref LL_DMAMUX_CHANNEL_11
-  *         @arg @ref LL_DMAMUX_CHANNEL_12
-  *         @arg @ref LL_DMAMUX_CHANNEL_13
-  *         @arg @ref LL_DMAMUX_CHANNEL_14
-  *         @arg @ref LL_DMAMUX_CHANNEL_15
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  return ((READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_EGE) == (DMAMUX_CxCR_EGE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable the synchronization mode.
-  * @rmtoll CxCR         SE            LL_DMAMUX_EnableSync
-  * @param  DMAMUXx DMAMUXx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMAMUX_CHANNEL_0
-  *         @arg @ref LL_DMAMUX_CHANNEL_1
-  *         @arg @ref LL_DMAMUX_CHANNEL_2
-  *         @arg @ref LL_DMAMUX_CHANNEL_3
-  *         @arg @ref LL_DMAMUX_CHANNEL_4
-  *         @arg @ref LL_DMAMUX_CHANNEL_5
-  *         @arg @ref LL_DMAMUX_CHANNEL_6
-  *         @arg @ref LL_DMAMUX_CHANNEL_7
-  *         @arg @ref LL_DMAMUX_CHANNEL_8
-  *         @arg @ref LL_DMAMUX_CHANNEL_9
-  *         @arg @ref LL_DMAMUX_CHANNEL_10
-  *         @arg @ref LL_DMAMUX_CHANNEL_11
-  *         @arg @ref LL_DMAMUX_CHANNEL_12
-  *         @arg @ref LL_DMAMUX_CHANNEL_13
-  *         @arg @ref LL_DMAMUX_CHANNEL_14
-  *         @arg @ref LL_DMAMUX_CHANNEL_15
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMAMUX_EnableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  SET_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SE);
-}
-
-/**
-  * @brief  Disable the synchronization mode.
-  * @rmtoll CxCR         SE            LL_DMAMUX_DisableSync
-  * @param  DMAMUXx DMAMUXx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMAMUX_CHANNEL_0
-  *         @arg @ref LL_DMAMUX_CHANNEL_1
-  *         @arg @ref LL_DMAMUX_CHANNEL_2
-  *         @arg @ref LL_DMAMUX_CHANNEL_3
-  *         @arg @ref LL_DMAMUX_CHANNEL_4
-  *         @arg @ref LL_DMAMUX_CHANNEL_5
-  *         @arg @ref LL_DMAMUX_CHANNEL_6
-  *         @arg @ref LL_DMAMUX_CHANNEL_7
-  *         @arg @ref LL_DMAMUX_CHANNEL_8
-  *         @arg @ref LL_DMAMUX_CHANNEL_9
-  *         @arg @ref LL_DMAMUX_CHANNEL_10
-  *         @arg @ref LL_DMAMUX_CHANNEL_11
-  *         @arg @ref LL_DMAMUX_CHANNEL_12
-  *         @arg @ref LL_DMAMUX_CHANNEL_13
-  *         @arg @ref LL_DMAMUX_CHANNEL_14
-  *         @arg @ref LL_DMAMUX_CHANNEL_15
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMAMUX_DisableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  CLEAR_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SE);
-}
-
-/**
-  * @brief  Check if the synchronization mode is enabled or disabled.
-  * @rmtoll CxCR         SE            LL_DMAMUX_IsEnabledSync
-  * @param  DMAMUXx DMAMUXx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMAMUX_CHANNEL_0
-  *         @arg @ref LL_DMAMUX_CHANNEL_1
-  *         @arg @ref LL_DMAMUX_CHANNEL_2
-  *         @arg @ref LL_DMAMUX_CHANNEL_3
-  *         @arg @ref LL_DMAMUX_CHANNEL_4
-  *         @arg @ref LL_DMAMUX_CHANNEL_5
-  *         @arg @ref LL_DMAMUX_CHANNEL_6
-  *         @arg @ref LL_DMAMUX_CHANNEL_7
-  *         @arg @ref LL_DMAMUX_CHANNEL_8
-  *         @arg @ref LL_DMAMUX_CHANNEL_9
-  *         @arg @ref LL_DMAMUX_CHANNEL_10
-  *         @arg @ref LL_DMAMUX_CHANNEL_11
-  *         @arg @ref LL_DMAMUX_CHANNEL_12
-  *         @arg @ref LL_DMAMUX_CHANNEL_13
-  *         @arg @ref LL_DMAMUX_CHANNEL_14
-  *         @arg @ref LL_DMAMUX_CHANNEL_15
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  return ((READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SE) == (DMAMUX_CxCR_SE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Set DMAMUX synchronization ID  on DMAMUX Channel x.
-  * @rmtoll CxCR         SYNC_ID       LL_DMAMUX_SetSyncID
-  * @param  DMAMUXx DMAMUXx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMAMUX_CHANNEL_0
-  *         @arg @ref LL_DMAMUX_CHANNEL_1
-  *         @arg @ref LL_DMAMUX_CHANNEL_2
-  *         @arg @ref LL_DMAMUX_CHANNEL_3
-  *         @arg @ref LL_DMAMUX_CHANNEL_4
-  *         @arg @ref LL_DMAMUX_CHANNEL_5
-  *         @arg @ref LL_DMAMUX_CHANNEL_6
-  *         @arg @ref LL_DMAMUX_CHANNEL_7
-  *         @arg @ref LL_DMAMUX_CHANNEL_8
-  *         @arg @ref LL_DMAMUX_CHANNEL_9
-  *         @arg @ref LL_DMAMUX_CHANNEL_10
-  *         @arg @ref LL_DMAMUX_CHANNEL_11
-  *         @arg @ref LL_DMAMUX_CHANNEL_12
-  *         @arg @ref LL_DMAMUX_CHANNEL_13
-  *         @arg @ref LL_DMAMUX_CHANNEL_14
-  *         @arg @ref LL_DMAMUX_CHANNEL_15
-  * @param  SyncID This parameter can be one of the following values:
-  *         @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT
-  *         @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT
-  *         @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT
-  *         @arg @ref LL_DMAMUX1_SYNC_LPTIM1_OUT
-  *         @arg @ref LL_DMAMUX1_SYNC_LPTIM2_OUT
-  *         @arg @ref LL_DMAMUX1_SYNC_LPTIM3_OUT
-  *         @arg @ref LL_DMAMUX1_SYNC_EXTI0
-  *         @arg @ref LL_DMAMUX1_SYNC_TIM12_TRGO
-  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT
-  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT
-  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT
-  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT
-  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT
-  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT
-  *         @arg @ref LL_DMAMUX2_SYNC_LPUART1_RX_WKUP
-  *         @arg @ref LL_DMAMUX2_SYNC_LPUART1_TX_WKUP
-  *         @arg @ref LL_DMAMUX2_SYNC_LPTIM2_OUT
-  *         @arg @ref LL_DMAMUX2_SYNC_LPTIM3_OUT
-  *         @arg @ref LL_DMAMUX2_SYNC_I2C4_WKUP
-  *         @arg @ref LL_DMAMUX2_SYNC_SPI6_WKUP
-  *         @arg @ref LL_DMAMUX2_SYNC_COMP1_OUT
-  *         @arg @ref LL_DMAMUX2_SYNC_RTC_WKUP
-  *         @arg @ref LL_DMAMUX2_SYNC_EXTI0
-  *         @arg @ref LL_DMAMUX2_SYNC_EXTI2
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMAMUX_SetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t SyncID)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  MODIFY_REG(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SYNC_ID, SyncID);
-}
-
-/**
-  * @brief  Get DMAMUX synchronization ID  on DMAMUX Channel x.
-  * @rmtoll CxCR         SYNC_ID       LL_DMAMUX_GetSyncID
-  * @param  DMAMUXx DMAMUXx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMAMUX_CHANNEL_0
-  *         @arg @ref LL_DMAMUX_CHANNEL_1
-  *         @arg @ref LL_DMAMUX_CHANNEL_2
-  *         @arg @ref LL_DMAMUX_CHANNEL_3
-  *         @arg @ref LL_DMAMUX_CHANNEL_4
-  *         @arg @ref LL_DMAMUX_CHANNEL_5
-  *         @arg @ref LL_DMAMUX_CHANNEL_6
-  *         @arg @ref LL_DMAMUX_CHANNEL_7
-  *         @arg @ref LL_DMAMUX_CHANNEL_8
-  *         @arg @ref LL_DMAMUX_CHANNEL_9
-  *         @arg @ref LL_DMAMUX_CHANNEL_10
-  *         @arg @ref LL_DMAMUX_CHANNEL_11
-  *         @arg @ref LL_DMAMUX_CHANNEL_12
-  *         @arg @ref LL_DMAMUX_CHANNEL_13
-  *         @arg @ref LL_DMAMUX_CHANNEL_14
-  *         @arg @ref LL_DMAMUX_CHANNEL_15
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT
-  *         @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT
-  *         @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT
-  *         @arg @ref LL_DMAMUX1_SYNC_LPTIM1_OUT
-  *         @arg @ref LL_DMAMUX1_SYNC_LPTIM2_OUT
-  *         @arg @ref LL_DMAMUX1_SYNC_LPTIM3_OUT
-  *         @arg @ref LL_DMAMUX1_SYNC_EXTI0
-  *         @arg @ref LL_DMAMUX1_SYNC_TIM12_TRGO
-  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT
-  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT
-  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT
-  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT
-  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT
-  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT
-  *         @arg @ref LL_DMAMUX2_SYNC_LPUART1_RX_WKUP
-  *         @arg @ref LL_DMAMUX2_SYNC_LPUART1_TX_WKUP
-  *         @arg @ref LL_DMAMUX2_SYNC_LPTIM2_OUT
-  *         @arg @ref LL_DMAMUX2_SYNC_LPTIM3_OUT
-  *         @arg @ref LL_DMAMUX2_SYNC_I2C4_WKUP
-  *         @arg @ref LL_DMAMUX2_SYNC_SPI6_WKUP
-  *         @arg @ref LL_DMAMUX2_SYNC_COMP1_OUT
-  *         @arg @ref LL_DMAMUX2_SYNC_RTC_WKUP
-  *         @arg @ref LL_DMAMUX2_SYNC_EXTI0
-  *         @arg @ref LL_DMAMUX2_SYNC_EXTI2
-  */
-__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SYNC_ID));
-}
-
-/**
-  * @brief  Enable the Request Generator.
-  * @rmtoll RGxCR        GE            LL_DMAMUX_EnableRequestGen
-  * @param  DMAMUXx DMAMUXx Instance
-  * @param  RequestGenChannel This parameter can be one of the following values:
-  *         @arg @ref LL_DMAMUX_REQ_GEN_0
-  *         @arg @ref LL_DMAMUX_REQ_GEN_1
-  *         @arg @ref LL_DMAMUX_REQ_GEN_2
-  *         @arg @ref LL_DMAMUX_REQ_GEN_3
-  *         @arg @ref LL_DMAMUX_REQ_GEN_4
-  *         @arg @ref LL_DMAMUX_REQ_GEN_5
-  *         @arg @ref LL_DMAMUX_REQ_GEN_6
-  *         @arg @ref LL_DMAMUX_REQ_GEN_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMAMUX_EnableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  SET_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * (RequestGenChannel))))->RGCR, DMAMUX_RGxCR_GE);
-}
-
-/**
-  * @brief  Disable the Request Generator.
-  * @rmtoll RGxCR        GE            LL_DMAMUX_DisableRequestGen
-  * @param  DMAMUXx DMAMUXx Instance
-  * @param  RequestGenChannel This parameter can be one of the following values:
-  *         @arg @ref LL_DMAMUX_REQ_GEN_0
-  *         @arg @ref LL_DMAMUX_REQ_GEN_1
-  *         @arg @ref LL_DMAMUX_REQ_GEN_2
-  *         @arg @ref LL_DMAMUX_REQ_GEN_3
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMAMUX_DisableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  CLEAR_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * (RequestGenChannel))))->RGCR, DMAMUX_RGxCR_GE);
-}
-
-/**
-  * @brief  Check if the Request Generator is enabled or disabled.
-  * @rmtoll RGxCR        GE            LL_DMAMUX_IsEnabledRequestGen
-  * @param  DMAMUXx DMAMUXx Instance
-  * @param  RequestGenChannel This parameter can be one of the following values:
-  *         @arg @ref LL_DMAMUX_REQ_GEN_0
-  *         @arg @ref LL_DMAMUX_REQ_GEN_1
-  *         @arg @ref LL_DMAMUX_REQ_GEN_2
-  *         @arg @ref LL_DMAMUX_REQ_GEN_3
-  *         @arg @ref LL_DMAMUX_REQ_GEN_4
-  *         @arg @ref LL_DMAMUX_REQ_GEN_5
-  *         @arg @ref LL_DMAMUX_REQ_GEN_6
-  *         @arg @ref LL_DMAMUX_REQ_GEN_7
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GE) == (DMAMUX_RGxCR_GE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Set the polarity of the signal on which the DMA request is generated.
-  * @rmtoll RGxCR        GPOL          LL_DMAMUX_SetRequestGenPolarity
-  * @param  DMAMUXx DMAMUXx Instance
-  * @param  RequestGenChannel This parameter can be one of the following values:
-  *         @arg @ref LL_DMAMUX_REQ_GEN_0
-  *         @arg @ref LL_DMAMUX_REQ_GEN_1
-  *         @arg @ref LL_DMAMUX_REQ_GEN_2
-  *         @arg @ref LL_DMAMUX_REQ_GEN_3
-  *         @arg @ref LL_DMAMUX_REQ_GEN_4
-  *         @arg @ref LL_DMAMUX_REQ_GEN_5
-  *         @arg @ref LL_DMAMUX_REQ_GEN_6
-  *         @arg @ref LL_DMAMUX_REQ_GEN_7
-  * @param  Polarity This parameter can be one of the following values:
-  *         @arg @ref LL_DMAMUX_REQ_GEN_NO_EVENT
-  *         @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING
-  *         @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING
-  *         @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t Polarity)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GPOL, Polarity);
-}
-
-/**
-  * @brief  Get the polarity of the signal on which the DMA request is generated.
-  * @rmtoll RGxCR        GPOL          LL_DMAMUX_GetRequestGenPolarity
-  * @param  DMAMUXx DMAMUXx Instance
-  * @param  RequestGenChannel This parameter can be one of the following values:
-  *         @arg @ref LL_DMAMUX_REQ_GEN_0
-  *         @arg @ref LL_DMAMUX_REQ_GEN_1
-  *         @arg @ref LL_DMAMUX_REQ_GEN_2
-  *         @arg @ref LL_DMAMUX_REQ_GEN_3
-  *         @arg @ref LL_DMAMUX_REQ_GEN_4
-  *         @arg @ref LL_DMAMUX_REQ_GEN_5
-  *         @arg @ref LL_DMAMUX_REQ_GEN_6
-  *         @arg @ref LL_DMAMUX_REQ_GEN_7
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DMAMUX_REQ_GEN_NO_EVENT
-  *         @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING
-  *         @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING
-  *         @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING
-  */
-__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GPOL));
-}
-
-/**
-  * @brief  Set the number of DMA request that will be autorized after a generation event.
-  * @note   This field can only be written when Generator is disabled.
-  * @rmtoll RGxCR        GNBREQ        LL_DMAMUX_SetGenRequestNb
-  * @param  DMAMUXx DMAMUXx Instance
-  * @param  RequestGenChannel This parameter can be one of the following values:
-  *         @arg @ref LL_DMAMUX_REQ_GEN_0
-  *         @arg @ref LL_DMAMUX_REQ_GEN_1
-  *         @arg @ref LL_DMAMUX_REQ_GEN_2
-  *         @arg @ref LL_DMAMUX_REQ_GEN_3
-  *         @arg @ref LL_DMAMUX_REQ_GEN_4
-  *         @arg @ref LL_DMAMUX_REQ_GEN_5
-  *         @arg @ref LL_DMAMUX_REQ_GEN_6
-  *         @arg @ref LL_DMAMUX_REQ_GEN_7
-  * @param  RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32.
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMAMUX_SetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestNb)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GNBREQ, (RequestNb - 1U) << DMAMUX_RGxCR_GNBREQ_Pos);
-}
-
-/**
-  * @brief  Get the number of DMA request that will be autorized after a generation event.
-  * @rmtoll RGxCR        GNBREQ        LL_DMAMUX_GetGenRequestNb
-  * @param  DMAMUXx DMAMUXx Instance
-  * @param  RequestGenChannel This parameter can be one of the following values:
-  *         @arg @ref LL_DMAMUX_REQ_GEN_0
-  *         @arg @ref LL_DMAMUX_REQ_GEN_1
-  *         @arg @ref LL_DMAMUX_REQ_GEN_2
-  *         @arg @ref LL_DMAMUX_REQ_GEN_3
-  *         @arg @ref LL_DMAMUX_REQ_GEN_4
-  *         @arg @ref LL_DMAMUX_REQ_GEN_5
-  *         @arg @ref LL_DMAMUX_REQ_GEN_6
-  *         @arg @ref LL_DMAMUX_REQ_GEN_7
-  * @retval Between Min_Data = 1 and Max_Data = 32
-  */
-__STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  return (uint32_t)((READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GNBREQ) >> DMAMUX_RGxCR_GNBREQ_Pos) + 1U);
-}
-
-/**
-  * @brief  Set DMAMUX external Request Signal ID on DMAMUX Request Generation Trigger Event Channel x.
-  * @rmtoll RGxCR        SIG_ID        LL_DMAMUX_SetRequestSignalID
-  * @param  DMAMUXx DMAMUXx Instance
-  * @param  RequestGenChannel This parameter can be one of the following values:
-  *         @arg @ref LL_DMAMUX_REQ_GEN_0
-  *         @arg @ref LL_DMAMUX_REQ_GEN_1
-  *         @arg @ref LL_DMAMUX_REQ_GEN_2
-  *         @arg @ref LL_DMAMUX_REQ_GEN_3
-  *         @arg @ref LL_DMAMUX_REQ_GEN_4
-  *         @arg @ref LL_DMAMUX_REQ_GEN_5
-  *         @arg @ref LL_DMAMUX_REQ_GEN_6
-  *         @arg @ref LL_DMAMUX_REQ_GEN_7
-  * @param  RequestSignalID This parameter can be one of the following values:
-  *         @arg @ref LL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
-  *         @arg @ref LL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
-  *         @arg @ref LL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
-  *         @arg @ref LL_DMAMUX1_REQ_GEN_LPTIM1_OUT
-  *         @arg @ref LL_DMAMUX1_REQ_GEN_LPTIM2_OUT
-  *         @arg @ref LL_DMAMUX1_REQ_GEN_LPTIM3_OUT
-  *         @arg @ref LL_DMAMUX1_REQ_GEN_EXTI0
-  *         @arg @ref LL_DMAMUX1_REQ_GEN_TIM12_TRGO
-  *         @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT
-  *         @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT
-  *         @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT
-  *         @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT
-  *         @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT
-  *         @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT
-  *         @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT
-  *         @arg @ref LL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP
-  *         @arg @ref LL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP
-  *         @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM2_WKUP
-  *         @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM2_OUT
-  *         @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM3_WKUP
-  *         @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM3_OUT
-  *         @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM4_WKUP (*)
-  *         @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM5_WKUP (*)
-  *         @arg @ref LL_DMAMUX2_REQ_GEN_I2C4_WKUP
-  *         @arg @ref LL_DMAMUX2_REQ_GEN_SPI6_WKUP
-  *         @arg @ref LL_DMAMUX2_REQ_GEN_COMP1_OUT
-  *         @arg @ref LL_DMAMUX2_REQ_GEN_COMP2_OUT
-  *         @arg @ref LL_DMAMUX2_REQ_GEN_RTC_WKUP
-  *         @arg @ref LL_DMAMUX2_REQ_GEN_EXTI0
-  *         @arg @ref LL_DMAMUX2_REQ_GEN_EXTI2
-  *         @arg @ref LL_DMAMUX2_REQ_GEN_I2C4_IT_EVT
-  *         @arg @ref LL_DMAMUX2_REQ_GEN_SPI6_IT
-  *         @arg @ref LL_DMAMUX2_REQ_GEN_LPUART1_TX_IT
-  *         @arg @ref LL_DMAMUX2_REQ_GEN_LPUART1_RX_IT
-  *         @arg @ref LL_DMAMUX2_REQ_GEN_ADC3_IT (*)
-  *         @arg @ref LL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT (*)
-  *         @arg @ref LL_DMAMUX2_REQ_GEN_BDMA_CH0_IT
-  *         @arg @ref LL_DMAMUX2_REQ_GEN_BDMA_CH1_IT
-  * @note   (*) Availability depends on devices.
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMAMUX_SetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestSignalID)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_SIG_ID, RequestSignalID);
-}
-
-/**
-  * @brief  Get DMAMUX external Request Signal ID set on DMAMUX Channel x.
-  * @rmtoll RGxCR        SIG_ID        LL_DMAMUX_GetRequestSignalID
-  * @param  DMAMUXx DMAMUXx Instance
-  * @param  RequestGenChannel This parameter can be one of the following values:
-  *         @arg @ref LL_DMAMUX_REQ_GEN_0
-  *         @arg @ref LL_DMAMUX_REQ_GEN_1
-  *         @arg @ref LL_DMAMUX_REQ_GEN_2
-  *         @arg @ref LL_DMAMUX_REQ_GEN_3
-  *         @arg @ref LL_DMAMUX_REQ_GEN_4
-  *         @arg @ref LL_DMAMUX_REQ_GEN_5
-  *         @arg @ref LL_DMAMUX_REQ_GEN_6
-  *         @arg @ref LL_DMAMUX_REQ_GEN_7
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT
-  *         @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT
-  *         @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT
-  *         @arg @ref LL_DMAMUX1_SYNC_LPTIM1_OUT
-  *         @arg @ref LL_DMAMUX1_SYNC_LPTIM2_OUT
-  *         @arg @ref LL_DMAMUX1_SYNC_LPTIM3_OUT
-  *         @arg @ref LL_DMAMUX1_SYNC_EXTI0
-  *         @arg @ref LL_DMAMUX1_SYNC_TIM12_TRGO
-  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT
-  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT
-  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT
-  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT
-  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT
-  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT
-  *         @arg @ref LL_DMAMUX2_SYNC_LPUART1_RX_WKUP
-  *         @arg @ref LL_DMAMUX2_SYNC_LPUART1_TX_WKUP
-  *         @arg @ref LL_DMAMUX2_SYNC_LPTIM2_OUT
-  *         @arg @ref LL_DMAMUX2_SYNC_LPTIM3_OUT
-  *         @arg @ref LL_DMAMUX2_SYNC_I2C4_WKUP
-  *         @arg @ref LL_DMAMUX2_SYNC_SPI6_WKUP
-  *         @arg @ref LL_DMAMUX2_SYNC_COMP1_OUT
-  *         @arg @ref LL_DMAMUX2_SYNC_RTC_WKUP
-  *         @arg @ref LL_DMAMUX2_SYNC_EXTI0
-  *         @arg @ref LL_DMAMUX2_SYNC_EXTI2
-  */
-__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_SIG_ID));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup DMAMUX_LL_EF_FLAG_Management FLAG_Management
-  * @{
-  */
-
-/**
-  * @brief  Get Synchronization Event Overrun Flag Channel 0.
-  * @rmtoll CSR          SOF0          LL_DMAMUX_IsActiveFlag_SO0
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF0) == (DMAMUX_CSR_SOF0)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Synchronization Event Overrun Flag Channel 1.
-  * @rmtoll CSR          SOF1          LL_DMAMUX_IsActiveFlag_SO1
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF1) == (DMAMUX_CSR_SOF1)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Synchronization Event Overrun Flag Channel 2.
-  * @rmtoll CSR          SOF2          LL_DMAMUX_IsActiveFlag_SO2
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF2) == (DMAMUX_CSR_SOF2)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Synchronization Event Overrun Flag Channel 3.
-  * @rmtoll CSR          SOF3          LL_DMAMUX_IsActiveFlag_SO3
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF3) == (DMAMUX_CSR_SOF3)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Synchronization Event Overrun Flag Channel 4.
-  * @rmtoll CSR          SOF4          LL_DMAMUX_IsActiveFlag_SO4
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF4) == (DMAMUX_CSR_SOF4)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Synchronization Event Overrun Flag Channel 5.
-  * @rmtoll CSR          SOF5          LL_DMAMUX_IsActiveFlag_SO5
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF5) == (DMAMUX_CSR_SOF5)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Synchronization Event Overrun Flag Channel 6.
-  * @rmtoll CSR          SOF6          LL_DMAMUX_IsActiveFlag_SO6
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF6) == (DMAMUX_CSR_SOF6)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Synchronization Event Overrun Flag Channel 7.
-  * @rmtoll CSR          SOF7          LL_DMAMUX_IsActiveFlag_SO7
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF7) == (DMAMUX_CSR_SOF7)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Synchronization Event Overrun Flag Channel 8.
-  * @rmtoll CSR          SOF8          LL_DMAMUX_IsActiveFlag_SO8
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF8) == (DMAMUX_CSR_SOF8)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Synchronization Event Overrun Flag Channel 9.
-  * @rmtoll CSR          SOF9          LL_DMAMUX_IsActiveFlag_SO9
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF9) == (DMAMUX_CSR_SOF9)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Synchronization Event Overrun Flag Channel 10.
-  * @rmtoll CSR          SOF10         LL_DMAMUX_IsActiveFlag_SO10
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF10) == (DMAMUX_CSR_SOF10)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Synchronization Event Overrun Flag Channel 11.
-  * @rmtoll CSR          SOF11         LL_DMAMUX_IsActiveFlag_SO11
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF11) == (DMAMUX_CSR_SOF11)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Synchronization Event Overrun Flag Channel 12.
-  * @rmtoll CSR          SOF12         LL_DMAMUX_IsActiveFlag_SO12
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF12) == (DMAMUX_CSR_SOF12)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Synchronization Event Overrun Flag Channel 13.
-  * @rmtoll CSR          SOF13         LL_DMAMUX_IsActiveFlag_SO13
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF13) == (DMAMUX_CSR_SOF13)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Synchronization Event Overrun Flag Channel 14.
-  * @rmtoll CSR          SOF14         LL_DMAMUX_IsActiveFlag_SO14
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO14(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF14) == (DMAMUX_CSR_SOF14)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Synchronization Event Overrun Flag Channel 15.
-  * @rmtoll CSR          SOF15         LL_DMAMUX_IsActiveFlag_SO15
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO15(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF15) == (DMAMUX_CSR_SOF15)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Request Generator 0 Trigger Event Overrun Flag.
-  * @rmtoll RGSR         OF0           LL_DMAMUX_IsActiveFlag_RGO0
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF0) == (DMAMUX_RGSR_OF0)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Request Generator 1 Trigger Event Overrun Flag.
-  * @rmtoll RGSR         OF1           LL_DMAMUX_IsActiveFlag_RGO1
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF1) == (DMAMUX_RGSR_OF1)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Request Generator 2 Trigger Event Overrun Flag.
-  * @rmtoll RGSR         OF2           LL_DMAMUX_IsActiveFlag_RGO2
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF2) == (DMAMUX_RGSR_OF2)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Request Generator 3 Trigger Event Overrun Flag.
-  * @rmtoll RGSR         OF3           LL_DMAMUX_IsActiveFlag_RGO3
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF3) == (DMAMUX_RGSR_OF3)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Request Generator 4 Trigger Event Overrun Flag.
-  * @rmtoll RGSR         OF4           LL_DMAMUX_IsActiveFlag_RGO4
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO4(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF4) == (DMAMUX_RGSR_OF4)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Request Generator 5 Trigger Event Overrun Flag.
-  * @rmtoll RGSR         OF5           LL_DMAMUX_IsActiveFlag_RGO5
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO5(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF5) == (DMAMUX_RGSR_OF5)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Request Generator 6 Trigger Event Overrun Flag.
-  * @rmtoll RGSR         OF6           LL_DMAMUX_IsActiveFlag_RGO6
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO6(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF6) == (DMAMUX_RGSR_OF6)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Request Generator 7 Trigger Event Overrun Flag.
-  * @rmtoll RGSR         OF7           LL_DMAMUX_IsActiveFlag_RGO7
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO7(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF7) == (DMAMUX_RGSR_OF7)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear Synchronization Event Overrun Flag Channel 0.
-  * @rmtoll CFR          CSOF0         LL_DMAMUX_ClearFlag_SO0
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF0);
-}
-
-/**
-  * @brief  Clear Synchronization Event Overrun Flag Channel 1.
-  * @rmtoll CFR          CSOF1         LL_DMAMUX_ClearFlag_SO1
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF1);
-}
-
-/**
-  * @brief  Clear Synchronization Event Overrun Flag Channel 2.
-  * @rmtoll CFR          CSOF2         LL_DMAMUX_ClearFlag_SO2
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF2);
-}
-
-/**
-  * @brief  Clear Synchronization Event Overrun Flag Channel 3.
-  * @rmtoll CFR          CSOF3         LL_DMAMUX_ClearFlag_SO3
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF3);
-}
-
-/**
-  * @brief  Clear Synchronization Event Overrun Flag Channel 4.
-  * @rmtoll CFR          CSOF4         LL_DMAMUX_ClearFlag_SO4
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF4);
-}
-
-/**
-  * @brief  Clear Synchronization Event Overrun Flag Channel 5.
-  * @rmtoll CFR          CSOF5         LL_DMAMUX_ClearFlag_SO5
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF5);
-}
-
-/**
-  * @brief  Clear Synchronization Event Overrun Flag Channel 6.
-  * @rmtoll CFR          CSOF6         LL_DMAMUX_ClearFlag_SO6
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF6);
-}
-
-/**
-  * @brief  Clear Synchronization Event Overrun Flag Channel 7.
-  * @rmtoll CFR          CSOF7         LL_DMAMUX_ClearFlag_SO7
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF7);
-}
-
-/**
-  * @brief  Clear Synchronization Event Overrun Flag Channel 8.
-  * @rmtoll CFR          CSOF8         LL_DMAMUX_ClearFlag_SO8
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF8);
-}
-
-/**
-  * @brief  Clear Synchronization Event Overrun Flag Channel 9.
-  * @rmtoll CFR          CSOF9         LL_DMAMUX_ClearFlag_SO9
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF9);
-}
-
-/**
-  * @brief  Clear Synchronization Event Overrun Flag Channel 10.
-  * @rmtoll CFR          CSOF10        LL_DMAMUX_ClearFlag_SO10
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF10);
-}
-
-/**
-  * @brief  Clear Synchronization Event Overrun Flag Channel 11.
-  * @rmtoll CFR          CSOF11        LL_DMAMUX_ClearFlag_SO11
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF11);
-}
-
-/**
-  * @brief  Clear Synchronization Event Overrun Flag Channel 12.
-  * @rmtoll CFR          CSOF12        LL_DMAMUX_ClearFlag_SO12
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF12);
-}
-
-/**
-  * @brief  Clear Synchronization Event Overrun Flag Channel 13.
-  * @rmtoll CFR          CSOF13        LL_DMAMUX_ClearFlag_SO13
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF13);
-}
-
-/**
-  * @brief  Clear Synchronization Event Overrun Flag Channel 14.
-  * @rmtoll CFR          CSOF14        LL_DMAMUX_ClearFlag_SO14
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO14(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF14);
-}
-
-/**
-  * @brief  Clear Synchronization Event Overrun Flag Channel 15.
-  * @rmtoll CFR          CSOF15        LL_DMAMUX_ClearFlag_SO15
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO15(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF15);
-}
-
-/**
-  * @brief  Clear Request Generator 0 Trigger Event Overrun Flag.
-  * @rmtoll RGCFR        COF0          LL_DMAMUX_ClearFlag_RGO0
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF0);
-}
-
-/**
-  * @brief  Clear Request Generator 1 Trigger Event Overrun Flag.
-  * @rmtoll RGCFR        COF1          LL_DMAMUX_ClearFlag_RGO1
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF1);
-}
-
-/**
-  * @brief  Clear Request Generator 2 Trigger Event Overrun Flag.
-  * @rmtoll RGCFR        COF2          LL_DMAMUX_ClearFlag_RGO2
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF2);
-}
-
-/**
-  * @brief  Clear Request Generator 3 Trigger Event Overrun Flag.
-  * @rmtoll RGCFR        COF3          LL_DMAMUX_ClearFlag_RGO3
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF3);
-}
-
-/**
-  * @brief  Clear Request Generator 4 Trigger Event Overrun Flag.
-  * @rmtoll RGCFR        COF4          LL_DMAMUX_ClearFlag_RGO4
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO4(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF4);
-}
-
-/**
-  * @brief  Clear Request Generator 5 Trigger Event Overrun Flag.
-  * @rmtoll RGCFR        COF5          LL_DMAMUX_ClearFlag_RGO5
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO5(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF5);
-}
-
-/**
-  * @brief  Clear Request Generator 6 Trigger Event Overrun Flag.
-  * @rmtoll RGCFR        COF6          LL_DMAMUX_ClearFlag_RGO6
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO6(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF6);
-}
-
-/**
-  * @brief  Clear Request Generator 7 Trigger Event Overrun Flag.
-  * @rmtoll RGCFR        COF7          LL_DMAMUX_ClearFlag_RGO7
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO7(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF7);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup DMAMUX_LL_EF_IT_Management IT_Management
-  * @{
-  */
-
-/**
-  * @brief  Enable the Synchronization Event Overrun Interrupt on DMAMUX channel x.
-  * @rmtoll CxCR         SOIE          LL_DMAMUX_EnableIT_SO
-  * @param  DMAMUXx DMAMUXx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMAMUX_CHANNEL_0
-  *         @arg @ref LL_DMAMUX_CHANNEL_1
-  *         @arg @ref LL_DMAMUX_CHANNEL_2
-  *         @arg @ref LL_DMAMUX_CHANNEL_3
-  *         @arg @ref LL_DMAMUX_CHANNEL_4
-  *         @arg @ref LL_DMAMUX_CHANNEL_5
-  *         @arg @ref LL_DMAMUX_CHANNEL_6
-  *         @arg @ref LL_DMAMUX_CHANNEL_7
-  *         @arg @ref LL_DMAMUX_CHANNEL_8
-  *         @arg @ref LL_DMAMUX_CHANNEL_9
-  *         @arg @ref LL_DMAMUX_CHANNEL_10
-  *         @arg @ref LL_DMAMUX_CHANNEL_11
-  *         @arg @ref LL_DMAMUX_CHANNEL_12
-  *         @arg @ref LL_DMAMUX_CHANNEL_13
-  *         @arg @ref LL_DMAMUX_CHANNEL_14
-  *         @arg @ref LL_DMAMUX_CHANNEL_15
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMAMUX_EnableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  SET_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_SOIE);
-}
-
-/**
-  * @brief  Disable the Synchronization Event Overrun Interrupt on DMAMUX channel x.
-  * @rmtoll CxCR         SOIE          LL_DMAMUX_DisableIT_SO
-  * @param  DMAMUXx DMAMUXx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMAMUX_CHANNEL_0
-  *         @arg @ref LL_DMAMUX_CHANNEL_1
-  *         @arg @ref LL_DMAMUX_CHANNEL_2
-  *         @arg @ref LL_DMAMUX_CHANNEL_3
-  *         @arg @ref LL_DMAMUX_CHANNEL_4
-  *         @arg @ref LL_DMAMUX_CHANNEL_5
-  *         @arg @ref LL_DMAMUX_CHANNEL_6
-  *         @arg @ref LL_DMAMUX_CHANNEL_7
-  *         @arg @ref LL_DMAMUX_CHANNEL_8
-  *         @arg @ref LL_DMAMUX_CHANNEL_9
-  *         @arg @ref LL_DMAMUX_CHANNEL_10
-  *         @arg @ref LL_DMAMUX_CHANNEL_11
-  *         @arg @ref LL_DMAMUX_CHANNEL_12
-  *         @arg @ref LL_DMAMUX_CHANNEL_13
-  *         @arg @ref LL_DMAMUX_CHANNEL_14
-  *         @arg @ref LL_DMAMUX_CHANNEL_15
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMAMUX_DisableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  CLEAR_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_SOIE);
-}
-
-/**
-  * @brief  Check if the Synchronization Event Overrun Interrupt on DMAMUX channel x is enabled or disabled.
-  * @rmtoll CxCR         SOIE          LL_DMAMUX_IsEnabledIT_SO
-  * @param  DMAMUXx DMAMUXx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMAMUX_CHANNEL_0
-  *         @arg @ref LL_DMAMUX_CHANNEL_1
-  *         @arg @ref LL_DMAMUX_CHANNEL_2
-  *         @arg @ref LL_DMAMUX_CHANNEL_3
-  *         @arg @ref LL_DMAMUX_CHANNEL_4
-  *         @arg @ref LL_DMAMUX_CHANNEL_5
-  *         @arg @ref LL_DMAMUX_CHANNEL_6
-  *         @arg @ref LL_DMAMUX_CHANNEL_7
-  *         @arg @ref LL_DMAMUX_CHANNEL_8
-  *         @arg @ref LL_DMAMUX_CHANNEL_9
-  *         @arg @ref LL_DMAMUX_CHANNEL_10
-  *         @arg @ref LL_DMAMUX_CHANNEL_11
-  *         @arg @ref LL_DMAMUX_CHANNEL_12
-  *         @arg @ref LL_DMAMUX_CHANNEL_13
-  *         @arg @ref LL_DMAMUX_CHANNEL_14
-  *         @arg @ref LL_DMAMUX_CHANNEL_15
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  return (READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SOIE));
-}
-
-/**
-  * @brief  Enable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x.
-  * @rmtoll RGxCR        OIE           LL_DMAMUX_EnableIT_RGO
-  * @param  DMAMUXx DMAMUXx Instance
-  * @param  RequestGenChannel This parameter can be one of the following values:
-  *         @arg @ref LL_DMAMUX_REQ_GEN_0
-  *         @arg @ref LL_DMAMUX_REQ_GEN_1
-  *         @arg @ref LL_DMAMUX_REQ_GEN_2
-  *         @arg @ref LL_DMAMUX_REQ_GEN_3
-  *         @arg @ref LL_DMAMUX_REQ_GEN_4
-  *         @arg @ref LL_DMAMUX_REQ_GEN_5
-  *         @arg @ref LL_DMAMUX_REQ_GEN_6
-  *         @arg @ref LL_DMAMUX_REQ_GEN_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMAMUX_EnableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  SET_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_OIE);
-}
-
-/**
-  * @brief  Disable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x.
-  * @rmtoll RGxCR        OIE           LL_DMAMUX_DisableIT_RGO
-  * @param  DMAMUXx DMAMUXx Instance
-  * @param  RequestGenChannel This parameter can be one of the following values:
-  *         @arg @ref LL_DMAMUX_REQ_GEN_0
-  *         @arg @ref LL_DMAMUX_REQ_GEN_1
-  *         @arg @ref LL_DMAMUX_REQ_GEN_2
-  *         @arg @ref LL_DMAMUX_REQ_GEN_3
-  *         @arg @ref LL_DMAMUX_REQ_GEN_4
-  *         @arg @ref LL_DMAMUX_REQ_GEN_5
-  *         @arg @ref LL_DMAMUX_REQ_GEN_6
-  *         @arg @ref LL_DMAMUX_REQ_GEN_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMAMUX_DisableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  CLEAR_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_OIE);
-}
-
-/**
-  * @brief  Check if the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x is enabled or disabled.
-  * @rmtoll RGxCR        OIE           LL_DMAMUX_IsEnabledIT_RGO
-  * @param  DMAMUXx DMAMUXx Instance
-  * @param  RequestGenChannel This parameter can be one of the following values:
-  *         @arg @ref LL_DMAMUX_REQ_GEN_0
-  *         @arg @ref LL_DMAMUX_REQ_GEN_1
-  *         @arg @ref LL_DMAMUX_REQ_GEN_2
-  *         @arg @ref LL_DMAMUX_REQ_GEN_3
-  *         @arg @ref LL_DMAMUX_REQ_GEN_4
-  *         @arg @ref LL_DMAMUX_REQ_GEN_5
-  *         @arg @ref LL_DMAMUX_REQ_GEN_6
-  *         @arg @ref LL_DMAMUX_REQ_GEN_7
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
-{
-  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
-
-  return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_OIE) == (DMAMUX_RGxCR_OIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* DMAMUX1 || DMAMUX2 */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32H7xx_LL_DMAMUX_H */
-
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_ll_dmamux.h
+  * @author  MCD Application Team
+  * @brief   Header file of DMAMUX LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_LL_DMAMUX_H
+#define STM32H7xx_LL_DMAMUX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx.h"
+
+/** @addtogroup STM32H7xx_LL_Driver
+  * @{
+  */
+
+#if defined (DMAMUX1) || defined (DMAMUX2)
+
+/** @defgroup DMAMUX_LL DMAMUX
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup DMAMUX_LL_Private_Constants DMAMUX Private Constants
+  * @{
+  */
+/* Define used to get DMAMUX CCR register size */
+#define DMAMUX_CCR_SIZE                   0x00000004U
+
+/* Define used to get DMAMUX RGCR register size */
+#define DMAMUX_RGCR_SIZE                  0x00000004U
+
+/* Define used to get DMAMUX RequestGenerator offset */
+#define DMAMUX_REQ_GEN_OFFSET             (DMAMUX1_RequestGenerator0_BASE - DMAMUX1_BASE)
+/* Define used to get DMAMUX Channel Status offset */
+#define DMAMUX_CH_STATUS_OFFSET           (DMAMUX1_ChannelStatus_BASE - DMAMUX1_BASE)
+/* Define used to get DMAMUX RequestGenerator status offset */
+#define DMAMUX_REQ_GEN_STATUS_OFFSET      (DMAMUX1_RequestGenStatus_BASE - DMAMUX1_BASE)
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DMAMUX_LL_Exported_Constants DMAMUX Exported Constants
+  * @{
+  */
+/** @defgroup DMAMUX_LL_EC_CLEAR_FLAG Clear Flags Defines
+  * @brief    Flags defines which can be used with LL_DMAMUX_WriteReg function
+  * @{
+  */
+#define LL_DMAMUX_CFR_CSOF0               DMAMUX_CFR_CSOF0       /*!< Synchronization Event Overrun Flag Channel 0   */
+#define LL_DMAMUX_CFR_CSOF1               DMAMUX_CFR_CSOF1       /*!< Synchronization Event Overrun Flag Channel 1   */
+#define LL_DMAMUX_CFR_CSOF2               DMAMUX_CFR_CSOF2       /*!< Synchronization Event Overrun Flag Channel 2   */
+#define LL_DMAMUX_CFR_CSOF3               DMAMUX_CFR_CSOF3       /*!< Synchronization Event Overrun Flag Channel 3   */
+#define LL_DMAMUX_CFR_CSOF4               DMAMUX_CFR_CSOF4       /*!< Synchronization Event Overrun Flag Channel 4   */
+#define LL_DMAMUX_CFR_CSOF5               DMAMUX_CFR_CSOF5       /*!< Synchronization Event Overrun Flag Channel 5   */
+#define LL_DMAMUX_CFR_CSOF6               DMAMUX_CFR_CSOF6       /*!< Synchronization Event Overrun Flag Channel 6   */
+#define LL_DMAMUX_CFR_CSOF7               DMAMUX_CFR_CSOF7       /*!< Synchronization Event Overrun Flag Channel 7   */
+#define LL_DMAMUX_CFR_CSOF8               DMAMUX_CFR_CSOF8       /*!< Synchronization Event Overrun Flag Channel 8   */
+#define LL_DMAMUX_CFR_CSOF9               DMAMUX_CFR_CSOF9       /*!< Synchronization Event Overrun Flag Channel 9   */
+#define LL_DMAMUX_CFR_CSOF10              DMAMUX_CFR_CSOF10      /*!< Synchronization Event Overrun Flag Channel 10  */
+#define LL_DMAMUX_CFR_CSOF11              DMAMUX_CFR_CSOF11      /*!< Synchronization Event Overrun Flag Channel 11  */
+#define LL_DMAMUX_CFR_CSOF12              DMAMUX_CFR_CSOF12      /*!< Synchronization Event Overrun Flag Channel 12  */
+#define LL_DMAMUX_CFR_CSOF13              DMAMUX_CFR_CSOF13      /*!< Synchronization Event Overrun Flag Channel 13  */
+#define LL_DMAMUX_CFR_CSOF14              DMAMUX_CFR_CSOF14      /*!< Synchronization Event Overrun Flag Channel 14  */
+#define LL_DMAMUX_CFR_CSOF15              DMAMUX_CFR_CSOF15      /*!< Synchronization Event Overrun Flag Channel 15  */
+#define LL_DMAMUX_RGCFR_RGCOF0            DMAMUX_RGCFR_COF0      /*!< Request Generator 0 Trigger Event Overrun Flag */
+#define LL_DMAMUX_RGCFR_RGCOF1            DMAMUX_RGCFR_COF1      /*!< Request Generator 1 Trigger Event Overrun Flag */
+#define LL_DMAMUX_RGCFR_RGCOF2            DMAMUX_RGCFR_COF2      /*!< Request Generator 2 Trigger Event Overrun Flag */
+#define LL_DMAMUX_RGCFR_RGCOF3            DMAMUX_RGCFR_COF3      /*!< Request Generator 3 Trigger Event Overrun Flag */
+#define LL_DMAMUX_RGCFR_RGCOF4            DMAMUX_RGCFR_COF4      /*!< Request Generator 4 Trigger Event Overrun Flag */
+#define LL_DMAMUX_RGCFR_RGCOF5            DMAMUX_RGCFR_COF5      /*!< Request Generator 5 Trigger Event Overrun Flag */
+#define LL_DMAMUX_RGCFR_RGCOF6            DMAMUX_RGCFR_COF6      /*!< Request Generator 6 Trigger Event Overrun Flag */
+#define LL_DMAMUX_RGCFR_RGCOF7            DMAMUX_RGCFR_COF7      /*!< Request Generator 7 Trigger Event Overrun Flag */
+/**
+  * @}
+  */
+
+/** @defgroup DMAMUX_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_DMAMUX_ReadReg function
+  * @{
+  */
+#define LL_DMAMUX_CSR_SOF0                DMAMUX_CSR_SOF0       /*!< Synchronization Event Overrun Flag Channel 0   */
+#define LL_DMAMUX_CSR_SOF1                DMAMUX_CSR_SOF1       /*!< Synchronization Event Overrun Flag Channel 1   */
+#define LL_DMAMUX_CSR_SOF2                DMAMUX_CSR_SOF2       /*!< Synchronization Event Overrun Flag Channel 2   */
+#define LL_DMAMUX_CSR_SOF3                DMAMUX_CSR_SOF3       /*!< Synchronization Event Overrun Flag Channel 3   */
+#define LL_DMAMUX_CSR_SOF4                DMAMUX_CSR_SOF4       /*!< Synchronization Event Overrun Flag Channel 4   */
+#define LL_DMAMUX_CSR_SOF5                DMAMUX_CSR_SOF5       /*!< Synchronization Event Overrun Flag Channel 5   */
+#define LL_DMAMUX_CSR_SOF6                DMAMUX_CSR_SOF6       /*!< Synchronization Event Overrun Flag Channel 6   */
+#define LL_DMAMUX_CSR_SOF7                DMAMUX_CSR_SOF7       /*!< Synchronization Event Overrun Flag Channel 7   */
+#define LL_DMAMUX_CSR_SOF8                DMAMUX_CSR_SOF8       /*!< Synchronization Event Overrun Flag Channel 8   */
+#define LL_DMAMUX_CSR_SOF9                DMAMUX_CSR_SOF9       /*!< Synchronization Event Overrun Flag Channel 9   */
+#define LL_DMAMUX_CSR_SOF10               DMAMUX_CSR_SOF10      /*!< Synchronization Event Overrun Flag Channel 10  */
+#define LL_DMAMUX_CSR_SOF11               DMAMUX_CSR_SOF11      /*!< Synchronization Event Overrun Flag Channel 11  */
+#define LL_DMAMUX_CSR_SOF12               DMAMUX_CSR_SOF12      /*!< Synchronization Event Overrun Flag Channel 12  */
+#define LL_DMAMUX_CSR_SOF13               DMAMUX_CSR_SOF13      /*!< Synchronization Event Overrun Flag Channel 13  */
+#define LL_DMAMUX_CSR_SOF14               DMAMUX_CSR_SOF14      /*!< Synchronization Event Overrun Flag Channel 14  */
+#define LL_DMAMUX_CSR_SOF15               DMAMUX_CSR_SOF15      /*!< Synchronization Event Overrun Flag Channel 15  */
+#define LL_DMAMUX_RGSR_RGOF0              DMAMUX_RGSR_OF0       /*!< Request Generator 0 Trigger Event Overrun Flag */
+#define LL_DMAMUX_RGSR_RGOF1              DMAMUX_RGSR_OF1       /*!< Request Generator 1 Trigger Event Overrun Flag */
+#define LL_DMAMUX_RGSR_RGOF2              DMAMUX_RGSR_OF2       /*!< Request Generator 2 Trigger Event Overrun Flag */
+#define LL_DMAMUX_RGSR_RGOF3              DMAMUX_RGSR_OF3       /*!< Request Generator 3 Trigger Event Overrun Flag */
+#define LL_DMAMUX_RGSR_RGOF4              DMAMUX_RGSR_OF4       /*!< Request Generator 4 Trigger Event Overrun Flag */
+#define LL_DMAMUX_RGSR_RGOF5              DMAMUX_RGSR_OF5       /*!< Request Generator 5 Trigger Event Overrun Flag */
+#define LL_DMAMUX_RGSR_RGOF6              DMAMUX_RGSR_OF6       /*!< Request Generator 6 Trigger Event Overrun Flag */
+#define LL_DMAMUX_RGSR_RGOF7              DMAMUX_RGSR_OF7       /*!< Request Generator 7 Trigger Event Overrun Flag */
+/**
+  * @}
+  */
+
+/** @defgroup DMAMUX_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_DMA_ReadReg and  LL_DMAMUX_WriteReg functions
+  * @{
+  */
+#define LL_DMAMUX_CCR_SOIE                DMAMUX_CxCR_SOIE          /*!< Synchronization Event Overrun Interrupt               */
+#define LL_DMAMUX_RGCR_RGOIE              DMAMUX_RGxCR_OIE          /*!< Request Generation Trigger Event Overrun Interrupt    */
+/**
+  * @}
+  */
+
+/** @defgroup DMAMUX1_Request_selection DMAMUX1 Request selection
+  * @brief    DMAMUX1 Request selection
+  * @{
+  */
+/* DMAMUX1 requests */
+#define LL_DMAMUX1_REQ_MEM2MEM          0U   /*!< memory to memory transfer       */
+#define LL_DMAMUX1_REQ_GENERATOR0       1U   /*!< DMAMUX1 request generator 0     */
+#define LL_DMAMUX1_REQ_GENERATOR1       2U   /*!< DMAMUX1 request generator 1     */
+#define LL_DMAMUX1_REQ_GENERATOR2       3U   /*!< DMAMUX1 request generator 2     */
+#define LL_DMAMUX1_REQ_GENERATOR3       4U   /*!< DMAMUX1 request generator 3     */
+#define LL_DMAMUX1_REQ_GENERATOR4       5U   /*!< DMAMUX1 request generator 4     */
+#define LL_DMAMUX1_REQ_GENERATOR5       6U   /*!< DMAMUX1 request generator 5     */
+#define LL_DMAMUX1_REQ_GENERATOR6       7U   /*!< DMAMUX1 request generator 6     */
+#define LL_DMAMUX1_REQ_GENERATOR7       8U   /*!< DMAMUX1 request generator 7     */
+#define LL_DMAMUX1_REQ_ADC1             9U   /*!< DMAMUX1 ADC1 request            */
+#define LL_DMAMUX1_REQ_ADC2             10U  /*!< DMAMUX1 ADC2 request            */
+#define LL_DMAMUX1_REQ_TIM1_CH1         11U  /*!< DMAMUX1 TIM1 CH1 request        */
+#define LL_DMAMUX1_REQ_TIM1_CH2         12U  /*!< DMAMUX1 TIM1 CH2 request        */
+#define LL_DMAMUX1_REQ_TIM1_CH3         13U  /*!< DMAMUX1 TIM1 CH3 request        */
+#define LL_DMAMUX1_REQ_TIM1_CH4         14U  /*!< DMAMUX1 TIM1 CH4 request        */
+#define LL_DMAMUX1_REQ_TIM1_UP          15U  /*!< DMAMUX1 TIM1 UP request         */
+#define LL_DMAMUX1_REQ_TIM1_TRIG        16U  /*!< DMAMUX1 TIM1 TRIG request       */
+#define LL_DMAMUX1_REQ_TIM1_COM         17U  /*!< DMAMUX1 TIM1 COM request        */
+#define LL_DMAMUX1_REQ_TIM2_CH1         18U  /*!< DMAMUX1 TIM2 CH1 request        */
+#define LL_DMAMUX1_REQ_TIM2_CH2         19U  /*!< DMAMUX1 TIM2 CH2 request        */
+#define LL_DMAMUX1_REQ_TIM2_CH3         20U  /*!< DMAMUX1 TIM2 CH3 request        */
+#define LL_DMAMUX1_REQ_TIM2_CH4         21U  /*!< DMAMUX1 TIM2 CH4 request        */
+#define LL_DMAMUX1_REQ_TIM2_UP          22U  /*!< DMAMUX1 TIM2 UP request         */
+#define LL_DMAMUX1_REQ_TIM3_CH1         23U  /*!< DMAMUX1 TIM3 CH1 request        */
+#define LL_DMAMUX1_REQ_TIM3_CH2         24U  /*!< DMAMUX1 TIM3 CH2 request        */
+#define LL_DMAMUX1_REQ_TIM3_CH3         25U  /*!< DMAMUX1 TIM3 CH3 request        */
+#define LL_DMAMUX1_REQ_TIM3_CH4         26U  /*!< DMAMUX1 TIM3 CH4 request        */
+#define LL_DMAMUX1_REQ_TIM3_UP          27U  /*!< DMAMUX1 TIM3 UP request         */
+#define LL_DMAMUX1_REQ_TIM3_TRIG        28U  /*!< DMAMUX1 TIM3 TRIG request       */
+#define LL_DMAMUX1_REQ_TIM4_CH1         29U  /*!< DMAMUX1 TIM4 CH1 request        */
+#define LL_DMAMUX1_REQ_TIM4_CH2         30U  /*!< DMAMUX1 TIM4 CH2 request        */
+#define LL_DMAMUX1_REQ_TIM4_CH3         31U  /*!< DMAMUX1 TIM4 CH3 request        */
+#define LL_DMAMUX1_REQ_TIM4_UP          32U  /*!< DMAMUX1 TIM4 UP request         */
+#define LL_DMAMUX1_REQ_I2C1_RX          33U  /*!< DMAMUX1 I2C1 RX request         */
+#define LL_DMAMUX1_REQ_I2C1_TX          34U  /*!< DMAMUX1 I2C1 TX request         */
+#define LL_DMAMUX1_REQ_I2C2_RX          35U  /*!< DMAMUX1 I2C2 RX request         */
+#define LL_DMAMUX1_REQ_I2C2_TX          36U  /*!< DMAMUX1 I2C2 TX request         */
+#define LL_DMAMUX1_REQ_SPI1_RX          37U  /*!< DMAMUX1 SPI1 RX request         */
+#define LL_DMAMUX1_REQ_SPI1_TX          38U  /*!< DMAMUX1 SPI1 TX request         */
+#define LL_DMAMUX1_REQ_SPI2_RX          39U  /*!< DMAMUX1 SPI2 RX request         */
+#define LL_DMAMUX1_REQ_SPI2_TX          40U  /*!< DMAMUX1 SPI2 TX request         */
+#define LL_DMAMUX1_REQ_USART1_RX        41U  /*!< DMAMUX1 USART1 RX request       */
+#define LL_DMAMUX1_REQ_USART1_TX        42U  /*!< DMAMUX1 USART1 TX request       */
+#define LL_DMAMUX1_REQ_USART2_RX        43U  /*!< DMAMUX1 USART2 RX request       */
+#define LL_DMAMUX1_REQ_USART2_TX        44U  /*!< DMAMUX1 USART2 TX request       */
+#define LL_DMAMUX1_REQ_USART3_RX        45U  /*!< DMAMUX1 USART3 RX request       */
+#define LL_DMAMUX1_REQ_USART3_TX        46U  /*!< DMAMUX1 USART3 TX request       */
+#define LL_DMAMUX1_REQ_TIM8_CH1         47U  /*!< DMAMUX1 TIM8 CH1 request        */
+#define LL_DMAMUX1_REQ_TIM8_CH2         48U  /*!< DMAMUX1 TIM8 CH2 request        */
+#define LL_DMAMUX1_REQ_TIM8_CH3         49U  /*!< DMAMUX1 TIM8 CH3 request        */
+#define LL_DMAMUX1_REQ_TIM8_CH4         50U  /*!< DMAMUX1 TIM8 CH4 request        */
+#define LL_DMAMUX1_REQ_TIM8_UP          51U  /*!< DMAMUX1 TIM8 UP request         */
+#define LL_DMAMUX1_REQ_TIM8_TRIG        52U  /*!< DMAMUX1 TIM8 TRIG request       */
+#define LL_DMAMUX1_REQ_TIM8_COM         53U  /*!< DMAMUX1 TIM8 COM request        */
+#define LL_DMAMUX1_REQ_TIM5_CH1         55U  /*!< DMAMUX1 TIM5 CH1 request        */
+#define LL_DMAMUX1_REQ_TIM5_CH2         56U  /*!< DMAMUX1 TIM5 CH2 request        */
+#define LL_DMAMUX1_REQ_TIM5_CH3         57U  /*!< DMAMUX1 TIM5 CH3 request        */
+#define LL_DMAMUX1_REQ_TIM5_CH4         58U  /*!< DMAMUX1 TIM5 CH4 request        */
+#define LL_DMAMUX1_REQ_TIM5_UP          59U  /*!< DMAMUX1 TIM5 UP request         */
+#define LL_DMAMUX1_REQ_TIM5_TRIG        60U  /*!< DMAMUX1 TIM5 TRIG request       */
+#define LL_DMAMUX1_REQ_SPI3_RX          61U  /*!< DMAMUX1 SPI3 RX request         */
+#define LL_DMAMUX1_REQ_SPI3_TX          62U  /*!< DMAMUX1 SPI3 TX request         */
+#define LL_DMAMUX1_REQ_UART4_RX         63U  /*!< DMAMUX1 UART4 RX request        */
+#define LL_DMAMUX1_REQ_UART4_TX         64U  /*!< DMAMUX1 UART4 TX request        */
+#define LL_DMAMUX1_REQ_UART5_RX         65U  /*!< DMAMUX1 UART5 RX request        */
+#define LL_DMAMUX1_REQ_UART5_TX         66U  /*!< DMAMUX1 UART5 TX request        */
+#define LL_DMAMUX1_REQ_DAC1_CH1         67U  /*!< DMAMUX1 DAC1 Channel 1 request  */
+#define LL_DMAMUX1_REQ_DAC1_CH2         68U  /*!< DMAMUX1 DAC1 Channel 2 request  */
+#define LL_DMAMUX1_REQ_TIM6_UP          69U  /*!< DMAMUX1 TIM6 UP request         */
+#define LL_DMAMUX1_REQ_TIM7_UP          70U  /*!< DMAMUX1 TIM7 UP request         */
+#define LL_DMAMUX1_REQ_USART6_RX        71U  /*!< DMAMUX1 USART6 RX request       */
+#define LL_DMAMUX1_REQ_USART6_TX        72U  /*!< DMAMUX1 USART6 TX request       */
+#define LL_DMAMUX1_REQ_I2C3_RX          73U  /*!< DMAMUX1 I2C3 RX request         */
+#define LL_DMAMUX1_REQ_I2C3_TX          74U  /*!< DMAMUX1 I2C3 TX request         */
+#if defined (PSSI)
+#define LL_DMAMUX1_REQ_DCMI_PSSI        75U  /*!< DMAMUX1 DCMI/PSSI request       */
+#define LL_DMAMUX1_REQ_DCMI             LL_DMAMUX1_REQ_DCMI_PSSI /* Legacy define */
+#else
+#define LL_DMAMUX1_REQ_DCMI             75U  /*!< DMAMUX1 DCMI request            */
+#endif /* PSSI */
+#define LL_DMAMUX1_REQ_CRYP_IN          76U  /*!< DMAMUX1 CRYP IN request         */
+#define LL_DMAMUX1_REQ_CRYP_OUT         77U  /*!< DMAMUX1 CRYP OUT request        */
+#define LL_DMAMUX1_REQ_HASH_IN          78U  /*!< DMAMUX1 HASH IN request         */
+#define LL_DMAMUX1_REQ_UART7_RX         79U  /*!< DMAMUX1 UART7 RX request        */
+#define LL_DMAMUX1_REQ_UART7_TX         80U  /*!< DMAMUX1 UART7 TX request        */
+#define LL_DMAMUX1_REQ_UART8_RX         81U  /*!< DMAMUX1 UART8 RX request        */
+#define LL_DMAMUX1_REQ_UART8_TX         82U  /*!< DMAMUX1 UART8 TX request        */
+#define LL_DMAMUX1_REQ_SPI4_RX          83U  /*!< DMAMUX1 SPI4 RX request         */
+#define LL_DMAMUX1_REQ_SPI4_TX          84U  /*!< DMAMUX1 SPI4 TX request         */
+#define LL_DMAMUX1_REQ_SPI5_RX          85U  /*!< DMAMUX1 SPI5 RX request         */
+#define LL_DMAMUX1_REQ_SPI5_TX          86U  /*!< DMAMUX1 SPI5 TX request         */
+#define LL_DMAMUX1_REQ_SAI1_A           87U  /*!< DMAMUX1 SAI1 A request          */
+#define LL_DMAMUX1_REQ_SAI1_B           88U  /*!< DMAMUX1 SAI1 B request          */
+#if defined(SAI2)
+#define LL_DMAMUX1_REQ_SAI2_A           89U  /*!< DMAMUX1 SAI2 A request          */
+#define LL_DMAMUX1_REQ_SAI2_B           90U  /*!< DMAMUX1 SAI2 B request          */
+#endif /* SAI2 */
+#define LL_DMAMUX1_REQ_SWPMI_RX         91U  /*!< DMAMUX1 SWPMI RX request        */
+#define LL_DMAMUX1_REQ_SWPMI_TX         92U  /*!< DMAMUX1 SWPMI TX request        */
+#define LL_DMAMUX1_REQ_SPDIF_RX_DT      93U  /*!< DMAMUX1 SPDIF RXDT request      */
+#define LL_DMAMUX1_REQ_SPDIF_RX_CS      94U  /*!< DMAMUX1 SPDIF RXCS request      */
+#if defined (HRTIM1)
+#define LL_DMAMUX1_REQ_HRTIM_MASTER     95U  /*!< DMAMUX1 HRTIM1 Master request 1 */
+#define LL_DMAMUX1_REQ_HRTIM_TIMER_A    96U  /*!< DMAMUX1 HRTIM1 Timer A request 2 */
+#define LL_DMAMUX1_REQ_HRTIM_TIMER_B    97U  /*!< DMAMUX1 HRTIM1 Timer B request 3 */
+#define LL_DMAMUX1_REQ_HRTIM_TIMER_C    98U  /*!< DMAMUX1 HRTIM1 Timer C request 4 */
+#define LL_DMAMUX1_REQ_HRTIM_TIMER_D    99U  /*!< DMAMUX1 HRTIM1 Timer D request 5 */
+#define LL_DMAMUX1_REQ_HRTIM_TIMER_E   100U  /*!< DMAMUX1 HRTIM1 Timer E request 6 */
+#endif /* HRTIM1 */
+#define LL_DMAMUX1_REQ_DFSDM1_FLT0     101U  /*!< DMAMUX1 DFSDM1 Filter0 request  */
+#define LL_DMAMUX1_REQ_DFSDM1_FLT1     102U  /*!< DMAMUX1 DFSDM1 Filter1 request  */
+#define LL_DMAMUX1_REQ_DFSDM1_FLT2     103U  /*!< DMAMUX1 DFSDM1 Filter2 request  */
+#define LL_DMAMUX1_REQ_DFSDM1_FLT3     104U  /*!< DMAMUX1 DFSDM1 Filter3 request  */
+#define LL_DMAMUX1_REQ_TIM15_CH1       105U  /*!< DMAMUX1 TIM15 CH1 request       */
+#define LL_DMAMUX1_REQ_TIM15_UP        106U  /*!< DMAMUX1 TIM15 UP request        */
+#define LL_DMAMUX1_REQ_TIM15_TRIG      107U  /*!< DMAMUX1 TIM15 TRIG request      */
+#define LL_DMAMUX1_REQ_TIM15_COM       108U  /*!< DMAMUX1 TIM15 COM request       */
+#define LL_DMAMUX1_REQ_TIM16_CH1       109U  /*!< DMAMUX1 TIM16 CH1 request       */
+#define LL_DMAMUX1_REQ_TIM16_UP        110U  /*!< DMAMUX1 TIM16 UP request        */
+#define LL_DMAMUX1_REQ_TIM17_CH1       111U  /*!< DMAMUX1 TIM17 CH1 request       */
+#define LL_DMAMUX1_REQ_TIM17_UP        112U  /*!< DMAMUX1 TIM17 UP request        */
+#if defined (SAI3)
+#define LL_DMAMUX1_REQ_SAI3_A          113U  /*!< DMAMUX1 SAI3 A request          */
+#define LL_DMAMUX1_REQ_SAI3_B          114U  /*!< DMAMUX1 SAI3 B request          */
+#endif /* SAI3 */
+#if defined (ADC3)
+#define LL_DMAMUX1_REQ_ADC3            115U  /*!< DMAMUX1 ADC3  request           */
+#endif /* ADC3 */
+#if defined (UART9)
+#define LL_DMAMUX1_REQ_UART9_RX        116U  /*!< DMAMUX1 UART9 RX request        */
+#define LL_DMAMUX1_REQ_UART9_TX        117U  /*!< DMAMUX1 UART9 TX request        */
+#endif /* UART9 */
+#if defined (USART10)
+#define LL_DMAMUX1_REQ_USART10_RX      118U  /*!< DMAMUX1 USART10 RX request      */
+#define LL_DMAMUX1_REQ_USART10_TX      119U  /*!< DMAMUX1 USART10 TX request      */
+#endif /* USART10 */
+#if defined(FMAC)
+#define LL_DMAMUX1_REQ_FMAC_READ       120U  /*!< DMAMUX1 FMAC Read request       */
+#define LL_DMAMUX1_REQ_FMAC_WRITE      121U  /*!< DMAMUX1 FMAC Write request      */
+#endif /* FMAC */
+#if defined(CORDIC)
+#define LL_DMAMUX1_REQ_CORDIC_READ     122U  /*!< DMAMUX1 CORDIC Read request     */
+#define LL_DMAMUX1_REQ_CORDIC_WRITE    123U  /*!< DMAMUX1 CORDIC Write request    */
+#endif /* CORDIC */
+#if defined(I2C5)
+#define LL_DMAMUX1_REQ_I2C5_RX         124U  /*!< DMAMUX1 I2C5 RX request         */
+#define LL_DMAMUX1_REQ_I2C5_TX         125U  /*!< DMAMUX1 I2C5 TX request         */
+#endif /* I2C5 */
+#if defined(TIM23)
+#define LL_DMAMUX1_REQ_TIM23_CH1       126U  /*!< DMAMUX1 TIM23 CH1 request  */
+#define LL_DMAMUX1_REQ_TIM23_CH2       127U  /*!< DMAMUX1 TIM23 CH2 request  */
+#define LL_DMAMUX1_REQ_TIM23_CH3       128U  /*!< DMAMUX1 TIM23 CH3 request  */
+#define LL_DMAMUX1_REQ_TIM23_CH4       129U  /*!< DMAMUX1 TIM23 CH4 request  */
+#define LL_DMAMUX1_REQ_TIM23_UP        130U  /*!< DMAMUX1 TIM23 UP request   */
+#define LL_DMAMUX1_REQ_TIM23_TRIG      131U  /*!< DMAMUX1 TIM23 TRIG request */
+#endif /* TIM23 */
+#if defined(TIM24)
+#define LL_DMAMUX1_REQ_TIM24_CH1       132U  /*!< DMAMUX1 TIM24 CH1 request  */
+#define LL_DMAMUX1_REQ_TIM24_CH2       133U  /*!< DMAMUX1 TIM24 CH2 request  */
+#define LL_DMAMUX1_REQ_TIM24_CH3       134U  /*!< DMAMUX1 TIM24 CH3 request  */
+#define LL_DMAMUX1_REQ_TIM24_CH4       135U  /*!< DMAMUX1 TIM24 CH4 request  */
+#define LL_DMAMUX1_REQ_TIM24_UP        136U  /*!< DMAMUX1 TIM24 UP request   */
+#define LL_DMAMUX1_REQ_TIM24_TRIG      137U  /*!< DMAMUX1 TIM24 TRIG request */
+#endif /* TIM24 */
+/**
+  * @}
+  */
+
+/** @defgroup DMAMUX2_Request_selection DMAMUX2 Request selection
+  * @brief    DMAMUX2 Request selection
+  * @{
+  */
+/* DMAMUX2 requests */
+#define LL_DMAMUX2_REQ_MEM2MEM          0U  /*!< memory to memory transfer        */
+#define LL_DMAMUX2_REQ_GENERATOR0       1U  /*!< DMAMUX2 request generator 0      */
+#define LL_DMAMUX2_REQ_GENERATOR1       2U  /*!< DMAMUX2 request generator 1      */
+#define LL_DMAMUX2_REQ_GENERATOR2       3U  /*!< DMAMUX2 request generator 2      */
+#define LL_DMAMUX2_REQ_GENERATOR3       4U  /*!< DMAMUX2 request generator 3      */
+#define LL_DMAMUX2_REQ_GENERATOR4       5U  /*!< DMAMUX2 request generator 4      */
+#define LL_DMAMUX2_REQ_GENERATOR5       6U  /*!< DMAMUX2 request generator 5      */
+#define LL_DMAMUX2_REQ_GENERATOR6       7U  /*!< DMAMUX2 request generator 6      */
+#define LL_DMAMUX2_REQ_GENERATOR7       8U  /*!< DMAMUX2 request generator 7      */
+#define LL_DMAMUX2_REQ_LPUART1_RX       9U  /*!< DMAMUX2 LP_UART1_RX request      */
+#define LL_DMAMUX2_REQ_LPUART1_TX      10U  /*!< DMAMUX2 LP_UART1_TX request      */
+#define LL_DMAMUX2_REQ_SPI6_RX         11U  /*!< DMAMUX2 SPI6 RX request          */
+#define LL_DMAMUX2_REQ_SPI6_TX         12U  /*!< DMAMUX2 SPI6 TX request          */
+#define LL_DMAMUX2_REQ_I2C4_RX         13U  /*!< DMAMUX2 I2C4 RX request          */
+#define LL_DMAMUX2_REQ_I2C4_TX         14U  /*!< DMAMUX2 I2C4 TX request          */
+#if defined (SAI4)
+#define LL_DMAMUX2_REQ_SAI4_A          15U  /*!< DMAMUX2 SAI4 A request           */
+#define LL_DMAMUX2_REQ_SAI4_B          16U  /*!< DMAMUX2 SAI4 B request           */
+#endif /* SAI4 */
+#if defined (ADC3)
+#define LL_DMAMUX2_REQ_ADC3            17U  /*!< DMAMUX2 ADC3 request             */
+#endif /* ADC3 */
+#if defined (DAC2)
+#define LL_DMAMUX2_REQ_DAC2_CH1        17U  /*!< DMAMUX2 DAC2 CH1 request         */
+#endif /* DAC2 */
+#if defined (DFSDM2_Channel0)
+#define LL_DMAMUX2_REQ_DFSDM2_FLT0     18U  /*!< DMAMUX2 DFSDM2 Filter0 request   */
+#endif /* DFSDM2_Channel0 */
+/**
+  * @}
+  */
+
+
+/** @defgroup DMAMUX_LL_EC_CHANNEL DMAMUX Channel
+  * @{
+  */
+#define LL_DMAMUX_CHANNEL_0     0x00000000U  /*!< DMAMUX1 Channel 0  connected to DMA1 Channel 0 , DMAMUX2 Channel 0 connected to BDMA Channel 0 */
+#define LL_DMAMUX_CHANNEL_1     0x00000001U  /*!< DMAMUX1 Channel 1  connected to DMA1 Channel 1 , DMAMUX2 Channel 1 connected to BDMA Channel 1 */
+#define LL_DMAMUX_CHANNEL_2     0x00000002U  /*!< DMAMUX1 Channel 2  connected to DMA1 Channel 2 , DMAMUX2 Channel 2 connected to BDMA Channel 2 */
+#define LL_DMAMUX_CHANNEL_3     0x00000003U  /*!< DMAMUX1 Channel 3  connected to DMA1 Channel 3 , DMAMUX2 Channel 3 connected to BDMA Channel 3 */
+#define LL_DMAMUX_CHANNEL_4     0x00000004U  /*!< DMAMUX1 Channel 4  connected to DMA1 Channel 4 , DMAMUX2 Channel 4 connected to BDMA Channel 4 */
+#define LL_DMAMUX_CHANNEL_5     0x00000005U  /*!< DMAMUX1 Channel 5  connected to DMA1 Channel 5 , DMAMUX2 Channel 5 connected to BDMA Channel 5 */
+#define LL_DMAMUX_CHANNEL_6     0x00000006U  /*!< DMAMUX1 Channel 6  connected to DMA1 Channel 6 , DMAMUX2 Channel 6 connected to BDMA Channel 6 */
+#define LL_DMAMUX_CHANNEL_7     0x00000007U  /*!< DMAMUX1 Channel 7  connected to DMA1 Channel 7 , DMAMUX2 Channel 7 connected to BDMA Channel 7 */
+#define LL_DMAMUX_CHANNEL_8     0x00000008U  /*!< DMAMUX1 Channel 8  connected to DMA2 Channel 0 */
+#define LL_DMAMUX_CHANNEL_9     0x00000009U  /*!< DMAMUX1 Channel 9  connected to DMA2 Channel 1 */
+#define LL_DMAMUX_CHANNEL_10    0x0000000AU  /*!< DMAMUX1 Channel 10 connected to DMA2 Channel 2 */
+#define LL_DMAMUX_CHANNEL_11    0x0000000BU  /*!< DMAMUX1 Channel 11 connected to DMA2 Channel 3 */
+#define LL_DMAMUX_CHANNEL_12    0x0000000CU  /*!< DMAMUX1 Channel 12 connected to DMA2 Channel 4 */
+#define LL_DMAMUX_CHANNEL_13    0x0000000DU  /*!< DMAMUX1 Channel 13 connected to DMA2 Channel 5 */
+#define LL_DMAMUX_CHANNEL_14    0x0000000EU  /*!< DMAMUX1 Channel 14 connected to DMA2 Channel 6 */
+#define LL_DMAMUX_CHANNEL_15    0x0000000FU  /*!< DMAMUX1 Channel 15 connected to DMA2 Channel 7 */
+/**
+  * @}
+  */
+
+/** @defgroup DMAMUX_LL_EC_SYNC_NO Synchronization Signal Polarity
+  * @{
+  */
+#define LL_DMAMUX_SYNC_NO_EVENT            0x00000000U                               /*!< All requests are blocked                            */
+#define LL_DMAMUX_SYNC_POL_RISING          DMAMUX_CxCR_SPOL_0                        /*!< Synchronization on event on rising edge             */
+#define LL_DMAMUX_SYNC_POL_FALLING         DMAMUX_CxCR_SPOL_1                        /*!< Synchronization on event on falling edge            */
+#define LL_DMAMUX_SYNC_POL_RISING_FALLING  (DMAMUX_CxCR_SPOL_0 | DMAMUX_CxCR_SPOL_1) /*!< Synchronization on event on rising and falling edge */
+/**
+  * @}
+  */
+
+/** @defgroup DMAMUX_LL_EC_SYNC_EVT Synchronization Signal Event
+  * @{
+  */
+#define LL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT   0x00000000U   /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel0 Event */
+#define LL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT   0x01000000U   /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel1 Event */
+#define LL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT   0x02000000U   /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel2 Event */
+#define LL_DMAMUX1_SYNC_LPTIM1_OUT        0x03000000U   /*!< DMAMUX1 synchronization Signal is LPTIM1 OUT             */
+#define LL_DMAMUX1_SYNC_LPTIM2_OUT        0x04000000U   /*!< DMAMUX1 synchronization Signal is LPTIM2 OUT             */
+#define LL_DMAMUX1_SYNC_LPTIM3_OUT        0x05000000U   /*!< DMAMUX1 synchronization Signal is LPTIM3 OUT             */
+#define LL_DMAMUX1_SYNC_EXTI0             0x06000000U   /*!< DMAMUX1 synchronization Signal is EXTI0 IT               */
+#define LL_DMAMUX1_SYNC_TIM12_TRGO        0x07000000U   /*!< DMAMUX1 synchronization Signal is TIM12 TRGO             */
+
+#define LL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT   0x00000000U   /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel0 Event */
+#define LL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT   0x01000000U   /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel1 Event */
+#define LL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT   0x02000000U   /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel2 Event */
+#define LL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT   0x03000000U   /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel3 Event */
+#define LL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT   0x04000000U   /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel4 Event */
+#define LL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT   0x05000000U   /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel5 Event */
+#define LL_DMAMUX2_SYNC_LPUART1_RX_WKUP   0x06000000U   /*!< DMAMUX2 synchronization Signal is LPUART1 RX Wakeup      */
+#define LL_DMAMUX2_SYNC_LPUART1_TX_WKUP   0x07000000U   /*!< DMAMUX2 synchronization Signal is LPUART1 TX Wakeup      */
+#define LL_DMAMUX2_SYNC_LPTIM2_OUT        0x08000000U   /*!< DMAMUX2 synchronization Signal is LPTIM2 output          */
+#define LL_DMAMUX2_SYNC_LPTIM3_OUT        0x09000000U   /*!< DMAMUX2 synchronization Signal is LPTIM3 output          */
+#define LL_DMAMUX2_SYNC_I2C4_WKUP         0x0A000000U   /*!< DMAMUX2 synchronization Signal is I2C4 Wakeup            */
+#define LL_DMAMUX2_SYNC_SPI6_WKUP         0x0B000000U   /*!< DMAMUX2 synchronization Signal is SPI6 Wakeup            */
+#define LL_DMAMUX2_SYNC_COMP1_OUT         0x0C000000U   /*!< DMAMUX2 synchronization Signal is Comparator 1 output    */
+#define LL_DMAMUX2_SYNC_RTC_WKUP          0x0D000000U   /*!< DMAMUX2 synchronization Signal is RTC Wakeup             */
+#define LL_DMAMUX2_SYNC_EXTI0             0x0E000000U   /*!< DMAMUX2 synchronization Signal is EXTI0 IT               */
+#define LL_DMAMUX2_SYNC_EXTI2             0x0F000000U   /*!< DMAMUX2 synchronization Signal is EXTI2 IT               */
+
+/**
+  * @}
+  */
+
+/** @defgroup DMAMUX_LL_EC_REQUEST_GENERATOR Request Generator Channel
+  * @{
+  */
+#define LL_DMAMUX_REQ_GEN_0           0x00000000U
+#define LL_DMAMUX_REQ_GEN_1           0x00000001U
+#define LL_DMAMUX_REQ_GEN_2           0x00000002U
+#define LL_DMAMUX_REQ_GEN_3           0x00000003U
+#define LL_DMAMUX_REQ_GEN_4           0x00000004U
+#define LL_DMAMUX_REQ_GEN_5           0x00000005U
+#define LL_DMAMUX_REQ_GEN_6           0x00000006U
+#define LL_DMAMUX_REQ_GEN_7           0x00000007U
+/**
+  * @}
+  */
+
+/** @defgroup DMAMUX_LL_EC_REQUEST_GEN_POLARITY External Request Signal Generation Polarity
+  * @{
+  */
+#define LL_DMAMUX_REQ_GEN_NO_EVENT             0x00000000U                                  /*!< No external DMA request  generation                        */
+#define LL_DMAMUX_REQ_GEN_POL_RISING           DMAMUX_RGxCR_GPOL_0                          /*!< External DMA request generation on event on rising edge    */
+#define LL_DMAMUX_REQ_GEN_POL_FALLING          DMAMUX_RGxCR_GPOL_1                          /*!< External DMA request generation on event on falling edge   */
+#define LL_DMAMUX_REQ_GEN_POL_RISING_FALLING   (DMAMUX_RGxCR_GPOL_0 | DMAMUX_RGxCR_GPOL_1)  /*!< External DMA request generation on rising and falling edge */
+/**
+  * @}
+  */
+
+/** @defgroup DMAMUX_LL_EC_REQUEST_GEN External Request Signal Generation
+  * @{
+  */
+#define LL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT   0U   /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel0 Event        */
+#define LL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT   1U   /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel1 Event        */
+#define LL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT   2U   /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel2 Event        */
+#define LL_DMAMUX1_REQ_GEN_LPTIM1_OUT        3U   /*!< DMAMUX1 Request generator Signal is LPTIM1 OUT                    */
+#define LL_DMAMUX1_REQ_GEN_LPTIM2_OUT        4U   /*!< DMAMUX1 Request generator Signal is LPTIM2 OUT                    */
+#define LL_DMAMUX1_REQ_GEN_LPTIM3_OUT        5U   /*!< DMAMUX1 Request generator Signal is LPTIM3 OUT                    */
+#define LL_DMAMUX1_REQ_GEN_EXTI0             6U   /*!< DMAMUX1 Request generator Signal is EXTI0 IT                      */
+#define LL_DMAMUX1_REQ_GEN_TIM12_TRGO        7U   /*!< DMAMUX1 Request generator Signal is TIM12 TRGO                    */
+
+#define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT   0U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel0 Event        */
+#define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT   1U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel1 Event        */
+#define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT   2U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel2 Event        */
+#define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT   3U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel3 Event        */
+#define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT   4U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel4 Event        */
+#define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT   5U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel5 Event        */
+#define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT   6U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel6 Event        */
+#define LL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP   7U   /*!< DMAMUX2 Request generator Signal is LPUART1 RX Wakeup             */
+#define LL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP   8U   /*!< DMAMUX2 Request generator Signal is LPUART1 TX Wakeup             */
+#define LL_DMAMUX2_REQ_GEN_LPTIM2_WKUP       9U   /*!< DMAMUX2 Request generator Signal is LPTIM2 Wakeup                 */
+#define LL_DMAMUX2_REQ_GEN_LPTIM2_OUT       10U   /*!< DMAMUX2 Request generator Signal is LPTIM2 OUT                    */
+#define LL_DMAMUX2_REQ_GEN_LPTIM3_WKUP      11U   /*!< DMAMUX2 Request generator Signal is LPTIM3 Wakeup                 */
+#define LL_DMAMUX2_REQ_GEN_LPTIM3_OUT       12U   /*!< DMAMUX2 Request generator Signal is LPTIM3 OUT                    */
+#if defined (LPTIM4)
+#define LL_DMAMUX2_REQ_GEN_LPTIM4_WKUP      13U   /*!< DMAMUX2 Request generator Signal is LPTIM4 Wakeup                 */
+#endif /* LPTIM4 */
+#if defined (LPTIM5)
+#define LL_DMAMUX2_REQ_GEN_LPTIM5_WKUP      14U   /*!< DMAMUX2 Request generator Signal is LPTIM5 Wakeup                 */
+#endif /* LPTIM5 */
+#define LL_DMAMUX2_REQ_GEN_I2C4_WKUP        15U   /*!< DMAMUX2 Request generator Signal is I2C4 Wakeup                   */
+#define LL_DMAMUX2_REQ_GEN_SPI6_WKUP        16U   /*!< DMAMUX2 Request generator Signal is SPI6 Wakeup                   */
+#define LL_DMAMUX2_REQ_GEN_COMP1_OUT        17U   /*!< DMAMUX2 Request generator Signal is Comparator 1 output           */
+#define LL_DMAMUX2_REQ_GEN_COMP2_OUT        18U   /*!< DMAMUX2 Request generator Signal is Comparator 2 output           */
+#define LL_DMAMUX2_REQ_GEN_RTC_WKUP         19U   /*!< DMAMUX2 Request generator Signal is RTC Wakeup                    */
+#define LL_DMAMUX2_REQ_GEN_EXTI0            20U   /*!< DMAMUX2 Request generator Signal is EXTI0                         */
+#define LL_DMAMUX2_REQ_GEN_EXTI2            21U   /*!< DMAMUX2 Request generator Signal is EXTI2                         */
+#define LL_DMAMUX2_REQ_GEN_I2C4_IT_EVT      22U   /*!< DMAMUX2 Request generator Signal is I2C4 IT Event                 */
+#define LL_DMAMUX2_REQ_GEN_SPI6_IT          23U   /*!< DMAMUX2 Request generator Signal is SPI6 IT                       */
+#define LL_DMAMUX2_REQ_GEN_LPUART1_TX_IT    24U   /*!< DMAMUX2 Request generator Signal is LPUART1 Tx IT                 */
+#define LL_DMAMUX2_REQ_GEN_LPUART1_RX_IT    25U   /*!< DMAMUX2 Request generator Signal is LPUART1 Rx IT                 */
+#if defined (ADC3)
+#define LL_DMAMUX2_REQ_GEN_ADC3_IT          26U   /*!< DMAMUX2 Request generator Signal is ADC3 IT                       */
+#define LL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT    27U   /*!< DMAMUX2 Request generator Signal is ADC3 Analog Watchdog 1 output */
+#endif /* ADC3 */
+#define LL_DMAMUX2_REQ_GEN_BDMA_CH0_IT      28U   /*!< DMAMUX2 Request generator Signal is BDMA Channel 0 IT             */
+#define LL_DMAMUX2_REQ_GEN_BDMA_CH1_IT      29U   /*!< DMAMUX2 Request generator Signal is BDMA Channel 1 IT             */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup DMAMUX_LL_Exported_Macros DMAMUX Exported Macros
+  * @{
+  */
+
+/** @defgroup DMAMUX_LL_EM_WRITE_READ Common Write and read registers macros
+  * @{
+  */
+/**
+  * @brief  Write a value in DMAMUX register
+  * @param  __INSTANCE__ DMAMUX Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_DMAMUX_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in DMAMUX register
+  * @param  __INSTANCE__ DMAMUX Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_DMAMUX_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup DMAMUX_LL_Exported_Functions DMAMUX Exported Functions
+ * @{
+ */
+
+/** @defgroup DMAMUX_LL_EF_Configuration Configuration
+  * @{
+  */
+/**
+  * @brief  Set DMAMUX request ID for DMAMUX Channel x.
+  * @note   DMAMUX1 channel 0 to 7 are mapped to DMA1 channel 0 to 7.
+  *         DMAMUX1 channel 8 to 15 are mapped to DMA2 channel 0 to 7.
+  *         DMAMUX2 channel 0 to 7 are mapped to  BDMA channel 0 to 7.
+  * @rmtoll CxCR         DMAREQ_ID     LL_DMAMUX_SetRequestID
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_CHANNEL_0
+  *         @arg @ref LL_DMAMUX_CHANNEL_1
+  *         @arg @ref LL_DMAMUX_CHANNEL_2
+  *         @arg @ref LL_DMAMUX_CHANNEL_3
+  *         @arg @ref LL_DMAMUX_CHANNEL_4
+  *         @arg @ref LL_DMAMUX_CHANNEL_5
+  *         @arg @ref LL_DMAMUX_CHANNEL_6
+  *         @arg @ref LL_DMAMUX_CHANNEL_7
+  *         @arg @ref LL_DMAMUX_CHANNEL_8
+  *         @arg @ref LL_DMAMUX_CHANNEL_9
+  *         @arg @ref LL_DMAMUX_CHANNEL_10
+  *         @arg @ref LL_DMAMUX_CHANNEL_11
+  *         @arg @ref LL_DMAMUX_CHANNEL_12
+  *         @arg @ref LL_DMAMUX_CHANNEL_13
+  *         @arg @ref LL_DMAMUX_CHANNEL_14
+  *         @arg @ref LL_DMAMUX_CHANNEL_15
+  * @param  Request This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX1_REQ_MEM2MEM
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR0
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR1
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR2
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR3
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR4
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR5
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR6
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR7
+  *         @arg @ref LL_DMAMUX1_REQ_ADC1
+  *         @arg @ref LL_DMAMUX1_REQ_ADC2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH4
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_TRIG
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_COM
+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH4
+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH4
+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_TRIG
+  *         @arg @ref LL_DMAMUX1_REQ_TIM4_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM4_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM4_CH3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM4_UP
+  *         @arg @ref LL_DMAMUX1_REQ_I2C1_RX
+  *         @arg @ref LL_DMAMUX1_REQ_I2C1_TX
+  *         @arg @ref LL_DMAMUX1_REQ_I2C2_RX
+  *         @arg @ref LL_DMAMUX1_REQ_I2C2_TX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI1_RX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI1_TX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI2_RX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI2_TX
+  *         @arg @ref LL_DMAMUX1_REQ_USART1_RX
+  *         @arg @ref LL_DMAMUX1_REQ_USART1_TX
+  *         @arg @ref LL_DMAMUX1_REQ_USART2_RX
+  *         @arg @ref LL_DMAMUX1_REQ_USART2_TX
+  *         @arg @ref LL_DMAMUX1_REQ_USART3_RX
+  *         @arg @ref LL_DMAMUX1_REQ_USART3_TX
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH4
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_TRIG
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_COM
+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH4
+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_TRIG
+  *         @arg @ref LL_DMAMUX1_REQ_SPI3_RX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI3_TX
+  *         @arg @ref LL_DMAMUX1_REQ_UART4_RX
+  *         @arg @ref LL_DMAMUX1_REQ_UART4_TX
+  *         @arg @ref LL_DMAMUX1_REQ_UART5_RX
+  *         @arg @ref LL_DMAMUX1_REQ_UART5_TX
+  *         @arg @ref LL_DMAMUX1_REQ_DAC1_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_DAC1_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM6_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM7_UP
+  *         @arg @ref LL_DMAMUX1_REQ_USART6_RX
+  *         @arg @ref LL_DMAMUX1_REQ_USART6_TX
+  *         @arg @ref LL_DMAMUX1_REQ_I2C3_RX
+  *         @arg @ref LL_DMAMUX1_REQ_I2C3_TX
+  *         @arg @ref LL_DMAMUX1_REQ_DCMI_PSSI (*)
+  *         @arg @ref LL_DMAMUX1_REQ_CRYP_IN
+  *         @arg @ref LL_DMAMUX1_REQ_CRYP_OUT
+  *         @arg @ref LL_DMAMUX1_REQ_HASH_IN
+  *         @arg @ref LL_DMAMUX1_REQ_UART7_RX
+  *         @arg @ref LL_DMAMUX1_REQ_UART7_TX
+  *         @arg @ref LL_DMAMUX1_REQ_UART8_RX
+  *         @arg @ref LL_DMAMUX1_REQ_UART8_TX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI4_RX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI4_TX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI5_RX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI5_TX
+  *         @arg @ref LL_DMAMUX1_REQ_SAI1_A
+  *         @arg @ref LL_DMAMUX1_REQ_SAI1_B
+  *         @arg @ref LL_DMAMUX1_REQ_SAI2_A (*)
+  *         @arg @ref LL_DMAMUX1_REQ_SAI2_B (*)
+  *         @arg @ref LL_DMAMUX1_REQ_SWPMI_RX
+  *         @arg @ref LL_DMAMUX1_REQ_SWPMI_TX
+  *         @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_DT
+  *         @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_CS
+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_MASTER (*)
+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_A (*)
+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_B (*)
+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_C (*)
+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_D (*)
+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_E (*)
+  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT0
+  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT1
+  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT2
+  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM15_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM15_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM15_TRIG
+  *         @arg @ref LL_DMAMUX1_REQ_TIM15_COM
+  *         @arg @ref LL_DMAMUX1_REQ_TIM16_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM16_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM17_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM17_UP
+  *         @arg @ref LL_DMAMUX1_REQ_SAI3_A (*)
+  *         @arg @ref LL_DMAMUX1_REQ_SAI3_B (*)
+  *         @arg @ref LL_DMAMUX1_REQ_ADC3 (*)
+  *         @arg @ref LL_DMAMUX1_REQ_UART9_RX (*)
+  *         @arg @ref LL_DMAMUX1_REQ_UART9_TX (*)
+  *         @arg @ref LL_DMAMUX1_REQ_USART10_RX (*)
+  *         @arg @ref LL_DMAMUX1_REQ_USART10_TX (*)
+  *         @arg @ref LL_DMAMUX1_REQ_FMAC_READ  (*)
+  *         @arg @ref LL_DMAMUX1_REQ_FMAC_WRITE (*)
+  *         @arg @ref LL_DMAMUX1_REQ_CORDIC_READ (*)
+  *         @arg @ref LL_DMAMUX1_REQ_CORDIC_WRITE(*)
+  *         @arg @ref LL_DMAMUX1_REQ_I2C5_RX     (*)
+  *         @arg @ref LL_DMAMUX1_REQ_I2C5_TX     (*)
+  *         @arg @ref LL_DMAMUX1_REQ_TIM23_CH1   (*)
+  *         @arg @ref LL_DMAMUX1_REQ_TIM23_CH2   (*)
+  *         @arg @ref LL_DMAMUX1_REQ_TIM23_CH3   (*)
+  *         @arg @ref LL_DMAMUX1_REQ_TIM23_CH4   (*)
+  *         @arg @ref LL_DMAMUX1_REQ_TIM23_UP    (*)
+  *         @arg @ref LL_DMAMUX1_REQ_TIM23_TRIG  (*)
+  *         @arg @ref LL_DMAMUX1_REQ_TIM24_CH1   (*)
+  *         @arg @ref LL_DMAMUX1_REQ_TIM24_CH2   (*)
+  *         @arg @ref LL_DMAMUX1_REQ_TIM24_CH3   (*)
+  *         @arg @ref LL_DMAMUX1_REQ_TIM24_CH4   (*)
+  *         @arg @ref LL_DMAMUX1_REQ_TIM24_UP    (*)
+  *         @arg @ref LL_DMAMUX1_REQ_TIM24_TRIG  (*)
+  *         @arg @ref LL_DMAMUX2_REQ_MEM2MEM
+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR0
+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR1
+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR2
+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR3
+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR4
+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR5
+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR6
+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR7
+  *         @arg @ref LL_DMAMUX2_REQ_LPUART1_RX
+  *         @arg @ref LL_DMAMUX2_REQ_LPUART1_TX
+  *         @arg @ref LL_DMAMUX2_REQ_SPI6_RX
+  *         @arg @ref LL_DMAMUX2_REQ_SPI6_TX
+  *         @arg @ref LL_DMAMUX2_REQ_I2C4_RX
+  *         @arg @ref LL_DMAMUX2_REQ_I2C4_TX
+  *         @arg @ref LL_DMAMUX2_REQ_SAI4_A (*)
+  *         @arg @ref LL_DMAMUX2_REQ_SAI4_B (*)
+  *         @arg @ref LL_DMAMUX2_REQ_ADC3 (*)
+  *         @arg @ref LL_DMAMUX2_REQ_DAC2_CH1 (*)
+  *         @arg @ref LL_DMAMUX2_REQ_DFSDM2_FLT0 (*)
+  *
+  * @note   (*) Availability depends on devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_SetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Request)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  MODIFY_REG(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_DMAREQ_ID, Request);
+}
+
+/**
+  * @brief  Get DMAMUX request ID for DMAMUX Channel x.
+  * @note   DMAMUX1 channel 0 to 7  are mapped to DMA1 channel 0 to 7.
+  *         DMAMUX1 channel 8 to 15 are mapped to DMA2 channel 0 to 7.
+  *         DMAMUX2 channel 0 to 7  are mapped to BDMA channel 0 to 7.
+  * @rmtoll CxCR         DMAREQ_ID     LL_DMAMUX_GetRequestID
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_CHANNEL_0
+  *         @arg @ref LL_DMAMUX_CHANNEL_1
+  *         @arg @ref LL_DMAMUX_CHANNEL_2
+  *         @arg @ref LL_DMAMUX_CHANNEL_3
+  *         @arg @ref LL_DMAMUX_CHANNEL_4
+  *         @arg @ref LL_DMAMUX_CHANNEL_5
+  *         @arg @ref LL_DMAMUX_CHANNEL_6
+  *         @arg @ref LL_DMAMUX_CHANNEL_7
+  *         @arg @ref LL_DMAMUX_CHANNEL_8
+  *         @arg @ref LL_DMAMUX_CHANNEL_9
+  *         @arg @ref LL_DMAMUX_CHANNEL_10
+  *         @arg @ref LL_DMAMUX_CHANNEL_11
+  *         @arg @ref LL_DMAMUX_CHANNEL_12
+  *         @arg @ref LL_DMAMUX_CHANNEL_13
+  *         @arg @ref LL_DMAMUX_CHANNEL_14
+  *         @arg @ref LL_DMAMUX_CHANNEL_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMAMUX1_REQ_MEM2MEM
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR0
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR1
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR2
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR3
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR4
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR5
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR6
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR7
+  *         @arg @ref LL_DMAMUX1_REQ_ADC1
+  *         @arg @ref LL_DMAMUX1_REQ_ADC2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH4
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_TRIG
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_COM
+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH4
+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH4
+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_TRIG
+  *         @arg @ref LL_DMAMUX1_REQ_TIM4_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM4_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM4_CH3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM4_UP
+  *         @arg @ref LL_DMAMUX1_REQ_I2C1_RX
+  *         @arg @ref LL_DMAMUX1_REQ_I2C1_TX
+  *         @arg @ref LL_DMAMUX1_REQ_I2C2_RX
+  *         @arg @ref LL_DMAMUX1_REQ_I2C2_TX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI1_RX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI1_TX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI2_RX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI2_TX
+  *         @arg @ref LL_DMAMUX1_REQ_USART1_RX
+  *         @arg @ref LL_DMAMUX1_REQ_USART1_TX
+  *         @arg @ref LL_DMAMUX1_REQ_USART2_RX
+  *         @arg @ref LL_DMAMUX1_REQ_USART2_TX
+  *         @arg @ref LL_DMAMUX1_REQ_USART3_RX
+  *         @arg @ref LL_DMAMUX1_REQ_USART3_TX
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH4
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_TRIG
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_COM
+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH4
+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_TRIG
+  *         @arg @ref LL_DMAMUX1_REQ_SPI3_RX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI3_TX
+  *         @arg @ref LL_DMAMUX1_REQ_UART4_RX
+  *         @arg @ref LL_DMAMUX1_REQ_UART4_TX
+  *         @arg @ref LL_DMAMUX1_REQ_UART5_RX
+  *         @arg @ref LL_DMAMUX1_REQ_UART5_TX
+  *         @arg @ref LL_DMAMUX1_REQ_DAC1_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_DAC1_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM6_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM7_UP
+  *         @arg @ref LL_DMAMUX1_REQ_USART6_RX
+  *         @arg @ref LL_DMAMUX1_REQ_USART6_TX
+  *         @arg @ref LL_DMAMUX1_REQ_I2C3_RX
+  *         @arg @ref LL_DMAMUX1_REQ_I2C3_TX
+  *         @arg @ref LL_DMAMUX1_REQ_DCMI_PSSI (*)
+  *         @arg @ref LL_DMAMUX1_REQ_CRYP_IN
+  *         @arg @ref LL_DMAMUX1_REQ_CRYP_OUT
+  *         @arg @ref LL_DMAMUX1_REQ_HASH_IN
+  *         @arg @ref LL_DMAMUX1_REQ_UART7_RX
+  *         @arg @ref LL_DMAMUX1_REQ_UART7_TX
+  *         @arg @ref LL_DMAMUX1_REQ_UART8_RX
+  *         @arg @ref LL_DMAMUX1_REQ_UART8_TX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI4_RX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI4_TX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI5_RX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI5_TX
+  *         @arg @ref LL_DMAMUX1_REQ_SAI1_A
+  *         @arg @ref LL_DMAMUX1_REQ_SAI1_B
+  *         @arg @ref LL_DMAMUX1_REQ_SAI2_A (*)
+  *         @arg @ref LL_DMAMUX1_REQ_SAI2_B (*)
+  *         @arg @ref LL_DMAMUX1_REQ_SWPMI_RX
+  *         @arg @ref LL_DMAMUX1_REQ_SWPMI_TX
+  *         @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_DT
+  *         @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_CS
+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_MASTER (*)
+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_A (*)
+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_B (*)
+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_C (*)
+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_D (*)
+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_E (*)
+  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT0
+  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT1
+  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT2
+  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM15_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM15_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM15_TRIG
+  *         @arg @ref LL_DMAMUX1_REQ_TIM15_COM
+  *         @arg @ref LL_DMAMUX1_REQ_TIM16_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM16_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM17_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM17_UP
+  *         @arg @ref LL_DMAMUX1_REQ_SAI3_A (*)
+  *         @arg @ref LL_DMAMUX1_REQ_SAI3_B (*)
+  *         @arg @ref LL_DMAMUX1_REQ_ADC3 (*)
+  *         @arg @ref LL_DMAMUX1_REQ_UART9_RX (*)
+  *         @arg @ref LL_DMAMUX1_REQ_UART9_TX (*)
+  *         @arg @ref LL_DMAMUX1_REQ_USART10_RX (*)
+  *         @arg @ref LL_DMAMUX1_REQ_USART10_TX (*)
+  *         @arg @ref LL_DMAMUX1_REQ_FMAC_READ  (*)
+  *         @arg @ref LL_DMAMUX1_REQ_FMAC_WRITE (*)
+  *         @arg @ref LL_DMAMUX1_REQ_CORDIC_READ (*)
+  *         @arg @ref LL_DMAMUX1_REQ_CORDIC_WRITE(*)
+  *         @arg @ref LL_DMAMUX1_REQ_I2C5_RX     (*)
+  *         @arg @ref LL_DMAMUX1_REQ_I2C5_TX     (*)
+  *         @arg @ref LL_DMAMUX1_REQ_TIM23_CH1   (*)
+  *         @arg @ref LL_DMAMUX1_REQ_TIM23_CH2   (*)
+  *         @arg @ref LL_DMAMUX1_REQ_TIM23_CH3   (*)
+  *         @arg @ref LL_DMAMUX1_REQ_TIM23_CH4   (*)
+  *         @arg @ref LL_DMAMUX1_REQ_TIM23_UP    (*)
+  *         @arg @ref LL_DMAMUX1_REQ_TIM23_TRIG  (*)
+  *         @arg @ref LL_DMAMUX1_REQ_TIM24_CH1   (*)
+  *         @arg @ref LL_DMAMUX1_REQ_TIM24_CH2   (*)
+  *         @arg @ref LL_DMAMUX1_REQ_TIM24_CH3   (*)
+  *         @arg @ref LL_DMAMUX1_REQ_TIM24_CH4   (*)
+  *         @arg @ref LL_DMAMUX1_REQ_TIM24_UP    (*)
+  *         @arg @ref LL_DMAMUX1_REQ_TIM24_TRIG  (*)
+  *         @arg @ref LL_DMAMUX2_REQ_MEM2MEM
+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR0
+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR1
+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR2
+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR3
+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR4
+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR5
+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR6
+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR7
+  *         @arg @ref LL_DMAMUX2_REQ_LPUART1_RX
+  *         @arg @ref LL_DMAMUX2_REQ_LPUART1_TX
+  *         @arg @ref LL_DMAMUX2_REQ_SPI6_RX
+  *         @arg @ref LL_DMAMUX2_REQ_SPI6_TX
+  *         @arg @ref LL_DMAMUX2_REQ_I2C4_RX
+  *         @arg @ref LL_DMAMUX2_REQ_I2C4_TX
+  *         @arg @ref LL_DMAMUX2_REQ_SAI4_A (*)
+  *         @arg @ref LL_DMAMUX2_REQ_SAI4_B (*)
+  *         @arg @ref LL_DMAMUX2_REQ_ADC3 (*)
+  *         @arg @ref LL_DMAMUX2_REQ_DAC2_CH1 (*)
+  *         @arg @ref LL_DMAMUX2_REQ_DFSDM2_FLT0 (*)
+  *
+  * @note   (*) Availability depends on devices.
+  * @retval None
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_DMAREQ_ID));
+}
+
+/**
+  * @brief  Set the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event.
+  * @rmtoll CxCR         NBREQ         LL_DMAMUX_SetSyncRequestNb
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_CHANNEL_0
+  *         @arg @ref LL_DMAMUX_CHANNEL_1
+  *         @arg @ref LL_DMAMUX_CHANNEL_2
+  *         @arg @ref LL_DMAMUX_CHANNEL_3
+  *         @arg @ref LL_DMAMUX_CHANNEL_4
+  *         @arg @ref LL_DMAMUX_CHANNEL_5
+  *         @arg @ref LL_DMAMUX_CHANNEL_6
+  *         @arg @ref LL_DMAMUX_CHANNEL_7
+  *         @arg @ref LL_DMAMUX_CHANNEL_8
+  *         @arg @ref LL_DMAMUX_CHANNEL_9
+  *         @arg @ref LL_DMAMUX_CHANNEL_10
+  *         @arg @ref LL_DMAMUX_CHANNEL_11
+  *         @arg @ref LL_DMAMUX_CHANNEL_12
+  *         @arg @ref LL_DMAMUX_CHANNEL_13
+  *         @arg @ref LL_DMAMUX_CHANNEL_14
+  *         @arg @ref LL_DMAMUX_CHANNEL_15
+  * @param  RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32.
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t RequestNb)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  MODIFY_REG(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_NBREQ, (RequestNb - 1U) << DMAMUX_CxCR_NBREQ_Pos);
+}
+
+/**
+  * @brief  Get the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event.
+  * @rmtoll CxCR         NBREQ         LL_DMAMUX_GetSyncRequestNb
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_CHANNEL_0
+  *         @arg @ref LL_DMAMUX_CHANNEL_1
+  *         @arg @ref LL_DMAMUX_CHANNEL_2
+  *         @arg @ref LL_DMAMUX_CHANNEL_3
+  *         @arg @ref LL_DMAMUX_CHANNEL_4
+  *         @arg @ref LL_DMAMUX_CHANNEL_5
+  *         @arg @ref LL_DMAMUX_CHANNEL_6
+  *         @arg @ref LL_DMAMUX_CHANNEL_7
+  *         @arg @ref LL_DMAMUX_CHANNEL_8
+  *         @arg @ref LL_DMAMUX_CHANNEL_9
+  *         @arg @ref LL_DMAMUX_CHANNEL_10
+  *         @arg @ref LL_DMAMUX_CHANNEL_11
+  *         @arg @ref LL_DMAMUX_CHANNEL_12
+  *         @arg @ref LL_DMAMUX_CHANNEL_13
+  *         @arg @ref LL_DMAMUX_CHANNEL_14
+  *         @arg @ref LL_DMAMUX_CHANNEL_15
+  * @retval Between Min_Data = 1 and Max_Data = 32
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return (uint32_t)((READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_NBREQ) >> DMAMUX_CxCR_NBREQ_Pos) + 1U);
+}
+
+/**
+  * @brief  Set the polarity of the signal on which the DMA request is synchronized.
+  * @rmtoll CxCR         SPOL          LL_DMAMUX_SetSyncPolarity
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_CHANNEL_0
+  *         @arg @ref LL_DMAMUX_CHANNEL_1
+  *         @arg @ref LL_DMAMUX_CHANNEL_2
+  *         @arg @ref LL_DMAMUX_CHANNEL_3
+  *         @arg @ref LL_DMAMUX_CHANNEL_4
+  *         @arg @ref LL_DMAMUX_CHANNEL_5
+  *         @arg @ref LL_DMAMUX_CHANNEL_6
+  *         @arg @ref LL_DMAMUX_CHANNEL_7
+  *         @arg @ref LL_DMAMUX_CHANNEL_8
+  *         @arg @ref LL_DMAMUX_CHANNEL_9
+  *         @arg @ref LL_DMAMUX_CHANNEL_10
+  *         @arg @ref LL_DMAMUX_CHANNEL_11
+  *         @arg @ref LL_DMAMUX_CHANNEL_12
+  *         @arg @ref LL_DMAMUX_CHANNEL_13
+  *         @arg @ref LL_DMAMUX_CHANNEL_14
+  *         @arg @ref LL_DMAMUX_CHANNEL_15
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_SYNC_NO_EVENT
+  *         @arg @ref LL_DMAMUX_SYNC_POL_RISING
+  *         @arg @ref LL_DMAMUX_SYNC_POL_FALLING
+  *         @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Polarity)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  MODIFY_REG(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SPOL, Polarity);
+}
+
+/**
+  * @brief  Get the polarity of the signal on which the DMA request is synchronized.
+  * @rmtoll CxCR         SPOL          LL_DMAMUX_GetSyncPolarity
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_CHANNEL_0
+  *         @arg @ref LL_DMAMUX_CHANNEL_1
+  *         @arg @ref LL_DMAMUX_CHANNEL_2
+  *         @arg @ref LL_DMAMUX_CHANNEL_3
+  *         @arg @ref LL_DMAMUX_CHANNEL_4
+  *         @arg @ref LL_DMAMUX_CHANNEL_5
+  *         @arg @ref LL_DMAMUX_CHANNEL_6
+  *         @arg @ref LL_DMAMUX_CHANNEL_7
+  *         @arg @ref LL_DMAMUX_CHANNEL_8
+  *         @arg @ref LL_DMAMUX_CHANNEL_9
+  *         @arg @ref LL_DMAMUX_CHANNEL_10
+  *         @arg @ref LL_DMAMUX_CHANNEL_11
+  *         @arg @ref LL_DMAMUX_CHANNEL_12
+  *         @arg @ref LL_DMAMUX_CHANNEL_13
+  *         @arg @ref LL_DMAMUX_CHANNEL_14
+  *         @arg @ref LL_DMAMUX_CHANNEL_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMAMUX_SYNC_NO_EVENT
+  *         @arg @ref LL_DMAMUX_SYNC_POL_RISING
+  *         @arg @ref LL_DMAMUX_SYNC_POL_FALLING
+  *         @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SPOL));
+}
+
+/**
+  * @brief  Enable the Event Generation on DMAMUX channel x.
+  * @rmtoll CxCR         EGE           LL_DMAMUX_EnableEventGeneration
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_CHANNEL_0
+  *         @arg @ref LL_DMAMUX_CHANNEL_1
+  *         @arg @ref LL_DMAMUX_CHANNEL_2
+  *         @arg @ref LL_DMAMUX_CHANNEL_3
+  *         @arg @ref LL_DMAMUX_CHANNEL_4
+  *         @arg @ref LL_DMAMUX_CHANNEL_5
+  *         @arg @ref LL_DMAMUX_CHANNEL_6
+  *         @arg @ref LL_DMAMUX_CHANNEL_7
+  *         @arg @ref LL_DMAMUX_CHANNEL_8
+  *         @arg @ref LL_DMAMUX_CHANNEL_9
+  *         @arg @ref LL_DMAMUX_CHANNEL_10
+  *         @arg @ref LL_DMAMUX_CHANNEL_11
+  *         @arg @ref LL_DMAMUX_CHANNEL_12
+  *         @arg @ref LL_DMAMUX_CHANNEL_13
+  *         @arg @ref LL_DMAMUX_CHANNEL_14
+  *         @arg @ref LL_DMAMUX_CHANNEL_15
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_EGE);
+}
+
+/**
+  * @brief  Disable the Event Generation on DMAMUX channel x.
+  * @rmtoll CxCR         EGE           LL_DMAMUX_DisableEventGeneration
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_CHANNEL_0
+  *         @arg @ref LL_DMAMUX_CHANNEL_1
+  *         @arg @ref LL_DMAMUX_CHANNEL_2
+  *         @arg @ref LL_DMAMUX_CHANNEL_3
+  *         @arg @ref LL_DMAMUX_CHANNEL_4
+  *         @arg @ref LL_DMAMUX_CHANNEL_5
+  *         @arg @ref LL_DMAMUX_CHANNEL_6
+  *         @arg @ref LL_DMAMUX_CHANNEL_7
+  *         @arg @ref LL_DMAMUX_CHANNEL_8
+  *         @arg @ref LL_DMAMUX_CHANNEL_9
+  *         @arg @ref LL_DMAMUX_CHANNEL_10
+  *         @arg @ref LL_DMAMUX_CHANNEL_11
+  *         @arg @ref LL_DMAMUX_CHANNEL_12
+  *         @arg @ref LL_DMAMUX_CHANNEL_13
+  *         @arg @ref LL_DMAMUX_CHANNEL_14
+  *         @arg @ref LL_DMAMUX_CHANNEL_15
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  CLEAR_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_EGE);
+}
+
+/**
+  * @brief  Check if the Event Generation on DMAMUX channel x is enabled or disabled.
+  * @rmtoll CxCR         EGE           LL_DMAMUX_IsEnabledEventGeneration
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_CHANNEL_0
+  *         @arg @ref LL_DMAMUX_CHANNEL_1
+  *         @arg @ref LL_DMAMUX_CHANNEL_2
+  *         @arg @ref LL_DMAMUX_CHANNEL_3
+  *         @arg @ref LL_DMAMUX_CHANNEL_4
+  *         @arg @ref LL_DMAMUX_CHANNEL_5
+  *         @arg @ref LL_DMAMUX_CHANNEL_6
+  *         @arg @ref LL_DMAMUX_CHANNEL_7
+  *         @arg @ref LL_DMAMUX_CHANNEL_8
+  *         @arg @ref LL_DMAMUX_CHANNEL_9
+  *         @arg @ref LL_DMAMUX_CHANNEL_10
+  *         @arg @ref LL_DMAMUX_CHANNEL_11
+  *         @arg @ref LL_DMAMUX_CHANNEL_12
+  *         @arg @ref LL_DMAMUX_CHANNEL_13
+  *         @arg @ref LL_DMAMUX_CHANNEL_14
+  *         @arg @ref LL_DMAMUX_CHANNEL_15
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_EGE) == (DMAMUX_CxCR_EGE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the synchronization mode.
+  * @rmtoll CxCR         SE            LL_DMAMUX_EnableSync
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_CHANNEL_0
+  *         @arg @ref LL_DMAMUX_CHANNEL_1
+  *         @arg @ref LL_DMAMUX_CHANNEL_2
+  *         @arg @ref LL_DMAMUX_CHANNEL_3
+  *         @arg @ref LL_DMAMUX_CHANNEL_4
+  *         @arg @ref LL_DMAMUX_CHANNEL_5
+  *         @arg @ref LL_DMAMUX_CHANNEL_6
+  *         @arg @ref LL_DMAMUX_CHANNEL_7
+  *         @arg @ref LL_DMAMUX_CHANNEL_8
+  *         @arg @ref LL_DMAMUX_CHANNEL_9
+  *         @arg @ref LL_DMAMUX_CHANNEL_10
+  *         @arg @ref LL_DMAMUX_CHANNEL_11
+  *         @arg @ref LL_DMAMUX_CHANNEL_12
+  *         @arg @ref LL_DMAMUX_CHANNEL_13
+  *         @arg @ref LL_DMAMUX_CHANNEL_14
+  *         @arg @ref LL_DMAMUX_CHANNEL_15
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_EnableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SE);
+}
+
+/**
+  * @brief  Disable the synchronization mode.
+  * @rmtoll CxCR         SE            LL_DMAMUX_DisableSync
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_CHANNEL_0
+  *         @arg @ref LL_DMAMUX_CHANNEL_1
+  *         @arg @ref LL_DMAMUX_CHANNEL_2
+  *         @arg @ref LL_DMAMUX_CHANNEL_3
+  *         @arg @ref LL_DMAMUX_CHANNEL_4
+  *         @arg @ref LL_DMAMUX_CHANNEL_5
+  *         @arg @ref LL_DMAMUX_CHANNEL_6
+  *         @arg @ref LL_DMAMUX_CHANNEL_7
+  *         @arg @ref LL_DMAMUX_CHANNEL_8
+  *         @arg @ref LL_DMAMUX_CHANNEL_9
+  *         @arg @ref LL_DMAMUX_CHANNEL_10
+  *         @arg @ref LL_DMAMUX_CHANNEL_11
+  *         @arg @ref LL_DMAMUX_CHANNEL_12
+  *         @arg @ref LL_DMAMUX_CHANNEL_13
+  *         @arg @ref LL_DMAMUX_CHANNEL_14
+  *         @arg @ref LL_DMAMUX_CHANNEL_15
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_DisableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  CLEAR_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SE);
+}
+
+/**
+  * @brief  Check if the synchronization mode is enabled or disabled.
+  * @rmtoll CxCR         SE            LL_DMAMUX_IsEnabledSync
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_CHANNEL_0
+  *         @arg @ref LL_DMAMUX_CHANNEL_1
+  *         @arg @ref LL_DMAMUX_CHANNEL_2
+  *         @arg @ref LL_DMAMUX_CHANNEL_3
+  *         @arg @ref LL_DMAMUX_CHANNEL_4
+  *         @arg @ref LL_DMAMUX_CHANNEL_5
+  *         @arg @ref LL_DMAMUX_CHANNEL_6
+  *         @arg @ref LL_DMAMUX_CHANNEL_7
+  *         @arg @ref LL_DMAMUX_CHANNEL_8
+  *         @arg @ref LL_DMAMUX_CHANNEL_9
+  *         @arg @ref LL_DMAMUX_CHANNEL_10
+  *         @arg @ref LL_DMAMUX_CHANNEL_11
+  *         @arg @ref LL_DMAMUX_CHANNEL_12
+  *         @arg @ref LL_DMAMUX_CHANNEL_13
+  *         @arg @ref LL_DMAMUX_CHANNEL_14
+  *         @arg @ref LL_DMAMUX_CHANNEL_15
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SE) == (DMAMUX_CxCR_SE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set DMAMUX synchronization ID  on DMAMUX Channel x.
+  * @rmtoll CxCR         SYNC_ID       LL_DMAMUX_SetSyncID
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_CHANNEL_0
+  *         @arg @ref LL_DMAMUX_CHANNEL_1
+  *         @arg @ref LL_DMAMUX_CHANNEL_2
+  *         @arg @ref LL_DMAMUX_CHANNEL_3
+  *         @arg @ref LL_DMAMUX_CHANNEL_4
+  *         @arg @ref LL_DMAMUX_CHANNEL_5
+  *         @arg @ref LL_DMAMUX_CHANNEL_6
+  *         @arg @ref LL_DMAMUX_CHANNEL_7
+  *         @arg @ref LL_DMAMUX_CHANNEL_8
+  *         @arg @ref LL_DMAMUX_CHANNEL_9
+  *         @arg @ref LL_DMAMUX_CHANNEL_10
+  *         @arg @ref LL_DMAMUX_CHANNEL_11
+  *         @arg @ref LL_DMAMUX_CHANNEL_12
+  *         @arg @ref LL_DMAMUX_CHANNEL_13
+  *         @arg @ref LL_DMAMUX_CHANNEL_14
+  *         @arg @ref LL_DMAMUX_CHANNEL_15
+  * @param  SyncID This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT
+  *         @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT
+  *         @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT
+  *         @arg @ref LL_DMAMUX1_SYNC_LPTIM1_OUT
+  *         @arg @ref LL_DMAMUX1_SYNC_LPTIM2_OUT
+  *         @arg @ref LL_DMAMUX1_SYNC_LPTIM3_OUT
+  *         @arg @ref LL_DMAMUX1_SYNC_EXTI0
+  *         @arg @ref LL_DMAMUX1_SYNC_TIM12_TRGO
+  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT
+  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT
+  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT
+  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT
+  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT
+  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT
+  *         @arg @ref LL_DMAMUX2_SYNC_LPUART1_RX_WKUP
+  *         @arg @ref LL_DMAMUX2_SYNC_LPUART1_TX_WKUP
+  *         @arg @ref LL_DMAMUX2_SYNC_LPTIM2_OUT
+  *         @arg @ref LL_DMAMUX2_SYNC_LPTIM3_OUT
+  *         @arg @ref LL_DMAMUX2_SYNC_I2C4_WKUP
+  *         @arg @ref LL_DMAMUX2_SYNC_SPI6_WKUP
+  *         @arg @ref LL_DMAMUX2_SYNC_COMP1_OUT
+  *         @arg @ref LL_DMAMUX2_SYNC_RTC_WKUP
+  *         @arg @ref LL_DMAMUX2_SYNC_EXTI0
+  *         @arg @ref LL_DMAMUX2_SYNC_EXTI2
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_SetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t SyncID)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  MODIFY_REG(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SYNC_ID, SyncID);
+}
+
+/**
+  * @brief  Get DMAMUX synchronization ID  on DMAMUX Channel x.
+  * @rmtoll CxCR         SYNC_ID       LL_DMAMUX_GetSyncID
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_CHANNEL_0
+  *         @arg @ref LL_DMAMUX_CHANNEL_1
+  *         @arg @ref LL_DMAMUX_CHANNEL_2
+  *         @arg @ref LL_DMAMUX_CHANNEL_3
+  *         @arg @ref LL_DMAMUX_CHANNEL_4
+  *         @arg @ref LL_DMAMUX_CHANNEL_5
+  *         @arg @ref LL_DMAMUX_CHANNEL_6
+  *         @arg @ref LL_DMAMUX_CHANNEL_7
+  *         @arg @ref LL_DMAMUX_CHANNEL_8
+  *         @arg @ref LL_DMAMUX_CHANNEL_9
+  *         @arg @ref LL_DMAMUX_CHANNEL_10
+  *         @arg @ref LL_DMAMUX_CHANNEL_11
+  *         @arg @ref LL_DMAMUX_CHANNEL_12
+  *         @arg @ref LL_DMAMUX_CHANNEL_13
+  *         @arg @ref LL_DMAMUX_CHANNEL_14
+  *         @arg @ref LL_DMAMUX_CHANNEL_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT
+  *         @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT
+  *         @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT
+  *         @arg @ref LL_DMAMUX1_SYNC_LPTIM1_OUT
+  *         @arg @ref LL_DMAMUX1_SYNC_LPTIM2_OUT
+  *         @arg @ref LL_DMAMUX1_SYNC_LPTIM3_OUT
+  *         @arg @ref LL_DMAMUX1_SYNC_EXTI0
+  *         @arg @ref LL_DMAMUX1_SYNC_TIM12_TRGO
+  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT
+  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT
+  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT
+  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT
+  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT
+  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT
+  *         @arg @ref LL_DMAMUX2_SYNC_LPUART1_RX_WKUP
+  *         @arg @ref LL_DMAMUX2_SYNC_LPUART1_TX_WKUP
+  *         @arg @ref LL_DMAMUX2_SYNC_LPTIM2_OUT
+  *         @arg @ref LL_DMAMUX2_SYNC_LPTIM3_OUT
+  *         @arg @ref LL_DMAMUX2_SYNC_I2C4_WKUP
+  *         @arg @ref LL_DMAMUX2_SYNC_SPI6_WKUP
+  *         @arg @ref LL_DMAMUX2_SYNC_COMP1_OUT
+  *         @arg @ref LL_DMAMUX2_SYNC_RTC_WKUP
+  *         @arg @ref LL_DMAMUX2_SYNC_EXTI0
+  *         @arg @ref LL_DMAMUX2_SYNC_EXTI2
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SYNC_ID));
+}
+
+/**
+  * @brief  Enable the Request Generator.
+  * @rmtoll RGxCR        GE            LL_DMAMUX_EnableRequestGen
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  RequestGenChannel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_REQ_GEN_0
+  *         @arg @ref LL_DMAMUX_REQ_GEN_1
+  *         @arg @ref LL_DMAMUX_REQ_GEN_2
+  *         @arg @ref LL_DMAMUX_REQ_GEN_3
+  *         @arg @ref LL_DMAMUX_REQ_GEN_4
+  *         @arg @ref LL_DMAMUX_REQ_GEN_5
+  *         @arg @ref LL_DMAMUX_REQ_GEN_6
+  *         @arg @ref LL_DMAMUX_REQ_GEN_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_EnableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * (RequestGenChannel))))->RGCR, DMAMUX_RGxCR_GE);
+}
+
+/**
+  * @brief  Disable the Request Generator.
+  * @rmtoll RGxCR        GE            LL_DMAMUX_DisableRequestGen
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  RequestGenChannel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_REQ_GEN_0
+  *         @arg @ref LL_DMAMUX_REQ_GEN_1
+  *         @arg @ref LL_DMAMUX_REQ_GEN_2
+  *         @arg @ref LL_DMAMUX_REQ_GEN_3
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_DisableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  CLEAR_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * (RequestGenChannel))))->RGCR, DMAMUX_RGxCR_GE);
+}
+
+/**
+  * @brief  Check if the Request Generator is enabled or disabled.
+  * @rmtoll RGxCR        GE            LL_DMAMUX_IsEnabledRequestGen
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  RequestGenChannel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_REQ_GEN_0
+  *         @arg @ref LL_DMAMUX_REQ_GEN_1
+  *         @arg @ref LL_DMAMUX_REQ_GEN_2
+  *         @arg @ref LL_DMAMUX_REQ_GEN_3
+  *         @arg @ref LL_DMAMUX_REQ_GEN_4
+  *         @arg @ref LL_DMAMUX_REQ_GEN_5
+  *         @arg @ref LL_DMAMUX_REQ_GEN_6
+  *         @arg @ref LL_DMAMUX_REQ_GEN_7
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GE) == (DMAMUX_RGxCR_GE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the polarity of the signal on which the DMA request is generated.
+  * @rmtoll RGxCR        GPOL          LL_DMAMUX_SetRequestGenPolarity
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  RequestGenChannel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_REQ_GEN_0
+  *         @arg @ref LL_DMAMUX_REQ_GEN_1
+  *         @arg @ref LL_DMAMUX_REQ_GEN_2
+  *         @arg @ref LL_DMAMUX_REQ_GEN_3
+  *         @arg @ref LL_DMAMUX_REQ_GEN_4
+  *         @arg @ref LL_DMAMUX_REQ_GEN_5
+  *         @arg @ref LL_DMAMUX_REQ_GEN_6
+  *         @arg @ref LL_DMAMUX_REQ_GEN_7
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_REQ_GEN_NO_EVENT
+  *         @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING
+  *         @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING
+  *         @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t Polarity)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GPOL, Polarity);
+}
+
+/**
+  * @brief  Get the polarity of the signal on which the DMA request is generated.
+  * @rmtoll RGxCR        GPOL          LL_DMAMUX_GetRequestGenPolarity
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  RequestGenChannel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_REQ_GEN_0
+  *         @arg @ref LL_DMAMUX_REQ_GEN_1
+  *         @arg @ref LL_DMAMUX_REQ_GEN_2
+  *         @arg @ref LL_DMAMUX_REQ_GEN_3
+  *         @arg @ref LL_DMAMUX_REQ_GEN_4
+  *         @arg @ref LL_DMAMUX_REQ_GEN_5
+  *         @arg @ref LL_DMAMUX_REQ_GEN_6
+  *         @arg @ref LL_DMAMUX_REQ_GEN_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMAMUX_REQ_GEN_NO_EVENT
+  *         @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING
+  *         @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING
+  *         @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GPOL));
+}
+
+/**
+  * @brief  Set the number of DMA request that will be autorized after a generation event.
+  * @note   This field can only be written when Generator is disabled.
+  * @rmtoll RGxCR        GNBREQ        LL_DMAMUX_SetGenRequestNb
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  RequestGenChannel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_REQ_GEN_0
+  *         @arg @ref LL_DMAMUX_REQ_GEN_1
+  *         @arg @ref LL_DMAMUX_REQ_GEN_2
+  *         @arg @ref LL_DMAMUX_REQ_GEN_3
+  *         @arg @ref LL_DMAMUX_REQ_GEN_4
+  *         @arg @ref LL_DMAMUX_REQ_GEN_5
+  *         @arg @ref LL_DMAMUX_REQ_GEN_6
+  *         @arg @ref LL_DMAMUX_REQ_GEN_7
+  * @param  RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32.
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_SetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestNb)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GNBREQ, (RequestNb - 1U) << DMAMUX_RGxCR_GNBREQ_Pos);
+}
+
+/**
+  * @brief  Get the number of DMA request that will be autorized after a generation event.
+  * @rmtoll RGxCR        GNBREQ        LL_DMAMUX_GetGenRequestNb
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  RequestGenChannel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_REQ_GEN_0
+  *         @arg @ref LL_DMAMUX_REQ_GEN_1
+  *         @arg @ref LL_DMAMUX_REQ_GEN_2
+  *         @arg @ref LL_DMAMUX_REQ_GEN_3
+  *         @arg @ref LL_DMAMUX_REQ_GEN_4
+  *         @arg @ref LL_DMAMUX_REQ_GEN_5
+  *         @arg @ref LL_DMAMUX_REQ_GEN_6
+  *         @arg @ref LL_DMAMUX_REQ_GEN_7
+  * @retval Between Min_Data = 1 and Max_Data = 32
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return (uint32_t)((READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GNBREQ) >> DMAMUX_RGxCR_GNBREQ_Pos) + 1U);
+}
+
+/**
+  * @brief  Set DMAMUX external Request Signal ID on DMAMUX Request Generation Trigger Event Channel x.
+  * @rmtoll RGxCR        SIG_ID        LL_DMAMUX_SetRequestSignalID
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  RequestGenChannel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_REQ_GEN_0
+  *         @arg @ref LL_DMAMUX_REQ_GEN_1
+  *         @arg @ref LL_DMAMUX_REQ_GEN_2
+  *         @arg @ref LL_DMAMUX_REQ_GEN_3
+  *         @arg @ref LL_DMAMUX_REQ_GEN_4
+  *         @arg @ref LL_DMAMUX_REQ_GEN_5
+  *         @arg @ref LL_DMAMUX_REQ_GEN_6
+  *         @arg @ref LL_DMAMUX_REQ_GEN_7
+  * @param  RequestSignalID This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
+  *         @arg @ref LL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
+  *         @arg @ref LL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
+  *         @arg @ref LL_DMAMUX1_REQ_GEN_LPTIM1_OUT
+  *         @arg @ref LL_DMAMUX1_REQ_GEN_LPTIM2_OUT
+  *         @arg @ref LL_DMAMUX1_REQ_GEN_LPTIM3_OUT
+  *         @arg @ref LL_DMAMUX1_REQ_GEN_EXTI0
+  *         @arg @ref LL_DMAMUX1_REQ_GEN_TIM12_TRGO
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM2_WKUP
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM2_OUT
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM3_WKUP
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM3_OUT
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM4_WKUP (*)
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM5_WKUP (*)
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_I2C4_WKUP
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_SPI6_WKUP
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_COMP1_OUT
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_COMP2_OUT
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_RTC_WKUP
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_EXTI0
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_EXTI2
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_I2C4_IT_EVT
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_SPI6_IT
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_LPUART1_TX_IT
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_LPUART1_RX_IT
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_ADC3_IT (*)
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT (*)
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_BDMA_CH0_IT
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_BDMA_CH1_IT
+  * @note   (*) Availability depends on devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_SetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestSignalID)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_SIG_ID, RequestSignalID);
+}
+
+/**
+  * @brief  Get DMAMUX external Request Signal ID set on DMAMUX Channel x.
+  * @rmtoll RGxCR        SIG_ID        LL_DMAMUX_GetRequestSignalID
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  RequestGenChannel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_REQ_GEN_0
+  *         @arg @ref LL_DMAMUX_REQ_GEN_1
+  *         @arg @ref LL_DMAMUX_REQ_GEN_2
+  *         @arg @ref LL_DMAMUX_REQ_GEN_3
+  *         @arg @ref LL_DMAMUX_REQ_GEN_4
+  *         @arg @ref LL_DMAMUX_REQ_GEN_5
+  *         @arg @ref LL_DMAMUX_REQ_GEN_6
+  *         @arg @ref LL_DMAMUX_REQ_GEN_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT
+  *         @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT
+  *         @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT
+  *         @arg @ref LL_DMAMUX1_SYNC_LPTIM1_OUT
+  *         @arg @ref LL_DMAMUX1_SYNC_LPTIM2_OUT
+  *         @arg @ref LL_DMAMUX1_SYNC_LPTIM3_OUT
+  *         @arg @ref LL_DMAMUX1_SYNC_EXTI0
+  *         @arg @ref LL_DMAMUX1_SYNC_TIM12_TRGO
+  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT
+  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT
+  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT
+  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT
+  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT
+  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT
+  *         @arg @ref LL_DMAMUX2_SYNC_LPUART1_RX_WKUP
+  *         @arg @ref LL_DMAMUX2_SYNC_LPUART1_TX_WKUP
+  *         @arg @ref LL_DMAMUX2_SYNC_LPTIM2_OUT
+  *         @arg @ref LL_DMAMUX2_SYNC_LPTIM3_OUT
+  *         @arg @ref LL_DMAMUX2_SYNC_I2C4_WKUP
+  *         @arg @ref LL_DMAMUX2_SYNC_SPI6_WKUP
+  *         @arg @ref LL_DMAMUX2_SYNC_COMP1_OUT
+  *         @arg @ref LL_DMAMUX2_SYNC_RTC_WKUP
+  *         @arg @ref LL_DMAMUX2_SYNC_EXTI0
+  *         @arg @ref LL_DMAMUX2_SYNC_EXTI2
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_SIG_ID));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DMAMUX_LL_EF_FLAG_Management FLAG_Management
+  * @{
+  */
+
+/**
+  * @brief  Get Synchronization Event Overrun Flag Channel 0.
+  * @rmtoll CSR          SOF0          LL_DMAMUX_IsActiveFlag_SO0
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF0) == (DMAMUX_CSR_SOF0)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Synchronization Event Overrun Flag Channel 1.
+  * @rmtoll CSR          SOF1          LL_DMAMUX_IsActiveFlag_SO1
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF1) == (DMAMUX_CSR_SOF1)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Synchronization Event Overrun Flag Channel 2.
+  * @rmtoll CSR          SOF2          LL_DMAMUX_IsActiveFlag_SO2
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF2) == (DMAMUX_CSR_SOF2)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Synchronization Event Overrun Flag Channel 3.
+  * @rmtoll CSR          SOF3          LL_DMAMUX_IsActiveFlag_SO3
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF3) == (DMAMUX_CSR_SOF3)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Synchronization Event Overrun Flag Channel 4.
+  * @rmtoll CSR          SOF4          LL_DMAMUX_IsActiveFlag_SO4
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF4) == (DMAMUX_CSR_SOF4)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Synchronization Event Overrun Flag Channel 5.
+  * @rmtoll CSR          SOF5          LL_DMAMUX_IsActiveFlag_SO5
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF5) == (DMAMUX_CSR_SOF5)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Synchronization Event Overrun Flag Channel 6.
+  * @rmtoll CSR          SOF6          LL_DMAMUX_IsActiveFlag_SO6
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF6) == (DMAMUX_CSR_SOF6)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Synchronization Event Overrun Flag Channel 7.
+  * @rmtoll CSR          SOF7          LL_DMAMUX_IsActiveFlag_SO7
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF7) == (DMAMUX_CSR_SOF7)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Synchronization Event Overrun Flag Channel 8.
+  * @rmtoll CSR          SOF8          LL_DMAMUX_IsActiveFlag_SO8
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF8) == (DMAMUX_CSR_SOF8)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Synchronization Event Overrun Flag Channel 9.
+  * @rmtoll CSR          SOF9          LL_DMAMUX_IsActiveFlag_SO9
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF9) == (DMAMUX_CSR_SOF9)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Synchronization Event Overrun Flag Channel 10.
+  * @rmtoll CSR          SOF10         LL_DMAMUX_IsActiveFlag_SO10
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF10) == (DMAMUX_CSR_SOF10)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Synchronization Event Overrun Flag Channel 11.
+  * @rmtoll CSR          SOF11         LL_DMAMUX_IsActiveFlag_SO11
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF11) == (DMAMUX_CSR_SOF11)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Synchronization Event Overrun Flag Channel 12.
+  * @rmtoll CSR          SOF12         LL_DMAMUX_IsActiveFlag_SO12
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF12) == (DMAMUX_CSR_SOF12)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Synchronization Event Overrun Flag Channel 13.
+  * @rmtoll CSR          SOF13         LL_DMAMUX_IsActiveFlag_SO13
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF13) == (DMAMUX_CSR_SOF13)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Synchronization Event Overrun Flag Channel 14.
+  * @rmtoll CSR          SOF14         LL_DMAMUX_IsActiveFlag_SO14
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO14(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF14) == (DMAMUX_CSR_SOF14)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Synchronization Event Overrun Flag Channel 15.
+  * @rmtoll CSR          SOF15         LL_DMAMUX_IsActiveFlag_SO15
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO15(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF15) == (DMAMUX_CSR_SOF15)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Request Generator 0 Trigger Event Overrun Flag.
+  * @rmtoll RGSR         OF0           LL_DMAMUX_IsActiveFlag_RGO0
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF0) == (DMAMUX_RGSR_OF0)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Request Generator 1 Trigger Event Overrun Flag.
+  * @rmtoll RGSR         OF1           LL_DMAMUX_IsActiveFlag_RGO1
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF1) == (DMAMUX_RGSR_OF1)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Request Generator 2 Trigger Event Overrun Flag.
+  * @rmtoll RGSR         OF2           LL_DMAMUX_IsActiveFlag_RGO2
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF2) == (DMAMUX_RGSR_OF2)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Request Generator 3 Trigger Event Overrun Flag.
+  * @rmtoll RGSR         OF3           LL_DMAMUX_IsActiveFlag_RGO3
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF3) == (DMAMUX_RGSR_OF3)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Request Generator 4 Trigger Event Overrun Flag.
+  * @rmtoll RGSR         OF4           LL_DMAMUX_IsActiveFlag_RGO4
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO4(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF4) == (DMAMUX_RGSR_OF4)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Request Generator 5 Trigger Event Overrun Flag.
+  * @rmtoll RGSR         OF5           LL_DMAMUX_IsActiveFlag_RGO5
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO5(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF5) == (DMAMUX_RGSR_OF5)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Request Generator 6 Trigger Event Overrun Flag.
+  * @rmtoll RGSR         OF6           LL_DMAMUX_IsActiveFlag_RGO6
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO6(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF6) == (DMAMUX_RGSR_OF6)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Request Generator 7 Trigger Event Overrun Flag.
+  * @rmtoll RGSR         OF7           LL_DMAMUX_IsActiveFlag_RGO7
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO7(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF7) == (DMAMUX_RGSR_OF7)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear Synchronization Event Overrun Flag Channel 0.
+  * @rmtoll CFR          CSOF0         LL_DMAMUX_ClearFlag_SO0
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF0);
+}
+
+/**
+  * @brief  Clear Synchronization Event Overrun Flag Channel 1.
+  * @rmtoll CFR          CSOF1         LL_DMAMUX_ClearFlag_SO1
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF1);
+}
+
+/**
+  * @brief  Clear Synchronization Event Overrun Flag Channel 2.
+  * @rmtoll CFR          CSOF2         LL_DMAMUX_ClearFlag_SO2
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF2);
+}
+
+/**
+  * @brief  Clear Synchronization Event Overrun Flag Channel 3.
+  * @rmtoll CFR          CSOF3         LL_DMAMUX_ClearFlag_SO3
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF3);
+}
+
+/**
+  * @brief  Clear Synchronization Event Overrun Flag Channel 4.
+  * @rmtoll CFR          CSOF4         LL_DMAMUX_ClearFlag_SO4
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF4);
+}
+
+/**
+  * @brief  Clear Synchronization Event Overrun Flag Channel 5.
+  * @rmtoll CFR          CSOF5         LL_DMAMUX_ClearFlag_SO5
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF5);
+}
+
+/**
+  * @brief  Clear Synchronization Event Overrun Flag Channel 6.
+  * @rmtoll CFR          CSOF6         LL_DMAMUX_ClearFlag_SO6
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF6);
+}
+
+/**
+  * @brief  Clear Synchronization Event Overrun Flag Channel 7.
+  * @rmtoll CFR          CSOF7         LL_DMAMUX_ClearFlag_SO7
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF7);
+}
+
+/**
+  * @brief  Clear Synchronization Event Overrun Flag Channel 8.
+  * @rmtoll CFR          CSOF8         LL_DMAMUX_ClearFlag_SO8
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF8);
+}
+
+/**
+  * @brief  Clear Synchronization Event Overrun Flag Channel 9.
+  * @rmtoll CFR          CSOF9         LL_DMAMUX_ClearFlag_SO9
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF9);
+}
+
+/**
+  * @brief  Clear Synchronization Event Overrun Flag Channel 10.
+  * @rmtoll CFR          CSOF10        LL_DMAMUX_ClearFlag_SO10
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF10);
+}
+
+/**
+  * @brief  Clear Synchronization Event Overrun Flag Channel 11.
+  * @rmtoll CFR          CSOF11        LL_DMAMUX_ClearFlag_SO11
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF11);
+}
+
+/**
+  * @brief  Clear Synchronization Event Overrun Flag Channel 12.
+  * @rmtoll CFR          CSOF12        LL_DMAMUX_ClearFlag_SO12
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF12);
+}
+
+/**
+  * @brief  Clear Synchronization Event Overrun Flag Channel 13.
+  * @rmtoll CFR          CSOF13        LL_DMAMUX_ClearFlag_SO13
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF13);
+}
+
+/**
+  * @brief  Clear Synchronization Event Overrun Flag Channel 14.
+  * @rmtoll CFR          CSOF14        LL_DMAMUX_ClearFlag_SO14
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO14(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF14);
+}
+
+/**
+  * @brief  Clear Synchronization Event Overrun Flag Channel 15.
+  * @rmtoll CFR          CSOF15        LL_DMAMUX_ClearFlag_SO15
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO15(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF15);
+}
+
+/**
+  * @brief  Clear Request Generator 0 Trigger Event Overrun Flag.
+  * @rmtoll RGCFR        COF0          LL_DMAMUX_ClearFlag_RGO0
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF0);
+}
+
+/**
+  * @brief  Clear Request Generator 1 Trigger Event Overrun Flag.
+  * @rmtoll RGCFR        COF1          LL_DMAMUX_ClearFlag_RGO1
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF1);
+}
+
+/**
+  * @brief  Clear Request Generator 2 Trigger Event Overrun Flag.
+  * @rmtoll RGCFR        COF2          LL_DMAMUX_ClearFlag_RGO2
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF2);
+}
+
+/**
+  * @brief  Clear Request Generator 3 Trigger Event Overrun Flag.
+  * @rmtoll RGCFR        COF3          LL_DMAMUX_ClearFlag_RGO3
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF3);
+}
+
+/**
+  * @brief  Clear Request Generator 4 Trigger Event Overrun Flag.
+  * @rmtoll RGCFR        COF4          LL_DMAMUX_ClearFlag_RGO4
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO4(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF4);
+}
+
+/**
+  * @brief  Clear Request Generator 5 Trigger Event Overrun Flag.
+  * @rmtoll RGCFR        COF5          LL_DMAMUX_ClearFlag_RGO5
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO5(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF5);
+}
+
+/**
+  * @brief  Clear Request Generator 6 Trigger Event Overrun Flag.
+  * @rmtoll RGCFR        COF6          LL_DMAMUX_ClearFlag_RGO6
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO6(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF6);
+}
+
+/**
+  * @brief  Clear Request Generator 7 Trigger Event Overrun Flag.
+  * @rmtoll RGCFR        COF7          LL_DMAMUX_ClearFlag_RGO7
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO7(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF7);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DMAMUX_LL_EF_IT_Management IT_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable the Synchronization Event Overrun Interrupt on DMAMUX channel x.
+  * @rmtoll CxCR         SOIE          LL_DMAMUX_EnableIT_SO
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_CHANNEL_0
+  *         @arg @ref LL_DMAMUX_CHANNEL_1
+  *         @arg @ref LL_DMAMUX_CHANNEL_2
+  *         @arg @ref LL_DMAMUX_CHANNEL_3
+  *         @arg @ref LL_DMAMUX_CHANNEL_4
+  *         @arg @ref LL_DMAMUX_CHANNEL_5
+  *         @arg @ref LL_DMAMUX_CHANNEL_6
+  *         @arg @ref LL_DMAMUX_CHANNEL_7
+  *         @arg @ref LL_DMAMUX_CHANNEL_8
+  *         @arg @ref LL_DMAMUX_CHANNEL_9
+  *         @arg @ref LL_DMAMUX_CHANNEL_10
+  *         @arg @ref LL_DMAMUX_CHANNEL_11
+  *         @arg @ref LL_DMAMUX_CHANNEL_12
+  *         @arg @ref LL_DMAMUX_CHANNEL_13
+  *         @arg @ref LL_DMAMUX_CHANNEL_14
+  *         @arg @ref LL_DMAMUX_CHANNEL_15
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_EnableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_SOIE);
+}
+
+/**
+  * @brief  Disable the Synchronization Event Overrun Interrupt on DMAMUX channel x.
+  * @rmtoll CxCR         SOIE          LL_DMAMUX_DisableIT_SO
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_CHANNEL_0
+  *         @arg @ref LL_DMAMUX_CHANNEL_1
+  *         @arg @ref LL_DMAMUX_CHANNEL_2
+  *         @arg @ref LL_DMAMUX_CHANNEL_3
+  *         @arg @ref LL_DMAMUX_CHANNEL_4
+  *         @arg @ref LL_DMAMUX_CHANNEL_5
+  *         @arg @ref LL_DMAMUX_CHANNEL_6
+  *         @arg @ref LL_DMAMUX_CHANNEL_7
+  *         @arg @ref LL_DMAMUX_CHANNEL_8
+  *         @arg @ref LL_DMAMUX_CHANNEL_9
+  *         @arg @ref LL_DMAMUX_CHANNEL_10
+  *         @arg @ref LL_DMAMUX_CHANNEL_11
+  *         @arg @ref LL_DMAMUX_CHANNEL_12
+  *         @arg @ref LL_DMAMUX_CHANNEL_13
+  *         @arg @ref LL_DMAMUX_CHANNEL_14
+  *         @arg @ref LL_DMAMUX_CHANNEL_15
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_DisableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  CLEAR_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_SOIE);
+}
+
+/**
+  * @brief  Check if the Synchronization Event Overrun Interrupt on DMAMUX channel x is enabled or disabled.
+  * @rmtoll CxCR         SOIE          LL_DMAMUX_IsEnabledIT_SO
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_CHANNEL_0
+  *         @arg @ref LL_DMAMUX_CHANNEL_1
+  *         @arg @ref LL_DMAMUX_CHANNEL_2
+  *         @arg @ref LL_DMAMUX_CHANNEL_3
+  *         @arg @ref LL_DMAMUX_CHANNEL_4
+  *         @arg @ref LL_DMAMUX_CHANNEL_5
+  *         @arg @ref LL_DMAMUX_CHANNEL_6
+  *         @arg @ref LL_DMAMUX_CHANNEL_7
+  *         @arg @ref LL_DMAMUX_CHANNEL_8
+  *         @arg @ref LL_DMAMUX_CHANNEL_9
+  *         @arg @ref LL_DMAMUX_CHANNEL_10
+  *         @arg @ref LL_DMAMUX_CHANNEL_11
+  *         @arg @ref LL_DMAMUX_CHANNEL_12
+  *         @arg @ref LL_DMAMUX_CHANNEL_13
+  *         @arg @ref LL_DMAMUX_CHANNEL_14
+  *         @arg @ref LL_DMAMUX_CHANNEL_15
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return (READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SOIE));
+}
+
+/**
+  * @brief  Enable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x.
+  * @rmtoll RGxCR        OIE           LL_DMAMUX_EnableIT_RGO
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  RequestGenChannel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_REQ_GEN_0
+  *         @arg @ref LL_DMAMUX_REQ_GEN_1
+  *         @arg @ref LL_DMAMUX_REQ_GEN_2
+  *         @arg @ref LL_DMAMUX_REQ_GEN_3
+  *         @arg @ref LL_DMAMUX_REQ_GEN_4
+  *         @arg @ref LL_DMAMUX_REQ_GEN_5
+  *         @arg @ref LL_DMAMUX_REQ_GEN_6
+  *         @arg @ref LL_DMAMUX_REQ_GEN_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_EnableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_OIE);
+}
+
+/**
+  * @brief  Disable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x.
+  * @rmtoll RGxCR        OIE           LL_DMAMUX_DisableIT_RGO
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  RequestGenChannel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_REQ_GEN_0
+  *         @arg @ref LL_DMAMUX_REQ_GEN_1
+  *         @arg @ref LL_DMAMUX_REQ_GEN_2
+  *         @arg @ref LL_DMAMUX_REQ_GEN_3
+  *         @arg @ref LL_DMAMUX_REQ_GEN_4
+  *         @arg @ref LL_DMAMUX_REQ_GEN_5
+  *         @arg @ref LL_DMAMUX_REQ_GEN_6
+  *         @arg @ref LL_DMAMUX_REQ_GEN_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_DisableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  CLEAR_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_OIE);
+}
+
+/**
+  * @brief  Check if the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x is enabled or disabled.
+  * @rmtoll RGxCR        OIE           LL_DMAMUX_IsEnabledIT_RGO
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  RequestGenChannel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_REQ_GEN_0
+  *         @arg @ref LL_DMAMUX_REQ_GEN_1
+  *         @arg @ref LL_DMAMUX_REQ_GEN_2
+  *         @arg @ref LL_DMAMUX_REQ_GEN_3
+  *         @arg @ref LL_DMAMUX_REQ_GEN_4
+  *         @arg @ref LL_DMAMUX_REQ_GEN_5
+  *         @arg @ref LL_DMAMUX_REQ_GEN_6
+  *         @arg @ref LL_DMAMUX_REQ_GEN_7
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
+{
+  uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_OIE) == (DMAMUX_RGxCR_OIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* DMAMUX1 || DMAMUX2 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32H7xx_LL_DMAMUX_H */
+
diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_exti.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_exti.h
index 885f22d9..2dad248f 100644
--- a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_exti.h
+++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_exti.h
@@ -1,3285 +1,3285 @@
-/**
-  ******************************************************************************
-  * @file    stm32h7xx_ll_exti.h
-  * @author  MCD Application Team
-  * @brief   Header file of EXTI LL module.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_LL_EXTI_H
-#define __STM32H7xx_LL_EXTI_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx.h"
-
-/** @addtogroup STM32H7xx_LL_Driver
-  * @{
-  */
-
-#if defined (EXTI)
-
-/** @defgroup EXTI_LL EXTI
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private Macros ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros
-  * @{
-  */
-/**
-  * @}
-  */
-#endif /*USE_FULL_LL_DRIVER*/
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure
-  * @{
-  */
-typedef struct
-{
-
-  uint32_t Line_0_31;           /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31
-                                     This parameter can be any combination of @ref EXTI_LL_EC_LINE */
-
-  uint32_t Line_32_63;          /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 32 to 63
-                                     This parameter can be any combination of @ref EXTI_LL_EC_LINE */
-
-  uint32_t Line_64_95;          /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 64 to 95
-                                     This parameter can be any combination of @ref EXTI_LL_EC_LINE */
-
-  FunctionalState LineCommand;  /*!< Specifies the new state of the selected EXTI lines.
-                                     This parameter can be set either to ENABLE or DISABLE */
-
-  uint8_t Mode;                 /*!< Specifies the mode for the EXTI lines.
-                                     This parameter can be a value of @ref EXTI_LL_EC_MODE. */
-
-  uint8_t Trigger;              /*!< Specifies the trigger signal active edge for the EXTI lines.
-                                     This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */
-} LL_EXTI_InitTypeDef;
-
-/**
-  * @}
-  */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants
-  * @{
-  */
-
-/** @defgroup EXTI_LL_EC_LINE LINE
-  * @{
-  */
-#define LL_EXTI_LINE_0                 EXTI_IMR1_IM0           /*!< Extended line 0 */
-#define LL_EXTI_LINE_1                 EXTI_IMR1_IM1           /*!< Extended line 1 */
-#define LL_EXTI_LINE_2                 EXTI_IMR1_IM2           /*!< Extended line 2 */
-#define LL_EXTI_LINE_3                 EXTI_IMR1_IM3           /*!< Extended line 3 */
-#define LL_EXTI_LINE_4                 EXTI_IMR1_IM4           /*!< Extended line 4 */
-#define LL_EXTI_LINE_5                 EXTI_IMR1_IM5           /*!< Extended line 5 */
-#define LL_EXTI_LINE_6                 EXTI_IMR1_IM6           /*!< Extended line 6 */
-#define LL_EXTI_LINE_7                 EXTI_IMR1_IM7           /*!< Extended line 7 */
-#define LL_EXTI_LINE_8                 EXTI_IMR1_IM8           /*!< Extended line 8 */
-#define LL_EXTI_LINE_9                 EXTI_IMR1_IM9           /*!< Extended line 9 */
-#define LL_EXTI_LINE_10                EXTI_IMR1_IM10          /*!< Extended line 10 */
-#define LL_EXTI_LINE_11                EXTI_IMR1_IM11          /*!< Extended line 11 */
-#define LL_EXTI_LINE_12                EXTI_IMR1_IM12          /*!< Extended line 12 */
-#define LL_EXTI_LINE_13                EXTI_IMR1_IM13          /*!< Extended line 13 */
-#define LL_EXTI_LINE_14                EXTI_IMR1_IM14          /*!< Extended line 14 */
-#define LL_EXTI_LINE_15                EXTI_IMR1_IM15          /*!< Extended line 15 */
-#define LL_EXTI_LINE_16                EXTI_IMR1_IM16          /*!< Extended line 16 */
-#define LL_EXTI_LINE_17                EXTI_IMR1_IM17          /*!< Extended line 17 */
-#define LL_EXTI_LINE_18                EXTI_IMR1_IM18          /*!< Extended line 18 */
-#define LL_EXTI_LINE_19                EXTI_IMR1_IM19          /*!< Extended line 19 */
-#define LL_EXTI_LINE_20                EXTI_IMR1_IM20          /*!< Extended line 20 */
-#define LL_EXTI_LINE_21                EXTI_IMR1_IM21          /*!< Extended line 21 */
-#define LL_EXTI_LINE_22                EXTI_IMR1_IM22          /*!< Extended line 22 */
-#define LL_EXTI_LINE_23                EXTI_IMR1_IM23          /*!< Extended line 23 */
-#define LL_EXTI_LINE_24                EXTI_IMR1_IM24          /*!< Extended line 24 */
-#define LL_EXTI_LINE_25                EXTI_IMR1_IM25          /*!< Extended line 25 */
-#define LL_EXTI_LINE_26                EXTI_IMR1_IM26          /*!< Extended line 26 */
-#define LL_EXTI_LINE_27                EXTI_IMR1_IM27          /*!< Extended line 27 */
-#define LL_EXTI_LINE_28                EXTI_IMR1_IM28          /*!< Extended line 28 */
-#define LL_EXTI_LINE_29                EXTI_IMR1_IM29          /*!< Extended line 29 */
-#define LL_EXTI_LINE_30                EXTI_IMR1_IM30          /*!< Extended line 30 */
-#define LL_EXTI_LINE_31                EXTI_IMR1_IM31          /*!< Extended line 31 */
-#define LL_EXTI_LINE_ALL_0_31          EXTI_IMR1_IM            /*!< All Extended line not reserved*/
-
-#define LL_EXTI_LINE_32                EXTI_IMR2_IM32          /*!< Extended line 32 */
-#define LL_EXTI_LINE_33                EXTI_IMR2_IM33          /*!< Extended line 33 */
-#define LL_EXTI_LINE_34                EXTI_IMR2_IM34          /*!< Extended line 34 */
-#define LL_EXTI_LINE_35                EXTI_IMR2_IM35          /*!< Extended line 35 */
-#define LL_EXTI_LINE_36                EXTI_IMR2_IM36          /*!< Extended line 36 */
-#define LL_EXTI_LINE_37                EXTI_IMR2_IM37          /*!< Extended line 37 */
-#define LL_EXTI_LINE_38                EXTI_IMR2_IM38          /*!< Extended line 38 */
-#define LL_EXTI_LINE_39                EXTI_IMR2_IM39          /*!< Extended line 39 */
-#define LL_EXTI_LINE_40                EXTI_IMR2_IM40          /*!< Extended line 40 */
-#define LL_EXTI_LINE_41                EXTI_IMR2_IM41          /*!< Extended line 41 */
-#define LL_EXTI_LINE_42                EXTI_IMR2_IM42          /*!< Extended line 42 */
-#define LL_EXTI_LINE_43                EXTI_IMR2_IM43          /*!< Extended line 43 */
-#if defined(USB2_OTG_FS)
-#define LL_EXTI_LINE_44                EXTI_IMR2_IM44          /*!< Extended line 44 */
-#endif /* USB2_OTG_FS */
-#if defined(DSI)
-#define LL_EXTI_LINE_46                EXTI_IMR2_IM46          /*!< Extended line 46 */
-#endif /* DSI */
-#define LL_EXTI_LINE_47                EXTI_IMR2_IM47          /*!< Extended line 47 */
-#define LL_EXTI_LINE_48                EXTI_IMR2_IM48          /*!< Extended line 48 */
-#define LL_EXTI_LINE_49                EXTI_IMR2_IM49          /*!< Extended line 49 */
-#define LL_EXTI_LINE_50                EXTI_IMR2_IM50          /*!< Extended line 50 */
-#define LL_EXTI_LINE_51                EXTI_IMR2_IM51          /*!< Extended line 51 */
-#define LL_EXTI_LINE_52                EXTI_IMR2_IM52          /*!< Extended line 52 */
-#define LL_EXTI_LINE_53                EXTI_IMR2_IM53          /*!< Extended line 53 */
-#define LL_EXTI_LINE_54                EXTI_IMR2_IM54          /*!< Extended line 54 */
-#define LL_EXTI_LINE_55                EXTI_IMR2_IM55          /*!< Extended line 55 */
-#define LL_EXTI_LINE_56                EXTI_IMR2_IM56          /*!< Extended line 56 */
-#if defined(EXTI_IMR2_IM57)
-#define LL_EXTI_LINE_57                EXTI_IMR2_IM57          /*!< Extended line 57 */
-#endif /*EXTI_IMR2_IM57*/
-#define LL_EXTI_LINE_58                EXTI_IMR2_IM58          /*!< Extended line 58 */
-#if defined(EXTI_IMR2_IM59)
-#define LL_EXTI_LINE_59                EXTI_IMR2_IM59          /*!< Extended line 59 */
-#endif /*EXTI_IMR2_IM59*/
-#define LL_EXTI_LINE_60                EXTI_IMR2_IM60          /*!< Extended line 60 */
-#define LL_EXTI_LINE_61                EXTI_IMR2_IM61          /*!< Extended line 61 */
-#define LL_EXTI_LINE_62                EXTI_IMR2_IM62          /*!< Extended line 62 */
-#define LL_EXTI_LINE_63                EXTI_IMR2_IM63          /*!< Extended line 63 */
-#define LL_EXTI_LINE_ALL_32_63         EXTI_IMR2_IM            /*!< All Extended line not reserved*/
-
-#define LL_EXTI_LINE_64                EXTI_IMR3_IM64          /*!< Extended line 64 */
-#define LL_EXTI_LINE_65                EXTI_IMR3_IM65          /*!< Extended line 65 */
-#define LL_EXTI_LINE_66                EXTI_IMR3_IM66          /*!< Extended line 66 */
-#define LL_EXTI_LINE_67                EXTI_IMR3_IM67          /*!< Extended line 67 */
-#define LL_EXTI_LINE_68                EXTI_IMR3_IM68          /*!< Extended line 68 */
-#define LL_EXTI_LINE_69                EXTI_IMR3_IM69          /*!< Extended line 69 */
-#define LL_EXTI_LINE_70                EXTI_IMR3_IM70          /*!< Extended line 70 */
-#define LL_EXTI_LINE_71                EXTI_IMR3_IM71          /*!< Extended line 71 */
-#define LL_EXTI_LINE_72                EXTI_IMR3_IM72          /*!< Extended line 72 */
-#define LL_EXTI_LINE_73                EXTI_IMR3_IM73          /*!< Extended line 73 */
-#define LL_EXTI_LINE_74                EXTI_IMR3_IM74          /*!< Extended line 74 */
-#if defined(ADC3)
-#define LL_EXTI_LINE_75                EXTI_IMR3_IM75          /*!< Extended line 75 */
-#endif /* ADC3 */
-#if defined(SAI4)
-#define LL_EXTI_LINE_76                EXTI_IMR3_IM76          /*!< Extended line 76 */
-#endif /* SAI4 */
-#if defined(DUAL_CORE)
-#define LL_EXTI_LINE_77                EXTI_IMR3_IM77          /*!< Extended line 77 */
-#define LL_EXTI_LINE_78                EXTI_IMR3_IM78          /*!< Extended line 78 */
-#define LL_EXTI_LINE_79                EXTI_IMR3_IM79          /*!< Extended line 79 */
-#define LL_EXTI_LINE_80                EXTI_IMR3_IM80          /*!< Extended line 80 */
-#define LL_EXTI_LINE_82                EXTI_IMR3_IM82          /*!< Extended line 82 */
-#define LL_EXTI_LINE_84                EXTI_IMR3_IM84          /*!< Extended line 84 */
-#endif /* DUAL_CORE */
-#define LL_EXTI_LINE_85                EXTI_IMR3_IM85          /*!< Extended line 85 */
-#if defined(ETH)
-#define LL_EXTI_LINE_86                EXTI_IMR3_IM86          /*!< Extended line 86 */
-#endif /* ETH */
-#define LL_EXTI_LINE_87                EXTI_IMR3_IM87          /*!< Extended line 87 */
-#if defined(DTS)
-#define LL_EXTI_LINE_88                EXTI_IMR3_IM88          /*!< Extended line 88 */
-#endif /* DTS */
-#if defined(EXTI_IMR3_IM89)
-#define LL_EXTI_LINE_89                EXTI_IMR3_IM89          /*!< Extended line 89 */
-#endif /* EXTI_IMR3_IM89 */
-#if defined(EXTI_IMR3_IM90)
-#define LL_EXTI_LINE_90                EXTI_IMR3_IM90          /*!< Extended line 90 */
-#endif /* EXTI_IMR3_IM90 */
-#if defined(I2C5)
-#define LL_EXTI_LINE_91                EXTI_IMR3_IM91          /*!< Extended line 91 */
-#endif /* I2C5 */
-#define LL_EXTI_LINE_ALL_64_95         EXTI_IMR3_IM            /*!< All Extended line not reserved*/
-
-
-#define LL_EXTI_LINE_ALL               (0xFFFFFFFFU)  /*!< All Extended line */
-
-#if defined(USE_FULL_LL_DRIVER)
-#define LL_EXTI_LINE_NONE              (0x00000000U)  /*!< None Extended line */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/**
-  * @}
-  */
-#if defined(USE_FULL_LL_DRIVER)
-
-/** @defgroup EXTI_LL_EC_MODE Mode
-  * @{
-  */
-#define LL_EXTI_MODE_IT               ((uint8_t)0x01U)      /*!< Cortex-M7 Interrupt Mode  */
-#define LL_EXTI_MODE_EVENT            ((uint8_t)0x02U)      /*!< Cortex-M7 Event Mode */
-#define LL_EXTI_MODE_IT_EVENT         ((uint8_t)0x03U)      /*!< Cortex-M7 Interrupt & Event Mode */
-
-#if defined(DUAL_CORE)
-#define LL_EXTI_MODE_C1_IT            LL_EXTI_MODE_IT       /*!< Cortex-M7 Interrupt Mode */
-#define LL_EXTI_MODE_C1_EVENT         LL_EXTI_MODE_EVENT    /*!< Cortex-M7 Event Mode */
-#define LL_EXTI_MODE_C1_IT_EVENT      LL_EXTI_MODE_IT_EVENT /*!< Cortex-M7 Interrupt & Event Mode */
-
-#define LL_EXTI_MODE_C2_IT            ((uint8_t)0x10U)      /*!< Cortex-M4 Interrupt Mode  */
-#define LL_EXTI_MODE_C2_EVENT         ((uint8_t)0x20U)      /*!< Cortex-M4 Event Mode  */
-#define LL_EXTI_MODE_C2_IT_EVENT      ((uint8_t)0x30U)      /*!< Cortex-M4 Interrupt & Event Mode */
-#endif /* DUAL_CORE */
-
-/**
-  * @}
-  */
-
-/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger
-  * @{
-  */
-#define LL_EXTI_TRIGGER_NONE            ((uint8_t)0x00U) /*!< No Trigger Mode */
-#define LL_EXTI_TRIGGER_RISING          ((uint8_t)0x01U) /*!< Trigger Rising Mode */
-#define LL_EXTI_TRIGGER_FALLING         ((uint8_t)0x02U) /*!< Trigger Falling Mode */
-#define LL_EXTI_TRIGGER_RISING_FALLING  ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */
-
-/**
-  * @}
-  */
-
-/** @defgroup EXTI_LL_D3_PEND_CLR D3 Pend Clear Source
-  * @{
-  */
-#define LL_EXTI_D3_PEND_CLR_DMACH6      ((uint8_t)0x00U) /*!< DMA ch6 event selected as D3 domain pendclear source */
-#define LL_EXTI_D3_PEND_CLR_DMACH7      ((uint8_t)0x01U) /*!< DMA ch7 event selected as D3 domain pendclear source */
-#if defined (LPTIM4)
-#define LL_EXTI_D3_PEND_CLR_LPTIM4      ((uint8_t)0x02U) /*!< LPTIM4 out selected as D3 domain pendclear source */
-#else
-#define LL_EXTI_D3_PEND_CLR_LPTIM2      ((uint8_t)0x02U) /*!< LPTIM2 out selected as D3 domain pendclear source */
-#endif /*LPTIM4*/
-#if defined (LPTIM5)
-#define LL_EXTI_D3_PEND_CLR_LPTIM5      ((uint8_t)0x03U) /*!< LPTIM5 out selected as D3 domain pendclear source */
-#else
-#define LL_EXTI_D3_PEND_CLR_LPTIM3      ((uint8_t)0x02U) /*!< LPTIM3 out selected as D3 domain pendclear source */
-#endif /*LPTIM5*/
-/**
-  * @}
-  */
-
-
-#endif /*USE_FULL_LL_DRIVER*/
-
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros
-  * @{
-  */
-
-/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros
-  * @{
-  */
-
-/**
-  * @brief  Write a value in EXTI register
-  * @param  __REG__ Register to be written
-  * @param  __VALUE__ Value to be written in the register
-  * @retval None
-  */
-#define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__))
-
-/**
-  * @brief  Read a value in EXTI register
-  * @param  __REG__ Register to be read
-  * @retval Register value
-  */
-#define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__)
-
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */
-
-
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions
- * @{
- */
-/** @defgroup EXTI_LL_EF_IT_Management IT_Management
-  * @{
-  */
-
-/**
-  * @brief  Enable ExtiLine Interrupt request for Lines in range 0 to 31
-  * @rmtoll IMR1         IMx           LL_EXTI_EnableIT_0_31
-  * @param  ExtiLine This parameter can be one of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_17
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19
-  *         @arg @ref LL_EXTI_LINE_20
-  *         @arg @ref LL_EXTI_LINE_21
-  *         @arg @ref LL_EXTI_LINE_22
-  *         @arg @ref LL_EXTI_LINE_23
-  *         @arg @ref LL_EXTI_LINE_24
-  *         @arg @ref LL_EXTI_LINE_25
-  *         @arg @ref LL_EXTI_LINE_26
-  *         @arg @ref LL_EXTI_LINE_27
-  *         @arg @ref LL_EXTI_LINE_28
-  *         @arg @ref LL_EXTI_LINE_29
-  *         @arg @ref LL_EXTI_LINE_30
-  *         @arg @ref LL_EXTI_LINE_31
-  *         @arg @ref LL_EXTI_LINE_ALL_0_31
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine)
-{
-  SET_BIT(EXTI->IMR1, ExtiLine);
-}
-
-/**
-  * @brief  Enable ExtiLine Interrupt request for Lines in range 32 to 63
-  * @rmtoll IMR2         IMx           LL_EXTI_EnableIT_32_63
-  * @param  ExtiLine This parameter can be one of the following values:
-  *         @arg @ref LL_EXTI_LINE_32
-  *         @arg @ref LL_EXTI_LINE_33
-  *         @arg @ref LL_EXTI_LINE_34
-  *         @arg @ref LL_EXTI_LINE_35
-  *         @arg @ref LL_EXTI_LINE_36
-  *         @arg @ref LL_EXTI_LINE_37
-  *         @arg @ref LL_EXTI_LINE_38
-  *         @arg @ref LL_EXTI_LINE_39
-  *         @arg @ref LL_EXTI_LINE_40
-  *         @arg @ref LL_EXTI_LINE_41
-  *         @arg @ref LL_EXTI_LINE_42
-  *         @arg @ref LL_EXTI_LINE_43
-  *         @arg @ref LL_EXTI_LINE_44 (*)
-  *         @arg @ref LL_EXTI_LINE_46 (*)
-  *         @arg @ref LL_EXTI_LINE_47
-  *         @arg @ref LL_EXTI_LINE_48
-  *         @arg @ref LL_EXTI_LINE_49
-  *         @arg @ref LL_EXTI_LINE_50
-  *         @arg @ref LL_EXTI_LINE_51
-  *         @arg @ref LL_EXTI_LINE_52
-  *         @arg @ref LL_EXTI_LINE_53
-  *         @arg @ref LL_EXTI_LINE_54
-  *         @arg @ref LL_EXTI_LINE_55
-  *         @arg @ref LL_EXTI_LINE_56
-  *         @arg @ref LL_EXTI_LINE_57 (*)
-  *         @arg @ref LL_EXTI_LINE_58
-  *         @arg @ref LL_EXTI_LINE_59 (*)
-  *         @arg @ref LL_EXTI_LINE_60
-  *         @arg @ref LL_EXTI_LINE_61
-  *         @arg @ref LL_EXTI_LINE_62
-  *         @arg @ref LL_EXTI_LINE_63
-  *         @arg @ref LL_EXTI_LINE_ALL_32_63
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_EnableIT_32_63(uint32_t ExtiLine)
-{
-  SET_BIT(EXTI->IMR2, ExtiLine);
-}
-
-
-/**
-  * @brief  Enable ExtiLine Interrupt request for Lines in range 64 to 95
-  * @rmtoll IMR3         IMx           LL_EXTI_EnableIT_64_95
-  * @param  ExtiLine This parameter can be one of the following values:
-  *         @arg @ref LL_EXTI_LINE_64
-  *         @arg @ref LL_EXTI_LINE_65
-  *         @arg @ref LL_EXTI_LINE_66
-  *         @arg @ref LL_EXTI_LINE_67
-  *         @arg @ref LL_EXTI_LINE_68
-  *         @arg @ref LL_EXTI_LINE_69
-  *         @arg @ref LL_EXTI_LINE_70
-  *         @arg @ref LL_EXTI_LINE_71
-  *         @arg @ref LL_EXTI_LINE_72
-  *         @arg @ref LL_EXTI_LINE_73
-  *         @arg @ref LL_EXTI_LINE_74
-  *         @arg @ref LL_EXTI_LINE_75 (*)
-  *         @arg @ref LL_EXTI_LINE_76 (*)
-  *         @arg @ref LL_EXTI_LINE_77 (**)
-  *         @arg @ref LL_EXTI_LINE_78 (**)
-  *         @arg @ref LL_EXTI_LINE_79 (**)
-  *         @arg @ref LL_EXTI_LINE_80 (**)
-  *         @arg @ref LL_EXTI_LINE_82 (**)
-  *         @arg @ref LL_EXTI_LINE_84 (**)
-  *         @arg @ref LL_EXTI_LINE_85
-  *         @arg @ref LL_EXTI_LINE_86 (*)
-  *         @arg @ref LL_EXTI_LINE_87
-  *         @arg @ref LL_EXTI_LINE_88 (*)
-  *         @arg @ref LL_EXTI_LINE_89 (*) 
-  *         @arg @ref LL_EXTI_LINE_90 (*)
-  *         @arg @ref LL_EXTI_LINE_91 (*)
-  *         @arg @ref LL_EXTI_LINE_ALL_64_95
-  *
-  *         (*) value not defined in all devices.
-  *         (**) value only defined in dual core devices.
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_EnableIT_64_95(uint32_t ExtiLine)
-{
-  SET_BIT(EXTI->IMR3, ExtiLine);
-}
-
-
-/**
-  * @brief  Disable ExtiLine Interrupt request for Lines in range 0 to 31
-  * @rmtoll IMR1         IMx           LL_EXTI_DisableIT_0_31
-  * @param  ExtiLine This parameter can be one of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_17
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19
-  *         @arg @ref LL_EXTI_LINE_20
-  *         @arg @ref LL_EXTI_LINE_21
-  *         @arg @ref LL_EXTI_LINE_22
-  *         @arg @ref LL_EXTI_LINE_23
-  *         @arg @ref LL_EXTI_LINE_24
-  *         @arg @ref LL_EXTI_LINE_25
-  *         @arg @ref LL_EXTI_LINE_26
-  *         @arg @ref LL_EXTI_LINE_27
-  *         @arg @ref LL_EXTI_LINE_28
-  *         @arg @ref LL_EXTI_LINE_29
-  *         @arg @ref LL_EXTI_LINE_30
-  *         @arg @ref LL_EXTI_LINE_31
-  *         @arg @ref LL_EXTI_LINE_ALL_0_31
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine)
-{
-  CLEAR_BIT(EXTI->IMR1, ExtiLine);
-}
-
-
-/**
-  * @brief  Disable ExtiLine Interrupt request for Lines in range 32 to 63
-  * @rmtoll IMR2         IMx           LL_EXTI_DisableIT_32_63
-  * @param  ExtiLine This parameter can be one of the following values:
-  *         @arg @ref LL_EXTI_LINE_32
-  *         @arg @ref LL_EXTI_LINE_33
-  *         @arg @ref LL_EXTI_LINE_34
-  *         @arg @ref LL_EXTI_LINE_35
-  *         @arg @ref LL_EXTI_LINE_36
-  *         @arg @ref LL_EXTI_LINE_37
-  *         @arg @ref LL_EXTI_LINE_38
-  *         @arg @ref LL_EXTI_LINE_39
-  *         @arg @ref LL_EXTI_LINE_40
-  *         @arg @ref LL_EXTI_LINE_41
-  *         @arg @ref LL_EXTI_LINE_42
-  *         @arg @ref LL_EXTI_LINE_43
-  *         @arg @ref LL_EXTI_LINE_44 (*)
-  *         @arg @ref LL_EXTI_LINE_46 (*)
-  *         @arg @ref LL_EXTI_LINE_47
-  *         @arg @ref LL_EXTI_LINE_48
-  *         @arg @ref LL_EXTI_LINE_49
-  *         @arg @ref LL_EXTI_LINE_50
-  *         @arg @ref LL_EXTI_LINE_51
-  *         @arg @ref LL_EXTI_LINE_52
-  *         @arg @ref LL_EXTI_LINE_53
-  *         @arg @ref LL_EXTI_LINE_54
-  *         @arg @ref LL_EXTI_LINE_55
-  *         @arg @ref LL_EXTI_LINE_56
-  *         @arg @ref LL_EXTI_LINE_57 (*)
-  *         @arg @ref LL_EXTI_LINE_58
-  *         @arg @ref LL_EXTI_LINE_59 (*)
-  *         @arg @ref LL_EXTI_LINE_60
-  *         @arg @ref LL_EXTI_LINE_61
-  *         @arg @ref LL_EXTI_LINE_62
-  *         @arg @ref LL_EXTI_LINE_63
-  *         @arg @ref LL_EXTI_LINE_ALL_32_63
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_DisableIT_32_63(uint32_t ExtiLine)
-{
-  CLEAR_BIT(EXTI->IMR2, ExtiLine);
-}
-
-/**
-  * @brief  Disable ExtiLine Interrupt request for Lines in range 64 to 95
-  * @rmtoll IMR3         IMx           LL_EXTI_DisableIT_64_95
-  * @param  ExtiLine This parameter can be one of the following values:
-  *         @arg @ref LL_EXTI_LINE_64
-  *         @arg @ref LL_EXTI_LINE_65
-  *         @arg @ref LL_EXTI_LINE_66
-  *         @arg @ref LL_EXTI_LINE_67
-  *         @arg @ref LL_EXTI_LINE_68
-  *         @arg @ref LL_EXTI_LINE_69
-  *         @arg @ref LL_EXTI_LINE_70
-  *         @arg @ref LL_EXTI_LINE_71
-  *         @arg @ref LL_EXTI_LINE_72
-  *         @arg @ref LL_EXTI_LINE_73
-  *         @arg @ref LL_EXTI_LINE_74
-  *         @arg @ref LL_EXTI_LINE_75 (*)
-  *         @arg @ref LL_EXTI_LINE_76 (*)
-  *         @arg @ref LL_EXTI_LINE_77 (**)
-  *         @arg @ref LL_EXTI_LINE_78 (**)
-  *         @arg @ref LL_EXTI_LINE_79 (**)
-  *         @arg @ref LL_EXTI_LINE_80 (**)
-  *         @arg @ref LL_EXTI_LINE_82 (**)
-  *         @arg @ref LL_EXTI_LINE_84 (**)
-  *         @arg @ref LL_EXTI_LINE_85
-  *         @arg @ref LL_EXTI_LINE_86 (*)
-  *         @arg @ref LL_EXTI_LINE_87
-  *         @arg @ref LL_EXTI_LINE_88 (*)
-  *         @arg @ref LL_EXTI_LINE_89 (*) 
-  *         @arg @ref LL_EXTI_LINE_90 (*)
-  *         @arg @ref LL_EXTI_LINE_91 (*)
-  *         @arg @ref LL_EXTI_LINE_ALL_64_95
-  *
-  *         (*) value not defined in all devices.
-  *         (**) value only defined in dual core devices.
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_DisableIT_64_95(uint32_t ExtiLine)
-{
-  CLEAR_BIT(EXTI->IMR3, ExtiLine);
-}
-
-
-/**
-  * @brief  Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31
-  * @rmtoll IMR1         IMx           LL_EXTI_IsEnabledIT_0_31
-  * @param  ExtiLine This parameter can be one of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_17
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19
-  *         @arg @ref LL_EXTI_LINE_20
-  *         @arg @ref LL_EXTI_LINE_21
-  *         @arg @ref LL_EXTI_LINE_22
-  *         @arg @ref LL_EXTI_LINE_23
-  *         @arg @ref LL_EXTI_LINE_24
-  *         @arg @ref LL_EXTI_LINE_25
-  *         @arg @ref LL_EXTI_LINE_26
-  *         @arg @ref LL_EXTI_LINE_27
-  *         @arg @ref LL_EXTI_LINE_28
-  *         @arg @ref LL_EXTI_LINE_29
-  *         @arg @ref LL_EXTI_LINE_30
-  *         @arg @ref LL_EXTI_LINE_31
-  *         @arg @ref LL_EXTI_LINE_ALL_0_31
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine)
-{
-  return ((READ_BIT(EXTI->IMR1, ExtiLine) == (ExtiLine)) ? 1U : 0U);
-}
-
-
-/**
-  * @brief  Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63
-  * @rmtoll IMR2         IMx           LL_EXTI_IsEnabledIT_32_63
-  * @param  ExtiLine This parameter can be one of the following values:
-  *         @arg @ref LL_EXTI_LINE_32
-  *         @arg @ref LL_EXTI_LINE_33
-  *         @arg @ref LL_EXTI_LINE_34
-  *         @arg @ref LL_EXTI_LINE_35
-  *         @arg @ref LL_EXTI_LINE_36
-  *         @arg @ref LL_EXTI_LINE_37
-  *         @arg @ref LL_EXTI_LINE_38
-  *         @arg @ref LL_EXTI_LINE_39
-  *         @arg @ref LL_EXTI_LINE_40
-  *         @arg @ref LL_EXTI_LINE_41
-  *         @arg @ref LL_EXTI_LINE_42
-  *         @arg @ref LL_EXTI_LINE_43
-  *         @arg @ref LL_EXTI_LINE_44 (*)
-  *         @arg @ref LL_EXTI_LINE_46 (*)
-  *         @arg @ref LL_EXTI_LINE_47
-  *         @arg @ref LL_EXTI_LINE_48
-  *         @arg @ref LL_EXTI_LINE_49
-  *         @arg @ref LL_EXTI_LINE_50
-  *         @arg @ref LL_EXTI_LINE_51
-  *         @arg @ref LL_EXTI_LINE_52
-  *         @arg @ref LL_EXTI_LINE_53
-  *         @arg @ref LL_EXTI_LINE_54
-  *         @arg @ref LL_EXTI_LINE_55
-  *         @arg @ref LL_EXTI_LINE_56
-  *         @arg @ref LL_EXTI_LINE_57 (*)
-  *         @arg @ref LL_EXTI_LINE_58
-  *         @arg @ref LL_EXTI_LINE_59 (*)
-  *         @arg @ref LL_EXTI_LINE_60
-  *         @arg @ref LL_EXTI_LINE_61
-  *         @arg @ref LL_EXTI_LINE_62
-  *         @arg @ref LL_EXTI_LINE_63
-  *         @arg @ref LL_EXTI_LINE_ALL_32_63
-  *
-  *         (*) value not defined in all devices.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_32_63(uint32_t ExtiLine)
-{
-  return ((READ_BIT(EXTI->IMR2, ExtiLine) == (ExtiLine)) ? 1U : 0U);
-}
-
-
-/**
-  * @brief  Indicate if ExtiLine Interrupt request is enabled for Lines in range 64 to 95
-  * @rmtoll IMR3         IMx           LL_EXTI_IsEnabledIT_64_95
-  * @param  ExtiLine This parameter can be one of the following values:
-  *         @arg @ref LL_EXTI_LINE_64
-  *         @arg @ref LL_EXTI_LINE_65
-  *         @arg @ref LL_EXTI_LINE_66
-  *         @arg @ref LL_EXTI_LINE_67
-  *         @arg @ref LL_EXTI_LINE_68
-  *         @arg @ref LL_EXTI_LINE_69
-  *         @arg @ref LL_EXTI_LINE_70
-  *         @arg @ref LL_EXTI_LINE_71
-  *         @arg @ref LL_EXTI_LINE_72
-  *         @arg @ref LL_EXTI_LINE_73
-  *         @arg @ref LL_EXTI_LINE_74
-  *         @arg @ref LL_EXTI_LINE_75 (*)
-  *         @arg @ref LL_EXTI_LINE_76 (*)
-  *         @arg @ref LL_EXTI_LINE_77 (**)
-  *         @arg @ref LL_EXTI_LINE_78 (**)
-  *         @arg @ref LL_EXTI_LINE_79 (**)
-  *         @arg @ref LL_EXTI_LINE_80 (**)
-  *         @arg @ref LL_EXTI_LINE_82 (**)
-  *         @arg @ref LL_EXTI_LINE_84 (**)
-  *         @arg @ref LL_EXTI_LINE_85
-  *         @arg @ref LL_EXTI_LINE_86 (*)
-  *         @arg @ref LL_EXTI_LINE_87
-  *         @arg @ref LL_EXTI_LINE_88 (*)
-  *         @arg @ref LL_EXTI_LINE_89 (*) 
-  *         @arg @ref LL_EXTI_LINE_90 (*)
-  *         @arg @ref LL_EXTI_LINE_91 (*)
-  *         @arg @ref LL_EXTI_LINE_ALL_64_95
-  *
-  *         (*) value not defined in all devices.
-  *         (**) value only defined in dual core devices.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_64_95(uint32_t ExtiLine)
-{
-  return ((READ_BIT(EXTI->IMR3, ExtiLine) == (ExtiLine)) ? 1U : 0U);
-}
-
-#if defined(DUAL_CORE)
-/**
-  * @brief  Enable ExtiLine Interrupt request for Lines in range 0 to 31 for cpu2
-  * @rmtoll C2IMR1         IMx           LL_C2_EXTI_EnableIT_0_31
-  * @param  ExtiLine This parameter can be one of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_17
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19
-  *         @arg @ref LL_EXTI_LINE_20
-  *         @arg @ref LL_EXTI_LINE_21
-  *         @arg @ref LL_EXTI_LINE_22
-  *         @arg @ref LL_EXTI_LINE_23
-  *         @arg @ref LL_EXTI_LINE_24
-  *         @arg @ref LL_EXTI_LINE_25
-  *         @arg @ref LL_EXTI_LINE_26
-  *         @arg @ref LL_EXTI_LINE_27
-  *         @arg @ref LL_EXTI_LINE_28
-  *         @arg @ref LL_EXTI_LINE_29
-  *         @arg @ref LL_EXTI_LINE_30
-  *         @arg @ref LL_EXTI_LINE_31
-  *         @arg @ref LL_EXTI_LINE_ALL_0_31
-  * @retval None
-  */
-__STATIC_INLINE void LL_C2_EXTI_EnableIT_0_31(uint32_t ExtiLine)
-{
-  SET_BIT(EXTI->C2IMR1, ExtiLine);
-}
-
-
-/**
-  * @brief  Enable ExtiLine Interrupt request for Lines in range 32 to 63 for cpu2
-  * @rmtoll C2IMR2         IMx           LL_C2_EXTI_EnableIT_32_63
-  * @param  ExtiLine This parameter can be one of the following values:
-  *         @arg @ref LL_EXTI_LINE_32
-  *         @arg @ref LL_EXTI_LINE_33
-  *         @arg @ref LL_EXTI_LINE_34
-  *         @arg @ref LL_EXTI_LINE_35
-  *         @arg @ref LL_EXTI_LINE_36
-  *         @arg @ref LL_EXTI_LINE_37
-  *         @arg @ref LL_EXTI_LINE_38
-  *         @arg @ref LL_EXTI_LINE_39
-  *         @arg @ref LL_EXTI_LINE_40
-  *         @arg @ref LL_EXTI_LINE_41
-  *         @arg @ref LL_EXTI_LINE_42
-  *         @arg @ref LL_EXTI_LINE_43
-  *         @arg @ref LL_EXTI_LINE_44
-  *         @arg @ref LL_EXTI_LINE_46
-  *         @arg @ref LL_EXTI_LINE_47
-  *         @arg @ref LL_EXTI_LINE_48
-  *         @arg @ref LL_EXTI_LINE_49
-  *         @arg @ref LL_EXTI_LINE_50
-  *         @arg @ref LL_EXTI_LINE_51
-  *         @arg @ref LL_EXTI_LINE_52
-  *         @arg @ref LL_EXTI_LINE_53
-  *         @arg @ref LL_EXTI_LINE_54
-  *         @arg @ref LL_EXTI_LINE_55
-  *         @arg @ref LL_EXTI_LINE_56
-  *         @arg @ref LL_EXTI_LINE_57
-  *         @arg @ref LL_EXTI_LINE_58
-  *         @arg @ref LL_EXTI_LINE_59
-  *         @arg @ref LL_EXTI_LINE_60
-  *         @arg @ref LL_EXTI_LINE_61
-  *         @arg @ref LL_EXTI_LINE_62
-  *         @arg @ref LL_EXTI_LINE_63
-  *         @arg @ref LL_EXTI_LINE_ALL_32_63
-  * @retval None
-  */
-__STATIC_INLINE void LL_C2_EXTI_EnableIT_32_63(uint32_t ExtiLine)
-{
-  SET_BIT(EXTI->C2IMR2, ExtiLine);
-}
-
-
-/**
-  * @brief  Enable ExtiLine Interrupt request for Lines in range 64 to 95
-  * @rmtoll C2IMR3         IMx           LL_C2_EXTI_EnableIT_64_95
-  * @param  ExtiLine This parameter can be one of the following values:
-  *         @arg @ref LL_EXTI_LINE_64
-  *         @arg @ref LL_EXTI_LINE_65
-  *         @arg @ref LL_EXTI_LINE_66
-  *         @arg @ref LL_EXTI_LINE_67
-  *         @arg @ref LL_EXTI_LINE_68
-  *         @arg @ref LL_EXTI_LINE_69
-  *         @arg @ref LL_EXTI_LINE_70
-  *         @arg @ref LL_EXTI_LINE_71
-  *         @arg @ref LL_EXTI_LINE_72
-  *         @arg @ref LL_EXTI_LINE_73
-  *         @arg @ref LL_EXTI_LINE_74
-  *         @arg @ref LL_EXTI_LINE_75
-  *         @arg @ref LL_EXTI_LINE_76
-  *         @arg @ref LL_EXTI_LINE_77
-  *         @arg @ref LL_EXTI_LINE_78
-  *         @arg @ref LL_EXTI_LINE_79
-  *         @arg @ref LL_EXTI_LINE_80
-  *         @arg @ref LL_EXTI_LINE_82
-  *         @arg @ref LL_EXTI_LINE_84
-  *         @arg @ref LL_EXTI_LINE_85
-  *         @arg @ref LL_EXTI_LINE_86
-  *         @arg @ref LL_EXTI_LINE_87
-  *         @arg @ref LL_EXTI_LINE_ALL_64_95
-  * @retval None
-  */
-__STATIC_INLINE void LL_C2_EXTI_EnableIT_64_95(uint32_t ExtiLine)
-{
-  SET_BIT(EXTI->C2IMR3, ExtiLine);
-}
-
-
-/**
-  * @brief  Disable ExtiLine Interrupt request for Lines in range 0 to 31 for cpu2
-  * @rmtoll C2IMR1         IMx           LL_C2_EXTI_DisableIT_0_31
-  * @param  ExtiLine This parameter can be one of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_17
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19
-  *         @arg @ref LL_EXTI_LINE_20
-  *         @arg @ref LL_EXTI_LINE_21
-  *         @arg @ref LL_EXTI_LINE_22
-  *         @arg @ref LL_EXTI_LINE_23
-  *         @arg @ref LL_EXTI_LINE_24
-  *         @arg @ref LL_EXTI_LINE_25
-  *         @arg @ref LL_EXTI_LINE_26
-  *         @arg @ref LL_EXTI_LINE_27
-  *         @arg @ref LL_EXTI_LINE_28
-  *         @arg @ref LL_EXTI_LINE_29
-  *         @arg @ref LL_EXTI_LINE_30
-  *         @arg @ref LL_EXTI_LINE_31
-  *         @arg @ref LL_EXTI_LINE_ALL_0_31
-  * @retval None
-  */
-__STATIC_INLINE void LL_C2_EXTI_DisableIT_0_31(uint32_t ExtiLine)
-{
-  CLEAR_BIT(EXTI->C2IMR1, ExtiLine);
-}
-
-
-
-/**
-  * @brief  Disable ExtiLine Interrupt request for Lines in range 32 to 63 for cpu2
-  * @rmtoll C2IMR2         IMx           LL_C2_EXTI_DisableIT_32_63
-  * @param  ExtiLine This parameter can be one of the following values:
-  *         @arg @ref LL_EXTI_LINE_32
-  *         @arg @ref LL_EXTI_LINE_33
-  *         @arg @ref LL_EXTI_LINE_34
-  *         @arg @ref LL_EXTI_LINE_35
-  *         @arg @ref LL_EXTI_LINE_36
-  *         @arg @ref LL_EXTI_LINE_37
-  *         @arg @ref LL_EXTI_LINE_38
-  *         @arg @ref LL_EXTI_LINE_39
-  *         @arg @ref LL_EXTI_LINE_40
-  *         @arg @ref LL_EXTI_LINE_41
-  *         @arg @ref LL_EXTI_LINE_42
-  *         @arg @ref LL_EXTI_LINE_43
-  *         @arg @ref LL_EXTI_LINE_44
-  *         @arg @ref LL_EXTI_LINE_46
-  *         @arg @ref LL_EXTI_LINE_47
-  *         @arg @ref LL_EXTI_LINE_48
-  *         @arg @ref LL_EXTI_LINE_49
-  *         @arg @ref LL_EXTI_LINE_50
-  *         @arg @ref LL_EXTI_LINE_51
-  *         @arg @ref LL_EXTI_LINE_52
-  *         @arg @ref LL_EXTI_LINE_53
-  *         @arg @ref LL_EXTI_LINE_54
-  *         @arg @ref LL_EXTI_LINE_55
-  *         @arg @ref LL_EXTI_LINE_56
-  *         @arg @ref LL_EXTI_LINE_57
-  *         @arg @ref LL_EXTI_LINE_58
-  *         @arg @ref LL_EXTI_LINE_59
-  *         @arg @ref LL_EXTI_LINE_60
-  *         @arg @ref LL_EXTI_LINE_61
-  *         @arg @ref LL_EXTI_LINE_62
-  *         @arg @ref LL_EXTI_LINE_63
-  *         @arg @ref LL_EXTI_LINE_ALL_32_63
-  * @retval None
-  */
-__STATIC_INLINE void LL_C2_EXTI_DisableIT_32_63(uint32_t ExtiLine)
-{
-  CLEAR_BIT(EXTI->C2IMR2, ExtiLine);
-}
-
-
-/**
-  * @brief  Disable ExtiLine Interrupt request for Lines in range 64 to 95 for cpu2
-  * @rmtoll C2IMR3         IMx           LL_C2_EXTI_DisableIT_64_95
-  * @param  ExtiLine This parameter can be one of the following values:
-  *         @arg @ref LL_EXTI_LINE_64
-  *         @arg @ref LL_EXTI_LINE_65
-  *         @arg @ref LL_EXTI_LINE_66
-  *         @arg @ref LL_EXTI_LINE_67
-  *         @arg @ref LL_EXTI_LINE_68
-  *         @arg @ref LL_EXTI_LINE_69
-  *         @arg @ref LL_EXTI_LINE_70
-  *         @arg @ref LL_EXTI_LINE_71
-  *         @arg @ref LL_EXTI_LINE_72
-  *         @arg @ref LL_EXTI_LINE_73
-  *         @arg @ref LL_EXTI_LINE_74
-  *         @arg @ref LL_EXTI_LINE_75
-  *         @arg @ref LL_EXTI_LINE_76
-  *         @arg @ref LL_EXTI_LINE_77
-  *         @arg @ref LL_EXTI_LINE_78
-  *         @arg @ref LL_EXTI_LINE_79
-  *         @arg @ref LL_EXTI_LINE_80
-  *         @arg @ref LL_EXTI_LINE_82
-  *         @arg @ref LL_EXTI_LINE_84
-  *         @arg @ref LL_EXTI_LINE_85
-  *         @arg @ref LL_EXTI_LINE_86
-  *         @arg @ref LL_EXTI_LINE_87
-  *         @arg @ref LL_EXTI_LINE_ALL_64_95
-  * @retval None
-  */
-__STATIC_INLINE void LL_C2_EXTI_DisableIT_64_95(uint32_t ExtiLine)
-{
-  CLEAR_BIT(EXTI->C2IMR3, ExtiLine);
-}
-
-
-/**
-  * @brief  Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31 for cpu2
-  * @rmtoll C2IMR1         IMx           LL_C2_EXTI_IsEnabledIT_0_31
-  * @param  ExtiLine This parameter can be one of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_17
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19
-  *         @arg @ref LL_EXTI_LINE_20
-  *         @arg @ref LL_EXTI_LINE_21
-  *         @arg @ref LL_EXTI_LINE_22
-  *         @arg @ref LL_EXTI_LINE_23
-  *         @arg @ref LL_EXTI_LINE_24
-  *         @arg @ref LL_EXTI_LINE_25
-  *         @arg @ref LL_EXTI_LINE_26
-  *         @arg @ref LL_EXTI_LINE_27
-  *         @arg @ref LL_EXTI_LINE_28
-  *         @arg @ref LL_EXTI_LINE_29
-  *         @arg @ref LL_EXTI_LINE_30
-  *         @arg @ref LL_EXTI_LINE_31
-  *         @arg @ref LL_EXTI_LINE_ALL_0_31
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine)
-{
-  return ((READ_BIT(EXTI->C2IMR1, ExtiLine) == (ExtiLine)) ? 1U : 0U);
-}
-
-
-/**
-  * @brief  Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63 for cpu2
-  * @rmtoll C2IMR2         IMx           LL_C2_EXTI_IsEnabledIT_32_63
-  * @param  ExtiLine This parameter can be one of the following values:
-  *         @arg @ref LL_EXTI_LINE_32
-  *         @arg @ref LL_EXTI_LINE_33
-  *         @arg @ref LL_EXTI_LINE_34
-  *         @arg @ref LL_EXTI_LINE_35
-  *         @arg @ref LL_EXTI_LINE_36
-  *         @arg @ref LL_EXTI_LINE_37
-  *         @arg @ref LL_EXTI_LINE_38
-  *         @arg @ref LL_EXTI_LINE_39
-  *         @arg @ref LL_EXTI_LINE_40
-  *         @arg @ref LL_EXTI_LINE_41
-  *         @arg @ref LL_EXTI_LINE_42
-  *         @arg @ref LL_EXTI_LINE_43
-  *         @arg @ref LL_EXTI_LINE_44
-  *         @arg @ref LL_EXTI_LINE_46
-  *         @arg @ref LL_EXTI_LINE_47
-  *         @arg @ref LL_EXTI_LINE_48
-  *         @arg @ref LL_EXTI_LINE_49
-  *         @arg @ref LL_EXTI_LINE_50
-  *         @arg @ref LL_EXTI_LINE_51
-  *         @arg @ref LL_EXTI_LINE_52
-  *         @arg @ref LL_EXTI_LINE_53
-  *         @arg @ref LL_EXTI_LINE_54
-  *         @arg @ref LL_EXTI_LINE_55
-  *         @arg @ref LL_EXTI_LINE_56
-  *         @arg @ref LL_EXTI_LINE_57
-  *         @arg @ref LL_EXTI_LINE_58
-  *         @arg @ref LL_EXTI_LINE_59
-  *         @arg @ref LL_EXTI_LINE_60
-  *         @arg @ref LL_EXTI_LINE_61
-  *         @arg @ref LL_EXTI_LINE_62
-  *         @arg @ref LL_EXTI_LINE_63
-  *         @arg @ref LL_EXTI_LINE_ALL_32_63
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledIT_32_63(uint32_t ExtiLine)
-{
-  return ((READ_BIT(EXTI->C2IMR2, ExtiLine) == (ExtiLine))? 1U : 0U);
-}
-
-
-/**
-  * @brief  Indicate if ExtiLine Interrupt request is enabled for Lines in range 64 to 95
-  * @rmtoll C2IMR3         IMx           LL_C2_EXTI_IsEnabledIT_64_95
-  * @param  ExtiLine This parameter can be one of the following values:
-  *         @arg @ref LL_EXTI_LINE_64
-  *         @arg @ref LL_EXTI_LINE_65
-  *         @arg @ref LL_EXTI_LINE_66
-  *         @arg @ref LL_EXTI_LINE_67
-  *         @arg @ref LL_EXTI_LINE_68
-  *         @arg @ref LL_EXTI_LINE_69
-  *         @arg @ref LL_EXTI_LINE_70
-  *         @arg @ref LL_EXTI_LINE_71
-  *         @arg @ref LL_EXTI_LINE_72
-  *         @arg @ref LL_EXTI_LINE_73
-  *         @arg @ref LL_EXTI_LINE_74
-  *         @arg @ref LL_EXTI_LINE_75
-  *         @arg @ref LL_EXTI_LINE_76
-  *         @arg @ref LL_EXTI_LINE_77
-  *         @arg @ref LL_EXTI_LINE_78
-  *         @arg @ref LL_EXTI_LINE_79
-  *         @arg @ref LL_EXTI_LINE_80
-  *         @arg @ref LL_EXTI_LINE_82
-  *         @arg @ref LL_EXTI_LINE_84
-  *         @arg @ref LL_EXTI_LINE_85
-  *         @arg @ref LL_EXTI_LINE_86
-  *         @arg @ref LL_EXTI_LINE_87
-  *         @arg @ref LL_EXTI_LINE_ALL_64_95
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledIT_64_95(uint32_t ExtiLine)
-{
-  return ((READ_BIT(EXTI->C2IMR3, ExtiLine) == (ExtiLine)) ? 1U : 0U);
-}
-
-#endif /* DUAL_CORE */
-
-
-/**
-  * @}
-  */
-
-/** @defgroup EXTI_LL_EF_Event_Management Event_Management
-  * @{
-  */
-
-/**
-  * @brief  Enable ExtiLine Event request for Lines in range 0 to 31
-  * @rmtoll EMR1         EMx           LL_EXTI_EnableEvent_0_31
-  * @param  ExtiLine This parameter can be one of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_17
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19
-  *         @arg @ref LL_EXTI_LINE_20
-  *         @arg @ref LL_EXTI_LINE_21
-  *         @arg @ref LL_EXTI_LINE_22
-  *         @arg @ref LL_EXTI_LINE_23
-  *         @arg @ref LL_EXTI_LINE_24
-  *         @arg @ref LL_EXTI_LINE_25
-  *         @arg @ref LL_EXTI_LINE_26
-  *         @arg @ref LL_EXTI_LINE_27
-  *         @arg @ref LL_EXTI_LINE_28
-  *         @arg @ref LL_EXTI_LINE_29
-  *         @arg @ref LL_EXTI_LINE_30
-  *         @arg @ref LL_EXTI_LINE_31
-  *         @arg @ref LL_EXTI_LINE_ALL_0_31
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine)
-{
-  SET_BIT(EXTI->EMR1, ExtiLine);
-}
-
-/**
-  * @brief  Enable ExtiLine Event request for Lines in range 32 to 63
-  * @rmtoll EMR2         EMx           LL_EXTI_EnableEvent_32_63
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_32
-  *         @arg @ref LL_EXTI_LINE_33
-  *         @arg @ref LL_EXTI_LINE_34
-  *         @arg @ref LL_EXTI_LINE_35
-  *         @arg @ref LL_EXTI_LINE_36
-  *         @arg @ref LL_EXTI_LINE_37
-  *         @arg @ref LL_EXTI_LINE_38
-  *         @arg @ref LL_EXTI_LINE_39
-  *         @arg @ref LL_EXTI_LINE_40
-  *         @arg @ref LL_EXTI_LINE_41
-  *         @arg @ref LL_EXTI_LINE_42
-  *         @arg @ref LL_EXTI_LINE_43
-  *         @arg @ref LL_EXTI_LINE_44 (*)
-  *         @arg @ref LL_EXTI_LINE_46 (*)
-  *         @arg @ref LL_EXTI_LINE_47
-  *         @arg @ref LL_EXTI_LINE_48
-  *         @arg @ref LL_EXTI_LINE_49
-  *         @arg @ref LL_EXTI_LINE_50
-  *         @arg @ref LL_EXTI_LINE_51
-  *         @arg @ref LL_EXTI_LINE_52
-  *         @arg @ref LL_EXTI_LINE_53
-  *         @arg @ref LL_EXTI_LINE_54
-  *         @arg @ref LL_EXTI_LINE_55
-  *         @arg @ref LL_EXTI_LINE_56
-  *         @arg @ref LL_EXTI_LINE_57 (*)
-  *         @arg @ref LL_EXTI_LINE_58
-  *         @arg @ref LL_EXTI_LINE_59 (*)
-  *         @arg @ref LL_EXTI_LINE_60
-  *         @arg @ref LL_EXTI_LINE_61
-  *         @arg @ref LL_EXTI_LINE_62
-  *         @arg @ref LL_EXTI_LINE_63
-  *         @arg @ref LL_EXTI_LINE_ALL_32_63
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_EnableEvent_32_63(uint32_t ExtiLine)
-{
-  SET_BIT(EXTI->EMR2, ExtiLine);
-}
-
-/**
-  * @brief  Enable ExtiLine Event request for Lines in range 64 to 95
-  * @rmtoll EMR3         EMx           LL_EXTI_EnableEvent_64_95
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_64
-  *         @arg @ref LL_EXTI_LINE_65
-  *         @arg @ref LL_EXTI_LINE_66
-  *         @arg @ref LL_EXTI_LINE_67
-  *         @arg @ref LL_EXTI_LINE_68
-  *         @arg @ref LL_EXTI_LINE_69
-  *         @arg @ref LL_EXTI_LINE_70
-  *         @arg @ref LL_EXTI_LINE_71
-  *         @arg @ref LL_EXTI_LINE_72
-  *         @arg @ref LL_EXTI_LINE_73
-  *         @arg @ref LL_EXTI_LINE_74
-  *         @arg @ref LL_EXTI_LINE_75 (*)
-  *         @arg @ref LL_EXTI_LINE_76 (*)
-  *         @arg @ref LL_EXTI_LINE_77 (**)
-  *         @arg @ref LL_EXTI_LINE_78 (**)
-  *         @arg @ref LL_EXTI_LINE_79 (**)
-  *         @arg @ref LL_EXTI_LINE_80 (**)
-  *         @arg @ref LL_EXTI_LINE_82 (**)
-  *         @arg @ref LL_EXTI_LINE_84 (**)
-  *         @arg @ref LL_EXTI_LINE_85
-  *         @arg @ref LL_EXTI_LINE_86 (*)
-  *         @arg @ref LL_EXTI_LINE_87
-  *         @arg @ref LL_EXTI_LINE_88 (*)
-  *         @arg @ref LL_EXTI_LINE_89 (*)
-  *         @arg @ref LL_EXTI_LINE_90 (*)
-  *         @arg @ref LL_EXTI_LINE_91 (*)
-  *         @arg @ref LL_EXTI_LINE_ALL_64_95
-  *
-  *         (*) value not defined in all devices.
-  *         (**) value only defined in dual core devices.
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_EnableEvent_64_95(uint32_t ExtiLine)
-{
-  SET_BIT(EXTI->EMR3, ExtiLine);
-}
-
-/**
-  * @brief  Disable ExtiLine Event request for Lines in range 0 to 31
-  * @rmtoll EMR1         EMx           LL_EXTI_DisableEvent_0_31
-  * @param  ExtiLine This parameter can be one of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_17
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19
-  *         @arg @ref LL_EXTI_LINE_20
-  *         @arg @ref LL_EXTI_LINE_21
-  *         @arg @ref LL_EXTI_LINE_22
-  *         @arg @ref LL_EXTI_LINE_23
-  *         @arg @ref LL_EXTI_LINE_24
-  *         @arg @ref LL_EXTI_LINE_25
-  *         @arg @ref LL_EXTI_LINE_26
-  *         @arg @ref LL_EXTI_LINE_27
-  *         @arg @ref LL_EXTI_LINE_28
-  *         @arg @ref LL_EXTI_LINE_29
-  *         @arg @ref LL_EXTI_LINE_30
-  *         @arg @ref LL_EXTI_LINE_31
-  *         @arg @ref LL_EXTI_LINE_ALL_0_31
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine)
-{
-  CLEAR_BIT(EXTI->EMR1, ExtiLine);
-}
-
-/**
-  * @brief  Disable ExtiLine Event request for Lines in range 32 to 63
-  * @rmtoll EMR2         EMx           LL_EXTI_DisableEvent_32_63
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_32
-  *         @arg @ref LL_EXTI_LINE_33
-  *         @arg @ref LL_EXTI_LINE_34
-  *         @arg @ref LL_EXTI_LINE_35
-  *         @arg @ref LL_EXTI_LINE_36
-  *         @arg @ref LL_EXTI_LINE_37
-  *         @arg @ref LL_EXTI_LINE_38
-  *         @arg @ref LL_EXTI_LINE_39
-  *         @arg @ref LL_EXTI_LINE_40
-  *         @arg @ref LL_EXTI_LINE_41
-  *         @arg @ref LL_EXTI_LINE_42
-  *         @arg @ref LL_EXTI_LINE_43
-  *         @arg @ref LL_EXTI_LINE_44 (*)
-  *         @arg @ref LL_EXTI_LINE_46 (*)
-  *         @arg @ref LL_EXTI_LINE_47
-  *         @arg @ref LL_EXTI_LINE_48
-  *         @arg @ref LL_EXTI_LINE_49
-  *         @arg @ref LL_EXTI_LINE_50
-  *         @arg @ref LL_EXTI_LINE_51
-  *         @arg @ref LL_EXTI_LINE_52
-  *         @arg @ref LL_EXTI_LINE_53
-  *         @arg @ref LL_EXTI_LINE_54
-  *         @arg @ref LL_EXTI_LINE_55
-  *         @arg @ref LL_EXTI_LINE_56
-  *         @arg @ref LL_EXTI_LINE_57 (*)
-  *         @arg @ref LL_EXTI_LINE_58
-  *         @arg @ref LL_EXTI_LINE_59 (*)
-  *         @arg @ref LL_EXTI_LINE_60
-  *         @arg @ref LL_EXTI_LINE_61
-  *         @arg @ref LL_EXTI_LINE_62
-  *         @arg @ref LL_EXTI_LINE_63
-  *         @arg @ref LL_EXTI_LINE_ALL_32_63
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_DisableEvent_32_63(uint32_t ExtiLine)
-{
-  CLEAR_BIT(EXTI->EMR2, ExtiLine);
-}
-
-/**
-  * @brief  Disable ExtiLine Event request for Lines in range 64 to 95
-  * @rmtoll EMR3         EMx           LL_EXTI_DisableEvent_64_95
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_64
-  *         @arg @ref LL_EXTI_LINE_65
-  *         @arg @ref LL_EXTI_LINE_66
-  *         @arg @ref LL_EXTI_LINE_67
-  *         @arg @ref LL_EXTI_LINE_68
-  *         @arg @ref LL_EXTI_LINE_69
-  *         @arg @ref LL_EXTI_LINE_70
-  *         @arg @ref LL_EXTI_LINE_71
-  *         @arg @ref LL_EXTI_LINE_72
-  *         @arg @ref LL_EXTI_LINE_73
-  *         @arg @ref LL_EXTI_LINE_74
-  *         @arg @ref LL_EXTI_LINE_75 (*)
-  *         @arg @ref LL_EXTI_LINE_76 (*)
-  *         @arg @ref LL_EXTI_LINE_77 (**)
-  *         @arg @ref LL_EXTI_LINE_78 (**)
-  *         @arg @ref LL_EXTI_LINE_79 (**)
-  *         @arg @ref LL_EXTI_LINE_80 (**)
-  *         @arg @ref LL_EXTI_LINE_82 (**)
-  *         @arg @ref LL_EXTI_LINE_84 (**)
-  *         @arg @ref LL_EXTI_LINE_85
-  *         @arg @ref LL_EXTI_LINE_86 (*)
-  *         @arg @ref LL_EXTI_LINE_87
-  *         @arg @ref LL_EXTI_LINE_88 (*)
-  *         @arg @ref LL_EXTI_LINE_89 (*)
-  *         @arg @ref LL_EXTI_LINE_90 (*)
-  *         @arg @ref LL_EXTI_LINE_91 (*)
-  *         @arg @ref LL_EXTI_LINE_ALL_64_95
-  *
-  *         (*) value not defined in all devices.
-  *         (**) value only defined in dual core devices.
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_DisableEvent_64_95(uint32_t ExtiLine)
-{
-  CLEAR_BIT(EXTI->EMR3, ExtiLine);
-}
-
-/**
-  * @brief  Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31
-  * @rmtoll EMR1         EMx           LL_EXTI_IsEnabledEvent_0_31
-  * @param  ExtiLine This parameter can be one of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_17
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19
-  *         @arg @ref LL_EXTI_LINE_20
-  *         @arg @ref LL_EXTI_LINE_21
-  *         @arg @ref LL_EXTI_LINE_22
-  *         @arg @ref LL_EXTI_LINE_23
-  *         @arg @ref LL_EXTI_LINE_24
-  *         @arg @ref LL_EXTI_LINE_25
-  *         @arg @ref LL_EXTI_LINE_26
-  *         @arg @ref LL_EXTI_LINE_27
-  *         @arg @ref LL_EXTI_LINE_28
-  *         @arg @ref LL_EXTI_LINE_29
-  *         @arg @ref LL_EXTI_LINE_30
-  *         @arg @ref LL_EXTI_LINE_31
-  *         @arg @ref LL_EXTI_LINE_ALL_0_31
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine)
-{
-  return ((READ_BIT(EXTI->EMR1, ExtiLine) == (ExtiLine)) ? 1U : 0U);
-}
-
-/**
-  * @brief  Indicate if ExtiLine Event request is enabled for Lines in range 32 to 63
-  * @rmtoll EMR2         EMx           LL_EXTI_IsEnabledEvent_32_63
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_32
-  *         @arg @ref LL_EXTI_LINE_33
-  *         @arg @ref LL_EXTI_LINE_34
-  *         @arg @ref LL_EXTI_LINE_35
-  *         @arg @ref LL_EXTI_LINE_36
-  *         @arg @ref LL_EXTI_LINE_37
-  *         @arg @ref LL_EXTI_LINE_38
-  *         @arg @ref LL_EXTI_LINE_39
-  *         @arg @ref LL_EXTI_LINE_40
-  *         @arg @ref LL_EXTI_LINE_41
-  *         @arg @ref LL_EXTI_LINE_42
-  *         @arg @ref LL_EXTI_LINE_43
-  *         @arg @ref LL_EXTI_LINE_44 (*)
-  *         @arg @ref LL_EXTI_LINE_46 (*)
-  *         @arg @ref LL_EXTI_LINE_47
-  *         @arg @ref LL_EXTI_LINE_48
-  *         @arg @ref LL_EXTI_LINE_49
-  *         @arg @ref LL_EXTI_LINE_50
-  *         @arg @ref LL_EXTI_LINE_51
-  *         @arg @ref LL_EXTI_LINE_52
-  *         @arg @ref LL_EXTI_LINE_53
-  *         @arg @ref LL_EXTI_LINE_54
-  *         @arg @ref LL_EXTI_LINE_55
-  *         @arg @ref LL_EXTI_LINE_56
-  *         @arg @ref LL_EXTI_LINE_57 (*)
-  *         @arg @ref LL_EXTI_LINE_58
-  *         @arg @ref LL_EXTI_LINE_59 (*)
-  *         @arg @ref LL_EXTI_LINE_60
-  *         @arg @ref LL_EXTI_LINE_61
-  *         @arg @ref LL_EXTI_LINE_62
-  *         @arg @ref LL_EXTI_LINE_63
-  *         @arg @ref LL_EXTI_LINE_ALL_32_63
-  *
-  *         (*) value not defined in all devices.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_32_63(uint32_t ExtiLine)
-{
-  return ((READ_BIT(EXTI->EMR2, ExtiLine) == (ExtiLine)) ? 1U : 0U);
-}
-
-/**
-  * @brief  Indicate if ExtiLine Event request is enabled for Lines in range 64 to 95
-  * @rmtoll EMR3         EMx           LL_EXTI_IsEnabledEvent_64_95
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_64
-  *         @arg @ref LL_EXTI_LINE_65
-  *         @arg @ref LL_EXTI_LINE_66
-  *         @arg @ref LL_EXTI_LINE_67
-  *         @arg @ref LL_EXTI_LINE_68
-  *         @arg @ref LL_EXTI_LINE_69
-  *         @arg @ref LL_EXTI_LINE_70
-  *         @arg @ref LL_EXTI_LINE_71
-  *         @arg @ref LL_EXTI_LINE_72
-  *         @arg @ref LL_EXTI_LINE_73
-  *         @arg @ref LL_EXTI_LINE_74
-  *         @arg @ref LL_EXTI_LINE_75 (*)
-  *         @arg @ref LL_EXTI_LINE_76 (*)
-  *         @arg @ref LL_EXTI_LINE_77 (**)
-  *         @arg @ref LL_EXTI_LINE_78 (**)
-  *         @arg @ref LL_EXTI_LINE_79 (**)
-  *         @arg @ref LL_EXTI_LINE_80 (**)
-  *         @arg @ref LL_EXTI_LINE_82 (**)
-  *         @arg @ref LL_EXTI_LINE_84 (**)
-  *         @arg @ref LL_EXTI_LINE_85
-  *         @arg @ref LL_EXTI_LINE_86 (*)
-  *         @arg @ref LL_EXTI_LINE_87
-  *         @arg @ref LL_EXTI_LINE_88 (*)
-  *         @arg @ref LL_EXTI_LINE_89 (*)
-  *         @arg @ref LL_EXTI_LINE_90 (*)
-  *         @arg @ref LL_EXTI_LINE_91 (*)
-  *         @arg @ref LL_EXTI_LINE_ALL_64_95
-  *
-  *         (*) value not defined in all devices.
-  *         (**) value only defined in dual core devices.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_64_95(uint32_t ExtiLine)
-{
-  return ((READ_BIT(EXTI->EMR3, ExtiLine) == (ExtiLine)) ? 1U : 0U);
-}
-
-#if defined(DUAL_CORE)
-
-/**
-  * @brief  Enable ExtiLine Event request for Lines in range 0 to 31 for cpu2
-  * @rmtoll C2EMR1         EMx           LL_C2_EXTI_EnableEvent_0_31
-  * @param  ExtiLine This parameter can be one of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_17
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19
-  *         @arg @ref LL_EXTI_LINE_20
-  *         @arg @ref LL_EXTI_LINE_21
-  *         @arg @ref LL_EXTI_LINE_22
-  *         @arg @ref LL_EXTI_LINE_23
-  *         @arg @ref LL_EXTI_LINE_24
-  *         @arg @ref LL_EXTI_LINE_25
-  *         @arg @ref LL_EXTI_LINE_26
-  *         @arg @ref LL_EXTI_LINE_27
-  *         @arg @ref LL_EXTI_LINE_28
-  *         @arg @ref LL_EXTI_LINE_29
-  *         @arg @ref LL_EXTI_LINE_30
-  *         @arg @ref LL_EXTI_LINE_31
-  *         @arg @ref LL_EXTI_LINE_ALL_0_31
-  * @retval None
-  */
-__STATIC_INLINE void LL_C2_EXTI_EnableEvent_0_31(uint32_t ExtiLine)
-{
-  SET_BIT(EXTI->C2EMR1, ExtiLine);
-}
-
-
-/**
-  * @brief  Enable ExtiLine Event request for Lines in range 32 to 63 for cpu2
-  * @rmtoll C2EMR2         EMx           LL_C2_EXTI_EnableEvent_32_63
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_32
-  *         @arg @ref LL_EXTI_LINE_33
-  *         @arg @ref LL_EXTI_LINE_34
-  *         @arg @ref LL_EXTI_LINE_35
-  *         @arg @ref LL_EXTI_LINE_36
-  *         @arg @ref LL_EXTI_LINE_37
-  *         @arg @ref LL_EXTI_LINE_38
-  *         @arg @ref LL_EXTI_LINE_39
-  *         @arg @ref LL_EXTI_LINE_40
-  *         @arg @ref LL_EXTI_LINE_41
-  *         @arg @ref LL_EXTI_LINE_42
-  *         @arg @ref LL_EXTI_LINE_43
-  *         @arg @ref LL_EXTI_LINE_44
-  *         @arg @ref LL_EXTI_LINE_46
-  *         @arg @ref LL_EXTI_LINE_47
-  *         @arg @ref LL_EXTI_LINE_48
-  *         @arg @ref LL_EXTI_LINE_49
-  *         @arg @ref LL_EXTI_LINE_50
-  *         @arg @ref LL_EXTI_LINE_51
-  *         @arg @ref LL_EXTI_LINE_52
-  *         @arg @ref LL_EXTI_LINE_53
-  *         @arg @ref LL_EXTI_LINE_54
-  *         @arg @ref LL_EXTI_LINE_55
-  *         @arg @ref LL_EXTI_LINE_56
-  *         @arg @ref LL_EXTI_LINE_57
-  *         @arg @ref LL_EXTI_LINE_58
-  *         @arg @ref LL_EXTI_LINE_59
-  *         @arg @ref LL_EXTI_LINE_60
-  *         @arg @ref LL_EXTI_LINE_61
-  *         @arg @ref LL_EXTI_LINE_62
-  *         @arg @ref LL_EXTI_LINE_63
-  *         @arg @ref LL_EXTI_LINE_ALL_32_63
-  * @retval None
-  */
-__STATIC_INLINE void LL_C2_EXTI_EnableEvent_32_63(uint32_t ExtiLine)
-{
-  SET_BIT(EXTI->C2EMR2, ExtiLine);
-}
-
-/**
-  * @brief  Enable ExtiLine Event request for Lines in range 64 to 95 for cpu2
-  * @rmtoll C2EMR3         EMx           LL_C2_EXTI_EnableEvent_64_95
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_64
-  *         @arg @ref LL_EXTI_LINE_65
-  *         @arg @ref LL_EXTI_LINE_66
-  *         @arg @ref LL_EXTI_LINE_67
-  *         @arg @ref LL_EXTI_LINE_68
-  *         @arg @ref LL_EXTI_LINE_69
-  *         @arg @ref LL_EXTI_LINE_70
-  *         @arg @ref LL_EXTI_LINE_71
-  *         @arg @ref LL_EXTI_LINE_72
-  *         @arg @ref LL_EXTI_LINE_73
-  *         @arg @ref LL_EXTI_LINE_74
-  *         @arg @ref LL_EXTI_LINE_75
-  *         @arg @ref LL_EXTI_LINE_76
-  *         @arg @ref LL_EXTI_LINE_77
-  *         @arg @ref LL_EXTI_LINE_78
-  *         @arg @ref LL_EXTI_LINE_79
-  *         @arg @ref LL_EXTI_LINE_80
-  *         @arg @ref LL_EXTI_LINE_82
-  *         @arg @ref LL_EXTI_LINE_84
-  *         @arg @ref LL_EXTI_LINE_85
-  *         @arg @ref LL_EXTI_LINE_86
-  *         @arg @ref LL_EXTI_LINE_87
-  *         @arg @ref LL_EXTI_LINE_ALL_64_95
-  * @retval None
-  */
-__STATIC_INLINE void LL_C2_EXTI_EnableEvent_64_95(uint32_t ExtiLine)
-{
-  SET_BIT(EXTI->C2EMR3, ExtiLine);
-}
-
-
-/**
-  * @brief  Disable ExtiLine Event request for Lines in range 0 to 31 for cpu2
-  * @rmtoll C2EMR1         EMx           LL_C2_EXTI_DisableEvent_0_31
-  * @param  ExtiLine This parameter can be one of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_17
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19
-  *         @arg @ref LL_EXTI_LINE_20
-  *         @arg @ref LL_EXTI_LINE_21
-  *         @arg @ref LL_EXTI_LINE_22
-  *         @arg @ref LL_EXTI_LINE_23
-  *         @arg @ref LL_EXTI_LINE_24
-  *         @arg @ref LL_EXTI_LINE_25
-  *         @arg @ref LL_EXTI_LINE_26
-  *         @arg @ref LL_EXTI_LINE_27
-  *         @arg @ref LL_EXTI_LINE_28
-  *         @arg @ref LL_EXTI_LINE_29
-  *         @arg @ref LL_EXTI_LINE_30
-  *         @arg @ref LL_EXTI_LINE_31
-  *         @arg @ref LL_EXTI_LINE_ALL_0_31
-  * @retval None
-  */
-__STATIC_INLINE void LL_C2_EXTI_DisableEvent_0_31(uint32_t ExtiLine)
-{
-  CLEAR_BIT(EXTI->C2EMR1, ExtiLine);
-}
-
-
-/**
-  * @brief  Disable ExtiLine Event request for Lines in range 32 to 63 for cpu2
-  * @rmtoll C2EMR2         EMx           LL_C2_EXTI_DisableEvent_32_63
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_32
-  *         @arg @ref LL_EXTI_LINE_33
-  *         @arg @ref LL_EXTI_LINE_34
-  *         @arg @ref LL_EXTI_LINE_35
-  *         @arg @ref LL_EXTI_LINE_36
-  *         @arg @ref LL_EXTI_LINE_37
-  *         @arg @ref LL_EXTI_LINE_38
-  *         @arg @ref LL_EXTI_LINE_39
-  *         @arg @ref LL_EXTI_LINE_40
-  *         @arg @ref LL_EXTI_LINE_41
-  *         @arg @ref LL_EXTI_LINE_42
-  *         @arg @ref LL_EXTI_LINE_43
-  *         @arg @ref LL_EXTI_LINE_44
-  *         @arg @ref LL_EXTI_LINE_46
-  *         @arg @ref LL_EXTI_LINE_47
-  *         @arg @ref LL_EXTI_LINE_48
-  *         @arg @ref LL_EXTI_LINE_49
-  *         @arg @ref LL_EXTI_LINE_50
-  *         @arg @ref LL_EXTI_LINE_51
-  *         @arg @ref LL_EXTI_LINE_52
-  *         @arg @ref LL_EXTI_LINE_53
-  *         @arg @ref LL_EXTI_LINE_54
-  *         @arg @ref LL_EXTI_LINE_55
-  *         @arg @ref LL_EXTI_LINE_56
-  *         @arg @ref LL_EXTI_LINE_57
-  *         @arg @ref LL_EXTI_LINE_58
-  *         @arg @ref LL_EXTI_LINE_59
-  *         @arg @ref LL_EXTI_LINE_60
-  *         @arg @ref LL_EXTI_LINE_61
-  *         @arg @ref LL_EXTI_LINE_62
-  *         @arg @ref LL_EXTI_LINE_63
-  *         @arg @ref LL_EXTI_LINE_ALL_32_63
-  * @retval None
-  */
-__STATIC_INLINE void LL_C2_EXTI_DisableEvent_32_63(uint32_t ExtiLine)
-{
-  CLEAR_BIT(EXTI->C2EMR2, ExtiLine);
-}
-
-
-/**
-  * @brief  Disable ExtiLine Event request for Lines in range 64 to 95 for cpu2
-  * @rmtoll C2EMR3         EMx           LL_C2_EXTI_DisableEvent_64_95
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_64
-  *         @arg @ref LL_EXTI_LINE_65
-  *         @arg @ref LL_EXTI_LINE_66
-  *         @arg @ref LL_EXTI_LINE_67
-  *         @arg @ref LL_EXTI_LINE_68
-  *         @arg @ref LL_EXTI_LINE_69
-  *         @arg @ref LL_EXTI_LINE_70
-  *         @arg @ref LL_EXTI_LINE_71
-  *         @arg @ref LL_EXTI_LINE_72
-  *         @arg @ref LL_EXTI_LINE_73
-  *         @arg @ref LL_EXTI_LINE_74
-  *         @arg @ref LL_EXTI_LINE_75
-  *         @arg @ref LL_EXTI_LINE_76
-  *         @arg @ref LL_EXTI_LINE_77
-  *         @arg @ref LL_EXTI_LINE_78
-  *         @arg @ref LL_EXTI_LINE_79
-  *         @arg @ref LL_EXTI_LINE_80
-  *         @arg @ref LL_EXTI_LINE_82
-  *         @arg @ref LL_EXTI_LINE_84
-  *         @arg @ref LL_EXTI_LINE_85
-  *         @arg @ref LL_EXTI_LINE_86
-  *         @arg @ref LL_EXTI_LINE_87
-  *         @arg @ref LL_EXTI_LINE_ALL_64_95
-  * @retval None
-  */
-__STATIC_INLINE void LL_C2_EXTI_DisableEvent_64_95(uint32_t ExtiLine)
-{
-  CLEAR_BIT(EXTI->C2EMR3, ExtiLine);
-}
-
-
-/**
-  * @brief  Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31 for cpu2
-  * @rmtoll C2EMR1         EMx           LL_C2_EXTI_IsEnabledEvent_0_31
-  * @param  ExtiLine This parameter can be one of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_17
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19
-  *         @arg @ref LL_EXTI_LINE_20
-  *         @arg @ref LL_EXTI_LINE_21
-  *         @arg @ref LL_EXTI_LINE_22
-  *         @arg @ref LL_EXTI_LINE_23
-  *         @arg @ref LL_EXTI_LINE_24
-  *         @arg @ref LL_EXTI_LINE_25
-  *         @arg @ref LL_EXTI_LINE_26
-  *         @arg @ref LL_EXTI_LINE_27
-  *         @arg @ref LL_EXTI_LINE_28
-  *         @arg @ref LL_EXTI_LINE_29
-  *         @arg @ref LL_EXTI_LINE_30
-  *         @arg @ref LL_EXTI_LINE_31
-  *         @arg @ref LL_EXTI_LINE_ALL_0_31
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine)
-{
-  return ((READ_BIT(EXTI->C2EMR1, ExtiLine) == (ExtiLine)) ? 1U : 0U);
-}
-
-
-/**
-  * @brief  Indicate if ExtiLine Event request is enabled for Lines in range 32 to 63 for cpu2
-  * @rmtoll C2EMR2         EMx           LL_C2_EXTI_IsEnabledEvent_32_63
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_32
-  *         @arg @ref LL_EXTI_LINE_33
-  *         @arg @ref LL_EXTI_LINE_34
-  *         @arg @ref LL_EXTI_LINE_35
-  *         @arg @ref LL_EXTI_LINE_36
-  *         @arg @ref LL_EXTI_LINE_37
-  *         @arg @ref LL_EXTI_LINE_38
-  *         @arg @ref LL_EXTI_LINE_39
-  *         @arg @ref LL_EXTI_LINE_40
-  *         @arg @ref LL_EXTI_LINE_41
-  *         @arg @ref LL_EXTI_LINE_42
-  *         @arg @ref LL_EXTI_LINE_43
-  *         @arg @ref LL_EXTI_LINE_44
-  *         @arg @ref LL_EXTI_LINE_46
-  *         @arg @ref LL_EXTI_LINE_47
-  *         @arg @ref LL_EXTI_LINE_48
-  *         @arg @ref LL_EXTI_LINE_49
-  *         @arg @ref LL_EXTI_LINE_50
-  *         @arg @ref LL_EXTI_LINE_51
-  *         @arg @ref LL_EXTI_LINE_52
-  *         @arg @ref LL_EXTI_LINE_53
-  *         @arg @ref LL_EXTI_LINE_54
-  *         @arg @ref LL_EXTI_LINE_55
-  *         @arg @ref LL_EXTI_LINE_56
-  *         @arg @ref LL_EXTI_LINE_57
-  *         @arg @ref LL_EXTI_LINE_58
-  *         @arg @ref LL_EXTI_LINE_59
-  *         @arg @ref LL_EXTI_LINE_60
-  *         @arg @ref LL_EXTI_LINE_61
-  *         @arg @ref LL_EXTI_LINE_62
-  *         @arg @ref LL_EXTI_LINE_63
-  *         @arg @ref LL_EXTI_LINE_ALL_32_63
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledEvent_32_63(uint32_t ExtiLine)
-{
-  return ((READ_BIT(EXTI->C2EMR2, ExtiLine) == (ExtiLine)) ? 1U : 0U);
-}
-
-
-/**
-  * @brief  Indicate if ExtiLine Event request is enabled for Lines in range 64 to 95 for cpu2
-  * @rmtoll C2EMR3         EMx           LL_C2_EXTI_IsEnabledEvent_64_95
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_64
-  *         @arg @ref LL_EXTI_LINE_65
-  *         @arg @ref LL_EXTI_LINE_66
-  *         @arg @ref LL_EXTI_LINE_67
-  *         @arg @ref LL_EXTI_LINE_68
-  *         @arg @ref LL_EXTI_LINE_69
-  *         @arg @ref LL_EXTI_LINE_70
-  *         @arg @ref LL_EXTI_LINE_71
-  *         @arg @ref LL_EXTI_LINE_72
-  *         @arg @ref LL_EXTI_LINE_73
-  *         @arg @ref LL_EXTI_LINE_74
-  *         @arg @ref LL_EXTI_LINE_75
-  *         @arg @ref LL_EXTI_LINE_76
-  *         @arg @ref LL_EXTI_LINE_77
-  *         @arg @ref LL_EXTI_LINE_78
-  *         @arg @ref LL_EXTI_LINE_79
-  *         @arg @ref LL_EXTI_LINE_80
-  *         @arg @ref LL_EXTI_LINE_82
-  *         @arg @ref LL_EXTI_LINE_84
-  *         @arg @ref LL_EXTI_LINE_85
-  *         @arg @ref LL_EXTI_LINE_86
-  *         @arg @ref LL_EXTI_LINE_87
-  *         @arg @ref LL_EXTI_LINE_ALL_64_95
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledEvent_64_95(uint32_t ExtiLine)
-{
-  return ((READ_BIT(EXTI->C2EMR3, ExtiLine) == (ExtiLine)) ? 1U : 0U);
-}
-
-
-#endif /* DUAL_CORE */
-
-/**
-  * @}
-  */
-
-/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management
-  * @{
-  */
-
-/**
-  * @brief  Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
-  * @note The configurable wakeup lines are edge-triggered. No glitch must be
-  *       generated on these lines. If a rising edge on a configurable interrupt
-  *       line occurs during a write operation in the EXTI_RTSR register, the
-  *       pending bit is not set.
-  *       Rising and falling edge triggers can be set for
-  *       the same interrupt line. In this case, both generate a trigger
-  *       condition.
-  * @rmtoll RTSR1        RTx           LL_EXTI_EnableRisingTrig_0_31
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_17
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19
-  *         @arg @ref LL_EXTI_LINE_20
-  *         @arg @ref LL_EXTI_LINE_21
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine)
-{
-  SET_BIT(EXTI->RTSR1, ExtiLine);
-
-}
-
-/**
-  * @brief  Enable ExtiLine Rising Edge Trigger for Lines in range 32 to 63
-  * @note The configurable wakeup lines are edge-triggered. No glitch must be
-  *       generated on these lines. If a rising edge on a configurable interrupt
-  *       line occurs during a write operation in the EXTI_RTSR register, the
-  *       pending bit is not set.Rising and falling edge triggers can be set for
-  *       the same interrupt line. In this case, both generate a trigger
-  *       condition.
-  * @rmtoll RTSR2        RTx           LL_EXTI_EnableRisingTrig_32_63
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_49
-  *         @arg @ref LL_EXTI_LINE_51
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_EnableRisingTrig_32_63(uint32_t ExtiLine)
-{
-  SET_BIT(EXTI->RTSR2, ExtiLine);
-}
-
-/**
-  * @brief  Enable ExtiLine Rising Edge Trigger for Lines in range 64 to 95
-  * @note The configurable wakeup lines are edge-triggered. No glitch must be
-  *       generated on these lines. If a rising edge on a configurable interrupt
-  *       line occurs during a write operation in the EXTI_RTSR register, the
-  *       pending bit is not set.Rising and falling edge triggers can be set for
-  *       the same interrupt line. In this case, both generate a trigger
-  *       condition.
-  * @rmtoll RTSR3        RTx           LL_EXTI_EnableRisingTrig_64_95
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_82 (*)
-  *         @arg @ref LL_EXTI_LINE_84 (*)
-  *         @arg @ref LL_EXTI_LINE_85
-  *         @arg @ref LL_EXTI_LINE_86 (**)
-  *
-  *         (*) value only defined in dual core devices.
-  *         (**) value not defined in all devices.
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_EnableRisingTrig_64_95(uint32_t ExtiLine)
-{
-  SET_BIT(EXTI->RTSR3, ExtiLine);
-}
-
-/**
-  * @brief  Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
-  * @note The configurable wakeup lines are edge-triggered. No glitch must be
-  *       generated on these lines. If a rising edge on a configurable interrupt
-  *       line occurs during a write operation in the EXTI_RTSR register, the
-  *       pending bit is not set.
-  *       Rising and falling edge triggers can be set for
-  *       the same interrupt line. In this case, both generate a trigger
-  *       condition.
-  * @rmtoll RTSR1        RTx           LL_EXTI_DisableRisingTrig_0_31
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_17
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19
-  *         @arg @ref LL_EXTI_LINE_20
-  *         @arg @ref LL_EXTI_LINE_21
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine)
-{
-  CLEAR_BIT(EXTI->RTSR1, ExtiLine);
-
-}
-
-/**
-  * @brief  Disable ExtiLine Rising Edge Trigger for Lines in range 32 to 63
-  * @note The configurable wakeup lines are edge-triggered. No glitch must be
-  *       generated on these lines. If a rising edge on a configurable interrupt
-  *       line occurs during a write operation in the EXTI_RTSR register, the
-  *       pending bit is not set.
-  *       Rising and falling edge triggers can be set for
-  *       the same interrupt line. In this case, both generate a trigger
-  *       condition.
-  * @rmtoll RTSR2        RTx           LL_EXTI_DisableRisingTrig_32_63
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_49
-  *         @arg @ref LL_EXTI_LINE_51
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_DisableRisingTrig_32_63(uint32_t ExtiLine)
-{
-  CLEAR_BIT(EXTI->RTSR2, ExtiLine);
-}
-
-/**
-  * @brief  Disable ExtiLine Rising Edge Trigger for Lines in range 64 to 95
-  * @note The configurable wakeup lines are edge-triggered. No glitch must be
-  *       generated on these lines. If a rising edge on a configurable interrupt
-  *       line occurs during a write operation in the EXTI_RTSR register, the
-  *       pending bit is not set.
-  *       Rising and falling edge triggers can be set for
-  *       the same interrupt line. In this case, both generate a trigger
-  *       condition.
-  * @rmtoll RTSR3        RTx           LL_EXTI_DisableRisingTrig_64_95
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_82 (*)
-  *         @arg @ref LL_EXTI_LINE_84 (*)
-  *         @arg @ref LL_EXTI_LINE_85
-  *         @arg @ref LL_EXTI_LINE_86 (**)
-  *
-  *         (*) value only defined in dual core devices.
-  *         (**) value not defined in all devices.
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_DisableRisingTrig_64_95(uint32_t ExtiLine)
-{
-  CLEAR_BIT(EXTI->RTSR3, ExtiLine);
-}
-
-/**
-  * @brief  Check if rising edge trigger is enabled for Lines in range 0 to 31
-  * @rmtoll RTSR1        RTx           LL_EXTI_IsEnabledRisingTrig_0_31
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_17
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19
-  *         @arg @ref LL_EXTI_LINE_20
-  *         @arg @ref LL_EXTI_LINE_21
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine)
-{
-  return ((READ_BIT(EXTI->RTSR1, ExtiLine) == (ExtiLine)) ? 1U : 0U);
-}
-
-
-/**
-  * @brief  Check if rising edge trigger is enabled for Lines in range 32 to 63
-  * @rmtoll RTSR2        RTx           LL_EXTI_IsEnabledRisingTrig_32_63
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_49
-  *         @arg @ref LL_EXTI_LINE_51
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_32_63(uint32_t ExtiLine)
-{
-  return ((READ_BIT(EXTI->RTSR2, ExtiLine) == (ExtiLine)) ? 1U : 0U);
-}
-
-/**
-  * @brief  Check if rising edge trigger is enabled for Lines in range 64 to 95
-  * @rmtoll RTSR3        RTx           LL_EXTI_IsEnabledRisingTrig_64_95
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_82 (*)
-  *         @arg @ref LL_EXTI_LINE_84 (*)
-  *         @arg @ref LL_EXTI_LINE_85
-  *         @arg @ref LL_EXTI_LINE_86 (**)
-  *
-  *         (*) value only defined in dual core devices.
-  *         (**) value not defined in all devices.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_64_95(uint32_t ExtiLine)
-{
-  return ((READ_BIT(EXTI->RTSR3, ExtiLine) == (ExtiLine)) ? 1U : 0U);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management
-  * @{
-  */
-
-/**
-  * @brief  Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
-  * @note The configurable wakeup lines are edge-triggered. No glitch must be
-  *       generated on these lines. If a falling edge on a configurable interrupt
-  *       line occurs during a write operation in the EXTI_FTSR register, the
-  *       pending bit is not set.
-  *       Rising and falling edge triggers can be set for
-  *       the same interrupt line. In this case, both generate a trigger
-  *       condition.
-  * @rmtoll FTSR1        FTx           LL_EXTI_EnableFallingTrig_0_31
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19
-  *         @arg @ref LL_EXTI_LINE_20
-  *         @arg @ref LL_EXTI_LINE_21
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine)
-{
-  SET_BIT(EXTI->FTSR1, ExtiLine);
-}
-
-/**
-  * @brief  Enable ExtiLine Falling Edge Trigger for Lines in range 32 to 63
-  * @note The configurable wakeup lines are edge-triggered. No glitch must be
-  *       generated on these lines. If a Falling edge on a configurable interrupt
-  *       line occurs during a write operation in the EXTI_FTSR register, the
-  *       pending bit is not set.
-  *       Rising and falling edge triggers can be set for
-  *       the same interrupt line. In this case, both generate a trigger
-  *       condition.
-  * @rmtoll FTSR2        FTx           LL_EXTI_EnableFallingTrig_32_63
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_49
-  *         @arg @ref LL_EXTI_LINE_51
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_EnableFallingTrig_32_63(uint32_t ExtiLine)
-{
-  SET_BIT(EXTI->FTSR2, ExtiLine);
-}
-
-/**
-  * @brief  Enable ExtiLine Falling Edge Trigger for Lines in range 64 to 95
-  * @note The configurable wakeup lines are edge-triggered. No glitch must be
-  *       generated on these lines. If a Falling edge on a configurable interrupt
-  *       line occurs during a write operation in the EXTI_FTSR register, the
-  *       pending bit is not set.
-  *       Rising and falling edge triggers can be set for
-  *       the same interrupt line. In this case, both generate a trigger
-  *       condition.
-  * @rmtoll FTSR3        FTx           LL_EXTI_EnableFallingTrig_64_95
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_82 (*)
-  *         @arg @ref LL_EXTI_LINE_84 (*)
-  *         @arg @ref LL_EXTI_LINE_85
-  *         @arg @ref LL_EXTI_LINE_86 (**)
-  *
-  *         (*) value only defined in dual core devices.
-  *         (**) value not defined in all devices.
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_EnableFallingTrig_64_95(uint32_t ExtiLine)
-{
-  SET_BIT(EXTI->FTSR3, ExtiLine);
-}
-
-
-/**
-  * @brief  Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
-  * @note The configurable wakeup lines are edge-triggered. No glitch must be
-  *       generated on these lines. If a Falling edge on a configurable interrupt
-  *       line occurs during a write operation in the EXTI_FTSR register, the
-  *       pending bit is not set.
-  *       Rising and falling edge triggers can be set for the same interrupt line.
-  *       In this case, both generate a trigger condition.
-  * @rmtoll FTSR1        FTx           LL_EXTI_DisableFallingTrig_0_31
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19
-  *         @arg @ref LL_EXTI_LINE_20
-  *         @arg @ref LL_EXTI_LINE_21
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine)
-{
-  CLEAR_BIT(EXTI->FTSR1, ExtiLine);
-}
-
-/**
-  * @brief  Disable ExtiLine Falling Edge Trigger for Lines in range 32 to 63
-  * @note The configurable wakeup lines are edge-triggered. No glitch must be
-  *       generated on these lines. If a Falling edge on a configurable interrupt
-  *       line occurs during a write operation in the EXTI_FTSR register, the
-  *       pending bit is not set.
-  *       Rising and falling edge triggers can be set for the same interrupt line.
-  *       In this case, both generate a trigger condition.
-  * @rmtoll FTSR2        FTx           LL_EXTI_DisableFallingTrig_32_63
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_49
-  *         @arg @ref LL_EXTI_LINE_51
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_DisableFallingTrig_32_63(uint32_t ExtiLine)
-{
-  CLEAR_BIT(EXTI->FTSR2, ExtiLine);
-}
-
-/**
-  * @brief  Disable ExtiLine Falling Edge Trigger for Lines in range 64 to 95
-  * @note The configurable wakeup lines are edge-triggered. No glitch must be
-  *       generated on these lines. If a Falling edge on a configurable interrupt
-  *       line occurs during a write operation in the EXTI_FTSR register, the
-  *       pending bit is not set.
-  *       Rising and falling edge triggers can be set for the same interrupt line.
-  *       In this case, both generate a trigger condition.
-  * @rmtoll FTSR3        FTx           LL_EXTI_DisableFallingTrig_64_95
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_82 (*)
-  *         @arg @ref LL_EXTI_LINE_84 (*)
-  *         @arg @ref LL_EXTI_LINE_85
-  *         @arg @ref LL_EXTI_LINE_86 (**)
-  *
-  *         (*) value only defined in dual core devices.
-  *         (**) value not defined in all devices.
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_DisableFallingTrig_64_95(uint32_t ExtiLine)
-{
-  CLEAR_BIT(EXTI->FTSR3, ExtiLine);
-}
-
-
-/**
-  * @brief  Check if falling edge trigger is enabled for Lines in range 0 to 31
-  * @rmtoll FTSR1        FTx           LL_EXTI_IsEnabledFallingTrig_0_31
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19
-  *         @arg @ref LL_EXTI_LINE_20
-  *         @arg @ref LL_EXTI_LINE_21
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine)
-{
-  return ((READ_BIT(EXTI->FTSR1, ExtiLine) == (ExtiLine)) ? 1U : 0U);
-}
-
-/**
-  * @brief  Check if falling edge trigger is enabled for Lines in range 32 to 63
-  * @rmtoll FTSR2        FTx           LL_EXTI_IsEnabledFallingTrig_32_63
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_49
-  *         @arg @ref LL_EXTI_LINE_51
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_32_63(uint32_t ExtiLine)
-{
-  return ((READ_BIT(EXTI->FTSR2, ExtiLine) == (ExtiLine)) ? 1U : 0U);
-}
-
-/**
-  * @brief  Check if falling edge trigger is enabled for Lines in range 64 to 95
-  * @rmtoll FTSR3        FTx           LL_EXTI_IsEnabledFallingTrig_64_95
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_82 (*)
-  *         @arg @ref LL_EXTI_LINE_84 (*)
-  *         @arg @ref LL_EXTI_LINE_85
-  *         @arg @ref LL_EXTI_LINE_86 (**)
-  *
-  *         (*) value only defined in dual core devices.
-  *         (**) value not defined in all devices.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_64_95(uint32_t ExtiLine)
-{
-  return ((READ_BIT(EXTI->FTSR3, ExtiLine) == (ExtiLine)) ? 1U : 0U);
-}
-
-
-/**
-  * @}
-  */
-
-/** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management
-  * @{
-  */
-
-/**
-  * @brief  Generate a software Interrupt Event for Lines in range 0 to 31
-  * @note If the interrupt is enabled on this line in the EXTI_C1IMR1, writing a 1 to
-  *       this bit when it is at '0' sets the corresponding pending bit in EXTI_PR1
-  *       resulting in an interrupt request generation.
-  *       This bit is cleared by clearing the corresponding bit in the EXTI_PR1
-  *       register (by writing a 1 into the bit)
-  * @rmtoll SWIER1       SWIx          LL_EXTI_GenerateSWI_0_31
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19
-  *         @arg @ref LL_EXTI_LINE_20
-  *         @arg @ref LL_EXTI_LINE_21
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine)
-{
-  SET_BIT(EXTI->SWIER1, ExtiLine);
-}
-
-/**
-  * @brief  Generate a software Interrupt Event for Lines in range 32 to 63
-  * @note If the interrupt is enabled on this line in the EXTI_IMR2, writing a 1 to
-  *       this bit when it is at '0' sets the corresponding pending bit in EXTI_PR2
-  *       resulting in an interrupt request generation.
-  *       This bit is cleared by clearing the corresponding bit in the EXTI_PR2
-  *       register (by writing a 1 into the bit)
-  * @rmtoll SWIER2       SWIx          LL_EXTI_GenerateSWI_32_63
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_49
-  *         @arg @ref LL_EXTI_LINE_51
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_GenerateSWI_32_63(uint32_t ExtiLine)
-{
-  SET_BIT(EXTI->SWIER2, ExtiLine);
-}
-
-/**
-  * @brief  Generate a software Interrupt Event for Lines in range 64 to 95
-  * @note If the interrupt is enabled on this line in the EXTI_IMR2, writing a 1 to
-  *       this bit when it is at '0' sets the corresponding pending bit in EXTI_PR2
-  *       resulting in an interrupt request generation.
-  *       This bit is cleared by clearing the corresponding bit in the EXTI_PR3
-  *       register (by writing a 1 into the bit)
-  * @rmtoll SWIER3       SWIx          LL_EXTI_GenerateSWI_64_95
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_82 (*)
-  *         @arg @ref LL_EXTI_LINE_84 (*)
-  *         @arg @ref LL_EXTI_LINE_85
-  *         @arg @ref LL_EXTI_LINE_86 (**)
-  *
-  *         (*) value only defined in dual core devices.
-  *         (**) value not defined in all devices.
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_GenerateSWI_64_95(uint32_t ExtiLine)
-{
-  SET_BIT(EXTI->SWIER3, ExtiLine);
-}
-
-
-/**
-  * @}
-  */
-
-/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management
-  * @{
-  */
-
-/**
-  * @brief  Check if the ExtLine Flag is set or not for Lines in range 0 to 31
-  * @note This bit is set when the selected edge event arrives on the interrupt
-  *       line. This bit is cleared by writing a 1 to the bit.
-  * @rmtoll PR1          PIFx           LL_EXTI_IsActiveFlag_0_31
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_17
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19
-  *         @arg @ref LL_EXTI_LINE_20
-  *         @arg @ref LL_EXTI_LINE_21
-  *         @arg @ref LL_EXTI_LINE_ALL_0_31
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine)
-{
-  return ((READ_BIT(EXTI->PR1, ExtiLine) == (ExtiLine)) ? 1U : 0U);
-}
-
-/**
-  * @brief  Check if the ExtLine Flag is set or not for  Lines in range 32 to 63
-  * @note This bit is set when the selected edge event arrives on the interrupt
-  *       line. This bit is cleared by writing a 1 to the bit.
-  * @rmtoll PR2          PIFx           LL_EXTI_IsActiveFlag_32_63
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_49
-  *         @arg @ref LL_EXTI_LINE_51
-  *         @arg @ref LL_EXTI_LINE_ALL_32_63
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_32_63(uint32_t ExtiLine)
-{
-  return ((READ_BIT(EXTI->PR2, ExtiLine) == (ExtiLine)) ? 1U : 0U);
-}
-
-/**
-  * @brief  Check if the ExtLine Flag is set or not for  Lines in range 64 to 95
-  * @note This bit is set when the selected edge event arrives on the interrupt
-  *       line. This bit is cleared by writing a 1 to the bit.
-  * @rmtoll PR3          PIFx           LL_EXTI_IsActiveFlag_64_95
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_82 (*)
-  *         @arg @ref LL_EXTI_LINE_84 (*)
-  *         @arg @ref LL_EXTI_LINE_85
-  *         @arg @ref LL_EXTI_LINE_86 (**)
-  *
-  *         (*) value only defined in dual core devices.
-  *         (**) value not defined in all devices.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_64_95(uint32_t ExtiLine)
-{
-  return ((READ_BIT(EXTI->PR3, ExtiLine) == (ExtiLine)) ? 1U : 0U);
-}
-
-
-/**
-  * @brief  Read ExtLine Combination Flag for Lines in range 0 to 31
-  * @note This bit is set when the selected edge event arrives on the interrupt
-  *       line. This bit is cleared by writing a 1 to the bit.
-  * @rmtoll PR1          PIFx           LL_EXTI_ReadFlag_0_31
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_17
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19
-  *         @arg @ref LL_EXTI_LINE_20
-  *         @arg @ref LL_EXTI_LINE_21
-  * @retval @note This bit is set when the selected edge event arrives on the interrupt
-  */
-__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine)
-{
-  return (uint32_t)(READ_BIT(EXTI->PR1, ExtiLine));
-}
-
-
-/**
-  * @brief  Read ExtLine Combination Flag for  Lines in range 32 to 63
-  * @note This bit is set when the selected edge event arrives on the interrupt
-  *       line. This bit is cleared by writing a 1 to the bit.
-  * @rmtoll PR2          PIFx           LL_EXTI_ReadFlag_32_63
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_49
-  *         @arg @ref LL_EXTI_LINE_51
-  * @retval @note This bit is set when the selected edge event arrives on the interrupt
-  */
-__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_32_63(uint32_t ExtiLine)
-{
-  return (uint32_t)(READ_BIT(EXTI->PR2, ExtiLine));
-}
-
-
-/**
-  * @brief  Read ExtLine Combination Flag for  Lines in range 64 to 95
-  * @note This bit is set when the selected edge event arrives on the interrupt
-  *       line. This bit is cleared by writing a 1 to the bit.
-  * @rmtoll PR3          PIFx           LL_EXTI_ReadFlag_64_95
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_82 (*)
-  *         @arg @ref LL_EXTI_LINE_84 (*)
-  *         @arg @ref LL_EXTI_LINE_85
-  *         @arg @ref LL_EXTI_LINE_86 (**)
-  *
-  *         (*) value only defined in dual core devices.
-  *         (**) value not defined in all devices.
-  * @retval @note This bit is set when the selected edge event arrives on the interrupt
-  */
-__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_64_95(uint32_t ExtiLine)
-{
-  return (uint32_t)(READ_BIT(EXTI->PR3, ExtiLine));
-}
-
-/**
-  * @brief  Clear ExtLine Flags for Lines in range 0 to 31
-  * @note This bit is set when the selected edge event arrives on the interrupt
-  *       line. This bit is cleared by writing a 1 to the bit.
-  * @rmtoll PR1          PIFx           LL_EXTI_ClearFlag_0_31
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_17
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19
-  *         @arg @ref LL_EXTI_LINE_20
-  *         @arg @ref LL_EXTI_LINE_21
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine)
-{
-  WRITE_REG(EXTI->PR1, ExtiLine);
-}
-
-/**
-  * @brief  Clear ExtLine Flags for Lines in range 32 to 63
-  * @note This bit is set when the selected edge event arrives on the interrupt
-  *       line. This bit is cleared by writing a 1 to the bit.
-  * @rmtoll PR2          PIFx           LL_EXTI_ClearFlag_32_63
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_49
-  *         @arg @ref LL_EXTI_LINE_51
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_ClearFlag_32_63(uint32_t ExtiLine)
-{
-  WRITE_REG(EXTI->PR2, ExtiLine);
-}
-
-/**
-  * @brief  Clear ExtLine Flags for Lines in range 64 to 95
-  * @note This bit is set when the selected edge event arrives on the interrupt
-  *       line. This bit is cleared by writing a 1 to the bit.
-  * @rmtoll PR3          PIFx           LL_EXTI_ClearFlag_64_95
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_82 (*)
-  *         @arg @ref LL_EXTI_LINE_84 (*)
-  *         @arg @ref LL_EXTI_LINE_85
-  *         @arg @ref LL_EXTI_LINE_86 (**)
-  *
-  *         (*) value only defined in dual core devices.
-  *         (**) value not defined in all devices.
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_ClearFlag_64_95(uint32_t ExtiLine)
-{
-  WRITE_REG(EXTI->PR3, ExtiLine);
-}
-
-#if defined(DUAL_CORE)
-
-/**
-  * @brief  Check if the ExtLine Flag is set or not for Lines in range 0 to 31 for cpu2
-  * @note This bit is set when the selected edge event arrives on the interrupt
-  *       line. This bit is cleared by writing a 1 to the bit.
-  * @rmtoll C2PR1          PIFx           LL_C2_EXTI_IsActiveFlag_0_31
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_17
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19
-  *         @arg @ref LL_EXTI_LINE_20
-  *         @arg @ref LL_EXTI_LINE_21
-  *         @arg @ref LL_EXTI_LINE_ALL_0_31
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_C2_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine)
-{
-  return ((READ_BIT(EXTI->C2PR1, ExtiLine) == (ExtiLine)) ? 1U : 0U);
-}
-
-/**
-  * @brief  Check if the ExtLine Flag is set or not for  Lines in range 32 to 63 for cpu2
-  * @note This bit is set when the selected edge event arrives on the interrupt
-  *       line. This bit is cleared by writing a 1 to the bit.
-  * @rmtoll C2PR2          PIFx           LL_C2_EXTI_IsActiveFlag_32_63
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_49
-  *         @arg @ref LL_EXTI_LINE_51
-  *         @arg @ref LL_EXTI_LINE_ALL_32_63
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_C2_EXTI_IsActiveFlag_32_63(uint32_t ExtiLine)
-{
-  return ((READ_BIT(EXTI->C2PR2, ExtiLine) == (ExtiLine)) ? 1U : 0U);
-}
-
-/**
-  * @brief  Check if the ExtLine Flag is set or not for  Lines in range 64 to 95 for cpu2
-  * @note This bit is set when the selected edge event arrives on the interrupt
-  *       line. This bit is cleared by writing a 1 to the bit.
-  * @rmtoll C2PR3          PIFx           LL_C2_EXTI_IsActiveFlag_64_95
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_82
-  *         @arg @ref LL_EXTI_LINE_84
-  *         @arg @ref LL_EXTI_LINE_85
-  *         @arg @ref LL_EXTI_LINE_86
-  *         @arg @ref LL_EXTI_LINE_ALL_64_95
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_C2_EXTI_IsActiveFlag_64_95(uint32_t ExtiLine)
-{
-  return ((READ_BIT(EXTI->C2PR3, ExtiLine) == (ExtiLine)) ? 1U : 0U);
-}
-
-/**
-  * @brief  Read ExtLine Combination Flag for Lines in range 0 to 31 for cpu2
-  * @note This bit is set when the selected edge event arrives on the interrupt
-  *       line. This bit is cleared by writing a 1 to the bit.
-  * @rmtoll C2PR1          PIFx           LL_C2_EXTI_ReadFlag_0_31
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_17
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19
-  *         @arg @ref LL_EXTI_LINE_20
-  *         @arg @ref LL_EXTI_LINE_21
-  * @retval @note This bit is set when the selected edge event arrives on the interrupt
-  */
-__STATIC_INLINE uint32_t LL_C2_EXTI_ReadFlag_0_31(uint32_t ExtiLine)
-{
-  return (uint32_t)(READ_BIT(EXTI->C2PR1, ExtiLine));
-}
-
-/**
-  * @brief  Read ExtLine Combination Flag for  Lines in range 32 to 63 for cpu2
-  * @note This bit is set when the selected edge event arrives on the interrupt
-  *       line. This bit is cleared by writing a 1 to the bit.
-  * @rmtoll C2PR2          PIFx           LL_C2_EXTI_ReadFlag_32_63
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_49
-  *         @arg @ref LL_EXTI_LINE_51
-  * @retval @note This bit is set when the selected edge event arrives on the interrupt
-  */
-__STATIC_INLINE uint32_t LL_C2_EXTI_ReadFlag_32_63(uint32_t ExtiLine)
-{
-  return (uint32_t)(READ_BIT(EXTI->C2PR2, ExtiLine));
-}
-
-
-/**
-  * @brief  Read ExtLine Combination Flag for  Lines in range 64 to 95 for cpu2
-  * @note This bit is set when the selected edge event arrives on the interrupt
-  *       line. This bit is cleared by writing a 1 to the bit.
-  * @rmtoll C2PR3          PIFx           LL_C2_EXTI_ReadFlag_64_95
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_82
-  *         @arg @ref LL_EXTI_LINE_84
-  *         @arg @ref LL_EXTI_LINE_85
-  *         @arg @ref LL_EXTI_LINE_86
-  * @retval @note This bit is set when the selected edge event arrives on the interrupt
-  */
-__STATIC_INLINE uint32_t LL_C2_EXTI_ReadFlag_64_95(uint32_t ExtiLine)
-{
-  return (uint32_t)(READ_BIT(EXTI->C2PR3, ExtiLine));
-}
-/**
-  * @brief  Clear ExtLine Flags for Lines in range 0 to 31 for cpu2
-  * @note This bit is set when the selected edge event arrives on the interrupt
-  *       line. This bit is cleared by writing a 1 to the bit.
-  * @rmtoll C2PR1          PIFx           LL_C2_EXTI_ClearFlag_0_31
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_17
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19
-  *         @arg @ref LL_EXTI_LINE_20
-  *         @arg @ref LL_EXTI_LINE_21
-  * @retval None
-  */
-__STATIC_INLINE void LL_C2_EXTI_ClearFlag_0_31(uint32_t ExtiLine)
-{
-  WRITE_REG(EXTI->C2PR1, ExtiLine);
-}
-
-/**
-  * @brief  Clear ExtLine Flags for Lines in range 32 to 63 for cpu2
-  * @note This bit is set when the selected edge event arrives on the interrupt
-  *       line. This bit is cleared by writing a 1 to the bit.
-  * @rmtoll C2PR2          PIFx           LL_C2_EXTI_ClearFlag_32_63
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_49
-  *         @arg @ref LL_EXTI_LINE_51
-  * @retval None
-  */
-__STATIC_INLINE void LL_C2_EXTI_ClearFlag_32_63(uint32_t ExtiLine)
-{
-  WRITE_REG(EXTI->C2PR2, ExtiLine);
-}
-
-/**
-  * @brief  Clear ExtLine Flags for Lines in range 64 to 95 for cpu2
-  * @note This bit is set when the selected edge event arrives on the interrupt
-  *       line. This bit is cleared by writing a 1 to the bit.
-  * @rmtoll C2PR3          PIFx           LL_C2_EXTI_ClearFlag_64_95
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_82
-  *         @arg @ref LL_EXTI_LINE_84
-  *         @arg @ref LL_EXTI_LINE_85
-  *         @arg @ref LL_EXTI_LINE_86
-  * @retval None
-  */
-__STATIC_INLINE void LL_C2_EXTI_ClearFlag_64_95(uint32_t ExtiLine)
-{
-  WRITE_REG(EXTI->C2PR3, ExtiLine);
-}
-
-#endif /* DUAL_CORE */
-
-/**
-  * @brief  Enable ExtiLine D3 Pending Mask for Lines in range 0 to 31
-  * @rmtoll D3PMR1         MRx           LL_D3_EXTI_EnablePendMask_0_31
-  * @param  ExtiLine This parameter can be one of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_19
-  *         @arg @ref LL_EXTI_LINE_20
-  *         @arg @ref LL_EXTI_LINE_21
-  *         @arg @ref LL_EXTI_LINE_25
-  * @retval None
-  */
-__STATIC_INLINE void LL_D3_EXTI_EnablePendMask_0_31(uint32_t ExtiLine)
-{
-  SET_BIT(EXTI->D3PMR1, ExtiLine);
-}
-
-/**
-  * @brief  Enable ExtiLine D3 Pending Mask for Lines in range 32 to 63
-  * @rmtoll D3PMR2         MRx           LL_D3_EXTI_EnablePendMask_32_63
-  * @param  ExtiLine This parameter can be one of the following values:
-  *         @arg @ref LL_EXTI_LINE_34
-  *         @arg @ref LL_EXTI_LINE_35
-  *         @arg @ref LL_EXTI_LINE_41
-  *         @arg @ref LL_EXTI_LINE_48
-  *         @arg @ref LL_EXTI_LINE_49
-  *         @arg @ref LL_EXTI_LINE_50
-  *         @arg @ref LL_EXTI_LINE_51
-  *         @arg @ref LL_EXTI_LINE_52
-  *         @arg @ref LL_EXTI_LINE_53
-  * @retval None
-  */
-__STATIC_INLINE void LL_D3_EXTI_EnablePendMask_32_63(uint32_t ExtiLine)
-{
-  SET_BIT(EXTI->D3PMR2, ExtiLine);
-}
-
-/**
-  * @brief  Disable ExtiLine D3 Pending Mask for Lines in range 0 to 31
-  * @rmtoll D3PMR1         MRx           LL_D3_EXTI_DisablePendMask_0_31
-  * @param  ExtiLine This parameter can be one of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_19
-  *         @arg @ref LL_EXTI_LINE_20
-  *         @arg @ref LL_EXTI_LINE_21
-  *         @arg @ref LL_EXTI_LINE_25
-  * @retval None
-  */
-__STATIC_INLINE void LL_D3_EXTI_DisablePendMask_0_31(uint32_t ExtiLine)
-{
-  CLEAR_BIT(EXTI->D3PMR1, ExtiLine);
-}
-
-/**
-  * @brief  Disable ExtiLine D3 Pending Mask for Lines in range 32 to 63
-  * @rmtoll D3PMR2         MRx           LL_D3_EXTI_DisablePendMask_32_63
-  * @param  ExtiLine This parameter can be one of the following values:
-  *         @arg @ref LL_EXTI_LINE_34
-  *         @arg @ref LL_EXTI_LINE_35
-  *         @arg @ref LL_EXTI_LINE_41
-  *         @arg @ref LL_EXTI_LINE_48
-  *         @arg @ref LL_EXTI_LINE_49
-  *         @arg @ref LL_EXTI_LINE_50
-  *         @arg @ref LL_EXTI_LINE_51
-  *         @arg @ref LL_EXTI_LINE_52
-  *         @arg @ref LL_EXTI_LINE_53
-  * @retval None
-  */
-__STATIC_INLINE void LL_D3_EXTI_DisablePendMask_32_63(uint32_t ExtiLine)
-{
-  CLEAR_BIT(EXTI->D3PMR2, ExtiLine);
-}
-
-/**
-  * @brief  Indicate if ExtiLine D3 Pending Mask is enabled for Lines in range 0 to 31
-  * @rmtoll D3PMR1         MRx           LL_D3_EXTI_IsEnabledPendMask_0_31
-  * @param  ExtiLine This parameter can be one of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_19
-  *         @arg @ref LL_EXTI_LINE_20
-  *         @arg @ref LL_EXTI_LINE_21
-  *         @arg @ref LL_EXTI_LINE_25
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_D3_EXTI_IsEnabledPendMask_0_31(uint32_t ExtiLine)
-{
-  return ((READ_BIT(EXTI->D3PMR1, ExtiLine) == (ExtiLine)) ? 1U : 0U);
-}
-
-/**
-  * @brief  Indicate if ExtiLine D3 Pending Mask is enabled for Lines in range 32 to 63
-  * @rmtoll D3PMR2         MRx           LL_D3_EXTI_IsEnabledPendMask_32_63
-  * @param  ExtiLine This parameter can be one of the following values:
-  *         @arg @ref LL_EXTI_LINE_34
-  *         @arg @ref LL_EXTI_LINE_35
-  *         @arg @ref LL_EXTI_LINE_41
-  *         @arg @ref LL_EXTI_LINE_48
-  *         @arg @ref LL_EXTI_LINE_49
-  *         @arg @ref LL_EXTI_LINE_50
-  *         @arg @ref LL_EXTI_LINE_51
-  *         @arg @ref LL_EXTI_LINE_52
-  *         @arg @ref LL_EXTI_LINE_53
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_D3_EXTI_IsEnabledPendMask_32_63(uint32_t ExtiLine)
-{
-  return ((READ_BIT(EXTI->D3PMR2, ExtiLine) == (ExtiLine)) ? 1U : 0U);
-}
-
-/**
-  * @brief  Set ExtLine D3 Domain Pend Clear Source selection for Lines in range 0 to 15
-  * @rmtoll D3PCR1L          PCSx           LL_D3_EXTI_SetPendClearSel_0_15
-  * @param  ExtiLine This parameter can be one of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  * @param  ClrSrc This parameter can be one of the following values:
-  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6
-  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7
-  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4 (*)
-  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5 (*)
-  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM2 (*)
-  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM3 (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-  */
-__STATIC_INLINE void LL_D3_EXTI_SetPendClearSel_0_15(uint32_t ExtiLine, uint32_t ClrSrc)
-{
-  MODIFY_REG(EXTI->D3PCR1L, ((ExtiLine * ExtiLine) * 3UL), ((ExtiLine * ExtiLine) * ClrSrc));
-}
-
-/**
-  * @brief  Set ExtLine D3 Domain Pend Clear Source selection for Lines in range 16 to 31
-  * @rmtoll D3PCR1H          PCSx           LL_D3_EXTI_SetPendClearSel_16_31
-  * @param  ExtiLine This parameter can be one of the following values:
-  *         @arg @ref LL_EXTI_LINE_19
-  *         @arg @ref LL_EXTI_LINE_20
-  *         @arg @ref LL_EXTI_LINE_21
-  *         @arg @ref LL_EXTI_LINE_25
-  * @param  ClrSrc This parameter can be one of the following values:
-  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6
-  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7
-  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4 (*)
-  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5 (*)
-  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM2 (*)
-  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM3 (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-  */
-__STATIC_INLINE void LL_D3_EXTI_SetPendClearSel_16_31(uint32_t ExtiLine, uint32_t ClrSrc)
-{
-  MODIFY_REG(EXTI->D3PCR1H, (((ExtiLine >> EXTI_IMR1_IM16_Pos) * (ExtiLine >> EXTI_IMR1_IM16_Pos)) * 3UL), (((ExtiLine >> EXTI_IMR1_IM16_Pos) * (ExtiLine >> EXTI_IMR1_IM16_Pos)) * ClrSrc));
-}
-
-
-/**
-  * @brief  Set ExtLine D3 Domain Pend Clear Source selection for Lines in range 32 to 47
-  * @rmtoll D3PCR2L          PCSx           LL_D3_EXTI_SetPendClearSel_32_47
-  * @param  ExtiLine This parameter can be one of the following values:
-  *         @arg @ref LL_EXTI_LINE_34
-  *         @arg @ref LL_EXTI_LINE_35
-  *         @arg @ref LL_EXTI_LINE_41
-  * @param  ClrSrc This parameter can be one of the following values:
-  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6
-  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7
-  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4 (*)
-  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5 (*)
-  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM2 (*)
-  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM3 (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-  */
-__STATIC_INLINE void LL_D3_EXTI_SetPendClearSel_32_47(uint32_t ExtiLine, uint32_t ClrSrc)
-{
-  MODIFY_REG(EXTI->D3PCR2L, ((ExtiLine * ExtiLine) * 3UL), ((ExtiLine * ExtiLine) * ClrSrc));
-}
-
-/**
-  * @brief  Set ExtLine D3 Domain Pend Clear Source selection for Lines in range 48 to 63
-  * @rmtoll D3PCR2H          PCSx           LL_D3_EXTI_SetPendClearSel_48_63
-  * @param  ExtiLine This parameter can be one of the following values:
-  *         @arg @ref LL_EXTI_LINE_48
-  *         @arg @ref LL_EXTI_LINE_49
-  *         @arg @ref LL_EXTI_LINE_50
-  *         @arg @ref LL_EXTI_LINE_51
-  *         @arg @ref LL_EXTI_LINE_52
-  *         @arg @ref LL_EXTI_LINE_53
-  * @param  ClrSrc This parameter can be one of the following values:
-  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6
-  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7
-  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4 (*)
-  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5 (*)
-  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM2 (*)
-  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM3 (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-  */
-__STATIC_INLINE void LL_D3_EXTI_SetPendClearSel_48_63(uint32_t ExtiLine, uint32_t ClrSrc)
-{
-  MODIFY_REG(EXTI->D3PCR2H, (((ExtiLine >> EXTI_IMR2_IM48_Pos) * (ExtiLine >> EXTI_IMR2_IM48_Pos)) * 3UL), (((ExtiLine >> EXTI_IMR2_IM48_Pos) * (ExtiLine >> EXTI_IMR2_IM48_Pos)) * ClrSrc));
-}
-
-/**
-  * @brief  Get ExtLine D3 Domain Pend Clear Source selection for Lines in range 0 to 15
-  * @rmtoll D3PCR1L          PCSx           LL_D3_EXTI_GetPendClearSel_0_15
-  * @param  ExtiLine This parameter can be one of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6
-  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7
-  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4 (*)
-  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5 (*)
-  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM2 (*)
-  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM3 (*)
-  *
-  *         (*) value not defined in all devices.
-  */
-__STATIC_INLINE uint32_t LL_D3_EXTI_GetPendClearSel_0_15(uint32_t ExtiLine)
-{
-  return (uint32_t)(READ_BIT(EXTI->D3PCR1L, ((ExtiLine * ExtiLine) * 3UL)) / (ExtiLine * ExtiLine));
-}
-
-/**
-  * @brief  Get ExtLine D3 Domain Pend Clear Source selection for Lines in range 16 to 31
-  * @rmtoll D3PCR1H          PCSx           LL_D3_EXTI_GetPendClearSel_16_31
-  * @param  ExtiLine This parameter can be one of the following values:
-  *         @arg @ref LL_EXTI_LINE_19
-  *         @arg @ref LL_EXTI_LINE_20
-  *         @arg @ref LL_EXTI_LINE_21
-  *         @arg @ref LL_EXTI_LINE_25
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6
-  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7
-  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4 (*)
-  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5 (*)
-  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM2 (*)
-  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM3 (*)
-  *
-  *         (*) value not defined in all devices.
-  */
-__STATIC_INLINE uint32_t LL_D3_EXTI_GetPendClearSel_16_31(uint32_t ExtiLine)
-{
-  return (uint32_t)(READ_BIT(EXTI->D3PCR1H, (((ExtiLine >> EXTI_IMR1_IM16_Pos) * (ExtiLine >> EXTI_IMR1_IM16_Pos)) * 3UL)) / ((ExtiLine >> EXTI_IMR1_IM16_Pos) * (ExtiLine >> EXTI_IMR1_IM16_Pos)));
-}
-
-/**
-  * @brief  Get ExtLine D3 Domain Pend Clear Source selection for Lines in range 32 to 47
-  * @rmtoll D3PCR2L          PCSx           LL_D3_EXTI_GetPendClearSel_32_47
-  * @param  ExtiLine This parameter can be one of the following values:
-  *         @arg @ref LL_EXTI_LINE_34
-  *         @arg @ref LL_EXTI_LINE_35
-  *         @arg @ref LL_EXTI_LINE_41
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6
-  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7
-  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4 (*)
-  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5 (*)
-  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM2 (*)
-  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM3 (*)
-  *
-  *         (*) value not defined in all devices.
-  */
-__STATIC_INLINE uint32_t LL_D3_EXTI_GetPendClearSel_32_47(uint32_t ExtiLine)
-{
-  return (uint32_t)(READ_BIT(EXTI->D3PCR2L, ((ExtiLine * ExtiLine) * 3UL)) / (ExtiLine * ExtiLine));
-}
-
-/**
-  * @brief  Get ExtLine D3 Domain Pend Clear Source selection for Lines in range 48 to 63
-  * @rmtoll D3PCR2H          PCSx           LL_D3_EXTI_GetPendClearSel_48_63
-  * @param  ExtiLine This parameter can be one of the following values:
-  *         @arg @ref LL_EXTI_LINE_48
-  *         @arg @ref LL_EXTI_LINE_49
-  *         @arg @ref LL_EXTI_LINE_50
-  *         @arg @ref LL_EXTI_LINE_51
-  *         @arg @ref LL_EXTI_LINE_52
-  *         @arg @ref LL_EXTI_LINE_53
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6
-  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7
-  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4 (*)
-  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5 (*)
-  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM2 (*)
-  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM3 (*)
-  *
-  *         (*) value not defined in all devices.
-  */
-__STATIC_INLINE uint32_t LL_D3_EXTI_GetPendClearSel_48_63(uint32_t ExtiLine)
-{
-  return (uint32_t)(READ_BIT(EXTI->D3PCR2H, (((ExtiLine >> EXTI_IMR2_IM48_Pos) * (ExtiLine >> EXTI_IMR2_IM48_Pos)) * 3UL)) / ((ExtiLine >> EXTI_IMR2_IM48_Pos) * (ExtiLine >> EXTI_IMR2_IM48_Pos)));
-}
-
-
-
-/**
-  * @}
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions
-  * @{,
-  */
-
-ErrorStatus LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct);
-ErrorStatus LL_EXTI_DeInit(void);
-void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct);
-
-
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* EXTI */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32H7xx_LL_EXTI_H */
-
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_ll_exti.h
+  * @author  MCD Application Team
+  * @brief   Header file of EXTI LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32H7xx_LL_EXTI_H
+#define __STM32H7xx_LL_EXTI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx.h"
+
+/** @addtogroup STM32H7xx_LL_Driver
+  * @{
+  */
+
+#if defined (EXTI)
+
+/** @defgroup EXTI_LL EXTI
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private Macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros
+  * @{
+  */
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure
+  * @{
+  */
+typedef struct
+{
+
+  uint32_t Line_0_31;           /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31
+                                     This parameter can be any combination of @ref EXTI_LL_EC_LINE */
+
+  uint32_t Line_32_63;          /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 32 to 63
+                                     This parameter can be any combination of @ref EXTI_LL_EC_LINE */
+
+  uint32_t Line_64_95;          /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 64 to 95
+                                     This parameter can be any combination of @ref EXTI_LL_EC_LINE */
+
+  FunctionalState LineCommand;  /*!< Specifies the new state of the selected EXTI lines.
+                                     This parameter can be set either to ENABLE or DISABLE */
+
+  uint8_t Mode;                 /*!< Specifies the mode for the EXTI lines.
+                                     This parameter can be a value of @ref EXTI_LL_EC_MODE. */
+
+  uint8_t Trigger;              /*!< Specifies the trigger signal active edge for the EXTI lines.
+                                     This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */
+} LL_EXTI_InitTypeDef;
+
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants
+  * @{
+  */
+
+/** @defgroup EXTI_LL_EC_LINE LINE
+  * @{
+  */
+#define LL_EXTI_LINE_0                 EXTI_IMR1_IM0           /*!< Extended line 0 */
+#define LL_EXTI_LINE_1                 EXTI_IMR1_IM1           /*!< Extended line 1 */
+#define LL_EXTI_LINE_2                 EXTI_IMR1_IM2           /*!< Extended line 2 */
+#define LL_EXTI_LINE_3                 EXTI_IMR1_IM3           /*!< Extended line 3 */
+#define LL_EXTI_LINE_4                 EXTI_IMR1_IM4           /*!< Extended line 4 */
+#define LL_EXTI_LINE_5                 EXTI_IMR1_IM5           /*!< Extended line 5 */
+#define LL_EXTI_LINE_6                 EXTI_IMR1_IM6           /*!< Extended line 6 */
+#define LL_EXTI_LINE_7                 EXTI_IMR1_IM7           /*!< Extended line 7 */
+#define LL_EXTI_LINE_8                 EXTI_IMR1_IM8           /*!< Extended line 8 */
+#define LL_EXTI_LINE_9                 EXTI_IMR1_IM9           /*!< Extended line 9 */
+#define LL_EXTI_LINE_10                EXTI_IMR1_IM10          /*!< Extended line 10 */
+#define LL_EXTI_LINE_11                EXTI_IMR1_IM11          /*!< Extended line 11 */
+#define LL_EXTI_LINE_12                EXTI_IMR1_IM12          /*!< Extended line 12 */
+#define LL_EXTI_LINE_13                EXTI_IMR1_IM13          /*!< Extended line 13 */
+#define LL_EXTI_LINE_14                EXTI_IMR1_IM14          /*!< Extended line 14 */
+#define LL_EXTI_LINE_15                EXTI_IMR1_IM15          /*!< Extended line 15 */
+#define LL_EXTI_LINE_16                EXTI_IMR1_IM16          /*!< Extended line 16 */
+#define LL_EXTI_LINE_17                EXTI_IMR1_IM17          /*!< Extended line 17 */
+#define LL_EXTI_LINE_18                EXTI_IMR1_IM18          /*!< Extended line 18 */
+#define LL_EXTI_LINE_19                EXTI_IMR1_IM19          /*!< Extended line 19 */
+#define LL_EXTI_LINE_20                EXTI_IMR1_IM20          /*!< Extended line 20 */
+#define LL_EXTI_LINE_21                EXTI_IMR1_IM21          /*!< Extended line 21 */
+#define LL_EXTI_LINE_22                EXTI_IMR1_IM22          /*!< Extended line 22 */
+#define LL_EXTI_LINE_23                EXTI_IMR1_IM23          /*!< Extended line 23 */
+#define LL_EXTI_LINE_24                EXTI_IMR1_IM24          /*!< Extended line 24 */
+#define LL_EXTI_LINE_25                EXTI_IMR1_IM25          /*!< Extended line 25 */
+#define LL_EXTI_LINE_26                EXTI_IMR1_IM26          /*!< Extended line 26 */
+#define LL_EXTI_LINE_27                EXTI_IMR1_IM27          /*!< Extended line 27 */
+#define LL_EXTI_LINE_28                EXTI_IMR1_IM28          /*!< Extended line 28 */
+#define LL_EXTI_LINE_29                EXTI_IMR1_IM29          /*!< Extended line 29 */
+#define LL_EXTI_LINE_30                EXTI_IMR1_IM30          /*!< Extended line 30 */
+#define LL_EXTI_LINE_31                EXTI_IMR1_IM31          /*!< Extended line 31 */
+#define LL_EXTI_LINE_ALL_0_31          EXTI_IMR1_IM            /*!< All Extended line not reserved*/
+
+#define LL_EXTI_LINE_32                EXTI_IMR2_IM32          /*!< Extended line 32 */
+#define LL_EXTI_LINE_33                EXTI_IMR2_IM33          /*!< Extended line 33 */
+#define LL_EXTI_LINE_34                EXTI_IMR2_IM34          /*!< Extended line 34 */
+#define LL_EXTI_LINE_35                EXTI_IMR2_IM35          /*!< Extended line 35 */
+#define LL_EXTI_LINE_36                EXTI_IMR2_IM36          /*!< Extended line 36 */
+#define LL_EXTI_LINE_37                EXTI_IMR2_IM37          /*!< Extended line 37 */
+#define LL_EXTI_LINE_38                EXTI_IMR2_IM38          /*!< Extended line 38 */
+#define LL_EXTI_LINE_39                EXTI_IMR2_IM39          /*!< Extended line 39 */
+#define LL_EXTI_LINE_40                EXTI_IMR2_IM40          /*!< Extended line 40 */
+#define LL_EXTI_LINE_41                EXTI_IMR2_IM41          /*!< Extended line 41 */
+#define LL_EXTI_LINE_42                EXTI_IMR2_IM42          /*!< Extended line 42 */
+#define LL_EXTI_LINE_43                EXTI_IMR2_IM43          /*!< Extended line 43 */
+#if defined(USB2_OTG_FS)
+#define LL_EXTI_LINE_44                EXTI_IMR2_IM44          /*!< Extended line 44 */
+#endif /* USB2_OTG_FS */
+#if defined(DSI)
+#define LL_EXTI_LINE_46                EXTI_IMR2_IM46          /*!< Extended line 46 */
+#endif /* DSI */
+#define LL_EXTI_LINE_47                EXTI_IMR2_IM47          /*!< Extended line 47 */
+#define LL_EXTI_LINE_48                EXTI_IMR2_IM48          /*!< Extended line 48 */
+#define LL_EXTI_LINE_49                EXTI_IMR2_IM49          /*!< Extended line 49 */
+#define LL_EXTI_LINE_50                EXTI_IMR2_IM50          /*!< Extended line 50 */
+#define LL_EXTI_LINE_51                EXTI_IMR2_IM51          /*!< Extended line 51 */
+#define LL_EXTI_LINE_52                EXTI_IMR2_IM52          /*!< Extended line 52 */
+#define LL_EXTI_LINE_53                EXTI_IMR2_IM53          /*!< Extended line 53 */
+#define LL_EXTI_LINE_54                EXTI_IMR2_IM54          /*!< Extended line 54 */
+#define LL_EXTI_LINE_55                EXTI_IMR2_IM55          /*!< Extended line 55 */
+#define LL_EXTI_LINE_56                EXTI_IMR2_IM56          /*!< Extended line 56 */
+#if defined(EXTI_IMR2_IM57)
+#define LL_EXTI_LINE_57                EXTI_IMR2_IM57          /*!< Extended line 57 */
+#endif /*EXTI_IMR2_IM57*/
+#define LL_EXTI_LINE_58                EXTI_IMR2_IM58          /*!< Extended line 58 */
+#if defined(EXTI_IMR2_IM59)
+#define LL_EXTI_LINE_59                EXTI_IMR2_IM59          /*!< Extended line 59 */
+#endif /*EXTI_IMR2_IM59*/
+#define LL_EXTI_LINE_60                EXTI_IMR2_IM60          /*!< Extended line 60 */
+#define LL_EXTI_LINE_61                EXTI_IMR2_IM61          /*!< Extended line 61 */
+#define LL_EXTI_LINE_62                EXTI_IMR2_IM62          /*!< Extended line 62 */
+#define LL_EXTI_LINE_63                EXTI_IMR2_IM63          /*!< Extended line 63 */
+#define LL_EXTI_LINE_ALL_32_63         EXTI_IMR2_IM            /*!< All Extended line not reserved*/
+
+#define LL_EXTI_LINE_64                EXTI_IMR3_IM64          /*!< Extended line 64 */
+#define LL_EXTI_LINE_65                EXTI_IMR3_IM65          /*!< Extended line 65 */
+#define LL_EXTI_LINE_66                EXTI_IMR3_IM66          /*!< Extended line 66 */
+#define LL_EXTI_LINE_67                EXTI_IMR3_IM67          /*!< Extended line 67 */
+#define LL_EXTI_LINE_68                EXTI_IMR3_IM68          /*!< Extended line 68 */
+#define LL_EXTI_LINE_69                EXTI_IMR3_IM69          /*!< Extended line 69 */
+#define LL_EXTI_LINE_70                EXTI_IMR3_IM70          /*!< Extended line 70 */
+#define LL_EXTI_LINE_71                EXTI_IMR3_IM71          /*!< Extended line 71 */
+#define LL_EXTI_LINE_72                EXTI_IMR3_IM72          /*!< Extended line 72 */
+#define LL_EXTI_LINE_73                EXTI_IMR3_IM73          /*!< Extended line 73 */
+#define LL_EXTI_LINE_74                EXTI_IMR3_IM74          /*!< Extended line 74 */
+#if defined(ADC3)
+#define LL_EXTI_LINE_75                EXTI_IMR3_IM75          /*!< Extended line 75 */
+#endif /* ADC3 */
+#if defined(SAI4)
+#define LL_EXTI_LINE_76                EXTI_IMR3_IM76          /*!< Extended line 76 */
+#endif /* SAI4 */
+#if defined(DUAL_CORE)
+#define LL_EXTI_LINE_77                EXTI_IMR3_IM77          /*!< Extended line 77 */
+#define LL_EXTI_LINE_78                EXTI_IMR3_IM78          /*!< Extended line 78 */
+#define LL_EXTI_LINE_79                EXTI_IMR3_IM79          /*!< Extended line 79 */
+#define LL_EXTI_LINE_80                EXTI_IMR3_IM80          /*!< Extended line 80 */
+#define LL_EXTI_LINE_82                EXTI_IMR3_IM82          /*!< Extended line 82 */
+#define LL_EXTI_LINE_84                EXTI_IMR3_IM84          /*!< Extended line 84 */
+#endif /* DUAL_CORE */
+#define LL_EXTI_LINE_85                EXTI_IMR3_IM85          /*!< Extended line 85 */
+#if defined(ETH)
+#define LL_EXTI_LINE_86                EXTI_IMR3_IM86          /*!< Extended line 86 */
+#endif /* ETH */
+#define LL_EXTI_LINE_87                EXTI_IMR3_IM87          /*!< Extended line 87 */
+#if defined(DTS)
+#define LL_EXTI_LINE_88                EXTI_IMR3_IM88          /*!< Extended line 88 */
+#endif /* DTS */
+#if defined(EXTI_IMR3_IM89)
+#define LL_EXTI_LINE_89                EXTI_IMR3_IM89          /*!< Extended line 89 */
+#endif /* EXTI_IMR3_IM89 */
+#if defined(EXTI_IMR3_IM90)
+#define LL_EXTI_LINE_90                EXTI_IMR3_IM90          /*!< Extended line 90 */
+#endif /* EXTI_IMR3_IM90 */
+#if defined(I2C5)
+#define LL_EXTI_LINE_91                EXTI_IMR3_IM91          /*!< Extended line 91 */
+#endif /* I2C5 */
+#define LL_EXTI_LINE_ALL_64_95         EXTI_IMR3_IM            /*!< All Extended line not reserved*/
+
+
+#define LL_EXTI_LINE_ALL               (0xFFFFFFFFU)  /*!< All Extended line */
+
+#if defined(USE_FULL_LL_DRIVER)
+#define LL_EXTI_LINE_NONE              (0x00000000U)  /*!< None Extended line */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/**
+  * @}
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/** @defgroup EXTI_LL_EC_MODE Mode
+  * @{
+  */
+#define LL_EXTI_MODE_IT               ((uint8_t)0x01U)      /*!< Cortex-M7 Interrupt Mode  */
+#define LL_EXTI_MODE_EVENT            ((uint8_t)0x02U)      /*!< Cortex-M7 Event Mode */
+#define LL_EXTI_MODE_IT_EVENT         ((uint8_t)0x03U)      /*!< Cortex-M7 Interrupt & Event Mode */
+
+#if defined(DUAL_CORE)
+#define LL_EXTI_MODE_C1_IT            LL_EXTI_MODE_IT       /*!< Cortex-M7 Interrupt Mode */
+#define LL_EXTI_MODE_C1_EVENT         LL_EXTI_MODE_EVENT    /*!< Cortex-M7 Event Mode */
+#define LL_EXTI_MODE_C1_IT_EVENT      LL_EXTI_MODE_IT_EVENT /*!< Cortex-M7 Interrupt & Event Mode */
+
+#define LL_EXTI_MODE_C2_IT            ((uint8_t)0x10U)      /*!< Cortex-M4 Interrupt Mode  */
+#define LL_EXTI_MODE_C2_EVENT         ((uint8_t)0x20U)      /*!< Cortex-M4 Event Mode  */
+#define LL_EXTI_MODE_C2_IT_EVENT      ((uint8_t)0x30U)      /*!< Cortex-M4 Interrupt & Event Mode */
+#endif /* DUAL_CORE */
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger
+  * @{
+  */
+#define LL_EXTI_TRIGGER_NONE            ((uint8_t)0x00U) /*!< No Trigger Mode */
+#define LL_EXTI_TRIGGER_RISING          ((uint8_t)0x01U) /*!< Trigger Rising Mode */
+#define LL_EXTI_TRIGGER_FALLING         ((uint8_t)0x02U) /*!< Trigger Falling Mode */
+#define LL_EXTI_TRIGGER_RISING_FALLING  ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_LL_D3_PEND_CLR D3 Pend Clear Source
+  * @{
+  */
+#define LL_EXTI_D3_PEND_CLR_DMACH6      ((uint8_t)0x00U) /*!< DMA ch6 event selected as D3 domain pendclear source */
+#define LL_EXTI_D3_PEND_CLR_DMACH7      ((uint8_t)0x01U) /*!< DMA ch7 event selected as D3 domain pendclear source */
+#if defined (LPTIM4)
+#define LL_EXTI_D3_PEND_CLR_LPTIM4      ((uint8_t)0x02U) /*!< LPTIM4 out selected as D3 domain pendclear source */
+#else
+#define LL_EXTI_D3_PEND_CLR_LPTIM2      ((uint8_t)0x02U) /*!< LPTIM2 out selected as D3 domain pendclear source */
+#endif /*LPTIM4*/
+#if defined (LPTIM5)
+#define LL_EXTI_D3_PEND_CLR_LPTIM5      ((uint8_t)0x03U) /*!< LPTIM5 out selected as D3 domain pendclear source */
+#else
+#define LL_EXTI_D3_PEND_CLR_LPTIM3      ((uint8_t)0x02U) /*!< LPTIM3 out selected as D3 domain pendclear source */
+#endif /*LPTIM5*/
+/**
+  * @}
+  */
+
+
+#endif /*USE_FULL_LL_DRIVER*/
+
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros
+  * @{
+  */
+
+/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in EXTI register
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in EXTI register
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__)
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions
+ * @{
+ */
+/** @defgroup EXTI_LL_EF_IT_Management IT_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable ExtiLine Interrupt request for Lines in range 0 to 31
+  * @rmtoll IMR1         IMx           LL_EXTI_EnableIT_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23
+  *         @arg @ref LL_EXTI_LINE_24
+  *         @arg @ref LL_EXTI_LINE_25
+  *         @arg @ref LL_EXTI_LINE_26
+  *         @arg @ref LL_EXTI_LINE_27
+  *         @arg @ref LL_EXTI_LINE_28
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->IMR1, ExtiLine);
+}
+
+/**
+  * @brief  Enable ExtiLine Interrupt request for Lines in range 32 to 63
+  * @rmtoll IMR2         IMx           LL_EXTI_EnableIT_32_63
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_32
+  *         @arg @ref LL_EXTI_LINE_33
+  *         @arg @ref LL_EXTI_LINE_34
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_36
+  *         @arg @ref LL_EXTI_LINE_37
+  *         @arg @ref LL_EXTI_LINE_38
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_41
+  *         @arg @ref LL_EXTI_LINE_42
+  *         @arg @ref LL_EXTI_LINE_43
+  *         @arg @ref LL_EXTI_LINE_44 (*)
+  *         @arg @ref LL_EXTI_LINE_46 (*)
+  *         @arg @ref LL_EXTI_LINE_47
+  *         @arg @ref LL_EXTI_LINE_48
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_50
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_52
+  *         @arg @ref LL_EXTI_LINE_53
+  *         @arg @ref LL_EXTI_LINE_54
+  *         @arg @ref LL_EXTI_LINE_55
+  *         @arg @ref LL_EXTI_LINE_56
+  *         @arg @ref LL_EXTI_LINE_57 (*)
+  *         @arg @ref LL_EXTI_LINE_58
+  *         @arg @ref LL_EXTI_LINE_59 (*)
+  *         @arg @ref LL_EXTI_LINE_60
+  *         @arg @ref LL_EXTI_LINE_61
+  *         @arg @ref LL_EXTI_LINE_62
+  *         @arg @ref LL_EXTI_LINE_63
+  *         @arg @ref LL_EXTI_LINE_ALL_32_63
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableIT_32_63(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->IMR2, ExtiLine);
+}
+
+
+/**
+  * @brief  Enable ExtiLine Interrupt request for Lines in range 64 to 95
+  * @rmtoll IMR3         IMx           LL_EXTI_EnableIT_64_95
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_64
+  *         @arg @ref LL_EXTI_LINE_65
+  *         @arg @ref LL_EXTI_LINE_66
+  *         @arg @ref LL_EXTI_LINE_67
+  *         @arg @ref LL_EXTI_LINE_68
+  *         @arg @ref LL_EXTI_LINE_69
+  *         @arg @ref LL_EXTI_LINE_70
+  *         @arg @ref LL_EXTI_LINE_71
+  *         @arg @ref LL_EXTI_LINE_72
+  *         @arg @ref LL_EXTI_LINE_73
+  *         @arg @ref LL_EXTI_LINE_74
+  *         @arg @ref LL_EXTI_LINE_75 (*)
+  *         @arg @ref LL_EXTI_LINE_76 (*)
+  *         @arg @ref LL_EXTI_LINE_77 (**)
+  *         @arg @ref LL_EXTI_LINE_78 (**)
+  *         @arg @ref LL_EXTI_LINE_79 (**)
+  *         @arg @ref LL_EXTI_LINE_80 (**)
+  *         @arg @ref LL_EXTI_LINE_82 (**)
+  *         @arg @ref LL_EXTI_LINE_84 (**)
+  *         @arg @ref LL_EXTI_LINE_85
+  *         @arg @ref LL_EXTI_LINE_86 (*)
+  *         @arg @ref LL_EXTI_LINE_87
+  *         @arg @ref LL_EXTI_LINE_88 (*)
+  *         @arg @ref LL_EXTI_LINE_89 (*) 
+  *         @arg @ref LL_EXTI_LINE_90 (*)
+  *         @arg @ref LL_EXTI_LINE_91 (*)
+  *         @arg @ref LL_EXTI_LINE_ALL_64_95
+  *
+  *         (*) value not defined in all devices.
+  *         (**) value only defined in dual core devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableIT_64_95(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->IMR3, ExtiLine);
+}
+
+
+/**
+  * @brief  Disable ExtiLine Interrupt request for Lines in range 0 to 31
+  * @rmtoll IMR1         IMx           LL_EXTI_DisableIT_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23
+  *         @arg @ref LL_EXTI_LINE_24
+  *         @arg @ref LL_EXTI_LINE_25
+  *         @arg @ref LL_EXTI_LINE_26
+  *         @arg @ref LL_EXTI_LINE_27
+  *         @arg @ref LL_EXTI_LINE_28
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->IMR1, ExtiLine);
+}
+
+
+/**
+  * @brief  Disable ExtiLine Interrupt request for Lines in range 32 to 63
+  * @rmtoll IMR2         IMx           LL_EXTI_DisableIT_32_63
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_32
+  *         @arg @ref LL_EXTI_LINE_33
+  *         @arg @ref LL_EXTI_LINE_34
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_36
+  *         @arg @ref LL_EXTI_LINE_37
+  *         @arg @ref LL_EXTI_LINE_38
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_41
+  *         @arg @ref LL_EXTI_LINE_42
+  *         @arg @ref LL_EXTI_LINE_43
+  *         @arg @ref LL_EXTI_LINE_44 (*)
+  *         @arg @ref LL_EXTI_LINE_46 (*)
+  *         @arg @ref LL_EXTI_LINE_47
+  *         @arg @ref LL_EXTI_LINE_48
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_50
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_52
+  *         @arg @ref LL_EXTI_LINE_53
+  *         @arg @ref LL_EXTI_LINE_54
+  *         @arg @ref LL_EXTI_LINE_55
+  *         @arg @ref LL_EXTI_LINE_56
+  *         @arg @ref LL_EXTI_LINE_57 (*)
+  *         @arg @ref LL_EXTI_LINE_58
+  *         @arg @ref LL_EXTI_LINE_59 (*)
+  *         @arg @ref LL_EXTI_LINE_60
+  *         @arg @ref LL_EXTI_LINE_61
+  *         @arg @ref LL_EXTI_LINE_62
+  *         @arg @ref LL_EXTI_LINE_63
+  *         @arg @ref LL_EXTI_LINE_ALL_32_63
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableIT_32_63(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->IMR2, ExtiLine);
+}
+
+/**
+  * @brief  Disable ExtiLine Interrupt request for Lines in range 64 to 95
+  * @rmtoll IMR3         IMx           LL_EXTI_DisableIT_64_95
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_64
+  *         @arg @ref LL_EXTI_LINE_65
+  *         @arg @ref LL_EXTI_LINE_66
+  *         @arg @ref LL_EXTI_LINE_67
+  *         @arg @ref LL_EXTI_LINE_68
+  *         @arg @ref LL_EXTI_LINE_69
+  *         @arg @ref LL_EXTI_LINE_70
+  *         @arg @ref LL_EXTI_LINE_71
+  *         @arg @ref LL_EXTI_LINE_72
+  *         @arg @ref LL_EXTI_LINE_73
+  *         @arg @ref LL_EXTI_LINE_74
+  *         @arg @ref LL_EXTI_LINE_75 (*)
+  *         @arg @ref LL_EXTI_LINE_76 (*)
+  *         @arg @ref LL_EXTI_LINE_77 (**)
+  *         @arg @ref LL_EXTI_LINE_78 (**)
+  *         @arg @ref LL_EXTI_LINE_79 (**)
+  *         @arg @ref LL_EXTI_LINE_80 (**)
+  *         @arg @ref LL_EXTI_LINE_82 (**)
+  *         @arg @ref LL_EXTI_LINE_84 (**)
+  *         @arg @ref LL_EXTI_LINE_85
+  *         @arg @ref LL_EXTI_LINE_86 (*)
+  *         @arg @ref LL_EXTI_LINE_87
+  *         @arg @ref LL_EXTI_LINE_88 (*)
+  *         @arg @ref LL_EXTI_LINE_89 (*) 
+  *         @arg @ref LL_EXTI_LINE_90 (*)
+  *         @arg @ref LL_EXTI_LINE_91 (*)
+  *         @arg @ref LL_EXTI_LINE_ALL_64_95
+  *
+  *         (*) value not defined in all devices.
+  *         (**) value only defined in dual core devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableIT_64_95(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->IMR3, ExtiLine);
+}
+
+
+/**
+  * @brief  Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31
+  * @rmtoll IMR1         IMx           LL_EXTI_IsEnabledIT_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23
+  *         @arg @ref LL_EXTI_LINE_24
+  *         @arg @ref LL_EXTI_LINE_25
+  *         @arg @ref LL_EXTI_LINE_26
+  *         @arg @ref LL_EXTI_LINE_27
+  *         @arg @ref LL_EXTI_LINE_28
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->IMR1, ExtiLine) == (ExtiLine)) ? 1U : 0U);
+}
+
+
+/**
+  * @brief  Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63
+  * @rmtoll IMR2         IMx           LL_EXTI_IsEnabledIT_32_63
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_32
+  *         @arg @ref LL_EXTI_LINE_33
+  *         @arg @ref LL_EXTI_LINE_34
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_36
+  *         @arg @ref LL_EXTI_LINE_37
+  *         @arg @ref LL_EXTI_LINE_38
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_41
+  *         @arg @ref LL_EXTI_LINE_42
+  *         @arg @ref LL_EXTI_LINE_43
+  *         @arg @ref LL_EXTI_LINE_44 (*)
+  *         @arg @ref LL_EXTI_LINE_46 (*)
+  *         @arg @ref LL_EXTI_LINE_47
+  *         @arg @ref LL_EXTI_LINE_48
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_50
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_52
+  *         @arg @ref LL_EXTI_LINE_53
+  *         @arg @ref LL_EXTI_LINE_54
+  *         @arg @ref LL_EXTI_LINE_55
+  *         @arg @ref LL_EXTI_LINE_56
+  *         @arg @ref LL_EXTI_LINE_57 (*)
+  *         @arg @ref LL_EXTI_LINE_58
+  *         @arg @ref LL_EXTI_LINE_59 (*)
+  *         @arg @ref LL_EXTI_LINE_60
+  *         @arg @ref LL_EXTI_LINE_61
+  *         @arg @ref LL_EXTI_LINE_62
+  *         @arg @ref LL_EXTI_LINE_63
+  *         @arg @ref LL_EXTI_LINE_ALL_32_63
+  *
+  *         (*) value not defined in all devices.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_32_63(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->IMR2, ExtiLine) == (ExtiLine)) ? 1U : 0U);
+}
+
+
+/**
+  * @brief  Indicate if ExtiLine Interrupt request is enabled for Lines in range 64 to 95
+  * @rmtoll IMR3         IMx           LL_EXTI_IsEnabledIT_64_95
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_64
+  *         @arg @ref LL_EXTI_LINE_65
+  *         @arg @ref LL_EXTI_LINE_66
+  *         @arg @ref LL_EXTI_LINE_67
+  *         @arg @ref LL_EXTI_LINE_68
+  *         @arg @ref LL_EXTI_LINE_69
+  *         @arg @ref LL_EXTI_LINE_70
+  *         @arg @ref LL_EXTI_LINE_71
+  *         @arg @ref LL_EXTI_LINE_72
+  *         @arg @ref LL_EXTI_LINE_73
+  *         @arg @ref LL_EXTI_LINE_74
+  *         @arg @ref LL_EXTI_LINE_75 (*)
+  *         @arg @ref LL_EXTI_LINE_76 (*)
+  *         @arg @ref LL_EXTI_LINE_77 (**)
+  *         @arg @ref LL_EXTI_LINE_78 (**)
+  *         @arg @ref LL_EXTI_LINE_79 (**)
+  *         @arg @ref LL_EXTI_LINE_80 (**)
+  *         @arg @ref LL_EXTI_LINE_82 (**)
+  *         @arg @ref LL_EXTI_LINE_84 (**)
+  *         @arg @ref LL_EXTI_LINE_85
+  *         @arg @ref LL_EXTI_LINE_86 (*)
+  *         @arg @ref LL_EXTI_LINE_87
+  *         @arg @ref LL_EXTI_LINE_88 (*)
+  *         @arg @ref LL_EXTI_LINE_89 (*) 
+  *         @arg @ref LL_EXTI_LINE_90 (*)
+  *         @arg @ref LL_EXTI_LINE_91 (*)
+  *         @arg @ref LL_EXTI_LINE_ALL_64_95
+  *
+  *         (*) value not defined in all devices.
+  *         (**) value only defined in dual core devices.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_64_95(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->IMR3, ExtiLine) == (ExtiLine)) ? 1U : 0U);
+}
+
+#if defined(DUAL_CORE)
+/**
+  * @brief  Enable ExtiLine Interrupt request for Lines in range 0 to 31 for cpu2
+  * @rmtoll C2IMR1         IMx           LL_C2_EXTI_EnableIT_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23
+  *         @arg @ref LL_EXTI_LINE_24
+  *         @arg @ref LL_EXTI_LINE_25
+  *         @arg @ref LL_EXTI_LINE_26
+  *         @arg @ref LL_EXTI_LINE_27
+  *         @arg @ref LL_EXTI_LINE_28
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @retval None
+  */
+__STATIC_INLINE void LL_C2_EXTI_EnableIT_0_31(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->C2IMR1, ExtiLine);
+}
+
+
+/**
+  * @brief  Enable ExtiLine Interrupt request for Lines in range 32 to 63 for cpu2
+  * @rmtoll C2IMR2         IMx           LL_C2_EXTI_EnableIT_32_63
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_32
+  *         @arg @ref LL_EXTI_LINE_33
+  *         @arg @ref LL_EXTI_LINE_34
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_36
+  *         @arg @ref LL_EXTI_LINE_37
+  *         @arg @ref LL_EXTI_LINE_38
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_41
+  *         @arg @ref LL_EXTI_LINE_42
+  *         @arg @ref LL_EXTI_LINE_43
+  *         @arg @ref LL_EXTI_LINE_44
+  *         @arg @ref LL_EXTI_LINE_46
+  *         @arg @ref LL_EXTI_LINE_47
+  *         @arg @ref LL_EXTI_LINE_48
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_50
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_52
+  *         @arg @ref LL_EXTI_LINE_53
+  *         @arg @ref LL_EXTI_LINE_54
+  *         @arg @ref LL_EXTI_LINE_55
+  *         @arg @ref LL_EXTI_LINE_56
+  *         @arg @ref LL_EXTI_LINE_57
+  *         @arg @ref LL_EXTI_LINE_58
+  *         @arg @ref LL_EXTI_LINE_59
+  *         @arg @ref LL_EXTI_LINE_60
+  *         @arg @ref LL_EXTI_LINE_61
+  *         @arg @ref LL_EXTI_LINE_62
+  *         @arg @ref LL_EXTI_LINE_63
+  *         @arg @ref LL_EXTI_LINE_ALL_32_63
+  * @retval None
+  */
+__STATIC_INLINE void LL_C2_EXTI_EnableIT_32_63(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->C2IMR2, ExtiLine);
+}
+
+
+/**
+  * @brief  Enable ExtiLine Interrupt request for Lines in range 64 to 95
+  * @rmtoll C2IMR3         IMx           LL_C2_EXTI_EnableIT_64_95
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_64
+  *         @arg @ref LL_EXTI_LINE_65
+  *         @arg @ref LL_EXTI_LINE_66
+  *         @arg @ref LL_EXTI_LINE_67
+  *         @arg @ref LL_EXTI_LINE_68
+  *         @arg @ref LL_EXTI_LINE_69
+  *         @arg @ref LL_EXTI_LINE_70
+  *         @arg @ref LL_EXTI_LINE_71
+  *         @arg @ref LL_EXTI_LINE_72
+  *         @arg @ref LL_EXTI_LINE_73
+  *         @arg @ref LL_EXTI_LINE_74
+  *         @arg @ref LL_EXTI_LINE_75
+  *         @arg @ref LL_EXTI_LINE_76
+  *         @arg @ref LL_EXTI_LINE_77
+  *         @arg @ref LL_EXTI_LINE_78
+  *         @arg @ref LL_EXTI_LINE_79
+  *         @arg @ref LL_EXTI_LINE_80
+  *         @arg @ref LL_EXTI_LINE_82
+  *         @arg @ref LL_EXTI_LINE_84
+  *         @arg @ref LL_EXTI_LINE_85
+  *         @arg @ref LL_EXTI_LINE_86
+  *         @arg @ref LL_EXTI_LINE_87
+  *         @arg @ref LL_EXTI_LINE_ALL_64_95
+  * @retval None
+  */
+__STATIC_INLINE void LL_C2_EXTI_EnableIT_64_95(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->C2IMR3, ExtiLine);
+}
+
+
+/**
+  * @brief  Disable ExtiLine Interrupt request for Lines in range 0 to 31 for cpu2
+  * @rmtoll C2IMR1         IMx           LL_C2_EXTI_DisableIT_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23
+  *         @arg @ref LL_EXTI_LINE_24
+  *         @arg @ref LL_EXTI_LINE_25
+  *         @arg @ref LL_EXTI_LINE_26
+  *         @arg @ref LL_EXTI_LINE_27
+  *         @arg @ref LL_EXTI_LINE_28
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @retval None
+  */
+__STATIC_INLINE void LL_C2_EXTI_DisableIT_0_31(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->C2IMR1, ExtiLine);
+}
+
+
+
+/**
+  * @brief  Disable ExtiLine Interrupt request for Lines in range 32 to 63 for cpu2
+  * @rmtoll C2IMR2         IMx           LL_C2_EXTI_DisableIT_32_63
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_32
+  *         @arg @ref LL_EXTI_LINE_33
+  *         @arg @ref LL_EXTI_LINE_34
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_36
+  *         @arg @ref LL_EXTI_LINE_37
+  *         @arg @ref LL_EXTI_LINE_38
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_41
+  *         @arg @ref LL_EXTI_LINE_42
+  *         @arg @ref LL_EXTI_LINE_43
+  *         @arg @ref LL_EXTI_LINE_44
+  *         @arg @ref LL_EXTI_LINE_46
+  *         @arg @ref LL_EXTI_LINE_47
+  *         @arg @ref LL_EXTI_LINE_48
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_50
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_52
+  *         @arg @ref LL_EXTI_LINE_53
+  *         @arg @ref LL_EXTI_LINE_54
+  *         @arg @ref LL_EXTI_LINE_55
+  *         @arg @ref LL_EXTI_LINE_56
+  *         @arg @ref LL_EXTI_LINE_57
+  *         @arg @ref LL_EXTI_LINE_58
+  *         @arg @ref LL_EXTI_LINE_59
+  *         @arg @ref LL_EXTI_LINE_60
+  *         @arg @ref LL_EXTI_LINE_61
+  *         @arg @ref LL_EXTI_LINE_62
+  *         @arg @ref LL_EXTI_LINE_63
+  *         @arg @ref LL_EXTI_LINE_ALL_32_63
+  * @retval None
+  */
+__STATIC_INLINE void LL_C2_EXTI_DisableIT_32_63(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->C2IMR2, ExtiLine);
+}
+
+
+/**
+  * @brief  Disable ExtiLine Interrupt request for Lines in range 64 to 95 for cpu2
+  * @rmtoll C2IMR3         IMx           LL_C2_EXTI_DisableIT_64_95
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_64
+  *         @arg @ref LL_EXTI_LINE_65
+  *         @arg @ref LL_EXTI_LINE_66
+  *         @arg @ref LL_EXTI_LINE_67
+  *         @arg @ref LL_EXTI_LINE_68
+  *         @arg @ref LL_EXTI_LINE_69
+  *         @arg @ref LL_EXTI_LINE_70
+  *         @arg @ref LL_EXTI_LINE_71
+  *         @arg @ref LL_EXTI_LINE_72
+  *         @arg @ref LL_EXTI_LINE_73
+  *         @arg @ref LL_EXTI_LINE_74
+  *         @arg @ref LL_EXTI_LINE_75
+  *         @arg @ref LL_EXTI_LINE_76
+  *         @arg @ref LL_EXTI_LINE_77
+  *         @arg @ref LL_EXTI_LINE_78
+  *         @arg @ref LL_EXTI_LINE_79
+  *         @arg @ref LL_EXTI_LINE_80
+  *         @arg @ref LL_EXTI_LINE_82
+  *         @arg @ref LL_EXTI_LINE_84
+  *         @arg @ref LL_EXTI_LINE_85
+  *         @arg @ref LL_EXTI_LINE_86
+  *         @arg @ref LL_EXTI_LINE_87
+  *         @arg @ref LL_EXTI_LINE_ALL_64_95
+  * @retval None
+  */
+__STATIC_INLINE void LL_C2_EXTI_DisableIT_64_95(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->C2IMR3, ExtiLine);
+}
+
+
+/**
+  * @brief  Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31 for cpu2
+  * @rmtoll C2IMR1         IMx           LL_C2_EXTI_IsEnabledIT_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23
+  *         @arg @ref LL_EXTI_LINE_24
+  *         @arg @ref LL_EXTI_LINE_25
+  *         @arg @ref LL_EXTI_LINE_26
+  *         @arg @ref LL_EXTI_LINE_27
+  *         @arg @ref LL_EXTI_LINE_28
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->C2IMR1, ExtiLine) == (ExtiLine)) ? 1U : 0U);
+}
+
+
+/**
+  * @brief  Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63 for cpu2
+  * @rmtoll C2IMR2         IMx           LL_C2_EXTI_IsEnabledIT_32_63
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_32
+  *         @arg @ref LL_EXTI_LINE_33
+  *         @arg @ref LL_EXTI_LINE_34
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_36
+  *         @arg @ref LL_EXTI_LINE_37
+  *         @arg @ref LL_EXTI_LINE_38
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_41
+  *         @arg @ref LL_EXTI_LINE_42
+  *         @arg @ref LL_EXTI_LINE_43
+  *         @arg @ref LL_EXTI_LINE_44
+  *         @arg @ref LL_EXTI_LINE_46
+  *         @arg @ref LL_EXTI_LINE_47
+  *         @arg @ref LL_EXTI_LINE_48
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_50
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_52
+  *         @arg @ref LL_EXTI_LINE_53
+  *         @arg @ref LL_EXTI_LINE_54
+  *         @arg @ref LL_EXTI_LINE_55
+  *         @arg @ref LL_EXTI_LINE_56
+  *         @arg @ref LL_EXTI_LINE_57
+  *         @arg @ref LL_EXTI_LINE_58
+  *         @arg @ref LL_EXTI_LINE_59
+  *         @arg @ref LL_EXTI_LINE_60
+  *         @arg @ref LL_EXTI_LINE_61
+  *         @arg @ref LL_EXTI_LINE_62
+  *         @arg @ref LL_EXTI_LINE_63
+  *         @arg @ref LL_EXTI_LINE_ALL_32_63
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledIT_32_63(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->C2IMR2, ExtiLine) == (ExtiLine))? 1U : 0U);
+}
+
+
+/**
+  * @brief  Indicate if ExtiLine Interrupt request is enabled for Lines in range 64 to 95
+  * @rmtoll C2IMR3         IMx           LL_C2_EXTI_IsEnabledIT_64_95
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_64
+  *         @arg @ref LL_EXTI_LINE_65
+  *         @arg @ref LL_EXTI_LINE_66
+  *         @arg @ref LL_EXTI_LINE_67
+  *         @arg @ref LL_EXTI_LINE_68
+  *         @arg @ref LL_EXTI_LINE_69
+  *         @arg @ref LL_EXTI_LINE_70
+  *         @arg @ref LL_EXTI_LINE_71
+  *         @arg @ref LL_EXTI_LINE_72
+  *         @arg @ref LL_EXTI_LINE_73
+  *         @arg @ref LL_EXTI_LINE_74
+  *         @arg @ref LL_EXTI_LINE_75
+  *         @arg @ref LL_EXTI_LINE_76
+  *         @arg @ref LL_EXTI_LINE_77
+  *         @arg @ref LL_EXTI_LINE_78
+  *         @arg @ref LL_EXTI_LINE_79
+  *         @arg @ref LL_EXTI_LINE_80
+  *         @arg @ref LL_EXTI_LINE_82
+  *         @arg @ref LL_EXTI_LINE_84
+  *         @arg @ref LL_EXTI_LINE_85
+  *         @arg @ref LL_EXTI_LINE_86
+  *         @arg @ref LL_EXTI_LINE_87
+  *         @arg @ref LL_EXTI_LINE_ALL_64_95
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledIT_64_95(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->C2IMR3, ExtiLine) == (ExtiLine)) ? 1U : 0U);
+}
+
+#endif /* DUAL_CORE */
+
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_LL_EF_Event_Management Event_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable ExtiLine Event request for Lines in range 0 to 31
+  * @rmtoll EMR1         EMx           LL_EXTI_EnableEvent_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23
+  *         @arg @ref LL_EXTI_LINE_24
+  *         @arg @ref LL_EXTI_LINE_25
+  *         @arg @ref LL_EXTI_LINE_26
+  *         @arg @ref LL_EXTI_LINE_27
+  *         @arg @ref LL_EXTI_LINE_28
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->EMR1, ExtiLine);
+}
+
+/**
+  * @brief  Enable ExtiLine Event request for Lines in range 32 to 63
+  * @rmtoll EMR2         EMx           LL_EXTI_EnableEvent_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_32
+  *         @arg @ref LL_EXTI_LINE_33
+  *         @arg @ref LL_EXTI_LINE_34
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_36
+  *         @arg @ref LL_EXTI_LINE_37
+  *         @arg @ref LL_EXTI_LINE_38
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_41
+  *         @arg @ref LL_EXTI_LINE_42
+  *         @arg @ref LL_EXTI_LINE_43
+  *         @arg @ref LL_EXTI_LINE_44 (*)
+  *         @arg @ref LL_EXTI_LINE_46 (*)
+  *         @arg @ref LL_EXTI_LINE_47
+  *         @arg @ref LL_EXTI_LINE_48
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_50
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_52
+  *         @arg @ref LL_EXTI_LINE_53
+  *         @arg @ref LL_EXTI_LINE_54
+  *         @arg @ref LL_EXTI_LINE_55
+  *         @arg @ref LL_EXTI_LINE_56
+  *         @arg @ref LL_EXTI_LINE_57 (*)
+  *         @arg @ref LL_EXTI_LINE_58
+  *         @arg @ref LL_EXTI_LINE_59 (*)
+  *         @arg @ref LL_EXTI_LINE_60
+  *         @arg @ref LL_EXTI_LINE_61
+  *         @arg @ref LL_EXTI_LINE_62
+  *         @arg @ref LL_EXTI_LINE_63
+  *         @arg @ref LL_EXTI_LINE_ALL_32_63
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableEvent_32_63(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->EMR2, ExtiLine);
+}
+
+/**
+  * @brief  Enable ExtiLine Event request for Lines in range 64 to 95
+  * @rmtoll EMR3         EMx           LL_EXTI_EnableEvent_64_95
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_64
+  *         @arg @ref LL_EXTI_LINE_65
+  *         @arg @ref LL_EXTI_LINE_66
+  *         @arg @ref LL_EXTI_LINE_67
+  *         @arg @ref LL_EXTI_LINE_68
+  *         @arg @ref LL_EXTI_LINE_69
+  *         @arg @ref LL_EXTI_LINE_70
+  *         @arg @ref LL_EXTI_LINE_71
+  *         @arg @ref LL_EXTI_LINE_72
+  *         @arg @ref LL_EXTI_LINE_73
+  *         @arg @ref LL_EXTI_LINE_74
+  *         @arg @ref LL_EXTI_LINE_75 (*)
+  *         @arg @ref LL_EXTI_LINE_76 (*)
+  *         @arg @ref LL_EXTI_LINE_77 (**)
+  *         @arg @ref LL_EXTI_LINE_78 (**)
+  *         @arg @ref LL_EXTI_LINE_79 (**)
+  *         @arg @ref LL_EXTI_LINE_80 (**)
+  *         @arg @ref LL_EXTI_LINE_82 (**)
+  *         @arg @ref LL_EXTI_LINE_84 (**)
+  *         @arg @ref LL_EXTI_LINE_85
+  *         @arg @ref LL_EXTI_LINE_86 (*)
+  *         @arg @ref LL_EXTI_LINE_87
+  *         @arg @ref LL_EXTI_LINE_88 (*)
+  *         @arg @ref LL_EXTI_LINE_89 (*)
+  *         @arg @ref LL_EXTI_LINE_90 (*)
+  *         @arg @ref LL_EXTI_LINE_91 (*)
+  *         @arg @ref LL_EXTI_LINE_ALL_64_95
+  *
+  *         (*) value not defined in all devices.
+  *         (**) value only defined in dual core devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableEvent_64_95(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->EMR3, ExtiLine);
+}
+
+/**
+  * @brief  Disable ExtiLine Event request for Lines in range 0 to 31
+  * @rmtoll EMR1         EMx           LL_EXTI_DisableEvent_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23
+  *         @arg @ref LL_EXTI_LINE_24
+  *         @arg @ref LL_EXTI_LINE_25
+  *         @arg @ref LL_EXTI_LINE_26
+  *         @arg @ref LL_EXTI_LINE_27
+  *         @arg @ref LL_EXTI_LINE_28
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->EMR1, ExtiLine);
+}
+
+/**
+  * @brief  Disable ExtiLine Event request for Lines in range 32 to 63
+  * @rmtoll EMR2         EMx           LL_EXTI_DisableEvent_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_32
+  *         @arg @ref LL_EXTI_LINE_33
+  *         @arg @ref LL_EXTI_LINE_34
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_36
+  *         @arg @ref LL_EXTI_LINE_37
+  *         @arg @ref LL_EXTI_LINE_38
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_41
+  *         @arg @ref LL_EXTI_LINE_42
+  *         @arg @ref LL_EXTI_LINE_43
+  *         @arg @ref LL_EXTI_LINE_44 (*)
+  *         @arg @ref LL_EXTI_LINE_46 (*)
+  *         @arg @ref LL_EXTI_LINE_47
+  *         @arg @ref LL_EXTI_LINE_48
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_50
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_52
+  *         @arg @ref LL_EXTI_LINE_53
+  *         @arg @ref LL_EXTI_LINE_54
+  *         @arg @ref LL_EXTI_LINE_55
+  *         @arg @ref LL_EXTI_LINE_56
+  *         @arg @ref LL_EXTI_LINE_57 (*)
+  *         @arg @ref LL_EXTI_LINE_58
+  *         @arg @ref LL_EXTI_LINE_59 (*)
+  *         @arg @ref LL_EXTI_LINE_60
+  *         @arg @ref LL_EXTI_LINE_61
+  *         @arg @ref LL_EXTI_LINE_62
+  *         @arg @ref LL_EXTI_LINE_63
+  *         @arg @ref LL_EXTI_LINE_ALL_32_63
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableEvent_32_63(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->EMR2, ExtiLine);
+}
+
+/**
+  * @brief  Disable ExtiLine Event request for Lines in range 64 to 95
+  * @rmtoll EMR3         EMx           LL_EXTI_DisableEvent_64_95
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_64
+  *         @arg @ref LL_EXTI_LINE_65
+  *         @arg @ref LL_EXTI_LINE_66
+  *         @arg @ref LL_EXTI_LINE_67
+  *         @arg @ref LL_EXTI_LINE_68
+  *         @arg @ref LL_EXTI_LINE_69
+  *         @arg @ref LL_EXTI_LINE_70
+  *         @arg @ref LL_EXTI_LINE_71
+  *         @arg @ref LL_EXTI_LINE_72
+  *         @arg @ref LL_EXTI_LINE_73
+  *         @arg @ref LL_EXTI_LINE_74
+  *         @arg @ref LL_EXTI_LINE_75 (*)
+  *         @arg @ref LL_EXTI_LINE_76 (*)
+  *         @arg @ref LL_EXTI_LINE_77 (**)
+  *         @arg @ref LL_EXTI_LINE_78 (**)
+  *         @arg @ref LL_EXTI_LINE_79 (**)
+  *         @arg @ref LL_EXTI_LINE_80 (**)
+  *         @arg @ref LL_EXTI_LINE_82 (**)
+  *         @arg @ref LL_EXTI_LINE_84 (**)
+  *         @arg @ref LL_EXTI_LINE_85
+  *         @arg @ref LL_EXTI_LINE_86 (*)
+  *         @arg @ref LL_EXTI_LINE_87
+  *         @arg @ref LL_EXTI_LINE_88 (*)
+  *         @arg @ref LL_EXTI_LINE_89 (*)
+  *         @arg @ref LL_EXTI_LINE_90 (*)
+  *         @arg @ref LL_EXTI_LINE_91 (*)
+  *         @arg @ref LL_EXTI_LINE_ALL_64_95
+  *
+  *         (*) value not defined in all devices.
+  *         (**) value only defined in dual core devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableEvent_64_95(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->EMR3, ExtiLine);
+}
+
+/**
+  * @brief  Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31
+  * @rmtoll EMR1         EMx           LL_EXTI_IsEnabledEvent_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23
+  *         @arg @ref LL_EXTI_LINE_24
+  *         @arg @ref LL_EXTI_LINE_25
+  *         @arg @ref LL_EXTI_LINE_26
+  *         @arg @ref LL_EXTI_LINE_27
+  *         @arg @ref LL_EXTI_LINE_28
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->EMR1, ExtiLine) == (ExtiLine)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Indicate if ExtiLine Event request is enabled for Lines in range 32 to 63
+  * @rmtoll EMR2         EMx           LL_EXTI_IsEnabledEvent_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_32
+  *         @arg @ref LL_EXTI_LINE_33
+  *         @arg @ref LL_EXTI_LINE_34
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_36
+  *         @arg @ref LL_EXTI_LINE_37
+  *         @arg @ref LL_EXTI_LINE_38
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_41
+  *         @arg @ref LL_EXTI_LINE_42
+  *         @arg @ref LL_EXTI_LINE_43
+  *         @arg @ref LL_EXTI_LINE_44 (*)
+  *         @arg @ref LL_EXTI_LINE_46 (*)
+  *         @arg @ref LL_EXTI_LINE_47
+  *         @arg @ref LL_EXTI_LINE_48
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_50
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_52
+  *         @arg @ref LL_EXTI_LINE_53
+  *         @arg @ref LL_EXTI_LINE_54
+  *         @arg @ref LL_EXTI_LINE_55
+  *         @arg @ref LL_EXTI_LINE_56
+  *         @arg @ref LL_EXTI_LINE_57 (*)
+  *         @arg @ref LL_EXTI_LINE_58
+  *         @arg @ref LL_EXTI_LINE_59 (*)
+  *         @arg @ref LL_EXTI_LINE_60
+  *         @arg @ref LL_EXTI_LINE_61
+  *         @arg @ref LL_EXTI_LINE_62
+  *         @arg @ref LL_EXTI_LINE_63
+  *         @arg @ref LL_EXTI_LINE_ALL_32_63
+  *
+  *         (*) value not defined in all devices.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_32_63(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->EMR2, ExtiLine) == (ExtiLine)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Indicate if ExtiLine Event request is enabled for Lines in range 64 to 95
+  * @rmtoll EMR3         EMx           LL_EXTI_IsEnabledEvent_64_95
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_64
+  *         @arg @ref LL_EXTI_LINE_65
+  *         @arg @ref LL_EXTI_LINE_66
+  *         @arg @ref LL_EXTI_LINE_67
+  *         @arg @ref LL_EXTI_LINE_68
+  *         @arg @ref LL_EXTI_LINE_69
+  *         @arg @ref LL_EXTI_LINE_70
+  *         @arg @ref LL_EXTI_LINE_71
+  *         @arg @ref LL_EXTI_LINE_72
+  *         @arg @ref LL_EXTI_LINE_73
+  *         @arg @ref LL_EXTI_LINE_74
+  *         @arg @ref LL_EXTI_LINE_75 (*)
+  *         @arg @ref LL_EXTI_LINE_76 (*)
+  *         @arg @ref LL_EXTI_LINE_77 (**)
+  *         @arg @ref LL_EXTI_LINE_78 (**)
+  *         @arg @ref LL_EXTI_LINE_79 (**)
+  *         @arg @ref LL_EXTI_LINE_80 (**)
+  *         @arg @ref LL_EXTI_LINE_82 (**)
+  *         @arg @ref LL_EXTI_LINE_84 (**)
+  *         @arg @ref LL_EXTI_LINE_85
+  *         @arg @ref LL_EXTI_LINE_86 (*)
+  *         @arg @ref LL_EXTI_LINE_87
+  *         @arg @ref LL_EXTI_LINE_88 (*)
+  *         @arg @ref LL_EXTI_LINE_89 (*)
+  *         @arg @ref LL_EXTI_LINE_90 (*)
+  *         @arg @ref LL_EXTI_LINE_91 (*)
+  *         @arg @ref LL_EXTI_LINE_ALL_64_95
+  *
+  *         (*) value not defined in all devices.
+  *         (**) value only defined in dual core devices.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_64_95(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->EMR3, ExtiLine) == (ExtiLine)) ? 1U : 0U);
+}
+
+#if defined(DUAL_CORE)
+
+/**
+  * @brief  Enable ExtiLine Event request for Lines in range 0 to 31 for cpu2
+  * @rmtoll C2EMR1         EMx           LL_C2_EXTI_EnableEvent_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23
+  *         @arg @ref LL_EXTI_LINE_24
+  *         @arg @ref LL_EXTI_LINE_25
+  *         @arg @ref LL_EXTI_LINE_26
+  *         @arg @ref LL_EXTI_LINE_27
+  *         @arg @ref LL_EXTI_LINE_28
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @retval None
+  */
+__STATIC_INLINE void LL_C2_EXTI_EnableEvent_0_31(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->C2EMR1, ExtiLine);
+}
+
+
+/**
+  * @brief  Enable ExtiLine Event request for Lines in range 32 to 63 for cpu2
+  * @rmtoll C2EMR2         EMx           LL_C2_EXTI_EnableEvent_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_32
+  *         @arg @ref LL_EXTI_LINE_33
+  *         @arg @ref LL_EXTI_LINE_34
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_36
+  *         @arg @ref LL_EXTI_LINE_37
+  *         @arg @ref LL_EXTI_LINE_38
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_41
+  *         @arg @ref LL_EXTI_LINE_42
+  *         @arg @ref LL_EXTI_LINE_43
+  *         @arg @ref LL_EXTI_LINE_44
+  *         @arg @ref LL_EXTI_LINE_46
+  *         @arg @ref LL_EXTI_LINE_47
+  *         @arg @ref LL_EXTI_LINE_48
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_50
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_52
+  *         @arg @ref LL_EXTI_LINE_53
+  *         @arg @ref LL_EXTI_LINE_54
+  *         @arg @ref LL_EXTI_LINE_55
+  *         @arg @ref LL_EXTI_LINE_56
+  *         @arg @ref LL_EXTI_LINE_57
+  *         @arg @ref LL_EXTI_LINE_58
+  *         @arg @ref LL_EXTI_LINE_59
+  *         @arg @ref LL_EXTI_LINE_60
+  *         @arg @ref LL_EXTI_LINE_61
+  *         @arg @ref LL_EXTI_LINE_62
+  *         @arg @ref LL_EXTI_LINE_63
+  *         @arg @ref LL_EXTI_LINE_ALL_32_63
+  * @retval None
+  */
+__STATIC_INLINE void LL_C2_EXTI_EnableEvent_32_63(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->C2EMR2, ExtiLine);
+}
+
+/**
+  * @brief  Enable ExtiLine Event request for Lines in range 64 to 95 for cpu2
+  * @rmtoll C2EMR3         EMx           LL_C2_EXTI_EnableEvent_64_95
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_64
+  *         @arg @ref LL_EXTI_LINE_65
+  *         @arg @ref LL_EXTI_LINE_66
+  *         @arg @ref LL_EXTI_LINE_67
+  *         @arg @ref LL_EXTI_LINE_68
+  *         @arg @ref LL_EXTI_LINE_69
+  *         @arg @ref LL_EXTI_LINE_70
+  *         @arg @ref LL_EXTI_LINE_71
+  *         @arg @ref LL_EXTI_LINE_72
+  *         @arg @ref LL_EXTI_LINE_73
+  *         @arg @ref LL_EXTI_LINE_74
+  *         @arg @ref LL_EXTI_LINE_75
+  *         @arg @ref LL_EXTI_LINE_76
+  *         @arg @ref LL_EXTI_LINE_77
+  *         @arg @ref LL_EXTI_LINE_78
+  *         @arg @ref LL_EXTI_LINE_79
+  *         @arg @ref LL_EXTI_LINE_80
+  *         @arg @ref LL_EXTI_LINE_82
+  *         @arg @ref LL_EXTI_LINE_84
+  *         @arg @ref LL_EXTI_LINE_85
+  *         @arg @ref LL_EXTI_LINE_86
+  *         @arg @ref LL_EXTI_LINE_87
+  *         @arg @ref LL_EXTI_LINE_ALL_64_95
+  * @retval None
+  */
+__STATIC_INLINE void LL_C2_EXTI_EnableEvent_64_95(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->C2EMR3, ExtiLine);
+}
+
+
+/**
+  * @brief  Disable ExtiLine Event request for Lines in range 0 to 31 for cpu2
+  * @rmtoll C2EMR1         EMx           LL_C2_EXTI_DisableEvent_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23
+  *         @arg @ref LL_EXTI_LINE_24
+  *         @arg @ref LL_EXTI_LINE_25
+  *         @arg @ref LL_EXTI_LINE_26
+  *         @arg @ref LL_EXTI_LINE_27
+  *         @arg @ref LL_EXTI_LINE_28
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @retval None
+  */
+__STATIC_INLINE void LL_C2_EXTI_DisableEvent_0_31(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->C2EMR1, ExtiLine);
+}
+
+
+/**
+  * @brief  Disable ExtiLine Event request for Lines in range 32 to 63 for cpu2
+  * @rmtoll C2EMR2         EMx           LL_C2_EXTI_DisableEvent_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_32
+  *         @arg @ref LL_EXTI_LINE_33
+  *         @arg @ref LL_EXTI_LINE_34
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_36
+  *         @arg @ref LL_EXTI_LINE_37
+  *         @arg @ref LL_EXTI_LINE_38
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_41
+  *         @arg @ref LL_EXTI_LINE_42
+  *         @arg @ref LL_EXTI_LINE_43
+  *         @arg @ref LL_EXTI_LINE_44
+  *         @arg @ref LL_EXTI_LINE_46
+  *         @arg @ref LL_EXTI_LINE_47
+  *         @arg @ref LL_EXTI_LINE_48
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_50
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_52
+  *         @arg @ref LL_EXTI_LINE_53
+  *         @arg @ref LL_EXTI_LINE_54
+  *         @arg @ref LL_EXTI_LINE_55
+  *         @arg @ref LL_EXTI_LINE_56
+  *         @arg @ref LL_EXTI_LINE_57
+  *         @arg @ref LL_EXTI_LINE_58
+  *         @arg @ref LL_EXTI_LINE_59
+  *         @arg @ref LL_EXTI_LINE_60
+  *         @arg @ref LL_EXTI_LINE_61
+  *         @arg @ref LL_EXTI_LINE_62
+  *         @arg @ref LL_EXTI_LINE_63
+  *         @arg @ref LL_EXTI_LINE_ALL_32_63
+  * @retval None
+  */
+__STATIC_INLINE void LL_C2_EXTI_DisableEvent_32_63(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->C2EMR2, ExtiLine);
+}
+
+
+/**
+  * @brief  Disable ExtiLine Event request for Lines in range 64 to 95 for cpu2
+  * @rmtoll C2EMR3         EMx           LL_C2_EXTI_DisableEvent_64_95
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_64
+  *         @arg @ref LL_EXTI_LINE_65
+  *         @arg @ref LL_EXTI_LINE_66
+  *         @arg @ref LL_EXTI_LINE_67
+  *         @arg @ref LL_EXTI_LINE_68
+  *         @arg @ref LL_EXTI_LINE_69
+  *         @arg @ref LL_EXTI_LINE_70
+  *         @arg @ref LL_EXTI_LINE_71
+  *         @arg @ref LL_EXTI_LINE_72
+  *         @arg @ref LL_EXTI_LINE_73
+  *         @arg @ref LL_EXTI_LINE_74
+  *         @arg @ref LL_EXTI_LINE_75
+  *         @arg @ref LL_EXTI_LINE_76
+  *         @arg @ref LL_EXTI_LINE_77
+  *         @arg @ref LL_EXTI_LINE_78
+  *         @arg @ref LL_EXTI_LINE_79
+  *         @arg @ref LL_EXTI_LINE_80
+  *         @arg @ref LL_EXTI_LINE_82
+  *         @arg @ref LL_EXTI_LINE_84
+  *         @arg @ref LL_EXTI_LINE_85
+  *         @arg @ref LL_EXTI_LINE_86
+  *         @arg @ref LL_EXTI_LINE_87
+  *         @arg @ref LL_EXTI_LINE_ALL_64_95
+  * @retval None
+  */
+__STATIC_INLINE void LL_C2_EXTI_DisableEvent_64_95(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->C2EMR3, ExtiLine);
+}
+
+
+/**
+  * @brief  Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31 for cpu2
+  * @rmtoll C2EMR1         EMx           LL_C2_EXTI_IsEnabledEvent_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23
+  *         @arg @ref LL_EXTI_LINE_24
+  *         @arg @ref LL_EXTI_LINE_25
+  *         @arg @ref LL_EXTI_LINE_26
+  *         @arg @ref LL_EXTI_LINE_27
+  *         @arg @ref LL_EXTI_LINE_28
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->C2EMR1, ExtiLine) == (ExtiLine)) ? 1U : 0U);
+}
+
+
+/**
+  * @brief  Indicate if ExtiLine Event request is enabled for Lines in range 32 to 63 for cpu2
+  * @rmtoll C2EMR2         EMx           LL_C2_EXTI_IsEnabledEvent_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_32
+  *         @arg @ref LL_EXTI_LINE_33
+  *         @arg @ref LL_EXTI_LINE_34
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_36
+  *         @arg @ref LL_EXTI_LINE_37
+  *         @arg @ref LL_EXTI_LINE_38
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_41
+  *         @arg @ref LL_EXTI_LINE_42
+  *         @arg @ref LL_EXTI_LINE_43
+  *         @arg @ref LL_EXTI_LINE_44
+  *         @arg @ref LL_EXTI_LINE_46
+  *         @arg @ref LL_EXTI_LINE_47
+  *         @arg @ref LL_EXTI_LINE_48
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_50
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_52
+  *         @arg @ref LL_EXTI_LINE_53
+  *         @arg @ref LL_EXTI_LINE_54
+  *         @arg @ref LL_EXTI_LINE_55
+  *         @arg @ref LL_EXTI_LINE_56
+  *         @arg @ref LL_EXTI_LINE_57
+  *         @arg @ref LL_EXTI_LINE_58
+  *         @arg @ref LL_EXTI_LINE_59
+  *         @arg @ref LL_EXTI_LINE_60
+  *         @arg @ref LL_EXTI_LINE_61
+  *         @arg @ref LL_EXTI_LINE_62
+  *         @arg @ref LL_EXTI_LINE_63
+  *         @arg @ref LL_EXTI_LINE_ALL_32_63
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledEvent_32_63(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->C2EMR2, ExtiLine) == (ExtiLine)) ? 1U : 0U);
+}
+
+
+/**
+  * @brief  Indicate if ExtiLine Event request is enabled for Lines in range 64 to 95 for cpu2
+  * @rmtoll C2EMR3         EMx           LL_C2_EXTI_IsEnabledEvent_64_95
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_64
+  *         @arg @ref LL_EXTI_LINE_65
+  *         @arg @ref LL_EXTI_LINE_66
+  *         @arg @ref LL_EXTI_LINE_67
+  *         @arg @ref LL_EXTI_LINE_68
+  *         @arg @ref LL_EXTI_LINE_69
+  *         @arg @ref LL_EXTI_LINE_70
+  *         @arg @ref LL_EXTI_LINE_71
+  *         @arg @ref LL_EXTI_LINE_72
+  *         @arg @ref LL_EXTI_LINE_73
+  *         @arg @ref LL_EXTI_LINE_74
+  *         @arg @ref LL_EXTI_LINE_75
+  *         @arg @ref LL_EXTI_LINE_76
+  *         @arg @ref LL_EXTI_LINE_77
+  *         @arg @ref LL_EXTI_LINE_78
+  *         @arg @ref LL_EXTI_LINE_79
+  *         @arg @ref LL_EXTI_LINE_80
+  *         @arg @ref LL_EXTI_LINE_82
+  *         @arg @ref LL_EXTI_LINE_84
+  *         @arg @ref LL_EXTI_LINE_85
+  *         @arg @ref LL_EXTI_LINE_86
+  *         @arg @ref LL_EXTI_LINE_87
+  *         @arg @ref LL_EXTI_LINE_ALL_64_95
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledEvent_64_95(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->C2EMR3, ExtiLine) == (ExtiLine)) ? 1U : 0U);
+}
+
+
+#endif /* DUAL_CORE */
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a rising edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_RTSR register, the
+  *       pending bit is not set.
+  *       Rising and falling edge triggers can be set for
+  *       the same interrupt line. In this case, both generate a trigger
+  *       condition.
+  * @rmtoll RTSR1        RTx           LL_EXTI_EnableRisingTrig_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->RTSR1, ExtiLine);
+
+}
+
+/**
+  * @brief  Enable ExtiLine Rising Edge Trigger for Lines in range 32 to 63
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a rising edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_RTSR register, the
+  *       pending bit is not set.Rising and falling edge triggers can be set for
+  *       the same interrupt line. In this case, both generate a trigger
+  *       condition.
+  * @rmtoll RTSR2        RTx           LL_EXTI_EnableRisingTrig_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_51
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableRisingTrig_32_63(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->RTSR2, ExtiLine);
+}
+
+/**
+  * @brief  Enable ExtiLine Rising Edge Trigger for Lines in range 64 to 95
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a rising edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_RTSR register, the
+  *       pending bit is not set.Rising and falling edge triggers can be set for
+  *       the same interrupt line. In this case, both generate a trigger
+  *       condition.
+  * @rmtoll RTSR3        RTx           LL_EXTI_EnableRisingTrig_64_95
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_82 (*)
+  *         @arg @ref LL_EXTI_LINE_84 (*)
+  *         @arg @ref LL_EXTI_LINE_85
+  *         @arg @ref LL_EXTI_LINE_86 (**)
+  *
+  *         (*) value only defined in dual core devices.
+  *         (**) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableRisingTrig_64_95(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->RTSR3, ExtiLine);
+}
+
+/**
+  * @brief  Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a rising edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_RTSR register, the
+  *       pending bit is not set.
+  *       Rising and falling edge triggers can be set for
+  *       the same interrupt line. In this case, both generate a trigger
+  *       condition.
+  * @rmtoll RTSR1        RTx           LL_EXTI_DisableRisingTrig_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->RTSR1, ExtiLine);
+
+}
+
+/**
+  * @brief  Disable ExtiLine Rising Edge Trigger for Lines in range 32 to 63
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a rising edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_RTSR register, the
+  *       pending bit is not set.
+  *       Rising and falling edge triggers can be set for
+  *       the same interrupt line. In this case, both generate a trigger
+  *       condition.
+  * @rmtoll RTSR2        RTx           LL_EXTI_DisableRisingTrig_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_51
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableRisingTrig_32_63(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->RTSR2, ExtiLine);
+}
+
+/**
+  * @brief  Disable ExtiLine Rising Edge Trigger for Lines in range 64 to 95
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a rising edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_RTSR register, the
+  *       pending bit is not set.
+  *       Rising and falling edge triggers can be set for
+  *       the same interrupt line. In this case, both generate a trigger
+  *       condition.
+  * @rmtoll RTSR3        RTx           LL_EXTI_DisableRisingTrig_64_95
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_82 (*)
+  *         @arg @ref LL_EXTI_LINE_84 (*)
+  *         @arg @ref LL_EXTI_LINE_85
+  *         @arg @ref LL_EXTI_LINE_86 (**)
+  *
+  *         (*) value only defined in dual core devices.
+  *         (**) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableRisingTrig_64_95(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->RTSR3, ExtiLine);
+}
+
+/**
+  * @brief  Check if rising edge trigger is enabled for Lines in range 0 to 31
+  * @rmtoll RTSR1        RTx           LL_EXTI_IsEnabledRisingTrig_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->RTSR1, ExtiLine) == (ExtiLine)) ? 1U : 0U);
+}
+
+
+/**
+  * @brief  Check if rising edge trigger is enabled for Lines in range 32 to 63
+  * @rmtoll RTSR2        RTx           LL_EXTI_IsEnabledRisingTrig_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_51
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_32_63(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->RTSR2, ExtiLine) == (ExtiLine)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Check if rising edge trigger is enabled for Lines in range 64 to 95
+  * @rmtoll RTSR3        RTx           LL_EXTI_IsEnabledRisingTrig_64_95
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_82 (*)
+  *         @arg @ref LL_EXTI_LINE_84 (*)
+  *         @arg @ref LL_EXTI_LINE_85
+  *         @arg @ref LL_EXTI_LINE_86 (**)
+  *
+  *         (*) value only defined in dual core devices.
+  *         (**) value not defined in all devices.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_64_95(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->RTSR3, ExtiLine) == (ExtiLine)) ? 1U : 0U);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a falling edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_FTSR register, the
+  *       pending bit is not set.
+  *       Rising and falling edge triggers can be set for
+  *       the same interrupt line. In this case, both generate a trigger
+  *       condition.
+  * @rmtoll FTSR1        FTx           LL_EXTI_EnableFallingTrig_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->FTSR1, ExtiLine);
+}
+
+/**
+  * @brief  Enable ExtiLine Falling Edge Trigger for Lines in range 32 to 63
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a Falling edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_FTSR register, the
+  *       pending bit is not set.
+  *       Rising and falling edge triggers can be set for
+  *       the same interrupt line. In this case, both generate a trigger
+  *       condition.
+  * @rmtoll FTSR2        FTx           LL_EXTI_EnableFallingTrig_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_51
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableFallingTrig_32_63(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->FTSR2, ExtiLine);
+}
+
+/**
+  * @brief  Enable ExtiLine Falling Edge Trigger for Lines in range 64 to 95
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a Falling edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_FTSR register, the
+  *       pending bit is not set.
+  *       Rising and falling edge triggers can be set for
+  *       the same interrupt line. In this case, both generate a trigger
+  *       condition.
+  * @rmtoll FTSR3        FTx           LL_EXTI_EnableFallingTrig_64_95
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_82 (*)
+  *         @arg @ref LL_EXTI_LINE_84 (*)
+  *         @arg @ref LL_EXTI_LINE_85
+  *         @arg @ref LL_EXTI_LINE_86 (**)
+  *
+  *         (*) value only defined in dual core devices.
+  *         (**) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableFallingTrig_64_95(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->FTSR3, ExtiLine);
+}
+
+
+/**
+  * @brief  Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a Falling edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_FTSR register, the
+  *       pending bit is not set.
+  *       Rising and falling edge triggers can be set for the same interrupt line.
+  *       In this case, both generate a trigger condition.
+  * @rmtoll FTSR1        FTx           LL_EXTI_DisableFallingTrig_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->FTSR1, ExtiLine);
+}
+
+/**
+  * @brief  Disable ExtiLine Falling Edge Trigger for Lines in range 32 to 63
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a Falling edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_FTSR register, the
+  *       pending bit is not set.
+  *       Rising and falling edge triggers can be set for the same interrupt line.
+  *       In this case, both generate a trigger condition.
+  * @rmtoll FTSR2        FTx           LL_EXTI_DisableFallingTrig_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_51
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableFallingTrig_32_63(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->FTSR2, ExtiLine);
+}
+
+/**
+  * @brief  Disable ExtiLine Falling Edge Trigger for Lines in range 64 to 95
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a Falling edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_FTSR register, the
+  *       pending bit is not set.
+  *       Rising and falling edge triggers can be set for the same interrupt line.
+  *       In this case, both generate a trigger condition.
+  * @rmtoll FTSR3        FTx           LL_EXTI_DisableFallingTrig_64_95
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_82 (*)
+  *         @arg @ref LL_EXTI_LINE_84 (*)
+  *         @arg @ref LL_EXTI_LINE_85
+  *         @arg @ref LL_EXTI_LINE_86 (**)
+  *
+  *         (*) value only defined in dual core devices.
+  *         (**) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableFallingTrig_64_95(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->FTSR3, ExtiLine);
+}
+
+
+/**
+  * @brief  Check if falling edge trigger is enabled for Lines in range 0 to 31
+  * @rmtoll FTSR1        FTx           LL_EXTI_IsEnabledFallingTrig_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->FTSR1, ExtiLine) == (ExtiLine)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Check if falling edge trigger is enabled for Lines in range 32 to 63
+  * @rmtoll FTSR2        FTx           LL_EXTI_IsEnabledFallingTrig_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_51
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_32_63(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->FTSR2, ExtiLine) == (ExtiLine)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Check if falling edge trigger is enabled for Lines in range 64 to 95
+  * @rmtoll FTSR3        FTx           LL_EXTI_IsEnabledFallingTrig_64_95
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_82 (*)
+  *         @arg @ref LL_EXTI_LINE_84 (*)
+  *         @arg @ref LL_EXTI_LINE_85
+  *         @arg @ref LL_EXTI_LINE_86 (**)
+  *
+  *         (*) value only defined in dual core devices.
+  *         (**) value not defined in all devices.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_64_95(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->FTSR3, ExtiLine) == (ExtiLine)) ? 1U : 0U);
+}
+
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management
+  * @{
+  */
+
+/**
+  * @brief  Generate a software Interrupt Event for Lines in range 0 to 31
+  * @note If the interrupt is enabled on this line in the EXTI_C1IMR1, writing a 1 to
+  *       this bit when it is at '0' sets the corresponding pending bit in EXTI_PR1
+  *       resulting in an interrupt request generation.
+  *       This bit is cleared by clearing the corresponding bit in the EXTI_PR1
+  *       register (by writing a 1 into the bit)
+  * @rmtoll SWIER1       SWIx          LL_EXTI_GenerateSWI_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->SWIER1, ExtiLine);
+}
+
+/**
+  * @brief  Generate a software Interrupt Event for Lines in range 32 to 63
+  * @note If the interrupt is enabled on this line in the EXTI_IMR2, writing a 1 to
+  *       this bit when it is at '0' sets the corresponding pending bit in EXTI_PR2
+  *       resulting in an interrupt request generation.
+  *       This bit is cleared by clearing the corresponding bit in the EXTI_PR2
+  *       register (by writing a 1 into the bit)
+  * @rmtoll SWIER2       SWIx          LL_EXTI_GenerateSWI_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_51
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_GenerateSWI_32_63(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->SWIER2, ExtiLine);
+}
+
+/**
+  * @brief  Generate a software Interrupt Event for Lines in range 64 to 95
+  * @note If the interrupt is enabled on this line in the EXTI_IMR2, writing a 1 to
+  *       this bit when it is at '0' sets the corresponding pending bit in EXTI_PR2
+  *       resulting in an interrupt request generation.
+  *       This bit is cleared by clearing the corresponding bit in the EXTI_PR3
+  *       register (by writing a 1 into the bit)
+  * @rmtoll SWIER3       SWIx          LL_EXTI_GenerateSWI_64_95
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_82 (*)
+  *         @arg @ref LL_EXTI_LINE_84 (*)
+  *         @arg @ref LL_EXTI_LINE_85
+  *         @arg @ref LL_EXTI_LINE_86 (**)
+  *
+  *         (*) value only defined in dual core devices.
+  *         (**) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_GenerateSWI_64_95(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->SWIER3, ExtiLine);
+}
+
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management
+  * @{
+  */
+
+/**
+  * @brief  Check if the ExtLine Flag is set or not for Lines in range 0 to 31
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll PR1          PIFx           LL_EXTI_IsActiveFlag_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->PR1, ExtiLine) == (ExtiLine)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Check if the ExtLine Flag is set or not for  Lines in range 32 to 63
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll PR2          PIFx           LL_EXTI_IsActiveFlag_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_ALL_32_63
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_32_63(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->PR2, ExtiLine) == (ExtiLine)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Check if the ExtLine Flag is set or not for  Lines in range 64 to 95
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll PR3          PIFx           LL_EXTI_IsActiveFlag_64_95
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_82 (*)
+  *         @arg @ref LL_EXTI_LINE_84 (*)
+  *         @arg @ref LL_EXTI_LINE_85
+  *         @arg @ref LL_EXTI_LINE_86 (**)
+  *
+  *         (*) value only defined in dual core devices.
+  *         (**) value not defined in all devices.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_64_95(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->PR3, ExtiLine) == (ExtiLine)) ? 1U : 0U);
+}
+
+
+/**
+  * @brief  Read ExtLine Combination Flag for Lines in range 0 to 31
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll PR1          PIFx           LL_EXTI_ReadFlag_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  * @retval @note This bit is set when the selected edge event arrives on the interrupt
+  */
+__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine)
+{
+  return (uint32_t)(READ_BIT(EXTI->PR1, ExtiLine));
+}
+
+
+/**
+  * @brief  Read ExtLine Combination Flag for  Lines in range 32 to 63
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll PR2          PIFx           LL_EXTI_ReadFlag_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_51
+  * @retval @note This bit is set when the selected edge event arrives on the interrupt
+  */
+__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_32_63(uint32_t ExtiLine)
+{
+  return (uint32_t)(READ_BIT(EXTI->PR2, ExtiLine));
+}
+
+
+/**
+  * @brief  Read ExtLine Combination Flag for  Lines in range 64 to 95
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll PR3          PIFx           LL_EXTI_ReadFlag_64_95
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_82 (*)
+  *         @arg @ref LL_EXTI_LINE_84 (*)
+  *         @arg @ref LL_EXTI_LINE_85
+  *         @arg @ref LL_EXTI_LINE_86 (**)
+  *
+  *         (*) value only defined in dual core devices.
+  *         (**) value not defined in all devices.
+  * @retval @note This bit is set when the selected edge event arrives on the interrupt
+  */
+__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_64_95(uint32_t ExtiLine)
+{
+  return (uint32_t)(READ_BIT(EXTI->PR3, ExtiLine));
+}
+
+/**
+  * @brief  Clear ExtLine Flags for Lines in range 0 to 31
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll PR1          PIFx           LL_EXTI_ClearFlag_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine)
+{
+  WRITE_REG(EXTI->PR1, ExtiLine);
+}
+
+/**
+  * @brief  Clear ExtLine Flags for Lines in range 32 to 63
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll PR2          PIFx           LL_EXTI_ClearFlag_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_51
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_ClearFlag_32_63(uint32_t ExtiLine)
+{
+  WRITE_REG(EXTI->PR2, ExtiLine);
+}
+
+/**
+  * @brief  Clear ExtLine Flags for Lines in range 64 to 95
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll PR3          PIFx           LL_EXTI_ClearFlag_64_95
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_82 (*)
+  *         @arg @ref LL_EXTI_LINE_84 (*)
+  *         @arg @ref LL_EXTI_LINE_85
+  *         @arg @ref LL_EXTI_LINE_86 (**)
+  *
+  *         (*) value only defined in dual core devices.
+  *         (**) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_ClearFlag_64_95(uint32_t ExtiLine)
+{
+  WRITE_REG(EXTI->PR3, ExtiLine);
+}
+
+#if defined(DUAL_CORE)
+
+/**
+  * @brief  Check if the ExtLine Flag is set or not for Lines in range 0 to 31 for cpu2
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll C2PR1          PIFx           LL_C2_EXTI_IsActiveFlag_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C2_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->C2PR1, ExtiLine) == (ExtiLine)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Check if the ExtLine Flag is set or not for  Lines in range 32 to 63 for cpu2
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll C2PR2          PIFx           LL_C2_EXTI_IsActiveFlag_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_ALL_32_63
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C2_EXTI_IsActiveFlag_32_63(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->C2PR2, ExtiLine) == (ExtiLine)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Check if the ExtLine Flag is set or not for  Lines in range 64 to 95 for cpu2
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll C2PR3          PIFx           LL_C2_EXTI_IsActiveFlag_64_95
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_82
+  *         @arg @ref LL_EXTI_LINE_84
+  *         @arg @ref LL_EXTI_LINE_85
+  *         @arg @ref LL_EXTI_LINE_86
+  *         @arg @ref LL_EXTI_LINE_ALL_64_95
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C2_EXTI_IsActiveFlag_64_95(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->C2PR3, ExtiLine) == (ExtiLine)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Read ExtLine Combination Flag for Lines in range 0 to 31 for cpu2
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll C2PR1          PIFx           LL_C2_EXTI_ReadFlag_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  * @retval @note This bit is set when the selected edge event arrives on the interrupt
+  */
+__STATIC_INLINE uint32_t LL_C2_EXTI_ReadFlag_0_31(uint32_t ExtiLine)
+{
+  return (uint32_t)(READ_BIT(EXTI->C2PR1, ExtiLine));
+}
+
+/**
+  * @brief  Read ExtLine Combination Flag for  Lines in range 32 to 63 for cpu2
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll C2PR2          PIFx           LL_C2_EXTI_ReadFlag_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_51
+  * @retval @note This bit is set when the selected edge event arrives on the interrupt
+  */
+__STATIC_INLINE uint32_t LL_C2_EXTI_ReadFlag_32_63(uint32_t ExtiLine)
+{
+  return (uint32_t)(READ_BIT(EXTI->C2PR2, ExtiLine));
+}
+
+
+/**
+  * @brief  Read ExtLine Combination Flag for  Lines in range 64 to 95 for cpu2
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll C2PR3          PIFx           LL_C2_EXTI_ReadFlag_64_95
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_82
+  *         @arg @ref LL_EXTI_LINE_84
+  *         @arg @ref LL_EXTI_LINE_85
+  *         @arg @ref LL_EXTI_LINE_86
+  * @retval @note This bit is set when the selected edge event arrives on the interrupt
+  */
+__STATIC_INLINE uint32_t LL_C2_EXTI_ReadFlag_64_95(uint32_t ExtiLine)
+{
+  return (uint32_t)(READ_BIT(EXTI->C2PR3, ExtiLine));
+}
+/**
+  * @brief  Clear ExtLine Flags for Lines in range 0 to 31 for cpu2
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll C2PR1          PIFx           LL_C2_EXTI_ClearFlag_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  * @retval None
+  */
+__STATIC_INLINE void LL_C2_EXTI_ClearFlag_0_31(uint32_t ExtiLine)
+{
+  WRITE_REG(EXTI->C2PR1, ExtiLine);
+}
+
+/**
+  * @brief  Clear ExtLine Flags for Lines in range 32 to 63 for cpu2
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll C2PR2          PIFx           LL_C2_EXTI_ClearFlag_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_51
+  * @retval None
+  */
+__STATIC_INLINE void LL_C2_EXTI_ClearFlag_32_63(uint32_t ExtiLine)
+{
+  WRITE_REG(EXTI->C2PR2, ExtiLine);
+}
+
+/**
+  * @brief  Clear ExtLine Flags for Lines in range 64 to 95 for cpu2
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll C2PR3          PIFx           LL_C2_EXTI_ClearFlag_64_95
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_82
+  *         @arg @ref LL_EXTI_LINE_84
+  *         @arg @ref LL_EXTI_LINE_85
+  *         @arg @ref LL_EXTI_LINE_86
+  * @retval None
+  */
+__STATIC_INLINE void LL_C2_EXTI_ClearFlag_64_95(uint32_t ExtiLine)
+{
+  WRITE_REG(EXTI->C2PR3, ExtiLine);
+}
+
+#endif /* DUAL_CORE */
+
+/**
+  * @brief  Enable ExtiLine D3 Pending Mask for Lines in range 0 to 31
+  * @rmtoll D3PMR1         MRx           LL_D3_EXTI_EnablePendMask_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_25
+  * @retval None
+  */
+__STATIC_INLINE void LL_D3_EXTI_EnablePendMask_0_31(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->D3PMR1, ExtiLine);
+}
+
+/**
+  * @brief  Enable ExtiLine D3 Pending Mask for Lines in range 32 to 63
+  * @rmtoll D3PMR2         MRx           LL_D3_EXTI_EnablePendMask_32_63
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_34
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_41
+  *         @arg @ref LL_EXTI_LINE_48
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_50
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_52
+  *         @arg @ref LL_EXTI_LINE_53
+  * @retval None
+  */
+__STATIC_INLINE void LL_D3_EXTI_EnablePendMask_32_63(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->D3PMR2, ExtiLine);
+}
+
+/**
+  * @brief  Disable ExtiLine D3 Pending Mask for Lines in range 0 to 31
+  * @rmtoll D3PMR1         MRx           LL_D3_EXTI_DisablePendMask_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_25
+  * @retval None
+  */
+__STATIC_INLINE void LL_D3_EXTI_DisablePendMask_0_31(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->D3PMR1, ExtiLine);
+}
+
+/**
+  * @brief  Disable ExtiLine D3 Pending Mask for Lines in range 32 to 63
+  * @rmtoll D3PMR2         MRx           LL_D3_EXTI_DisablePendMask_32_63
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_34
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_41
+  *         @arg @ref LL_EXTI_LINE_48
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_50
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_52
+  *         @arg @ref LL_EXTI_LINE_53
+  * @retval None
+  */
+__STATIC_INLINE void LL_D3_EXTI_DisablePendMask_32_63(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->D3PMR2, ExtiLine);
+}
+
+/**
+  * @brief  Indicate if ExtiLine D3 Pending Mask is enabled for Lines in range 0 to 31
+  * @rmtoll D3PMR1         MRx           LL_D3_EXTI_IsEnabledPendMask_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_25
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_D3_EXTI_IsEnabledPendMask_0_31(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->D3PMR1, ExtiLine) == (ExtiLine)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Indicate if ExtiLine D3 Pending Mask is enabled for Lines in range 32 to 63
+  * @rmtoll D3PMR2         MRx           LL_D3_EXTI_IsEnabledPendMask_32_63
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_34
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_41
+  *         @arg @ref LL_EXTI_LINE_48
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_50
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_52
+  *         @arg @ref LL_EXTI_LINE_53
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_D3_EXTI_IsEnabledPendMask_32_63(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->D3PMR2, ExtiLine) == (ExtiLine)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Set ExtLine D3 Domain Pend Clear Source selection for Lines in range 0 to 15
+  * @rmtoll D3PCR1L          PCSx           LL_D3_EXTI_SetPendClearSel_0_15
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  * @param  ClrSrc This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4 (*)
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5 (*)
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM2 (*)
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM3 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_D3_EXTI_SetPendClearSel_0_15(uint32_t ExtiLine, uint32_t ClrSrc)
+{
+  MODIFY_REG(EXTI->D3PCR1L, ((ExtiLine * ExtiLine) * 3UL), ((ExtiLine * ExtiLine) * ClrSrc));
+}
+
+/**
+  * @brief  Set ExtLine D3 Domain Pend Clear Source selection for Lines in range 16 to 31
+  * @rmtoll D3PCR1H          PCSx           LL_D3_EXTI_SetPendClearSel_16_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_25
+  * @param  ClrSrc This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4 (*)
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5 (*)
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM2 (*)
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM3 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_D3_EXTI_SetPendClearSel_16_31(uint32_t ExtiLine, uint32_t ClrSrc)
+{
+  MODIFY_REG(EXTI->D3PCR1H, (((ExtiLine >> EXTI_IMR1_IM16_Pos) * (ExtiLine >> EXTI_IMR1_IM16_Pos)) * 3UL), (((ExtiLine >> EXTI_IMR1_IM16_Pos) * (ExtiLine >> EXTI_IMR1_IM16_Pos)) * ClrSrc));
+}
+
+
+/**
+  * @brief  Set ExtLine D3 Domain Pend Clear Source selection for Lines in range 32 to 47
+  * @rmtoll D3PCR2L          PCSx           LL_D3_EXTI_SetPendClearSel_32_47
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_34
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_41
+  * @param  ClrSrc This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4 (*)
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5 (*)
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM2 (*)
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM3 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_D3_EXTI_SetPendClearSel_32_47(uint32_t ExtiLine, uint32_t ClrSrc)
+{
+  MODIFY_REG(EXTI->D3PCR2L, ((ExtiLine * ExtiLine) * 3UL), ((ExtiLine * ExtiLine) * ClrSrc));
+}
+
+/**
+  * @brief  Set ExtLine D3 Domain Pend Clear Source selection for Lines in range 48 to 63
+  * @rmtoll D3PCR2H          PCSx           LL_D3_EXTI_SetPendClearSel_48_63
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_48
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_50
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_52
+  *         @arg @ref LL_EXTI_LINE_53
+  * @param  ClrSrc This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4 (*)
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5 (*)
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM2 (*)
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM3 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_D3_EXTI_SetPendClearSel_48_63(uint32_t ExtiLine, uint32_t ClrSrc)
+{
+  MODIFY_REG(EXTI->D3PCR2H, (((ExtiLine >> EXTI_IMR2_IM48_Pos) * (ExtiLine >> EXTI_IMR2_IM48_Pos)) * 3UL), (((ExtiLine >> EXTI_IMR2_IM48_Pos) * (ExtiLine >> EXTI_IMR2_IM48_Pos)) * ClrSrc));
+}
+
+/**
+  * @brief  Get ExtLine D3 Domain Pend Clear Source selection for Lines in range 0 to 15
+  * @rmtoll D3PCR1L          PCSx           LL_D3_EXTI_GetPendClearSel_0_15
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4 (*)
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5 (*)
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM2 (*)
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM3 (*)
+  *
+  *         (*) value not defined in all devices.
+  */
+__STATIC_INLINE uint32_t LL_D3_EXTI_GetPendClearSel_0_15(uint32_t ExtiLine)
+{
+  return (uint32_t)(READ_BIT(EXTI->D3PCR1L, ((ExtiLine * ExtiLine) * 3UL)) / (ExtiLine * ExtiLine));
+}
+
+/**
+  * @brief  Get ExtLine D3 Domain Pend Clear Source selection for Lines in range 16 to 31
+  * @rmtoll D3PCR1H          PCSx           LL_D3_EXTI_GetPendClearSel_16_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_25
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4 (*)
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5 (*)
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM2 (*)
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM3 (*)
+  *
+  *         (*) value not defined in all devices.
+  */
+__STATIC_INLINE uint32_t LL_D3_EXTI_GetPendClearSel_16_31(uint32_t ExtiLine)
+{
+  return (uint32_t)(READ_BIT(EXTI->D3PCR1H, (((ExtiLine >> EXTI_IMR1_IM16_Pos) * (ExtiLine >> EXTI_IMR1_IM16_Pos)) * 3UL)) / ((ExtiLine >> EXTI_IMR1_IM16_Pos) * (ExtiLine >> EXTI_IMR1_IM16_Pos)));
+}
+
+/**
+  * @brief  Get ExtLine D3 Domain Pend Clear Source selection for Lines in range 32 to 47
+  * @rmtoll D3PCR2L          PCSx           LL_D3_EXTI_GetPendClearSel_32_47
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_34
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_41
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4 (*)
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5 (*)
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM2 (*)
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM3 (*)
+  *
+  *         (*) value not defined in all devices.
+  */
+__STATIC_INLINE uint32_t LL_D3_EXTI_GetPendClearSel_32_47(uint32_t ExtiLine)
+{
+  return (uint32_t)(READ_BIT(EXTI->D3PCR2L, ((ExtiLine * ExtiLine) * 3UL)) / (ExtiLine * ExtiLine));
+}
+
+/**
+  * @brief  Get ExtLine D3 Domain Pend Clear Source selection for Lines in range 48 to 63
+  * @rmtoll D3PCR2H          PCSx           LL_D3_EXTI_GetPendClearSel_48_63
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_48
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_50
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_52
+  *         @arg @ref LL_EXTI_LINE_53
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4 (*)
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5 (*)
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM2 (*)
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM3 (*)
+  *
+  *         (*) value not defined in all devices.
+  */
+__STATIC_INLINE uint32_t LL_D3_EXTI_GetPendClearSel_48_63(uint32_t ExtiLine)
+{
+  return (uint32_t)(READ_BIT(EXTI->D3PCR2H, (((ExtiLine >> EXTI_IMR2_IM48_Pos) * (ExtiLine >> EXTI_IMR2_IM48_Pos)) * 3UL)) / ((ExtiLine >> EXTI_IMR2_IM48_Pos) * (ExtiLine >> EXTI_IMR2_IM48_Pos)));
+}
+
+
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions
+  * @{,
+  */
+
+ErrorStatus LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct);
+ErrorStatus LL_EXTI_DeInit(void);
+void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct);
+
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* EXTI */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32H7xx_LL_EXTI_H */
+
diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_gpio.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_gpio.h
index b51f9d3b..31dff598 100644
--- a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_gpio.h
+++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_gpio.h
@@ -1,984 +1,984 @@
-/**
-  ******************************************************************************
-  * @file    stm32h7xx_ll_gpio.h
-  * @author  MCD Application Team
-  * @brief   Header file of GPIO LL module.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32H7xx_LL_GPIO_H
-#define STM32H7xx_LL_GPIO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx.h"
-
-/** @addtogroup STM32H7xx_LL_Driver
-  * @{
-  */
-
-#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK)
-
-/** @defgroup GPIO_LL GPIO
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup GPIO_LL_Private_Macros GPIO Private Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures
-  * @{
-  */
-
-/**
-  * @brief LL GPIO Init Structure definition
-  */
-typedef struct
-{
-  uint32_t Pin;          /*!< Specifies the GPIO pins to be configured.
-                              This parameter can be any value of @ref GPIO_LL_EC_PIN */
-
-  uint32_t Mode;         /*!< Specifies the operating mode for the selected pins.
-                              This parameter can be a value of @ref GPIO_LL_EC_MODE.
-
-                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/
-
-  uint32_t Speed;        /*!< Specifies the speed for the selected pins.
-                              This parameter can be a value of @ref GPIO_LL_EC_SPEED.
-
-                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/
-
-  uint32_t OutputType;   /*!< Specifies the operating output type for the selected pins.
-                              This parameter can be a value of @ref GPIO_LL_EC_OUTPUT.
-
-                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/
-
-  uint32_t Pull;         /*!< Specifies the operating Pull-up/Pull down for the selected pins.
-                              This parameter can be a value of @ref GPIO_LL_EC_PULL.
-
-                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/
-
-  uint32_t Alternate;    /*!< Specifies the Peripheral to be connected to the selected pins.
-                              This parameter can be a value of @ref GPIO_LL_EC_AF.
-
-                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().*/
-} LL_GPIO_InitTypeDef;
-
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants
-  * @{
-  */
-
-/** @defgroup GPIO_LL_EC_PIN PIN
-  * @{
-  */
-#define LL_GPIO_PIN_0                      GPIO_BSRR_BS0 /*!< Select pin 0 */
-#define LL_GPIO_PIN_1                      GPIO_BSRR_BS1 /*!< Select pin 1 */
-#define LL_GPIO_PIN_2                      GPIO_BSRR_BS2 /*!< Select pin 2 */
-#define LL_GPIO_PIN_3                      GPIO_BSRR_BS3 /*!< Select pin 3 */
-#define LL_GPIO_PIN_4                      GPIO_BSRR_BS4 /*!< Select pin 4 */
-#define LL_GPIO_PIN_5                      GPIO_BSRR_BS5 /*!< Select pin 5 */
-#define LL_GPIO_PIN_6                      GPIO_BSRR_BS6 /*!< Select pin 6 */
-#define LL_GPIO_PIN_7                      GPIO_BSRR_BS7 /*!< Select pin 7 */
-#define LL_GPIO_PIN_8                      GPIO_BSRR_BS8 /*!< Select pin 8 */
-#define LL_GPIO_PIN_9                      GPIO_BSRR_BS9 /*!< Select pin 9 */
-#define LL_GPIO_PIN_10                     GPIO_BSRR_BS10 /*!< Select pin 10 */
-#define LL_GPIO_PIN_11                     GPIO_BSRR_BS11 /*!< Select pin 11 */
-#define LL_GPIO_PIN_12                     GPIO_BSRR_BS12 /*!< Select pin 12 */
-#define LL_GPIO_PIN_13                     GPIO_BSRR_BS13 /*!< Select pin 13 */
-#define LL_GPIO_PIN_14                     GPIO_BSRR_BS14 /*!< Select pin 14 */
-#define LL_GPIO_PIN_15                     GPIO_BSRR_BS15 /*!< Select pin 15 */
-#define LL_GPIO_PIN_ALL                    (GPIO_BSRR_BS0 | GPIO_BSRR_BS1  | GPIO_BSRR_BS2  | \
-                                           GPIO_BSRR_BS3  | GPIO_BSRR_BS4  | GPIO_BSRR_BS5  | \
-                                           GPIO_BSRR_BS6  | GPIO_BSRR_BS7  | GPIO_BSRR_BS8  | \
-                                           GPIO_BSRR_BS9  | GPIO_BSRR_BS10 | GPIO_BSRR_BS11 | \
-                                           GPIO_BSRR_BS12 | GPIO_BSRR_BS13 | GPIO_BSRR_BS14 | \
-                                           GPIO_BSRR_BS15) /*!< Select all pins */
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_LL_EC_MODE Mode
-  * @{
-  */
-#define LL_GPIO_MODE_INPUT                 (0x00000000U) /*!< Select input mode */
-#define LL_GPIO_MODE_OUTPUT                GPIO_MODER_MODE0_0  /*!< Select output mode */
-#define LL_GPIO_MODE_ALTERNATE             GPIO_MODER_MODE0_1  /*!< Select alternate function mode */
-#define LL_GPIO_MODE_ANALOG                GPIO_MODER_MODE0    /*!< Select analog mode */
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_LL_EC_OUTPUT Output Type
-  * @{
-  */
-#define LL_GPIO_OUTPUT_PUSHPULL            (0x00000000U) /*!< Select push-pull as output type */
-#define LL_GPIO_OUTPUT_OPENDRAIN           GPIO_OTYPER_OT0 /*!< Select open-drain as output type */
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_LL_EC_SPEED Output Speed
-  * @{
-  */
-#define LL_GPIO_SPEED_FREQ_LOW             (0x00000000U) /*!< Select I/O low output speed    */
-#define LL_GPIO_SPEED_FREQ_MEDIUM          GPIO_OSPEEDR_OSPEED0_0 /*!< Select I/O medium output speed */
-#define LL_GPIO_SPEED_FREQ_HIGH            GPIO_OSPEEDR_OSPEED0_1 /*!< Select I/O fast output speed   */
-#define LL_GPIO_SPEED_FREQ_VERY_HIGH       GPIO_OSPEEDR_OSPEED0   /*!< Select I/O high output speed   */
-/**
-  * @}
-  */
-#define LL_GPIO_SPEED_LOW                  LL_GPIO_SPEED_FREQ_LOW
-#define LL_GPIO_SPEED_MEDIUM               LL_GPIO_SPEED_FREQ_MEDIUM
-#define LL_GPIO_SPEED_FAST                 LL_GPIO_SPEED_FREQ_HIGH
-#define LL_GPIO_SPEED_HIGH                 LL_GPIO_SPEED_FREQ_VERY_HIGH
-
-
-/** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down
-  * @{
-  */
-#define LL_GPIO_PULL_NO                    (0x00000000U) /*!< Select I/O no pull */
-#define LL_GPIO_PULL_UP                    GPIO_PUPDR_PUPD0_0 /*!< Select I/O pull up */
-#define LL_GPIO_PULL_DOWN                  GPIO_PUPDR_PUPD0_1 /*!< Select I/O pull down */
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_LL_EC_AF Alternate Function
-  * @{
-  */
-#define LL_GPIO_AF_0                       (0x0000000U) /*!< Select alternate function 0 */
-#define LL_GPIO_AF_1                       (0x0000001U) /*!< Select alternate function 1 */
-#define LL_GPIO_AF_2                       (0x0000002U) /*!< Select alternate function 2 */
-#define LL_GPIO_AF_3                       (0x0000003U) /*!< Select alternate function 3 */
-#define LL_GPIO_AF_4                       (0x0000004U) /*!< Select alternate function 4 */
-#define LL_GPIO_AF_5                       (0x0000005U) /*!< Select alternate function 5 */
-#define LL_GPIO_AF_6                       (0x0000006U) /*!< Select alternate function 6 */
-#define LL_GPIO_AF_7                       (0x0000007U) /*!< Select alternate function 7 */
-#define LL_GPIO_AF_8                       (0x0000008U) /*!< Select alternate function 8 */
-#define LL_GPIO_AF_9                       (0x0000009U) /*!< Select alternate function 9 */
-#define LL_GPIO_AF_10                      (0x000000AU) /*!< Select alternate function 10 */
-#define LL_GPIO_AF_11                      (0x000000BU) /*!< Select alternate function 11 */
-#define LL_GPIO_AF_12                      (0x000000CU) /*!< Select alternate function 12 */
-#define LL_GPIO_AF_13                      (0x000000DU) /*!< Select alternate function 13 */
-#define LL_GPIO_AF_14                      (0x000000EU) /*!< Select alternate function 14 */
-#define LL_GPIO_AF_15                      (0x000000FU) /*!< Select alternate function 15 */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros
-  * @{
-  */
-
-/** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros
-  * @{
-  */
-
-/**
-  * @brief  Write a value in GPIO register
-  * @param  __INSTANCE__ GPIO Instance
-  * @param  __REG__ Register to be written
-  * @param  __VALUE__ Value to be written in the register
-  * @retval None
-  */
-#define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
-  * @brief  Read a value in GPIO register
-  * @param  __INSTANCE__ GPIO Instance
-  * @param  __REG__ Register to be read
-  * @retval Register value
-  */
-#define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions
-  * @{
-  */
-
-/** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration
-  * @{
-  */
-
-/**
-  * @brief  Configure gpio mode for a dedicated pin on dedicated port.
-  * @note   I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
-  * @note   Warning: only one pin can be passed as parameter.
-  * @rmtoll MODER        MODEy         LL_GPIO_SetPinMode
-  * @param  GPIOx GPIO Port
-  * @param  Pin This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  * @param  Mode This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_MODE_INPUT
-  *         @arg @ref LL_GPIO_MODE_OUTPUT
-  *         @arg @ref LL_GPIO_MODE_ALTERNATE
-  *         @arg @ref LL_GPIO_MODE_ANALOG
-  * @retval None
-  */
-__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
-{
-  MODIFY_REG(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODE0), ((Pin * Pin) * Mode));
-}
-
-/**
-  * @brief  Return gpio mode for a dedicated pin on dedicated port.
-  * @note   I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
-  * @note   Warning: only one pin can be passed as parameter.
-  * @rmtoll MODER        MODEy         LL_GPIO_GetPinMode
-  * @param  GPIOx GPIO Port
-  * @param  Pin This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_GPIO_MODE_INPUT
-  *         @arg @ref LL_GPIO_MODE_OUTPUT
-  *         @arg @ref LL_GPIO_MODE_ALTERNATE
-  *         @arg @ref LL_GPIO_MODE_ANALOG
-  */
-__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin)
-{
-  return (uint32_t)(READ_BIT(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODE0)) / (Pin * Pin));
-}
-
-/**
-  * @brief  Configure gpio output type for several pins on dedicated port.
-  * @note   Output type as to be set when gpio pin is in output or
-  *         alternate modes. Possible type are Push-pull or Open-drain.
-  * @rmtoll OTYPER       OTy           LL_GPIO_SetPinOutputType
-  * @param  GPIOx GPIO Port
-  * @param  PinMask This parameter can be a combination of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  *         @arg @ref LL_GPIO_PIN_ALL
-  * @param  OutputType This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_OUTPUT_PUSHPULL
-  *         @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
-  * @retval None
-  */
-__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType)
-{
-  MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType));
-}
-
-/**
-  * @brief  Return gpio output type for several pins on dedicated port.
-  * @note   Output type as to be set when gpio pin is in output or
-  *         alternate modes. Possible type are Push-pull or Open-drain.
-  * @note   Warning: only one pin can be passed as parameter.
-  * @rmtoll OTYPER       OTy           LL_GPIO_GetPinOutputType
-  * @param  GPIOx GPIO Port
-  * @param  Pin This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  *         @arg @ref LL_GPIO_PIN_ALL
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_GPIO_OUTPUT_PUSHPULL
-  *         @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
-  */
-__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin)
-{
-  return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) / Pin);
-}
-
-/**
-  * @brief  Configure gpio speed for a dedicated pin on dedicated port.
-  * @note   I/O speed can be Low, Medium, Fast or High speed.
-  * @note   Warning: only one pin can be passed as parameter.
-  * @note   Refer to datasheet for frequency specifications and the power
-  *         supply and load conditions for each speed.
-  * @rmtoll OSPEEDR      OSPEEDy       LL_GPIO_SetPinSpeed
-  * @param  GPIOx GPIO Port
-  * @param  Pin This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  * @param  Speed This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_SPEED_FREQ_LOW
-  *         @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
-  *         @arg @ref LL_GPIO_SPEED_FREQ_HIGH
-  *         @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH
-  * @retval None
-  */
-__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t  Speed)
-{
-  MODIFY_REG(GPIOx->OSPEEDR, ((Pin * Pin) * GPIO_OSPEEDR_OSPEED0), ((Pin * Pin) * Speed));
-}
-
-/**
-  * @brief  Return gpio speed for a dedicated pin on dedicated port.
-  * @note   I/O speed can be Low, Medium, Fast or High speed.
-  * @note   Warning: only one pin can be passed as parameter.
-  * @note   Refer to datasheet for frequency specifications and the power
-  *         supply and load conditions for each speed.
-  * @rmtoll OSPEEDR      OSPEEDy       LL_GPIO_GetPinSpeed
-  * @param  GPIOx GPIO Port
-  * @param  Pin This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_GPIO_SPEED_FREQ_LOW
-  *         @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
-  *         @arg @ref LL_GPIO_SPEED_FREQ_HIGH
-  *         @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH
-  */
-__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin)
-{
-  return (uint32_t)(READ_BIT(GPIOx->OSPEEDR, ((Pin * Pin) * GPIO_OSPEEDR_OSPEED0)) / (Pin * Pin));
-}
-
-/**
-  * @brief  Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.
-  * @note   Warning: only one pin can be passed as parameter.
-  * @rmtoll PUPDR        PUPDy         LL_GPIO_SetPinPull
-  * @param  GPIOx GPIO Port
-  * @param  Pin This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  * @param  Pull This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_PULL_NO
-  *         @arg @ref LL_GPIO_PULL_UP
-  *         @arg @ref LL_GPIO_PULL_DOWN
-  * @retval None
-  */
-__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)
-{
-  MODIFY_REG(GPIOx->PUPDR, ((Pin * Pin) * GPIO_PUPDR_PUPD0), ((Pin * Pin) * Pull));
-}
-
-/**
-  * @brief  Return gpio pull-up or pull-down for a dedicated pin on a dedicated port
-  * @note   Warning: only one pin can be passed as parameter.
-  * @rmtoll PUPDR        PUPDy         LL_GPIO_GetPinPull
-  * @param  GPIOx GPIO Port
-  * @param  Pin This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_GPIO_PULL_NO
-  *         @arg @ref LL_GPIO_PULL_UP
-  *         @arg @ref LL_GPIO_PULL_DOWN
-  */
-__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin)
-{
-  return (uint32_t)(READ_BIT(GPIOx->PUPDR, ((Pin * Pin) * GPIO_PUPDR_PUPD0)) / (Pin * Pin));
-}
-
-/**
-  * @brief  Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
-  * @note   Possible values are from AF0 to AF15 depending on target.
-  * @note   Warning: only one pin can be passed as parameter.
-  * @rmtoll AFRL         AFSELy        LL_GPIO_SetAFPin_0_7
-  * @param  GPIOx GPIO Port
-  * @param  Pin This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  * @param  Alternate This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_AF_0
-  *         @arg @ref LL_GPIO_AF_1
-  *         @arg @ref LL_GPIO_AF_2
-  *         @arg @ref LL_GPIO_AF_3
-  *         @arg @ref LL_GPIO_AF_4
-  *         @arg @ref LL_GPIO_AF_5
-  *         @arg @ref LL_GPIO_AF_6
-  *         @arg @ref LL_GPIO_AF_7
-  *         @arg @ref LL_GPIO_AF_8
-  *         @arg @ref LL_GPIO_AF_9
-  *         @arg @ref LL_GPIO_AF_10
-  *         @arg @ref LL_GPIO_AF_11
-  *         @arg @ref LL_GPIO_AF_12
-  *         @arg @ref LL_GPIO_AF_13
-  *         @arg @ref LL_GPIO_AF_14
-  *         @arg @ref LL_GPIO_AF_15
-  * @retval None
-  */
-__STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
-{
-  MODIFY_REG(GPIOx->AFR[0], ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFSEL0),
-             ((((Pin * Pin) * Pin) * Pin) * Alternate));
-}
-
-/**
-  * @brief  Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
-  * @rmtoll AFRL         AFSELy        LL_GPIO_GetAFPin_0_7
-  * @param  GPIOx GPIO Port
-  * @param  Pin This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_GPIO_AF_0
-  *         @arg @ref LL_GPIO_AF_1
-  *         @arg @ref LL_GPIO_AF_2
-  *         @arg @ref LL_GPIO_AF_3
-  *         @arg @ref LL_GPIO_AF_4
-  *         @arg @ref LL_GPIO_AF_5
-  *         @arg @ref LL_GPIO_AF_6
-  *         @arg @ref LL_GPIO_AF_7
-  *         @arg @ref LL_GPIO_AF_8
-  *         @arg @ref LL_GPIO_AF_9
-  *         @arg @ref LL_GPIO_AF_10
-  *         @arg @ref LL_GPIO_AF_11
-  *         @arg @ref LL_GPIO_AF_12
-  *         @arg @ref LL_GPIO_AF_13
-  *         @arg @ref LL_GPIO_AF_14
-  *         @arg @ref LL_GPIO_AF_15
-  */
-__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin)
-{
-  return (uint32_t)(READ_BIT(GPIOx->AFR[0],
-                             ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFSEL0)) / (((Pin * Pin) * Pin) * Pin));
-}
-
-/**
-  * @brief  Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
-  * @note   Possible values are from AF0 to AF15 depending on target.
-  * @note   Warning: only one pin can be passed as parameter.
-  * @rmtoll AFRH         AFSELy        LL_GPIO_SetAFPin_8_15
-  * @param  GPIOx GPIO Port
-  * @param  Pin This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  * @param  Alternate This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_AF_0
-  *         @arg @ref LL_GPIO_AF_1
-  *         @arg @ref LL_GPIO_AF_2
-  *         @arg @ref LL_GPIO_AF_3
-  *         @arg @ref LL_GPIO_AF_4
-  *         @arg @ref LL_GPIO_AF_5
-  *         @arg @ref LL_GPIO_AF_6
-  *         @arg @ref LL_GPIO_AF_7
-  *         @arg @ref LL_GPIO_AF_8
-  *         @arg @ref LL_GPIO_AF_9
-  *         @arg @ref LL_GPIO_AF_10
-  *         @arg @ref LL_GPIO_AF_11
-  *         @arg @ref LL_GPIO_AF_12
-  *         @arg @ref LL_GPIO_AF_13
-  *         @arg @ref LL_GPIO_AF_14
-  *         @arg @ref LL_GPIO_AF_15
-  * @retval None
-  */
-__STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
-{
-  MODIFY_REG(GPIOx->AFR[1], (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFSEL8),
-             (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * Alternate));
-}
-
-/**
-  * @brief  Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
-  * @note   Possible values are from AF0 to AF15 depending on target.
-  * @rmtoll AFRH         AFSELy        LL_GPIO_GetAFPin_8_15
-  * @param  GPIOx GPIO Port
-  * @param  Pin This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_GPIO_AF_0
-  *         @arg @ref LL_GPIO_AF_1
-  *         @arg @ref LL_GPIO_AF_2
-  *         @arg @ref LL_GPIO_AF_3
-  *         @arg @ref LL_GPIO_AF_4
-  *         @arg @ref LL_GPIO_AF_5
-  *         @arg @ref LL_GPIO_AF_6
-  *         @arg @ref LL_GPIO_AF_7
-  *         @arg @ref LL_GPIO_AF_8
-  *         @arg @ref LL_GPIO_AF_9
-  *         @arg @ref LL_GPIO_AF_10
-  *         @arg @ref LL_GPIO_AF_11
-  *         @arg @ref LL_GPIO_AF_12
-  *         @arg @ref LL_GPIO_AF_13
-  *         @arg @ref LL_GPIO_AF_14
-  *         @arg @ref LL_GPIO_AF_15
-  */
-__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin)
-{
-  return (uint32_t)(READ_BIT(GPIOx->AFR[1],
-                             (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFSEL8)) / ((((Pin >> 8U) *
-                                 (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)));
-}
-
-
-/**
-  * @brief  Lock configuration of several pins for a dedicated port.
-  * @note   When the lock sequence has been applied on a port bit, the
-  *         value of this port bit can no longer be modified until the
-  *         next reset.
-  * @note   Each lock bit freezes a specific configuration register
-  *         (control and alternate function registers).
-  * @rmtoll LCKR         LCKK          LL_GPIO_LockPin
-  * @param  GPIOx GPIO Port
-  * @param  PinMask This parameter can be a combination of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  *         @arg @ref LL_GPIO_PIN_ALL
-  * @retval None
-  */
-__STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
-{
-  __IO uint32_t temp;
-  WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
-  WRITE_REG(GPIOx->LCKR, PinMask);
-  WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
-  /* Read LCKK register. This read is mandatory to complete key lock sequence */
-  temp = READ_REG(GPIOx->LCKR);
-  (void) temp;
-}
-
-/**
-  * @brief  Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0.
-  * @rmtoll LCKR         LCKy          LL_GPIO_IsPinLocked
-  * @param  GPIOx GPIO Port
-  * @param  PinMask This parameter can be a combination of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  *         @arg @ref LL_GPIO_PIN_ALL
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask)
-{
-  return ((READ_BIT(GPIOx->LCKR, PinMask) == (PinMask)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Return 1 if one of the pin of a dedicated port is locked. else return 0.
-  * @rmtoll LCKR         LCKK          LL_GPIO_IsAnyPinLocked
-  * @param  GPIOx GPIO Port
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx)
-{
-  return ((READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK)) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_LL_EF_Data_Access Data Access
-  * @{
-  */
-
-/**
-  * @brief  Return full input data register value for a dedicated port.
-  * @rmtoll IDR          IDy           LL_GPIO_ReadInputPort
-  * @param  GPIOx GPIO Port
-  * @retval Input data register value of port
-  */
-__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx)
-{
-  return (uint32_t)(READ_REG(GPIOx->IDR));
-}
-
-/**
-  * @brief  Return if input data level for several pins of dedicated port is high or low.
-  * @rmtoll IDR          IDy           LL_GPIO_IsInputPinSet
-  * @param  GPIOx GPIO Port
-  * @param  PinMask This parameter can be a combination of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  *         @arg @ref LL_GPIO_PIN_ALL
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
-{
-  return ((READ_BIT(GPIOx->IDR, PinMask) == (PinMask)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Write output data register for the port.
-  * @rmtoll ODR          ODy           LL_GPIO_WriteOutputPort
-  * @param  GPIOx GPIO Port
-  * @param  PortValue Level value for each pin of the port
-  * @retval None
-  */
-__STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue)
-{
-  WRITE_REG(GPIOx->ODR, PortValue);
-}
-
-/**
-  * @brief  Return full output data register value for a dedicated port.
-  * @rmtoll ODR          ODy           LL_GPIO_ReadOutputPort
-  * @param  GPIOx GPIO Port
-  * @retval Output data register value of port
-  */
-__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx)
-{
-  return (uint32_t)(READ_REG(GPIOx->ODR));
-}
-
-/**
-  * @brief  Return if input data level for several pins of dedicated port is high or low.
-  * @rmtoll ODR          ODy           LL_GPIO_IsOutputPinSet
-  * @param  GPIOx GPIO Port
-  * @param  PinMask This parameter can be a combination of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  *         @arg @ref LL_GPIO_PIN_ALL
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
-{
-  return ((READ_BIT(GPIOx->ODR, PinMask) == (PinMask)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Set several pins to high level on dedicated gpio port.
-  * @rmtoll BSRR         BSy           LL_GPIO_SetOutputPin
-  * @param  GPIOx GPIO Port
-  * @param  PinMask This parameter can be a combination of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  *         @arg @ref LL_GPIO_PIN_ALL
-  * @retval None
-  */
-__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
-{
-  WRITE_REG(GPIOx->BSRR, PinMask);
-}
-
-/**
-  * @brief  Set several pins to low level on dedicated gpio port.
-  * @rmtoll BSRR         BRy           LL_GPIO_ResetOutputPin
-  * @param  GPIOx GPIO Port
-  * @param  PinMask This parameter can be a combination of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  *         @arg @ref LL_GPIO_PIN_ALL
-  * @retval None
-  */
-__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
-{
-  WRITE_REG(GPIOx->BSRR, PinMask << 16U);
-}
-
-/**
-  * @brief  Toggle data value for several pin of dedicated port.
-  * @rmtoll ODR          ODy           LL_GPIO_TogglePin
-  * @param  GPIOx GPIO Port
-  * @param  PinMask This parameter can be a combination of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  *         @arg @ref LL_GPIO_PIN_ALL
-  * @retval None
-  */
-__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
-{
-  uint32_t odr = READ_REG(GPIOx->ODR);
-  WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask));
-}
-
-/**
-  * @}
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions
-  * @{
-  */
-
-ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx);
-ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct);
-void        LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct);
-
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /*defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK) */
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32H7xx_LL_GPIO_H */
-
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_ll_gpio.h
+  * @author  MCD Application Team
+  * @brief   Header file of GPIO LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_LL_GPIO_H
+#define STM32H7xx_LL_GPIO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx.h"
+
+/** @addtogroup STM32H7xx_LL_Driver
+  * @{
+  */
+
+#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK)
+
+/** @defgroup GPIO_LL GPIO
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup GPIO_LL_Private_Macros GPIO Private Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures
+  * @{
+  */
+
+/**
+  * @brief LL GPIO Init Structure definition
+  */
+typedef struct
+{
+  uint32_t Pin;          /*!< Specifies the GPIO pins to be configured.
+                              This parameter can be any value of @ref GPIO_LL_EC_PIN */
+
+  uint32_t Mode;         /*!< Specifies the operating mode for the selected pins.
+                              This parameter can be a value of @ref GPIO_LL_EC_MODE.
+
+                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/
+
+  uint32_t Speed;        /*!< Specifies the speed for the selected pins.
+                              This parameter can be a value of @ref GPIO_LL_EC_SPEED.
+
+                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/
+
+  uint32_t OutputType;   /*!< Specifies the operating output type for the selected pins.
+                              This parameter can be a value of @ref GPIO_LL_EC_OUTPUT.
+
+                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/
+
+  uint32_t Pull;         /*!< Specifies the operating Pull-up/Pull down for the selected pins.
+                              This parameter can be a value of @ref GPIO_LL_EC_PULL.
+
+                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/
+
+  uint32_t Alternate;    /*!< Specifies the Peripheral to be connected to the selected pins.
+                              This parameter can be a value of @ref GPIO_LL_EC_AF.
+
+                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().*/
+} LL_GPIO_InitTypeDef;
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants
+  * @{
+  */
+
+/** @defgroup GPIO_LL_EC_PIN PIN
+  * @{
+  */
+#define LL_GPIO_PIN_0                      GPIO_BSRR_BS0 /*!< Select pin 0 */
+#define LL_GPIO_PIN_1                      GPIO_BSRR_BS1 /*!< Select pin 1 */
+#define LL_GPIO_PIN_2                      GPIO_BSRR_BS2 /*!< Select pin 2 */
+#define LL_GPIO_PIN_3                      GPIO_BSRR_BS3 /*!< Select pin 3 */
+#define LL_GPIO_PIN_4                      GPIO_BSRR_BS4 /*!< Select pin 4 */
+#define LL_GPIO_PIN_5                      GPIO_BSRR_BS5 /*!< Select pin 5 */
+#define LL_GPIO_PIN_6                      GPIO_BSRR_BS6 /*!< Select pin 6 */
+#define LL_GPIO_PIN_7                      GPIO_BSRR_BS7 /*!< Select pin 7 */
+#define LL_GPIO_PIN_8                      GPIO_BSRR_BS8 /*!< Select pin 8 */
+#define LL_GPIO_PIN_9                      GPIO_BSRR_BS9 /*!< Select pin 9 */
+#define LL_GPIO_PIN_10                     GPIO_BSRR_BS10 /*!< Select pin 10 */
+#define LL_GPIO_PIN_11                     GPIO_BSRR_BS11 /*!< Select pin 11 */
+#define LL_GPIO_PIN_12                     GPIO_BSRR_BS12 /*!< Select pin 12 */
+#define LL_GPIO_PIN_13                     GPIO_BSRR_BS13 /*!< Select pin 13 */
+#define LL_GPIO_PIN_14                     GPIO_BSRR_BS14 /*!< Select pin 14 */
+#define LL_GPIO_PIN_15                     GPIO_BSRR_BS15 /*!< Select pin 15 */
+#define LL_GPIO_PIN_ALL                    (GPIO_BSRR_BS0 | GPIO_BSRR_BS1  | GPIO_BSRR_BS2  | \
+                                           GPIO_BSRR_BS3  | GPIO_BSRR_BS4  | GPIO_BSRR_BS5  | \
+                                           GPIO_BSRR_BS6  | GPIO_BSRR_BS7  | GPIO_BSRR_BS8  | \
+                                           GPIO_BSRR_BS9  | GPIO_BSRR_BS10 | GPIO_BSRR_BS11 | \
+                                           GPIO_BSRR_BS12 | GPIO_BSRR_BS13 | GPIO_BSRR_BS14 | \
+                                           GPIO_BSRR_BS15) /*!< Select all pins */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_LL_EC_MODE Mode
+  * @{
+  */
+#define LL_GPIO_MODE_INPUT                 (0x00000000U) /*!< Select input mode */
+#define LL_GPIO_MODE_OUTPUT                GPIO_MODER_MODE0_0  /*!< Select output mode */
+#define LL_GPIO_MODE_ALTERNATE             GPIO_MODER_MODE0_1  /*!< Select alternate function mode */
+#define LL_GPIO_MODE_ANALOG                GPIO_MODER_MODE0    /*!< Select analog mode */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_LL_EC_OUTPUT Output Type
+  * @{
+  */
+#define LL_GPIO_OUTPUT_PUSHPULL            (0x00000000U) /*!< Select push-pull as output type */
+#define LL_GPIO_OUTPUT_OPENDRAIN           GPIO_OTYPER_OT0 /*!< Select open-drain as output type */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_LL_EC_SPEED Output Speed
+  * @{
+  */
+#define LL_GPIO_SPEED_FREQ_LOW             (0x00000000U) /*!< Select I/O low output speed    */
+#define LL_GPIO_SPEED_FREQ_MEDIUM          GPIO_OSPEEDR_OSPEED0_0 /*!< Select I/O medium output speed */
+#define LL_GPIO_SPEED_FREQ_HIGH            GPIO_OSPEEDR_OSPEED0_1 /*!< Select I/O fast output speed   */
+#define LL_GPIO_SPEED_FREQ_VERY_HIGH       GPIO_OSPEEDR_OSPEED0   /*!< Select I/O high output speed   */
+/**
+  * @}
+  */
+#define LL_GPIO_SPEED_LOW                  LL_GPIO_SPEED_FREQ_LOW
+#define LL_GPIO_SPEED_MEDIUM               LL_GPIO_SPEED_FREQ_MEDIUM
+#define LL_GPIO_SPEED_FAST                 LL_GPIO_SPEED_FREQ_HIGH
+#define LL_GPIO_SPEED_HIGH                 LL_GPIO_SPEED_FREQ_VERY_HIGH
+
+
+/** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down
+  * @{
+  */
+#define LL_GPIO_PULL_NO                    (0x00000000U) /*!< Select I/O no pull */
+#define LL_GPIO_PULL_UP                    GPIO_PUPDR_PUPD0_0 /*!< Select I/O pull up */
+#define LL_GPIO_PULL_DOWN                  GPIO_PUPDR_PUPD0_1 /*!< Select I/O pull down */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_LL_EC_AF Alternate Function
+  * @{
+  */
+#define LL_GPIO_AF_0                       (0x0000000U) /*!< Select alternate function 0 */
+#define LL_GPIO_AF_1                       (0x0000001U) /*!< Select alternate function 1 */
+#define LL_GPIO_AF_2                       (0x0000002U) /*!< Select alternate function 2 */
+#define LL_GPIO_AF_3                       (0x0000003U) /*!< Select alternate function 3 */
+#define LL_GPIO_AF_4                       (0x0000004U) /*!< Select alternate function 4 */
+#define LL_GPIO_AF_5                       (0x0000005U) /*!< Select alternate function 5 */
+#define LL_GPIO_AF_6                       (0x0000006U) /*!< Select alternate function 6 */
+#define LL_GPIO_AF_7                       (0x0000007U) /*!< Select alternate function 7 */
+#define LL_GPIO_AF_8                       (0x0000008U) /*!< Select alternate function 8 */
+#define LL_GPIO_AF_9                       (0x0000009U) /*!< Select alternate function 9 */
+#define LL_GPIO_AF_10                      (0x000000AU) /*!< Select alternate function 10 */
+#define LL_GPIO_AF_11                      (0x000000BU) /*!< Select alternate function 11 */
+#define LL_GPIO_AF_12                      (0x000000CU) /*!< Select alternate function 12 */
+#define LL_GPIO_AF_13                      (0x000000DU) /*!< Select alternate function 13 */
+#define LL_GPIO_AF_14                      (0x000000EU) /*!< Select alternate function 14 */
+#define LL_GPIO_AF_15                      (0x000000FU) /*!< Select alternate function 15 */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros
+  * @{
+  */
+
+/** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in GPIO register
+  * @param  __INSTANCE__ GPIO Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in GPIO register
+  * @param  __INSTANCE__ GPIO Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions
+  * @{
+  */
+
+/** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration
+  * @{
+  */
+
+/**
+  * @brief  Configure gpio mode for a dedicated pin on dedicated port.
+  * @note   I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @rmtoll MODER        MODEy         LL_GPIO_SetPinMode
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @param  Mode This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_MODE_INPUT
+  *         @arg @ref LL_GPIO_MODE_OUTPUT
+  *         @arg @ref LL_GPIO_MODE_ALTERNATE
+  *         @arg @ref LL_GPIO_MODE_ANALOG
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
+{
+  MODIFY_REG(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODE0), ((Pin * Pin) * Mode));
+}
+
+/**
+  * @brief  Return gpio mode for a dedicated pin on dedicated port.
+  * @note   I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @rmtoll MODER        MODEy         LL_GPIO_GetPinMode
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_GPIO_MODE_INPUT
+  *         @arg @ref LL_GPIO_MODE_OUTPUT
+  *         @arg @ref LL_GPIO_MODE_ALTERNATE
+  *         @arg @ref LL_GPIO_MODE_ANALOG
+  */
+__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+  return (uint32_t)(READ_BIT(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODE0)) / (Pin * Pin));
+}
+
+/**
+  * @brief  Configure gpio output type for several pins on dedicated port.
+  * @note   Output type as to be set when gpio pin is in output or
+  *         alternate modes. Possible type are Push-pull or Open-drain.
+  * @rmtoll OTYPER       OTy           LL_GPIO_SetPinOutputType
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @param  OutputType This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_OUTPUT_PUSHPULL
+  *         @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType)
+{
+  MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType));
+}
+
+/**
+  * @brief  Return gpio output type for several pins on dedicated port.
+  * @note   Output type as to be set when gpio pin is in output or
+  *         alternate modes. Possible type are Push-pull or Open-drain.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @rmtoll OTYPER       OTy           LL_GPIO_GetPinOutputType
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_GPIO_OUTPUT_PUSHPULL
+  *         @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
+  */
+__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+  return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) / Pin);
+}
+
+/**
+  * @brief  Configure gpio speed for a dedicated pin on dedicated port.
+  * @note   I/O speed can be Low, Medium, Fast or High speed.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @note   Refer to datasheet for frequency specifications and the power
+  *         supply and load conditions for each speed.
+  * @rmtoll OSPEEDR      OSPEEDy       LL_GPIO_SetPinSpeed
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @param  Speed This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_SPEED_FREQ_LOW
+  *         @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
+  *         @arg @ref LL_GPIO_SPEED_FREQ_HIGH
+  *         @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t  Speed)
+{
+  MODIFY_REG(GPIOx->OSPEEDR, ((Pin * Pin) * GPIO_OSPEEDR_OSPEED0), ((Pin * Pin) * Speed));
+}
+
+/**
+  * @brief  Return gpio speed for a dedicated pin on dedicated port.
+  * @note   I/O speed can be Low, Medium, Fast or High speed.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @note   Refer to datasheet for frequency specifications and the power
+  *         supply and load conditions for each speed.
+  * @rmtoll OSPEEDR      OSPEEDy       LL_GPIO_GetPinSpeed
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_GPIO_SPEED_FREQ_LOW
+  *         @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
+  *         @arg @ref LL_GPIO_SPEED_FREQ_HIGH
+  *         @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH
+  */
+__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+  return (uint32_t)(READ_BIT(GPIOx->OSPEEDR, ((Pin * Pin) * GPIO_OSPEEDR_OSPEED0)) / (Pin * Pin));
+}
+
+/**
+  * @brief  Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @rmtoll PUPDR        PUPDy         LL_GPIO_SetPinPull
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @param  Pull This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PULL_NO
+  *         @arg @ref LL_GPIO_PULL_UP
+  *         @arg @ref LL_GPIO_PULL_DOWN
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)
+{
+  MODIFY_REG(GPIOx->PUPDR, ((Pin * Pin) * GPIO_PUPDR_PUPD0), ((Pin * Pin) * Pull));
+}
+
+/**
+  * @brief  Return gpio pull-up or pull-down for a dedicated pin on a dedicated port
+  * @note   Warning: only one pin can be passed as parameter.
+  * @rmtoll PUPDR        PUPDy         LL_GPIO_GetPinPull
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_GPIO_PULL_NO
+  *         @arg @ref LL_GPIO_PULL_UP
+  *         @arg @ref LL_GPIO_PULL_DOWN
+  */
+__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+  return (uint32_t)(READ_BIT(GPIOx->PUPDR, ((Pin * Pin) * GPIO_PUPDR_PUPD0)) / (Pin * Pin));
+}
+
+/**
+  * @brief  Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
+  * @note   Possible values are from AF0 to AF15 depending on target.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @rmtoll AFRL         AFSELy        LL_GPIO_SetAFPin_0_7
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  * @param  Alternate This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_AF_0
+  *         @arg @ref LL_GPIO_AF_1
+  *         @arg @ref LL_GPIO_AF_2
+  *         @arg @ref LL_GPIO_AF_3
+  *         @arg @ref LL_GPIO_AF_4
+  *         @arg @ref LL_GPIO_AF_5
+  *         @arg @ref LL_GPIO_AF_6
+  *         @arg @ref LL_GPIO_AF_7
+  *         @arg @ref LL_GPIO_AF_8
+  *         @arg @ref LL_GPIO_AF_9
+  *         @arg @ref LL_GPIO_AF_10
+  *         @arg @ref LL_GPIO_AF_11
+  *         @arg @ref LL_GPIO_AF_12
+  *         @arg @ref LL_GPIO_AF_13
+  *         @arg @ref LL_GPIO_AF_14
+  *         @arg @ref LL_GPIO_AF_15
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
+{
+  MODIFY_REG(GPIOx->AFR[0], ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFSEL0),
+             ((((Pin * Pin) * Pin) * Pin) * Alternate));
+}
+
+/**
+  * @brief  Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
+  * @rmtoll AFRL         AFSELy        LL_GPIO_GetAFPin_0_7
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_GPIO_AF_0
+  *         @arg @ref LL_GPIO_AF_1
+  *         @arg @ref LL_GPIO_AF_2
+  *         @arg @ref LL_GPIO_AF_3
+  *         @arg @ref LL_GPIO_AF_4
+  *         @arg @ref LL_GPIO_AF_5
+  *         @arg @ref LL_GPIO_AF_6
+  *         @arg @ref LL_GPIO_AF_7
+  *         @arg @ref LL_GPIO_AF_8
+  *         @arg @ref LL_GPIO_AF_9
+  *         @arg @ref LL_GPIO_AF_10
+  *         @arg @ref LL_GPIO_AF_11
+  *         @arg @ref LL_GPIO_AF_12
+  *         @arg @ref LL_GPIO_AF_13
+  *         @arg @ref LL_GPIO_AF_14
+  *         @arg @ref LL_GPIO_AF_15
+  */
+__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+  return (uint32_t)(READ_BIT(GPIOx->AFR[0],
+                             ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFSEL0)) / (((Pin * Pin) * Pin) * Pin));
+}
+
+/**
+  * @brief  Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
+  * @note   Possible values are from AF0 to AF15 depending on target.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @rmtoll AFRH         AFSELy        LL_GPIO_SetAFPin_8_15
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @param  Alternate This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_AF_0
+  *         @arg @ref LL_GPIO_AF_1
+  *         @arg @ref LL_GPIO_AF_2
+  *         @arg @ref LL_GPIO_AF_3
+  *         @arg @ref LL_GPIO_AF_4
+  *         @arg @ref LL_GPIO_AF_5
+  *         @arg @ref LL_GPIO_AF_6
+  *         @arg @ref LL_GPIO_AF_7
+  *         @arg @ref LL_GPIO_AF_8
+  *         @arg @ref LL_GPIO_AF_9
+  *         @arg @ref LL_GPIO_AF_10
+  *         @arg @ref LL_GPIO_AF_11
+  *         @arg @ref LL_GPIO_AF_12
+  *         @arg @ref LL_GPIO_AF_13
+  *         @arg @ref LL_GPIO_AF_14
+  *         @arg @ref LL_GPIO_AF_15
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
+{
+  MODIFY_REG(GPIOx->AFR[1], (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFSEL8),
+             (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * Alternate));
+}
+
+/**
+  * @brief  Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
+  * @note   Possible values are from AF0 to AF15 depending on target.
+  * @rmtoll AFRH         AFSELy        LL_GPIO_GetAFPin_8_15
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_GPIO_AF_0
+  *         @arg @ref LL_GPIO_AF_1
+  *         @arg @ref LL_GPIO_AF_2
+  *         @arg @ref LL_GPIO_AF_3
+  *         @arg @ref LL_GPIO_AF_4
+  *         @arg @ref LL_GPIO_AF_5
+  *         @arg @ref LL_GPIO_AF_6
+  *         @arg @ref LL_GPIO_AF_7
+  *         @arg @ref LL_GPIO_AF_8
+  *         @arg @ref LL_GPIO_AF_9
+  *         @arg @ref LL_GPIO_AF_10
+  *         @arg @ref LL_GPIO_AF_11
+  *         @arg @ref LL_GPIO_AF_12
+  *         @arg @ref LL_GPIO_AF_13
+  *         @arg @ref LL_GPIO_AF_14
+  *         @arg @ref LL_GPIO_AF_15
+  */
+__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+  return (uint32_t)(READ_BIT(GPIOx->AFR[1],
+                             (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFSEL8)) / ((((Pin >> 8U) *
+                                 (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)));
+}
+
+
+/**
+  * @brief  Lock configuration of several pins for a dedicated port.
+  * @note   When the lock sequence has been applied on a port bit, the
+  *         value of this port bit can no longer be modified until the
+  *         next reset.
+  * @note   Each lock bit freezes a specific configuration register
+  *         (control and alternate function registers).
+  * @rmtoll LCKR         LCKK          LL_GPIO_LockPin
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  __IO uint32_t temp;
+  WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
+  WRITE_REG(GPIOx->LCKR, PinMask);
+  WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
+  /* Read LCKK register. This read is mandatory to complete key lock sequence */
+  temp = READ_REG(GPIOx->LCKR);
+  (void) temp;
+}
+
+/**
+  * @brief  Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0.
+  * @rmtoll LCKR         LCKy          LL_GPIO_IsPinLocked
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  return ((READ_BIT(GPIOx->LCKR, PinMask) == (PinMask)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Return 1 if one of the pin of a dedicated port is locked. else return 0.
+  * @rmtoll LCKR         LCKK          LL_GPIO_IsAnyPinLocked
+  * @param  GPIOx GPIO Port
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx)
+{
+  return ((READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_LL_EF_Data_Access Data Access
+  * @{
+  */
+
+/**
+  * @brief  Return full input data register value for a dedicated port.
+  * @rmtoll IDR          IDy           LL_GPIO_ReadInputPort
+  * @param  GPIOx GPIO Port
+  * @retval Input data register value of port
+  */
+__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx)
+{
+  return (uint32_t)(READ_REG(GPIOx->IDR));
+}
+
+/**
+  * @brief  Return if input data level for several pins of dedicated port is high or low.
+  * @rmtoll IDR          IDy           LL_GPIO_IsInputPinSet
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  return ((READ_BIT(GPIOx->IDR, PinMask) == (PinMask)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Write output data register for the port.
+  * @rmtoll ODR          ODy           LL_GPIO_WriteOutputPort
+  * @param  GPIOx GPIO Port
+  * @param  PortValue Level value for each pin of the port
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue)
+{
+  WRITE_REG(GPIOx->ODR, PortValue);
+}
+
+/**
+  * @brief  Return full output data register value for a dedicated port.
+  * @rmtoll ODR          ODy           LL_GPIO_ReadOutputPort
+  * @param  GPIOx GPIO Port
+  * @retval Output data register value of port
+  */
+__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx)
+{
+  return (uint32_t)(READ_REG(GPIOx->ODR));
+}
+
+/**
+  * @brief  Return if input data level for several pins of dedicated port is high or low.
+  * @rmtoll ODR          ODy           LL_GPIO_IsOutputPinSet
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  return ((READ_BIT(GPIOx->ODR, PinMask) == (PinMask)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set several pins to high level on dedicated gpio port.
+  * @rmtoll BSRR         BSy           LL_GPIO_SetOutputPin
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  WRITE_REG(GPIOx->BSRR, PinMask);
+}
+
+/**
+  * @brief  Set several pins to low level on dedicated gpio port.
+  * @rmtoll BSRR         BRy           LL_GPIO_ResetOutputPin
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  WRITE_REG(GPIOx->BSRR, PinMask << 16U);
+}
+
+/**
+  * @brief  Toggle data value for several pin of dedicated port.
+  * @rmtoll ODR          ODy           LL_GPIO_TogglePin
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  uint32_t odr = READ_REG(GPIOx->ODR);
+  WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask));
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+
+ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx);
+ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct);
+void        LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct);
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /*defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK) */
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_LL_GPIO_H */
+
diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_hsem.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_hsem.h
index cff88b5c..34525878 100644
--- a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_hsem.h
+++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_hsem.h
@@ -1,902 +1,902 @@
-/**
-  ******************************************************************************
-  * @file    stm32h7xx_ll_hsem.h
-  * @author  MCD Application Team
-  * @brief   Header file of HSEM LL module.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32H7xx_LL_HSEM_H
-#define STM32H7xx_LL_HSEM_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx.h"
-
-/** @addtogroup STM32H7xx_LL_Driver
-  * @{
-  */
-
-#if defined(HSEM)
-
-/** @defgroup HSEM_LL HSEM
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup HSEM_LL_Exported_Constants HSEM Exported Constants
-  * @{
-  */
-
-/** @defgroup HSEM_LL_EC_COREID COREID Defines
-  * @{
-  */
-#define LL_HSEM_COREID_NONE             0U
-#define LL_HSEM_COREID_CPU1             HSEM_CR_COREID_CPU1
-#if defined(DUAL_CORE)
-#define LL_HSEM_COREID_CPU2             HSEM_CR_COREID_CPU2
-#endif /* DUAL_CORE */
-#define LL_HSEM_COREID                  HSEM_CR_COREID_CURRENT
-/**
-  * @}
-  */
-
-
-/** @defgroup HSEM_LL_EC_GET_FLAG Get Flags Defines
-  * @brief    Flags defines which can be used with LL_HSEM_ReadReg function
-  * @{
-  */
-
-#define LL_HSEM_SEMAPHORE_0                HSEM_C1IER_ISE0
-#define LL_HSEM_SEMAPHORE_1                HSEM_C1IER_ISE1
-#define LL_HSEM_SEMAPHORE_2                HSEM_C1IER_ISE2
-#define LL_HSEM_SEMAPHORE_3                HSEM_C1IER_ISE3
-#define LL_HSEM_SEMAPHORE_4                HSEM_C1IER_ISE4
-#define LL_HSEM_SEMAPHORE_5                HSEM_C1IER_ISE5
-#define LL_HSEM_SEMAPHORE_6                HSEM_C1IER_ISE6
-#define LL_HSEM_SEMAPHORE_7                HSEM_C1IER_ISE7
-#define LL_HSEM_SEMAPHORE_8                HSEM_C1IER_ISE8
-#define LL_HSEM_SEMAPHORE_9                HSEM_C1IER_ISE9
-#define LL_HSEM_SEMAPHORE_10               HSEM_C1IER_ISE10
-#define LL_HSEM_SEMAPHORE_11               HSEM_C1IER_ISE11
-#define LL_HSEM_SEMAPHORE_12               HSEM_C1IER_ISE12
-#define LL_HSEM_SEMAPHORE_13               HSEM_C1IER_ISE13
-#define LL_HSEM_SEMAPHORE_14               HSEM_C1IER_ISE14
-#define LL_HSEM_SEMAPHORE_15               HSEM_C1IER_ISE15
-#if (HSEM_SEMID_MAX == 15)
-#define LL_HSEM_SEMAPHORE_ALL              0x0000FFFFU
-#else /* HSEM_SEMID_MAX == 31 */
-#define LL_HSEM_SEMAPHORE_16               HSEM_C1IER_ISE16
-#define LL_HSEM_SEMAPHORE_17               HSEM_C1IER_ISE17
-#define LL_HSEM_SEMAPHORE_18               HSEM_C1IER_ISE18
-#define LL_HSEM_SEMAPHORE_19               HSEM_C1IER_ISE19
-#define LL_HSEM_SEMAPHORE_20               HSEM_C1IER_ISE20
-#define LL_HSEM_SEMAPHORE_21               HSEM_C1IER_ISE21
-#define LL_HSEM_SEMAPHORE_22               HSEM_C1IER_ISE22
-#define LL_HSEM_SEMAPHORE_23               HSEM_C1IER_ISE23
-#define LL_HSEM_SEMAPHORE_24               HSEM_C1IER_ISE24
-#define LL_HSEM_SEMAPHORE_25               HSEM_C1IER_ISE25
-#define LL_HSEM_SEMAPHORE_26               HSEM_C1IER_ISE26
-#define LL_HSEM_SEMAPHORE_27               HSEM_C1IER_ISE27
-#define LL_HSEM_SEMAPHORE_28               HSEM_C1IER_ISE28
-#define LL_HSEM_SEMAPHORE_29               HSEM_C1IER_ISE29
-#define LL_HSEM_SEMAPHORE_30               HSEM_C1IER_ISE30
-#define LL_HSEM_SEMAPHORE_31               HSEM_C1IER_ISE31
-#define LL_HSEM_SEMAPHORE_ALL              0xFFFFFFFFU
-#endif /* HSEM_SEMID_MAX == 15 */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup HSEM_LL_Exported_Macros HSEM Exported Macros
-  * @{
-  */
-
-/** @defgroup HSEM_LL_EM_WRITE_READ Common Write and read registers Macros
-  * @{
-  */
-
-/**
-  * @brief  Write a value in HSEM register
-  * @param  __INSTANCE__ HSEM Instance
-  * @param  __REG__ Register to be written
-  * @param  __VALUE__ Value to be written in the register
-  * @retval None
-  */
-#define LL_HSEM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
-  * @brief  Read a value in HSEM register
-  * @param  __INSTANCE__ HSEM Instance
-  * @param  __REG__ Register to be read
-  * @retval Register value
-  */
-#define LL_HSEM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup HSEM_LL_Exported_Functions HSEM Exported Functions
-  * @{
-  */
-
-/** @defgroup HSEM_LL_EF_Data_Management Data_Management
-  * @{
-  */
-
-
-/**
-  * @brief  Return 1 if the semaphore is locked, else return 0.
-  * @rmtoll R            LOCK          LL_HSEM_IsSemaphoreLocked
-  * @param  HSEMx HSEM Instance.
-  * @param  Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_HSEM_IsSemaphoreLocked(HSEM_TypeDef *HSEMx, uint32_t Semaphore)
-{
-  return ((READ_BIT(HSEMx->R[Semaphore], HSEM_R_LOCK) == (HSEM_R_LOCK_Msk)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get core id.
-  * @rmtoll R            COREID        LL_HSEM_GetCoreId
-  * @param  HSEMx HSEM Instance.
-  * @param  Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_HSEM_COREID_NONE
-  *         @arg @ref LL_HSEM_COREID_CPU1
-  *         @arg @ref LL_HSEM_COREID_CPU2
-  */
-__STATIC_INLINE uint32_t LL_HSEM_GetCoreId(HSEM_TypeDef *HSEMx, uint32_t Semaphore)
-{
-  return (uint32_t)(READ_BIT(HSEMx->R[Semaphore], HSEM_R_COREID_Msk));
-}
-
-/**
-  * @brief  Get process id.
-  * @rmtoll R            PROCID        LL_HSEM_GetProcessId
-  * @param  HSEMx HSEM Instance.
-  * @param  Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
-  * @retval Process number. Value between Min_Data=0 and Max_Data=255
-  */
-__STATIC_INLINE uint32_t LL_HSEM_GetProcessId(HSEM_TypeDef *HSEMx, uint32_t Semaphore)
-{
-  return (uint32_t)(READ_BIT(HSEMx->R[Semaphore], HSEM_R_PROCID_Msk));
-}
-
-/**
-  * @brief  Get the lock by writing in R register.
-  * @note The R register has to be read to determined if the lock is taken.
-  * @rmtoll R            LOCK          LL_HSEM_SetLock
-  * @rmtoll R            COREID        LL_HSEM_SetLock
-  * @rmtoll R            PROCID        LL_HSEM_SetLock
-  * @param  HSEMx HSEM Instance.
-  * @param  Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
-  * @param  process Process id. Value between Min_Data=0 and Max_Data=255
-  * @retval None
-  */
-__STATIC_INLINE void LL_HSEM_SetLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore, uint32_t process)
-{
-  WRITE_REG(HSEMx->R[Semaphore], (HSEM_R_LOCK | LL_HSEM_COREID | process));
-}
-
-/**
-  * @brief  Get the lock with 2-step lock.
-  * @rmtoll R            LOCK          LL_HSEM_2StepLock
-  * @rmtoll R            COREID        LL_HSEM_2StepLock
-  * @rmtoll R            PROCID        LL_HSEM_2StepLock
-  * @param  HSEMx HSEM Instance.
-  * @param  Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
-  * @param  process Process id. Value between Min_Data=0 and Max_Data=255
-  * @retval 1 lock fail, 0 lock successful or already locked by same process and core
-  */
-__STATIC_INLINE uint32_t LL_HSEM_2StepLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore, uint32_t process)
-{
-  WRITE_REG(HSEMx->R[Semaphore], (HSEM_R_LOCK | LL_HSEM_COREID | process));
-  return ((HSEMx->R[Semaphore] != (HSEM_R_LOCK | LL_HSEM_COREID | process)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get the lock with 1-step lock.
-  * @rmtoll RLR          LOCK          LL_HSEM_1StepLock
-  * @rmtoll RLR          COREID        LL_HSEM_1StepLock
-  * @rmtoll RLR          PROCID        LL_HSEM_1StepLock
-  * @param  HSEMx HSEM Instance.
-  * @param  Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
-  * @retval 1 lock fail, 0 lock successful or already locked by same core
-  */
-__STATIC_INLINE uint32_t LL_HSEM_1StepLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore)
-{
-  return ((HSEMx->RLR[Semaphore] != (HSEM_RLR_LOCK | LL_HSEM_COREID)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Release the lock of the semaphore.
-  * @note In case of LL_HSEM_1StepLock usage to lock a semaphore, the process is 0.
-  * @rmtoll R            LOCK          LL_HSEM_ReleaseLock
-  * @param  HSEMx HSEM Instance.
-  * @param  Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
-  * @param  process Process number. Value between Min_Data=0 and Max_Data=255
-  * @retval None
-  */
-__STATIC_INLINE void LL_HSEM_ReleaseLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore, uint32_t process)
-{
-  WRITE_REG(HSEMx->R[Semaphore], (LL_HSEM_COREID | process));
-}
-
-/**
-  * @brief  Get the lock status of the semaphore.
-  * @rmtoll R            LOCK          LL_HSEM_GetStatus
-  * @param  HSEMx HSEM Instance.
-  * @param  Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
-  * @retval 0 semaphore is free, 1 semaphore is locked  */
-__STATIC_INLINE uint32_t LL_HSEM_GetStatus(HSEM_TypeDef *HSEMx, uint32_t Semaphore)
-{
-  return ((HSEMx->R[Semaphore] != 0U) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Set the key.
-  * @rmtoll KEYR         KEY           LL_HSEM_SetKey
-  * @param  HSEMx HSEM Instance.
-  * @param  key Key value.
-  * @retval None
-  */
-__STATIC_INLINE void LL_HSEM_SetKey(HSEM_TypeDef *HSEMx, uint32_t key)
-{
-  WRITE_REG(HSEMx->KEYR, key << HSEM_KEYR_KEY_Pos);
-}
-
-/**
-  * @brief  Get the key.
-  * @rmtoll KEYR         KEY           LL_HSEM_GetKey
-  * @param  HSEMx HSEM Instance.
-  * @retval key to unlock all semaphore from the same core
-  */
-__STATIC_INLINE uint32_t LL_HSEM_GetKey(HSEM_TypeDef *HSEMx)
-{
-  return (uint32_t)(READ_BIT(HSEMx->KEYR, HSEM_KEYR_KEY) >> HSEM_KEYR_KEY_Pos);
-}
-
-/**
-  * @brief  Release all semaphore with the same core id.
-  * @rmtoll CR           KEY           LL_HSEM_ResetAllLock
-  * @rmtoll CR           SEC           LL_HSEM_ResetAllLock
-  * @rmtoll CR           PRIV          LL_HSEM_ResetAllLock
-  * @param  HSEMx HSEM Instance.
-  * @param  key Key value.
-  * @param  core This parameter can be one of the following values:
-  *         @arg @ref LL_HSEM_COREID_CPU1
-  *         @arg @ref LL_HSEM_COREID_CPU2
-  * @retval None
-  */
-__STATIC_INLINE void LL_HSEM_ResetAllLock(HSEM_TypeDef *HSEMx, uint32_t key, uint32_t core)
-{
-  WRITE_REG(HSEMx->CR, (key << HSEM_CR_KEY_Pos) | core);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup HSEM_LL_EF_IT_Management IT_Management
-  * @{
-  */
-
-/**
-  * @brief  Enable interrupt.
-  * @rmtoll C1IER         ISEM          LL_HSEM_EnableIT_C1IER
-  * @param  HSEMx HSEM Instance.
-  * @param  SemaphoreMask This parameter can be a combination of the following values:
-  *         @arg @ref LL_HSEM_SEMAPHORE_0
-  *         @arg @ref LL_HSEM_SEMAPHORE_1
-  *         @arg @ref LL_HSEM_SEMAPHORE_2
-  *         @arg @ref LL_HSEM_SEMAPHORE_3
-  *         @arg @ref LL_HSEM_SEMAPHORE_4
-  *         @arg @ref LL_HSEM_SEMAPHORE_5
-  *         @arg @ref LL_HSEM_SEMAPHORE_6
-  *         @arg @ref LL_HSEM_SEMAPHORE_7
-  *         @arg @ref LL_HSEM_SEMAPHORE_8
-  *         @arg @ref LL_HSEM_SEMAPHORE_9
-  *         @arg @ref LL_HSEM_SEMAPHORE_10
-  *         @arg @ref LL_HSEM_SEMAPHORE_11
-  *         @arg @ref LL_HSEM_SEMAPHORE_12
-  *         @arg @ref LL_HSEM_SEMAPHORE_13
-  *         @arg @ref LL_HSEM_SEMAPHORE_14
-  *         @arg @ref LL_HSEM_SEMAPHORE_15
-  *         @arg @ref LL_HSEM_SEMAPHORE_16
-  *         @arg @ref LL_HSEM_SEMAPHORE_17
-  *         @arg @ref LL_HSEM_SEMAPHORE_18
-  *         @arg @ref LL_HSEM_SEMAPHORE_19
-  *         @arg @ref LL_HSEM_SEMAPHORE_20
-  *         @arg @ref LL_HSEM_SEMAPHORE_21
-  *         @arg @ref LL_HSEM_SEMAPHORE_22
-  *         @arg @ref LL_HSEM_SEMAPHORE_23
-  *         @arg @ref LL_HSEM_SEMAPHORE_24
-  *         @arg @ref LL_HSEM_SEMAPHORE_25
-  *         @arg @ref LL_HSEM_SEMAPHORE_26
-  *         @arg @ref LL_HSEM_SEMAPHORE_27
-  *         @arg @ref LL_HSEM_SEMAPHORE_28
-  *         @arg @ref LL_HSEM_SEMAPHORE_29
-  *         @arg @ref LL_HSEM_SEMAPHORE_30
-  *         @arg @ref LL_HSEM_SEMAPHORE_31
-  *         @arg @ref LL_HSEM_SEMAPHORE_ALL
-  * @note   Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31
-  *         depends on devices.
-  * @retval None
-  */
-__STATIC_INLINE void LL_HSEM_EnableIT_C1IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
-{
-  SET_BIT(HSEMx->C1IER, SemaphoreMask);
-}
-
-/**
-  * @brief  Disable interrupt.
-  * @rmtoll C1IER          ISEM          LL_HSEM_DisableIT_C1IER
-  * @param  HSEMx HSEM Instance.
-  * @param  SemaphoreMask This parameter can be a combination of the following values:
-  *         @arg @ref LL_HSEM_SEMAPHORE_0
-  *         @arg @ref LL_HSEM_SEMAPHORE_1
-  *         @arg @ref LL_HSEM_SEMAPHORE_2
-  *         @arg @ref LL_HSEM_SEMAPHORE_3
-  *         @arg @ref LL_HSEM_SEMAPHORE_4
-  *         @arg @ref LL_HSEM_SEMAPHORE_5
-  *         @arg @ref LL_HSEM_SEMAPHORE_6
-  *         @arg @ref LL_HSEM_SEMAPHORE_7
-  *         @arg @ref LL_HSEM_SEMAPHORE_8
-  *         @arg @ref LL_HSEM_SEMAPHORE_9
-  *         @arg @ref LL_HSEM_SEMAPHORE_10
-  *         @arg @ref LL_HSEM_SEMAPHORE_11
-  *         @arg @ref LL_HSEM_SEMAPHORE_12
-  *         @arg @ref LL_HSEM_SEMAPHORE_13
-  *         @arg @ref LL_HSEM_SEMAPHORE_14
-  *         @arg @ref LL_HSEM_SEMAPHORE_15
-  *         @arg @ref LL_HSEM_SEMAPHORE_16
-  *         @arg @ref LL_HSEM_SEMAPHORE_17
-  *         @arg @ref LL_HSEM_SEMAPHORE_18
-  *         @arg @ref LL_HSEM_SEMAPHORE_19
-  *         @arg @ref LL_HSEM_SEMAPHORE_20
-  *         @arg @ref LL_HSEM_SEMAPHORE_21
-  *         @arg @ref LL_HSEM_SEMAPHORE_22
-  *         @arg @ref LL_HSEM_SEMAPHORE_23
-  *         @arg @ref LL_HSEM_SEMAPHORE_24
-  *         @arg @ref LL_HSEM_SEMAPHORE_25
-  *         @arg @ref LL_HSEM_SEMAPHORE_26
-  *         @arg @ref LL_HSEM_SEMAPHORE_27
-  *         @arg @ref LL_HSEM_SEMAPHORE_28
-  *         @arg @ref LL_HSEM_SEMAPHORE_29
-  *         @arg @ref LL_HSEM_SEMAPHORE_30
-  *         @arg @ref LL_HSEM_SEMAPHORE_31
-  *         @arg @ref LL_HSEM_SEMAPHORE_ALL
-  * @note   Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31
-  *         depends on devices.
-  * @retval None
-  */
-__STATIC_INLINE void LL_HSEM_DisableIT_C1IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
-{
-  CLEAR_BIT(HSEMx->C1IER, SemaphoreMask);
-}
-
-/**
-  * @brief  Check if interrupt is enabled.
-  * @rmtoll C1IER          ISEM          LL_HSEM_IsEnabledIT_C1IER
-  * @param  HSEMx HSEM Instance.
-  * @param  SemaphoreMask This parameter can be a combination of the following values:
-  *         @arg @ref LL_HSEM_SEMAPHORE_0
-  *         @arg @ref LL_HSEM_SEMAPHORE_1
-  *         @arg @ref LL_HSEM_SEMAPHORE_2
-  *         @arg @ref LL_HSEM_SEMAPHORE_3
-  *         @arg @ref LL_HSEM_SEMAPHORE_4
-  *         @arg @ref LL_HSEM_SEMAPHORE_5
-  *         @arg @ref LL_HSEM_SEMAPHORE_6
-  *         @arg @ref LL_HSEM_SEMAPHORE_7
-  *         @arg @ref LL_HSEM_SEMAPHORE_8
-  *         @arg @ref LL_HSEM_SEMAPHORE_9
-  *         @arg @ref LL_HSEM_SEMAPHORE_10
-  *         @arg @ref LL_HSEM_SEMAPHORE_11
-  *         @arg @ref LL_HSEM_SEMAPHORE_12
-  *         @arg @ref LL_HSEM_SEMAPHORE_13
-  *         @arg @ref LL_HSEM_SEMAPHORE_14
-  *         @arg @ref LL_HSEM_SEMAPHORE_15
-  *         @arg @ref LL_HSEM_SEMAPHORE_16
-  *         @arg @ref LL_HSEM_SEMAPHORE_17
-  *         @arg @ref LL_HSEM_SEMAPHORE_18
-  *         @arg @ref LL_HSEM_SEMAPHORE_19
-  *         @arg @ref LL_HSEM_SEMAPHORE_20
-  *         @arg @ref LL_HSEM_SEMAPHORE_21
-  *         @arg @ref LL_HSEM_SEMAPHORE_22
-  *         @arg @ref LL_HSEM_SEMAPHORE_23
-  *         @arg @ref LL_HSEM_SEMAPHORE_24
-  *         @arg @ref LL_HSEM_SEMAPHORE_25
-  *         @arg @ref LL_HSEM_SEMAPHORE_26
-  *         @arg @ref LL_HSEM_SEMAPHORE_27
-  *         @arg @ref LL_HSEM_SEMAPHORE_28
-  *         @arg @ref LL_HSEM_SEMAPHORE_29
-  *         @arg @ref LL_HSEM_SEMAPHORE_30
-  *         @arg @ref LL_HSEM_SEMAPHORE_31
-  *         @arg @ref LL_HSEM_SEMAPHORE_ALL
-  * @note   Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31
-  *         depends on devices.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_HSEM_IsEnabledIT_C1IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
-{
-  return ((READ_BIT(HSEMx->C1IER, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
-}
-
-#if defined(DUAL_CORE)
-/**
-  * @brief  Enable interrupt.
-  * @rmtoll C2IER         ISEM          LL_HSEM_EnableIT_C2IER
-  * @param  HSEMx HSEM Instance.
-  * @param  SemaphoreMask This parameter can be a combination of the following values:
-  *         @arg @ref LL_HSEM_SEMAPHORE_0
-  *         @arg @ref LL_HSEM_SEMAPHORE_1
-  *         @arg @ref LL_HSEM_SEMAPHORE_2
-  *         @arg @ref LL_HSEM_SEMAPHORE_3
-  *         @arg @ref LL_HSEM_SEMAPHORE_4
-  *         @arg @ref LL_HSEM_SEMAPHORE_5
-  *         @arg @ref LL_HSEM_SEMAPHORE_6
-  *         @arg @ref LL_HSEM_SEMAPHORE_7
-  *         @arg @ref LL_HSEM_SEMAPHORE_8
-  *         @arg @ref LL_HSEM_SEMAPHORE_9
-  *         @arg @ref LL_HSEM_SEMAPHORE_10
-  *         @arg @ref LL_HSEM_SEMAPHORE_11
-  *         @arg @ref LL_HSEM_SEMAPHORE_12
-  *         @arg @ref LL_HSEM_SEMAPHORE_13
-  *         @arg @ref LL_HSEM_SEMAPHORE_14
-  *         @arg @ref LL_HSEM_SEMAPHORE_15
-  *         @arg @ref LL_HSEM_SEMAPHORE_16
-  *         @arg @ref LL_HSEM_SEMAPHORE_17
-  *         @arg @ref LL_HSEM_SEMAPHORE_18
-  *         @arg @ref LL_HSEM_SEMAPHORE_19
-  *         @arg @ref LL_HSEM_SEMAPHORE_20
-  *         @arg @ref LL_HSEM_SEMAPHORE_21
-  *         @arg @ref LL_HSEM_SEMAPHORE_22
-  *         @arg @ref LL_HSEM_SEMAPHORE_23
-  *         @arg @ref LL_HSEM_SEMAPHORE_24
-  *         @arg @ref LL_HSEM_SEMAPHORE_25
-  *         @arg @ref LL_HSEM_SEMAPHORE_26
-  *         @arg @ref LL_HSEM_SEMAPHORE_27
-  *         @arg @ref LL_HSEM_SEMAPHORE_28
-  *         @arg @ref LL_HSEM_SEMAPHORE_29
-  *         @arg @ref LL_HSEM_SEMAPHORE_30
-  *         @arg @ref LL_HSEM_SEMAPHORE_31
-  *         @arg @ref LL_HSEM_SEMAPHORE_ALL
-  * @retval None
-  */
-__STATIC_INLINE void LL_HSEM_EnableIT_C2IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
-{
-  SET_BIT(HSEMx->C2IER, SemaphoreMask);
-}
-
-/**
-  * @brief  Disable interrupt.
-  * @rmtoll C2IER          ISEM          LL_HSEM_DisableIT_C2IER
-  * @param  HSEMx HSEM Instance.
-  * @param  SemaphoreMask This parameter can be a combination of the following values:
-  *         @arg @ref LL_HSEM_SEMAPHORE_0
-  *         @arg @ref LL_HSEM_SEMAPHORE_1
-  *         @arg @ref LL_HSEM_SEMAPHORE_2
-  *         @arg @ref LL_HSEM_SEMAPHORE_3
-  *         @arg @ref LL_HSEM_SEMAPHORE_4
-  *         @arg @ref LL_HSEM_SEMAPHORE_5
-  *         @arg @ref LL_HSEM_SEMAPHORE_6
-  *         @arg @ref LL_HSEM_SEMAPHORE_7
-  *         @arg @ref LL_HSEM_SEMAPHORE_8
-  *         @arg @ref LL_HSEM_SEMAPHORE_9
-  *         @arg @ref LL_HSEM_SEMAPHORE_10
-  *         @arg @ref LL_HSEM_SEMAPHORE_11
-  *         @arg @ref LL_HSEM_SEMAPHORE_12
-  *         @arg @ref LL_HSEM_SEMAPHORE_13
-  *         @arg @ref LL_HSEM_SEMAPHORE_14
-  *         @arg @ref LL_HSEM_SEMAPHORE_15
-  *         @arg @ref LL_HSEM_SEMAPHORE_16
-  *         @arg @ref LL_HSEM_SEMAPHORE_17
-  *         @arg @ref LL_HSEM_SEMAPHORE_18
-  *         @arg @ref LL_HSEM_SEMAPHORE_19
-  *         @arg @ref LL_HSEM_SEMAPHORE_20
-  *         @arg @ref LL_HSEM_SEMAPHORE_21
-  *         @arg @ref LL_HSEM_SEMAPHORE_22
-  *         @arg @ref LL_HSEM_SEMAPHORE_23
-  *         @arg @ref LL_HSEM_SEMAPHORE_24
-  *         @arg @ref LL_HSEM_SEMAPHORE_25
-  *         @arg @ref LL_HSEM_SEMAPHORE_26
-  *         @arg @ref LL_HSEM_SEMAPHORE_27
-  *         @arg @ref LL_HSEM_SEMAPHORE_28
-  *         @arg @ref LL_HSEM_SEMAPHORE_29
-  *         @arg @ref LL_HSEM_SEMAPHORE_30
-  *         @arg @ref LL_HSEM_SEMAPHORE_31
-  *         @arg @ref LL_HSEM_SEMAPHORE_ALL
-  * @retval None
-  */
-__STATIC_INLINE void LL_HSEM_DisableIT_C2IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
-{
-  CLEAR_BIT(HSEMx->C2IER, SemaphoreMask);
-}
-
-/**
-  * @brief  Check if interrupt is enabled.
-  * @rmtoll C2IER          ISEM          LL_HSEM_IsEnabledIT_C2IER
-  * @param  HSEMx HSEM Instance.
-  * @param  SemaphoreMask This parameter can be a combination of the following values:
-  *         @arg @ref LL_HSEM_SEMAPHORE_0
-  *         @arg @ref LL_HSEM_SEMAPHORE_1
-  *         @arg @ref LL_HSEM_SEMAPHORE_2
-  *         @arg @ref LL_HSEM_SEMAPHORE_3
-  *         @arg @ref LL_HSEM_SEMAPHORE_4
-  *         @arg @ref LL_HSEM_SEMAPHORE_5
-  *         @arg @ref LL_HSEM_SEMAPHORE_6
-  *         @arg @ref LL_HSEM_SEMAPHORE_7
-  *         @arg @ref LL_HSEM_SEMAPHORE_8
-  *         @arg @ref LL_HSEM_SEMAPHORE_9
-  *         @arg @ref LL_HSEM_SEMAPHORE_10
-  *         @arg @ref LL_HSEM_SEMAPHORE_11
-  *         @arg @ref LL_HSEM_SEMAPHORE_12
-  *         @arg @ref LL_HSEM_SEMAPHORE_13
-  *         @arg @ref LL_HSEM_SEMAPHORE_14
-  *         @arg @ref LL_HSEM_SEMAPHORE_15
-  *         @arg @ref LL_HSEM_SEMAPHORE_16
-  *         @arg @ref LL_HSEM_SEMAPHORE_17
-  *         @arg @ref LL_HSEM_SEMAPHORE_18
-  *         @arg @ref LL_HSEM_SEMAPHORE_19
-  *         @arg @ref LL_HSEM_SEMAPHORE_20
-  *         @arg @ref LL_HSEM_SEMAPHORE_21
-  *         @arg @ref LL_HSEM_SEMAPHORE_22
-  *         @arg @ref LL_HSEM_SEMAPHORE_23
-  *         @arg @ref LL_HSEM_SEMAPHORE_24
-  *         @arg @ref LL_HSEM_SEMAPHORE_25
-  *         @arg @ref LL_HSEM_SEMAPHORE_26
-  *         @arg @ref LL_HSEM_SEMAPHORE_27
-  *         @arg @ref LL_HSEM_SEMAPHORE_28
-  *         @arg @ref LL_HSEM_SEMAPHORE_29
-  *         @arg @ref LL_HSEM_SEMAPHORE_30
-  *         @arg @ref LL_HSEM_SEMAPHORE_31
-  *         @arg @ref LL_HSEM_SEMAPHORE_ALL
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_HSEM_IsEnabledIT_C2IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
-{
-  return ((READ_BIT(HSEMx->C2IER, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
-}
-#endif /* DUAL_CORE */
-
-/**
-  * @}
-  */
-
-/** @defgroup HSEM_LL_EF_FLAG_Management FLAG_Management
-  * @{
-  */
-
-/**
-  * @brief  Clear interrupt status.
-  * @rmtoll C1ICR         ISEM          LL_HSEM_ClearFlag_C1ICR
-  * @param  HSEMx HSEM Instance.
-  * @param  SemaphoreMask This parameter can be a combination of the following values:
-  *         @arg @ref LL_HSEM_SEMAPHORE_0
-  *         @arg @ref LL_HSEM_SEMAPHORE_1
-  *         @arg @ref LL_HSEM_SEMAPHORE_2
-  *         @arg @ref LL_HSEM_SEMAPHORE_3
-  *         @arg @ref LL_HSEM_SEMAPHORE_4
-  *         @arg @ref LL_HSEM_SEMAPHORE_5
-  *         @arg @ref LL_HSEM_SEMAPHORE_6
-  *         @arg @ref LL_HSEM_SEMAPHORE_7
-  *         @arg @ref LL_HSEM_SEMAPHORE_8
-  *         @arg @ref LL_HSEM_SEMAPHORE_9
-  *         @arg @ref LL_HSEM_SEMAPHORE_10
-  *         @arg @ref LL_HSEM_SEMAPHORE_11
-  *         @arg @ref LL_HSEM_SEMAPHORE_12
-  *         @arg @ref LL_HSEM_SEMAPHORE_13
-  *         @arg @ref LL_HSEM_SEMAPHORE_14
-  *         @arg @ref LL_HSEM_SEMAPHORE_15
-  *         @arg @ref LL_HSEM_SEMAPHORE_16
-  *         @arg @ref LL_HSEM_SEMAPHORE_17
-  *         @arg @ref LL_HSEM_SEMAPHORE_18
-  *         @arg @ref LL_HSEM_SEMAPHORE_19
-  *         @arg @ref LL_HSEM_SEMAPHORE_20
-  *         @arg @ref LL_HSEM_SEMAPHORE_21
-  *         @arg @ref LL_HSEM_SEMAPHORE_22
-  *         @arg @ref LL_HSEM_SEMAPHORE_23
-  *         @arg @ref LL_HSEM_SEMAPHORE_24
-  *         @arg @ref LL_HSEM_SEMAPHORE_25
-  *         @arg @ref LL_HSEM_SEMAPHORE_26
-  *         @arg @ref LL_HSEM_SEMAPHORE_27
-  *         @arg @ref LL_HSEM_SEMAPHORE_28
-  *         @arg @ref LL_HSEM_SEMAPHORE_29
-  *         @arg @ref LL_HSEM_SEMAPHORE_30
-  *         @arg @ref LL_HSEM_SEMAPHORE_31
-  *         @arg @ref LL_HSEM_SEMAPHORE_ALL
-  * @note   Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31
-  *         depends on devices.
-  * @retval None
-  */
-__STATIC_INLINE void LL_HSEM_ClearFlag_C1ICR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
-{
-  WRITE_REG(HSEMx->C1ICR, SemaphoreMask);
-}
-
-/**
-  * @brief  Get interrupt status from ISR register.
-  * @rmtoll C1ISR         ISEM          LL_HSEM_IsActiveFlag_C1ISR
-  * @param  HSEMx HSEM Instance.
-  * @param  SemaphoreMask This parameter can be a combination of the following values:
-  *         @arg @ref LL_HSEM_SEMAPHORE_0
-  *         @arg @ref LL_HSEM_SEMAPHORE_1
-  *         @arg @ref LL_HSEM_SEMAPHORE_2
-  *         @arg @ref LL_HSEM_SEMAPHORE_3
-  *         @arg @ref LL_HSEM_SEMAPHORE_4
-  *         @arg @ref LL_HSEM_SEMAPHORE_5
-  *         @arg @ref LL_HSEM_SEMAPHORE_6
-  *         @arg @ref LL_HSEM_SEMAPHORE_7
-  *         @arg @ref LL_HSEM_SEMAPHORE_8
-  *         @arg @ref LL_HSEM_SEMAPHORE_9
-  *         @arg @ref LL_HSEM_SEMAPHORE_10
-  *         @arg @ref LL_HSEM_SEMAPHORE_11
-  *         @arg @ref LL_HSEM_SEMAPHORE_12
-  *         @arg @ref LL_HSEM_SEMAPHORE_13
-  *         @arg @ref LL_HSEM_SEMAPHORE_14
-  *         @arg @ref LL_HSEM_SEMAPHORE_15
-  *         @arg @ref LL_HSEM_SEMAPHORE_16
-  *         @arg @ref LL_HSEM_SEMAPHORE_17
-  *         @arg @ref LL_HSEM_SEMAPHORE_18
-  *         @arg @ref LL_HSEM_SEMAPHORE_19
-  *         @arg @ref LL_HSEM_SEMAPHORE_20
-  *         @arg @ref LL_HSEM_SEMAPHORE_21
-  *         @arg @ref LL_HSEM_SEMAPHORE_22
-  *         @arg @ref LL_HSEM_SEMAPHORE_23
-  *         @arg @ref LL_HSEM_SEMAPHORE_24
-  *         @arg @ref LL_HSEM_SEMAPHORE_25
-  *         @arg @ref LL_HSEM_SEMAPHORE_26
-  *         @arg @ref LL_HSEM_SEMAPHORE_27
-  *         @arg @ref LL_HSEM_SEMAPHORE_28
-  *         @arg @ref LL_HSEM_SEMAPHORE_29
-  *         @arg @ref LL_HSEM_SEMAPHORE_30
-  *         @arg @ref LL_HSEM_SEMAPHORE_31
-  *         @arg @ref LL_HSEM_SEMAPHORE_ALL
-  * @note   Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31
-  *         depends on devices.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C1ISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
-{
-  return ((READ_BIT(HSEMx->C1ISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get interrupt status from MISR register.
-  * @rmtoll C1MISR        ISEM          LL_HSEM_IsActiveFlag_C1MISR
-  * @param  HSEMx HSEM Instance.
-  * @param  SemaphoreMask This parameter can be a combination of the following values:
-  *         @arg @ref LL_HSEM_SEMAPHORE_0
-  *         @arg @ref LL_HSEM_SEMAPHORE_1
-  *         @arg @ref LL_HSEM_SEMAPHORE_2
-  *         @arg @ref LL_HSEM_SEMAPHORE_3
-  *         @arg @ref LL_HSEM_SEMAPHORE_4
-  *         @arg @ref LL_HSEM_SEMAPHORE_5
-  *         @arg @ref LL_HSEM_SEMAPHORE_6
-  *         @arg @ref LL_HSEM_SEMAPHORE_7
-  *         @arg @ref LL_HSEM_SEMAPHORE_8
-  *         @arg @ref LL_HSEM_SEMAPHORE_9
-  *         @arg @ref LL_HSEM_SEMAPHORE_10
-  *         @arg @ref LL_HSEM_SEMAPHORE_11
-  *         @arg @ref LL_HSEM_SEMAPHORE_12
-  *         @arg @ref LL_HSEM_SEMAPHORE_13
-  *         @arg @ref LL_HSEM_SEMAPHORE_14
-  *         @arg @ref LL_HSEM_SEMAPHORE_15
-  *         @arg @ref LL_HSEM_SEMAPHORE_16
-  *         @arg @ref LL_HSEM_SEMAPHORE_17
-  *         @arg @ref LL_HSEM_SEMAPHORE_18
-  *         @arg @ref LL_HSEM_SEMAPHORE_19
-  *         @arg @ref LL_HSEM_SEMAPHORE_20
-  *         @arg @ref LL_HSEM_SEMAPHORE_21
-  *         @arg @ref LL_HSEM_SEMAPHORE_22
-  *         @arg @ref LL_HSEM_SEMAPHORE_23
-  *         @arg @ref LL_HSEM_SEMAPHORE_24
-  *         @arg @ref LL_HSEM_SEMAPHORE_25
-  *         @arg @ref LL_HSEM_SEMAPHORE_26
-  *         @arg @ref LL_HSEM_SEMAPHORE_27
-  *         @arg @ref LL_HSEM_SEMAPHORE_28
-  *         @arg @ref LL_HSEM_SEMAPHORE_29
-  *         @arg @ref LL_HSEM_SEMAPHORE_30
-  *         @arg @ref LL_HSEM_SEMAPHORE_31
-  *         @arg @ref LL_HSEM_SEMAPHORE_ALL
-  * @note   Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31
-  *         depends on devices.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C1MISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
-{
-  return ((READ_BIT(HSEMx->C1MISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
-}
-
-#if defined(DUAL_CORE)
-/**
-  * @brief  Clear interrupt status.
-  * @rmtoll C2ICR         ISEM          LL_HSEM_ClearFlag_C2ICR
-  * @param  HSEMx HSEM Instance.
-  * @param  SemaphoreMask This parameter can be a combination of the following values:
-  *         @arg @ref LL_HSEM_SEMAPHORE_0
-  *         @arg @ref LL_HSEM_SEMAPHORE_1
-  *         @arg @ref LL_HSEM_SEMAPHORE_2
-  *         @arg @ref LL_HSEM_SEMAPHORE_3
-  *         @arg @ref LL_HSEM_SEMAPHORE_4
-  *         @arg @ref LL_HSEM_SEMAPHORE_5
-  *         @arg @ref LL_HSEM_SEMAPHORE_6
-  *         @arg @ref LL_HSEM_SEMAPHORE_7
-  *         @arg @ref LL_HSEM_SEMAPHORE_8
-  *         @arg @ref LL_HSEM_SEMAPHORE_9
-  *         @arg @ref LL_HSEM_SEMAPHORE_10
-  *         @arg @ref LL_HSEM_SEMAPHORE_11
-  *         @arg @ref LL_HSEM_SEMAPHORE_12
-  *         @arg @ref LL_HSEM_SEMAPHORE_13
-  *         @arg @ref LL_HSEM_SEMAPHORE_14
-  *         @arg @ref LL_HSEM_SEMAPHORE_15
-  *         @arg @ref LL_HSEM_SEMAPHORE_16
-  *         @arg @ref LL_HSEM_SEMAPHORE_17
-  *         @arg @ref LL_HSEM_SEMAPHORE_18
-  *         @arg @ref LL_HSEM_SEMAPHORE_19
-  *         @arg @ref LL_HSEM_SEMAPHORE_20
-  *         @arg @ref LL_HSEM_SEMAPHORE_21
-  *         @arg @ref LL_HSEM_SEMAPHORE_22
-  *         @arg @ref LL_HSEM_SEMAPHORE_23
-  *         @arg @ref LL_HSEM_SEMAPHORE_24
-  *         @arg @ref LL_HSEM_SEMAPHORE_25
-  *         @arg @ref LL_HSEM_SEMAPHORE_26
-  *         @arg @ref LL_HSEM_SEMAPHORE_27
-  *         @arg @ref LL_HSEM_SEMAPHORE_28
-  *         @arg @ref LL_HSEM_SEMAPHORE_29
-  *         @arg @ref LL_HSEM_SEMAPHORE_30
-  *         @arg @ref LL_HSEM_SEMAPHORE_31
-  *         @arg @ref LL_HSEM_SEMAPHORE_ALL
-  * @retval None
-  */
-__STATIC_INLINE void LL_HSEM_ClearFlag_C2ICR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
-{
-  WRITE_REG(HSEMx->C2ICR, SemaphoreMask);
-}
-
-/**
-  * @brief  Get interrupt status from ISR register.
-  * @rmtoll C2ISR         ISEM          LL_HSEM_IsActiveFlag_C2ISR
-  * @param  HSEMx HSEM Instance.
-  * @param  SemaphoreMask This parameter can be a combination of the following values:
-  *         @arg @ref LL_HSEM_SEMAPHORE_0
-  *         @arg @ref LL_HSEM_SEMAPHORE_1
-  *         @arg @ref LL_HSEM_SEMAPHORE_2
-  *         @arg @ref LL_HSEM_SEMAPHORE_3
-  *         @arg @ref LL_HSEM_SEMAPHORE_4
-  *         @arg @ref LL_HSEM_SEMAPHORE_5
-  *         @arg @ref LL_HSEM_SEMAPHORE_6
-  *         @arg @ref LL_HSEM_SEMAPHORE_7
-  *         @arg @ref LL_HSEM_SEMAPHORE_8
-  *         @arg @ref LL_HSEM_SEMAPHORE_9
-  *         @arg @ref LL_HSEM_SEMAPHORE_10
-  *         @arg @ref LL_HSEM_SEMAPHORE_11
-  *         @arg @ref LL_HSEM_SEMAPHORE_12
-  *         @arg @ref LL_HSEM_SEMAPHORE_13
-  *         @arg @ref LL_HSEM_SEMAPHORE_14
-  *         @arg @ref LL_HSEM_SEMAPHORE_15
-  *         @arg @ref LL_HSEM_SEMAPHORE_16
-  *         @arg @ref LL_HSEM_SEMAPHORE_17
-  *         @arg @ref LL_HSEM_SEMAPHORE_18
-  *         @arg @ref LL_HSEM_SEMAPHORE_19
-  *         @arg @ref LL_HSEM_SEMAPHORE_20
-  *         @arg @ref LL_HSEM_SEMAPHORE_21
-  *         @arg @ref LL_HSEM_SEMAPHORE_22
-  *         @arg @ref LL_HSEM_SEMAPHORE_23
-  *         @arg @ref LL_HSEM_SEMAPHORE_24
-  *         @arg @ref LL_HSEM_SEMAPHORE_25
-  *         @arg @ref LL_HSEM_SEMAPHORE_26
-  *         @arg @ref LL_HSEM_SEMAPHORE_27
-  *         @arg @ref LL_HSEM_SEMAPHORE_28
-  *         @arg @ref LL_HSEM_SEMAPHORE_29
-  *         @arg @ref LL_HSEM_SEMAPHORE_30
-  *         @arg @ref LL_HSEM_SEMAPHORE_31
-  *         @arg @ref LL_HSEM_SEMAPHORE_ALL
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C2ISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
-{
-  return ((READ_BIT(HSEMx->C2ISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get interrupt status from MISR register.
-  * @rmtoll C2MISR        ISEM          LL_HSEM_IsActiveFlag_C2MISR
-  * @param  HSEMx HSEM Instance.
-  * @param  SemaphoreMask This parameter can be a combination of the following values:
-  *         @arg @ref LL_HSEM_SEMAPHORE_0
-  *         @arg @ref LL_HSEM_SEMAPHORE_1
-  *         @arg @ref LL_HSEM_SEMAPHORE_2
-  *         @arg @ref LL_HSEM_SEMAPHORE_3
-  *         @arg @ref LL_HSEM_SEMAPHORE_4
-  *         @arg @ref LL_HSEM_SEMAPHORE_5
-  *         @arg @ref LL_HSEM_SEMAPHORE_6
-  *         @arg @ref LL_HSEM_SEMAPHORE_7
-  *         @arg @ref LL_HSEM_SEMAPHORE_8
-  *         @arg @ref LL_HSEM_SEMAPHORE_9
-  *         @arg @ref LL_HSEM_SEMAPHORE_10
-  *         @arg @ref LL_HSEM_SEMAPHORE_11
-  *         @arg @ref LL_HSEM_SEMAPHORE_12
-  *         @arg @ref LL_HSEM_SEMAPHORE_13
-  *         @arg @ref LL_HSEM_SEMAPHORE_14
-  *         @arg @ref LL_HSEM_SEMAPHORE_15
-  *         @arg @ref LL_HSEM_SEMAPHORE_16
-  *         @arg @ref LL_HSEM_SEMAPHORE_17
-  *         @arg @ref LL_HSEM_SEMAPHORE_18
-  *         @arg @ref LL_HSEM_SEMAPHORE_19
-  *         @arg @ref LL_HSEM_SEMAPHORE_20
-  *         @arg @ref LL_HSEM_SEMAPHORE_21
-  *         @arg @ref LL_HSEM_SEMAPHORE_22
-  *         @arg @ref LL_HSEM_SEMAPHORE_23
-  *         @arg @ref LL_HSEM_SEMAPHORE_24
-  *         @arg @ref LL_HSEM_SEMAPHORE_25
-  *         @arg @ref LL_HSEM_SEMAPHORE_26
-  *         @arg @ref LL_HSEM_SEMAPHORE_27
-  *         @arg @ref LL_HSEM_SEMAPHORE_28
-  *         @arg @ref LL_HSEM_SEMAPHORE_29
-  *         @arg @ref LL_HSEM_SEMAPHORE_30
-  *         @arg @ref LL_HSEM_SEMAPHORE_31
-  *         @arg @ref LL_HSEM_SEMAPHORE_ALL
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C2MISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
-{
-  return ((READ_BIT(HSEMx->C2MISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
-}
-#endif /* DUAL_CORE */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* defined(HSEM) */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32H7xx_LL_HSEM_H */
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_ll_hsem.h
+  * @author  MCD Application Team
+  * @brief   Header file of HSEM LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_LL_HSEM_H
+#define STM32H7xx_LL_HSEM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx.h"
+
+/** @addtogroup STM32H7xx_LL_Driver
+  * @{
+  */
+
+#if defined(HSEM)
+
+/** @defgroup HSEM_LL HSEM
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup HSEM_LL_Exported_Constants HSEM Exported Constants
+  * @{
+  */
+
+/** @defgroup HSEM_LL_EC_COREID COREID Defines
+  * @{
+  */
+#define LL_HSEM_COREID_NONE             0U
+#define LL_HSEM_COREID_CPU1             HSEM_CR_COREID_CPU1
+#if defined(DUAL_CORE)
+#define LL_HSEM_COREID_CPU2             HSEM_CR_COREID_CPU2
+#endif /* DUAL_CORE */
+#define LL_HSEM_COREID                  HSEM_CR_COREID_CURRENT
+/**
+  * @}
+  */
+
+
+/** @defgroup HSEM_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_HSEM_ReadReg function
+  * @{
+  */
+
+#define LL_HSEM_SEMAPHORE_0                HSEM_C1IER_ISE0
+#define LL_HSEM_SEMAPHORE_1                HSEM_C1IER_ISE1
+#define LL_HSEM_SEMAPHORE_2                HSEM_C1IER_ISE2
+#define LL_HSEM_SEMAPHORE_3                HSEM_C1IER_ISE3
+#define LL_HSEM_SEMAPHORE_4                HSEM_C1IER_ISE4
+#define LL_HSEM_SEMAPHORE_5                HSEM_C1IER_ISE5
+#define LL_HSEM_SEMAPHORE_6                HSEM_C1IER_ISE6
+#define LL_HSEM_SEMAPHORE_7                HSEM_C1IER_ISE7
+#define LL_HSEM_SEMAPHORE_8                HSEM_C1IER_ISE8
+#define LL_HSEM_SEMAPHORE_9                HSEM_C1IER_ISE9
+#define LL_HSEM_SEMAPHORE_10               HSEM_C1IER_ISE10
+#define LL_HSEM_SEMAPHORE_11               HSEM_C1IER_ISE11
+#define LL_HSEM_SEMAPHORE_12               HSEM_C1IER_ISE12
+#define LL_HSEM_SEMAPHORE_13               HSEM_C1IER_ISE13
+#define LL_HSEM_SEMAPHORE_14               HSEM_C1IER_ISE14
+#define LL_HSEM_SEMAPHORE_15               HSEM_C1IER_ISE15
+#if (HSEM_SEMID_MAX == 15)
+#define LL_HSEM_SEMAPHORE_ALL              0x0000FFFFU
+#else /* HSEM_SEMID_MAX == 31 */
+#define LL_HSEM_SEMAPHORE_16               HSEM_C1IER_ISE16
+#define LL_HSEM_SEMAPHORE_17               HSEM_C1IER_ISE17
+#define LL_HSEM_SEMAPHORE_18               HSEM_C1IER_ISE18
+#define LL_HSEM_SEMAPHORE_19               HSEM_C1IER_ISE19
+#define LL_HSEM_SEMAPHORE_20               HSEM_C1IER_ISE20
+#define LL_HSEM_SEMAPHORE_21               HSEM_C1IER_ISE21
+#define LL_HSEM_SEMAPHORE_22               HSEM_C1IER_ISE22
+#define LL_HSEM_SEMAPHORE_23               HSEM_C1IER_ISE23
+#define LL_HSEM_SEMAPHORE_24               HSEM_C1IER_ISE24
+#define LL_HSEM_SEMAPHORE_25               HSEM_C1IER_ISE25
+#define LL_HSEM_SEMAPHORE_26               HSEM_C1IER_ISE26
+#define LL_HSEM_SEMAPHORE_27               HSEM_C1IER_ISE27
+#define LL_HSEM_SEMAPHORE_28               HSEM_C1IER_ISE28
+#define LL_HSEM_SEMAPHORE_29               HSEM_C1IER_ISE29
+#define LL_HSEM_SEMAPHORE_30               HSEM_C1IER_ISE30
+#define LL_HSEM_SEMAPHORE_31               HSEM_C1IER_ISE31
+#define LL_HSEM_SEMAPHORE_ALL              0xFFFFFFFFU
+#endif /* HSEM_SEMID_MAX == 15 */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup HSEM_LL_Exported_Macros HSEM Exported Macros
+  * @{
+  */
+
+/** @defgroup HSEM_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in HSEM register
+  * @param  __INSTANCE__ HSEM Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_HSEM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in HSEM register
+  * @param  __INSTANCE__ HSEM Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_HSEM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup HSEM_LL_Exported_Functions HSEM Exported Functions
+  * @{
+  */
+
+/** @defgroup HSEM_LL_EF_Data_Management Data_Management
+  * @{
+  */
+
+
+/**
+  * @brief  Return 1 if the semaphore is locked, else return 0.
+  * @rmtoll R            LOCK          LL_HSEM_IsSemaphoreLocked
+  * @param  HSEMx HSEM Instance.
+  * @param  Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HSEM_IsSemaphoreLocked(HSEM_TypeDef *HSEMx, uint32_t Semaphore)
+{
+  return ((READ_BIT(HSEMx->R[Semaphore], HSEM_R_LOCK) == (HSEM_R_LOCK_Msk)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get core id.
+  * @rmtoll R            COREID        LL_HSEM_GetCoreId
+  * @param  HSEMx HSEM Instance.
+  * @param  Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_HSEM_COREID_NONE
+  *         @arg @ref LL_HSEM_COREID_CPU1
+  *         @arg @ref LL_HSEM_COREID_CPU2
+  */
+__STATIC_INLINE uint32_t LL_HSEM_GetCoreId(HSEM_TypeDef *HSEMx, uint32_t Semaphore)
+{
+  return (uint32_t)(READ_BIT(HSEMx->R[Semaphore], HSEM_R_COREID_Msk));
+}
+
+/**
+  * @brief  Get process id.
+  * @rmtoll R            PROCID        LL_HSEM_GetProcessId
+  * @param  HSEMx HSEM Instance.
+  * @param  Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
+  * @retval Process number. Value between Min_Data=0 and Max_Data=255
+  */
+__STATIC_INLINE uint32_t LL_HSEM_GetProcessId(HSEM_TypeDef *HSEMx, uint32_t Semaphore)
+{
+  return (uint32_t)(READ_BIT(HSEMx->R[Semaphore], HSEM_R_PROCID_Msk));
+}
+
+/**
+  * @brief  Get the lock by writing in R register.
+  * @note The R register has to be read to determined if the lock is taken.
+  * @rmtoll R            LOCK          LL_HSEM_SetLock
+  * @rmtoll R            COREID        LL_HSEM_SetLock
+  * @rmtoll R            PROCID        LL_HSEM_SetLock
+  * @param  HSEMx HSEM Instance.
+  * @param  Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
+  * @param  process Process id. Value between Min_Data=0 and Max_Data=255
+  * @retval None
+  */
+__STATIC_INLINE void LL_HSEM_SetLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore, uint32_t process)
+{
+  WRITE_REG(HSEMx->R[Semaphore], (HSEM_R_LOCK | LL_HSEM_COREID | process));
+}
+
+/**
+  * @brief  Get the lock with 2-step lock.
+  * @rmtoll R            LOCK          LL_HSEM_2StepLock
+  * @rmtoll R            COREID        LL_HSEM_2StepLock
+  * @rmtoll R            PROCID        LL_HSEM_2StepLock
+  * @param  HSEMx HSEM Instance.
+  * @param  Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
+  * @param  process Process id. Value between Min_Data=0 and Max_Data=255
+  * @retval 1 lock fail, 0 lock successful or already locked by same process and core
+  */
+__STATIC_INLINE uint32_t LL_HSEM_2StepLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore, uint32_t process)
+{
+  WRITE_REG(HSEMx->R[Semaphore], (HSEM_R_LOCK | LL_HSEM_COREID | process));
+  return ((HSEMx->R[Semaphore] != (HSEM_R_LOCK | LL_HSEM_COREID | process)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get the lock with 1-step lock.
+  * @rmtoll RLR          LOCK          LL_HSEM_1StepLock
+  * @rmtoll RLR          COREID        LL_HSEM_1StepLock
+  * @rmtoll RLR          PROCID        LL_HSEM_1StepLock
+  * @param  HSEMx HSEM Instance.
+  * @param  Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
+  * @retval 1 lock fail, 0 lock successful or already locked by same core
+  */
+__STATIC_INLINE uint32_t LL_HSEM_1StepLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore)
+{
+  return ((HSEMx->RLR[Semaphore] != (HSEM_RLR_LOCK | LL_HSEM_COREID)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Release the lock of the semaphore.
+  * @note In case of LL_HSEM_1StepLock usage to lock a semaphore, the process is 0.
+  * @rmtoll R            LOCK          LL_HSEM_ReleaseLock
+  * @param  HSEMx HSEM Instance.
+  * @param  Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
+  * @param  process Process number. Value between Min_Data=0 and Max_Data=255
+  * @retval None
+  */
+__STATIC_INLINE void LL_HSEM_ReleaseLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore, uint32_t process)
+{
+  WRITE_REG(HSEMx->R[Semaphore], (LL_HSEM_COREID | process));
+}
+
+/**
+  * @brief  Get the lock status of the semaphore.
+  * @rmtoll R            LOCK          LL_HSEM_GetStatus
+  * @param  HSEMx HSEM Instance.
+  * @param  Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
+  * @retval 0 semaphore is free, 1 semaphore is locked  */
+__STATIC_INLINE uint32_t LL_HSEM_GetStatus(HSEM_TypeDef *HSEMx, uint32_t Semaphore)
+{
+  return ((HSEMx->R[Semaphore] != 0U) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the key.
+  * @rmtoll KEYR         KEY           LL_HSEM_SetKey
+  * @param  HSEMx HSEM Instance.
+  * @param  key Key value.
+  * @retval None
+  */
+__STATIC_INLINE void LL_HSEM_SetKey(HSEM_TypeDef *HSEMx, uint32_t key)
+{
+  WRITE_REG(HSEMx->KEYR, key << HSEM_KEYR_KEY_Pos);
+}
+
+/**
+  * @brief  Get the key.
+  * @rmtoll KEYR         KEY           LL_HSEM_GetKey
+  * @param  HSEMx HSEM Instance.
+  * @retval key to unlock all semaphore from the same core
+  */
+__STATIC_INLINE uint32_t LL_HSEM_GetKey(HSEM_TypeDef *HSEMx)
+{
+  return (uint32_t)(READ_BIT(HSEMx->KEYR, HSEM_KEYR_KEY) >> HSEM_KEYR_KEY_Pos);
+}
+
+/**
+  * @brief  Release all semaphore with the same core id.
+  * @rmtoll CR           KEY           LL_HSEM_ResetAllLock
+  * @rmtoll CR           SEC           LL_HSEM_ResetAllLock
+  * @rmtoll CR           PRIV          LL_HSEM_ResetAllLock
+  * @param  HSEMx HSEM Instance.
+  * @param  key Key value.
+  * @param  core This parameter can be one of the following values:
+  *         @arg @ref LL_HSEM_COREID_CPU1
+  *         @arg @ref LL_HSEM_COREID_CPU2
+  * @retval None
+  */
+__STATIC_INLINE void LL_HSEM_ResetAllLock(HSEM_TypeDef *HSEMx, uint32_t key, uint32_t core)
+{
+  WRITE_REG(HSEMx->CR, (key << HSEM_CR_KEY_Pos) | core);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HSEM_LL_EF_IT_Management IT_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable interrupt.
+  * @rmtoll C1IER         ISEM          LL_HSEM_EnableIT_C1IER
+  * @param  HSEMx HSEM Instance.
+  * @param  SemaphoreMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_HSEM_SEMAPHORE_0
+  *         @arg @ref LL_HSEM_SEMAPHORE_1
+  *         @arg @ref LL_HSEM_SEMAPHORE_2
+  *         @arg @ref LL_HSEM_SEMAPHORE_3
+  *         @arg @ref LL_HSEM_SEMAPHORE_4
+  *         @arg @ref LL_HSEM_SEMAPHORE_5
+  *         @arg @ref LL_HSEM_SEMAPHORE_6
+  *         @arg @ref LL_HSEM_SEMAPHORE_7
+  *         @arg @ref LL_HSEM_SEMAPHORE_8
+  *         @arg @ref LL_HSEM_SEMAPHORE_9
+  *         @arg @ref LL_HSEM_SEMAPHORE_10
+  *         @arg @ref LL_HSEM_SEMAPHORE_11
+  *         @arg @ref LL_HSEM_SEMAPHORE_12
+  *         @arg @ref LL_HSEM_SEMAPHORE_13
+  *         @arg @ref LL_HSEM_SEMAPHORE_14
+  *         @arg @ref LL_HSEM_SEMAPHORE_15
+  *         @arg @ref LL_HSEM_SEMAPHORE_16
+  *         @arg @ref LL_HSEM_SEMAPHORE_17
+  *         @arg @ref LL_HSEM_SEMAPHORE_18
+  *         @arg @ref LL_HSEM_SEMAPHORE_19
+  *         @arg @ref LL_HSEM_SEMAPHORE_20
+  *         @arg @ref LL_HSEM_SEMAPHORE_21
+  *         @arg @ref LL_HSEM_SEMAPHORE_22
+  *         @arg @ref LL_HSEM_SEMAPHORE_23
+  *         @arg @ref LL_HSEM_SEMAPHORE_24
+  *         @arg @ref LL_HSEM_SEMAPHORE_25
+  *         @arg @ref LL_HSEM_SEMAPHORE_26
+  *         @arg @ref LL_HSEM_SEMAPHORE_27
+  *         @arg @ref LL_HSEM_SEMAPHORE_28
+  *         @arg @ref LL_HSEM_SEMAPHORE_29
+  *         @arg @ref LL_HSEM_SEMAPHORE_30
+  *         @arg @ref LL_HSEM_SEMAPHORE_31
+  *         @arg @ref LL_HSEM_SEMAPHORE_ALL
+  * @note   Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31
+  *         depends on devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_HSEM_EnableIT_C1IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
+{
+  SET_BIT(HSEMx->C1IER, SemaphoreMask);
+}
+
+/**
+  * @brief  Disable interrupt.
+  * @rmtoll C1IER          ISEM          LL_HSEM_DisableIT_C1IER
+  * @param  HSEMx HSEM Instance.
+  * @param  SemaphoreMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_HSEM_SEMAPHORE_0
+  *         @arg @ref LL_HSEM_SEMAPHORE_1
+  *         @arg @ref LL_HSEM_SEMAPHORE_2
+  *         @arg @ref LL_HSEM_SEMAPHORE_3
+  *         @arg @ref LL_HSEM_SEMAPHORE_4
+  *         @arg @ref LL_HSEM_SEMAPHORE_5
+  *         @arg @ref LL_HSEM_SEMAPHORE_6
+  *         @arg @ref LL_HSEM_SEMAPHORE_7
+  *         @arg @ref LL_HSEM_SEMAPHORE_8
+  *         @arg @ref LL_HSEM_SEMAPHORE_9
+  *         @arg @ref LL_HSEM_SEMAPHORE_10
+  *         @arg @ref LL_HSEM_SEMAPHORE_11
+  *         @arg @ref LL_HSEM_SEMAPHORE_12
+  *         @arg @ref LL_HSEM_SEMAPHORE_13
+  *         @arg @ref LL_HSEM_SEMAPHORE_14
+  *         @arg @ref LL_HSEM_SEMAPHORE_15
+  *         @arg @ref LL_HSEM_SEMAPHORE_16
+  *         @arg @ref LL_HSEM_SEMAPHORE_17
+  *         @arg @ref LL_HSEM_SEMAPHORE_18
+  *         @arg @ref LL_HSEM_SEMAPHORE_19
+  *         @arg @ref LL_HSEM_SEMAPHORE_20
+  *         @arg @ref LL_HSEM_SEMAPHORE_21
+  *         @arg @ref LL_HSEM_SEMAPHORE_22
+  *         @arg @ref LL_HSEM_SEMAPHORE_23
+  *         @arg @ref LL_HSEM_SEMAPHORE_24
+  *         @arg @ref LL_HSEM_SEMAPHORE_25
+  *         @arg @ref LL_HSEM_SEMAPHORE_26
+  *         @arg @ref LL_HSEM_SEMAPHORE_27
+  *         @arg @ref LL_HSEM_SEMAPHORE_28
+  *         @arg @ref LL_HSEM_SEMAPHORE_29
+  *         @arg @ref LL_HSEM_SEMAPHORE_30
+  *         @arg @ref LL_HSEM_SEMAPHORE_31
+  *         @arg @ref LL_HSEM_SEMAPHORE_ALL
+  * @note   Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31
+  *         depends on devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_HSEM_DisableIT_C1IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
+{
+  CLEAR_BIT(HSEMx->C1IER, SemaphoreMask);
+}
+
+/**
+  * @brief  Check if interrupt is enabled.
+  * @rmtoll C1IER          ISEM          LL_HSEM_IsEnabledIT_C1IER
+  * @param  HSEMx HSEM Instance.
+  * @param  SemaphoreMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_HSEM_SEMAPHORE_0
+  *         @arg @ref LL_HSEM_SEMAPHORE_1
+  *         @arg @ref LL_HSEM_SEMAPHORE_2
+  *         @arg @ref LL_HSEM_SEMAPHORE_3
+  *         @arg @ref LL_HSEM_SEMAPHORE_4
+  *         @arg @ref LL_HSEM_SEMAPHORE_5
+  *         @arg @ref LL_HSEM_SEMAPHORE_6
+  *         @arg @ref LL_HSEM_SEMAPHORE_7
+  *         @arg @ref LL_HSEM_SEMAPHORE_8
+  *         @arg @ref LL_HSEM_SEMAPHORE_9
+  *         @arg @ref LL_HSEM_SEMAPHORE_10
+  *         @arg @ref LL_HSEM_SEMAPHORE_11
+  *         @arg @ref LL_HSEM_SEMAPHORE_12
+  *         @arg @ref LL_HSEM_SEMAPHORE_13
+  *         @arg @ref LL_HSEM_SEMAPHORE_14
+  *         @arg @ref LL_HSEM_SEMAPHORE_15
+  *         @arg @ref LL_HSEM_SEMAPHORE_16
+  *         @arg @ref LL_HSEM_SEMAPHORE_17
+  *         @arg @ref LL_HSEM_SEMAPHORE_18
+  *         @arg @ref LL_HSEM_SEMAPHORE_19
+  *         @arg @ref LL_HSEM_SEMAPHORE_20
+  *         @arg @ref LL_HSEM_SEMAPHORE_21
+  *         @arg @ref LL_HSEM_SEMAPHORE_22
+  *         @arg @ref LL_HSEM_SEMAPHORE_23
+  *         @arg @ref LL_HSEM_SEMAPHORE_24
+  *         @arg @ref LL_HSEM_SEMAPHORE_25
+  *         @arg @ref LL_HSEM_SEMAPHORE_26
+  *         @arg @ref LL_HSEM_SEMAPHORE_27
+  *         @arg @ref LL_HSEM_SEMAPHORE_28
+  *         @arg @ref LL_HSEM_SEMAPHORE_29
+  *         @arg @ref LL_HSEM_SEMAPHORE_30
+  *         @arg @ref LL_HSEM_SEMAPHORE_31
+  *         @arg @ref LL_HSEM_SEMAPHORE_ALL
+  * @note   Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31
+  *         depends on devices.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HSEM_IsEnabledIT_C1IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
+{
+  return ((READ_BIT(HSEMx->C1IER, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
+}
+
+#if defined(DUAL_CORE)
+/**
+  * @brief  Enable interrupt.
+  * @rmtoll C2IER         ISEM          LL_HSEM_EnableIT_C2IER
+  * @param  HSEMx HSEM Instance.
+  * @param  SemaphoreMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_HSEM_SEMAPHORE_0
+  *         @arg @ref LL_HSEM_SEMAPHORE_1
+  *         @arg @ref LL_HSEM_SEMAPHORE_2
+  *         @arg @ref LL_HSEM_SEMAPHORE_3
+  *         @arg @ref LL_HSEM_SEMAPHORE_4
+  *         @arg @ref LL_HSEM_SEMAPHORE_5
+  *         @arg @ref LL_HSEM_SEMAPHORE_6
+  *         @arg @ref LL_HSEM_SEMAPHORE_7
+  *         @arg @ref LL_HSEM_SEMAPHORE_8
+  *         @arg @ref LL_HSEM_SEMAPHORE_9
+  *         @arg @ref LL_HSEM_SEMAPHORE_10
+  *         @arg @ref LL_HSEM_SEMAPHORE_11
+  *         @arg @ref LL_HSEM_SEMAPHORE_12
+  *         @arg @ref LL_HSEM_SEMAPHORE_13
+  *         @arg @ref LL_HSEM_SEMAPHORE_14
+  *         @arg @ref LL_HSEM_SEMAPHORE_15
+  *         @arg @ref LL_HSEM_SEMAPHORE_16
+  *         @arg @ref LL_HSEM_SEMAPHORE_17
+  *         @arg @ref LL_HSEM_SEMAPHORE_18
+  *         @arg @ref LL_HSEM_SEMAPHORE_19
+  *         @arg @ref LL_HSEM_SEMAPHORE_20
+  *         @arg @ref LL_HSEM_SEMAPHORE_21
+  *         @arg @ref LL_HSEM_SEMAPHORE_22
+  *         @arg @ref LL_HSEM_SEMAPHORE_23
+  *         @arg @ref LL_HSEM_SEMAPHORE_24
+  *         @arg @ref LL_HSEM_SEMAPHORE_25
+  *         @arg @ref LL_HSEM_SEMAPHORE_26
+  *         @arg @ref LL_HSEM_SEMAPHORE_27
+  *         @arg @ref LL_HSEM_SEMAPHORE_28
+  *         @arg @ref LL_HSEM_SEMAPHORE_29
+  *         @arg @ref LL_HSEM_SEMAPHORE_30
+  *         @arg @ref LL_HSEM_SEMAPHORE_31
+  *         @arg @ref LL_HSEM_SEMAPHORE_ALL
+  * @retval None
+  */
+__STATIC_INLINE void LL_HSEM_EnableIT_C2IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
+{
+  SET_BIT(HSEMx->C2IER, SemaphoreMask);
+}
+
+/**
+  * @brief  Disable interrupt.
+  * @rmtoll C2IER          ISEM          LL_HSEM_DisableIT_C2IER
+  * @param  HSEMx HSEM Instance.
+  * @param  SemaphoreMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_HSEM_SEMAPHORE_0
+  *         @arg @ref LL_HSEM_SEMAPHORE_1
+  *         @arg @ref LL_HSEM_SEMAPHORE_2
+  *         @arg @ref LL_HSEM_SEMAPHORE_3
+  *         @arg @ref LL_HSEM_SEMAPHORE_4
+  *         @arg @ref LL_HSEM_SEMAPHORE_5
+  *         @arg @ref LL_HSEM_SEMAPHORE_6
+  *         @arg @ref LL_HSEM_SEMAPHORE_7
+  *         @arg @ref LL_HSEM_SEMAPHORE_8
+  *         @arg @ref LL_HSEM_SEMAPHORE_9
+  *         @arg @ref LL_HSEM_SEMAPHORE_10
+  *         @arg @ref LL_HSEM_SEMAPHORE_11
+  *         @arg @ref LL_HSEM_SEMAPHORE_12
+  *         @arg @ref LL_HSEM_SEMAPHORE_13
+  *         @arg @ref LL_HSEM_SEMAPHORE_14
+  *         @arg @ref LL_HSEM_SEMAPHORE_15
+  *         @arg @ref LL_HSEM_SEMAPHORE_16
+  *         @arg @ref LL_HSEM_SEMAPHORE_17
+  *         @arg @ref LL_HSEM_SEMAPHORE_18
+  *         @arg @ref LL_HSEM_SEMAPHORE_19
+  *         @arg @ref LL_HSEM_SEMAPHORE_20
+  *         @arg @ref LL_HSEM_SEMAPHORE_21
+  *         @arg @ref LL_HSEM_SEMAPHORE_22
+  *         @arg @ref LL_HSEM_SEMAPHORE_23
+  *         @arg @ref LL_HSEM_SEMAPHORE_24
+  *         @arg @ref LL_HSEM_SEMAPHORE_25
+  *         @arg @ref LL_HSEM_SEMAPHORE_26
+  *         @arg @ref LL_HSEM_SEMAPHORE_27
+  *         @arg @ref LL_HSEM_SEMAPHORE_28
+  *         @arg @ref LL_HSEM_SEMAPHORE_29
+  *         @arg @ref LL_HSEM_SEMAPHORE_30
+  *         @arg @ref LL_HSEM_SEMAPHORE_31
+  *         @arg @ref LL_HSEM_SEMAPHORE_ALL
+  * @retval None
+  */
+__STATIC_INLINE void LL_HSEM_DisableIT_C2IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
+{
+  CLEAR_BIT(HSEMx->C2IER, SemaphoreMask);
+}
+
+/**
+  * @brief  Check if interrupt is enabled.
+  * @rmtoll C2IER          ISEM          LL_HSEM_IsEnabledIT_C2IER
+  * @param  HSEMx HSEM Instance.
+  * @param  SemaphoreMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_HSEM_SEMAPHORE_0
+  *         @arg @ref LL_HSEM_SEMAPHORE_1
+  *         @arg @ref LL_HSEM_SEMAPHORE_2
+  *         @arg @ref LL_HSEM_SEMAPHORE_3
+  *         @arg @ref LL_HSEM_SEMAPHORE_4
+  *         @arg @ref LL_HSEM_SEMAPHORE_5
+  *         @arg @ref LL_HSEM_SEMAPHORE_6
+  *         @arg @ref LL_HSEM_SEMAPHORE_7
+  *         @arg @ref LL_HSEM_SEMAPHORE_8
+  *         @arg @ref LL_HSEM_SEMAPHORE_9
+  *         @arg @ref LL_HSEM_SEMAPHORE_10
+  *         @arg @ref LL_HSEM_SEMAPHORE_11
+  *         @arg @ref LL_HSEM_SEMAPHORE_12
+  *         @arg @ref LL_HSEM_SEMAPHORE_13
+  *         @arg @ref LL_HSEM_SEMAPHORE_14
+  *         @arg @ref LL_HSEM_SEMAPHORE_15
+  *         @arg @ref LL_HSEM_SEMAPHORE_16
+  *         @arg @ref LL_HSEM_SEMAPHORE_17
+  *         @arg @ref LL_HSEM_SEMAPHORE_18
+  *         @arg @ref LL_HSEM_SEMAPHORE_19
+  *         @arg @ref LL_HSEM_SEMAPHORE_20
+  *         @arg @ref LL_HSEM_SEMAPHORE_21
+  *         @arg @ref LL_HSEM_SEMAPHORE_22
+  *         @arg @ref LL_HSEM_SEMAPHORE_23
+  *         @arg @ref LL_HSEM_SEMAPHORE_24
+  *         @arg @ref LL_HSEM_SEMAPHORE_25
+  *         @arg @ref LL_HSEM_SEMAPHORE_26
+  *         @arg @ref LL_HSEM_SEMAPHORE_27
+  *         @arg @ref LL_HSEM_SEMAPHORE_28
+  *         @arg @ref LL_HSEM_SEMAPHORE_29
+  *         @arg @ref LL_HSEM_SEMAPHORE_30
+  *         @arg @ref LL_HSEM_SEMAPHORE_31
+  *         @arg @ref LL_HSEM_SEMAPHORE_ALL
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HSEM_IsEnabledIT_C2IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
+{
+  return ((READ_BIT(HSEMx->C2IER, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
+}
+#endif /* DUAL_CORE */
+
+/**
+  * @}
+  */
+
+/** @defgroup HSEM_LL_EF_FLAG_Management FLAG_Management
+  * @{
+  */
+
+/**
+  * @brief  Clear interrupt status.
+  * @rmtoll C1ICR         ISEM          LL_HSEM_ClearFlag_C1ICR
+  * @param  HSEMx HSEM Instance.
+  * @param  SemaphoreMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_HSEM_SEMAPHORE_0
+  *         @arg @ref LL_HSEM_SEMAPHORE_1
+  *         @arg @ref LL_HSEM_SEMAPHORE_2
+  *         @arg @ref LL_HSEM_SEMAPHORE_3
+  *         @arg @ref LL_HSEM_SEMAPHORE_4
+  *         @arg @ref LL_HSEM_SEMAPHORE_5
+  *         @arg @ref LL_HSEM_SEMAPHORE_6
+  *         @arg @ref LL_HSEM_SEMAPHORE_7
+  *         @arg @ref LL_HSEM_SEMAPHORE_8
+  *         @arg @ref LL_HSEM_SEMAPHORE_9
+  *         @arg @ref LL_HSEM_SEMAPHORE_10
+  *         @arg @ref LL_HSEM_SEMAPHORE_11
+  *         @arg @ref LL_HSEM_SEMAPHORE_12
+  *         @arg @ref LL_HSEM_SEMAPHORE_13
+  *         @arg @ref LL_HSEM_SEMAPHORE_14
+  *         @arg @ref LL_HSEM_SEMAPHORE_15
+  *         @arg @ref LL_HSEM_SEMAPHORE_16
+  *         @arg @ref LL_HSEM_SEMAPHORE_17
+  *         @arg @ref LL_HSEM_SEMAPHORE_18
+  *         @arg @ref LL_HSEM_SEMAPHORE_19
+  *         @arg @ref LL_HSEM_SEMAPHORE_20
+  *         @arg @ref LL_HSEM_SEMAPHORE_21
+  *         @arg @ref LL_HSEM_SEMAPHORE_22
+  *         @arg @ref LL_HSEM_SEMAPHORE_23
+  *         @arg @ref LL_HSEM_SEMAPHORE_24
+  *         @arg @ref LL_HSEM_SEMAPHORE_25
+  *         @arg @ref LL_HSEM_SEMAPHORE_26
+  *         @arg @ref LL_HSEM_SEMAPHORE_27
+  *         @arg @ref LL_HSEM_SEMAPHORE_28
+  *         @arg @ref LL_HSEM_SEMAPHORE_29
+  *         @arg @ref LL_HSEM_SEMAPHORE_30
+  *         @arg @ref LL_HSEM_SEMAPHORE_31
+  *         @arg @ref LL_HSEM_SEMAPHORE_ALL
+  * @note   Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31
+  *         depends on devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_HSEM_ClearFlag_C1ICR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
+{
+  WRITE_REG(HSEMx->C1ICR, SemaphoreMask);
+}
+
+/**
+  * @brief  Get interrupt status from ISR register.
+  * @rmtoll C1ISR         ISEM          LL_HSEM_IsActiveFlag_C1ISR
+  * @param  HSEMx HSEM Instance.
+  * @param  SemaphoreMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_HSEM_SEMAPHORE_0
+  *         @arg @ref LL_HSEM_SEMAPHORE_1
+  *         @arg @ref LL_HSEM_SEMAPHORE_2
+  *         @arg @ref LL_HSEM_SEMAPHORE_3
+  *         @arg @ref LL_HSEM_SEMAPHORE_4
+  *         @arg @ref LL_HSEM_SEMAPHORE_5
+  *         @arg @ref LL_HSEM_SEMAPHORE_6
+  *         @arg @ref LL_HSEM_SEMAPHORE_7
+  *         @arg @ref LL_HSEM_SEMAPHORE_8
+  *         @arg @ref LL_HSEM_SEMAPHORE_9
+  *         @arg @ref LL_HSEM_SEMAPHORE_10
+  *         @arg @ref LL_HSEM_SEMAPHORE_11
+  *         @arg @ref LL_HSEM_SEMAPHORE_12
+  *         @arg @ref LL_HSEM_SEMAPHORE_13
+  *         @arg @ref LL_HSEM_SEMAPHORE_14
+  *         @arg @ref LL_HSEM_SEMAPHORE_15
+  *         @arg @ref LL_HSEM_SEMAPHORE_16
+  *         @arg @ref LL_HSEM_SEMAPHORE_17
+  *         @arg @ref LL_HSEM_SEMAPHORE_18
+  *         @arg @ref LL_HSEM_SEMAPHORE_19
+  *         @arg @ref LL_HSEM_SEMAPHORE_20
+  *         @arg @ref LL_HSEM_SEMAPHORE_21
+  *         @arg @ref LL_HSEM_SEMAPHORE_22
+  *         @arg @ref LL_HSEM_SEMAPHORE_23
+  *         @arg @ref LL_HSEM_SEMAPHORE_24
+  *         @arg @ref LL_HSEM_SEMAPHORE_25
+  *         @arg @ref LL_HSEM_SEMAPHORE_26
+  *         @arg @ref LL_HSEM_SEMAPHORE_27
+  *         @arg @ref LL_HSEM_SEMAPHORE_28
+  *         @arg @ref LL_HSEM_SEMAPHORE_29
+  *         @arg @ref LL_HSEM_SEMAPHORE_30
+  *         @arg @ref LL_HSEM_SEMAPHORE_31
+  *         @arg @ref LL_HSEM_SEMAPHORE_ALL
+  * @note   Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31
+  *         depends on devices.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C1ISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
+{
+  return ((READ_BIT(HSEMx->C1ISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get interrupt status from MISR register.
+  * @rmtoll C1MISR        ISEM          LL_HSEM_IsActiveFlag_C1MISR
+  * @param  HSEMx HSEM Instance.
+  * @param  SemaphoreMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_HSEM_SEMAPHORE_0
+  *         @arg @ref LL_HSEM_SEMAPHORE_1
+  *         @arg @ref LL_HSEM_SEMAPHORE_2
+  *         @arg @ref LL_HSEM_SEMAPHORE_3
+  *         @arg @ref LL_HSEM_SEMAPHORE_4
+  *         @arg @ref LL_HSEM_SEMAPHORE_5
+  *         @arg @ref LL_HSEM_SEMAPHORE_6
+  *         @arg @ref LL_HSEM_SEMAPHORE_7
+  *         @arg @ref LL_HSEM_SEMAPHORE_8
+  *         @arg @ref LL_HSEM_SEMAPHORE_9
+  *         @arg @ref LL_HSEM_SEMAPHORE_10
+  *         @arg @ref LL_HSEM_SEMAPHORE_11
+  *         @arg @ref LL_HSEM_SEMAPHORE_12
+  *         @arg @ref LL_HSEM_SEMAPHORE_13
+  *         @arg @ref LL_HSEM_SEMAPHORE_14
+  *         @arg @ref LL_HSEM_SEMAPHORE_15
+  *         @arg @ref LL_HSEM_SEMAPHORE_16
+  *         @arg @ref LL_HSEM_SEMAPHORE_17
+  *         @arg @ref LL_HSEM_SEMAPHORE_18
+  *         @arg @ref LL_HSEM_SEMAPHORE_19
+  *         @arg @ref LL_HSEM_SEMAPHORE_20
+  *         @arg @ref LL_HSEM_SEMAPHORE_21
+  *         @arg @ref LL_HSEM_SEMAPHORE_22
+  *         @arg @ref LL_HSEM_SEMAPHORE_23
+  *         @arg @ref LL_HSEM_SEMAPHORE_24
+  *         @arg @ref LL_HSEM_SEMAPHORE_25
+  *         @arg @ref LL_HSEM_SEMAPHORE_26
+  *         @arg @ref LL_HSEM_SEMAPHORE_27
+  *         @arg @ref LL_HSEM_SEMAPHORE_28
+  *         @arg @ref LL_HSEM_SEMAPHORE_29
+  *         @arg @ref LL_HSEM_SEMAPHORE_30
+  *         @arg @ref LL_HSEM_SEMAPHORE_31
+  *         @arg @ref LL_HSEM_SEMAPHORE_ALL
+  * @note   Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31
+  *         depends on devices.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C1MISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
+{
+  return ((READ_BIT(HSEMx->C1MISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
+}
+
+#if defined(DUAL_CORE)
+/**
+  * @brief  Clear interrupt status.
+  * @rmtoll C2ICR         ISEM          LL_HSEM_ClearFlag_C2ICR
+  * @param  HSEMx HSEM Instance.
+  * @param  SemaphoreMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_HSEM_SEMAPHORE_0
+  *         @arg @ref LL_HSEM_SEMAPHORE_1
+  *         @arg @ref LL_HSEM_SEMAPHORE_2
+  *         @arg @ref LL_HSEM_SEMAPHORE_3
+  *         @arg @ref LL_HSEM_SEMAPHORE_4
+  *         @arg @ref LL_HSEM_SEMAPHORE_5
+  *         @arg @ref LL_HSEM_SEMAPHORE_6
+  *         @arg @ref LL_HSEM_SEMAPHORE_7
+  *         @arg @ref LL_HSEM_SEMAPHORE_8
+  *         @arg @ref LL_HSEM_SEMAPHORE_9
+  *         @arg @ref LL_HSEM_SEMAPHORE_10
+  *         @arg @ref LL_HSEM_SEMAPHORE_11
+  *         @arg @ref LL_HSEM_SEMAPHORE_12
+  *         @arg @ref LL_HSEM_SEMAPHORE_13
+  *         @arg @ref LL_HSEM_SEMAPHORE_14
+  *         @arg @ref LL_HSEM_SEMAPHORE_15
+  *         @arg @ref LL_HSEM_SEMAPHORE_16
+  *         @arg @ref LL_HSEM_SEMAPHORE_17
+  *         @arg @ref LL_HSEM_SEMAPHORE_18
+  *         @arg @ref LL_HSEM_SEMAPHORE_19
+  *         @arg @ref LL_HSEM_SEMAPHORE_20
+  *         @arg @ref LL_HSEM_SEMAPHORE_21
+  *         @arg @ref LL_HSEM_SEMAPHORE_22
+  *         @arg @ref LL_HSEM_SEMAPHORE_23
+  *         @arg @ref LL_HSEM_SEMAPHORE_24
+  *         @arg @ref LL_HSEM_SEMAPHORE_25
+  *         @arg @ref LL_HSEM_SEMAPHORE_26
+  *         @arg @ref LL_HSEM_SEMAPHORE_27
+  *         @arg @ref LL_HSEM_SEMAPHORE_28
+  *         @arg @ref LL_HSEM_SEMAPHORE_29
+  *         @arg @ref LL_HSEM_SEMAPHORE_30
+  *         @arg @ref LL_HSEM_SEMAPHORE_31
+  *         @arg @ref LL_HSEM_SEMAPHORE_ALL
+  * @retval None
+  */
+__STATIC_INLINE void LL_HSEM_ClearFlag_C2ICR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
+{
+  WRITE_REG(HSEMx->C2ICR, SemaphoreMask);
+}
+
+/**
+  * @brief  Get interrupt status from ISR register.
+  * @rmtoll C2ISR         ISEM          LL_HSEM_IsActiveFlag_C2ISR
+  * @param  HSEMx HSEM Instance.
+  * @param  SemaphoreMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_HSEM_SEMAPHORE_0
+  *         @arg @ref LL_HSEM_SEMAPHORE_1
+  *         @arg @ref LL_HSEM_SEMAPHORE_2
+  *         @arg @ref LL_HSEM_SEMAPHORE_3
+  *         @arg @ref LL_HSEM_SEMAPHORE_4
+  *         @arg @ref LL_HSEM_SEMAPHORE_5
+  *         @arg @ref LL_HSEM_SEMAPHORE_6
+  *         @arg @ref LL_HSEM_SEMAPHORE_7
+  *         @arg @ref LL_HSEM_SEMAPHORE_8
+  *         @arg @ref LL_HSEM_SEMAPHORE_9
+  *         @arg @ref LL_HSEM_SEMAPHORE_10
+  *         @arg @ref LL_HSEM_SEMAPHORE_11
+  *         @arg @ref LL_HSEM_SEMAPHORE_12
+  *         @arg @ref LL_HSEM_SEMAPHORE_13
+  *         @arg @ref LL_HSEM_SEMAPHORE_14
+  *         @arg @ref LL_HSEM_SEMAPHORE_15
+  *         @arg @ref LL_HSEM_SEMAPHORE_16
+  *         @arg @ref LL_HSEM_SEMAPHORE_17
+  *         @arg @ref LL_HSEM_SEMAPHORE_18
+  *         @arg @ref LL_HSEM_SEMAPHORE_19
+  *         @arg @ref LL_HSEM_SEMAPHORE_20
+  *         @arg @ref LL_HSEM_SEMAPHORE_21
+  *         @arg @ref LL_HSEM_SEMAPHORE_22
+  *         @arg @ref LL_HSEM_SEMAPHORE_23
+  *         @arg @ref LL_HSEM_SEMAPHORE_24
+  *         @arg @ref LL_HSEM_SEMAPHORE_25
+  *         @arg @ref LL_HSEM_SEMAPHORE_26
+  *         @arg @ref LL_HSEM_SEMAPHORE_27
+  *         @arg @ref LL_HSEM_SEMAPHORE_28
+  *         @arg @ref LL_HSEM_SEMAPHORE_29
+  *         @arg @ref LL_HSEM_SEMAPHORE_30
+  *         @arg @ref LL_HSEM_SEMAPHORE_31
+  *         @arg @ref LL_HSEM_SEMAPHORE_ALL
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C2ISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
+{
+  return ((READ_BIT(HSEMx->C2ISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get interrupt status from MISR register.
+  * @rmtoll C2MISR        ISEM          LL_HSEM_IsActiveFlag_C2MISR
+  * @param  HSEMx HSEM Instance.
+  * @param  SemaphoreMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_HSEM_SEMAPHORE_0
+  *         @arg @ref LL_HSEM_SEMAPHORE_1
+  *         @arg @ref LL_HSEM_SEMAPHORE_2
+  *         @arg @ref LL_HSEM_SEMAPHORE_3
+  *         @arg @ref LL_HSEM_SEMAPHORE_4
+  *         @arg @ref LL_HSEM_SEMAPHORE_5
+  *         @arg @ref LL_HSEM_SEMAPHORE_6
+  *         @arg @ref LL_HSEM_SEMAPHORE_7
+  *         @arg @ref LL_HSEM_SEMAPHORE_8
+  *         @arg @ref LL_HSEM_SEMAPHORE_9
+  *         @arg @ref LL_HSEM_SEMAPHORE_10
+  *         @arg @ref LL_HSEM_SEMAPHORE_11
+  *         @arg @ref LL_HSEM_SEMAPHORE_12
+  *         @arg @ref LL_HSEM_SEMAPHORE_13
+  *         @arg @ref LL_HSEM_SEMAPHORE_14
+  *         @arg @ref LL_HSEM_SEMAPHORE_15
+  *         @arg @ref LL_HSEM_SEMAPHORE_16
+  *         @arg @ref LL_HSEM_SEMAPHORE_17
+  *         @arg @ref LL_HSEM_SEMAPHORE_18
+  *         @arg @ref LL_HSEM_SEMAPHORE_19
+  *         @arg @ref LL_HSEM_SEMAPHORE_20
+  *         @arg @ref LL_HSEM_SEMAPHORE_21
+  *         @arg @ref LL_HSEM_SEMAPHORE_22
+  *         @arg @ref LL_HSEM_SEMAPHORE_23
+  *         @arg @ref LL_HSEM_SEMAPHORE_24
+  *         @arg @ref LL_HSEM_SEMAPHORE_25
+  *         @arg @ref LL_HSEM_SEMAPHORE_26
+  *         @arg @ref LL_HSEM_SEMAPHORE_27
+  *         @arg @ref LL_HSEM_SEMAPHORE_28
+  *         @arg @ref LL_HSEM_SEMAPHORE_29
+  *         @arg @ref LL_HSEM_SEMAPHORE_30
+  *         @arg @ref LL_HSEM_SEMAPHORE_31
+  *         @arg @ref LL_HSEM_SEMAPHORE_ALL
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C2MISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
+{
+  return ((READ_BIT(HSEMx->C2MISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
+}
+#endif /* DUAL_CORE */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined(HSEM) */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32H7xx_LL_HSEM_H */
diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_i2c.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_i2c.h
index a93b97f5..351dfb9f 100644
--- a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_i2c.h
+++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_i2c.h
@@ -1,2272 +1,2272 @@
-/**
-  ******************************************************************************
-  * @file    stm32h7xx_ll_i2c.h
-  * @author  MCD Application Team
-  * @brief   Header file of I2C LL module.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32H7xx_LL_I2C_H
-#define STM32H7xx_LL_I2C_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx.h"
-
-/** @addtogroup STM32H7xx_LL_Driver
-  * @{
-  */
-
-#if defined (I2C1) || defined (I2C2) || defined (I2C3) || defined (I2C4) || defined (I2C5)
-
-/** @defgroup I2C_LL I2C
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup I2C_LL_Private_Constants I2C Private Constants
-  * @{
-  */
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup I2C_LL_Private_Macros I2C Private Macros
-  * @{
-  */
-/**
-  * @}
-  */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup I2C_LL_ES_INIT I2C Exported Init structure
-  * @{
-  */
-typedef struct
-{
-  uint32_t PeripheralMode;      /*!< Specifies the peripheral mode.
-                                     This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE.
-
-                                     This feature can be modified afterwards using unitary function
-                                     @ref LL_I2C_SetMode(). */
-
-  uint32_t Timing;              /*!< Specifies the SDA setup, hold time and the SCL high, low period values.
-                                     This parameter must be set by referring to the STM32CubeMX Tool and
-                                     the helper macro @ref __LL_I2C_CONVERT_TIMINGS().
-
-                                     This feature can be modified afterwards using unitary function
-                                     @ref LL_I2C_SetTiming(). */
-
-  uint32_t AnalogFilter;        /*!< Enables or disables analog noise filter.
-                                     This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION.
-
-                                     This feature can be modified afterwards using unitary functions
-                                     @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */
-
-  uint32_t DigitalFilter;       /*!< Configures the digital noise filter.
-                                     This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F.
-
-                                     This feature can be modified afterwards using unitary function
-                                     @ref LL_I2C_SetDigitalFilter(). */
-
-  uint32_t OwnAddress1;         /*!< Specifies the device own address 1.
-                                     This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF.
-
-                                     This feature can be modified afterwards using unitary function
-                                     @ref LL_I2C_SetOwnAddress1(). */
-
-  uint32_t TypeAcknowledge;     /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive
-                                     match code or next received byte.
-                                     This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE.
-
-                                     This feature can be modified afterwards using unitary function
-                                     @ref LL_I2C_AcknowledgeNextData(). */
-
-  uint32_t OwnAddrSize;         /*!< Specifies the device own address 1 size (7-bit or 10-bit).
-                                     This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1.
-
-                                     This feature can be modified afterwards using unitary function
-                                     @ref LL_I2C_SetOwnAddress1(). */
-} LL_I2C_InitTypeDef;
-/**
-  * @}
-  */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup I2C_LL_Exported_Constants I2C Exported Constants
-  * @{
-  */
-
-/** @defgroup I2C_LL_EC_CLEAR_FLAG Clear Flags Defines
-  * @brief    Flags defines which can be used with LL_I2C_WriteReg function
-  * @{
-  */
-#define LL_I2C_ICR_ADDRCF                   I2C_ICR_ADDRCF          /*!< Address Matched flag   */
-#define LL_I2C_ICR_NACKCF                   I2C_ICR_NACKCF          /*!< Not Acknowledge flag   */
-#define LL_I2C_ICR_STOPCF                   I2C_ICR_STOPCF          /*!< Stop detection flag    */
-#define LL_I2C_ICR_BERRCF                   I2C_ICR_BERRCF          /*!< Bus error flag         */
-#define LL_I2C_ICR_ARLOCF                   I2C_ICR_ARLOCF          /*!< Arbitration Lost flag  */
-#define LL_I2C_ICR_OVRCF                    I2C_ICR_OVRCF           /*!< Overrun/Underrun flag  */
-#define LL_I2C_ICR_PECCF                    I2C_ICR_PECCF           /*!< PEC error flag         */
-#define LL_I2C_ICR_TIMOUTCF                 I2C_ICR_TIMOUTCF        /*!< Timeout detection flag */
-#define LL_I2C_ICR_ALERTCF                  I2C_ICR_ALERTCF         /*!< Alert flag             */
-/**
-  * @}
-  */
-
-/** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines
-  * @brief    Flags defines which can be used with LL_I2C_ReadReg function
-  * @{
-  */
-#define LL_I2C_ISR_TXE                      I2C_ISR_TXE             /*!< Transmit data register empty        */
-#define LL_I2C_ISR_TXIS                     I2C_ISR_TXIS            /*!< Transmit interrupt status           */
-#define LL_I2C_ISR_RXNE                     I2C_ISR_RXNE            /*!< Receive data register not empty     */
-#define LL_I2C_ISR_ADDR                     I2C_ISR_ADDR            /*!< Address matched (slave mode)        */
-#define LL_I2C_ISR_NACKF                    I2C_ISR_NACKF           /*!< Not Acknowledge received flag       */
-#define LL_I2C_ISR_STOPF                    I2C_ISR_STOPF           /*!< Stop detection flag                 */
-#define LL_I2C_ISR_TC                       I2C_ISR_TC              /*!< Transfer Complete (master mode)     */
-#define LL_I2C_ISR_TCR                      I2C_ISR_TCR             /*!< Transfer Complete Reload            */
-#define LL_I2C_ISR_BERR                     I2C_ISR_BERR            /*!< Bus error                           */
-#define LL_I2C_ISR_ARLO                     I2C_ISR_ARLO            /*!< Arbitration lost                    */
-#define LL_I2C_ISR_OVR                      I2C_ISR_OVR             /*!< Overrun/Underrun (slave mode)       */
-#define LL_I2C_ISR_PECERR                   I2C_ISR_PECERR          /*!< PEC Error in reception (SMBus mode) */
-#define LL_I2C_ISR_TIMEOUT                  I2C_ISR_TIMEOUT         /*!< Timeout detection flag (SMBus mode) */
-#define LL_I2C_ISR_ALERT                    I2C_ISR_ALERT           /*!< SMBus alert (SMBus mode)            */
-#define LL_I2C_ISR_BUSY                     I2C_ISR_BUSY            /*!< Bus busy                            */
-/**
-  * @}
-  */
-
-/** @defgroup I2C_LL_EC_IT IT Defines
-  * @brief    IT defines which can be used with LL_I2C_ReadReg and  LL_I2C_WriteReg functions
-  * @{
-  */
-#define LL_I2C_CR1_TXIE                     I2C_CR1_TXIE            /*!< TX Interrupt enable                         */
-#define LL_I2C_CR1_RXIE                     I2C_CR1_RXIE            /*!< RX Interrupt enable                         */
-#define LL_I2C_CR1_ADDRIE                   I2C_CR1_ADDRIE          /*!< Address match Interrupt enable (slave only) */
-#define LL_I2C_CR1_NACKIE                   I2C_CR1_NACKIE          /*!< Not acknowledge received Interrupt enable   */
-#define LL_I2C_CR1_STOPIE                   I2C_CR1_STOPIE          /*!< STOP detection Interrupt enable             */
-#define LL_I2C_CR1_TCIE                     I2C_CR1_TCIE            /*!< Transfer Complete interrupt enable          */
-#define LL_I2C_CR1_ERRIE                    I2C_CR1_ERRIE           /*!< Error interrupts enable                     */
-/**
-  * @}
-  */
-
-/** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
-  * @{
-  */
-#define LL_I2C_MODE_I2C                    0x00000000U              /*!< I2C Master or Slave mode                 */
-#define LL_I2C_MODE_SMBUS_HOST             I2C_CR1_SMBHEN           /*!< SMBus Host address acknowledge           */
-#define LL_I2C_MODE_SMBUS_DEVICE           0x00000000U              /*!< SMBus Device default mode
-                                                                         (Default address not acknowledge)        */
-#define LL_I2C_MODE_SMBUS_DEVICE_ARP       I2C_CR1_SMBDEN           /*!< SMBus Device Default address acknowledge */
-/**
-  * @}
-  */
-
-/** @defgroup I2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection
-  * @{
-  */
-#define LL_I2C_ANALOGFILTER_ENABLE          0x00000000U             /*!< Analog filter is enabled.  */
-#define LL_I2C_ANALOGFILTER_DISABLE         I2C_CR1_ANFOFF          /*!< Analog filter is disabled. */
-/**
-  * @}
-  */
-
-/** @defgroup I2C_LL_EC_ADDRESSING_MODE Master Addressing Mode
-  * @{
-  */
-#define LL_I2C_ADDRESSING_MODE_7BIT         0x00000000U              /*!< Master operates in 7-bit addressing mode. */
-#define LL_I2C_ADDRESSING_MODE_10BIT        I2C_CR2_ADD10            /*!< Master operates in 10-bit addressing mode.*/
-/**
-  * @}
-  */
-
-/** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length
-  * @{
-  */
-#define LL_I2C_OWNADDRESS1_7BIT             0x00000000U             /*!< Own address 1 is a 7-bit address. */
-#define LL_I2C_OWNADDRESS1_10BIT            I2C_OAR1_OA1MODE        /*!< Own address 1 is a 10-bit address.*/
-/**
-  * @}
-  */
-
-/** @defgroup I2C_LL_EC_OWNADDRESS2 Own Address 2 Masks
-  * @{
-  */
-#define LL_I2C_OWNADDRESS2_NOMASK           I2C_OAR2_OA2NOMASK      /*!< Own Address2 No mask.                 */
-#define LL_I2C_OWNADDRESS2_MASK01           I2C_OAR2_OA2MASK01      /*!< Only Address2 bits[7:2] are compared. */
-#define LL_I2C_OWNADDRESS2_MASK02           I2C_OAR2_OA2MASK02      /*!< Only Address2 bits[7:3] are compared. */
-#define LL_I2C_OWNADDRESS2_MASK03           I2C_OAR2_OA2MASK03      /*!< Only Address2 bits[7:4] are compared. */
-#define LL_I2C_OWNADDRESS2_MASK04           I2C_OAR2_OA2MASK04      /*!< Only Address2 bits[7:5] are compared. */
-#define LL_I2C_OWNADDRESS2_MASK05           I2C_OAR2_OA2MASK05      /*!< Only Address2 bits[7:6] are compared. */
-#define LL_I2C_OWNADDRESS2_MASK06           I2C_OAR2_OA2MASK06      /*!< Only Address2 bits[7] are compared.   */
-#define LL_I2C_OWNADDRESS2_MASK07           I2C_OAR2_OA2MASK07      /*!< No comparison is done.
-                                                                         All Address2 are acknowledged.        */
-/**
-  * @}
-  */
-
-/** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation
-  * @{
-  */
-#define LL_I2C_ACK                          0x00000000U              /*!< ACK is sent after current received byte. */
-#define LL_I2C_NACK                         I2C_CR2_NACK             /*!< NACK is sent after current received byte.*/
-/**
-  * @}
-  */
-
-/** @defgroup I2C_LL_EC_ADDRSLAVE Slave Address Length
-  * @{
-  */
-#define LL_I2C_ADDRSLAVE_7BIT               0x00000000U              /*!< Slave Address in 7-bit. */
-#define LL_I2C_ADDRSLAVE_10BIT              I2C_CR2_ADD10            /*!< Slave Address in 10-bit.*/
-/**
-  * @}
-  */
-
-/** @defgroup I2C_LL_EC_REQUEST Transfer Request Direction
-  * @{
-  */
-#define LL_I2C_REQUEST_WRITE                0x00000000U              /*!< Master request a write transfer. */
-#define LL_I2C_REQUEST_READ                 I2C_CR2_RD_WRN           /*!< Master request a read transfer.  */
-/**
-  * @}
-  */
-
-/** @defgroup I2C_LL_EC_MODE Transfer End Mode
-  * @{
-  */
-#define LL_I2C_MODE_RELOAD                  I2C_CR2_RELOAD           /*!< Enable I2C Reload mode.     */
-#define LL_I2C_MODE_AUTOEND                 I2C_CR2_AUTOEND          /*!< Enable I2C Automatic end mode
-                                                                          with no HW PEC comparison.  */
-#define LL_I2C_MODE_SOFTEND                 0x00000000U              /*!< Enable I2C Software end mode
-                                                                          with no HW PEC comparison.  */
-#define LL_I2C_MODE_SMBUS_RELOAD            LL_I2C_MODE_RELOAD       /*!< Enable SMBUS Automatic end mode
-                                                                          with HW PEC comparison.     */
-#define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC    LL_I2C_MODE_AUTOEND      /*!< Enable SMBUS Automatic end mode
-                                                                          with HW PEC comparison.     */
-#define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC    LL_I2C_MODE_SOFTEND      /*!< Enable SMBUS Software end mode
-                                                                          with HW PEC comparison.     */
-#define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC  (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE)
-/*!< Enable SMBUS Automatic end mode with HW PEC comparison.   */
-#define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC  (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE)
-/*!< Enable SMBUS Software end mode with HW PEC comparison.    */
-/**
-  * @}
-  */
-
-/** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation
-  * @{
-  */
-#define LL_I2C_GENERATE_NOSTARTSTOP         0x00000000U
-/*!< Don't Generate Stop and Start condition. */
-#define LL_I2C_GENERATE_STOP                (uint32_t)(0x80000000U | I2C_CR2_STOP)
-/*!< Generate Stop condition (Size should be set to 0).      */
-#define LL_I2C_GENERATE_START_READ          (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
-/*!< Generate Start for read request. */
-#define LL_I2C_GENERATE_START_WRITE         (uint32_t)(0x80000000U | I2C_CR2_START)
-/*!< Generate Start for write request. */
-#define LL_I2C_GENERATE_RESTART_7BIT_READ   (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
-/*!< Generate Restart for read request, slave 7Bit address.  */
-#define LL_I2C_GENERATE_RESTART_7BIT_WRITE  (uint32_t)(0x80000000U | I2C_CR2_START)
-/*!< Generate Restart for write request, slave 7Bit address. */
-#define LL_I2C_GENERATE_RESTART_10BIT_READ  (uint32_t)(0x80000000U | I2C_CR2_START | \
-                                                       I2C_CR2_RD_WRN | I2C_CR2_HEAD10R)
-/*!< Generate Restart for read request, slave 10Bit address. */
-#define LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
-/*!< Generate Restart for write request, slave 10Bit address.*/
-/**
-  * @}
-  */
-
-/** @defgroup I2C_LL_EC_DIRECTION Read Write Direction
-  * @{
-  */
-#define LL_I2C_DIRECTION_WRITE              0x00000000U              /*!< Write transfer request by master,
-                                                                          slave enters receiver mode.  */
-#define LL_I2C_DIRECTION_READ               I2C_ISR_DIR              /*!< Read transfer request by master,
-                                                                          slave enters transmitter mode.*/
-/**
-  * @}
-  */
-
-/** @defgroup I2C_LL_EC_DMA_REG_DATA DMA Register Data
-  * @{
-  */
-#define LL_I2C_DMA_REG_DATA_TRANSMIT        0x00000000U              /*!< Get address of data register used for
-                                                                          transmission */
-#define LL_I2C_DMA_REG_DATA_RECEIVE         0x00000001U              /*!< Get address of data register used for
-                                                                          reception */
-/**
-  * @}
-  */
-
-/** @defgroup I2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus TimeoutA Mode SCL SDA Timeout
-  * @{
-  */
-#define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW      0x00000000U          /*!< TimeoutA is used to detect
-                                                                          SCL low level timeout.              */
-#define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE   /*!< TimeoutA is used to detect
-                                                                          both SCL and SDA high level timeout.*/
-/**
-  * @}
-  */
-
-/** @defgroup I2C_LL_EC_SMBUS_TIMEOUT_SELECTION SMBus Timeout Selection
-  * @{
-  */
-#define LL_I2C_SMBUS_TIMEOUTA               I2C_TIMEOUTR_TIMOUTEN                 /*!< TimeoutA enable bit          */
-#define LL_I2C_SMBUS_TIMEOUTB               I2C_TIMEOUTR_TEXTEN                   /*!< TimeoutB (extended clock)
-                                                                                       enable bit                   */
-#define LL_I2C_SMBUS_ALL_TIMEOUT            (uint32_t)(I2C_TIMEOUTR_TIMOUTEN | \
-                                                       I2C_TIMEOUTR_TEXTEN)       /*!< TimeoutA and TimeoutB
-(extended clock) enable bits */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup I2C_LL_Exported_Macros I2C Exported Macros
-  * @{
-  */
-
-/** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros
-  * @{
-  */
-
-/**
-  * @brief  Write a value in I2C register
-  * @param  __INSTANCE__ I2C Instance
-  * @param  __REG__ Register to be written
-  * @param  __VALUE__ Value to be written in the register
-  * @retval None
-  */
-#define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
-  * @brief  Read a value in I2C register
-  * @param  __INSTANCE__ I2C Instance
-  * @param  __REG__ Register to be read
-  * @retval Register value
-  */
-#define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
-  * @}
-  */
-
-/** @defgroup I2C_LL_EM_CONVERT_TIMINGS Convert SDA SCL timings
-  * @{
-  */
-/**
-  * @brief  Configure the SDA setup, hold time and the SCL high, low period.
-  * @param  __PRESCALER__ This parameter must be a value between  Min_Data=0 and Max_Data=0xF.
-  * @param  __SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF.
-                           (tscldel = (SCLDEL+1)xtpresc)
-  * @param  __HOLD_TIME__  This parameter must be a value between Min_Data=0 and Max_Data=0xF.
-                           (tsdadel = SDADELxtpresc)
-  * @param  __SCLH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF.
-                            (tsclh = (SCLH+1)xtpresc)
-  * @param  __SCLL_PERIOD__ This parameter must be a value between  Min_Data=0 and Max_Data=0xFF.
-                            (tscll = (SCLL+1)xtpresc)
-  * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
-  */
-#define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __SETUP_TIME__, __HOLD_TIME__, __SCLH_PERIOD__, __SCLL_PERIOD__) \
-  ((((uint32_t)(__PRESCALER__)    << I2C_TIMINGR_PRESC_Pos)  & I2C_TIMINGR_PRESC)   | \
-   (((uint32_t)(__SETUP_TIME__)   << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL)  | \
-   (((uint32_t)(__HOLD_TIME__)    << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL)  | \
-   (((uint32_t)(__SCLH_PERIOD__)  << I2C_TIMINGR_SCLH_Pos)   & I2C_TIMINGR_SCLH)    | \
-   (((uint32_t)(__SCLL_PERIOD__)  << I2C_TIMINGR_SCLL_Pos)   & I2C_TIMINGR_SCLL))
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup I2C_LL_Exported_Functions I2C Exported Functions
-  * @{
-  */
-
-/** @defgroup I2C_LL_EF_Configuration Configuration
-  * @{
-  */
-
-/**
-  * @brief  Enable I2C peripheral (PE = 1).
-  * @rmtoll CR1          PE            LL_I2C_Enable
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR1, I2C_CR1_PE);
-}
-
-/**
-  * @brief  Disable I2C peripheral (PE = 0).
-  * @note   When PE = 0, the I2C SCL and SDA lines are released.
-  *         Internal state machines and status bits are put back to their reset value.
-  *         When cleared, PE must be kept low for at least 3 APB clock cycles.
-  * @rmtoll CR1          PE            LL_I2C_Disable
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE);
-}
-
-/**
-  * @brief  Check if the I2C peripheral is enabled or disabled.
-  * @rmtoll CR1          PE            LL_I2C_IsEnabled
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Configure Noise Filters (Analog and Digital).
-  * @note   If the analog filter is also enabled, the digital filter is added to analog filter.
-  *         The filters can only be programmed when the I2C is disabled (PE = 0).
-  * @rmtoll CR1          ANFOFF        LL_I2C_ConfigFilters\n
-  *         CR1          DNF           LL_I2C_ConfigFilters
-  * @param  I2Cx I2C Instance.
-  * @param  AnalogFilter This parameter can be one of the following values:
-  *         @arg @ref LL_I2C_ANALOGFILTER_ENABLE
-  *         @arg @ref LL_I2C_ANALOGFILTER_DISABLE
-  * @param  DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled)
-                          and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
-  *         This parameter is used to configure the digital noise filter on SDA and SCL input.
-  *         The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter)
-{
-  MODIFY_REG(I2Cx->CR1, I2C_CR1_ANFOFF | I2C_CR1_DNF, AnalogFilter | (DigitalFilter << I2C_CR1_DNF_Pos));
-}
-
-/**
-  * @brief  Configure Digital Noise Filter.
-  * @note   If the analog filter is also enabled, the digital filter is added to analog filter.
-  *         This filter can only be programmed when the I2C is disabled (PE = 0).
-  * @rmtoll CR1          DNF           LL_I2C_SetDigitalFilter
-  * @param  I2Cx I2C Instance.
-  * @param  DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled)
-                          and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
-  *         This parameter is used to configure the digital noise filter on SDA and SCL input.
-  *         The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t DigitalFilter)
-{
-  MODIFY_REG(I2Cx->CR1, I2C_CR1_DNF, DigitalFilter << I2C_CR1_DNF_Pos);
-}
-
-/**
-  * @brief  Get the current Digital Noise Filter configuration.
-  * @rmtoll CR1          DNF           LL_I2C_GetDigitalFilter
-  * @param  I2Cx I2C Instance.
-  * @retval Value between Min_Data=0x0 and Max_Data=0xF
-  */
-__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(I2C_TypeDef *I2Cx)
-{
-  return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_CR1_DNF_Pos);
-}
-
-/**
-  * @brief  Enable Analog Noise Filter.
-  * @note   This filter can only be programmed when the I2C is disabled (PE = 0).
-  * @rmtoll CR1          ANFOFF        LL_I2C_EnableAnalogFilter
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableAnalogFilter(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
-}
-
-/**
-  * @brief  Disable Analog Noise Filter.
-  * @note   This filter can only be programmed when the I2C is disabled (PE = 0).
-  * @rmtoll CR1          ANFOFF        LL_I2C_DisableAnalogFilter
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
-}
-
-/**
-  * @brief  Check if Analog Noise Filter is enabled or disabled.
-  * @rmtoll CR1          ANFOFF        LL_I2C_IsEnabledAnalogFilter
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable DMA transmission requests.
-  * @rmtoll CR1          TXDMAEN       LL_I2C_EnableDMAReq_TX
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
-}
-
-/**
-  * @brief  Disable DMA transmission requests.
-  * @rmtoll CR1          TXDMAEN       LL_I2C_DisableDMAReq_TX
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
-}
-
-/**
-  * @brief  Check if DMA transmission requests are enabled or disabled.
-  * @rmtoll CR1          TXDMAEN       LL_I2C_IsEnabledDMAReq_TX
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable DMA reception requests.
-  * @rmtoll CR1          RXDMAEN       LL_I2C_EnableDMAReq_RX
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
-}
-
-/**
-  * @brief  Disable DMA reception requests.
-  * @rmtoll CR1          RXDMAEN       LL_I2C_DisableDMAReq_RX
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
-}
-
-/**
-  * @brief  Check if DMA reception requests are enabled or disabled.
-  * @rmtoll CR1          RXDMAEN       LL_I2C_IsEnabledDMAReq_RX
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get the data register address used for DMA transfer
-  * @rmtoll TXDR         TXDATA        LL_I2C_DMA_GetRegAddr\n
-  *         RXDR         RXDATA        LL_I2C_DMA_GetRegAddr
-  * @param  I2Cx I2C Instance
-  * @param  Direction This parameter can be one of the following values:
-  *         @arg @ref LL_I2C_DMA_REG_DATA_TRANSMIT
-  *         @arg @ref LL_I2C_DMA_REG_DATA_RECEIVE
-  * @retval Address of data register
-  */
-__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx, uint32_t Direction)
-{
-  uint32_t data_reg_addr;
-
-  if (Direction == LL_I2C_DMA_REG_DATA_TRANSMIT)
-  {
-    /* return address of TXDR register */
-    data_reg_addr = (uint32_t) &(I2Cx->TXDR);
-  }
-  else
-  {
-    /* return address of RXDR register */
-    data_reg_addr = (uint32_t) &(I2Cx->RXDR);
-  }
-
-  return data_reg_addr;
-}
-
-/**
-  * @brief  Enable Clock stretching.
-  * @note   This bit can only be programmed when the I2C is disabled (PE = 0).
-  * @rmtoll CR1          NOSTRETCH     LL_I2C_EnableClockStretching
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
-}
-
-/**
-  * @brief  Disable Clock stretching.
-  * @note   This bit can only be programmed when the I2C is disabled (PE = 0).
-  * @rmtoll CR1          NOSTRETCH     LL_I2C_DisableClockStretching
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
-}
-
-/**
-  * @brief  Check if Clock stretching is enabled or disabled.
-  * @rmtoll CR1          NOSTRETCH     LL_I2C_IsEnabledClockStretching
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable hardware byte control in slave mode.
-  * @rmtoll CR1          SBC           LL_I2C_EnableSlaveByteControl
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableSlaveByteControl(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR1, I2C_CR1_SBC);
-}
-
-/**
-  * @brief  Disable hardware byte control in slave mode.
-  * @rmtoll CR1          SBC           LL_I2C_DisableSlaveByteControl
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableSlaveByteControl(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR1, I2C_CR1_SBC);
-}
-
-/**
-  * @brief  Check if hardware byte control in slave mode is enabled or disabled.
-  * @rmtoll CR1          SBC           LL_I2C_IsEnabledSlaveByteControl
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable Wakeup from STOP.
-  * @note   The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
-  *         WakeUpFromStop feature is supported by the I2Cx Instance.
-  * @note   This bit can only be programmed when Digital Filter is disabled.
-  * @rmtoll CR1          WUPEN         LL_I2C_EnableWakeUpFromStop
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableWakeUpFromStop(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
-}
-
-/**
-  * @brief  Disable Wakeup from STOP.
-  * @note   The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
-  *         WakeUpFromStop feature is supported by the I2Cx Instance.
-  * @rmtoll CR1          WUPEN         LL_I2C_DisableWakeUpFromStop
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableWakeUpFromStop(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
-}
-
-/**
-  * @brief  Check if Wakeup from STOP is enabled or disabled.
-  * @note   The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
-  *         WakeUpFromStop feature is supported by the I2Cx Instance.
-  * @rmtoll CR1          WUPEN         LL_I2C_IsEnabledWakeUpFromStop
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->CR1, I2C_CR1_WUPEN) == (I2C_CR1_WUPEN)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable General Call.
-  * @note   When enabled the Address 0x00 is ACKed.
-  * @rmtoll CR1          GCEN          LL_I2C_EnableGeneralCall
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR1, I2C_CR1_GCEN);
-}
-
-/**
-  * @brief  Disable General Call.
-  * @note   When disabled the Address 0x00 is NACKed.
-  * @rmtoll CR1          GCEN          LL_I2C_DisableGeneralCall
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR1, I2C_CR1_GCEN);
-}
-
-/**
-  * @brief  Check if General Call is enabled or disabled.
-  * @rmtoll CR1          GCEN          LL_I2C_IsEnabledGeneralCall
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Configure the Master to operate in 7-bit or 10-bit addressing mode.
-  * @note   Changing this bit is not allowed, when the START bit is set.
-  * @rmtoll CR2          ADD10         LL_I2C_SetMasterAddressingMode
-  * @param  I2Cx I2C Instance.
-  * @param  AddressingMode This parameter can be one of the following values:
-  *         @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
-  *         @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_SetMasterAddressingMode(I2C_TypeDef *I2Cx, uint32_t AddressingMode)
-{
-  MODIFY_REG(I2Cx->CR2, I2C_CR2_ADD10, AddressingMode);
-}
-
-/**
-  * @brief  Get the Master addressing mode.
-  * @rmtoll CR2          ADD10         LL_I2C_GetMasterAddressingMode
-  * @param  I2Cx I2C Instance.
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
-  *         @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
-  */
-__STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(I2C_TypeDef *I2Cx)
-{
-  return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_ADD10));
-}
-
-/**
-  * @brief  Set the Own Address1.
-  * @rmtoll OAR1         OA1           LL_I2C_SetOwnAddress1\n
-  *         OAR1         OA1MODE       LL_I2C_SetOwnAddress1
-  * @param  I2Cx I2C Instance.
-  * @param  OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.
-  * @param  OwnAddrSize This parameter can be one of the following values:
-  *         @arg @ref LL_I2C_OWNADDRESS1_7BIT
-  *         @arg @ref LL_I2C_OWNADDRESS1_10BIT
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
-{
-  MODIFY_REG(I2Cx->OAR1, I2C_OAR1_OA1 | I2C_OAR1_OA1MODE, OwnAddress1 | OwnAddrSize);
-}
-
-/**
-  * @brief  Enable acknowledge on Own Address1 match address.
-  * @rmtoll OAR1         OA1EN         LL_I2C_EnableOwnAddress1
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableOwnAddress1(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
-}
-
-/**
-  * @brief  Disable acknowledge on Own Address1 match address.
-  * @rmtoll OAR1         OA1EN         LL_I2C_DisableOwnAddress1
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableOwnAddress1(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
-}
-
-/**
-  * @brief  Check if Own Address1 acknowledge is enabled or disabled.
-  * @rmtoll OAR1         OA1EN         LL_I2C_IsEnabledOwnAddress1
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Set the 7bits Own Address2.
-  * @note   This action has no effect if own address2 is enabled.
-  * @rmtoll OAR2         OA2           LL_I2C_SetOwnAddress2\n
-  *         OAR2         OA2MSK        LL_I2C_SetOwnAddress2
-  * @param  I2Cx I2C Instance.
-  * @param  OwnAddress2 Value between Min_Data=0 and Max_Data=0x7F.
-  * @param  OwnAddrMask This parameter can be one of the following values:
-  *         @arg @ref LL_I2C_OWNADDRESS2_NOMASK
-  *         @arg @ref LL_I2C_OWNADDRESS2_MASK01
-  *         @arg @ref LL_I2C_OWNADDRESS2_MASK02
-  *         @arg @ref LL_I2C_OWNADDRESS2_MASK03
-  *         @arg @ref LL_I2C_OWNADDRESS2_MASK04
-  *         @arg @ref LL_I2C_OWNADDRESS2_MASK05
-  *         @arg @ref LL_I2C_OWNADDRESS2_MASK06
-  *         @arg @ref LL_I2C_OWNADDRESS2_MASK07
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2, uint32_t OwnAddrMask)
-{
-  MODIFY_REG(I2Cx->OAR2, I2C_OAR2_OA2 | I2C_OAR2_OA2MSK, OwnAddress2 | OwnAddrMask);
-}
-
-/**
-  * @brief  Enable acknowledge on Own Address2 match address.
-  * @rmtoll OAR2         OA2EN         LL_I2C_EnableOwnAddress2
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
-}
-
-/**
-  * @brief  Disable  acknowledge on Own Address2 match address.
-  * @rmtoll OAR2         OA2EN         LL_I2C_DisableOwnAddress2
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
-}
-
-/**
-  * @brief  Check if Own Address1 acknowledge is enabled or disabled.
-  * @rmtoll OAR2         OA2EN         LL_I2C_IsEnabledOwnAddress2
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Configure the SDA setup, hold time and the SCL high, low period.
-  * @note   This bit can only be programmed when the I2C is disabled (PE = 0).
-  * @rmtoll TIMINGR      TIMINGR       LL_I2C_SetTiming
-  * @param  I2Cx I2C Instance.
-  * @param  Timing This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF.
-  * @note   This parameter is computed with the STM32CubeMX Tool.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_SetTiming(I2C_TypeDef *I2Cx, uint32_t Timing)
-{
-  WRITE_REG(I2Cx->TIMINGR, Timing);
-}
-
-/**
-  * @brief  Get the Timing Prescaler setting.
-  * @rmtoll TIMINGR      PRESC         LL_I2C_GetTimingPrescaler
-  * @param  I2Cx I2C Instance.
-  * @retval Value between Min_Data=0x0 and Max_Data=0xF
-  */
-__STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef *I2Cx)
-{
-  return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_TIMINGR_PRESC_Pos);
-}
-
-/**
-  * @brief  Get the SCL low period setting.
-  * @rmtoll TIMINGR      SCLL          LL_I2C_GetClockLowPeriod
-  * @param  I2Cx I2C Instance.
-  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
-  */
-__STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef *I2Cx)
-{
-  return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_TIMINGR_SCLL_Pos);
-}
-
-/**
-  * @brief  Get the SCL high period setting.
-  * @rmtoll TIMINGR      SCLH          LL_I2C_GetClockHighPeriod
-  * @param  I2Cx I2C Instance.
-  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
-  */
-__STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef *I2Cx)
-{
-  return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_TIMINGR_SCLH_Pos);
-}
-
-/**
-  * @brief  Get the SDA hold time.
-  * @rmtoll TIMINGR      SDADEL        LL_I2C_GetDataHoldTime
-  * @param  I2Cx I2C Instance.
-  * @retval Value between Min_Data=0x0 and Max_Data=0xF
-  */
-__STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef *I2Cx)
-{
-  return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_TIMINGR_SDADEL_Pos);
-}
-
-/**
-  * @brief  Get the SDA setup time.
-  * @rmtoll TIMINGR      SCLDEL        LL_I2C_GetDataSetupTime
-  * @param  I2Cx I2C Instance.
-  * @retval Value between Min_Data=0x0 and Max_Data=0xF
-  */
-__STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(I2C_TypeDef *I2Cx)
-{
-  return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_TIMINGR_SCLDEL_Pos);
-}
-
-/**
-  * @brief  Configure peripheral mode.
-  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @rmtoll CR1          SMBHEN        LL_I2C_SetMode\n
-  *         CR1          SMBDEN        LL_I2C_SetMode
-  * @param  I2Cx I2C Instance.
-  * @param  PeripheralMode This parameter can be one of the following values:
-  *         @arg @ref LL_I2C_MODE_I2C
-  *         @arg @ref LL_I2C_MODE_SMBUS_HOST
-  *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE
-  *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
-{
-  MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN, PeripheralMode);
-}
-
-/**
-  * @brief  Get peripheral mode.
-  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @rmtoll CR1          SMBHEN        LL_I2C_GetMode\n
-  *         CR1          SMBDEN        LL_I2C_GetMode
-  * @param  I2Cx I2C Instance.
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_I2C_MODE_I2C
-  *         @arg @ref LL_I2C_MODE_SMBUS_HOST
-  *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE
-  *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
-  */
-__STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx)
-{
-  return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN));
-}
-
-/**
-  * @brief  Enable SMBus alert (Host or Device mode)
-  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @note   SMBus Device mode:
-  *         - SMBus Alert pin is drived low and
-  *           Alert Response Address Header acknowledge is enabled.
-  *         SMBus Host mode:
-  *         - SMBus Alert pin management is supported.
-  * @rmtoll CR1          ALERTEN       LL_I2C_EnableSMBusAlert
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
-}
-
-/**
-  * @brief  Disable SMBus alert (Host or Device mode)
-  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @note   SMBus Device mode:
-  *         - SMBus Alert pin is not drived (can be used as a standard GPIO) and
-  *           Alert Response Address Header acknowledge is disabled.
-  *         SMBus Host mode:
-  *         - SMBus Alert pin management is not supported.
-  * @rmtoll CR1          ALERTEN       LL_I2C_DisableSMBusAlert
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
-}
-
-/**
-  * @brief  Check if SMBus alert (Host or Device mode) is enabled or disabled.
-  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @rmtoll CR1          ALERTEN       LL_I2C_IsEnabledSMBusAlert
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable SMBus Packet Error Calculation (PEC).
-  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @rmtoll CR1          PECEN         LL_I2C_EnableSMBusPEC
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR1, I2C_CR1_PECEN);
-}
-
-/**
-  * @brief  Disable SMBus Packet Error Calculation (PEC).
-  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @rmtoll CR1          PECEN         LL_I2C_DisableSMBusPEC
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR1, I2C_CR1_PECEN);
-}
-
-/**
-  * @brief  Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
-  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @rmtoll CR1          PECEN         LL_I2C_IsEnabledSMBusPEC
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Configure the SMBus Clock Timeout.
-  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @note   This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB).
-  * @rmtoll TIMEOUTR     TIMEOUTA      LL_I2C_ConfigSMBusTimeout\n
-  *         TIMEOUTR     TIDLE         LL_I2C_ConfigSMBusTimeout\n
-  *         TIMEOUTR     TIMEOUTB      LL_I2C_ConfigSMBusTimeout
-  * @param  I2Cx I2C Instance.
-  * @param  TimeoutA This parameter must be a value between  Min_Data=0 and Max_Data=0xFFF.
-  * @param  TimeoutAMode This parameter can be one of the following values:
-  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
-  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
-  * @param  TimeoutB
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_ConfigSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode,
-                                               uint32_t TimeoutB)
-{
-  MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA | I2C_TIMEOUTR_TIDLE | I2C_TIMEOUTR_TIMEOUTB,
-             TimeoutA | TimeoutAMode | (TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos));
-}
-
-/**
-  * @brief  Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode).
-  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @note   These bits can only be programmed when TimeoutA is disabled.
-  * @rmtoll TIMEOUTR     TIMEOUTA      LL_I2C_SetSMBusTimeoutA
-  * @param  I2Cx I2C Instance.
-  * @param  TimeoutA This parameter must be a value between  Min_Data=0 and Max_Data=0xFFF.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *I2Cx, uint32_t TimeoutA)
-{
-  WRITE_REG(I2Cx->TIMEOUTR, TimeoutA);
-}
-
-/**
-  * @brief  Get the SMBus Clock TimeoutA setting.
-  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @rmtoll TIMEOUTR     TIMEOUTA      LL_I2C_GetSMBusTimeoutA
-  * @param  I2Cx I2C Instance.
-  * @retval Value between Min_Data=0 and Max_Data=0xFFF
-  */
-__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(I2C_TypeDef *I2Cx)
-{
-  return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA));
-}
-
-/**
-  * @brief  Set the SMBus Clock TimeoutA mode.
-  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @note   This bit can only be programmed when TimeoutA is disabled.
-  * @rmtoll TIMEOUTR     TIDLE         LL_I2C_SetSMBusTimeoutAMode
-  * @param  I2Cx I2C Instance.
-  * @param  TimeoutAMode This parameter can be one of the following values:
-  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
-  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t TimeoutAMode)
-{
-  WRITE_REG(I2Cx->TIMEOUTR, TimeoutAMode);
-}
-
-/**
-  * @brief  Get the SMBus Clock TimeoutA mode.
-  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @rmtoll TIMEOUTR     TIDLE         LL_I2C_GetSMBusTimeoutAMode
-  * @param  I2Cx I2C Instance.
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
-  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
-  */
-__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(I2C_TypeDef *I2Cx)
-{
-  return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE));
-}
-
-/**
-  * @brief  Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode).
-  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @note   These bits can only be programmed when TimeoutB is disabled.
-  * @rmtoll TIMEOUTR     TIMEOUTB      LL_I2C_SetSMBusTimeoutB
-  * @param  I2Cx I2C Instance.
-  * @param  TimeoutB This parameter must be a value between  Min_Data=0 and Max_Data=0xFFF.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t TimeoutB)
-{
-  WRITE_REG(I2Cx->TIMEOUTR, TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos);
-}
-
-/**
-  * @brief  Get the SMBus Extended Cumulative Clock TimeoutB setting.
-  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @rmtoll TIMEOUTR     TIMEOUTB      LL_I2C_GetSMBusTimeoutB
-  * @param  I2Cx I2C Instance.
-  * @retval Value between Min_Data=0 and Max_Data=0xFFF
-  */
-__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(I2C_TypeDef *I2Cx)
-{
-  return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_TIMEOUTR_TIMEOUTB_Pos);
-}
-
-/**
-  * @brief  Enable the SMBus Clock Timeout.
-  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @rmtoll TIMEOUTR     TIMOUTEN      LL_I2C_EnableSMBusTimeout\n
-  *         TIMEOUTR     TEXTEN        LL_I2C_EnableSMBusTimeout
-  * @param  I2Cx I2C Instance.
-  * @param  ClockTimeout This parameter can be one of the following values:
-  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA
-  *         @arg @ref LL_I2C_SMBUS_TIMEOUTB
-  *         @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
-{
-  SET_BIT(I2Cx->TIMEOUTR, ClockTimeout);
-}
-
-/**
-  * @brief  Disable the SMBus Clock Timeout.
-  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @rmtoll TIMEOUTR     TIMOUTEN      LL_I2C_DisableSMBusTimeout\n
-  *         TIMEOUTR     TEXTEN        LL_I2C_DisableSMBusTimeout
-  * @param  I2Cx I2C Instance.
-  * @param  ClockTimeout This parameter can be one of the following values:
-  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA
-  *         @arg @ref LL_I2C_SMBUS_TIMEOUTB
-  *         @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
-{
-  CLEAR_BIT(I2Cx->TIMEOUTR, ClockTimeout);
-}
-
-/**
-  * @brief  Check if the SMBus Clock Timeout is enabled or disabled.
-  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @rmtoll TIMEOUTR     TIMOUTEN      LL_I2C_IsEnabledSMBusTimeout\n
-  *         TIMEOUTR     TEXTEN        LL_I2C_IsEnabledSMBusTimeout
-  * @param  I2Cx I2C Instance.
-  * @param  ClockTimeout This parameter can be one of the following values:
-  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA
-  *         @arg @ref LL_I2C_SMBUS_TIMEOUTB
-  *         @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
-{
-  return ((READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == \
-           (ClockTimeout)) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup I2C_LL_EF_IT_Management IT_Management
-  * @{
-  */
-
-/**
-  * @brief  Enable TXIS interrupt.
-  * @rmtoll CR1          TXIE          LL_I2C_EnableIT_TX
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR1, I2C_CR1_TXIE);
-}
-
-/**
-  * @brief  Disable TXIS interrupt.
-  * @rmtoll CR1          TXIE          LL_I2C_DisableIT_TX
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE);
-}
-
-/**
-  * @brief  Check if the TXIS Interrupt is enabled or disabled.
-  * @rmtoll CR1          TXIE          LL_I2C_IsEnabledIT_TX
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable RXNE interrupt.
-  * @rmtoll CR1          RXIE          LL_I2C_EnableIT_RX
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR1, I2C_CR1_RXIE);
-}
-
-/**
-  * @brief  Disable RXNE interrupt.
-  * @rmtoll CR1          RXIE          LL_I2C_DisableIT_RX
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXIE);
-}
-
-/**
-  * @brief  Check if the RXNE Interrupt is enabled or disabled.
-  * @rmtoll CR1          RXIE          LL_I2C_IsEnabledIT_RX
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable Address match interrupt (slave mode only).
-  * @rmtoll CR1          ADDRIE        LL_I2C_EnableIT_ADDR
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableIT_ADDR(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
-}
-
-/**
-  * @brief  Disable Address match interrupt (slave mode only).
-  * @rmtoll CR1          ADDRIE        LL_I2C_DisableIT_ADDR
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableIT_ADDR(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
-}
-
-/**
-  * @brief  Check if Address match interrupt is enabled or disabled.
-  * @rmtoll CR1          ADDRIE        LL_I2C_IsEnabledIT_ADDR
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable Not acknowledge received interrupt.
-  * @rmtoll CR1          NACKIE        LL_I2C_EnableIT_NACK
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableIT_NACK(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
-}
-
-/**
-  * @brief  Disable Not acknowledge received interrupt.
-  * @rmtoll CR1          NACKIE        LL_I2C_DisableIT_NACK
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableIT_NACK(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
-}
-
-/**
-  * @brief  Check if Not acknowledge received interrupt is enabled or disabled.
-  * @rmtoll CR1          NACKIE        LL_I2C_IsEnabledIT_NACK
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable STOP detection interrupt.
-  * @rmtoll CR1          STOPIE        LL_I2C_EnableIT_STOP
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableIT_STOP(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
-}
-
-/**
-  * @brief  Disable STOP detection interrupt.
-  * @rmtoll CR1          STOPIE        LL_I2C_DisableIT_STOP
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableIT_STOP(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
-}
-
-/**
-  * @brief  Check if STOP detection interrupt is enabled or disabled.
-  * @rmtoll CR1          STOPIE        LL_I2C_IsEnabledIT_STOP
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable Transfer Complete interrupt.
-  * @note   Any of these events will generate interrupt :
-  *         Transfer Complete (TC)
-  *         Transfer Complete Reload (TCR)
-  * @rmtoll CR1          TCIE          LL_I2C_EnableIT_TC
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableIT_TC(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR1, I2C_CR1_TCIE);
-}
-
-/**
-  * @brief  Disable Transfer Complete interrupt.
-  * @note   Any of these events will generate interrupt :
-  *         Transfer Complete (TC)
-  *         Transfer Complete Reload (TCR)
-  * @rmtoll CR1          TCIE          LL_I2C_DisableIT_TC
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableIT_TC(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR1, I2C_CR1_TCIE);
-}
-
-/**
-  * @brief  Check if Transfer Complete interrupt is enabled or disabled.
-  * @rmtoll CR1          TCIE          LL_I2C_IsEnabledIT_TC
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable Error interrupts.
-  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @note   Any of these errors will generate interrupt :
-  *         Arbitration Loss (ARLO)
-  *         Bus Error detection (BERR)
-  *         Overrun/Underrun (OVR)
-  *         SMBus Timeout detection (TIMEOUT)
-  *         SMBus PEC error detection (PECERR)
-  *         SMBus Alert pin event detection (ALERT)
-  * @rmtoll CR1          ERRIE         LL_I2C_EnableIT_ERR
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
-}
-
-/**
-  * @brief  Disable Error interrupts.
-  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @note   Any of these errors will generate interrupt :
-  *         Arbitration Loss (ARLO)
-  *         Bus Error detection (BERR)
-  *         Overrun/Underrun (OVR)
-  *         SMBus Timeout detection (TIMEOUT)
-  *         SMBus PEC error detection (PECERR)
-  *         SMBus Alert pin event detection (ALERT)
-  * @rmtoll CR1          ERRIE         LL_I2C_DisableIT_ERR
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
-}
-
-/**
-  * @brief  Check if Error interrupts are enabled or disabled.
-  * @rmtoll CR1          ERRIE         LL_I2C_IsEnabledIT_ERR
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup I2C_LL_EF_FLAG_management FLAG_management
-  * @{
-  */
-
-/**
-  * @brief  Indicate the status of Transmit data register empty flag.
-  * @note   RESET: When next data is written in Transmit data register.
-  *         SET: When Transmit data register is empty.
-  * @rmtoll ISR          TXE           LL_I2C_IsActiveFlag_TXE
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicate the status of Transmit interrupt flag.
-  * @note   RESET: When next data is written in Transmit data register.
-  *         SET: When Transmit data register is empty.
-  * @rmtoll ISR          TXIS          LL_I2C_IsActiveFlag_TXIS
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicate the status of Receive data register not empty flag.
-  * @note   RESET: When Receive data register is read.
-  *         SET: When the received data is copied in Receive data register.
-  * @rmtoll ISR          RXNE          LL_I2C_IsActiveFlag_RXNE
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicate the status of Address matched flag (slave mode).
-  * @note   RESET: Clear default value.
-  *         SET: When the received slave address matched with one of the enabled slave address.
-  * @rmtoll ISR          ADDR          LL_I2C_IsActiveFlag_ADDR
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicate the status of Not Acknowledge received flag.
-  * @note   RESET: Clear default value.
-  *         SET: When a NACK is received after a byte transmission.
-  * @rmtoll ISR          NACKF         LL_I2C_IsActiveFlag_NACK
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicate the status of Stop detection flag.
-  * @note   RESET: Clear default value.
-  *         SET: When a Stop condition is detected.
-  * @rmtoll ISR          STOPF         LL_I2C_IsActiveFlag_STOP
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicate the status of Transfer complete flag (master mode).
-  * @note   RESET: Clear default value.
-  *         SET: When RELOAD=0, AUTOEND=0 and NBYTES date have been transferred.
-  * @rmtoll ISR          TC            LL_I2C_IsActiveFlag_TC
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicate the status of Transfer complete flag (master mode).
-  * @note   RESET: Clear default value.
-  *         SET: When RELOAD=1 and NBYTES date have been transferred.
-  * @rmtoll ISR          TCR           LL_I2C_IsActiveFlag_TCR
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicate the status of Bus error flag.
-  * @note   RESET: Clear default value.
-  *         SET: When a misplaced Start or Stop condition is detected.
-  * @rmtoll ISR          BERR          LL_I2C_IsActiveFlag_BERR
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicate the status of Arbitration lost flag.
-  * @note   RESET: Clear default value.
-  *         SET: When arbitration lost.
-  * @rmtoll ISR          ARLO          LL_I2C_IsActiveFlag_ARLO
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicate the status of Overrun/Underrun flag (slave mode).
-  * @note   RESET: Clear default value.
-  *         SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
-  * @rmtoll ISR          OVR           LL_I2C_IsActiveFlag_OVR
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicate the status of SMBus PEC error flag in reception.
-  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @note   RESET: Clear default value.
-  *         SET: When the received PEC does not match with the PEC register content.
-  * @rmtoll ISR          PECERR        LL_I2C_IsActiveSMBusFlag_PECERR
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicate the status of SMBus Timeout detection flag.
-  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @note   RESET: Clear default value.
-  *         SET: When a timeout or extended clock timeout occurs.
-  * @rmtoll ISR          TIMEOUT       LL_I2C_IsActiveSMBusFlag_TIMEOUT
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicate the status of SMBus alert flag.
-  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @note   RESET: Clear default value.
-  *         SET: When SMBus host configuration, SMBus alert enabled and
-  *              a falling edge event occurs on SMBA pin.
-  * @rmtoll ISR          ALERT         LL_I2C_IsActiveSMBusFlag_ALERT
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicate the status of Bus Busy flag.
-  * @note   RESET: Clear default value.
-  *         SET: When a Start condition is detected.
-  * @rmtoll ISR          BUSY          LL_I2C_IsActiveFlag_BUSY
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear Address Matched flag.
-  * @rmtoll ICR          ADDRCF        LL_I2C_ClearFlag_ADDR
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->ICR, I2C_ICR_ADDRCF);
-}
-
-/**
-  * @brief  Clear Not Acknowledge flag.
-  * @rmtoll ICR          NACKCF        LL_I2C_ClearFlag_NACK
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_ClearFlag_NACK(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->ICR, I2C_ICR_NACKCF);
-}
-
-/**
-  * @brief  Clear Stop detection flag.
-  * @rmtoll ICR          STOPCF        LL_I2C_ClearFlag_STOP
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->ICR, I2C_ICR_STOPCF);
-}
-
-/**
-  * @brief  Clear Transmit data register empty flag (TXE).
-  * @note   This bit can be clear by software in order to flush the transmit data register (TXDR).
-  * @rmtoll ISR          TXE           LL_I2C_ClearFlag_TXE
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_ClearFlag_TXE(I2C_TypeDef *I2Cx)
-{
-  WRITE_REG(I2Cx->ISR, I2C_ISR_TXE);
-}
-
-/**
-  * @brief  Clear Bus error flag.
-  * @rmtoll ICR          BERRCF        LL_I2C_ClearFlag_BERR
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->ICR, I2C_ICR_BERRCF);
-}
-
-/**
-  * @brief  Clear Arbitration lost flag.
-  * @rmtoll ICR          ARLOCF        LL_I2C_ClearFlag_ARLO
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->ICR, I2C_ICR_ARLOCF);
-}
-
-/**
-  * @brief  Clear Overrun/Underrun flag.
-  * @rmtoll ICR          OVRCF         LL_I2C_ClearFlag_OVR
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->ICR, I2C_ICR_OVRCF);
-}
-
-/**
-  * @brief  Clear SMBus PEC error flag.
-  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @rmtoll ICR          PECCF         LL_I2C_ClearSMBusFlag_PECERR
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->ICR, I2C_ICR_PECCF);
-}
-
-/**
-  * @brief  Clear SMBus Timeout detection flag.
-  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @rmtoll ICR          TIMOUTCF      LL_I2C_ClearSMBusFlag_TIMEOUT
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->ICR, I2C_ICR_TIMOUTCF);
-}
-
-/**
-  * @brief  Clear SMBus Alert flag.
-  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @rmtoll ICR          ALERTCF       LL_I2C_ClearSMBusFlag_ALERT
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->ICR, I2C_ICR_ALERTCF);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup I2C_LL_EF_Data_Management Data_Management
-  * @{
-  */
-
-/**
-  * @brief  Enable automatic STOP condition generation (master mode).
-  * @note   Automatic end mode : a STOP condition is automatically sent when NBYTES data are transferred.
-  *         This bit has no effect in slave mode or when RELOAD bit is set.
-  * @rmtoll CR2          AUTOEND       LL_I2C_EnableAutoEndMode
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableAutoEndMode(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
-}
-
-/**
-  * @brief  Disable automatic STOP condition generation (master mode).
-  * @note   Software end mode : TC flag is set when NBYTES data are transferre, stretching SCL low.
-  * @rmtoll CR2          AUTOEND       LL_I2C_DisableAutoEndMode
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableAutoEndMode(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
-}
-
-/**
-  * @brief  Check if automatic STOP condition is enabled or disabled.
-  * @rmtoll CR2          AUTOEND       LL_I2C_IsEnabledAutoEndMode
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable reload mode (master mode).
-  * @note   The transfer is not completed after the NBYTES data transfer, NBYTES will be reloaded when TCR flag is set.
-  * @rmtoll CR2          RELOAD       LL_I2C_EnableReloadMode
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableReloadMode(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
-}
-
-/**
-  * @brief  Disable reload mode (master mode).
-  * @note   The transfer is completed after the NBYTES data transfer(STOP or RESTART will follow).
-  * @rmtoll CR2          RELOAD       LL_I2C_DisableReloadMode
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableReloadMode(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
-}
-
-/**
-  * @brief  Check if reload mode is enabled or disabled.
-  * @rmtoll CR2          RELOAD       LL_I2C_IsEnabledReloadMode
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Configure the number of bytes for transfer.
-  * @note   Changing these bits when START bit is set is not allowed.
-  * @rmtoll CR2          NBYTES           LL_I2C_SetTransferSize
-  * @param  I2Cx I2C Instance.
-  * @param  TransferSize This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t TransferSize)
-{
-  MODIFY_REG(I2Cx->CR2, I2C_CR2_NBYTES, TransferSize << I2C_CR2_NBYTES_Pos);
-}
-
-/**
-  * @brief  Get the number of bytes configured for transfer.
-  * @rmtoll CR2          NBYTES           LL_I2C_GetTransferSize
-  * @param  I2Cx I2C Instance.
-  * @retval Value between Min_Data=0x0 and Max_Data=0xFF
-  */
-__STATIC_INLINE uint32_t LL_I2C_GetTransferSize(I2C_TypeDef *I2Cx)
-{
-  return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_CR2_NBYTES_Pos);
-}
-
-/**
-  * @brief  Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code
-            or next received byte.
-  * @note   Usage in Slave mode only.
-  * @rmtoll CR2          NACK          LL_I2C_AcknowledgeNextData
-  * @param  I2Cx I2C Instance.
-  * @param  TypeAcknowledge This parameter can be one of the following values:
-  *         @arg @ref LL_I2C_ACK
-  *         @arg @ref LL_I2C_NACK
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
-{
-  MODIFY_REG(I2Cx->CR2, I2C_CR2_NACK, TypeAcknowledge);
-}
-
-/**
-  * @brief  Generate a START or RESTART condition
-  * @note   The START bit can be set even if bus is BUSY or I2C is in slave mode.
-  *         This action has no effect when RELOAD is set.
-  * @rmtoll CR2          START           LL_I2C_GenerateStartCondition
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR2, I2C_CR2_START);
-}
-
-/**
-  * @brief  Generate a STOP condition after the current byte transfer (master mode).
-  * @rmtoll CR2          STOP          LL_I2C_GenerateStopCondition
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR2, I2C_CR2_STOP);
-}
-
-/**
-  * @brief  Enable automatic RESTART Read request condition for 10bit address header (master mode).
-  * @note   The master sends the complete 10bit slave address read sequence :
-  *         Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address
-            in Read direction.
-  * @rmtoll CR2          HEAD10R       LL_I2C_EnableAuto10BitRead
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableAuto10BitRead(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
-}
-
-/**
-  * @brief  Disable automatic RESTART Read request condition for 10bit address header (master mode).
-  * @note   The master only sends the first 7 bits of 10bit address in Read direction.
-  * @rmtoll CR2          HEAD10R       LL_I2C_DisableAuto10BitRead
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableAuto10BitRead(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
-}
-
-/**
-  * @brief  Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled.
-  * @rmtoll CR2          HEAD10R       LL_I2C_IsEnabledAuto10BitRead
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Configure the transfer direction (master mode).
-  * @note   Changing these bits when START bit is set is not allowed.
-  * @rmtoll CR2          RD_WRN           LL_I2C_SetTransferRequest
-  * @param  I2Cx I2C Instance.
-  * @param  TransferRequest This parameter can be one of the following values:
-  *         @arg @ref LL_I2C_REQUEST_WRITE
-  *         @arg @ref LL_I2C_REQUEST_READ
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_SetTransferRequest(I2C_TypeDef *I2Cx, uint32_t TransferRequest)
-{
-  MODIFY_REG(I2Cx->CR2, I2C_CR2_RD_WRN, TransferRequest);
-}
-
-/**
-  * @brief  Get the transfer direction requested (master mode).
-  * @rmtoll CR2          RD_WRN           LL_I2C_GetTransferRequest
-  * @param  I2Cx I2C Instance.
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_I2C_REQUEST_WRITE
-  *         @arg @ref LL_I2C_REQUEST_READ
-  */
-__STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(I2C_TypeDef *I2Cx)
-{
-  return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_RD_WRN));
-}
-
-/**
-  * @brief  Configure the slave address for transfer (master mode).
-  * @note   Changing these bits when START bit is set is not allowed.
-  * @rmtoll CR2          SADD           LL_I2C_SetSlaveAddr
-  * @param  I2Cx I2C Instance.
-  * @param  SlaveAddr This parameter must be a value between Min_Data=0x00 and Max_Data=0x3F.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_SetSlaveAddr(I2C_TypeDef *I2Cx, uint32_t SlaveAddr)
-{
-  MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD, SlaveAddr);
-}
-
-/**
-  * @brief  Get the slave address programmed for transfer.
-  * @rmtoll CR2          SADD           LL_I2C_GetSlaveAddr
-  * @param  I2Cx I2C Instance.
-  * @retval Value between Min_Data=0x0 and Max_Data=0x3F
-  */
-__STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx)
-{
-  return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_SADD));
-}
-
-/**
-  * @brief  Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
-  * @rmtoll CR2          SADD          LL_I2C_HandleTransfer\n
-  *         CR2          ADD10         LL_I2C_HandleTransfer\n
-  *         CR2          RD_WRN        LL_I2C_HandleTransfer\n
-  *         CR2          START         LL_I2C_HandleTransfer\n
-  *         CR2          STOP          LL_I2C_HandleTransfer\n
-  *         CR2          RELOAD        LL_I2C_HandleTransfer\n
-  *         CR2          NBYTES        LL_I2C_HandleTransfer\n
-  *         CR2          AUTOEND       LL_I2C_HandleTransfer\n
-  *         CR2          HEAD10R       LL_I2C_HandleTransfer
-  * @param  I2Cx I2C Instance.
-  * @param  SlaveAddr Specifies the slave address to be programmed.
-  * @param  SlaveAddrSize This parameter can be one of the following values:
-  *         @arg @ref LL_I2C_ADDRSLAVE_7BIT
-  *         @arg @ref LL_I2C_ADDRSLAVE_10BIT
-  * @param  TransferSize Specifies the number of bytes to be programmed.
-  *                       This parameter must be a value between Min_Data=0 and Max_Data=255.
-  * @param  EndMode This parameter can be one of the following values:
-  *         @arg @ref LL_I2C_MODE_RELOAD
-  *         @arg @ref LL_I2C_MODE_AUTOEND
-  *         @arg @ref LL_I2C_MODE_SOFTEND
-  *         @arg @ref LL_I2C_MODE_SMBUS_RELOAD
-  *         @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC
-  *         @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC
-  *         @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC
-  *         @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC
-  * @param  Request This parameter can be one of the following values:
-  *         @arg @ref LL_I2C_GENERATE_NOSTARTSTOP
-  *         @arg @ref LL_I2C_GENERATE_STOP
-  *         @arg @ref LL_I2C_GENERATE_START_READ
-  *         @arg @ref LL_I2C_GENERATE_START_WRITE
-  *         @arg @ref LL_I2C_GENERATE_RESTART_7BIT_READ
-  *         @arg @ref LL_I2C_GENERATE_RESTART_7BIT_WRITE
-  *         @arg @ref LL_I2C_GENERATE_RESTART_10BIT_READ
-  *         @arg @ref LL_I2C_GENERATE_RESTART_10BIT_WRITE
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize,
-                                           uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
-{
-  MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 |
-             (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) |
-             I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD |
-             I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R,
-             SlaveAddr | SlaveAddrSize | (TransferSize << I2C_CR2_NBYTES_Pos) | EndMode | Request);
-}
-
-/**
-  * @brief  Indicate the value of transfer direction (slave mode).
-  * @note   RESET: Write transfer, Slave enters in receiver mode.
-  *         SET: Read transfer, Slave enters in transmitter mode.
-  * @rmtoll ISR          DIR           LL_I2C_GetTransferDirection
-  * @param  I2Cx I2C Instance.
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_I2C_DIRECTION_WRITE
-  *         @arg @ref LL_I2C_DIRECTION_READ
-  */
-__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
-{
-  return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_DIR));
-}
-
-/**
-  * @brief  Return the slave matched address.
-  * @rmtoll ISR          ADDCODE       LL_I2C_GetAddressMatchCode
-  * @param  I2Cx I2C Instance.
-  * @retval Value between Min_Data=0x00 and Max_Data=0x3F
-  */
-__STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(I2C_TypeDef *I2Cx)
-{
-  return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_ISR_ADDCODE_Pos << 1);
-}
-
-/**
-  * @brief  Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode).
-  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @note   This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition
-            or an Address Matched is received.
-  *         This bit has no effect when RELOAD bit is set.
-  *         This bit has no effect in device mode when SBC bit is not set.
-  * @rmtoll CR2          PECBYTE       LL_I2C_EnableSMBusPECCompare
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR2, I2C_CR2_PECBYTE);
-}
-
-/**
-  * @brief  Check if the SMBus Packet Error byte internal comparison is requested or not.
-  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @rmtoll CR2          PECBYTE       LL_I2C_IsEnabledSMBusPECCompare
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get the SMBus Packet Error byte calculated.
-  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @rmtoll PECR         PEC           LL_I2C_GetSMBusPEC
-  * @param  I2Cx I2C Instance.
-  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
-  */
-__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
-{
-  return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC));
-}
-
-/**
-  * @brief  Read Receive Data register.
-  * @rmtoll RXDR         RXDATA        LL_I2C_ReceiveData8
-  * @param  I2Cx I2C Instance.
-  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
-  */
-__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx)
-{
-  return (uint8_t)(READ_BIT(I2Cx->RXDR, I2C_RXDR_RXDATA));
-}
-
-/**
-  * @brief  Write in Transmit Data Register .
-  * @rmtoll TXDR         TXDATA        LL_I2C_TransmitData8
-  * @param  I2Cx I2C Instance.
-  * @param  Data Value between Min_Data=0x00 and Max_Data=0xFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
-{
-  WRITE_REG(I2Cx->TXDR, Data);
-}
-
-/**
-  * @}
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions
-  * @{
-  */
-
-ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct);
-ErrorStatus LL_I2C_DeInit(I2C_TypeDef *I2Cx);
-void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
-
-
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* I2C1 || I2C2 || I2C3 || I2C4  || I2C5 */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32H7xx_LL_I2C_H */
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_ll_i2c.h
+  * @author  MCD Application Team
+  * @brief   Header file of I2C LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_LL_I2C_H
+#define STM32H7xx_LL_I2C_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx.h"
+
+/** @addtogroup STM32H7xx_LL_Driver
+  * @{
+  */
+
+#if defined (I2C1) || defined (I2C2) || defined (I2C3) || defined (I2C4) || defined (I2C5)
+
+/** @defgroup I2C_LL I2C
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup I2C_LL_Private_Constants I2C Private Constants
+  * @{
+  */
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup I2C_LL_Private_Macros I2C Private Macros
+  * @{
+  */
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup I2C_LL_ES_INIT I2C Exported Init structure
+  * @{
+  */
+typedef struct
+{
+  uint32_t PeripheralMode;      /*!< Specifies the peripheral mode.
+                                     This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE.
+
+                                     This feature can be modified afterwards using unitary function
+                                     @ref LL_I2C_SetMode(). */
+
+  uint32_t Timing;              /*!< Specifies the SDA setup, hold time and the SCL high, low period values.
+                                     This parameter must be set by referring to the STM32CubeMX Tool and
+                                     the helper macro @ref __LL_I2C_CONVERT_TIMINGS().
+
+                                     This feature can be modified afterwards using unitary function
+                                     @ref LL_I2C_SetTiming(). */
+
+  uint32_t AnalogFilter;        /*!< Enables or disables analog noise filter.
+                                     This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION.
+
+                                     This feature can be modified afterwards using unitary functions
+                                     @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */
+
+  uint32_t DigitalFilter;       /*!< Configures the digital noise filter.
+                                     This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F.
+
+                                     This feature can be modified afterwards using unitary function
+                                     @ref LL_I2C_SetDigitalFilter(). */
+
+  uint32_t OwnAddress1;         /*!< Specifies the device own address 1.
+                                     This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF.
+
+                                     This feature can be modified afterwards using unitary function
+                                     @ref LL_I2C_SetOwnAddress1(). */
+
+  uint32_t TypeAcknowledge;     /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive
+                                     match code or next received byte.
+                                     This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE.
+
+                                     This feature can be modified afterwards using unitary function
+                                     @ref LL_I2C_AcknowledgeNextData(). */
+
+  uint32_t OwnAddrSize;         /*!< Specifies the device own address 1 size (7-bit or 10-bit).
+                                     This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1.
+
+                                     This feature can be modified afterwards using unitary function
+                                     @ref LL_I2C_SetOwnAddress1(). */
+} LL_I2C_InitTypeDef;
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup I2C_LL_Exported_Constants I2C Exported Constants
+  * @{
+  */
+
+/** @defgroup I2C_LL_EC_CLEAR_FLAG Clear Flags Defines
+  * @brief    Flags defines which can be used with LL_I2C_WriteReg function
+  * @{
+  */
+#define LL_I2C_ICR_ADDRCF                   I2C_ICR_ADDRCF          /*!< Address Matched flag   */
+#define LL_I2C_ICR_NACKCF                   I2C_ICR_NACKCF          /*!< Not Acknowledge flag   */
+#define LL_I2C_ICR_STOPCF                   I2C_ICR_STOPCF          /*!< Stop detection flag    */
+#define LL_I2C_ICR_BERRCF                   I2C_ICR_BERRCF          /*!< Bus error flag         */
+#define LL_I2C_ICR_ARLOCF                   I2C_ICR_ARLOCF          /*!< Arbitration Lost flag  */
+#define LL_I2C_ICR_OVRCF                    I2C_ICR_OVRCF           /*!< Overrun/Underrun flag  */
+#define LL_I2C_ICR_PECCF                    I2C_ICR_PECCF           /*!< PEC error flag         */
+#define LL_I2C_ICR_TIMOUTCF                 I2C_ICR_TIMOUTCF        /*!< Timeout detection flag */
+#define LL_I2C_ICR_ALERTCF                  I2C_ICR_ALERTCF         /*!< Alert flag             */
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_I2C_ReadReg function
+  * @{
+  */
+#define LL_I2C_ISR_TXE                      I2C_ISR_TXE             /*!< Transmit data register empty        */
+#define LL_I2C_ISR_TXIS                     I2C_ISR_TXIS            /*!< Transmit interrupt status           */
+#define LL_I2C_ISR_RXNE                     I2C_ISR_RXNE            /*!< Receive data register not empty     */
+#define LL_I2C_ISR_ADDR                     I2C_ISR_ADDR            /*!< Address matched (slave mode)        */
+#define LL_I2C_ISR_NACKF                    I2C_ISR_NACKF           /*!< Not Acknowledge received flag       */
+#define LL_I2C_ISR_STOPF                    I2C_ISR_STOPF           /*!< Stop detection flag                 */
+#define LL_I2C_ISR_TC                       I2C_ISR_TC              /*!< Transfer Complete (master mode)     */
+#define LL_I2C_ISR_TCR                      I2C_ISR_TCR             /*!< Transfer Complete Reload            */
+#define LL_I2C_ISR_BERR                     I2C_ISR_BERR            /*!< Bus error                           */
+#define LL_I2C_ISR_ARLO                     I2C_ISR_ARLO            /*!< Arbitration lost                    */
+#define LL_I2C_ISR_OVR                      I2C_ISR_OVR             /*!< Overrun/Underrun (slave mode)       */
+#define LL_I2C_ISR_PECERR                   I2C_ISR_PECERR          /*!< PEC Error in reception (SMBus mode) */
+#define LL_I2C_ISR_TIMEOUT                  I2C_ISR_TIMEOUT         /*!< Timeout detection flag (SMBus mode) */
+#define LL_I2C_ISR_ALERT                    I2C_ISR_ALERT           /*!< SMBus alert (SMBus mode)            */
+#define LL_I2C_ISR_BUSY                     I2C_ISR_BUSY            /*!< Bus busy                            */
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_I2C_ReadReg and  LL_I2C_WriteReg functions
+  * @{
+  */
+#define LL_I2C_CR1_TXIE                     I2C_CR1_TXIE            /*!< TX Interrupt enable                         */
+#define LL_I2C_CR1_RXIE                     I2C_CR1_RXIE            /*!< RX Interrupt enable                         */
+#define LL_I2C_CR1_ADDRIE                   I2C_CR1_ADDRIE          /*!< Address match Interrupt enable (slave only) */
+#define LL_I2C_CR1_NACKIE                   I2C_CR1_NACKIE          /*!< Not acknowledge received Interrupt enable   */
+#define LL_I2C_CR1_STOPIE                   I2C_CR1_STOPIE          /*!< STOP detection Interrupt enable             */
+#define LL_I2C_CR1_TCIE                     I2C_CR1_TCIE            /*!< Transfer Complete interrupt enable          */
+#define LL_I2C_CR1_ERRIE                    I2C_CR1_ERRIE           /*!< Error interrupts enable                     */
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
+  * @{
+  */
+#define LL_I2C_MODE_I2C                    0x00000000U              /*!< I2C Master or Slave mode                 */
+#define LL_I2C_MODE_SMBUS_HOST             I2C_CR1_SMBHEN           /*!< SMBus Host address acknowledge           */
+#define LL_I2C_MODE_SMBUS_DEVICE           0x00000000U              /*!< SMBus Device default mode
+                                                                         (Default address not acknowledge)        */
+#define LL_I2C_MODE_SMBUS_DEVICE_ARP       I2C_CR1_SMBDEN           /*!< SMBus Device Default address acknowledge */
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection
+  * @{
+  */
+#define LL_I2C_ANALOGFILTER_ENABLE          0x00000000U             /*!< Analog filter is enabled.  */
+#define LL_I2C_ANALOGFILTER_DISABLE         I2C_CR1_ANFOFF          /*!< Analog filter is disabled. */
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_ADDRESSING_MODE Master Addressing Mode
+  * @{
+  */
+#define LL_I2C_ADDRESSING_MODE_7BIT         0x00000000U              /*!< Master operates in 7-bit addressing mode. */
+#define LL_I2C_ADDRESSING_MODE_10BIT        I2C_CR2_ADD10            /*!< Master operates in 10-bit addressing mode.*/
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length
+  * @{
+  */
+#define LL_I2C_OWNADDRESS1_7BIT             0x00000000U             /*!< Own address 1 is a 7-bit address. */
+#define LL_I2C_OWNADDRESS1_10BIT            I2C_OAR1_OA1MODE        /*!< Own address 1 is a 10-bit address.*/
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_OWNADDRESS2 Own Address 2 Masks
+  * @{
+  */
+#define LL_I2C_OWNADDRESS2_NOMASK           I2C_OAR2_OA2NOMASK      /*!< Own Address2 No mask.                 */
+#define LL_I2C_OWNADDRESS2_MASK01           I2C_OAR2_OA2MASK01      /*!< Only Address2 bits[7:2] are compared. */
+#define LL_I2C_OWNADDRESS2_MASK02           I2C_OAR2_OA2MASK02      /*!< Only Address2 bits[7:3] are compared. */
+#define LL_I2C_OWNADDRESS2_MASK03           I2C_OAR2_OA2MASK03      /*!< Only Address2 bits[7:4] are compared. */
+#define LL_I2C_OWNADDRESS2_MASK04           I2C_OAR2_OA2MASK04      /*!< Only Address2 bits[7:5] are compared. */
+#define LL_I2C_OWNADDRESS2_MASK05           I2C_OAR2_OA2MASK05      /*!< Only Address2 bits[7:6] are compared. */
+#define LL_I2C_OWNADDRESS2_MASK06           I2C_OAR2_OA2MASK06      /*!< Only Address2 bits[7] are compared.   */
+#define LL_I2C_OWNADDRESS2_MASK07           I2C_OAR2_OA2MASK07      /*!< No comparison is done.
+                                                                         All Address2 are acknowledged.        */
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation
+  * @{
+  */
+#define LL_I2C_ACK                          0x00000000U              /*!< ACK is sent after current received byte. */
+#define LL_I2C_NACK                         I2C_CR2_NACK             /*!< NACK is sent after current received byte.*/
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_ADDRSLAVE Slave Address Length
+  * @{
+  */
+#define LL_I2C_ADDRSLAVE_7BIT               0x00000000U              /*!< Slave Address in 7-bit. */
+#define LL_I2C_ADDRSLAVE_10BIT              I2C_CR2_ADD10            /*!< Slave Address in 10-bit.*/
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_REQUEST Transfer Request Direction
+  * @{
+  */
+#define LL_I2C_REQUEST_WRITE                0x00000000U              /*!< Master request a write transfer. */
+#define LL_I2C_REQUEST_READ                 I2C_CR2_RD_WRN           /*!< Master request a read transfer.  */
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_MODE Transfer End Mode
+  * @{
+  */
+#define LL_I2C_MODE_RELOAD                  I2C_CR2_RELOAD           /*!< Enable I2C Reload mode.     */
+#define LL_I2C_MODE_AUTOEND                 I2C_CR2_AUTOEND          /*!< Enable I2C Automatic end mode
+                                                                          with no HW PEC comparison.  */
+#define LL_I2C_MODE_SOFTEND                 0x00000000U              /*!< Enable I2C Software end mode
+                                                                          with no HW PEC comparison.  */
+#define LL_I2C_MODE_SMBUS_RELOAD            LL_I2C_MODE_RELOAD       /*!< Enable SMBUS Automatic end mode
+                                                                          with HW PEC comparison.     */
+#define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC    LL_I2C_MODE_AUTOEND      /*!< Enable SMBUS Automatic end mode
+                                                                          with HW PEC comparison.     */
+#define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC    LL_I2C_MODE_SOFTEND      /*!< Enable SMBUS Software end mode
+                                                                          with HW PEC comparison.     */
+#define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC  (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE)
+/*!< Enable SMBUS Automatic end mode with HW PEC comparison.   */
+#define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC  (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE)
+/*!< Enable SMBUS Software end mode with HW PEC comparison.    */
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation
+  * @{
+  */
+#define LL_I2C_GENERATE_NOSTARTSTOP         0x00000000U
+/*!< Don't Generate Stop and Start condition. */
+#define LL_I2C_GENERATE_STOP                (uint32_t)(0x80000000U | I2C_CR2_STOP)
+/*!< Generate Stop condition (Size should be set to 0).      */
+#define LL_I2C_GENERATE_START_READ          (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
+/*!< Generate Start for read request. */
+#define LL_I2C_GENERATE_START_WRITE         (uint32_t)(0x80000000U | I2C_CR2_START)
+/*!< Generate Start for write request. */
+#define LL_I2C_GENERATE_RESTART_7BIT_READ   (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
+/*!< Generate Restart for read request, slave 7Bit address.  */
+#define LL_I2C_GENERATE_RESTART_7BIT_WRITE  (uint32_t)(0x80000000U | I2C_CR2_START)
+/*!< Generate Restart for write request, slave 7Bit address. */
+#define LL_I2C_GENERATE_RESTART_10BIT_READ  (uint32_t)(0x80000000U | I2C_CR2_START | \
+                                                       I2C_CR2_RD_WRN | I2C_CR2_HEAD10R)
+/*!< Generate Restart for read request, slave 10Bit address. */
+#define LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
+/*!< Generate Restart for write request, slave 10Bit address.*/
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_DIRECTION Read Write Direction
+  * @{
+  */
+#define LL_I2C_DIRECTION_WRITE              0x00000000U              /*!< Write transfer request by master,
+                                                                          slave enters receiver mode.  */
+#define LL_I2C_DIRECTION_READ               I2C_ISR_DIR              /*!< Read transfer request by master,
+                                                                          slave enters transmitter mode.*/
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_DMA_REG_DATA DMA Register Data
+  * @{
+  */
+#define LL_I2C_DMA_REG_DATA_TRANSMIT        0x00000000U              /*!< Get address of data register used for
+                                                                          transmission */
+#define LL_I2C_DMA_REG_DATA_RECEIVE         0x00000001U              /*!< Get address of data register used for
+                                                                          reception */
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus TimeoutA Mode SCL SDA Timeout
+  * @{
+  */
+#define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW      0x00000000U          /*!< TimeoutA is used to detect
+                                                                          SCL low level timeout.              */
+#define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE   /*!< TimeoutA is used to detect
+                                                                          both SCL and SDA high level timeout.*/
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_SMBUS_TIMEOUT_SELECTION SMBus Timeout Selection
+  * @{
+  */
+#define LL_I2C_SMBUS_TIMEOUTA               I2C_TIMEOUTR_TIMOUTEN                 /*!< TimeoutA enable bit          */
+#define LL_I2C_SMBUS_TIMEOUTB               I2C_TIMEOUTR_TEXTEN                   /*!< TimeoutB (extended clock)
+                                                                                       enable bit                   */
+#define LL_I2C_SMBUS_ALL_TIMEOUT            (uint32_t)(I2C_TIMEOUTR_TIMOUTEN | \
+                                                       I2C_TIMEOUTR_TEXTEN)       /*!< TimeoutA and TimeoutB
+(extended clock) enable bits */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup I2C_LL_Exported_Macros I2C Exported Macros
+  * @{
+  */
+
+/** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in I2C register
+  * @param  __INSTANCE__ I2C Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in I2C register
+  * @param  __INSTANCE__ I2C Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EM_CONVERT_TIMINGS Convert SDA SCL timings
+  * @{
+  */
+/**
+  * @brief  Configure the SDA setup, hold time and the SCL high, low period.
+  * @param  __PRESCALER__ This parameter must be a value between  Min_Data=0 and Max_Data=0xF.
+  * @param  __SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF.
+                           (tscldel = (SCLDEL+1)xtpresc)
+  * @param  __HOLD_TIME__  This parameter must be a value between Min_Data=0 and Max_Data=0xF.
+                           (tsdadel = SDADELxtpresc)
+  * @param  __SCLH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF.
+                            (tsclh = (SCLH+1)xtpresc)
+  * @param  __SCLL_PERIOD__ This parameter must be a value between  Min_Data=0 and Max_Data=0xFF.
+                            (tscll = (SCLL+1)xtpresc)
+  * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
+  */
+#define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __SETUP_TIME__, __HOLD_TIME__, __SCLH_PERIOD__, __SCLL_PERIOD__) \
+  ((((uint32_t)(__PRESCALER__)    << I2C_TIMINGR_PRESC_Pos)  & I2C_TIMINGR_PRESC)   | \
+   (((uint32_t)(__SETUP_TIME__)   << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL)  | \
+   (((uint32_t)(__HOLD_TIME__)    << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL)  | \
+   (((uint32_t)(__SCLH_PERIOD__)  << I2C_TIMINGR_SCLH_Pos)   & I2C_TIMINGR_SCLH)    | \
+   (((uint32_t)(__SCLL_PERIOD__)  << I2C_TIMINGR_SCLL_Pos)   & I2C_TIMINGR_SCLL))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup I2C_LL_Exported_Functions I2C Exported Functions
+  * @{
+  */
+
+/** @defgroup I2C_LL_EF_Configuration Configuration
+  * @{
+  */
+
+/**
+  * @brief  Enable I2C peripheral (PE = 1).
+  * @rmtoll CR1          PE            LL_I2C_Enable
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_PE);
+}
+
+/**
+  * @brief  Disable I2C peripheral (PE = 0).
+  * @note   When PE = 0, the I2C SCL and SDA lines are released.
+  *         Internal state machines and status bits are put back to their reset value.
+  *         When cleared, PE must be kept low for at least 3 APB clock cycles.
+  * @rmtoll CR1          PE            LL_I2C_Disable
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE);
+}
+
+/**
+  * @brief  Check if the I2C peripheral is enabled or disabled.
+  * @rmtoll CR1          PE            LL_I2C_IsEnabled
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Configure Noise Filters (Analog and Digital).
+  * @note   If the analog filter is also enabled, the digital filter is added to analog filter.
+  *         The filters can only be programmed when the I2C is disabled (PE = 0).
+  * @rmtoll CR1          ANFOFF        LL_I2C_ConfigFilters\n
+  *         CR1          DNF           LL_I2C_ConfigFilters
+  * @param  I2Cx I2C Instance.
+  * @param  AnalogFilter This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_ANALOGFILTER_ENABLE
+  *         @arg @ref LL_I2C_ANALOGFILTER_DISABLE
+  * @param  DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled)
+                          and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
+  *         This parameter is used to configure the digital noise filter on SDA and SCL input.
+  *         The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter)
+{
+  MODIFY_REG(I2Cx->CR1, I2C_CR1_ANFOFF | I2C_CR1_DNF, AnalogFilter | (DigitalFilter << I2C_CR1_DNF_Pos));
+}
+
+/**
+  * @brief  Configure Digital Noise Filter.
+  * @note   If the analog filter is also enabled, the digital filter is added to analog filter.
+  *         This filter can only be programmed when the I2C is disabled (PE = 0).
+  * @rmtoll CR1          DNF           LL_I2C_SetDigitalFilter
+  * @param  I2Cx I2C Instance.
+  * @param  DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled)
+                          and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
+  *         This parameter is used to configure the digital noise filter on SDA and SCL input.
+  *         The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t DigitalFilter)
+{
+  MODIFY_REG(I2Cx->CR1, I2C_CR1_DNF, DigitalFilter << I2C_CR1_DNF_Pos);
+}
+
+/**
+  * @brief  Get the current Digital Noise Filter configuration.
+  * @rmtoll CR1          DNF           LL_I2C_GetDigitalFilter
+  * @param  I2Cx I2C Instance.
+  * @retval Value between Min_Data=0x0 and Max_Data=0xF
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_CR1_DNF_Pos);
+}
+
+/**
+  * @brief  Enable Analog Noise Filter.
+  * @note   This filter can only be programmed when the I2C is disabled (PE = 0).
+  * @rmtoll CR1          ANFOFF        LL_I2C_EnableAnalogFilter
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableAnalogFilter(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
+}
+
+/**
+  * @brief  Disable Analog Noise Filter.
+  * @note   This filter can only be programmed when the I2C is disabled (PE = 0).
+  * @rmtoll CR1          ANFOFF        LL_I2C_DisableAnalogFilter
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
+}
+
+/**
+  * @brief  Check if Analog Noise Filter is enabled or disabled.
+  * @rmtoll CR1          ANFOFF        LL_I2C_IsEnabledAnalogFilter
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable DMA transmission requests.
+  * @rmtoll CR1          TXDMAEN       LL_I2C_EnableDMAReq_TX
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
+}
+
+/**
+  * @brief  Disable DMA transmission requests.
+  * @rmtoll CR1          TXDMAEN       LL_I2C_DisableDMAReq_TX
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
+}
+
+/**
+  * @brief  Check if DMA transmission requests are enabled or disabled.
+  * @rmtoll CR1          TXDMAEN       LL_I2C_IsEnabledDMAReq_TX
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable DMA reception requests.
+  * @rmtoll CR1          RXDMAEN       LL_I2C_EnableDMAReq_RX
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
+}
+
+/**
+  * @brief  Disable DMA reception requests.
+  * @rmtoll CR1          RXDMAEN       LL_I2C_DisableDMAReq_RX
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
+}
+
+/**
+  * @brief  Check if DMA reception requests are enabled or disabled.
+  * @rmtoll CR1          RXDMAEN       LL_I2C_IsEnabledDMAReq_RX
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get the data register address used for DMA transfer
+  * @rmtoll TXDR         TXDATA        LL_I2C_DMA_GetRegAddr\n
+  *         RXDR         RXDATA        LL_I2C_DMA_GetRegAddr
+  * @param  I2Cx I2C Instance
+  * @param  Direction This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_DMA_REG_DATA_TRANSMIT
+  *         @arg @ref LL_I2C_DMA_REG_DATA_RECEIVE
+  * @retval Address of data register
+  */
+__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx, uint32_t Direction)
+{
+  uint32_t data_reg_addr;
+
+  if (Direction == LL_I2C_DMA_REG_DATA_TRANSMIT)
+  {
+    /* return address of TXDR register */
+    data_reg_addr = (uint32_t) &(I2Cx->TXDR);
+  }
+  else
+  {
+    /* return address of RXDR register */
+    data_reg_addr = (uint32_t) &(I2Cx->RXDR);
+  }
+
+  return data_reg_addr;
+}
+
+/**
+  * @brief  Enable Clock stretching.
+  * @note   This bit can only be programmed when the I2C is disabled (PE = 0).
+  * @rmtoll CR1          NOSTRETCH     LL_I2C_EnableClockStretching
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
+}
+
+/**
+  * @brief  Disable Clock stretching.
+  * @note   This bit can only be programmed when the I2C is disabled (PE = 0).
+  * @rmtoll CR1          NOSTRETCH     LL_I2C_DisableClockStretching
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
+}
+
+/**
+  * @brief  Check if Clock stretching is enabled or disabled.
+  * @rmtoll CR1          NOSTRETCH     LL_I2C_IsEnabledClockStretching
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable hardware byte control in slave mode.
+  * @rmtoll CR1          SBC           LL_I2C_EnableSlaveByteControl
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableSlaveByteControl(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_SBC);
+}
+
+/**
+  * @brief  Disable hardware byte control in slave mode.
+  * @rmtoll CR1          SBC           LL_I2C_DisableSlaveByteControl
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableSlaveByteControl(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_SBC);
+}
+
+/**
+  * @brief  Check if hardware byte control in slave mode is enabled or disabled.
+  * @rmtoll CR1          SBC           LL_I2C_IsEnabledSlaveByteControl
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Wakeup from STOP.
+  * @note   The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
+  *         WakeUpFromStop feature is supported by the I2Cx Instance.
+  * @note   This bit can only be programmed when Digital Filter is disabled.
+  * @rmtoll CR1          WUPEN         LL_I2C_EnableWakeUpFromStop
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableWakeUpFromStop(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
+}
+
+/**
+  * @brief  Disable Wakeup from STOP.
+  * @note   The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
+  *         WakeUpFromStop feature is supported by the I2Cx Instance.
+  * @rmtoll CR1          WUPEN         LL_I2C_DisableWakeUpFromStop
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableWakeUpFromStop(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
+}
+
+/**
+  * @brief  Check if Wakeup from STOP is enabled or disabled.
+  * @note   The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
+  *         WakeUpFromStop feature is supported by the I2Cx Instance.
+  * @rmtoll CR1          WUPEN         LL_I2C_IsEnabledWakeUpFromStop
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->CR1, I2C_CR1_WUPEN) == (I2C_CR1_WUPEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable General Call.
+  * @note   When enabled the Address 0x00 is ACKed.
+  * @rmtoll CR1          GCEN          LL_I2C_EnableGeneralCall
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_GCEN);
+}
+
+/**
+  * @brief  Disable General Call.
+  * @note   When disabled the Address 0x00 is NACKed.
+  * @rmtoll CR1          GCEN          LL_I2C_DisableGeneralCall
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_GCEN);
+}
+
+/**
+  * @brief  Check if General Call is enabled or disabled.
+  * @rmtoll CR1          GCEN          LL_I2C_IsEnabledGeneralCall
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Configure the Master to operate in 7-bit or 10-bit addressing mode.
+  * @note   Changing this bit is not allowed, when the START bit is set.
+  * @rmtoll CR2          ADD10         LL_I2C_SetMasterAddressingMode
+  * @param  I2Cx I2C Instance.
+  * @param  AddressingMode This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
+  *         @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_SetMasterAddressingMode(I2C_TypeDef *I2Cx, uint32_t AddressingMode)
+{
+  MODIFY_REG(I2Cx->CR2, I2C_CR2_ADD10, AddressingMode);
+}
+
+/**
+  * @brief  Get the Master addressing mode.
+  * @rmtoll CR2          ADD10         LL_I2C_GetMasterAddressingMode
+  * @param  I2Cx I2C Instance.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
+  *         @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_ADD10));
+}
+
+/**
+  * @brief  Set the Own Address1.
+  * @rmtoll OAR1         OA1           LL_I2C_SetOwnAddress1\n
+  *         OAR1         OA1MODE       LL_I2C_SetOwnAddress1
+  * @param  I2Cx I2C Instance.
+  * @param  OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.
+  * @param  OwnAddrSize This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_OWNADDRESS1_7BIT
+  *         @arg @ref LL_I2C_OWNADDRESS1_10BIT
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
+{
+  MODIFY_REG(I2Cx->OAR1, I2C_OAR1_OA1 | I2C_OAR1_OA1MODE, OwnAddress1 | OwnAddrSize);
+}
+
+/**
+  * @brief  Enable acknowledge on Own Address1 match address.
+  * @rmtoll OAR1         OA1EN         LL_I2C_EnableOwnAddress1
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableOwnAddress1(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
+}
+
+/**
+  * @brief  Disable acknowledge on Own Address1 match address.
+  * @rmtoll OAR1         OA1EN         LL_I2C_DisableOwnAddress1
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableOwnAddress1(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
+}
+
+/**
+  * @brief  Check if Own Address1 acknowledge is enabled or disabled.
+  * @rmtoll OAR1         OA1EN         LL_I2C_IsEnabledOwnAddress1
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the 7bits Own Address2.
+  * @note   This action has no effect if own address2 is enabled.
+  * @rmtoll OAR2         OA2           LL_I2C_SetOwnAddress2\n
+  *         OAR2         OA2MSK        LL_I2C_SetOwnAddress2
+  * @param  I2Cx I2C Instance.
+  * @param  OwnAddress2 Value between Min_Data=0 and Max_Data=0x7F.
+  * @param  OwnAddrMask This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_OWNADDRESS2_NOMASK
+  *         @arg @ref LL_I2C_OWNADDRESS2_MASK01
+  *         @arg @ref LL_I2C_OWNADDRESS2_MASK02
+  *         @arg @ref LL_I2C_OWNADDRESS2_MASK03
+  *         @arg @ref LL_I2C_OWNADDRESS2_MASK04
+  *         @arg @ref LL_I2C_OWNADDRESS2_MASK05
+  *         @arg @ref LL_I2C_OWNADDRESS2_MASK06
+  *         @arg @ref LL_I2C_OWNADDRESS2_MASK07
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2, uint32_t OwnAddrMask)
+{
+  MODIFY_REG(I2Cx->OAR2, I2C_OAR2_OA2 | I2C_OAR2_OA2MSK, OwnAddress2 | OwnAddrMask);
+}
+
+/**
+  * @brief  Enable acknowledge on Own Address2 match address.
+  * @rmtoll OAR2         OA2EN         LL_I2C_EnableOwnAddress2
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
+}
+
+/**
+  * @brief  Disable  acknowledge on Own Address2 match address.
+  * @rmtoll OAR2         OA2EN         LL_I2C_DisableOwnAddress2
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
+}
+
+/**
+  * @brief  Check if Own Address1 acknowledge is enabled or disabled.
+  * @rmtoll OAR2         OA2EN         LL_I2C_IsEnabledOwnAddress2
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Configure the SDA setup, hold time and the SCL high, low period.
+  * @note   This bit can only be programmed when the I2C is disabled (PE = 0).
+  * @rmtoll TIMINGR      TIMINGR       LL_I2C_SetTiming
+  * @param  I2Cx I2C Instance.
+  * @param  Timing This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF.
+  * @note   This parameter is computed with the STM32CubeMX Tool.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_SetTiming(I2C_TypeDef *I2Cx, uint32_t Timing)
+{
+  WRITE_REG(I2Cx->TIMINGR, Timing);
+}
+
+/**
+  * @brief  Get the Timing Prescaler setting.
+  * @rmtoll TIMINGR      PRESC         LL_I2C_GetTimingPrescaler
+  * @param  I2Cx I2C Instance.
+  * @retval Value between Min_Data=0x0 and Max_Data=0xF
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_TIMINGR_PRESC_Pos);
+}
+
+/**
+  * @brief  Get the SCL low period setting.
+  * @rmtoll TIMINGR      SCLL          LL_I2C_GetClockLowPeriod
+  * @param  I2Cx I2C Instance.
+  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_TIMINGR_SCLL_Pos);
+}
+
+/**
+  * @brief  Get the SCL high period setting.
+  * @rmtoll TIMINGR      SCLH          LL_I2C_GetClockHighPeriod
+  * @param  I2Cx I2C Instance.
+  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_TIMINGR_SCLH_Pos);
+}
+
+/**
+  * @brief  Get the SDA hold time.
+  * @rmtoll TIMINGR      SDADEL        LL_I2C_GetDataHoldTime
+  * @param  I2Cx I2C Instance.
+  * @retval Value between Min_Data=0x0 and Max_Data=0xF
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_TIMINGR_SDADEL_Pos);
+}
+
+/**
+  * @brief  Get the SDA setup time.
+  * @rmtoll TIMINGR      SCLDEL        LL_I2C_GetDataSetupTime
+  * @param  I2Cx I2C Instance.
+  * @retval Value between Min_Data=0x0 and Max_Data=0xF
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_TIMINGR_SCLDEL_Pos);
+}
+
+/**
+  * @brief  Configure peripheral mode.
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll CR1          SMBHEN        LL_I2C_SetMode\n
+  *         CR1          SMBDEN        LL_I2C_SetMode
+  * @param  I2Cx I2C Instance.
+  * @param  PeripheralMode This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_MODE_I2C
+  *         @arg @ref LL_I2C_MODE_SMBUS_HOST
+  *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE
+  *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
+{
+  MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN, PeripheralMode);
+}
+
+/**
+  * @brief  Get peripheral mode.
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll CR1          SMBHEN        LL_I2C_GetMode\n
+  *         CR1          SMBDEN        LL_I2C_GetMode
+  * @param  I2Cx I2C Instance.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_I2C_MODE_I2C
+  *         @arg @ref LL_I2C_MODE_SMBUS_HOST
+  *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE
+  *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN));
+}
+
+/**
+  * @brief  Enable SMBus alert (Host or Device mode)
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @note   SMBus Device mode:
+  *         - SMBus Alert pin is drived low and
+  *           Alert Response Address Header acknowledge is enabled.
+  *         SMBus Host mode:
+  *         - SMBus Alert pin management is supported.
+  * @rmtoll CR1          ALERTEN       LL_I2C_EnableSMBusAlert
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
+}
+
+/**
+  * @brief  Disable SMBus alert (Host or Device mode)
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @note   SMBus Device mode:
+  *         - SMBus Alert pin is not drived (can be used as a standard GPIO) and
+  *           Alert Response Address Header acknowledge is disabled.
+  *         SMBus Host mode:
+  *         - SMBus Alert pin management is not supported.
+  * @rmtoll CR1          ALERTEN       LL_I2C_DisableSMBusAlert
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
+}
+
+/**
+  * @brief  Check if SMBus alert (Host or Device mode) is enabled or disabled.
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll CR1          ALERTEN       LL_I2C_IsEnabledSMBusAlert
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable SMBus Packet Error Calculation (PEC).
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll CR1          PECEN         LL_I2C_EnableSMBusPEC
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_PECEN);
+}
+
+/**
+  * @brief  Disable SMBus Packet Error Calculation (PEC).
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll CR1          PECEN         LL_I2C_DisableSMBusPEC
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_PECEN);
+}
+
+/**
+  * @brief  Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll CR1          PECEN         LL_I2C_IsEnabledSMBusPEC
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Configure the SMBus Clock Timeout.
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @note   This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB).
+  * @rmtoll TIMEOUTR     TIMEOUTA      LL_I2C_ConfigSMBusTimeout\n
+  *         TIMEOUTR     TIDLE         LL_I2C_ConfigSMBusTimeout\n
+  *         TIMEOUTR     TIMEOUTB      LL_I2C_ConfigSMBusTimeout
+  * @param  I2Cx I2C Instance.
+  * @param  TimeoutA This parameter must be a value between  Min_Data=0 and Max_Data=0xFFF.
+  * @param  TimeoutAMode This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
+  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
+  * @param  TimeoutB
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_ConfigSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode,
+                                               uint32_t TimeoutB)
+{
+  MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA | I2C_TIMEOUTR_TIDLE | I2C_TIMEOUTR_TIMEOUTB,
+             TimeoutA | TimeoutAMode | (TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos));
+}
+
+/**
+  * @brief  Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode).
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @note   These bits can only be programmed when TimeoutA is disabled.
+  * @rmtoll TIMEOUTR     TIMEOUTA      LL_I2C_SetSMBusTimeoutA
+  * @param  I2Cx I2C Instance.
+  * @param  TimeoutA This parameter must be a value between  Min_Data=0 and Max_Data=0xFFF.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *I2Cx, uint32_t TimeoutA)
+{
+  WRITE_REG(I2Cx->TIMEOUTR, TimeoutA);
+}
+
+/**
+  * @brief  Get the SMBus Clock TimeoutA setting.
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll TIMEOUTR     TIMEOUTA      LL_I2C_GetSMBusTimeoutA
+  * @param  I2Cx I2C Instance.
+  * @retval Value between Min_Data=0 and Max_Data=0xFFF
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA));
+}
+
+/**
+  * @brief  Set the SMBus Clock TimeoutA mode.
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @note   This bit can only be programmed when TimeoutA is disabled.
+  * @rmtoll TIMEOUTR     TIDLE         LL_I2C_SetSMBusTimeoutAMode
+  * @param  I2Cx I2C Instance.
+  * @param  TimeoutAMode This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
+  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t TimeoutAMode)
+{
+  WRITE_REG(I2Cx->TIMEOUTR, TimeoutAMode);
+}
+
+/**
+  * @brief  Get the SMBus Clock TimeoutA mode.
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll TIMEOUTR     TIDLE         LL_I2C_GetSMBusTimeoutAMode
+  * @param  I2Cx I2C Instance.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
+  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE));
+}
+
+/**
+  * @brief  Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode).
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @note   These bits can only be programmed when TimeoutB is disabled.
+  * @rmtoll TIMEOUTR     TIMEOUTB      LL_I2C_SetSMBusTimeoutB
+  * @param  I2Cx I2C Instance.
+  * @param  TimeoutB This parameter must be a value between  Min_Data=0 and Max_Data=0xFFF.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t TimeoutB)
+{
+  WRITE_REG(I2Cx->TIMEOUTR, TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos);
+}
+
+/**
+  * @brief  Get the SMBus Extended Cumulative Clock TimeoutB setting.
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll TIMEOUTR     TIMEOUTB      LL_I2C_GetSMBusTimeoutB
+  * @param  I2Cx I2C Instance.
+  * @retval Value between Min_Data=0 and Max_Data=0xFFF
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_TIMEOUTR_TIMEOUTB_Pos);
+}
+
+/**
+  * @brief  Enable the SMBus Clock Timeout.
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll TIMEOUTR     TIMOUTEN      LL_I2C_EnableSMBusTimeout\n
+  *         TIMEOUTR     TEXTEN        LL_I2C_EnableSMBusTimeout
+  * @param  I2Cx I2C Instance.
+  * @param  ClockTimeout This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA
+  *         @arg @ref LL_I2C_SMBUS_TIMEOUTB
+  *         @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
+{
+  SET_BIT(I2Cx->TIMEOUTR, ClockTimeout);
+}
+
+/**
+  * @brief  Disable the SMBus Clock Timeout.
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll TIMEOUTR     TIMOUTEN      LL_I2C_DisableSMBusTimeout\n
+  *         TIMEOUTR     TEXTEN        LL_I2C_DisableSMBusTimeout
+  * @param  I2Cx I2C Instance.
+  * @param  ClockTimeout This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA
+  *         @arg @ref LL_I2C_SMBUS_TIMEOUTB
+  *         @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
+{
+  CLEAR_BIT(I2Cx->TIMEOUTR, ClockTimeout);
+}
+
+/**
+  * @brief  Check if the SMBus Clock Timeout is enabled or disabled.
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll TIMEOUTR     TIMOUTEN      LL_I2C_IsEnabledSMBusTimeout\n
+  *         TIMEOUTR     TEXTEN        LL_I2C_IsEnabledSMBusTimeout
+  * @param  I2Cx I2C Instance.
+  * @param  ClockTimeout This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA
+  *         @arg @ref LL_I2C_SMBUS_TIMEOUTB
+  *         @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
+{
+  return ((READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == \
+           (ClockTimeout)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EF_IT_Management IT_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable TXIS interrupt.
+  * @rmtoll CR1          TXIE          LL_I2C_EnableIT_TX
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_TXIE);
+}
+
+/**
+  * @brief  Disable TXIS interrupt.
+  * @rmtoll CR1          TXIE          LL_I2C_DisableIT_TX
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE);
+}
+
+/**
+  * @brief  Check if the TXIS Interrupt is enabled or disabled.
+  * @rmtoll CR1          TXIE          LL_I2C_IsEnabledIT_TX
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable RXNE interrupt.
+  * @rmtoll CR1          RXIE          LL_I2C_EnableIT_RX
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_RXIE);
+}
+
+/**
+  * @brief  Disable RXNE interrupt.
+  * @rmtoll CR1          RXIE          LL_I2C_DisableIT_RX
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXIE);
+}
+
+/**
+  * @brief  Check if the RXNE Interrupt is enabled or disabled.
+  * @rmtoll CR1          RXIE          LL_I2C_IsEnabledIT_RX
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Address match interrupt (slave mode only).
+  * @rmtoll CR1          ADDRIE        LL_I2C_EnableIT_ADDR
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableIT_ADDR(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
+}
+
+/**
+  * @brief  Disable Address match interrupt (slave mode only).
+  * @rmtoll CR1          ADDRIE        LL_I2C_DisableIT_ADDR
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableIT_ADDR(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
+}
+
+/**
+  * @brief  Check if Address match interrupt is enabled or disabled.
+  * @rmtoll CR1          ADDRIE        LL_I2C_IsEnabledIT_ADDR
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Not acknowledge received interrupt.
+  * @rmtoll CR1          NACKIE        LL_I2C_EnableIT_NACK
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableIT_NACK(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
+}
+
+/**
+  * @brief  Disable Not acknowledge received interrupt.
+  * @rmtoll CR1          NACKIE        LL_I2C_DisableIT_NACK
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableIT_NACK(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
+}
+
+/**
+  * @brief  Check if Not acknowledge received interrupt is enabled or disabled.
+  * @rmtoll CR1          NACKIE        LL_I2C_IsEnabledIT_NACK
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable STOP detection interrupt.
+  * @rmtoll CR1          STOPIE        LL_I2C_EnableIT_STOP
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableIT_STOP(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
+}
+
+/**
+  * @brief  Disable STOP detection interrupt.
+  * @rmtoll CR1          STOPIE        LL_I2C_DisableIT_STOP
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableIT_STOP(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
+}
+
+/**
+  * @brief  Check if STOP detection interrupt is enabled or disabled.
+  * @rmtoll CR1          STOPIE        LL_I2C_IsEnabledIT_STOP
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Transfer Complete interrupt.
+  * @note   Any of these events will generate interrupt :
+  *         Transfer Complete (TC)
+  *         Transfer Complete Reload (TCR)
+  * @rmtoll CR1          TCIE          LL_I2C_EnableIT_TC
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableIT_TC(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_TCIE);
+}
+
+/**
+  * @brief  Disable Transfer Complete interrupt.
+  * @note   Any of these events will generate interrupt :
+  *         Transfer Complete (TC)
+  *         Transfer Complete Reload (TCR)
+  * @rmtoll CR1          TCIE          LL_I2C_DisableIT_TC
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableIT_TC(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_TCIE);
+}
+
+/**
+  * @brief  Check if Transfer Complete interrupt is enabled or disabled.
+  * @rmtoll CR1          TCIE          LL_I2C_IsEnabledIT_TC
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Error interrupts.
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @note   Any of these errors will generate interrupt :
+  *         Arbitration Loss (ARLO)
+  *         Bus Error detection (BERR)
+  *         Overrun/Underrun (OVR)
+  *         SMBus Timeout detection (TIMEOUT)
+  *         SMBus PEC error detection (PECERR)
+  *         SMBus Alert pin event detection (ALERT)
+  * @rmtoll CR1          ERRIE         LL_I2C_EnableIT_ERR
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
+}
+
+/**
+  * @brief  Disable Error interrupts.
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @note   Any of these errors will generate interrupt :
+  *         Arbitration Loss (ARLO)
+  *         Bus Error detection (BERR)
+  *         Overrun/Underrun (OVR)
+  *         SMBus Timeout detection (TIMEOUT)
+  *         SMBus PEC error detection (PECERR)
+  *         SMBus Alert pin event detection (ALERT)
+  * @rmtoll CR1          ERRIE         LL_I2C_DisableIT_ERR
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
+}
+
+/**
+  * @brief  Check if Error interrupts are enabled or disabled.
+  * @rmtoll CR1          ERRIE         LL_I2C_IsEnabledIT_ERR
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EF_FLAG_management FLAG_management
+  * @{
+  */
+
+/**
+  * @brief  Indicate the status of Transmit data register empty flag.
+  * @note   RESET: When next data is written in Transmit data register.
+  *         SET: When Transmit data register is empty.
+  * @rmtoll ISR          TXE           LL_I2C_IsActiveFlag_TXE
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate the status of Transmit interrupt flag.
+  * @note   RESET: When next data is written in Transmit data register.
+  *         SET: When Transmit data register is empty.
+  * @rmtoll ISR          TXIS          LL_I2C_IsActiveFlag_TXIS
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate the status of Receive data register not empty flag.
+  * @note   RESET: When Receive data register is read.
+  *         SET: When the received data is copied in Receive data register.
+  * @rmtoll ISR          RXNE          LL_I2C_IsActiveFlag_RXNE
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate the status of Address matched flag (slave mode).
+  * @note   RESET: Clear default value.
+  *         SET: When the received slave address matched with one of the enabled slave address.
+  * @rmtoll ISR          ADDR          LL_I2C_IsActiveFlag_ADDR
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate the status of Not Acknowledge received flag.
+  * @note   RESET: Clear default value.
+  *         SET: When a NACK is received after a byte transmission.
+  * @rmtoll ISR          NACKF         LL_I2C_IsActiveFlag_NACK
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate the status of Stop detection flag.
+  * @note   RESET: Clear default value.
+  *         SET: When a Stop condition is detected.
+  * @rmtoll ISR          STOPF         LL_I2C_IsActiveFlag_STOP
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate the status of Transfer complete flag (master mode).
+  * @note   RESET: Clear default value.
+  *         SET: When RELOAD=0, AUTOEND=0 and NBYTES date have been transferred.
+  * @rmtoll ISR          TC            LL_I2C_IsActiveFlag_TC
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate the status of Transfer complete flag (master mode).
+  * @note   RESET: Clear default value.
+  *         SET: When RELOAD=1 and NBYTES date have been transferred.
+  * @rmtoll ISR          TCR           LL_I2C_IsActiveFlag_TCR
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate the status of Bus error flag.
+  * @note   RESET: Clear default value.
+  *         SET: When a misplaced Start or Stop condition is detected.
+  * @rmtoll ISR          BERR          LL_I2C_IsActiveFlag_BERR
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate the status of Arbitration lost flag.
+  * @note   RESET: Clear default value.
+  *         SET: When arbitration lost.
+  * @rmtoll ISR          ARLO          LL_I2C_IsActiveFlag_ARLO
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate the status of Overrun/Underrun flag (slave mode).
+  * @note   RESET: Clear default value.
+  *         SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
+  * @rmtoll ISR          OVR           LL_I2C_IsActiveFlag_OVR
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate the status of SMBus PEC error flag in reception.
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @note   RESET: Clear default value.
+  *         SET: When the received PEC does not match with the PEC register content.
+  * @rmtoll ISR          PECERR        LL_I2C_IsActiveSMBusFlag_PECERR
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate the status of SMBus Timeout detection flag.
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @note   RESET: Clear default value.
+  *         SET: When a timeout or extended clock timeout occurs.
+  * @rmtoll ISR          TIMEOUT       LL_I2C_IsActiveSMBusFlag_TIMEOUT
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate the status of SMBus alert flag.
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @note   RESET: Clear default value.
+  *         SET: When SMBus host configuration, SMBus alert enabled and
+  *              a falling edge event occurs on SMBA pin.
+  * @rmtoll ISR          ALERT         LL_I2C_IsActiveSMBusFlag_ALERT
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate the status of Bus Busy flag.
+  * @note   RESET: Clear default value.
+  *         SET: When a Start condition is detected.
+  * @rmtoll ISR          BUSY          LL_I2C_IsActiveFlag_BUSY
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear Address Matched flag.
+  * @rmtoll ICR          ADDRCF        LL_I2C_ClearFlag_ADDR
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->ICR, I2C_ICR_ADDRCF);
+}
+
+/**
+  * @brief  Clear Not Acknowledge flag.
+  * @rmtoll ICR          NACKCF        LL_I2C_ClearFlag_NACK
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_ClearFlag_NACK(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->ICR, I2C_ICR_NACKCF);
+}
+
+/**
+  * @brief  Clear Stop detection flag.
+  * @rmtoll ICR          STOPCF        LL_I2C_ClearFlag_STOP
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->ICR, I2C_ICR_STOPCF);
+}
+
+/**
+  * @brief  Clear Transmit data register empty flag (TXE).
+  * @note   This bit can be clear by software in order to flush the transmit data register (TXDR).
+  * @rmtoll ISR          TXE           LL_I2C_ClearFlag_TXE
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_ClearFlag_TXE(I2C_TypeDef *I2Cx)
+{
+  WRITE_REG(I2Cx->ISR, I2C_ISR_TXE);
+}
+
+/**
+  * @brief  Clear Bus error flag.
+  * @rmtoll ICR          BERRCF        LL_I2C_ClearFlag_BERR
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->ICR, I2C_ICR_BERRCF);
+}
+
+/**
+  * @brief  Clear Arbitration lost flag.
+  * @rmtoll ICR          ARLOCF        LL_I2C_ClearFlag_ARLO
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->ICR, I2C_ICR_ARLOCF);
+}
+
+/**
+  * @brief  Clear Overrun/Underrun flag.
+  * @rmtoll ICR          OVRCF         LL_I2C_ClearFlag_OVR
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->ICR, I2C_ICR_OVRCF);
+}
+
+/**
+  * @brief  Clear SMBus PEC error flag.
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll ICR          PECCF         LL_I2C_ClearSMBusFlag_PECERR
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->ICR, I2C_ICR_PECCF);
+}
+
+/**
+  * @brief  Clear SMBus Timeout detection flag.
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll ICR          TIMOUTCF      LL_I2C_ClearSMBusFlag_TIMEOUT
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->ICR, I2C_ICR_TIMOUTCF);
+}
+
+/**
+  * @brief  Clear SMBus Alert flag.
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll ICR          ALERTCF       LL_I2C_ClearSMBusFlag_ALERT
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->ICR, I2C_ICR_ALERTCF);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EF_Data_Management Data_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable automatic STOP condition generation (master mode).
+  * @note   Automatic end mode : a STOP condition is automatically sent when NBYTES data are transferred.
+  *         This bit has no effect in slave mode or when RELOAD bit is set.
+  * @rmtoll CR2          AUTOEND       LL_I2C_EnableAutoEndMode
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableAutoEndMode(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
+}
+
+/**
+  * @brief  Disable automatic STOP condition generation (master mode).
+  * @note   Software end mode : TC flag is set when NBYTES data are transferre, stretching SCL low.
+  * @rmtoll CR2          AUTOEND       LL_I2C_DisableAutoEndMode
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableAutoEndMode(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
+}
+
+/**
+  * @brief  Check if automatic STOP condition is enabled or disabled.
+  * @rmtoll CR2          AUTOEND       LL_I2C_IsEnabledAutoEndMode
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable reload mode (master mode).
+  * @note   The transfer is not completed after the NBYTES data transfer, NBYTES will be reloaded when TCR flag is set.
+  * @rmtoll CR2          RELOAD       LL_I2C_EnableReloadMode
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableReloadMode(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
+}
+
+/**
+  * @brief  Disable reload mode (master mode).
+  * @note   The transfer is completed after the NBYTES data transfer(STOP or RESTART will follow).
+  * @rmtoll CR2          RELOAD       LL_I2C_DisableReloadMode
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableReloadMode(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
+}
+
+/**
+  * @brief  Check if reload mode is enabled or disabled.
+  * @rmtoll CR2          RELOAD       LL_I2C_IsEnabledReloadMode
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Configure the number of bytes for transfer.
+  * @note   Changing these bits when START bit is set is not allowed.
+  * @rmtoll CR2          NBYTES           LL_I2C_SetTransferSize
+  * @param  I2Cx I2C Instance.
+  * @param  TransferSize This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t TransferSize)
+{
+  MODIFY_REG(I2Cx->CR2, I2C_CR2_NBYTES, TransferSize << I2C_CR2_NBYTES_Pos);
+}
+
+/**
+  * @brief  Get the number of bytes configured for transfer.
+  * @rmtoll CR2          NBYTES           LL_I2C_GetTransferSize
+  * @param  I2Cx I2C Instance.
+  * @retval Value between Min_Data=0x0 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetTransferSize(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_CR2_NBYTES_Pos);
+}
+
+/**
+  * @brief  Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code
+            or next received byte.
+  * @note   Usage in Slave mode only.
+  * @rmtoll CR2          NACK          LL_I2C_AcknowledgeNextData
+  * @param  I2Cx I2C Instance.
+  * @param  TypeAcknowledge This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_ACK
+  *         @arg @ref LL_I2C_NACK
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
+{
+  MODIFY_REG(I2Cx->CR2, I2C_CR2_NACK, TypeAcknowledge);
+}
+
+/**
+  * @brief  Generate a START or RESTART condition
+  * @note   The START bit can be set even if bus is BUSY or I2C is in slave mode.
+  *         This action has no effect when RELOAD is set.
+  * @rmtoll CR2          START           LL_I2C_GenerateStartCondition
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR2, I2C_CR2_START);
+}
+
+/**
+  * @brief  Generate a STOP condition after the current byte transfer (master mode).
+  * @rmtoll CR2          STOP          LL_I2C_GenerateStopCondition
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR2, I2C_CR2_STOP);
+}
+
+/**
+  * @brief  Enable automatic RESTART Read request condition for 10bit address header (master mode).
+  * @note   The master sends the complete 10bit slave address read sequence :
+  *         Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address
+            in Read direction.
+  * @rmtoll CR2          HEAD10R       LL_I2C_EnableAuto10BitRead
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableAuto10BitRead(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
+}
+
+/**
+  * @brief  Disable automatic RESTART Read request condition for 10bit address header (master mode).
+  * @note   The master only sends the first 7 bits of 10bit address in Read direction.
+  * @rmtoll CR2          HEAD10R       LL_I2C_DisableAuto10BitRead
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableAuto10BitRead(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
+}
+
+/**
+  * @brief  Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled.
+  * @rmtoll CR2          HEAD10R       LL_I2C_IsEnabledAuto10BitRead
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Configure the transfer direction (master mode).
+  * @note   Changing these bits when START bit is set is not allowed.
+  * @rmtoll CR2          RD_WRN           LL_I2C_SetTransferRequest
+  * @param  I2Cx I2C Instance.
+  * @param  TransferRequest This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_REQUEST_WRITE
+  *         @arg @ref LL_I2C_REQUEST_READ
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_SetTransferRequest(I2C_TypeDef *I2Cx, uint32_t TransferRequest)
+{
+  MODIFY_REG(I2Cx->CR2, I2C_CR2_RD_WRN, TransferRequest);
+}
+
+/**
+  * @brief  Get the transfer direction requested (master mode).
+  * @rmtoll CR2          RD_WRN           LL_I2C_GetTransferRequest
+  * @param  I2Cx I2C Instance.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_I2C_REQUEST_WRITE
+  *         @arg @ref LL_I2C_REQUEST_READ
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_RD_WRN));
+}
+
+/**
+  * @brief  Configure the slave address for transfer (master mode).
+  * @note   Changing these bits when START bit is set is not allowed.
+  * @rmtoll CR2          SADD           LL_I2C_SetSlaveAddr
+  * @param  I2Cx I2C Instance.
+  * @param  SlaveAddr This parameter must be a value between Min_Data=0x00 and Max_Data=0x3F.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_SetSlaveAddr(I2C_TypeDef *I2Cx, uint32_t SlaveAddr)
+{
+  MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD, SlaveAddr);
+}
+
+/**
+  * @brief  Get the slave address programmed for transfer.
+  * @rmtoll CR2          SADD           LL_I2C_GetSlaveAddr
+  * @param  I2Cx I2C Instance.
+  * @retval Value between Min_Data=0x0 and Max_Data=0x3F
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_SADD));
+}
+
+/**
+  * @brief  Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
+  * @rmtoll CR2          SADD          LL_I2C_HandleTransfer\n
+  *         CR2          ADD10         LL_I2C_HandleTransfer\n
+  *         CR2          RD_WRN        LL_I2C_HandleTransfer\n
+  *         CR2          START         LL_I2C_HandleTransfer\n
+  *         CR2          STOP          LL_I2C_HandleTransfer\n
+  *         CR2          RELOAD        LL_I2C_HandleTransfer\n
+  *         CR2          NBYTES        LL_I2C_HandleTransfer\n
+  *         CR2          AUTOEND       LL_I2C_HandleTransfer\n
+  *         CR2          HEAD10R       LL_I2C_HandleTransfer
+  * @param  I2Cx I2C Instance.
+  * @param  SlaveAddr Specifies the slave address to be programmed.
+  * @param  SlaveAddrSize This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_ADDRSLAVE_7BIT
+  *         @arg @ref LL_I2C_ADDRSLAVE_10BIT
+  * @param  TransferSize Specifies the number of bytes to be programmed.
+  *                       This parameter must be a value between Min_Data=0 and Max_Data=255.
+  * @param  EndMode This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_MODE_RELOAD
+  *         @arg @ref LL_I2C_MODE_AUTOEND
+  *         @arg @ref LL_I2C_MODE_SOFTEND
+  *         @arg @ref LL_I2C_MODE_SMBUS_RELOAD
+  *         @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC
+  *         @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC
+  *         @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC
+  *         @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC
+  * @param  Request This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_GENERATE_NOSTARTSTOP
+  *         @arg @ref LL_I2C_GENERATE_STOP
+  *         @arg @ref LL_I2C_GENERATE_START_READ
+  *         @arg @ref LL_I2C_GENERATE_START_WRITE
+  *         @arg @ref LL_I2C_GENERATE_RESTART_7BIT_READ
+  *         @arg @ref LL_I2C_GENERATE_RESTART_7BIT_WRITE
+  *         @arg @ref LL_I2C_GENERATE_RESTART_10BIT_READ
+  *         @arg @ref LL_I2C_GENERATE_RESTART_10BIT_WRITE
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize,
+                                           uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
+{
+  MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 |
+             (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) |
+             I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD |
+             I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R,
+             SlaveAddr | SlaveAddrSize | (TransferSize << I2C_CR2_NBYTES_Pos) | EndMode | Request);
+}
+
+/**
+  * @brief  Indicate the value of transfer direction (slave mode).
+  * @note   RESET: Write transfer, Slave enters in receiver mode.
+  *         SET: Read transfer, Slave enters in transmitter mode.
+  * @rmtoll ISR          DIR           LL_I2C_GetTransferDirection
+  * @param  I2Cx I2C Instance.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_I2C_DIRECTION_WRITE
+  *         @arg @ref LL_I2C_DIRECTION_READ
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_DIR));
+}
+
+/**
+  * @brief  Return the slave matched address.
+  * @rmtoll ISR          ADDCODE       LL_I2C_GetAddressMatchCode
+  * @param  I2Cx I2C Instance.
+  * @retval Value between Min_Data=0x00 and Max_Data=0x3F
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_ISR_ADDCODE_Pos << 1);
+}
+
+/**
+  * @brief  Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode).
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @note   This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition
+            or an Address Matched is received.
+  *         This bit has no effect when RELOAD bit is set.
+  *         This bit has no effect in device mode when SBC bit is not set.
+  * @rmtoll CR2          PECBYTE       LL_I2C_EnableSMBusPECCompare
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR2, I2C_CR2_PECBYTE);
+}
+
+/**
+  * @brief  Check if the SMBus Packet Error byte internal comparison is requested or not.
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll CR2          PECBYTE       LL_I2C_IsEnabledSMBusPECCompare
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get the SMBus Packet Error byte calculated.
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll PECR         PEC           LL_I2C_GetSMBusPEC
+  * @param  I2Cx I2C Instance.
+  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC));
+}
+
+/**
+  * @brief  Read Receive Data register.
+  * @rmtoll RXDR         RXDATA        LL_I2C_ReceiveData8
+  * @param  I2Cx I2C Instance.
+  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx)
+{
+  return (uint8_t)(READ_BIT(I2Cx->RXDR, I2C_RXDR_RXDATA));
+}
+
+/**
+  * @brief  Write in Transmit Data Register .
+  * @rmtoll TXDR         TXDATA        LL_I2C_TransmitData8
+  * @param  I2Cx I2C Instance.
+  * @param  Data Value between Min_Data=0x00 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
+{
+  WRITE_REG(I2Cx->TXDR, Data);
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+
+ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct);
+ErrorStatus LL_I2C_DeInit(I2C_TypeDef *I2Cx);
+void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
+
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* I2C1 || I2C2 || I2C3 || I2C4  || I2C5 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_LL_I2C_H */
diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_lpuart.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_lpuart.h
index 3fef9da7..282dfc5c 100644
--- a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_lpuart.h
+++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_lpuart.h
@@ -1,2650 +1,2650 @@
-/**
-  ******************************************************************************
-  * @file    stm32h7xx_ll_lpuart.h
-  * @author  MCD Application Team
-  * @brief   Header file of LPUART LL module.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32H7xx_LL_LPUART_H
-#define STM32H7xx_LL_LPUART_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx.h"
-
-/** @addtogroup STM32H7xx_LL_Driver
-  * @{
-  */
-
-#if defined (LPUART1)
-
-/** @defgroup LPUART_LL LPUART
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup LPUART_LL_Private_Variables LPUART Private Variables
-  * @{
-  */
-/* Array used to get the LPUART prescaler division decimal values versus @ref LPUART_LL_EC_PRESCALER values */
-static const uint16_t LPUART_PRESCALER_TAB[] =
-{
-  (uint16_t)1,
-  (uint16_t)2,
-  (uint16_t)4,
-  (uint16_t)6,
-  (uint16_t)8,
-  (uint16_t)10,
-  (uint16_t)12,
-  (uint16_t)16,
-  (uint16_t)32,
-  (uint16_t)64,
-  (uint16_t)128,
-  (uint16_t)256
-};
-/**
-  * @}
-  */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup LPUART_LL_Private_Constants LPUART Private Constants
-  * @{
-  */
-/* Defines used in Baud Rate related macros and corresponding register setting computation */
-#define LPUART_LPUARTDIV_FREQ_MUL     256U
-#define LPUART_BRR_MASK               0x000FFFFFU
-#define LPUART_BRR_MIN_VALUE          0x00000300U
-/**
-  * @}
-  */
-
-
-/* Private macros ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup LPUART_LL_Private_Macros LPUART Private Macros
-  * @{
-  */
-/**
-  * @}
-  */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup LPUART_LL_ES_INIT LPUART Exported Init structures
-  * @{
-  */
-
-/**
-  * @brief LL LPUART Init Structure definition
-  */
-typedef struct
-{
-  uint32_t PrescalerValue;            /*!< Specifies the Prescaler to compute the communication baud rate.
-                                           This parameter can be a value of @ref LPUART_LL_EC_PRESCALER.
-
-                                           This feature can be modified afterwards using unitary
-                                           function @ref LL_LPUART_SetPrescaler().*/
-
-  uint32_t BaudRate;                  /*!< This field defines expected LPUART communication baud rate.
-
-                                           This feature can be modified afterwards using unitary
-                                           function @ref LL_LPUART_SetBaudRate().*/
-
-  uint32_t DataWidth;                 /*!< Specifies the number of data bits transmitted or received in a frame.
-                                           This parameter can be a value of @ref LPUART_LL_EC_DATAWIDTH.
-
-                                           This feature can be modified afterwards using unitary
-                                           function @ref LL_LPUART_SetDataWidth().*/
-
-  uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
-                                           This parameter can be a value of @ref LPUART_LL_EC_STOPBITS.
-
-                                           This feature can be modified afterwards using unitary
-                                           function @ref LL_LPUART_SetStopBitsLength().*/
-
-  uint32_t Parity;                    /*!< Specifies the parity mode.
-                                           This parameter can be a value of @ref LPUART_LL_EC_PARITY.
-
-                                           This feature can be modified afterwards using unitary
-                                           function @ref LL_LPUART_SetParity().*/
-
-  uint32_t TransferDirection;         /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
-                                           This parameter can be a value of @ref LPUART_LL_EC_DIRECTION.
-
-                                           This feature can be modified afterwards using unitary
-                                           function @ref LL_LPUART_SetTransferDirection().*/
-
-  uint32_t HardwareFlowControl;       /*!< Specifies whether the hardware flow control mode is enabled or disabled.
-                                           This parameter can be a value of @ref LPUART_LL_EC_HWCONTROL.
-
-                                           This feature can be modified afterwards using unitary
-                                           function @ref LL_LPUART_SetHWFlowCtrl().*/
-
-} LL_LPUART_InitTypeDef;
-
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup LPUART_LL_Exported_Constants LPUART Exported Constants
-  * @{
-  */
-
-/** @defgroup LPUART_LL_EC_CLEAR_FLAG Clear Flags Defines
-  * @brief    Flags defines which can be used with LL_LPUART_WriteReg function
-  * @{
-  */
-#define LL_LPUART_ICR_PECF                 USART_ICR_PECF                /*!< Parity error clear flag */
-#define LL_LPUART_ICR_FECF                 USART_ICR_FECF                /*!< Framing error clear flag */
-#define LL_LPUART_ICR_NCF                  USART_ICR_NECF                /*!< Noise error detected clear flag */
-#define LL_LPUART_ICR_ORECF                USART_ICR_ORECF               /*!< Overrun error clear flag */
-#define LL_LPUART_ICR_IDLECF               USART_ICR_IDLECF              /*!< Idle line detected clear flag */
-#define LL_LPUART_ICR_TCCF                 USART_ICR_TCCF                /*!< Transmission complete clear flag */
-#define LL_LPUART_ICR_CTSCF                USART_ICR_CTSCF               /*!< CTS clear flag */
-#define LL_LPUART_ICR_CMCF                 USART_ICR_CMCF                /*!< Character match clear flag */
-#define LL_LPUART_ICR_WUCF                 USART_ICR_WUCF                /*!< Wakeup from Stop mode clear flag */
-/**
-  * @}
-  */
-
-/** @defgroup LPUART_LL_EC_GET_FLAG Get Flags Defines
-  * @brief    Flags defines which can be used with LL_LPUART_ReadReg function
-  * @{
-  */
-#define LL_LPUART_ISR_PE               USART_ISR_PE         /*!< Parity error flag */
-#define LL_LPUART_ISR_FE               USART_ISR_FE         /*!< Framing error flag */
-#define LL_LPUART_ISR_NE               USART_ISR_NE         /*!< Noise detected flag */
-#define LL_LPUART_ISR_ORE              USART_ISR_ORE        /*!< Overrun error flag */
-#define LL_LPUART_ISR_IDLE             USART_ISR_IDLE       /*!< Idle line detected flag */
-#define LL_LPUART_ISR_RXNE_RXFNE       USART_ISR_RXNE_RXFNE /*!< Read data register or RX FIFO not empty flag */
-#define LL_LPUART_ISR_TC               USART_ISR_TC         /*!< Transmission complete flag */
-#define LL_LPUART_ISR_TXE_TXFNF        USART_ISR_TXE_TXFNF  /*!< Transmit data register empty or TX FIFO Not Full flag*/
-#define LL_LPUART_ISR_CTSIF            USART_ISR_CTSIF      /*!< CTS interrupt flag */
-#define LL_LPUART_ISR_CTS              USART_ISR_CTS        /*!< CTS flag */
-#define LL_LPUART_ISR_BUSY             USART_ISR_BUSY       /*!< Busy flag */
-#define LL_LPUART_ISR_CMF              USART_ISR_CMF        /*!< Character match flag */
-#define LL_LPUART_ISR_SBKF             USART_ISR_SBKF       /*!< Send break flag */
-#define LL_LPUART_ISR_RWU              USART_ISR_RWU        /*!< Receiver wakeup from Mute mode flag */
-#define LL_LPUART_ISR_WUF              USART_ISR_WUF        /*!< Wakeup from Stop mode flag */
-#define LL_LPUART_ISR_TEACK            USART_ISR_TEACK      /*!< Transmit enable acknowledge flag */
-#define LL_LPUART_ISR_REACK            USART_ISR_REACK      /*!< Receive enable acknowledge flag */
-#define LL_LPUART_ISR_TXFE             USART_ISR_TXFE       /*!< TX FIFO empty flag */
-#define LL_LPUART_ISR_RXFF             USART_ISR_RXFF       /*!< RX FIFO full flag */
-#define LL_LPUART_ISR_RXFT             USART_ISR_RXFT       /*!< RX FIFO threshold flag */
-#define LL_LPUART_ISR_TXFT             USART_ISR_TXFT       /*!< TX FIFO threshold flag */
-/**
-  * @}
-  */
-
-/** @defgroup LPUART_LL_EC_IT IT Defines
-  * @brief    IT defines which can be used with LL_LPUART_ReadReg and  LL_LPUART_WriteReg functions
-  * @{
-  */
-#define LL_LPUART_CR1_IDLEIE         USART_CR1_IDLEIE         /*!< IDLE interrupt enable */
-#define LL_LPUART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE /*!< Read data register and RXFIFO not empty
-                                                                   interrupt enable */
-#define LL_LPUART_CR1_TCIE           USART_CR1_TCIE           /*!< Transmission complete interrupt enable */
-#define LL_LPUART_CR1_TXEIE_TXFNFIE  USART_CR1_TXEIE_TXFNFIE  /*!< Transmit data register empty and TX FIFO
-                                                                   not full interrupt enable */
-#define LL_LPUART_CR1_PEIE           USART_CR1_PEIE           /*!< Parity error */
-#define LL_LPUART_CR1_CMIE           USART_CR1_CMIE           /*!< Character match interrupt enable */
-#define LL_LPUART_CR1_TXFEIE         USART_CR1_TXFEIE         /*!< TX FIFO empty interrupt enable */
-#define LL_LPUART_CR1_RXFFIE         USART_CR1_RXFFIE         /*!< RX FIFO full interrupt enable */
-#define LL_LPUART_CR3_EIE            USART_CR3_EIE            /*!< Error interrupt enable */
-#define LL_LPUART_CR3_CTSIE          USART_CR3_CTSIE          /*!< CTS interrupt enable */
-#define LL_LPUART_CR3_WUFIE          USART_CR3_WUFIE          /*!< Wakeup from Stop mode interrupt enable */
-#define LL_LPUART_CR3_TXFTIE         USART_CR3_TXFTIE         /*!< TX FIFO threshold interrupt enable */
-#define LL_LPUART_CR3_RXFTIE         USART_CR3_RXFTIE         /*!< RX FIFO threshold interrupt enable */
-/**
-  * @}
-  */
-
-/** @defgroup LPUART_LL_EC_FIFOTHRESHOLD FIFO Threshold
-  * @{
-  */
-#define LL_LPUART_FIFOTHRESHOLD_1_8        0x00000000U /*!< FIFO reaches 1/8 of its depth */
-#define LL_LPUART_FIFOTHRESHOLD_1_4        0x00000001U /*!< FIFO reaches 1/4 of its depth */
-#define LL_LPUART_FIFOTHRESHOLD_1_2        0x00000002U /*!< FIFO reaches 1/2 of its depth */
-#define LL_LPUART_FIFOTHRESHOLD_3_4        0x00000003U /*!< FIFO reaches 3/4 of its depth */
-#define LL_LPUART_FIFOTHRESHOLD_7_8        0x00000004U /*!< FIFO reaches 7/8 of its depth */
-#define LL_LPUART_FIFOTHRESHOLD_8_8        0x00000005U /*!< FIFO becomes empty for TX and full for RX */
-/**
-  * @}
-  */
-
-/** @defgroup LPUART_LL_EC_DIRECTION Direction
-  * @{
-  */
-#define LL_LPUART_DIRECTION_NONE  0x00000000U                  /*!< Transmitter and Receiver are disabled           */
-#define LL_LPUART_DIRECTION_RX    USART_CR1_RE                 /*!< Transmitter is disabled and Receiver is enabled */
-#define LL_LPUART_DIRECTION_TX    USART_CR1_TE                 /*!< Transmitter is enabled and Receiver is disabled */
-#define LL_LPUART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled            */
-/**
-  * @}
-  */
-
-/** @defgroup LPUART_LL_EC_PARITY Parity Control
-  * @{
-  */
-#define LL_LPUART_PARITY_NONE 0x00000000U                    /*!< Parity control disabled                            */
-#define LL_LPUART_PARITY_EVEN USART_CR1_PCE                  /*!< Parity control enabled and Even Parity is selected */
-#define LL_LPUART_PARITY_ODD  (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected  */
-/**
-  * @}
-  */
-
-/** @defgroup LPUART_LL_EC_WAKEUP Wakeup
-  * @{
-  */
-#define LL_LPUART_WAKEUP_IDLELINE    0x00000000U    /*!<  LPUART wake up from Mute mode on Idle Line    */
-#define LL_LPUART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!<  LPUART wake up from Mute mode on Address Mark */
-/**
-  * @}
-  */
-
-/** @defgroup LPUART_LL_EC_DATAWIDTH Datawidth
-  * @{
-  */
-#define LL_LPUART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */
-#define LL_LPUART_DATAWIDTH_8B 0x00000000U  /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
-#define LL_LPUART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
-/**
-  * @}
-  */
-
-/** @defgroup LPUART_LL_EC_PRESCALER Clock Source Prescaler
-  * @{
-  */
-#define LL_LPUART_PRESCALER_DIV1   0x00000000U                    /*!< Input clock not divided   */
-#define LL_LPUART_PRESCALER_DIV2   (USART_PRESC_PRESCALER_0)      /*!< Input clock divided by 2  */
-#define LL_LPUART_PRESCALER_DIV4   (USART_PRESC_PRESCALER_1)      /*!< Input clock divided by 4  */
-#define LL_LPUART_PRESCALER_DIV6   (USART_PRESC_PRESCALER_1 |\
-                                    USART_PRESC_PRESCALER_0)      /*!< Input clock divided by 6  */
-#define LL_LPUART_PRESCALER_DIV8   (USART_PRESC_PRESCALER_2)      /*!< Input clock divided by 8  */
-#define LL_LPUART_PRESCALER_DIV10  (USART_PRESC_PRESCALER_2 |\
-                                    USART_PRESC_PRESCALER_0)      /*!< Input clock divided by 10 */
-#define LL_LPUART_PRESCALER_DIV12  (USART_PRESC_PRESCALER_2 |\
-                                    USART_PRESC_PRESCALER_1)      /*!< Input clock divided by 12 */
-#define LL_LPUART_PRESCALER_DIV16  (USART_PRESC_PRESCALER_2 |\
-                                    USART_PRESC_PRESCALER_1 |\
-                                    USART_PRESC_PRESCALER_0)      /*!< Input clock divided by 16 */
-#define LL_LPUART_PRESCALER_DIV32  (USART_PRESC_PRESCALER_3)      /*!< Input clock divided by 32 */
-#define LL_LPUART_PRESCALER_DIV64  (USART_PRESC_PRESCALER_3 |\
-                                    USART_PRESC_PRESCALER_0)      /*!< Input clock divided by 64 */
-#define LL_LPUART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 |\
-                                    USART_PRESC_PRESCALER_1)      /*!< Input clock divided by 128 */
-#define LL_LPUART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 |\
-                                    USART_PRESC_PRESCALER_1 |\
-                                    USART_PRESC_PRESCALER_0)      /*!< Input clock divided by 256 */
-/**
-  * @}
-  */
-
-/** @defgroup LPUART_LL_EC_STOPBITS Stop Bits
-  * @{
-  */
-#define LL_LPUART_STOPBITS_1         0x00000000U             /*!< 1 stop bit */
-#define LL_LPUART_STOPBITS_2         USART_CR2_STOP_1        /*!< 2 stop bits */
-/**
-  * @}
-  */
-
-/** @defgroup LPUART_LL_EC_TXRX TX RX Pins Swap
-  * @{
-  */
-#define LL_LPUART_TXRX_STANDARD      0x00000000U        /*!< TX/RX pins are used as defined in standard pinout */
-#define LL_LPUART_TXRX_SWAPPED       (USART_CR2_SWAP)   /*!< TX and RX pins functions are swapped.             */
-/**
-  * @}
-  */
-
-/** @defgroup LPUART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion
-  * @{
-  */
-#define LL_LPUART_RXPIN_LEVEL_STANDARD   0x00000000U       /*!< RX pin signal works using the standard logic levels */
-#define LL_LPUART_RXPIN_LEVEL_INVERTED   (USART_CR2_RXINV) /*!< RX pin signal values are inverted.                  */
-/**
-  * @}
-  */
-
-/** @defgroup LPUART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion
-  * @{
-  */
-#define LL_LPUART_TXPIN_LEVEL_STANDARD  0x00000000U       /*!< TX pin signal works using the standard logic levels */
-#define LL_LPUART_TXPIN_LEVEL_INVERTED  (USART_CR2_TXINV) /*!< TX pin signal values are inverted.                  */
-/**
-  * @}
-  */
-
-/** @defgroup LPUART_LL_EC_BINARY_LOGIC Binary Data Inversion
-  * @{
-  */
-#define LL_LPUART_BINARY_LOGIC_POSITIVE 0x00000000U       /*!< Logical data from the data register are send/received
-                                                               in positive/direct logic. (1=H, 0=L)                  */
-#define LL_LPUART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the data register are send/received
-                                                               in negative/inverse logic. (1=L, 0=H).
-                                                               The parity bit is also inverted.                      */
-/**
-  * @}
-  */
-
-/** @defgroup LPUART_LL_EC_BITORDER Bit Order
-  * @{
-  */
-#define LL_LPUART_BITORDER_LSBFIRST 0x00000000U        /*!< data is transmitted/received with data bit 0 first,
-                                                            following the start bit */
-#define LL_LPUART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/received with the MSB first,
-                                                            following the start bit */
-/**
-  * @}
-  */
-
-/** @defgroup LPUART_LL_EC_ADDRESS_DETECT Address Length Detection
-  * @{
-  */
-#define LL_LPUART_ADDRESS_DETECT_4B 0x00000000U     /*!< 4-bit address detection method selected */
-#define LL_LPUART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method selected */
-/**
-  * @}
-  */
-
-/** @defgroup LPUART_LL_EC_HWCONTROL Hardware Control
-  * @{
-  */
-#define LL_LPUART_HWCONTROL_NONE    0x00000000U                       /*!< CTS and RTS hardware flow control disabled */
-#define LL_LPUART_HWCONTROL_RTS     USART_CR3_RTSE                    /*!< RTS output enabled, data is only requested
-                                                                           when there is space in the receive buffer  */
-#define LL_LPUART_HWCONTROL_CTS     USART_CR3_CTSE                    /*!< CTS mode enabled, data is only transmitted
-                                                                           when the nCTS input is asserted (tied to 0)*/
-#define LL_LPUART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled  */
-/**
-  * @}
-  */
-
-/** @defgroup LPUART_LL_EC_WAKEUP_ON Wakeup Activation
-  * @{
-  */
-#define LL_LPUART_WAKEUP_ON_ADDRESS   0x00000000U                          /*!< Wake up active on address match */
-#define LL_LPUART_WAKEUP_ON_STARTBIT  USART_CR3_WUS_1                      /*!< Wake up active on Start bit detection */
-#define LL_LPUART_WAKEUP_ON_RXNE      (USART_CR3_WUS_0 | USART_CR3_WUS_1)  /*!< Wake up active on RXNE */
-/**
-  * @}
-  */
-
-/** @defgroup LPUART_LL_EC_DE_POLARITY Driver Enable Polarity
-  * @{
-  */
-#define LL_LPUART_DE_POLARITY_HIGH         0x00000000U    /*!< DE signal is active high */
-#define LL_LPUART_DE_POLARITY_LOW          USART_CR3_DEP  /*!< DE signal is active low */
-/**
-  * @}
-  */
-
-/** @defgroup LPUART_LL_EC_DMA_REG_DATA DMA Register Data
-  * @{
-  */
-#define LL_LPUART_DMA_REG_DATA_TRANSMIT    0x00000000U    /*!< Get address of data register used for transmission */
-#define LL_LPUART_DMA_REG_DATA_RECEIVE     0x00000001U    /*!< Get address of data register used for reception */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup LPUART_LL_Exported_Macros LPUART Exported Macros
-  * @{
-  */
-
-/** @defgroup LPUART_LL_EM_WRITE_READ Common Write and read registers Macros
-  * @{
-  */
-
-/**
-  * @brief  Write a value in LPUART register
-  * @param  __INSTANCE__ LPUART Instance
-  * @param  __REG__ Register to be written
-  * @param  __VALUE__ Value to be written in the register
-  * @retval None
-  */
-#define LL_LPUART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
-  * @brief  Read a value in LPUART register
-  * @param  __INSTANCE__ LPUART Instance
-  * @param  __REG__ Register to be read
-  * @retval Register value
-  */
-#define LL_LPUART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
-  * @}
-  */
-
-/** @defgroup LPUART_LL_EM_Exported_Macros_Helper Helper Macros
-  * @{
-  */
-
-/**
-  * @brief  Compute LPUARTDIV value according to Peripheral Clock and
-  *         expected Baud Rate (20-bit value of LPUARTDIV is returned)
-  * @param  __PERIPHCLK__ Peripheral Clock frequency used for LPUART Instance
-  * @param  __PRESCALER__ This parameter can be one of the following values:
-  *         @arg @ref LL_LPUART_PRESCALER_DIV1
-  *         @arg @ref LL_LPUART_PRESCALER_DIV2
-  *         @arg @ref LL_LPUART_PRESCALER_DIV4
-  *         @arg @ref LL_LPUART_PRESCALER_DIV6
-  *         @arg @ref LL_LPUART_PRESCALER_DIV8
-  *         @arg @ref LL_LPUART_PRESCALER_DIV10
-  *         @arg @ref LL_LPUART_PRESCALER_DIV12
-  *         @arg @ref LL_LPUART_PRESCALER_DIV16
-  *         @arg @ref LL_LPUART_PRESCALER_DIV32
-  *         @arg @ref LL_LPUART_PRESCALER_DIV64
-  *         @arg @ref LL_LPUART_PRESCALER_DIV128
-  *         @arg @ref LL_LPUART_PRESCALER_DIV256
-  * @param  __BAUDRATE__ Baud Rate value to achieve
-  * @retval LPUARTDIV value to be used for BRR register filling
-  */
-#define __LL_LPUART_DIV(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (uint32_t)\
-  ((((((uint64_t)(__PERIPHCLK__)/(uint64_t)(LPUART_PRESCALER_TAB[(uint16_t)(__PRESCALER__)]))\
-      * LPUART_LPUARTDIV_FREQ_MUL) + (uint32_t)((__BAUDRATE__)/2U))/(__BAUDRATE__)) & LPUART_BRR_MASK)
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup LPUART_LL_Exported_Functions LPUART Exported Functions
-  * @{
-  */
-
-/** @defgroup LPUART_LL_EF_Configuration Configuration functions
-  * @{
-  */
-
-/**
-  * @brief  LPUART Enable
-  * @rmtoll CR1          UE            LL_LPUART_Enable
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_Enable(USART_TypeDef *LPUARTx)
-{
-  SET_BIT(LPUARTx->CR1, USART_CR1_UE);
-}
-
-/**
-  * @brief  LPUART Disable
-  * @note   When LPUART is disabled, LPUART prescalers and outputs are stopped immediately,
-  *         and current operations are discarded. The configuration of the LPUART is kept, but all the status
-  *         flags, in the LPUARTx_ISR are set to their default values.
-  * @note   In order to go into low-power mode without generating errors on the line,
-  *         the TE bit must be reset before and the software must wait
-  *         for the TC bit in the LPUART_ISR to be set before resetting the UE bit.
-  *         The DMA requests are also reset when UE = 0 so the DMA channel must
-  *         be disabled before resetting the UE bit.
-  * @rmtoll CR1          UE            LL_LPUART_Disable
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_Disable(USART_TypeDef *LPUARTx)
-{
-  CLEAR_BIT(LPUARTx->CR1, USART_CR1_UE);
-}
-
-/**
-  * @brief  Indicate if LPUART is enabled
-  * @rmtoll CR1          UE            LL_LPUART_IsEnabled
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabled(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  FIFO Mode Enable
-  * @rmtoll CR1          FIFOEN        LL_LPUART_EnableFIFO
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_EnableFIFO(USART_TypeDef *LPUARTx)
-{
-  SET_BIT(LPUARTx->CR1, USART_CR1_FIFOEN);
-}
-
-/**
-  * @brief  FIFO Mode Disable
-  * @rmtoll CR1          FIFOEN        LL_LPUART_DisableFIFO
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_DisableFIFO(USART_TypeDef *LPUARTx)
-{
-  CLEAR_BIT(LPUARTx->CR1, USART_CR1_FIFOEN);
-}
-
-/**
-  * @brief  Indicate if FIFO Mode is enabled
-  * @rmtoll CR1          FIFOEN        LL_LPUART_IsEnabledFIFO
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledFIFO(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Configure TX FIFO Threshold
-  * @rmtoll CR3          TXFTCFG       LL_LPUART_SetTXFIFOThreshold
-  * @param  LPUARTx LPUART Instance
-  * @param  Threshold This parameter can be one of the following values:
-  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
-  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
-  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
-  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
-  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
-  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_SetTXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold)
-{
-  ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos);
-}
-
-/**
-  * @brief  Return TX FIFO Threshold Configuration
-  * @rmtoll CR3          TXFTCFG       LL_LPUART_GetTXFIFOThreshold
-  * @param  LPUARTx LPUART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
-  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
-  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
-  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
-  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
-  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
-  */
-__STATIC_INLINE uint32_t LL_LPUART_GetTXFIFOThreshold(USART_TypeDef *LPUARTx)
-{
-  return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
-}
-
-/**
-  * @brief  Configure RX FIFO Threshold
-  * @rmtoll CR3          RXFTCFG       LL_LPUART_SetRXFIFOThreshold
-  * @param  LPUARTx LPUART Instance
-  * @param  Threshold This parameter can be one of the following values:
-  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
-  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
-  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
-  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
-  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
-  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_SetRXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold)
-{
-  ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos);
-}
-
-/**
-  * @brief  Return RX FIFO Threshold Configuration
-  * @rmtoll CR3          RXFTCFG       LL_LPUART_GetRXFIFOThreshold
-  * @param  LPUARTx LPUART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
-  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
-  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
-  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
-  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
-  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
-  */
-__STATIC_INLINE uint32_t LL_LPUART_GetRXFIFOThreshold(USART_TypeDef *LPUARTx)
-{
-  return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
-}
-
-/**
-  * @brief  Configure TX and RX FIFOs Threshold
-  * @rmtoll CR3          TXFTCFG       LL_LPUART_ConfigFIFOsThreshold\n
-  *         CR3          RXFTCFG       LL_LPUART_ConfigFIFOsThreshold
-  * @param  LPUARTx LPUART Instance
-  * @param  TXThreshold This parameter can be one of the following values:
-  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
-  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
-  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
-  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
-  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
-  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
-  * @param  RXThreshold This parameter can be one of the following values:
-  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
-  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
-  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
-  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
-  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
-  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_ConfigFIFOsThreshold(USART_TypeDef *LPUARTx, uint32_t TXThreshold, uint32_t RXThreshold)
-{
-  ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | \
-                    (RXThreshold << USART_CR3_RXFTCFG_Pos));
-}
-
-/**
-  * @brief  LPUART enabled in STOP Mode
-  * @note   When this function is enabled, LPUART is able to wake up the MCU from Stop mode, provided that
-  *         LPUART clock selection is HSI or LSE in RCC.
-  * @rmtoll CR1          UESM          LL_LPUART_EnableInStopMode
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_EnableInStopMode(USART_TypeDef *LPUARTx)
-{
-  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_UESM);
-}
-
-/**
-  * @brief  LPUART disabled in STOP Mode
-  * @note   When this function is disabled, LPUART is not able to wake up the MCU from Stop mode
-  * @rmtoll CR1          UESM          LL_LPUART_DisableInStopMode
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_DisableInStopMode(USART_TypeDef *LPUARTx)
-{
-  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_UESM);
-}
-
-/**
-  * @brief  Indicate if LPUART is enabled in STOP Mode
-  *         (able to wake up MCU from Stop mode or not)
-  * @rmtoll CR1          UESM          LL_LPUART_IsEnabledInStopMode
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledInStopMode(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Receiver Enable (Receiver is enabled and begins searching for a start bit)
-  * @rmtoll CR1          RE            LL_LPUART_EnableDirectionRx
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_EnableDirectionRx(USART_TypeDef *LPUARTx)
-{
-  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RE);
-}
-
-/**
-  * @brief  Receiver Disable
-  * @rmtoll CR1          RE            LL_LPUART_DisableDirectionRx
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_DisableDirectionRx(USART_TypeDef *LPUARTx)
-{
-  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RE);
-}
-
-/**
-  * @brief  Transmitter Enable
-  * @rmtoll CR1          TE            LL_LPUART_EnableDirectionTx
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_EnableDirectionTx(USART_TypeDef *LPUARTx)
-{
-  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TE);
-}
-
-/**
-  * @brief  Transmitter Disable
-  * @rmtoll CR1          TE            LL_LPUART_DisableDirectionTx
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_DisableDirectionTx(USART_TypeDef *LPUARTx)
-{
-  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TE);
-}
-
-/**
-  * @brief  Configure simultaneously enabled/disabled states
-  *         of Transmitter and Receiver
-  * @rmtoll CR1          RE            LL_LPUART_SetTransferDirection\n
-  *         CR1          TE            LL_LPUART_SetTransferDirection
-  * @param  LPUARTx LPUART Instance
-  * @param  TransferDirection This parameter can be one of the following values:
-  *         @arg @ref LL_LPUART_DIRECTION_NONE
-  *         @arg @ref LL_LPUART_DIRECTION_RX
-  *         @arg @ref LL_LPUART_DIRECTION_TX
-  *         @arg @ref LL_LPUART_DIRECTION_TX_RX
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_SetTransferDirection(USART_TypeDef *LPUARTx, uint32_t TransferDirection)
-{
-  ATOMIC_MODIFY_REG(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
-}
-
-/**
-  * @brief  Return enabled/disabled states of Transmitter and Receiver
-  * @rmtoll CR1          RE            LL_LPUART_GetTransferDirection\n
-  *         CR1          TE            LL_LPUART_GetTransferDirection
-  * @param  LPUARTx LPUART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_LPUART_DIRECTION_NONE
-  *         @arg @ref LL_LPUART_DIRECTION_RX
-  *         @arg @ref LL_LPUART_DIRECTION_TX
-  *         @arg @ref LL_LPUART_DIRECTION_TX_RX
-  */
-__STATIC_INLINE uint32_t LL_LPUART_GetTransferDirection(USART_TypeDef *LPUARTx)
-{
-  return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE));
-}
-
-/**
-  * @brief  Configure Parity (enabled/disabled and parity mode if enabled)
-  * @note   This function selects if hardware parity control (generation and detection) is enabled or disabled.
-  *         When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position
-  *         (depending on data width) and parity is checked on the received data.
-  * @rmtoll CR1          PS            LL_LPUART_SetParity\n
-  *         CR1          PCE           LL_LPUART_SetParity
-  * @param  LPUARTx LPUART Instance
-  * @param  Parity This parameter can be one of the following values:
-  *         @arg @ref LL_LPUART_PARITY_NONE
-  *         @arg @ref LL_LPUART_PARITY_EVEN
-  *         @arg @ref LL_LPUART_PARITY_ODD
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_SetParity(USART_TypeDef *LPUARTx, uint32_t Parity)
-{
-  MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);
-}
-
-/**
-  * @brief  Return Parity configuration (enabled/disabled and parity mode if enabled)
-  * @rmtoll CR1          PS            LL_LPUART_GetParity\n
-  *         CR1          PCE           LL_LPUART_GetParity
-  * @param  LPUARTx LPUART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_LPUART_PARITY_NONE
-  *         @arg @ref LL_LPUART_PARITY_EVEN
-  *         @arg @ref LL_LPUART_PARITY_ODD
-  */
-__STATIC_INLINE uint32_t LL_LPUART_GetParity(USART_TypeDef *LPUARTx)
-{
-  return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
-}
-
-/**
-  * @brief  Set Receiver Wake Up method from Mute mode.
-  * @rmtoll CR1          WAKE          LL_LPUART_SetWakeUpMethod
-  * @param  LPUARTx LPUART Instance
-  * @param  Method This parameter can be one of the following values:
-  *         @arg @ref LL_LPUART_WAKEUP_IDLELINE
-  *         @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_SetWakeUpMethod(USART_TypeDef *LPUARTx, uint32_t Method)
-{
-  MODIFY_REG(LPUARTx->CR1, USART_CR1_WAKE, Method);
-}
-
-/**
-  * @brief  Return Receiver Wake Up method from Mute mode
-  * @rmtoll CR1          WAKE          LL_LPUART_GetWakeUpMethod
-  * @param  LPUARTx LPUART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_LPUART_WAKEUP_IDLELINE
-  *         @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK
-  */
-__STATIC_INLINE uint32_t LL_LPUART_GetWakeUpMethod(USART_TypeDef *LPUARTx)
-{
-  return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_WAKE));
-}
-
-/**
-  * @brief  Set Word length (nb of data bits, excluding start and stop bits)
-  * @rmtoll CR1          M             LL_LPUART_SetDataWidth
-  * @param  LPUARTx LPUART Instance
-  * @param  DataWidth This parameter can be one of the following values:
-  *         @arg @ref LL_LPUART_DATAWIDTH_7B
-  *         @arg @ref LL_LPUART_DATAWIDTH_8B
-  *         @arg @ref LL_LPUART_DATAWIDTH_9B
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_SetDataWidth(USART_TypeDef *LPUARTx, uint32_t DataWidth)
-{
-  MODIFY_REG(LPUARTx->CR1, USART_CR1_M, DataWidth);
-}
-
-/**
-  * @brief  Return Word length (i.e. nb of data bits, excluding start and stop bits)
-  * @rmtoll CR1          M             LL_LPUART_GetDataWidth
-  * @param  LPUARTx LPUART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_LPUART_DATAWIDTH_7B
-  *         @arg @ref LL_LPUART_DATAWIDTH_8B
-  *         @arg @ref LL_LPUART_DATAWIDTH_9B
-  */
-__STATIC_INLINE uint32_t LL_LPUART_GetDataWidth(USART_TypeDef *LPUARTx)
-{
-  return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_M));
-}
-
-/**
-  * @brief  Allow switch between Mute Mode and Active mode
-  * @rmtoll CR1          MME           LL_LPUART_EnableMuteMode
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_EnableMuteMode(USART_TypeDef *LPUARTx)
-{
-  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_MME);
-}
-
-/**
-  * @brief  Prevent Mute Mode use. Set Receiver in active mode permanently.
-  * @rmtoll CR1          MME           LL_LPUART_DisableMuteMode
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_DisableMuteMode(USART_TypeDef *LPUARTx)
-{
-  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_MME);
-}
-
-/**
-  * @brief  Indicate if switch between Mute Mode and Active mode is allowed
-  * @rmtoll CR1          MME           LL_LPUART_IsEnabledMuteMode
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledMuteMode(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Configure Clock source prescaler for baudrate generator and oversampling
-  * @rmtoll PRESC        PRESCALER     LL_LPUART_SetPrescaler
-  * @param  LPUARTx LPUART Instance
-  * @param  PrescalerValue This parameter can be one of the following values:
-  *         @arg @ref LL_LPUART_PRESCALER_DIV1
-  *         @arg @ref LL_LPUART_PRESCALER_DIV2
-  *         @arg @ref LL_LPUART_PRESCALER_DIV4
-  *         @arg @ref LL_LPUART_PRESCALER_DIV6
-  *         @arg @ref LL_LPUART_PRESCALER_DIV8
-  *         @arg @ref LL_LPUART_PRESCALER_DIV10
-  *         @arg @ref LL_LPUART_PRESCALER_DIV12
-  *         @arg @ref LL_LPUART_PRESCALER_DIV16
-  *         @arg @ref LL_LPUART_PRESCALER_DIV32
-  *         @arg @ref LL_LPUART_PRESCALER_DIV64
-  *         @arg @ref LL_LPUART_PRESCALER_DIV128
-  *         @arg @ref LL_LPUART_PRESCALER_DIV256
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_SetPrescaler(USART_TypeDef *LPUARTx, uint32_t PrescalerValue)
-{
-  MODIFY_REG(LPUARTx->PRESC, USART_PRESC_PRESCALER, (uint16_t)PrescalerValue);
-}
-
-/**
-  * @brief  Retrieve the Clock source prescaler for baudrate generator and oversampling
-  * @rmtoll PRESC        PRESCALER     LL_LPUART_GetPrescaler
-  * @param  LPUARTx LPUART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_LPUART_PRESCALER_DIV1
-  *         @arg @ref LL_LPUART_PRESCALER_DIV2
-  *         @arg @ref LL_LPUART_PRESCALER_DIV4
-  *         @arg @ref LL_LPUART_PRESCALER_DIV6
-  *         @arg @ref LL_LPUART_PRESCALER_DIV8
-  *         @arg @ref LL_LPUART_PRESCALER_DIV10
-  *         @arg @ref LL_LPUART_PRESCALER_DIV12
-  *         @arg @ref LL_LPUART_PRESCALER_DIV16
-  *         @arg @ref LL_LPUART_PRESCALER_DIV32
-  *         @arg @ref LL_LPUART_PRESCALER_DIV64
-  *         @arg @ref LL_LPUART_PRESCALER_DIV128
-  *         @arg @ref LL_LPUART_PRESCALER_DIV256
-  */
-__STATIC_INLINE uint32_t LL_LPUART_GetPrescaler(USART_TypeDef *LPUARTx)
-{
-  return (uint32_t)(READ_BIT(LPUARTx->PRESC, USART_PRESC_PRESCALER));
-}
-
-/**
-  * @brief  Set the length of the stop bits
-  * @rmtoll CR2          STOP          LL_LPUART_SetStopBitsLength
-  * @param  LPUARTx LPUART Instance
-  * @param  StopBits This parameter can be one of the following values:
-  *         @arg @ref LL_LPUART_STOPBITS_1
-  *         @arg @ref LL_LPUART_STOPBITS_2
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_SetStopBitsLength(USART_TypeDef *LPUARTx, uint32_t StopBits)
-{
-  MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);
-}
-
-/**
-  * @brief  Retrieve the length of the stop bits
-  * @rmtoll CR2          STOP          LL_LPUART_GetStopBitsLength
-  * @param  LPUARTx LPUART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_LPUART_STOPBITS_1
-  *         @arg @ref LL_LPUART_STOPBITS_2
-  */
-__STATIC_INLINE uint32_t LL_LPUART_GetStopBitsLength(USART_TypeDef *LPUARTx)
-{
-  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_STOP));
-}
-
-/**
-  * @brief  Configure Character frame format (Datawidth, Parity control, Stop Bits)
-  * @note   Call of this function is equivalent to following function call sequence :
-  *         - Data Width configuration using @ref LL_LPUART_SetDataWidth() function
-  *         - Parity Control and mode configuration using @ref LL_LPUART_SetParity() function
-  *         - Stop bits configuration using @ref LL_LPUART_SetStopBitsLength() function
-  * @rmtoll CR1          PS            LL_LPUART_ConfigCharacter\n
-  *         CR1          PCE           LL_LPUART_ConfigCharacter\n
-  *         CR1          M             LL_LPUART_ConfigCharacter\n
-  *         CR2          STOP          LL_LPUART_ConfigCharacter
-  * @param  LPUARTx LPUART Instance
-  * @param  DataWidth This parameter can be one of the following values:
-  *         @arg @ref LL_LPUART_DATAWIDTH_7B
-  *         @arg @ref LL_LPUART_DATAWIDTH_8B
-  *         @arg @ref LL_LPUART_DATAWIDTH_9B
-  * @param  Parity This parameter can be one of the following values:
-  *         @arg @ref LL_LPUART_PARITY_NONE
-  *         @arg @ref LL_LPUART_PARITY_EVEN
-  *         @arg @ref LL_LPUART_PARITY_ODD
-  * @param  StopBits This parameter can be one of the following values:
-  *         @arg @ref LL_LPUART_STOPBITS_1
-  *         @arg @ref LL_LPUART_STOPBITS_2
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_ConfigCharacter(USART_TypeDef *LPUARTx, uint32_t DataWidth, uint32_t Parity,
-                                               uint32_t StopBits)
-{
-  MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);
-  MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);
-}
-
-/**
-  * @brief  Configure TX/RX pins swapping setting.
-  * @rmtoll CR2          SWAP          LL_LPUART_SetTXRXSwap
-  * @param  LPUARTx LPUART Instance
-  * @param  SwapConfig This parameter can be one of the following values:
-  *         @arg @ref LL_LPUART_TXRX_STANDARD
-  *         @arg @ref LL_LPUART_TXRX_SWAPPED
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_SetTXRXSwap(USART_TypeDef *LPUARTx, uint32_t SwapConfig)
-{
-  MODIFY_REG(LPUARTx->CR2, USART_CR2_SWAP, SwapConfig);
-}
-
-/**
-  * @brief  Retrieve TX/RX pins swapping configuration.
-  * @rmtoll CR2          SWAP          LL_LPUART_GetTXRXSwap
-  * @param  LPUARTx LPUART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_LPUART_TXRX_STANDARD
-  *         @arg @ref LL_LPUART_TXRX_SWAPPED
-  */
-__STATIC_INLINE uint32_t LL_LPUART_GetTXRXSwap(USART_TypeDef *LPUARTx)
-{
-  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_SWAP));
-}
-
-/**
-  * @brief  Configure RX pin active level logic
-  * @rmtoll CR2          RXINV         LL_LPUART_SetRXPinLevel
-  * @param  LPUARTx LPUART Instance
-  * @param  PinInvMethod This parameter can be one of the following values:
-  *         @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD
-  *         @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_SetRXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
-{
-  MODIFY_REG(LPUARTx->CR2, USART_CR2_RXINV, PinInvMethod);
-}
-
-/**
-  * @brief  Retrieve RX pin active level logic configuration
-  * @rmtoll CR2          RXINV         LL_LPUART_GetRXPinLevel
-  * @param  LPUARTx LPUART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD
-  *         @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED
-  */
-__STATIC_INLINE uint32_t LL_LPUART_GetRXPinLevel(USART_TypeDef *LPUARTx)
-{
-  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_RXINV));
-}
-
-/**
-  * @brief  Configure TX pin active level logic
-  * @rmtoll CR2          TXINV         LL_LPUART_SetTXPinLevel
-  * @param  LPUARTx LPUART Instance
-  * @param  PinInvMethod This parameter can be one of the following values:
-  *         @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD
-  *         @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_SetTXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
-{
-  MODIFY_REG(LPUARTx->CR2, USART_CR2_TXINV, PinInvMethod);
-}
-
-/**
-  * @brief  Retrieve TX pin active level logic configuration
-  * @rmtoll CR2          TXINV         LL_LPUART_GetTXPinLevel
-  * @param  LPUARTx LPUART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD
-  *         @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED
-  */
-__STATIC_INLINE uint32_t LL_LPUART_GetTXPinLevel(USART_TypeDef *LPUARTx)
-{
-  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_TXINV));
-}
-
-/**
-  * @brief  Configure Binary data logic.
-  *
-  * @note   Allow to define how Logical data from the data register are send/received :
-  *         either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)
-  * @rmtoll CR2          DATAINV       LL_LPUART_SetBinaryDataLogic
-  * @param  LPUARTx LPUART Instance
-  * @param  DataLogic This parameter can be one of the following values:
-  *         @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE
-  *         @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_SetBinaryDataLogic(USART_TypeDef *LPUARTx, uint32_t DataLogic)
-{
-  MODIFY_REG(LPUARTx->CR2, USART_CR2_DATAINV, DataLogic);
-}
-
-/**
-  * @brief  Retrieve Binary data configuration
-  * @rmtoll CR2          DATAINV       LL_LPUART_GetBinaryDataLogic
-  * @param  LPUARTx LPUART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE
-  *         @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE
-  */
-__STATIC_INLINE uint32_t LL_LPUART_GetBinaryDataLogic(USART_TypeDef *LPUARTx)
-{
-  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_DATAINV));
-}
-
-/**
-  * @brief  Configure transfer bit order (either Less or Most Significant Bit First)
-  * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.
-  *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.
-  * @rmtoll CR2          MSBFIRST      LL_LPUART_SetTransferBitOrder
-  * @param  LPUARTx LPUART Instance
-  * @param  BitOrder This parameter can be one of the following values:
-  *         @arg @ref LL_LPUART_BITORDER_LSBFIRST
-  *         @arg @ref LL_LPUART_BITORDER_MSBFIRST
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_SetTransferBitOrder(USART_TypeDef *LPUARTx, uint32_t BitOrder)
-{
-  MODIFY_REG(LPUARTx->CR2, USART_CR2_MSBFIRST, BitOrder);
-}
-
-/**
-  * @brief  Return transfer bit order (either Less or Most Significant Bit First)
-  * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.
-  *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.
-  * @rmtoll CR2          MSBFIRST      LL_LPUART_GetTransferBitOrder
-  * @param  LPUARTx LPUART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_LPUART_BITORDER_LSBFIRST
-  *         @arg @ref LL_LPUART_BITORDER_MSBFIRST
-  */
-__STATIC_INLINE uint32_t LL_LPUART_GetTransferBitOrder(USART_TypeDef *LPUARTx)
-{
-  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_MSBFIRST));
-}
-
-/**
-  * @brief  Set Address of the LPUART node.
-  * @note   This is used in multiprocessor communication during Mute mode or Stop mode,
-  *         for wake up with address mark detection.
-  * @note   4bits address node is used when 4-bit Address Detection is selected in ADDM7.
-  *         (b7-b4 should be set to 0)
-  *         8bits address node is used when 7-bit Address Detection is selected in ADDM7.
-  *         (This is used in multiprocessor communication during Mute mode or Stop mode,
-  *         for wake up with 7-bit address mark detection.
-  *         The MSB of the character sent by the transmitter should be equal to 1.
-  *         It may also be used for character detection during normal reception,
-  *         Mute mode inactive (for example, end of block detection in ModBus protocol).
-  *         In this case, the whole received character (8-bit) is compared to the ADD[7:0]
-  *         value and CMF flag is set on match)
-  * @rmtoll CR2          ADD           LL_LPUART_ConfigNodeAddress\n
-  *         CR2          ADDM7         LL_LPUART_ConfigNodeAddress
-  * @param  LPUARTx LPUART Instance
-  * @param  AddressLen This parameter can be one of the following values:
-  *         @arg @ref LL_LPUART_ADDRESS_DETECT_4B
-  *         @arg @ref LL_LPUART_ADDRESS_DETECT_7B
-  * @param  NodeAddress 4 or 7 bit Address of the LPUART node.
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_ConfigNodeAddress(USART_TypeDef *LPUARTx, uint32_t AddressLen, uint32_t NodeAddress)
-{
-  MODIFY_REG(LPUARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7,
-             (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos)));
-}
-
-/**
-  * @brief  Return 8 bit Address of the LPUART node as set in ADD field of CR2.
-  * @note   If 4-bit Address Detection is selected in ADDM7,
-  *         only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)
-  *         If 7-bit Address Detection is selected in ADDM7,
-  *         only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)
-  * @rmtoll CR2          ADD           LL_LPUART_GetNodeAddress
-  * @param  LPUARTx LPUART Instance
-  * @retval Address of the LPUART node (Value between Min_Data=0 and Max_Data=255)
-  */
-__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddress(USART_TypeDef *LPUARTx)
-{
-  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos);
-}
-
-/**
-  * @brief  Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
-  * @rmtoll CR2          ADDM7         LL_LPUART_GetNodeAddressLen
-  * @param  LPUARTx LPUART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_LPUART_ADDRESS_DETECT_4B
-  *         @arg @ref LL_LPUART_ADDRESS_DETECT_7B
-  */
-__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddressLen(USART_TypeDef *LPUARTx)
-{
-  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADDM7));
-}
-
-/**
-  * @brief  Enable RTS HW Flow Control
-  * @rmtoll CR3          RTSE          LL_LPUART_EnableRTSHWFlowCtrl
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_EnableRTSHWFlowCtrl(USART_TypeDef *LPUARTx)
-{
-  SET_BIT(LPUARTx->CR3, USART_CR3_RTSE);
-}
-
-/**
-  * @brief  Disable RTS HW Flow Control
-  * @rmtoll CR3          RTSE          LL_LPUART_DisableRTSHWFlowCtrl
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_DisableRTSHWFlowCtrl(USART_TypeDef *LPUARTx)
-{
-  CLEAR_BIT(LPUARTx->CR3, USART_CR3_RTSE);
-}
-
-/**
-  * @brief  Enable CTS HW Flow Control
-  * @rmtoll CR3          CTSE          LL_LPUART_EnableCTSHWFlowCtrl
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_EnableCTSHWFlowCtrl(USART_TypeDef *LPUARTx)
-{
-  SET_BIT(LPUARTx->CR3, USART_CR3_CTSE);
-}
-
-/**
-  * @brief  Disable CTS HW Flow Control
-  * @rmtoll CR3          CTSE          LL_LPUART_DisableCTSHWFlowCtrl
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_DisableCTSHWFlowCtrl(USART_TypeDef *LPUARTx)
-{
-  CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSE);
-}
-
-/**
-  * @brief  Configure HW Flow Control mode (both CTS and RTS)
-  * @rmtoll CR3          RTSE          LL_LPUART_SetHWFlowCtrl\n
-  *         CR3          CTSE          LL_LPUART_SetHWFlowCtrl
-  * @param  LPUARTx LPUART Instance
-  * @param  HardwareFlowControl This parameter can be one of the following values:
-  *         @arg @ref LL_LPUART_HWCONTROL_NONE
-  *         @arg @ref LL_LPUART_HWCONTROL_RTS
-  *         @arg @ref LL_LPUART_HWCONTROL_CTS
-  *         @arg @ref LL_LPUART_HWCONTROL_RTS_CTS
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_SetHWFlowCtrl(USART_TypeDef *LPUARTx, uint32_t HardwareFlowControl)
-{
-  MODIFY_REG(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);
-}
-
-/**
-  * @brief  Return HW Flow Control configuration (both CTS and RTS)
-  * @rmtoll CR3          RTSE          LL_LPUART_GetHWFlowCtrl\n
-  *         CR3          CTSE          LL_LPUART_GetHWFlowCtrl
-  * @param  LPUARTx LPUART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_LPUART_HWCONTROL_NONE
-  *         @arg @ref LL_LPUART_HWCONTROL_RTS
-  *         @arg @ref LL_LPUART_HWCONTROL_CTS
-  *         @arg @ref LL_LPUART_HWCONTROL_RTS_CTS
-  */
-__STATIC_INLINE uint32_t LL_LPUART_GetHWFlowCtrl(USART_TypeDef *LPUARTx)
-{
-  return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
-}
-
-/**
-  * @brief  Enable Overrun detection
-  * @rmtoll CR3          OVRDIS        LL_LPUART_EnableOverrunDetect
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_EnableOverrunDetect(USART_TypeDef *LPUARTx)
-{
-  CLEAR_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);
-}
-
-/**
-  * @brief  Disable Overrun detection
-  * @rmtoll CR3          OVRDIS        LL_LPUART_DisableOverrunDetect
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_DisableOverrunDetect(USART_TypeDef *LPUARTx)
-{
-  SET_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);
-}
-
-/**
-  * @brief  Indicate if Overrun detection is enabled
-  * @rmtoll CR3          OVRDIS        LL_LPUART_IsEnabledOverrunDetect
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledOverrunDetect(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
-  * @rmtoll CR3          WUS           LL_LPUART_SetWKUPType
-  * @param  LPUARTx LPUART Instance
-  * @param  Type This parameter can be one of the following values:
-  *         @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS
-  *         @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT
-  *         @arg @ref LL_LPUART_WAKEUP_ON_RXNE
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_SetWKUPType(USART_TypeDef *LPUARTx, uint32_t Type)
-{
-  MODIFY_REG(LPUARTx->CR3, USART_CR3_WUS, Type);
-}
-
-/**
-  * @brief  Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
-  * @rmtoll CR3          WUS           LL_LPUART_GetWKUPType
-  * @param  LPUARTx LPUART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS
-  *         @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT
-  *         @arg @ref LL_LPUART_WAKEUP_ON_RXNE
-  */
-__STATIC_INLINE uint32_t LL_LPUART_GetWKUPType(USART_TypeDef *LPUARTx)
-{
-  return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_WUS));
-}
-
-/**
-  * @brief  Configure LPUART BRR register for achieving expected Baud Rate value.
-  *
-  * @note   Compute and set LPUARTDIV value in BRR Register (full BRR content)
-  *         according to used Peripheral Clock and expected Baud Rate values
-  * @note   Peripheral clock and Baud Rate values provided as function parameters should be valid
-  *         (Baud rate value != 0).
-  * @note   Provided that LPUARTx_BRR must be > = 0x300 and LPUART_BRR is 20-bit,
-  *         a care should be taken when generating high baud rates using high PeriphClk
-  *         values. PeriphClk must be in the range [3 x BaudRate, 4096 x BaudRate].
-  * @rmtoll BRR          BRR           LL_LPUART_SetBaudRate
-  * @param  LPUARTx LPUART Instance
-  * @param  PeriphClk Peripheral Clock
-  * @param  PrescalerValue This parameter can be one of the following values:
-  *         @arg @ref LL_LPUART_PRESCALER_DIV1
-  *         @arg @ref LL_LPUART_PRESCALER_DIV2
-  *         @arg @ref LL_LPUART_PRESCALER_DIV4
-  *         @arg @ref LL_LPUART_PRESCALER_DIV6
-  *         @arg @ref LL_LPUART_PRESCALER_DIV8
-  *         @arg @ref LL_LPUART_PRESCALER_DIV10
-  *         @arg @ref LL_LPUART_PRESCALER_DIV12
-  *         @arg @ref LL_LPUART_PRESCALER_DIV16
-  *         @arg @ref LL_LPUART_PRESCALER_DIV32
-  *         @arg @ref LL_LPUART_PRESCALER_DIV64
-  *         @arg @ref LL_LPUART_PRESCALER_DIV128
-  *         @arg @ref LL_LPUART_PRESCALER_DIV256
-  * @param  BaudRate Baud Rate
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
-                                           uint32_t BaudRate)
-{
-  if (BaudRate != 0U)
-  {
-    LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, PrescalerValue, BaudRate);
-  }
-}
-
-/**
-  * @brief  Return current Baud Rate value, according to LPUARTDIV present in BRR register
-  *         (full BRR content), and to used Peripheral Clock values
-  * @note   In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
-  * @rmtoll BRR          BRR           LL_LPUART_GetBaudRate
-  * @param  LPUARTx LPUART Instance
-  * @param  PeriphClk Peripheral Clock
-  * @param  PrescalerValue This parameter can be one of the following values:
-  *         @arg @ref LL_LPUART_PRESCALER_DIV1
-  *         @arg @ref LL_LPUART_PRESCALER_DIV2
-  *         @arg @ref LL_LPUART_PRESCALER_DIV4
-  *         @arg @ref LL_LPUART_PRESCALER_DIV6
-  *         @arg @ref LL_LPUART_PRESCALER_DIV8
-  *         @arg @ref LL_LPUART_PRESCALER_DIV10
-  *         @arg @ref LL_LPUART_PRESCALER_DIV12
-  *         @arg @ref LL_LPUART_PRESCALER_DIV16
-  *         @arg @ref LL_LPUART_PRESCALER_DIV32
-  *         @arg @ref LL_LPUART_PRESCALER_DIV64
-  *         @arg @ref LL_LPUART_PRESCALER_DIV128
-  *         @arg @ref LL_LPUART_PRESCALER_DIV256
-  * @retval Baud Rate
-  */
-__STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue)
-{
-  uint32_t lpuartdiv;
-  uint32_t brrresult;
-  uint32_t periphclkpresc = (uint32_t)(PeriphClk / (LPUART_PRESCALER_TAB[(uint16_t)PrescalerValue]));
-
-  lpuartdiv = LPUARTx->BRR & LPUART_BRR_MASK;
-
-  if (lpuartdiv >= LPUART_BRR_MIN_VALUE)
-  {
-    brrresult = (uint32_t)(((uint64_t)(periphclkpresc) * LPUART_LPUARTDIV_FREQ_MUL) / lpuartdiv);
-  }
-  else
-  {
-    brrresult = 0x0UL;
-  }
-
-  return (brrresult);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup LPUART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature
-  * @{
-  */
-
-/**
-  * @brief  Enable Single Wire Half-Duplex mode
-  * @rmtoll CR3          HDSEL         LL_LPUART_EnableHalfDuplex
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_EnableHalfDuplex(USART_TypeDef *LPUARTx)
-{
-  SET_BIT(LPUARTx->CR3, USART_CR3_HDSEL);
-}
-
-/**
-  * @brief  Disable Single Wire Half-Duplex mode
-  * @rmtoll CR3          HDSEL         LL_LPUART_DisableHalfDuplex
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_DisableHalfDuplex(USART_TypeDef *LPUARTx)
-{
-  CLEAR_BIT(LPUARTx->CR3, USART_CR3_HDSEL);
-}
-
-/**
-  * @brief  Indicate if Single Wire Half-Duplex mode is enabled
-  * @rmtoll CR3          HDSEL         LL_LPUART_IsEnabledHalfDuplex
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledHalfDuplex(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup LPUART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature
-  * @{
-  */
-
-/**
-  * @brief  Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
-  * @rmtoll CR1          DEDT          LL_LPUART_SetDEDeassertionTime
-  * @param  LPUARTx LPUART Instance
-  * @param  Time Value between Min_Data=0 and Max_Data=31
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_SetDEDeassertionTime(USART_TypeDef *LPUARTx, uint32_t Time)
-{
-  MODIFY_REG(LPUARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos);
-}
-
-/**
-  * @brief  Return DEDT (Driver Enable De-Assertion Time)
-  * @rmtoll CR1          DEDT          LL_LPUART_GetDEDeassertionTime
-  * @param  LPUARTx LPUART Instance
-  * @retval Time value expressed on 5 bits ([4:0] bits) : c
-  */
-__STATIC_INLINE uint32_t LL_LPUART_GetDEDeassertionTime(USART_TypeDef *LPUARTx)
-{
-  return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos);
-}
-
-/**
-  * @brief  Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
-  * @rmtoll CR1          DEAT          LL_LPUART_SetDEAssertionTime
-  * @param  LPUARTx LPUART Instance
-  * @param  Time Value between Min_Data=0 and Max_Data=31
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_SetDEAssertionTime(USART_TypeDef *LPUARTx, uint32_t Time)
-{
-  MODIFY_REG(LPUARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos);
-}
-
-/**
-  * @brief  Return DEAT (Driver Enable Assertion Time)
-  * @rmtoll CR1          DEAT          LL_LPUART_GetDEAssertionTime
-  * @param  LPUARTx LPUART Instance
-  * @retval Time value expressed on 5 bits ([4:0] bits) : Time Value between Min_Data=0 and Max_Data=31
-  */
-__STATIC_INLINE uint32_t LL_LPUART_GetDEAssertionTime(USART_TypeDef *LPUARTx)
-{
-  return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos);
-}
-
-/**
-  * @brief  Enable Driver Enable (DE) Mode
-  * @rmtoll CR3          DEM           LL_LPUART_EnableDEMode
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_EnableDEMode(USART_TypeDef *LPUARTx)
-{
-  SET_BIT(LPUARTx->CR3, USART_CR3_DEM);
-}
-
-/**
-  * @brief  Disable Driver Enable (DE) Mode
-  * @rmtoll CR3          DEM           LL_LPUART_DisableDEMode
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_DisableDEMode(USART_TypeDef *LPUARTx)
-{
-  CLEAR_BIT(LPUARTx->CR3, USART_CR3_DEM);
-}
-
-/**
-  * @brief  Indicate if Driver Enable (DE) Mode is enabled
-  * @rmtoll CR3          DEM           LL_LPUART_IsEnabledDEMode
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDEMode(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Select Driver Enable Polarity
-  * @rmtoll CR3          DEP           LL_LPUART_SetDESignalPolarity
-  * @param  LPUARTx LPUART Instance
-  * @param  Polarity This parameter can be one of the following values:
-  *         @arg @ref LL_LPUART_DE_POLARITY_HIGH
-  *         @arg @ref LL_LPUART_DE_POLARITY_LOW
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_SetDESignalPolarity(USART_TypeDef *LPUARTx, uint32_t Polarity)
-{
-  MODIFY_REG(LPUARTx->CR3, USART_CR3_DEP, Polarity);
-}
-
-/**
-  * @brief  Return Driver Enable Polarity
-  * @rmtoll CR3          DEP           LL_LPUART_GetDESignalPolarity
-  * @param  LPUARTx LPUART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_LPUART_DE_POLARITY_HIGH
-  *         @arg @ref LL_LPUART_DE_POLARITY_LOW
-  */
-__STATIC_INLINE uint32_t LL_LPUART_GetDESignalPolarity(USART_TypeDef *LPUARTx)
-{
-  return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_DEP));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup LPUART_LL_EF_FLAG_Management FLAG_Management
-  * @{
-  */
-
-/**
-  * @brief  Check if the LPUART Parity Error Flag is set or not
-  * @rmtoll ISR          PE            LL_LPUART_IsActiveFlag_PE
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_PE(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the LPUART Framing Error Flag is set or not
-  * @rmtoll ISR          FE            LL_LPUART_IsActiveFlag_FE
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_FE(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the LPUART Noise error detected Flag is set or not
-  * @rmtoll ISR          NE            LL_LPUART_IsActiveFlag_NE
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_NE(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the LPUART OverRun Error Flag is set or not
-  * @rmtoll ISR          ORE           LL_LPUART_IsActiveFlag_ORE
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_ORE(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the LPUART IDLE line detected Flag is set or not
-  * @rmtoll ISR          IDLE          LL_LPUART_IsActiveFlag_IDLE
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL);
-}
-
-/* Legacy define */
-#define LL_LPUART_IsActiveFlag_RXNE  LL_LPUART_IsActiveFlag_RXNE_RXFNE
-
-/**
-  * @brief  Check if the LPUART Read Data Register or LPUART RX FIFO Not Empty Flag is set or not
-  * @rmtoll ISR          RXNE_RXFNE    LL_LPUART_IsActiveFlag_RXNE_RXFNE
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE_RXFNE(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the LPUART Transmission Complete Flag is set or not
-  * @rmtoll ISR          TC            LL_LPUART_IsActiveFlag_TC
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL);
-}
-
-/* Legacy define */
-#define LL_LPUART_IsActiveFlag_TXE  LL_LPUART_IsActiveFlag_TXE_TXFNF
-
-/**
-  * @brief  Check if the LPUART Transmit Data Register Empty or LPUART TX FIFO Not Full Flag is set or not
-  * @rmtoll ISR          TXE_TXFNF     LL_LPUART_IsActiveFlag_TXE_TXFNF
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE_TXFNF(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the LPUART CTS interrupt Flag is set or not
-  * @rmtoll ISR          CTSIF         LL_LPUART_IsActiveFlag_nCTS
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_nCTS(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the LPUART CTS Flag is set or not
-  * @rmtoll ISR          CTS           LL_LPUART_IsActiveFlag_CTS
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CTS(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the LPUART Busy Flag is set or not
-  * @rmtoll ISR          BUSY          LL_LPUART_IsActiveFlag_BUSY
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_BUSY(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the LPUART Character Match Flag is set or not
-  * @rmtoll ISR          CMF           LL_LPUART_IsActiveFlag_CM
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CM(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the LPUART Send Break Flag is set or not
-  * @rmtoll ISR          SBKF          LL_LPUART_IsActiveFlag_SBK
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_SBK(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the LPUART Receive Wake Up from mute mode Flag is set or not
-  * @rmtoll ISR          RWU           LL_LPUART_IsActiveFlag_RWU
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RWU(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the LPUART Wake Up from stop mode Flag is set or not
-  * @rmtoll ISR          WUF           LL_LPUART_IsActiveFlag_WKUP
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_WKUP(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the LPUART Transmit Enable Acknowledge Flag is set or not
-  * @rmtoll ISR          TEACK         LL_LPUART_IsActiveFlag_TEACK
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TEACK(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the LPUART Receive Enable Acknowledge Flag is set or not
-  * @rmtoll ISR          REACK         LL_LPUART_IsActiveFlag_REACK
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the LPUART TX FIFO Empty Flag is set or not
-  * @rmtoll ISR          TXFE          LL_LPUART_IsActiveFlag_TXFE
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFE(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the LPUART RX FIFO Full Flag is set or not
-  * @rmtoll ISR          RXFF          LL_LPUART_IsActiveFlag_RXFF
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFF(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the LPUART TX FIFO Threshold Flag is set or not
-  * @rmtoll ISR          TXFT          LL_LPUART_IsActiveFlag_TXFT
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFT(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the LPUART RX FIFO Threshold Flag is set or not
-  * @rmtoll ISR          RXFT          LL_LPUART_IsActiveFlag_RXFT
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFT(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear Parity Error Flag
-  * @rmtoll ICR          PECF          LL_LPUART_ClearFlag_PE
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_ClearFlag_PE(USART_TypeDef *LPUARTx)
-{
-  WRITE_REG(LPUARTx->ICR, USART_ICR_PECF);
-}
-
-/**
-  * @brief  Clear Framing Error Flag
-  * @rmtoll ICR          FECF          LL_LPUART_ClearFlag_FE
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_ClearFlag_FE(USART_TypeDef *LPUARTx)
-{
-  WRITE_REG(LPUARTx->ICR, USART_ICR_FECF);
-}
-
-/**
-  * @brief  Clear Noise detected Flag
-  * @rmtoll ICR          NECF          LL_LPUART_ClearFlag_NE
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_ClearFlag_NE(USART_TypeDef *LPUARTx)
-{
-  WRITE_REG(LPUARTx->ICR, USART_ICR_NECF);
-}
-
-/**
-  * @brief  Clear OverRun Error Flag
-  * @rmtoll ICR          ORECF         LL_LPUART_ClearFlag_ORE
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_ClearFlag_ORE(USART_TypeDef *LPUARTx)
-{
-  WRITE_REG(LPUARTx->ICR, USART_ICR_ORECF);
-}
-
-/**
-  * @brief  Clear IDLE line detected Flag
-  * @rmtoll ICR          IDLECF        LL_LPUART_ClearFlag_IDLE
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_ClearFlag_IDLE(USART_TypeDef *LPUARTx)
-{
-  WRITE_REG(LPUARTx->ICR, USART_ICR_IDLECF);
-}
-
-/**
-  * @brief  Clear Transmission Complete Flag
-  * @rmtoll ICR          TCCF          LL_LPUART_ClearFlag_TC
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_ClearFlag_TC(USART_TypeDef *LPUARTx)
-{
-  WRITE_REG(LPUARTx->ICR, USART_ICR_TCCF);
-}
-
-/**
-  * @brief  Clear CTS Interrupt Flag
-  * @rmtoll ICR          CTSCF         LL_LPUART_ClearFlag_nCTS
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_ClearFlag_nCTS(USART_TypeDef *LPUARTx)
-{
-  WRITE_REG(LPUARTx->ICR, USART_ICR_CTSCF);
-}
-
-/**
-  * @brief  Clear Character Match Flag
-  * @rmtoll ICR          CMCF          LL_LPUART_ClearFlag_CM
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_ClearFlag_CM(USART_TypeDef *LPUARTx)
-{
-  WRITE_REG(LPUARTx->ICR, USART_ICR_CMCF);
-}
-
-/**
-  * @brief  Clear Wake Up from stop mode Flag
-  * @rmtoll ICR          WUCF          LL_LPUART_ClearFlag_WKUP
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_ClearFlag_WKUP(USART_TypeDef *LPUARTx)
-{
-  WRITE_REG(LPUARTx->ICR, USART_ICR_WUCF);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup LPUART_LL_EF_IT_Management IT_Management
-  * @{
-  */
-
-/**
-  * @brief  Enable IDLE Interrupt
-  * @rmtoll CR1          IDLEIE        LL_LPUART_EnableIT_IDLE
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_EnableIT_IDLE(USART_TypeDef *LPUARTx)
-{
-  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
-}
-
-/* Legacy define */
-#define LL_LPUART_EnableIT_RXNE  LL_LPUART_EnableIT_RXNE_RXFNE
-
-/**
-  * @brief  Enable RX Not Empty and RX FIFO Not Empty Interrupt
-  * @rmtoll CR1        RXNEIE_RXFNEIE  LL_LPUART_EnableIT_RXNE_RXFNE
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_EnableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)
-{
-  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
-}
-
-/**
-  * @brief  Enable Transmission Complete Interrupt
-  * @rmtoll CR1          TCIE          LL_LPUART_EnableIT_TC
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_EnableIT_TC(USART_TypeDef *LPUARTx)
-{
-  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TCIE);
-}
-
-/* Legacy define */
-#define LL_LPUART_EnableIT_TXE  LL_LPUART_EnableIT_TXE_TXFNF
-
-/**
-  * @brief  Enable TX Empty and TX FIFO Not Full Interrupt
-  * @rmtoll CR1         TXEIE_TXFNFIE  LL_LPUART_EnableIT_TXE_TXFNF
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_EnableIT_TXE_TXFNF(USART_TypeDef *LPUARTx)
-{
-  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
-}
-
-/**
-  * @brief  Enable Parity Error Interrupt
-  * @rmtoll CR1          PEIE          LL_LPUART_EnableIT_PE
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_EnableIT_PE(USART_TypeDef *LPUARTx)
-{
-  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_PEIE);
-}
-
-/**
-  * @brief  Enable Character Match Interrupt
-  * @rmtoll CR1          CMIE          LL_LPUART_EnableIT_CM
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_EnableIT_CM(USART_TypeDef *LPUARTx)
-{
-  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_CMIE);
-}
-
-/**
-  * @brief  Enable TX FIFO Empty Interrupt
-  * @rmtoll CR1          TXFEIE        LL_LPUART_EnableIT_TXFE
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_EnableIT_TXFE(USART_TypeDef *LPUARTx)
-{
-  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXFEIE);
-}
-
-/**
-  * @brief  Enable RX FIFO Full Interrupt
-  * @rmtoll CR1          RXFFIE        LL_LPUART_EnableIT_RXFF
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_EnableIT_RXFF(USART_TypeDef *LPUARTx)
-{
-  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXFFIE);
-}
-
-/**
-  * @brief  Enable Error Interrupt
-  * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
-  *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
-  *         - 0: Interrupt is inhibited
-  *         - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
-  * @rmtoll CR3          EIE           LL_LPUART_EnableIT_ERROR
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_EnableIT_ERROR(USART_TypeDef *LPUARTx)
-{
-  ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_EIE);
-}
-
-/**
-  * @brief  Enable CTS Interrupt
-  * @rmtoll CR3          CTSIE         LL_LPUART_EnableIT_CTS
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_EnableIT_CTS(USART_TypeDef *LPUARTx)
-{
-  ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
-}
-
-/**
-  * @brief  Enable Wake Up from Stop Mode Interrupt
-  * @rmtoll CR3          WUFIE         LL_LPUART_EnableIT_WKUP
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_EnableIT_WKUP(USART_TypeDef *LPUARTx)
-{
-  ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
-}
-
-/**
-  * @brief  Enable TX FIFO Threshold Interrupt
-  * @rmtoll CR3          TXFTIE        LL_LPUART_EnableIT_TXFT
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_EnableIT_TXFT(USART_TypeDef *LPUARTx)
-{
-  ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_TXFTIE);
-}
-
-/**
-  * @brief  Enable RX FIFO Threshold Interrupt
-  * @rmtoll CR3          RXFTIE        LL_LPUART_EnableIT_RXFT
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_EnableIT_RXFT(USART_TypeDef *LPUARTx)
-{
-  ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_RXFTIE);
-}
-
-/**
-  * @brief  Disable IDLE Interrupt
-  * @rmtoll CR1          IDLEIE        LL_LPUART_DisableIT_IDLE
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_DisableIT_IDLE(USART_TypeDef *LPUARTx)
-{
-  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
-}
-
-/* Legacy define */
-#define LL_LPUART_DisableIT_RXNE  LL_LPUART_DisableIT_RXNE_RXFNE
-
-/**
-  * @brief  Disable RX Not Empty and RX FIFO Not Empty Interrupt
-  * @rmtoll CR1        RXNEIE_RXFNEIE  LL_LPUART_DisableIT_RXNE_RXFNE
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_DisableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)
-{
-  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
-}
-
-/**
-  * @brief  Disable Transmission Complete Interrupt
-  * @rmtoll CR1          TCIE          LL_LPUART_DisableIT_TC
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_DisableIT_TC(USART_TypeDef *LPUARTx)
-{
-  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TCIE);
-}
-
-/* Legacy define */
-#define LL_LPUART_DisableIT_TXE  LL_LPUART_DisableIT_TXE_TXFNF
-
-/**
-  * @brief  Disable TX Empty and TX FIFO Not Full Interrupt
-  * @rmtoll CR1        TXEIE_TXFNFIE  LL_LPUART_DisableIT_TXE_TXFNF
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_DisableIT_TXE_TXFNF(USART_TypeDef *LPUARTx)
-{
-  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
-}
-
-/**
-  * @brief  Disable Parity Error Interrupt
-  * @rmtoll CR1          PEIE          LL_LPUART_DisableIT_PE
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_DisableIT_PE(USART_TypeDef *LPUARTx)
-{
-  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_PEIE);
-}
-
-/**
-  * @brief  Disable Character Match Interrupt
-  * @rmtoll CR1          CMIE          LL_LPUART_DisableIT_CM
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_DisableIT_CM(USART_TypeDef *LPUARTx)
-{
-  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_CMIE);
-}
-
-/**
-  * @brief  Disable TX FIFO Empty Interrupt
-  * @rmtoll CR1          TXFEIE        LL_LPUART_DisableIT_TXFE
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_DisableIT_TXFE(USART_TypeDef *LPUARTx)
-{
-  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXFEIE);
-}
-
-/**
-  * @brief  Disable RX FIFO Full Interrupt
-  * @rmtoll CR1          RXFFIE        LL_LPUART_DisableIT_RXFF
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_DisableIT_RXFF(USART_TypeDef *LPUARTx)
-{
-  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXFFIE);
-}
-
-/**
-  * @brief  Disable Error Interrupt
-  * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
-  *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
-  *         - 0: Interrupt is inhibited
-  *         - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
-  * @rmtoll CR3          EIE           LL_LPUART_DisableIT_ERROR
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_DisableIT_ERROR(USART_TypeDef *LPUARTx)
-{
-  ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_EIE);
-}
-
-/**
-  * @brief  Disable CTS Interrupt
-  * @rmtoll CR3          CTSIE         LL_LPUART_DisableIT_CTS
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_DisableIT_CTS(USART_TypeDef *LPUARTx)
-{
-  ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
-}
-
-/**
-  * @brief  Disable Wake Up from Stop Mode Interrupt
-  * @rmtoll CR3          WUFIE         LL_LPUART_DisableIT_WKUP
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_DisableIT_WKUP(USART_TypeDef *LPUARTx)
-{
-  ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
-}
-
-/**
-  * @brief  Disable TX FIFO Threshold Interrupt
-  * @rmtoll CR3          TXFTIE        LL_LPUART_DisableIT_TXFT
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_DisableIT_TXFT(USART_TypeDef *LPUARTx)
-{
-  ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_TXFTIE);
-}
-
-/**
-  * @brief  Disable RX FIFO Threshold Interrupt
-  * @rmtoll CR3          RXFTIE        LL_LPUART_DisableIT_RXFT
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_DisableIT_RXFT(USART_TypeDef *LPUARTx)
-{
-  ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_RXFTIE);
-}
-
-/**
-  * @brief  Check if the LPUART IDLE Interrupt  source is enabled or disabled.
-  * @rmtoll CR1          IDLEIE        LL_LPUART_IsEnabledIT_IDLE
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL);
-}
-
-/* Legacy define */
-#define LL_LPUART_IsEnabledIT_RXNE  LL_LPUART_IsEnabledIT_RXNE_RXFNE
-
-/**
-  * @brief  Check if the LPUART RX Not Empty and LPUART RX FIFO Not Empty Interrupt is enabled or disabled.
-  * @rmtoll CR1        RXNEIE_RXFNEIE  LL_LPUART_IsEnabledIT_RXNE_RXFNE
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the LPUART Transmission Complete Interrupt is enabled or disabled.
-  * @rmtoll CR1          TCIE          LL_LPUART_IsEnabledIT_TC
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL);
-}
-
-/* Legacy define */
-#define LL_LPUART_IsEnabledIT_TXE  LL_LPUART_IsEnabledIT_TXE_TXFNF
-
-/**
-  * @brief  Check if the LPUART TX Empty and LPUART TX FIFO Not Full Interrupt is enabled or disabled
-  * @rmtoll CR1         TXEIE_TXFNFIE  LL_LPUART_IsEnabledIT_TXE_TXFNF
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE_TXFNF(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the LPUART Parity Error Interrupt is enabled or disabled.
-  * @rmtoll CR1          PEIE          LL_LPUART_IsEnabledIT_PE
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_PE(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the LPUART Character Match Interrupt is enabled or disabled.
-  * @rmtoll CR1          CMIE          LL_LPUART_IsEnabledIT_CM
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the LPUART TX FIFO Empty Interrupt is enabled or disabled
-  * @rmtoll CR1          TXFEIE        LL_LPUART_IsEnabledIT_TXFE
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFE(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the LPUART RX FIFO Full Interrupt is enabled or disabled
-  * @rmtoll CR1          RXFFIE        LL_LPUART_IsEnabledIT_RXFF
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFF(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the LPUART Error Interrupt is enabled or disabled.
-  * @rmtoll CR3          EIE           LL_LPUART_IsEnabledIT_ERROR
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_ERROR(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the LPUART CTS Interrupt is enabled or disabled.
-  * @rmtoll CR3          CTSIE         LL_LPUART_IsEnabledIT_CTS
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CTS(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the LPUART Wake Up from Stop Mode Interrupt is enabled or disabled.
-  * @rmtoll CR3          WUFIE         LL_LPUART_IsEnabledIT_WKUP
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_WKUP(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if LPUART TX FIFO Threshold Interrupt is enabled or disabled
-  * @rmtoll CR3          TXFTIE        LL_LPUART_IsEnabledIT_TXFT
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFT(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if LPUART RX FIFO Threshold Interrupt is enabled or disabled
-  * @rmtoll CR3          RXFTIE        LL_LPUART_IsEnabledIT_RXFT
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFT(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup LPUART_LL_EF_DMA_Management DMA_Management
-  * @{
-  */
-
-/**
-  * @brief  Enable DMA Mode for reception
-  * @rmtoll CR3          DMAR          LL_LPUART_EnableDMAReq_RX
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_EnableDMAReq_RX(USART_TypeDef *LPUARTx)
-{
-  ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAR);
-}
-
-/**
-  * @brief  Disable DMA Mode for reception
-  * @rmtoll CR3          DMAR          LL_LPUART_DisableDMAReq_RX
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_DisableDMAReq_RX(USART_TypeDef *LPUARTx)
-{
-  ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAR);
-}
-
-/**
-  * @brief  Check if DMA Mode is enabled for reception
-  * @rmtoll CR3          DMAR          LL_LPUART_IsEnabledDMAReq_RX
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_RX(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable DMA Mode for transmission
-  * @rmtoll CR3          DMAT          LL_LPUART_EnableDMAReq_TX
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_EnableDMAReq_TX(USART_TypeDef *LPUARTx)
-{
-  ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAT);
-}
-
-/**
-  * @brief  Disable DMA Mode for transmission
-  * @rmtoll CR3          DMAT          LL_LPUART_DisableDMAReq_TX
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_DisableDMAReq_TX(USART_TypeDef *LPUARTx)
-{
-  ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAT);
-}
-
-/**
-  * @brief  Check if DMA Mode is enabled for transmission
-  * @rmtoll CR3          DMAT          LL_LPUART_IsEnabledDMAReq_TX
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_TX(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable DMA Disabling on Reception Error
-  * @rmtoll CR3          DDRE          LL_LPUART_EnableDMADeactOnRxErr
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_EnableDMADeactOnRxErr(USART_TypeDef *LPUARTx)
-{
-  SET_BIT(LPUARTx->CR3, USART_CR3_DDRE);
-}
-
-/**
-  * @brief  Disable DMA Disabling on Reception Error
-  * @rmtoll CR3          DDRE          LL_LPUART_DisableDMADeactOnRxErr
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_DisableDMADeactOnRxErr(USART_TypeDef *LPUARTx)
-{
-  CLEAR_BIT(LPUARTx->CR3, USART_CR3_DDRE);
-}
-
-/**
-  * @brief  Indicate if DMA Disabling on Reception Error is disabled
-  * @rmtoll CR3          DDRE          LL_LPUART_IsEnabledDMADeactOnRxErr
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMADeactOnRxErr(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get the LPUART data register address used for DMA transfer
-  * @rmtoll RDR          RDR           LL_LPUART_DMA_GetRegAddr\n
-  * @rmtoll TDR          TDR           LL_LPUART_DMA_GetRegAddr
-  * @param  LPUARTx LPUART Instance
-  * @param  Direction This parameter can be one of the following values:
-  *         @arg @ref LL_LPUART_DMA_REG_DATA_TRANSMIT
-  *         @arg @ref LL_LPUART_DMA_REG_DATA_RECEIVE
-  * @retval Address of data register
-  */
-__STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(USART_TypeDef *LPUARTx, uint32_t Direction)
-{
-  uint32_t data_reg_addr;
-
-  if (Direction == LL_LPUART_DMA_REG_DATA_TRANSMIT)
-  {
-    /* return address of TDR register */
-    data_reg_addr = (uint32_t) &(LPUARTx->TDR);
-  }
-  else
-  {
-    /* return address of RDR register */
-    data_reg_addr = (uint32_t) &(LPUARTx->RDR);
-  }
-
-  return data_reg_addr;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup LPUART_LL_EF_Data_Management Data_Management
-  * @{
-  */
-
-/**
-  * @brief  Read Receiver Data register (Receive Data value, 8 bits)
-  * @rmtoll RDR          RDR           LL_LPUART_ReceiveData8
-  * @param  LPUARTx LPUART Instance
-  * @retval Time Value between Min_Data=0x00 and Max_Data=0xFF
-  */
-__STATIC_INLINE uint8_t LL_LPUART_ReceiveData8(USART_TypeDef *LPUARTx)
-{
-  return (uint8_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR) & 0xFFU);
-}
-
-/**
-  * @brief  Read Receiver Data register (Receive Data value, 9 bits)
-  * @rmtoll RDR          RDR           LL_LPUART_ReceiveData9
-  * @param  LPUARTx LPUART Instance
-  * @retval Time Value between Min_Data=0x00 and Max_Data=0x1FF
-  */
-__STATIC_INLINE uint16_t LL_LPUART_ReceiveData9(USART_TypeDef *LPUARTx)
-{
-  return (uint16_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR));
-}
-
-/**
-  * @brief  Write in Transmitter Data Register (Transmit Data value, 8 bits)
-  * @rmtoll TDR          TDR           LL_LPUART_TransmitData8
-  * @param  LPUARTx LPUART Instance
-  * @param  Value between Min_Data=0x00 and Max_Data=0xFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_TransmitData8(USART_TypeDef *LPUARTx, uint8_t Value)
-{
-  LPUARTx->TDR = Value;
-}
-
-/**
-  * @brief  Write in Transmitter Data Register (Transmit Data value, 9 bits)
-  * @rmtoll TDR          TDR           LL_LPUART_TransmitData9
-  * @param  LPUARTx LPUART Instance
-  * @param  Value between Min_Data=0x00 and Max_Data=0x1FF
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_TransmitData9(USART_TypeDef *LPUARTx, uint16_t Value)
-{
-  LPUARTx->TDR = Value & 0x1FFUL;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup LPUART_LL_EF_Execution Execution
-  * @{
-  */
-
-/**
-  * @brief  Request Break sending
-  * @rmtoll RQR          SBKRQ         LL_LPUART_RequestBreakSending
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_RequestBreakSending(USART_TypeDef *LPUARTx)
-{
-  SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_SBKRQ);
-}
-
-/**
-  * @brief  Put LPUART in mute mode and set the RWU flag
-  * @rmtoll RQR          MMRQ          LL_LPUART_RequestEnterMuteMode
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_RequestEnterMuteMode(USART_TypeDef *LPUARTx)
-{
-  SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_MMRQ);
-}
-
-/**
-  * @brief  Request a Receive Data and FIFO flush
-  * @note   Allows to discard the received data without reading them, and avoid an overrun
-  *         condition.
-  * @rmtoll RQR          RXFRQ         LL_LPUART_RequestRxDataFlush
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_RequestRxDataFlush(USART_TypeDef *LPUARTx)
-{
-  SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_RXFRQ);
-}
-
-/**
-  * @}
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup LPUART_LL_EF_Init Initialization and de-initialization functions
-  * @{
-  */
-ErrorStatus LL_LPUART_DeInit(USART_TypeDef *LPUARTx);
-ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, LL_LPUART_InitTypeDef *LPUART_InitStruct);
-void        LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct);
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* LPUART1 */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32H7xx_LL_LPUART_H */
-
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_ll_lpuart.h
+  * @author  MCD Application Team
+  * @brief   Header file of LPUART LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_LL_LPUART_H
+#define STM32H7xx_LL_LPUART_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx.h"
+
+/** @addtogroup STM32H7xx_LL_Driver
+  * @{
+  */
+
+#if defined (LPUART1)
+
+/** @defgroup LPUART_LL LPUART
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup LPUART_LL_Private_Variables LPUART Private Variables
+  * @{
+  */
+/* Array used to get the LPUART prescaler division decimal values versus @ref LPUART_LL_EC_PRESCALER values */
+static const uint16_t LPUART_PRESCALER_TAB[] =
+{
+  (uint16_t)1,
+  (uint16_t)2,
+  (uint16_t)4,
+  (uint16_t)6,
+  (uint16_t)8,
+  (uint16_t)10,
+  (uint16_t)12,
+  (uint16_t)16,
+  (uint16_t)32,
+  (uint16_t)64,
+  (uint16_t)128,
+  (uint16_t)256
+};
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup LPUART_LL_Private_Constants LPUART Private Constants
+  * @{
+  */
+/* Defines used in Baud Rate related macros and corresponding register setting computation */
+#define LPUART_LPUARTDIV_FREQ_MUL     256U
+#define LPUART_BRR_MASK               0x000FFFFFU
+#define LPUART_BRR_MIN_VALUE          0x00000300U
+/**
+  * @}
+  */
+
+
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup LPUART_LL_Private_Macros LPUART Private Macros
+  * @{
+  */
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup LPUART_LL_ES_INIT LPUART Exported Init structures
+  * @{
+  */
+
+/**
+  * @brief LL LPUART Init Structure definition
+  */
+typedef struct
+{
+  uint32_t PrescalerValue;            /*!< Specifies the Prescaler to compute the communication baud rate.
+                                           This parameter can be a value of @ref LPUART_LL_EC_PRESCALER.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_LPUART_SetPrescaler().*/
+
+  uint32_t BaudRate;                  /*!< This field defines expected LPUART communication baud rate.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_LPUART_SetBaudRate().*/
+
+  uint32_t DataWidth;                 /*!< Specifies the number of data bits transmitted or received in a frame.
+                                           This parameter can be a value of @ref LPUART_LL_EC_DATAWIDTH.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_LPUART_SetDataWidth().*/
+
+  uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
+                                           This parameter can be a value of @ref LPUART_LL_EC_STOPBITS.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_LPUART_SetStopBitsLength().*/
+
+  uint32_t Parity;                    /*!< Specifies the parity mode.
+                                           This parameter can be a value of @ref LPUART_LL_EC_PARITY.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_LPUART_SetParity().*/
+
+  uint32_t TransferDirection;         /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
+                                           This parameter can be a value of @ref LPUART_LL_EC_DIRECTION.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_LPUART_SetTransferDirection().*/
+
+  uint32_t HardwareFlowControl;       /*!< Specifies whether the hardware flow control mode is enabled or disabled.
+                                           This parameter can be a value of @ref LPUART_LL_EC_HWCONTROL.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_LPUART_SetHWFlowCtrl().*/
+
+} LL_LPUART_InitTypeDef;
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup LPUART_LL_Exported_Constants LPUART Exported Constants
+  * @{
+  */
+
+/** @defgroup LPUART_LL_EC_CLEAR_FLAG Clear Flags Defines
+  * @brief    Flags defines which can be used with LL_LPUART_WriteReg function
+  * @{
+  */
+#define LL_LPUART_ICR_PECF                 USART_ICR_PECF                /*!< Parity error clear flag */
+#define LL_LPUART_ICR_FECF                 USART_ICR_FECF                /*!< Framing error clear flag */
+#define LL_LPUART_ICR_NCF                  USART_ICR_NECF                /*!< Noise error detected clear flag */
+#define LL_LPUART_ICR_ORECF                USART_ICR_ORECF               /*!< Overrun error clear flag */
+#define LL_LPUART_ICR_IDLECF               USART_ICR_IDLECF              /*!< Idle line detected clear flag */
+#define LL_LPUART_ICR_TCCF                 USART_ICR_TCCF                /*!< Transmission complete clear flag */
+#define LL_LPUART_ICR_CTSCF                USART_ICR_CTSCF               /*!< CTS clear flag */
+#define LL_LPUART_ICR_CMCF                 USART_ICR_CMCF                /*!< Character match clear flag */
+#define LL_LPUART_ICR_WUCF                 USART_ICR_WUCF                /*!< Wakeup from Stop mode clear flag */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_LPUART_ReadReg function
+  * @{
+  */
+#define LL_LPUART_ISR_PE               USART_ISR_PE         /*!< Parity error flag */
+#define LL_LPUART_ISR_FE               USART_ISR_FE         /*!< Framing error flag */
+#define LL_LPUART_ISR_NE               USART_ISR_NE         /*!< Noise detected flag */
+#define LL_LPUART_ISR_ORE              USART_ISR_ORE        /*!< Overrun error flag */
+#define LL_LPUART_ISR_IDLE             USART_ISR_IDLE       /*!< Idle line detected flag */
+#define LL_LPUART_ISR_RXNE_RXFNE       USART_ISR_RXNE_RXFNE /*!< Read data register or RX FIFO not empty flag */
+#define LL_LPUART_ISR_TC               USART_ISR_TC         /*!< Transmission complete flag */
+#define LL_LPUART_ISR_TXE_TXFNF        USART_ISR_TXE_TXFNF  /*!< Transmit data register empty or TX FIFO Not Full flag*/
+#define LL_LPUART_ISR_CTSIF            USART_ISR_CTSIF      /*!< CTS interrupt flag */
+#define LL_LPUART_ISR_CTS              USART_ISR_CTS        /*!< CTS flag */
+#define LL_LPUART_ISR_BUSY             USART_ISR_BUSY       /*!< Busy flag */
+#define LL_LPUART_ISR_CMF              USART_ISR_CMF        /*!< Character match flag */
+#define LL_LPUART_ISR_SBKF             USART_ISR_SBKF       /*!< Send break flag */
+#define LL_LPUART_ISR_RWU              USART_ISR_RWU        /*!< Receiver wakeup from Mute mode flag */
+#define LL_LPUART_ISR_WUF              USART_ISR_WUF        /*!< Wakeup from Stop mode flag */
+#define LL_LPUART_ISR_TEACK            USART_ISR_TEACK      /*!< Transmit enable acknowledge flag */
+#define LL_LPUART_ISR_REACK            USART_ISR_REACK      /*!< Receive enable acknowledge flag */
+#define LL_LPUART_ISR_TXFE             USART_ISR_TXFE       /*!< TX FIFO empty flag */
+#define LL_LPUART_ISR_RXFF             USART_ISR_RXFF       /*!< RX FIFO full flag */
+#define LL_LPUART_ISR_RXFT             USART_ISR_RXFT       /*!< RX FIFO threshold flag */
+#define LL_LPUART_ISR_TXFT             USART_ISR_TXFT       /*!< TX FIFO threshold flag */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_LPUART_ReadReg and  LL_LPUART_WriteReg functions
+  * @{
+  */
+#define LL_LPUART_CR1_IDLEIE         USART_CR1_IDLEIE         /*!< IDLE interrupt enable */
+#define LL_LPUART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE /*!< Read data register and RXFIFO not empty
+                                                                   interrupt enable */
+#define LL_LPUART_CR1_TCIE           USART_CR1_TCIE           /*!< Transmission complete interrupt enable */
+#define LL_LPUART_CR1_TXEIE_TXFNFIE  USART_CR1_TXEIE_TXFNFIE  /*!< Transmit data register empty and TX FIFO
+                                                                   not full interrupt enable */
+#define LL_LPUART_CR1_PEIE           USART_CR1_PEIE           /*!< Parity error */
+#define LL_LPUART_CR1_CMIE           USART_CR1_CMIE           /*!< Character match interrupt enable */
+#define LL_LPUART_CR1_TXFEIE         USART_CR1_TXFEIE         /*!< TX FIFO empty interrupt enable */
+#define LL_LPUART_CR1_RXFFIE         USART_CR1_RXFFIE         /*!< RX FIFO full interrupt enable */
+#define LL_LPUART_CR3_EIE            USART_CR3_EIE            /*!< Error interrupt enable */
+#define LL_LPUART_CR3_CTSIE          USART_CR3_CTSIE          /*!< CTS interrupt enable */
+#define LL_LPUART_CR3_WUFIE          USART_CR3_WUFIE          /*!< Wakeup from Stop mode interrupt enable */
+#define LL_LPUART_CR3_TXFTIE         USART_CR3_TXFTIE         /*!< TX FIFO threshold interrupt enable */
+#define LL_LPUART_CR3_RXFTIE         USART_CR3_RXFTIE         /*!< RX FIFO threshold interrupt enable */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_FIFOTHRESHOLD FIFO Threshold
+  * @{
+  */
+#define LL_LPUART_FIFOTHRESHOLD_1_8        0x00000000U /*!< FIFO reaches 1/8 of its depth */
+#define LL_LPUART_FIFOTHRESHOLD_1_4        0x00000001U /*!< FIFO reaches 1/4 of its depth */
+#define LL_LPUART_FIFOTHRESHOLD_1_2        0x00000002U /*!< FIFO reaches 1/2 of its depth */
+#define LL_LPUART_FIFOTHRESHOLD_3_4        0x00000003U /*!< FIFO reaches 3/4 of its depth */
+#define LL_LPUART_FIFOTHRESHOLD_7_8        0x00000004U /*!< FIFO reaches 7/8 of its depth */
+#define LL_LPUART_FIFOTHRESHOLD_8_8        0x00000005U /*!< FIFO becomes empty for TX and full for RX */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_DIRECTION Direction
+  * @{
+  */
+#define LL_LPUART_DIRECTION_NONE  0x00000000U                  /*!< Transmitter and Receiver are disabled           */
+#define LL_LPUART_DIRECTION_RX    USART_CR1_RE                 /*!< Transmitter is disabled and Receiver is enabled */
+#define LL_LPUART_DIRECTION_TX    USART_CR1_TE                 /*!< Transmitter is enabled and Receiver is disabled */
+#define LL_LPUART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled            */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_PARITY Parity Control
+  * @{
+  */
+#define LL_LPUART_PARITY_NONE 0x00000000U                    /*!< Parity control disabled                            */
+#define LL_LPUART_PARITY_EVEN USART_CR1_PCE                  /*!< Parity control enabled and Even Parity is selected */
+#define LL_LPUART_PARITY_ODD  (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected  */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_WAKEUP Wakeup
+  * @{
+  */
+#define LL_LPUART_WAKEUP_IDLELINE    0x00000000U    /*!<  LPUART wake up from Mute mode on Idle Line    */
+#define LL_LPUART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!<  LPUART wake up from Mute mode on Address Mark */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_DATAWIDTH Datawidth
+  * @{
+  */
+#define LL_LPUART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */
+#define LL_LPUART_DATAWIDTH_8B 0x00000000U  /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
+#define LL_LPUART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_PRESCALER Clock Source Prescaler
+  * @{
+  */
+#define LL_LPUART_PRESCALER_DIV1   0x00000000U                    /*!< Input clock not divided   */
+#define LL_LPUART_PRESCALER_DIV2   (USART_PRESC_PRESCALER_0)      /*!< Input clock divided by 2  */
+#define LL_LPUART_PRESCALER_DIV4   (USART_PRESC_PRESCALER_1)      /*!< Input clock divided by 4  */
+#define LL_LPUART_PRESCALER_DIV6   (USART_PRESC_PRESCALER_1 |\
+                                    USART_PRESC_PRESCALER_0)      /*!< Input clock divided by 6  */
+#define LL_LPUART_PRESCALER_DIV8   (USART_PRESC_PRESCALER_2)      /*!< Input clock divided by 8  */
+#define LL_LPUART_PRESCALER_DIV10  (USART_PRESC_PRESCALER_2 |\
+                                    USART_PRESC_PRESCALER_0)      /*!< Input clock divided by 10 */
+#define LL_LPUART_PRESCALER_DIV12  (USART_PRESC_PRESCALER_2 |\
+                                    USART_PRESC_PRESCALER_1)      /*!< Input clock divided by 12 */
+#define LL_LPUART_PRESCALER_DIV16  (USART_PRESC_PRESCALER_2 |\
+                                    USART_PRESC_PRESCALER_1 |\
+                                    USART_PRESC_PRESCALER_0)      /*!< Input clock divided by 16 */
+#define LL_LPUART_PRESCALER_DIV32  (USART_PRESC_PRESCALER_3)      /*!< Input clock divided by 32 */
+#define LL_LPUART_PRESCALER_DIV64  (USART_PRESC_PRESCALER_3 |\
+                                    USART_PRESC_PRESCALER_0)      /*!< Input clock divided by 64 */
+#define LL_LPUART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 |\
+                                    USART_PRESC_PRESCALER_1)      /*!< Input clock divided by 128 */
+#define LL_LPUART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 |\
+                                    USART_PRESC_PRESCALER_1 |\
+                                    USART_PRESC_PRESCALER_0)      /*!< Input clock divided by 256 */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_STOPBITS Stop Bits
+  * @{
+  */
+#define LL_LPUART_STOPBITS_1         0x00000000U             /*!< 1 stop bit */
+#define LL_LPUART_STOPBITS_2         USART_CR2_STOP_1        /*!< 2 stop bits */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_TXRX TX RX Pins Swap
+  * @{
+  */
+#define LL_LPUART_TXRX_STANDARD      0x00000000U        /*!< TX/RX pins are used as defined in standard pinout */
+#define LL_LPUART_TXRX_SWAPPED       (USART_CR2_SWAP)   /*!< TX and RX pins functions are swapped.             */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion
+  * @{
+  */
+#define LL_LPUART_RXPIN_LEVEL_STANDARD   0x00000000U       /*!< RX pin signal works using the standard logic levels */
+#define LL_LPUART_RXPIN_LEVEL_INVERTED   (USART_CR2_RXINV) /*!< RX pin signal values are inverted.                  */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion
+  * @{
+  */
+#define LL_LPUART_TXPIN_LEVEL_STANDARD  0x00000000U       /*!< TX pin signal works using the standard logic levels */
+#define LL_LPUART_TXPIN_LEVEL_INVERTED  (USART_CR2_TXINV) /*!< TX pin signal values are inverted.                  */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_BINARY_LOGIC Binary Data Inversion
+  * @{
+  */
+#define LL_LPUART_BINARY_LOGIC_POSITIVE 0x00000000U       /*!< Logical data from the data register are send/received
+                                                               in positive/direct logic. (1=H, 0=L)                  */
+#define LL_LPUART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the data register are send/received
+                                                               in negative/inverse logic. (1=L, 0=H).
+                                                               The parity bit is also inverted.                      */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_BITORDER Bit Order
+  * @{
+  */
+#define LL_LPUART_BITORDER_LSBFIRST 0x00000000U        /*!< data is transmitted/received with data bit 0 first,
+                                                            following the start bit */
+#define LL_LPUART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/received with the MSB first,
+                                                            following the start bit */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_ADDRESS_DETECT Address Length Detection
+  * @{
+  */
+#define LL_LPUART_ADDRESS_DETECT_4B 0x00000000U     /*!< 4-bit address detection method selected */
+#define LL_LPUART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method selected */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_HWCONTROL Hardware Control
+  * @{
+  */
+#define LL_LPUART_HWCONTROL_NONE    0x00000000U                       /*!< CTS and RTS hardware flow control disabled */
+#define LL_LPUART_HWCONTROL_RTS     USART_CR3_RTSE                    /*!< RTS output enabled, data is only requested
+                                                                           when there is space in the receive buffer  */
+#define LL_LPUART_HWCONTROL_CTS     USART_CR3_CTSE                    /*!< CTS mode enabled, data is only transmitted
+                                                                           when the nCTS input is asserted (tied to 0)*/
+#define LL_LPUART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_WAKEUP_ON Wakeup Activation
+  * @{
+  */
+#define LL_LPUART_WAKEUP_ON_ADDRESS   0x00000000U                          /*!< Wake up active on address match */
+#define LL_LPUART_WAKEUP_ON_STARTBIT  USART_CR3_WUS_1                      /*!< Wake up active on Start bit detection */
+#define LL_LPUART_WAKEUP_ON_RXNE      (USART_CR3_WUS_0 | USART_CR3_WUS_1)  /*!< Wake up active on RXNE */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_DE_POLARITY Driver Enable Polarity
+  * @{
+  */
+#define LL_LPUART_DE_POLARITY_HIGH         0x00000000U    /*!< DE signal is active high */
+#define LL_LPUART_DE_POLARITY_LOW          USART_CR3_DEP  /*!< DE signal is active low */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_DMA_REG_DATA DMA Register Data
+  * @{
+  */
+#define LL_LPUART_DMA_REG_DATA_TRANSMIT    0x00000000U    /*!< Get address of data register used for transmission */
+#define LL_LPUART_DMA_REG_DATA_RECEIVE     0x00000001U    /*!< Get address of data register used for reception */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup LPUART_LL_Exported_Macros LPUART Exported Macros
+  * @{
+  */
+
+/** @defgroup LPUART_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in LPUART register
+  * @param  __INSTANCE__ LPUART Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_LPUART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in LPUART register
+  * @param  __INSTANCE__ LPUART Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_LPUART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EM_Exported_Macros_Helper Helper Macros
+  * @{
+  */
+
+/**
+  * @brief  Compute LPUARTDIV value according to Peripheral Clock and
+  *         expected Baud Rate (20-bit value of LPUARTDIV is returned)
+  * @param  __PERIPHCLK__ Peripheral Clock frequency used for LPUART Instance
+  * @param  __PRESCALER__ This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_PRESCALER_DIV1
+  *         @arg @ref LL_LPUART_PRESCALER_DIV2
+  *         @arg @ref LL_LPUART_PRESCALER_DIV4
+  *         @arg @ref LL_LPUART_PRESCALER_DIV6
+  *         @arg @ref LL_LPUART_PRESCALER_DIV8
+  *         @arg @ref LL_LPUART_PRESCALER_DIV10
+  *         @arg @ref LL_LPUART_PRESCALER_DIV12
+  *         @arg @ref LL_LPUART_PRESCALER_DIV16
+  *         @arg @ref LL_LPUART_PRESCALER_DIV32
+  *         @arg @ref LL_LPUART_PRESCALER_DIV64
+  *         @arg @ref LL_LPUART_PRESCALER_DIV128
+  *         @arg @ref LL_LPUART_PRESCALER_DIV256
+  * @param  __BAUDRATE__ Baud Rate value to achieve
+  * @retval LPUARTDIV value to be used for BRR register filling
+  */
+#define __LL_LPUART_DIV(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (uint32_t)\
+  ((((((uint64_t)(__PERIPHCLK__)/(uint64_t)(LPUART_PRESCALER_TAB[(uint16_t)(__PRESCALER__)]))\
+      * LPUART_LPUARTDIV_FREQ_MUL) + (uint32_t)((__BAUDRATE__)/2U))/(__BAUDRATE__)) & LPUART_BRR_MASK)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup LPUART_LL_Exported_Functions LPUART Exported Functions
+  * @{
+  */
+
+/** @defgroup LPUART_LL_EF_Configuration Configuration functions
+  * @{
+  */
+
+/**
+  * @brief  LPUART Enable
+  * @rmtoll CR1          UE            LL_LPUART_Enable
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_Enable(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR1, USART_CR1_UE);
+}
+
+/**
+  * @brief  LPUART Disable
+  * @note   When LPUART is disabled, LPUART prescalers and outputs are stopped immediately,
+  *         and current operations are discarded. The configuration of the LPUART is kept, but all the status
+  *         flags, in the LPUARTx_ISR are set to their default values.
+  * @note   In order to go into low-power mode without generating errors on the line,
+  *         the TE bit must be reset before and the software must wait
+  *         for the TC bit in the LPUART_ISR to be set before resetting the UE bit.
+  *         The DMA requests are also reset when UE = 0 so the DMA channel must
+  *         be disabled before resetting the UE bit.
+  * @rmtoll CR1          UE            LL_LPUART_Disable
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_Disable(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR1, USART_CR1_UE);
+}
+
+/**
+  * @brief  Indicate if LPUART is enabled
+  * @rmtoll CR1          UE            LL_LPUART_IsEnabled
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabled(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  FIFO Mode Enable
+  * @rmtoll CR1          FIFOEN        LL_LPUART_EnableFIFO
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableFIFO(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR1, USART_CR1_FIFOEN);
+}
+
+/**
+  * @brief  FIFO Mode Disable
+  * @rmtoll CR1          FIFOEN        LL_LPUART_DisableFIFO
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableFIFO(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR1, USART_CR1_FIFOEN);
+}
+
+/**
+  * @brief  Indicate if FIFO Mode is enabled
+  * @rmtoll CR1          FIFOEN        LL_LPUART_IsEnabledFIFO
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledFIFO(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Configure TX FIFO Threshold
+  * @rmtoll CR3          TXFTCFG       LL_LPUART_SetTXFIFOThreshold
+  * @param  LPUARTx LPUART Instance
+  * @param  Threshold This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetTXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold)
+{
+  ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos);
+}
+
+/**
+  * @brief  Return TX FIFO Threshold Configuration
+  * @rmtoll CR3          TXFTCFG       LL_LPUART_GetTXFIFOThreshold
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetTXFIFOThreshold(USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
+}
+
+/**
+  * @brief  Configure RX FIFO Threshold
+  * @rmtoll CR3          RXFTCFG       LL_LPUART_SetRXFIFOThreshold
+  * @param  LPUARTx LPUART Instance
+  * @param  Threshold This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetRXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold)
+{
+  ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos);
+}
+
+/**
+  * @brief  Return RX FIFO Threshold Configuration
+  * @rmtoll CR3          RXFTCFG       LL_LPUART_GetRXFIFOThreshold
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetRXFIFOThreshold(USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
+}
+
+/**
+  * @brief  Configure TX and RX FIFOs Threshold
+  * @rmtoll CR3          TXFTCFG       LL_LPUART_ConfigFIFOsThreshold\n
+  *         CR3          RXFTCFG       LL_LPUART_ConfigFIFOsThreshold
+  * @param  LPUARTx LPUART Instance
+  * @param  TXThreshold This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
+  * @param  RXThreshold This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ConfigFIFOsThreshold(USART_TypeDef *LPUARTx, uint32_t TXThreshold, uint32_t RXThreshold)
+{
+  ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | \
+                    (RXThreshold << USART_CR3_RXFTCFG_Pos));
+}
+
+/**
+  * @brief  LPUART enabled in STOP Mode
+  * @note   When this function is enabled, LPUART is able to wake up the MCU from Stop mode, provided that
+  *         LPUART clock selection is HSI or LSE in RCC.
+  * @rmtoll CR1          UESM          LL_LPUART_EnableInStopMode
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableInStopMode(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_UESM);
+}
+
+/**
+  * @brief  LPUART disabled in STOP Mode
+  * @note   When this function is disabled, LPUART is not able to wake up the MCU from Stop mode
+  * @rmtoll CR1          UESM          LL_LPUART_DisableInStopMode
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableInStopMode(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_UESM);
+}
+
+/**
+  * @brief  Indicate if LPUART is enabled in STOP Mode
+  *         (able to wake up MCU from Stop mode or not)
+  * @rmtoll CR1          UESM          LL_LPUART_IsEnabledInStopMode
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledInStopMode(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Receiver Enable (Receiver is enabled and begins searching for a start bit)
+  * @rmtoll CR1          RE            LL_LPUART_EnableDirectionRx
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableDirectionRx(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RE);
+}
+
+/**
+  * @brief  Receiver Disable
+  * @rmtoll CR1          RE            LL_LPUART_DisableDirectionRx
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableDirectionRx(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RE);
+}
+
+/**
+  * @brief  Transmitter Enable
+  * @rmtoll CR1          TE            LL_LPUART_EnableDirectionTx
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableDirectionTx(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TE);
+}
+
+/**
+  * @brief  Transmitter Disable
+  * @rmtoll CR1          TE            LL_LPUART_DisableDirectionTx
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableDirectionTx(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TE);
+}
+
+/**
+  * @brief  Configure simultaneously enabled/disabled states
+  *         of Transmitter and Receiver
+  * @rmtoll CR1          RE            LL_LPUART_SetTransferDirection\n
+  *         CR1          TE            LL_LPUART_SetTransferDirection
+  * @param  LPUARTx LPUART Instance
+  * @param  TransferDirection This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_DIRECTION_NONE
+  *         @arg @ref LL_LPUART_DIRECTION_RX
+  *         @arg @ref LL_LPUART_DIRECTION_TX
+  *         @arg @ref LL_LPUART_DIRECTION_TX_RX
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetTransferDirection(USART_TypeDef *LPUARTx, uint32_t TransferDirection)
+{
+  ATOMIC_MODIFY_REG(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
+}
+
+/**
+  * @brief  Return enabled/disabled states of Transmitter and Receiver
+  * @rmtoll CR1          RE            LL_LPUART_GetTransferDirection\n
+  *         CR1          TE            LL_LPUART_GetTransferDirection
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_DIRECTION_NONE
+  *         @arg @ref LL_LPUART_DIRECTION_RX
+  *         @arg @ref LL_LPUART_DIRECTION_TX
+  *         @arg @ref LL_LPUART_DIRECTION_TX_RX
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetTransferDirection(USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE));
+}
+
+/**
+  * @brief  Configure Parity (enabled/disabled and parity mode if enabled)
+  * @note   This function selects if hardware parity control (generation and detection) is enabled or disabled.
+  *         When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position
+  *         (depending on data width) and parity is checked on the received data.
+  * @rmtoll CR1          PS            LL_LPUART_SetParity\n
+  *         CR1          PCE           LL_LPUART_SetParity
+  * @param  LPUARTx LPUART Instance
+  * @param  Parity This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_PARITY_NONE
+  *         @arg @ref LL_LPUART_PARITY_EVEN
+  *         @arg @ref LL_LPUART_PARITY_ODD
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetParity(USART_TypeDef *LPUARTx, uint32_t Parity)
+{
+  MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);
+}
+
+/**
+  * @brief  Return Parity configuration (enabled/disabled and parity mode if enabled)
+  * @rmtoll CR1          PS            LL_LPUART_GetParity\n
+  *         CR1          PCE           LL_LPUART_GetParity
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_PARITY_NONE
+  *         @arg @ref LL_LPUART_PARITY_EVEN
+  *         @arg @ref LL_LPUART_PARITY_ODD
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetParity(USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
+}
+
+/**
+  * @brief  Set Receiver Wake Up method from Mute mode.
+  * @rmtoll CR1          WAKE          LL_LPUART_SetWakeUpMethod
+  * @param  LPUARTx LPUART Instance
+  * @param  Method This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_WAKEUP_IDLELINE
+  *         @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetWakeUpMethod(USART_TypeDef *LPUARTx, uint32_t Method)
+{
+  MODIFY_REG(LPUARTx->CR1, USART_CR1_WAKE, Method);
+}
+
+/**
+  * @brief  Return Receiver Wake Up method from Mute mode
+  * @rmtoll CR1          WAKE          LL_LPUART_GetWakeUpMethod
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_WAKEUP_IDLELINE
+  *         @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetWakeUpMethod(USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_WAKE));
+}
+
+/**
+  * @brief  Set Word length (nb of data bits, excluding start and stop bits)
+  * @rmtoll CR1          M             LL_LPUART_SetDataWidth
+  * @param  LPUARTx LPUART Instance
+  * @param  DataWidth This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_DATAWIDTH_7B
+  *         @arg @ref LL_LPUART_DATAWIDTH_8B
+  *         @arg @ref LL_LPUART_DATAWIDTH_9B
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetDataWidth(USART_TypeDef *LPUARTx, uint32_t DataWidth)
+{
+  MODIFY_REG(LPUARTx->CR1, USART_CR1_M, DataWidth);
+}
+
+/**
+  * @brief  Return Word length (i.e. nb of data bits, excluding start and stop bits)
+  * @rmtoll CR1          M             LL_LPUART_GetDataWidth
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_DATAWIDTH_7B
+  *         @arg @ref LL_LPUART_DATAWIDTH_8B
+  *         @arg @ref LL_LPUART_DATAWIDTH_9B
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetDataWidth(USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_M));
+}
+
+/**
+  * @brief  Allow switch between Mute Mode and Active mode
+  * @rmtoll CR1          MME           LL_LPUART_EnableMuteMode
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableMuteMode(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_MME);
+}
+
+/**
+  * @brief  Prevent Mute Mode use. Set Receiver in active mode permanently.
+  * @rmtoll CR1          MME           LL_LPUART_DisableMuteMode
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableMuteMode(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_MME);
+}
+
+/**
+  * @brief  Indicate if switch between Mute Mode and Active mode is allowed
+  * @rmtoll CR1          MME           LL_LPUART_IsEnabledMuteMode
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledMuteMode(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Configure Clock source prescaler for baudrate generator and oversampling
+  * @rmtoll PRESC        PRESCALER     LL_LPUART_SetPrescaler
+  * @param  LPUARTx LPUART Instance
+  * @param  PrescalerValue This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_PRESCALER_DIV1
+  *         @arg @ref LL_LPUART_PRESCALER_DIV2
+  *         @arg @ref LL_LPUART_PRESCALER_DIV4
+  *         @arg @ref LL_LPUART_PRESCALER_DIV6
+  *         @arg @ref LL_LPUART_PRESCALER_DIV8
+  *         @arg @ref LL_LPUART_PRESCALER_DIV10
+  *         @arg @ref LL_LPUART_PRESCALER_DIV12
+  *         @arg @ref LL_LPUART_PRESCALER_DIV16
+  *         @arg @ref LL_LPUART_PRESCALER_DIV32
+  *         @arg @ref LL_LPUART_PRESCALER_DIV64
+  *         @arg @ref LL_LPUART_PRESCALER_DIV128
+  *         @arg @ref LL_LPUART_PRESCALER_DIV256
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetPrescaler(USART_TypeDef *LPUARTx, uint32_t PrescalerValue)
+{
+  MODIFY_REG(LPUARTx->PRESC, USART_PRESC_PRESCALER, (uint16_t)PrescalerValue);
+}
+
+/**
+  * @brief  Retrieve the Clock source prescaler for baudrate generator and oversampling
+  * @rmtoll PRESC        PRESCALER     LL_LPUART_GetPrescaler
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_PRESCALER_DIV1
+  *         @arg @ref LL_LPUART_PRESCALER_DIV2
+  *         @arg @ref LL_LPUART_PRESCALER_DIV4
+  *         @arg @ref LL_LPUART_PRESCALER_DIV6
+  *         @arg @ref LL_LPUART_PRESCALER_DIV8
+  *         @arg @ref LL_LPUART_PRESCALER_DIV10
+  *         @arg @ref LL_LPUART_PRESCALER_DIV12
+  *         @arg @ref LL_LPUART_PRESCALER_DIV16
+  *         @arg @ref LL_LPUART_PRESCALER_DIV32
+  *         @arg @ref LL_LPUART_PRESCALER_DIV64
+  *         @arg @ref LL_LPUART_PRESCALER_DIV128
+  *         @arg @ref LL_LPUART_PRESCALER_DIV256
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetPrescaler(USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->PRESC, USART_PRESC_PRESCALER));
+}
+
+/**
+  * @brief  Set the length of the stop bits
+  * @rmtoll CR2          STOP          LL_LPUART_SetStopBitsLength
+  * @param  LPUARTx LPUART Instance
+  * @param  StopBits This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_STOPBITS_1
+  *         @arg @ref LL_LPUART_STOPBITS_2
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetStopBitsLength(USART_TypeDef *LPUARTx, uint32_t StopBits)
+{
+  MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);
+}
+
+/**
+  * @brief  Retrieve the length of the stop bits
+  * @rmtoll CR2          STOP          LL_LPUART_GetStopBitsLength
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_STOPBITS_1
+  *         @arg @ref LL_LPUART_STOPBITS_2
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetStopBitsLength(USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_STOP));
+}
+
+/**
+  * @brief  Configure Character frame format (Datawidth, Parity control, Stop Bits)
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Data Width configuration using @ref LL_LPUART_SetDataWidth() function
+  *         - Parity Control and mode configuration using @ref LL_LPUART_SetParity() function
+  *         - Stop bits configuration using @ref LL_LPUART_SetStopBitsLength() function
+  * @rmtoll CR1          PS            LL_LPUART_ConfigCharacter\n
+  *         CR1          PCE           LL_LPUART_ConfigCharacter\n
+  *         CR1          M             LL_LPUART_ConfigCharacter\n
+  *         CR2          STOP          LL_LPUART_ConfigCharacter
+  * @param  LPUARTx LPUART Instance
+  * @param  DataWidth This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_DATAWIDTH_7B
+  *         @arg @ref LL_LPUART_DATAWIDTH_8B
+  *         @arg @ref LL_LPUART_DATAWIDTH_9B
+  * @param  Parity This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_PARITY_NONE
+  *         @arg @ref LL_LPUART_PARITY_EVEN
+  *         @arg @ref LL_LPUART_PARITY_ODD
+  * @param  StopBits This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_STOPBITS_1
+  *         @arg @ref LL_LPUART_STOPBITS_2
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ConfigCharacter(USART_TypeDef *LPUARTx, uint32_t DataWidth, uint32_t Parity,
+                                               uint32_t StopBits)
+{
+  MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);
+  MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);
+}
+
+/**
+  * @brief  Configure TX/RX pins swapping setting.
+  * @rmtoll CR2          SWAP          LL_LPUART_SetTXRXSwap
+  * @param  LPUARTx LPUART Instance
+  * @param  SwapConfig This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_TXRX_STANDARD
+  *         @arg @ref LL_LPUART_TXRX_SWAPPED
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetTXRXSwap(USART_TypeDef *LPUARTx, uint32_t SwapConfig)
+{
+  MODIFY_REG(LPUARTx->CR2, USART_CR2_SWAP, SwapConfig);
+}
+
+/**
+  * @brief  Retrieve TX/RX pins swapping configuration.
+  * @rmtoll CR2          SWAP          LL_LPUART_GetTXRXSwap
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_TXRX_STANDARD
+  *         @arg @ref LL_LPUART_TXRX_SWAPPED
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetTXRXSwap(USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_SWAP));
+}
+
+/**
+  * @brief  Configure RX pin active level logic
+  * @rmtoll CR2          RXINV         LL_LPUART_SetRXPinLevel
+  * @param  LPUARTx LPUART Instance
+  * @param  PinInvMethod This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD
+  *         @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetRXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
+{
+  MODIFY_REG(LPUARTx->CR2, USART_CR2_RXINV, PinInvMethod);
+}
+
+/**
+  * @brief  Retrieve RX pin active level logic configuration
+  * @rmtoll CR2          RXINV         LL_LPUART_GetRXPinLevel
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD
+  *         @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetRXPinLevel(USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_RXINV));
+}
+
+/**
+  * @brief  Configure TX pin active level logic
+  * @rmtoll CR2          TXINV         LL_LPUART_SetTXPinLevel
+  * @param  LPUARTx LPUART Instance
+  * @param  PinInvMethod This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD
+  *         @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetTXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
+{
+  MODIFY_REG(LPUARTx->CR2, USART_CR2_TXINV, PinInvMethod);
+}
+
+/**
+  * @brief  Retrieve TX pin active level logic configuration
+  * @rmtoll CR2          TXINV         LL_LPUART_GetTXPinLevel
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD
+  *         @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetTXPinLevel(USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_TXINV));
+}
+
+/**
+  * @brief  Configure Binary data logic.
+  *
+  * @note   Allow to define how Logical data from the data register are send/received :
+  *         either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)
+  * @rmtoll CR2          DATAINV       LL_LPUART_SetBinaryDataLogic
+  * @param  LPUARTx LPUART Instance
+  * @param  DataLogic This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE
+  *         @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetBinaryDataLogic(USART_TypeDef *LPUARTx, uint32_t DataLogic)
+{
+  MODIFY_REG(LPUARTx->CR2, USART_CR2_DATAINV, DataLogic);
+}
+
+/**
+  * @brief  Retrieve Binary data configuration
+  * @rmtoll CR2          DATAINV       LL_LPUART_GetBinaryDataLogic
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE
+  *         @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetBinaryDataLogic(USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_DATAINV));
+}
+
+/**
+  * @brief  Configure transfer bit order (either Less or Most Significant Bit First)
+  * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.
+  *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.
+  * @rmtoll CR2          MSBFIRST      LL_LPUART_SetTransferBitOrder
+  * @param  LPUARTx LPUART Instance
+  * @param  BitOrder This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_BITORDER_LSBFIRST
+  *         @arg @ref LL_LPUART_BITORDER_MSBFIRST
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetTransferBitOrder(USART_TypeDef *LPUARTx, uint32_t BitOrder)
+{
+  MODIFY_REG(LPUARTx->CR2, USART_CR2_MSBFIRST, BitOrder);
+}
+
+/**
+  * @brief  Return transfer bit order (either Less or Most Significant Bit First)
+  * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.
+  *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.
+  * @rmtoll CR2          MSBFIRST      LL_LPUART_GetTransferBitOrder
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_BITORDER_LSBFIRST
+  *         @arg @ref LL_LPUART_BITORDER_MSBFIRST
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetTransferBitOrder(USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_MSBFIRST));
+}
+
+/**
+  * @brief  Set Address of the LPUART node.
+  * @note   This is used in multiprocessor communication during Mute mode or Stop mode,
+  *         for wake up with address mark detection.
+  * @note   4bits address node is used when 4-bit Address Detection is selected in ADDM7.
+  *         (b7-b4 should be set to 0)
+  *         8bits address node is used when 7-bit Address Detection is selected in ADDM7.
+  *         (This is used in multiprocessor communication during Mute mode or Stop mode,
+  *         for wake up with 7-bit address mark detection.
+  *         The MSB of the character sent by the transmitter should be equal to 1.
+  *         It may also be used for character detection during normal reception,
+  *         Mute mode inactive (for example, end of block detection in ModBus protocol).
+  *         In this case, the whole received character (8-bit) is compared to the ADD[7:0]
+  *         value and CMF flag is set on match)
+  * @rmtoll CR2          ADD           LL_LPUART_ConfigNodeAddress\n
+  *         CR2          ADDM7         LL_LPUART_ConfigNodeAddress
+  * @param  LPUARTx LPUART Instance
+  * @param  AddressLen This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_ADDRESS_DETECT_4B
+  *         @arg @ref LL_LPUART_ADDRESS_DETECT_7B
+  * @param  NodeAddress 4 or 7 bit Address of the LPUART node.
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ConfigNodeAddress(USART_TypeDef *LPUARTx, uint32_t AddressLen, uint32_t NodeAddress)
+{
+  MODIFY_REG(LPUARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7,
+             (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos)));
+}
+
+/**
+  * @brief  Return 8 bit Address of the LPUART node as set in ADD field of CR2.
+  * @note   If 4-bit Address Detection is selected in ADDM7,
+  *         only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)
+  *         If 7-bit Address Detection is selected in ADDM7,
+  *         only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)
+  * @rmtoll CR2          ADD           LL_LPUART_GetNodeAddress
+  * @param  LPUARTx LPUART Instance
+  * @retval Address of the LPUART node (Value between Min_Data=0 and Max_Data=255)
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddress(USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos);
+}
+
+/**
+  * @brief  Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
+  * @rmtoll CR2          ADDM7         LL_LPUART_GetNodeAddressLen
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_ADDRESS_DETECT_4B
+  *         @arg @ref LL_LPUART_ADDRESS_DETECT_7B
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddressLen(USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADDM7));
+}
+
+/**
+  * @brief  Enable RTS HW Flow Control
+  * @rmtoll CR3          RTSE          LL_LPUART_EnableRTSHWFlowCtrl
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableRTSHWFlowCtrl(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR3, USART_CR3_RTSE);
+}
+
+/**
+  * @brief  Disable RTS HW Flow Control
+  * @rmtoll CR3          RTSE          LL_LPUART_DisableRTSHWFlowCtrl
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableRTSHWFlowCtrl(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR3, USART_CR3_RTSE);
+}
+
+/**
+  * @brief  Enable CTS HW Flow Control
+  * @rmtoll CR3          CTSE          LL_LPUART_EnableCTSHWFlowCtrl
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableCTSHWFlowCtrl(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR3, USART_CR3_CTSE);
+}
+
+/**
+  * @brief  Disable CTS HW Flow Control
+  * @rmtoll CR3          CTSE          LL_LPUART_DisableCTSHWFlowCtrl
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableCTSHWFlowCtrl(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSE);
+}
+
+/**
+  * @brief  Configure HW Flow Control mode (both CTS and RTS)
+  * @rmtoll CR3          RTSE          LL_LPUART_SetHWFlowCtrl\n
+  *         CR3          CTSE          LL_LPUART_SetHWFlowCtrl
+  * @param  LPUARTx LPUART Instance
+  * @param  HardwareFlowControl This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_HWCONTROL_NONE
+  *         @arg @ref LL_LPUART_HWCONTROL_RTS
+  *         @arg @ref LL_LPUART_HWCONTROL_CTS
+  *         @arg @ref LL_LPUART_HWCONTROL_RTS_CTS
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetHWFlowCtrl(USART_TypeDef *LPUARTx, uint32_t HardwareFlowControl)
+{
+  MODIFY_REG(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);
+}
+
+/**
+  * @brief  Return HW Flow Control configuration (both CTS and RTS)
+  * @rmtoll CR3          RTSE          LL_LPUART_GetHWFlowCtrl\n
+  *         CR3          CTSE          LL_LPUART_GetHWFlowCtrl
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_HWCONTROL_NONE
+  *         @arg @ref LL_LPUART_HWCONTROL_RTS
+  *         @arg @ref LL_LPUART_HWCONTROL_CTS
+  *         @arg @ref LL_LPUART_HWCONTROL_RTS_CTS
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetHWFlowCtrl(USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
+}
+
+/**
+  * @brief  Enable Overrun detection
+  * @rmtoll CR3          OVRDIS        LL_LPUART_EnableOverrunDetect
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableOverrunDetect(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);
+}
+
+/**
+  * @brief  Disable Overrun detection
+  * @rmtoll CR3          OVRDIS        LL_LPUART_DisableOverrunDetect
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableOverrunDetect(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);
+}
+
+/**
+  * @brief  Indicate if Overrun detection is enabled
+  * @rmtoll CR3          OVRDIS        LL_LPUART_IsEnabledOverrunDetect
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledOverrunDetect(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
+  * @rmtoll CR3          WUS           LL_LPUART_SetWKUPType
+  * @param  LPUARTx LPUART Instance
+  * @param  Type This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS
+  *         @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT
+  *         @arg @ref LL_LPUART_WAKEUP_ON_RXNE
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetWKUPType(USART_TypeDef *LPUARTx, uint32_t Type)
+{
+  MODIFY_REG(LPUARTx->CR3, USART_CR3_WUS, Type);
+}
+
+/**
+  * @brief  Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
+  * @rmtoll CR3          WUS           LL_LPUART_GetWKUPType
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS
+  *         @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT
+  *         @arg @ref LL_LPUART_WAKEUP_ON_RXNE
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetWKUPType(USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_WUS));
+}
+
+/**
+  * @brief  Configure LPUART BRR register for achieving expected Baud Rate value.
+  *
+  * @note   Compute and set LPUARTDIV value in BRR Register (full BRR content)
+  *         according to used Peripheral Clock and expected Baud Rate values
+  * @note   Peripheral clock and Baud Rate values provided as function parameters should be valid
+  *         (Baud rate value != 0).
+  * @note   Provided that LPUARTx_BRR must be > = 0x300 and LPUART_BRR is 20-bit,
+  *         a care should be taken when generating high baud rates using high PeriphClk
+  *         values. PeriphClk must be in the range [3 x BaudRate, 4096 x BaudRate].
+  * @rmtoll BRR          BRR           LL_LPUART_SetBaudRate
+  * @param  LPUARTx LPUART Instance
+  * @param  PeriphClk Peripheral Clock
+  * @param  PrescalerValue This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_PRESCALER_DIV1
+  *         @arg @ref LL_LPUART_PRESCALER_DIV2
+  *         @arg @ref LL_LPUART_PRESCALER_DIV4
+  *         @arg @ref LL_LPUART_PRESCALER_DIV6
+  *         @arg @ref LL_LPUART_PRESCALER_DIV8
+  *         @arg @ref LL_LPUART_PRESCALER_DIV10
+  *         @arg @ref LL_LPUART_PRESCALER_DIV12
+  *         @arg @ref LL_LPUART_PRESCALER_DIV16
+  *         @arg @ref LL_LPUART_PRESCALER_DIV32
+  *         @arg @ref LL_LPUART_PRESCALER_DIV64
+  *         @arg @ref LL_LPUART_PRESCALER_DIV128
+  *         @arg @ref LL_LPUART_PRESCALER_DIV256
+  * @param  BaudRate Baud Rate
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
+                                           uint32_t BaudRate)
+{
+  if (BaudRate != 0U)
+  {
+    LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, PrescalerValue, BaudRate);
+  }
+}
+
+/**
+  * @brief  Return current Baud Rate value, according to LPUARTDIV present in BRR register
+  *         (full BRR content), and to used Peripheral Clock values
+  * @note   In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
+  * @rmtoll BRR          BRR           LL_LPUART_GetBaudRate
+  * @param  LPUARTx LPUART Instance
+  * @param  PeriphClk Peripheral Clock
+  * @param  PrescalerValue This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_PRESCALER_DIV1
+  *         @arg @ref LL_LPUART_PRESCALER_DIV2
+  *         @arg @ref LL_LPUART_PRESCALER_DIV4
+  *         @arg @ref LL_LPUART_PRESCALER_DIV6
+  *         @arg @ref LL_LPUART_PRESCALER_DIV8
+  *         @arg @ref LL_LPUART_PRESCALER_DIV10
+  *         @arg @ref LL_LPUART_PRESCALER_DIV12
+  *         @arg @ref LL_LPUART_PRESCALER_DIV16
+  *         @arg @ref LL_LPUART_PRESCALER_DIV32
+  *         @arg @ref LL_LPUART_PRESCALER_DIV64
+  *         @arg @ref LL_LPUART_PRESCALER_DIV128
+  *         @arg @ref LL_LPUART_PRESCALER_DIV256
+  * @retval Baud Rate
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue)
+{
+  uint32_t lpuartdiv;
+  uint32_t brrresult;
+  uint32_t periphclkpresc = (uint32_t)(PeriphClk / (LPUART_PRESCALER_TAB[(uint16_t)PrescalerValue]));
+
+  lpuartdiv = LPUARTx->BRR & LPUART_BRR_MASK;
+
+  if (lpuartdiv >= LPUART_BRR_MIN_VALUE)
+  {
+    brrresult = (uint32_t)(((uint64_t)(periphclkpresc) * LPUART_LPUARTDIV_FREQ_MUL) / lpuartdiv);
+  }
+  else
+  {
+    brrresult = 0x0UL;
+  }
+
+  return (brrresult);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature
+  * @{
+  */
+
+/**
+  * @brief  Enable Single Wire Half-Duplex mode
+  * @rmtoll CR3          HDSEL         LL_LPUART_EnableHalfDuplex
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableHalfDuplex(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR3, USART_CR3_HDSEL);
+}
+
+/**
+  * @brief  Disable Single Wire Half-Duplex mode
+  * @rmtoll CR3          HDSEL         LL_LPUART_DisableHalfDuplex
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableHalfDuplex(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR3, USART_CR3_HDSEL);
+}
+
+/**
+  * @brief  Indicate if Single Wire Half-Duplex mode is enabled
+  * @rmtoll CR3          HDSEL         LL_LPUART_IsEnabledHalfDuplex
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledHalfDuplex(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature
+  * @{
+  */
+
+/**
+  * @brief  Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
+  * @rmtoll CR1          DEDT          LL_LPUART_SetDEDeassertionTime
+  * @param  LPUARTx LPUART Instance
+  * @param  Time Value between Min_Data=0 and Max_Data=31
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetDEDeassertionTime(USART_TypeDef *LPUARTx, uint32_t Time)
+{
+  MODIFY_REG(LPUARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos);
+}
+
+/**
+  * @brief  Return DEDT (Driver Enable De-Assertion Time)
+  * @rmtoll CR1          DEDT          LL_LPUART_GetDEDeassertionTime
+  * @param  LPUARTx LPUART Instance
+  * @retval Time value expressed on 5 bits ([4:0] bits) : c
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetDEDeassertionTime(USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos);
+}
+
+/**
+  * @brief  Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
+  * @rmtoll CR1          DEAT          LL_LPUART_SetDEAssertionTime
+  * @param  LPUARTx LPUART Instance
+  * @param  Time Value between Min_Data=0 and Max_Data=31
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetDEAssertionTime(USART_TypeDef *LPUARTx, uint32_t Time)
+{
+  MODIFY_REG(LPUARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos);
+}
+
+/**
+  * @brief  Return DEAT (Driver Enable Assertion Time)
+  * @rmtoll CR1          DEAT          LL_LPUART_GetDEAssertionTime
+  * @param  LPUARTx LPUART Instance
+  * @retval Time value expressed on 5 bits ([4:0] bits) : Time Value between Min_Data=0 and Max_Data=31
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetDEAssertionTime(USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos);
+}
+
+/**
+  * @brief  Enable Driver Enable (DE) Mode
+  * @rmtoll CR3          DEM           LL_LPUART_EnableDEMode
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableDEMode(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR3, USART_CR3_DEM);
+}
+
+/**
+  * @brief  Disable Driver Enable (DE) Mode
+  * @rmtoll CR3          DEM           LL_LPUART_DisableDEMode
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableDEMode(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR3, USART_CR3_DEM);
+}
+
+/**
+  * @brief  Indicate if Driver Enable (DE) Mode is enabled
+  * @rmtoll CR3          DEM           LL_LPUART_IsEnabledDEMode
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDEMode(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Select Driver Enable Polarity
+  * @rmtoll CR3          DEP           LL_LPUART_SetDESignalPolarity
+  * @param  LPUARTx LPUART Instance
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_DE_POLARITY_HIGH
+  *         @arg @ref LL_LPUART_DE_POLARITY_LOW
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetDESignalPolarity(USART_TypeDef *LPUARTx, uint32_t Polarity)
+{
+  MODIFY_REG(LPUARTx->CR3, USART_CR3_DEP, Polarity);
+}
+
+/**
+  * @brief  Return Driver Enable Polarity
+  * @rmtoll CR3          DEP           LL_LPUART_GetDESignalPolarity
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_DE_POLARITY_HIGH
+  *         @arg @ref LL_LPUART_DE_POLARITY_LOW
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetDESignalPolarity(USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_DEP));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EF_FLAG_Management FLAG_Management
+  * @{
+  */
+
+/**
+  * @brief  Check if the LPUART Parity Error Flag is set or not
+  * @rmtoll ISR          PE            LL_LPUART_IsActiveFlag_PE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_PE(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART Framing Error Flag is set or not
+  * @rmtoll ISR          FE            LL_LPUART_IsActiveFlag_FE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_FE(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART Noise error detected Flag is set or not
+  * @rmtoll ISR          NE            LL_LPUART_IsActiveFlag_NE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_NE(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART OverRun Error Flag is set or not
+  * @rmtoll ISR          ORE           LL_LPUART_IsActiveFlag_ORE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_ORE(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART IDLE line detected Flag is set or not
+  * @rmtoll ISR          IDLE          LL_LPUART_IsActiveFlag_IDLE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL);
+}
+
+/* Legacy define */
+#define LL_LPUART_IsActiveFlag_RXNE  LL_LPUART_IsActiveFlag_RXNE_RXFNE
+
+/**
+  * @brief  Check if the LPUART Read Data Register or LPUART RX FIFO Not Empty Flag is set or not
+  * @rmtoll ISR          RXNE_RXFNE    LL_LPUART_IsActiveFlag_RXNE_RXFNE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE_RXFNE(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART Transmission Complete Flag is set or not
+  * @rmtoll ISR          TC            LL_LPUART_IsActiveFlag_TC
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL);
+}
+
+/* Legacy define */
+#define LL_LPUART_IsActiveFlag_TXE  LL_LPUART_IsActiveFlag_TXE_TXFNF
+
+/**
+  * @brief  Check if the LPUART Transmit Data Register Empty or LPUART TX FIFO Not Full Flag is set or not
+  * @rmtoll ISR          TXE_TXFNF     LL_LPUART_IsActiveFlag_TXE_TXFNF
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE_TXFNF(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART CTS interrupt Flag is set or not
+  * @rmtoll ISR          CTSIF         LL_LPUART_IsActiveFlag_nCTS
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_nCTS(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART CTS Flag is set or not
+  * @rmtoll ISR          CTS           LL_LPUART_IsActiveFlag_CTS
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CTS(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART Busy Flag is set or not
+  * @rmtoll ISR          BUSY          LL_LPUART_IsActiveFlag_BUSY
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_BUSY(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART Character Match Flag is set or not
+  * @rmtoll ISR          CMF           LL_LPUART_IsActiveFlag_CM
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CM(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART Send Break Flag is set or not
+  * @rmtoll ISR          SBKF          LL_LPUART_IsActiveFlag_SBK
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_SBK(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART Receive Wake Up from mute mode Flag is set or not
+  * @rmtoll ISR          RWU           LL_LPUART_IsActiveFlag_RWU
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RWU(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART Wake Up from stop mode Flag is set or not
+  * @rmtoll ISR          WUF           LL_LPUART_IsActiveFlag_WKUP
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_WKUP(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART Transmit Enable Acknowledge Flag is set or not
+  * @rmtoll ISR          TEACK         LL_LPUART_IsActiveFlag_TEACK
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TEACK(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART Receive Enable Acknowledge Flag is set or not
+  * @rmtoll ISR          REACK         LL_LPUART_IsActiveFlag_REACK
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART TX FIFO Empty Flag is set or not
+  * @rmtoll ISR          TXFE          LL_LPUART_IsActiveFlag_TXFE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFE(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART RX FIFO Full Flag is set or not
+  * @rmtoll ISR          RXFF          LL_LPUART_IsActiveFlag_RXFF
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFF(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART TX FIFO Threshold Flag is set or not
+  * @rmtoll ISR          TXFT          LL_LPUART_IsActiveFlag_TXFT
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFT(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART RX FIFO Threshold Flag is set or not
+  * @rmtoll ISR          RXFT          LL_LPUART_IsActiveFlag_RXFT
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFT(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear Parity Error Flag
+  * @rmtoll ICR          PECF          LL_LPUART_ClearFlag_PE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ClearFlag_PE(USART_TypeDef *LPUARTx)
+{
+  WRITE_REG(LPUARTx->ICR, USART_ICR_PECF);
+}
+
+/**
+  * @brief  Clear Framing Error Flag
+  * @rmtoll ICR          FECF          LL_LPUART_ClearFlag_FE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ClearFlag_FE(USART_TypeDef *LPUARTx)
+{
+  WRITE_REG(LPUARTx->ICR, USART_ICR_FECF);
+}
+
+/**
+  * @brief  Clear Noise detected Flag
+  * @rmtoll ICR          NECF          LL_LPUART_ClearFlag_NE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ClearFlag_NE(USART_TypeDef *LPUARTx)
+{
+  WRITE_REG(LPUARTx->ICR, USART_ICR_NECF);
+}
+
+/**
+  * @brief  Clear OverRun Error Flag
+  * @rmtoll ICR          ORECF         LL_LPUART_ClearFlag_ORE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ClearFlag_ORE(USART_TypeDef *LPUARTx)
+{
+  WRITE_REG(LPUARTx->ICR, USART_ICR_ORECF);
+}
+
+/**
+  * @brief  Clear IDLE line detected Flag
+  * @rmtoll ICR          IDLECF        LL_LPUART_ClearFlag_IDLE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ClearFlag_IDLE(USART_TypeDef *LPUARTx)
+{
+  WRITE_REG(LPUARTx->ICR, USART_ICR_IDLECF);
+}
+
+/**
+  * @brief  Clear Transmission Complete Flag
+  * @rmtoll ICR          TCCF          LL_LPUART_ClearFlag_TC
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ClearFlag_TC(USART_TypeDef *LPUARTx)
+{
+  WRITE_REG(LPUARTx->ICR, USART_ICR_TCCF);
+}
+
+/**
+  * @brief  Clear CTS Interrupt Flag
+  * @rmtoll ICR          CTSCF         LL_LPUART_ClearFlag_nCTS
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ClearFlag_nCTS(USART_TypeDef *LPUARTx)
+{
+  WRITE_REG(LPUARTx->ICR, USART_ICR_CTSCF);
+}
+
+/**
+  * @brief  Clear Character Match Flag
+  * @rmtoll ICR          CMCF          LL_LPUART_ClearFlag_CM
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ClearFlag_CM(USART_TypeDef *LPUARTx)
+{
+  WRITE_REG(LPUARTx->ICR, USART_ICR_CMCF);
+}
+
+/**
+  * @brief  Clear Wake Up from stop mode Flag
+  * @rmtoll ICR          WUCF          LL_LPUART_ClearFlag_WKUP
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ClearFlag_WKUP(USART_TypeDef *LPUARTx)
+{
+  WRITE_REG(LPUARTx->ICR, USART_ICR_WUCF);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EF_IT_Management IT_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable IDLE Interrupt
+  * @rmtoll CR1          IDLEIE        LL_LPUART_EnableIT_IDLE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_IDLE(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
+}
+
+/* Legacy define */
+#define LL_LPUART_EnableIT_RXNE  LL_LPUART_EnableIT_RXNE_RXFNE
+
+/**
+  * @brief  Enable RX Not Empty and RX FIFO Not Empty Interrupt
+  * @rmtoll CR1        RXNEIE_RXFNEIE  LL_LPUART_EnableIT_RXNE_RXFNE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
+}
+
+/**
+  * @brief  Enable Transmission Complete Interrupt
+  * @rmtoll CR1          TCIE          LL_LPUART_EnableIT_TC
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_TC(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TCIE);
+}
+
+/* Legacy define */
+#define LL_LPUART_EnableIT_TXE  LL_LPUART_EnableIT_TXE_TXFNF
+
+/**
+  * @brief  Enable TX Empty and TX FIFO Not Full Interrupt
+  * @rmtoll CR1         TXEIE_TXFNFIE  LL_LPUART_EnableIT_TXE_TXFNF
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_TXE_TXFNF(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
+}
+
+/**
+  * @brief  Enable Parity Error Interrupt
+  * @rmtoll CR1          PEIE          LL_LPUART_EnableIT_PE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_PE(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_PEIE);
+}
+
+/**
+  * @brief  Enable Character Match Interrupt
+  * @rmtoll CR1          CMIE          LL_LPUART_EnableIT_CM
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_CM(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_CMIE);
+}
+
+/**
+  * @brief  Enable TX FIFO Empty Interrupt
+  * @rmtoll CR1          TXFEIE        LL_LPUART_EnableIT_TXFE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_TXFE(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXFEIE);
+}
+
+/**
+  * @brief  Enable RX FIFO Full Interrupt
+  * @rmtoll CR1          RXFFIE        LL_LPUART_EnableIT_RXFF
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_RXFF(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXFFIE);
+}
+
+/**
+  * @brief  Enable Error Interrupt
+  * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
+  *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
+  *         - 0: Interrupt is inhibited
+  *         - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
+  * @rmtoll CR3          EIE           LL_LPUART_EnableIT_ERROR
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_ERROR(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_EIE);
+}
+
+/**
+  * @brief  Enable CTS Interrupt
+  * @rmtoll CR3          CTSIE         LL_LPUART_EnableIT_CTS
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_CTS(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
+}
+
+/**
+  * @brief  Enable Wake Up from Stop Mode Interrupt
+  * @rmtoll CR3          WUFIE         LL_LPUART_EnableIT_WKUP
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_WKUP(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
+}
+
+/**
+  * @brief  Enable TX FIFO Threshold Interrupt
+  * @rmtoll CR3          TXFTIE        LL_LPUART_EnableIT_TXFT
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_TXFT(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_TXFTIE);
+}
+
+/**
+  * @brief  Enable RX FIFO Threshold Interrupt
+  * @rmtoll CR3          RXFTIE        LL_LPUART_EnableIT_RXFT
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_RXFT(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_RXFTIE);
+}
+
+/**
+  * @brief  Disable IDLE Interrupt
+  * @rmtoll CR1          IDLEIE        LL_LPUART_DisableIT_IDLE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_IDLE(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
+}
+
+/* Legacy define */
+#define LL_LPUART_DisableIT_RXNE  LL_LPUART_DisableIT_RXNE_RXFNE
+
+/**
+  * @brief  Disable RX Not Empty and RX FIFO Not Empty Interrupt
+  * @rmtoll CR1        RXNEIE_RXFNEIE  LL_LPUART_DisableIT_RXNE_RXFNE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
+}
+
+/**
+  * @brief  Disable Transmission Complete Interrupt
+  * @rmtoll CR1          TCIE          LL_LPUART_DisableIT_TC
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_TC(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TCIE);
+}
+
+/* Legacy define */
+#define LL_LPUART_DisableIT_TXE  LL_LPUART_DisableIT_TXE_TXFNF
+
+/**
+  * @brief  Disable TX Empty and TX FIFO Not Full Interrupt
+  * @rmtoll CR1        TXEIE_TXFNFIE  LL_LPUART_DisableIT_TXE_TXFNF
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_TXE_TXFNF(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
+}
+
+/**
+  * @brief  Disable Parity Error Interrupt
+  * @rmtoll CR1          PEIE          LL_LPUART_DisableIT_PE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_PE(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_PEIE);
+}
+
+/**
+  * @brief  Disable Character Match Interrupt
+  * @rmtoll CR1          CMIE          LL_LPUART_DisableIT_CM
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_CM(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_CMIE);
+}
+
+/**
+  * @brief  Disable TX FIFO Empty Interrupt
+  * @rmtoll CR1          TXFEIE        LL_LPUART_DisableIT_TXFE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_TXFE(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXFEIE);
+}
+
+/**
+  * @brief  Disable RX FIFO Full Interrupt
+  * @rmtoll CR1          RXFFIE        LL_LPUART_DisableIT_RXFF
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_RXFF(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXFFIE);
+}
+
+/**
+  * @brief  Disable Error Interrupt
+  * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
+  *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
+  *         - 0: Interrupt is inhibited
+  *         - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
+  * @rmtoll CR3          EIE           LL_LPUART_DisableIT_ERROR
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_ERROR(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_EIE);
+}
+
+/**
+  * @brief  Disable CTS Interrupt
+  * @rmtoll CR3          CTSIE         LL_LPUART_DisableIT_CTS
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_CTS(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
+}
+
+/**
+  * @brief  Disable Wake Up from Stop Mode Interrupt
+  * @rmtoll CR3          WUFIE         LL_LPUART_DisableIT_WKUP
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_WKUP(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
+}
+
+/**
+  * @brief  Disable TX FIFO Threshold Interrupt
+  * @rmtoll CR3          TXFTIE        LL_LPUART_DisableIT_TXFT
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_TXFT(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_TXFTIE);
+}
+
+/**
+  * @brief  Disable RX FIFO Threshold Interrupt
+  * @rmtoll CR3          RXFTIE        LL_LPUART_DisableIT_RXFT
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_RXFT(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_RXFTIE);
+}
+
+/**
+  * @brief  Check if the LPUART IDLE Interrupt  source is enabled or disabled.
+  * @rmtoll CR1          IDLEIE        LL_LPUART_IsEnabledIT_IDLE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL);
+}
+
+/* Legacy define */
+#define LL_LPUART_IsEnabledIT_RXNE  LL_LPUART_IsEnabledIT_RXNE_RXFNE
+
+/**
+  * @brief  Check if the LPUART RX Not Empty and LPUART RX FIFO Not Empty Interrupt is enabled or disabled.
+  * @rmtoll CR1        RXNEIE_RXFNEIE  LL_LPUART_IsEnabledIT_RXNE_RXFNE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART Transmission Complete Interrupt is enabled or disabled.
+  * @rmtoll CR1          TCIE          LL_LPUART_IsEnabledIT_TC
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL);
+}
+
+/* Legacy define */
+#define LL_LPUART_IsEnabledIT_TXE  LL_LPUART_IsEnabledIT_TXE_TXFNF
+
+/**
+  * @brief  Check if the LPUART TX Empty and LPUART TX FIFO Not Full Interrupt is enabled or disabled
+  * @rmtoll CR1         TXEIE_TXFNFIE  LL_LPUART_IsEnabledIT_TXE_TXFNF
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE_TXFNF(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART Parity Error Interrupt is enabled or disabled.
+  * @rmtoll CR1          PEIE          LL_LPUART_IsEnabledIT_PE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_PE(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART Character Match Interrupt is enabled or disabled.
+  * @rmtoll CR1          CMIE          LL_LPUART_IsEnabledIT_CM
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART TX FIFO Empty Interrupt is enabled or disabled
+  * @rmtoll CR1          TXFEIE        LL_LPUART_IsEnabledIT_TXFE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFE(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART RX FIFO Full Interrupt is enabled or disabled
+  * @rmtoll CR1          RXFFIE        LL_LPUART_IsEnabledIT_RXFF
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFF(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART Error Interrupt is enabled or disabled.
+  * @rmtoll CR3          EIE           LL_LPUART_IsEnabledIT_ERROR
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_ERROR(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART CTS Interrupt is enabled or disabled.
+  * @rmtoll CR3          CTSIE         LL_LPUART_IsEnabledIT_CTS
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CTS(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART Wake Up from Stop Mode Interrupt is enabled or disabled.
+  * @rmtoll CR3          WUFIE         LL_LPUART_IsEnabledIT_WKUP
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_WKUP(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if LPUART TX FIFO Threshold Interrupt is enabled or disabled
+  * @rmtoll CR3          TXFTIE        LL_LPUART_IsEnabledIT_TXFT
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFT(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if LPUART RX FIFO Threshold Interrupt is enabled or disabled
+  * @rmtoll CR3          RXFTIE        LL_LPUART_IsEnabledIT_RXFT
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFT(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EF_DMA_Management DMA_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable DMA Mode for reception
+  * @rmtoll CR3          DMAR          LL_LPUART_EnableDMAReq_RX
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableDMAReq_RX(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAR);
+}
+
+/**
+  * @brief  Disable DMA Mode for reception
+  * @rmtoll CR3          DMAR          LL_LPUART_DisableDMAReq_RX
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableDMAReq_RX(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAR);
+}
+
+/**
+  * @brief  Check if DMA Mode is enabled for reception
+  * @rmtoll CR3          DMAR          LL_LPUART_IsEnabledDMAReq_RX
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_RX(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable DMA Mode for transmission
+  * @rmtoll CR3          DMAT          LL_LPUART_EnableDMAReq_TX
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableDMAReq_TX(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAT);
+}
+
+/**
+  * @brief  Disable DMA Mode for transmission
+  * @rmtoll CR3          DMAT          LL_LPUART_DisableDMAReq_TX
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableDMAReq_TX(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAT);
+}
+
+/**
+  * @brief  Check if DMA Mode is enabled for transmission
+  * @rmtoll CR3          DMAT          LL_LPUART_IsEnabledDMAReq_TX
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_TX(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable DMA Disabling on Reception Error
+  * @rmtoll CR3          DDRE          LL_LPUART_EnableDMADeactOnRxErr
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableDMADeactOnRxErr(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR3, USART_CR3_DDRE);
+}
+
+/**
+  * @brief  Disable DMA Disabling on Reception Error
+  * @rmtoll CR3          DDRE          LL_LPUART_DisableDMADeactOnRxErr
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableDMADeactOnRxErr(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR3, USART_CR3_DDRE);
+}
+
+/**
+  * @brief  Indicate if DMA Disabling on Reception Error is disabled
+  * @rmtoll CR3          DDRE          LL_LPUART_IsEnabledDMADeactOnRxErr
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMADeactOnRxErr(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get the LPUART data register address used for DMA transfer
+  * @rmtoll RDR          RDR           LL_LPUART_DMA_GetRegAddr\n
+  * @rmtoll TDR          TDR           LL_LPUART_DMA_GetRegAddr
+  * @param  LPUARTx LPUART Instance
+  * @param  Direction This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_DMA_REG_DATA_TRANSMIT
+  *         @arg @ref LL_LPUART_DMA_REG_DATA_RECEIVE
+  * @retval Address of data register
+  */
+__STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(USART_TypeDef *LPUARTx, uint32_t Direction)
+{
+  uint32_t data_reg_addr;
+
+  if (Direction == LL_LPUART_DMA_REG_DATA_TRANSMIT)
+  {
+    /* return address of TDR register */
+    data_reg_addr = (uint32_t) &(LPUARTx->TDR);
+  }
+  else
+  {
+    /* return address of RDR register */
+    data_reg_addr = (uint32_t) &(LPUARTx->RDR);
+  }
+
+  return data_reg_addr;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EF_Data_Management Data_Management
+  * @{
+  */
+
+/**
+  * @brief  Read Receiver Data register (Receive Data value, 8 bits)
+  * @rmtoll RDR          RDR           LL_LPUART_ReceiveData8
+  * @param  LPUARTx LPUART Instance
+  * @retval Time Value between Min_Data=0x00 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint8_t LL_LPUART_ReceiveData8(USART_TypeDef *LPUARTx)
+{
+  return (uint8_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR) & 0xFFU);
+}
+
+/**
+  * @brief  Read Receiver Data register (Receive Data value, 9 bits)
+  * @rmtoll RDR          RDR           LL_LPUART_ReceiveData9
+  * @param  LPUARTx LPUART Instance
+  * @retval Time Value between Min_Data=0x00 and Max_Data=0x1FF
+  */
+__STATIC_INLINE uint16_t LL_LPUART_ReceiveData9(USART_TypeDef *LPUARTx)
+{
+  return (uint16_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR));
+}
+
+/**
+  * @brief  Write in Transmitter Data Register (Transmit Data value, 8 bits)
+  * @rmtoll TDR          TDR           LL_LPUART_TransmitData8
+  * @param  LPUARTx LPUART Instance
+  * @param  Value between Min_Data=0x00 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_TransmitData8(USART_TypeDef *LPUARTx, uint8_t Value)
+{
+  LPUARTx->TDR = Value;
+}
+
+/**
+  * @brief  Write in Transmitter Data Register (Transmit Data value, 9 bits)
+  * @rmtoll TDR          TDR           LL_LPUART_TransmitData9
+  * @param  LPUARTx LPUART Instance
+  * @param  Value between Min_Data=0x00 and Max_Data=0x1FF
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_TransmitData9(USART_TypeDef *LPUARTx, uint16_t Value)
+{
+  LPUARTx->TDR = Value & 0x1FFUL;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EF_Execution Execution
+  * @{
+  */
+
+/**
+  * @brief  Request Break sending
+  * @rmtoll RQR          SBKRQ         LL_LPUART_RequestBreakSending
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_RequestBreakSending(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_SBKRQ);
+}
+
+/**
+  * @brief  Put LPUART in mute mode and set the RWU flag
+  * @rmtoll RQR          MMRQ          LL_LPUART_RequestEnterMuteMode
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_RequestEnterMuteMode(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_MMRQ);
+}
+
+/**
+  * @brief  Request a Receive Data and FIFO flush
+  * @note   Allows to discard the received data without reading them, and avoid an overrun
+  *         condition.
+  * @rmtoll RQR          RXFRQ         LL_LPUART_RequestRxDataFlush
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_RequestRxDataFlush(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_RXFRQ);
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup LPUART_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+ErrorStatus LL_LPUART_DeInit(USART_TypeDef *LPUARTx);
+ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, LL_LPUART_InitTypeDef *LPUART_InitStruct);
+void        LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct);
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* LPUART1 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_LL_LPUART_H */
+
diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_pwr.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_pwr.h
index be137a46..57a7697d 100644
--- a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_pwr.h
+++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_pwr.h
@@ -1,2301 +1,2301 @@
-/**
-  ******************************************************************************
-  * @file    stm32h7xx_ll_pwr.h
-  * @author  MCD Application Team
-  * @brief   Header file of PWR LL module.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32H7xx_LL_PWR_H
-#define STM32H7xx_LL_PWR_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx.h"
-
-/** @addtogroup STM32H7xx_LL_Driver
-  * @{
-  */
-
-#if defined (PWR)
-
-/** @defgroup PWR_LL PWR
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup PWR_LL_Private_Constants PWR Private Constants
-  * @{
-  */
-
-/** @defgroup PWR_LL_WAKEUP_PIN_OFFSET Wake-Up Pins register offsets Defines
-  * @brief    Flags defines which can be used with LL_PWR_WriteReg function
-  * @{
-  */
-/* Wake-Up Pins PWR register offsets */
-#define LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET    2UL
-#define LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK       0x1FU
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-/* Private macros ------------------------------------------------------------*/
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
-  * @{
-  */
-
-/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
-  * @brief    Flags defines which can be used with LL_PWR_WriteReg function
-  * @{
-  */
-#define LL_PWR_FLAG_CPU_CSSF          PWR_CPUCR_CSSF      /*!< Clear flags for CPU  */
-#if defined (DUAL_CORE)
-#define LL_PWR_FLAG_CPU2_CSSF         PWR_CPU2CR_CSSF     /*!< Clear flags for CPU2 */
-#endif /* DUAL_CORE */
-#define LL_PWR_FLAG_WKUPCR_WKUPC6     PWR_WKUPCR_WKUPC6   /*!< Clear PC1 WKUP flag  */
-#if defined (PWR_WKUPCR_WKUPC5)
-#define LL_PWR_FLAG_WKUPCR_WKUPC5     PWR_WKUPCR_WKUPC5   /*!< Clear PI11 WKUP flag */
-#endif /* defined (PWR_WKUPCR_WKUPC5) */
-#define LL_PWR_FLAG_WKUPCR_WKUPC4     PWR_WKUPCR_WKUPC4   /*!< Clear PC13 WKUP flag */
-#if defined (PWR_WKUPCR_WKUPC3)
-#define LL_PWR_FLAG_WKUPCR_WKUPC3     PWR_WKUPCR_WKUPC3   /*!< Clear PI8 WKUP flag  */
-#endif /* defined (PWR_WKUPCR_WKUPC3) */
-#define LL_PWR_FLAG_WKUPCR_WKUPC2     PWR_WKUPCR_WKUPC2   /*!< Clear PA2 WKUP flag  */
-#define LL_PWR_FLAG_WKUPCR_WKUPC1     PWR_WKUPCR_WKUPC1   /*!< Clear PA0 WKUP flag  */
-/**
-  * @}
-  */
-
-/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
-  * @brief    Flags defines which can be used with LL_PWR_ReadReg function
-  * @{
-  */
-#define LL_PWR_FLAG_AVDO              PWR_CSR1_AVDO       /*!< Analog voltage detector output on VDDA flag                          */
-#define LL_PWR_FLAG_PVDO              PWR_CSR1_PVDO       /*!< Programmable voltage detect output flag                              */
-#define LL_PWR_FLAG_ACTVOS            PWR_CSR1_ACTVOS     /*!< Current VOS applied for VCORE voltage scaling flag                   */
-#define LL_PWR_FLAG_ACTVOSRDY         PWR_CSR1_ACTVOSRDY  /*!< Ready bit for current actual used VOS for VCORE voltage scaling flag */
-#if defined (PWR_CSR1_MMCVDO)
-#define LL_PWR_FLAG_MMCVDO            PWR_CSR1_MMCVDO     /*!< Voltage detector output on VDDMMC flag                               */
-#endif /* PWR_CSR1_MMCVDO */
-
-#define LL_PWR_FLAG_TEMPH             PWR_CR2_TEMPH       /*!< Temperature high threshold flag */
-#define LL_PWR_FLAG_TEMPL             PWR_CR2_TEMPL       /*!< Temperature low threshold flag  */
-#define LL_PWR_FLAG_VBATH             PWR_CR2_VBATH       /*!< VBAT high threshold flag        */
-#define LL_PWR_FLAG_VBATL             PWR_CR2_VBATL       /*!< VBAT low threshold flag         */
-#define LL_PWR_FLAG_BRRDY             PWR_CR2_BRRDY       /*!< Backup Regulator ready flag     */
-
-#define LL_PWR_FLAG_USBRDY            PWR_CR3_USB33RDY    /*!< USB supply ready flag           */
-#define LL_PWR_FLAG_SMPSEXTRDY        PWR_CR3_SMPSEXTRDY  /*!< SMPS External supply ready flag */
-
-#if defined (PWR_CPUCR_SBF_D2)
-#define LL_PWR_FLAG_CPU_SBF_D2        PWR_CPUCR_SBF_D2    /*!< D2 domain DSTANDBY Flag  */
-#endif /* PWR_CPUCR_SBF_D2 */
-#if defined (PWR_CPUCR_SBF_D1)
-#define LL_PWR_FLAG_CPU_SBF_D1        PWR_CPUCR_SBF_D1    /*!< D1 domain DSTANDBY Flag  */
-#endif /* PWR_CPUCR_SBF_D1 */
-#define LL_PWR_FLAG_CPU_SBF           PWR_CPUCR_SBF       /*!< System STANDBY Flag      */
-#define LL_PWR_FLAG_CPU_STOPF         PWR_CPUCR_STOPF     /*!< STOP Flag                */
-#if defined (DUAL_CORE)
-#define LL_PWR_FLAG_CPU_HOLD2F        PWR_CPUCR_HOLD2F    /*!< CPU2 in hold wakeup flag */
-#endif /* DUAL_CORE */
-
-#if defined (DUAL_CORE)
-#define LL_PWR_FLAG_CPU2_SBF_D2       PWR_CPU2CR_SBF_D2   /*!< D2 domain DSTANDBY Flag  */
-#define LL_PWR_FLAG_CPU2_SBF_D1       PWR_CPU2CR_SBF_D1   /*!< D1 domain DSTANDBY Flag  */
-#define LL_PWR_FLAG_CPU2_SBF          PWR_CPU2CR_SBF      /*!< System STANDBY Flag      */
-#define LL_PWR_FLAG_CPU2_STOPF        PWR_CPU2CR_STOPF    /*!< STOP Flag                */
-#define LL_PWR_FLAG_CPU2_HOLD1F       PWR_CPU2CR_HOLD1F   /*!< CPU1 in hold wakeup flag */
-#endif /* DUAL_CORE */
-
-#if defined (PWR_CPUCR_PDDS_D2)
-#define LL_PWR_D3CR_VOSRDY            PWR_D3CR_VOSRDY     /*!< Voltage scaling ready flag */
-#else
-#define LL_PWR_SRDCR_VOSRDY           PWR_SRDCR_VOSRDY    /*!< Voltage scaling ready flag */
-#endif /* PWR_CPUCR_PDDS_D2 */
-
-#define LL_PWR_WKUPFR_WKUPF6          PWR_WKUPFR_WKUPF6   /*!< Wakeup flag on PC1  */
-#if defined (PWR_WKUPFR_WKUPF5)
-#define LL_PWR_WKUPFR_WKUPF5          PWR_WKUPFR_WKUPF5   /*!< Wakeup flag on PI11 */
-#endif /* defined (PWR_WKUPFR_WKUPF5) */
-#define LL_PWR_WKUPFR_WKUPF4          PWR_WKUPFR_WKUPF4   /*!< Wakeup flag on PC13 */
-#if defined (PWR_WKUPFR_WKUPF3)
-#define LL_PWR_WKUPFR_WKUPF3          PWR_WKUPFR_WKUPF3   /*!< Wakeup flag on PI8  */
-#endif /* defined (PWR_WKUPFR_WKUPF3) */
-#define LL_PWR_WKUPFR_WKUPF2          PWR_WKUPFR_WKUPF2   /*!< Wakeup flag on PA2  */
-#define LL_PWR_WKUPFR_WKUPF1          PWR_WKUPFR_WKUPF1   /*!< Wakeup flag on PA0  */
-/**
-  * @}
-  */
-
-/** @defgroup PWR_LL_EC_MODE_PWR Power mode
-  * @{
-  */
-#if defined (PWR_CPUCR_PDDS_D2)
-#define LL_PWR_CPU_MODE_D1STOP        0x00000000U           /*!< Enter D1 domain to Stop mode when the CPU enters deepsleep       */
-#define LL_PWR_CPU_MODE_D1STANDBY     PWR_CPUCR_PDDS_D1     /*!< Enter D1 domain to Standby mode when the CPU enters deepsleep    */
-#else
-#define LL_PWR_CPU_MODE_CDSTOP        0x00000000U           /*!< Enter CD domain to Stop mode when the CPU enters deepsleep       */
-#define LL_PWR_CPU_MODE_CDSTOP2       PWR_CPUCR_RETDS_CD    /*!< Enter CD domain to Stop2 mode when the CPU enters deepsleep      */
-#endif /* PWR_CPUCR_PDDS_D2 */
-
-#if defined (PWR_CPUCR_PDDS_D2)
-#define LL_PWR_CPU_MODE_D2STOP        0x00000000U           /*!< Enter D2 domain to Stop mode when the CPU enters deepsleep       */
-#define LL_PWR_CPU_MODE_D2STANDBY     PWR_CPUCR_PDDS_D2     /*!< Enter D2 domain to Standby mode when the CPU enters deepsleep    */
-#endif /* PWR_CPUCR_PDDS_D2 */
-
-#if defined (PWR_CPUCR_PDDS_D2)
-#define LL_PWR_CPU_MODE_D3RUN         PWR_CPUCR_RUN_D3      /*!< Keep system D3 domain in Run mode when the CPU enter deepsleep   */
-#define LL_PWR_CPU_MODE_D3STOP        0x00000000U           /*!< Enter D3 domain to Stop mode when the CPU enters deepsleep       */
-#define LL_PWR_CPU_MODE_D3STANDBY     PWR_CPUCR_PDDS_D3     /*!< Enter D3 domain to Standby mode when the CPU enters deepsleep    */
-#else
-#define LL_PWR_CPU_MODE_SRDRUN        PWR_CPUCR_RUN_SRD     /*!< Keep system SRD domain in Run mode when the CPU enter deepsleep  */
-#define LL_PWR_CPU_MODE_SRDSTOP       0x00000000U           /*!< Enter SRD domain to Stop mode when the CPU enters deepsleep      */
-#define LL_PWR_CPU_MODE_SRDSTANDBY    PWR_CPUCR_PDDS_SRD    /*!< Enter SRD domain to Standby mode when the CPU enters deepsleep   */
-#endif /* PWR_CPUCR_PDDS_D2 */
-
-#if defined (DUAL_CORE)
-#define LL_PWR_CPU2_MODE_D1STOP       0x00000000U           /*!< Enter D1 domain to Stop mode when the CPU2 enters deepsleep      */
-#define LL_PWR_CPU2_MODE_D1STANDBY    PWR_CPU2CR_PDDS_D1    /*!< Enter D1 domain to Standby mode when the CPU2 enters deepsleep   */
-#define LL_PWR_CPU2_MODE_D2STOP       0x00000000U           /*!< Enter D2 domain to Stop mode when the CPU2 enters deepsleep      */
-#define LL_PWR_CPU2_MODE_D2STANDBY    PWR_CPU2CR_PDDS_D2    /*!< Enter D2 domain to Standby mode when the CPU2 enters deepsleep   */
-#define LL_PWR_CPU2_MODE_D3RUN        PWR_CPU2CR_RUN_D3     /*!< Keep system D3 domain in RUN mode when the CPU2 enter deepsleep  */
-#define LL_PWR_CPU2_MODE_D3STOP       0x00000000U           /*!< Enter D3 domain to Stop mode when the CPU2 enters deepsleep      */
-#define LL_PWR_CPU2_MODE_D3STANDBY    PWR_CPU2CR_PDDS_D3    /*!< Enter D3 domain to Standby mode when the CPU2 enter deepsleep    */
-#endif /* DUAL_CORE */
-/**
-  * @}
-  */
-
-/** @defgroup PWR_LL_EC_REGU_VOLTAGE Run mode Regulator Voltage Scaling
-  * @{
-  */
-#if defined (PWR_CPUCR_PDDS_D2)
-#define LL_PWR_REGU_VOLTAGE_SCALE3      PWR_D3CR_VOS_0                    /*!< Select voltage scale 3 */
-#define LL_PWR_REGU_VOLTAGE_SCALE2      PWR_D3CR_VOS_1                    /*!< Select voltage scale 2 */
-#define LL_PWR_REGU_VOLTAGE_SCALE1      (PWR_D3CR_VOS_0 | PWR_D3CR_VOS_1) /*!< Select voltage scale 1 */
-#if defined (SYSCFG_PWRCR_ODEN) /* STM32H74xxx and STM32H75xxx lines */
-#define LL_PWR_REGU_VOLTAGE_SCALE0      (PWR_D3CR_VOS_0 | PWR_D3CR_VOS_1) /*!< Select voltage scale 0 */
-#else
-#define LL_PWR_REGU_VOLTAGE_SCALE0      0x00000000U                       /*!< Select voltage scale 0 */
-#endif /* defined (SYSCFG_PWRCR_ODEN) */
-#else
-#define LL_PWR_REGU_VOLTAGE_SCALE3      0x00000000U                       /*!< Select voltage scale 3 */
-#define LL_PWR_REGU_VOLTAGE_SCALE2      PWR_D3CR_VOS_0                    /*!< Select voltage scale 2 */
-#define LL_PWR_REGU_VOLTAGE_SCALE1      PWR_D3CR_VOS_1                    /*!< Select voltage scale 1 */
-#define LL_PWR_REGU_VOLTAGE_SCALE0      (PWR_D3CR_VOS_0 | PWR_D3CR_VOS_1) /*!< Select voltage scale 0 */
-#endif /* PWR_CPUCR_PDDS_D2 */
-/**
-  * @}
-  */
-
-/** @defgroup PWR_LL_EC_STOP_MODE_REGU_VOLTAGE Stop mode Regulator Voltage Scaling
-  * @{
-  */
-#define LL_PWR_REGU_VOLTAGE_SVOS_SCALE5   PWR_CR1_SVOS_0                    /*!< Select voltage scale 5 when system enters STOP mode */
-#define LL_PWR_REGU_VOLTAGE_SVOS_SCALE4   PWR_CR1_SVOS_1                    /*!< Select voltage scale 4 when system enters STOP mode */
-#define LL_PWR_REGU_VOLTAGE_SVOS_SCALE3   (PWR_CR1_SVOS_0 | PWR_CR1_SVOS_1) /*!< Select voltage scale 3 when system enters STOP mode */
-/**
-  * @}
-  */
-
-/** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE  Regulator Mode In Deep Sleep Mode
-  * @{
-  */
-#define LL_PWR_REGU_DSMODE_MAIN           0x00000000U   /*!< Voltage Regulator in main mode during deepsleep mode      */
-#define LL_PWR_REGU_DSMODE_LOW_POWER      PWR_CR1_LPDS  /*!< Voltage Regulator in low-power mode during deepsleep mode */
-/**
-  * @}
-  */
-
-/** @defgroup PWR_LL_EC_PVDLEVEL Power Digital Voltage Level Detector
-  * @{
-  */
-#define LL_PWR_PVDLEVEL_0   PWR_CR1_PLS_LEV0  /*!< Voltage threshold detected by PVD 1.95 V */
-#define LL_PWR_PVDLEVEL_1   PWR_CR1_PLS_LEV1  /*!< Voltage threshold detected by PVD 2.1 V  */
-#define LL_PWR_PVDLEVEL_2   PWR_CR1_PLS_LEV2  /*!< Voltage threshold detected by PVD 2.25 V */
-#define LL_PWR_PVDLEVEL_3   PWR_CR1_PLS_LEV3  /*!< Voltage threshold detected by PVD 2.4 V  */
-#define LL_PWR_PVDLEVEL_4   PWR_CR1_PLS_LEV4  /*!< Voltage threshold detected by PVD 2.55 V */
-#define LL_PWR_PVDLEVEL_5   PWR_CR1_PLS_LEV5  /*!< Voltage threshold detected by PVD 2.7 V  */
-#define LL_PWR_PVDLEVEL_6   PWR_CR1_PLS_LEV6  /*!< Voltage threshold detected by PVD 2.85 V */
-#define LL_PWR_PVDLEVEL_7   PWR_CR1_PLS_LEV7  /*!< External voltage level on PVD_IN pin, compared to internal VREFINT level. */
-/**
-  * @}
-  */
-
-/** @defgroup PWR_LL_EC_AVDLEVEL Power Analog Voltage Level Detector
-  * @{
-  */
-#define LL_PWR_AVDLEVEL_0   PWR_CR1_ALS_LEV0  /*!< Analog Voltage threshold detected by AVD 1.7 V */
-#define LL_PWR_AVDLEVEL_1   PWR_CR1_ALS_LEV1  /*!< Analog Voltage threshold detected by AVD 2.1 V */
-#define LL_PWR_AVDLEVEL_2   PWR_CR1_ALS_LEV2  /*!< Analog Voltage threshold detected by AVD 2.5 V */
-#define LL_PWR_AVDLEVEL_3   PWR_CR1_ALS_LEV3  /*!< Analog Voltage threshold detected by AVD 2.8 V */
-
-/**
-  * @}
-  */
-
-/** @defgroup PWR_LL_EC_BATT_CHARG_RESISTOR Battery Charge Resistor
-  * @{
-  */
-#define LL_PWR_BATT_CHARG_RESISTOR_5K     0x00000000U   /*!< Charge the Battery through a 5 kO resistor    */
-#define LL_PWR_BATT_CHARGRESISTOR_1_5K    PWR_CR3_VBRS  /*!< Charge the Battery through a 1.5 kO resistor  */
-/**
-  * @}
-  */
-
-/** @defgroup PWR_LL_EC_WAKEUP_PIN  Wakeup Pins
-  * @{
-  */
-#define LL_PWR_WAKEUP_PIN1    PWR_WKUPEPR_WKUPEN1  /*!< Wake-Up pin 1 : PA0  */
-#define LL_PWR_WAKEUP_PIN2    PWR_WKUPEPR_WKUPEN2  /*!< Wake-Up pin 2 : PA2  */
-#if defined (PWR_WKUPEPR_WKUPEN3)
-#define LL_PWR_WAKEUP_PIN3    PWR_WKUPEPR_WKUPEN3  /*!< Wake-Up pin 3 : PI8  */
-#endif /* defined (PWR_WKUPEPR_WKUPEN3) */
-#define LL_PWR_WAKEUP_PIN4    PWR_WKUPEPR_WKUPEN4  /*!< Wake-Up pin 4 : PC13 */
-#if defined (PWR_WKUPEPR_WKUPEN5)
-#define LL_PWR_WAKEUP_PIN5    PWR_WKUPEPR_WKUPEN5  /*!< Wake-Up pin 5 : PI11 */
-#endif /* defined (PWR_WKUPEPR_WKUPEN5) */
-#define LL_PWR_WAKEUP_PIN6    PWR_WKUPEPR_WKUPEN6  /*!< Wake-Up pin 6 : PC1  */
-/**
-  * @}
-  */
-
-/** @defgroup PWR_LL_EC_WAKEUP_PIN_PULL  Wakeup Pins pull configuration
-  * @{
-  */
-#define LL_PWR_WAKEUP_PIN_NOPULL      0x00000000UL   /*!< Configure Wake-Up pin in no pull   */
-#define LL_PWR_WAKEUP_PIN_PULLUP      0x00000001UL   /*!< Configure Wake-Up pin in pull Up   */
-#define LL_PWR_WAKEUP_PIN_PULLDOWN    0x00000002UL   /*!< Configure Wake-Up pin in pull Down */
-/**
-  * @}
-  */
-
-/** @defgroup PWR_LL_EC_SUPPLY_PWR Power supply source configuration
-  * @{
-  */
-#define LL_PWR_LDO_SUPPLY                     PWR_CR3_LDOEN                                                               /*!< Core domains are supplied from the LDO                                                                     */
-#if defined (SMPS)
-#define LL_PWR_DIRECT_SMPS_SUPPLY             PWR_CR3_SMPSEN                                                              /*!< Core domains are supplied from the SMPS                                                                    */
-#define LL_PWR_SMPS_1V8_SUPPLIES_LDO          (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)                      /*!< The SMPS 1.8V output supplies the LDO which supplies the Core domains                                       */
-#define LL_PWR_SMPS_2V5_SUPPLIES_LDO          (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)                      /*!< The SMPS 2.5V output supplies the LDO which supplies the Core domains                                       */
-#define LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO  (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)  /*!< The SMPS 1.8V output supplies an external circuits and the LDO. The Core domains are supplied from the LDO */
-#define LL_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO  (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)  /*!< The SMPS 2.5V output supplies an external circuits and the LDO. The Core domains are supplied from the LDO */
-#define LL_PWR_SMPS_1V8_SUPPLIES_EXT          (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 1.8V output supplies an external source which supplies the Core domains                            */
-#define LL_PWR_SMPS_2V5_SUPPLIES_EXT          (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 2.5V output supplies an external source which supplies the Core domains                            */
-#endif /* SMPS */
-#define LL_PWR_EXTERNAL_SOURCE_SUPPLY         PWR_CR3_BYPASS                                                              /*!< The SMPS and the LDO are Bypassed. The Core domains are supplied from an external source                    */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
-  * @{
-  */
-
-/** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros
-  * @{
-  */
-
-/**
-  * @brief  Write a value in PWR register
-  * @param  __REG__ Register to be written
-  * @param  __VALUE__ Value to be written in the register
-  * @retval None
-  */
-#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
-
-/**
-  * @brief  Read a value in PWR register
-  * @param  __REG__ Register to be read
-  * @retval Register value
-  */
-#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
-  * @{
-  */
-
-/** @defgroup PWR_LL_EF_Configuration Configuration
-  * @{
-  */
-
-  /**
-  * @brief  Set the voltage Regulator mode during deep sleep mode
-  * @rmtoll CR1    LPDS         LL_PWR_SetRegulModeDS
-  * @param  RegulMode This parameter can be one of the following values:
-  *         @arg @ref LL_PWR_REGU_DSMODE_MAIN
-  *         @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode)
-{
-  MODIFY_REG(PWR->CR1, PWR_CR1_LPDS, RegulMode);
-}
-
-/**
-  * @brief  Get the voltage Regulator mode during deep sleep mode
-  * @rmtoll CR1    LPDS         LL_PWR_GetRegulModeDS
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_PWR_REGU_DSMODE_MAIN
-  *         @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
-  */
-__STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void)
-{
-  return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_LPDS));
-}
-
-/**
-  * @brief  Enable Power Voltage Detector
-  * @rmtoll CR1    PVDEN       LL_PWR_EnablePVD
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_EnablePVD(void)
-{
-  SET_BIT(PWR->CR1, PWR_CR1_PVDEN);
-}
-
-/**
-  * @brief  Disable Power Voltage Detector
-  * @rmtoll CR1    PVDEN       LL_PWR_DisablePVD
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_DisablePVD(void)
-{
-  CLEAR_BIT(PWR->CR1, PWR_CR1_PVDEN);
-}
-
-/**
-  * @brief  Check if Power Voltage Detector is enabled
-  * @rmtoll CR1    PVDEN       LL_PWR_IsEnabledPVD
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
-{
-  return ((READ_BIT(PWR->CR1, PWR_CR1_PVDEN) == (PWR_CR1_PVDEN)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Configure the voltage threshold detected by the Power Voltage Detector
-  * @rmtoll CR1    PLS       LL_PWR_SetPVDLevel
-  * @param  PVDLevel This parameter can be one of the following values:
-  *         @arg @ref LL_PWR_PVDLEVEL_0
-  *         @arg @ref LL_PWR_PVDLEVEL_1
-  *         @arg @ref LL_PWR_PVDLEVEL_2
-  *         @arg @ref LL_PWR_PVDLEVEL_3
-  *         @arg @ref LL_PWR_PVDLEVEL_4
-  *         @arg @ref LL_PWR_PVDLEVEL_5
-  *         @arg @ref LL_PWR_PVDLEVEL_6
-  *         @arg @ref LL_PWR_PVDLEVEL_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
-{
-  MODIFY_REG(PWR->CR1, PWR_CR1_PLS, PVDLevel);
-}
-
-/**
-  * @brief  Get the voltage threshold detection
-  * @rmtoll CR1    PLS       LL_PWR_GetPVDLevel
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_PWR_PVDLEVEL_0
-  *         @arg @ref LL_PWR_PVDLEVEL_1
-  *         @arg @ref LL_PWR_PVDLEVEL_2
-  *         @arg @ref LL_PWR_PVDLEVEL_3
-  *         @arg @ref LL_PWR_PVDLEVEL_4
-  *         @arg @ref LL_PWR_PVDLEVEL_5
-  *         @arg @ref LL_PWR_PVDLEVEL_6
-  *         @arg @ref LL_PWR_PVDLEVEL_7
-  */
-__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
-{
-  return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_PLS));
-}
-
-/**
-  * @brief  Enable access to the backup domain
-  * @rmtoll CR1    DBP       LL_PWR_EnableBkUpAccess
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
-{
-  SET_BIT(PWR->CR1, PWR_CR1_DBP);
-}
-
-/**
-  * @brief  Disable access to the backup domain
-  * @rmtoll CR1    DBP       LL_PWR_DisableBkUpAccess
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
-{
-  CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
-}
-
-/**
-  * @brief  Check if the backup domain is enabled
-  * @rmtoll CR1    DBP       LL_PWR_IsEnabledBkUpAccess
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
-{
-  return ((READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable the Flash Power Down in Stop Mode
-  * @rmtoll CR1    FLPS       LL_PWR_EnableFlashPowerDown
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_EnableFlashPowerDown(void)
-{
-  SET_BIT(PWR->CR1, PWR_CR1_FLPS);
-}
-
-/**
-  * @brief  Disable the Flash Power Down in Stop Mode
-  * @rmtoll CR1    FLPS       LL_PWR_DisableFlashPowerDown
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_DisableFlashPowerDown(void)
-{
-  CLEAR_BIT(PWR->CR1, PWR_CR1_FLPS);
-}
-
-/**
-  * @brief  Check if the Flash Power Down in Stop Mode is enabled
-  * @rmtoll CR1    FLPS       LL_PWR_IsEnabledFlashPowerDown
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledFlashPowerDown(void)
-{
-  return ((READ_BIT(PWR->CR1, PWR_CR1_FLPS) == (PWR_CR1_FLPS)) ? 1UL : 0UL);
-}
-
-#if defined (PWR_CR1_BOOSTE)
-/**
-  * @brief  Enable the Analog Voltage Booster (VDDA)
-  * @rmtoll CR1    BOOSTE     LL_PWR_EnableAnalogBooster
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_EnableAnalogBooster(void)
-{
-  SET_BIT(PWR->CR1, PWR_CR1_BOOSTE);
-}
-
-/**
-  * @brief  Disable the Analog Voltage Booster (VDDA)
-  * @rmtoll CR1    BOOSTE     LL_PWR_DisableAnalogBooster
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_DisableAnalogBooster(void)
-{
-  CLEAR_BIT(PWR->CR1, PWR_CR1_BOOSTE);
-}
-
-/**
-  * @brief  Check if the Analog Voltage Booster (VDDA) is enabled
-  * @rmtoll CR1    BOOSTE     LL_PWR_IsEnabledAnalogBooster
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledAnalogBooster(void)
-{
-  return ((READ_BIT(PWR->CR1, PWR_CR1_BOOSTE) == (PWR_CR1_BOOSTE)) ? 1UL : 0UL);
-}
-#endif /* PWR_CR1_BOOSTE */
-
-#if defined (PWR_CR1_AVD_READY)
-/**
-  * @brief  Enable the Analog Voltage Ready to isolate the BOOST IP until VDDA will be ready
-  * @rmtoll CR1    AVD_READY  LL_PWR_EnableAnalogVoltageReady
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_EnableAnalogVoltageReady(void)
-{
-  SET_BIT(PWR->CR1, PWR_CR1_AVD_READY);
-}
-
-/**
-  * @brief  Disable the Analog Voltage Ready (VDDA)
-  * @rmtoll CR1    AVD_READY  LL_PWR_DisableAnalogVoltageReady
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_DisableAnalogVoltageReady(void)
-{
-  CLEAR_BIT(PWR->CR1, PWR_CR1_AVD_READY);
-}
-
-/**
-  * @brief  Check if the Analog Voltage Booster (VDDA) is enabled
-  * @rmtoll CR1    AVD_READY  LL_PWR_IsEnabledAnalogVoltageReady
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledAnalogVoltageReady(void)
-{
-  return ((READ_BIT(PWR->CR1, PWR_CR1_AVD_READY) == (PWR_CR1_AVD_READY)) ? 1UL : 0UL);
-}
-#endif /* PWR_CR1_AVD_READY */
-
-/**
-  * @brief  Set the internal Regulator output voltage in STOP mode
-  * @rmtoll CR1    SVOS       LL_PWR_SetStopModeRegulVoltageScaling
-  * @param  VoltageScaling This parameter can be one of the following values:
-  *         @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE3
-  *         @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE4
-  *         @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE5
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_SetStopModeRegulVoltageScaling(uint32_t VoltageScaling)
-{
-  MODIFY_REG(PWR->CR1, PWR_CR1_SVOS, VoltageScaling);
-}
-
-/**
-  * @brief  Get the internal Regulator output voltage in STOP mode
-  * @rmtoll CR1    SVOS       LL_PWR_GetStopModeRegulVoltageScaling
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE3
-  *         @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE4
-  *         @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE5
-  */
-__STATIC_INLINE uint32_t LL_PWR_GetStopModeRegulVoltageScaling(void)
-{
-  return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_SVOS));
-}
-
-/**
-  * @brief  Enable Analog Power Voltage Detector
-  * @rmtoll CR1    AVDEN       LL_PWR_EnableAVD
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_EnableAVD(void)
-{
-  SET_BIT(PWR->CR1, PWR_CR1_AVDEN);
-}
-
-/**
-  * @brief  Disable Analog Power Voltage Detector
-  * @rmtoll CR1    AVDEN       LL_PWR_DisableAVD
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_DisableAVD(void)
-{
-  CLEAR_BIT(PWR->CR1, PWR_CR1_AVDEN);
-}
-
-/**
-  * @brief  Check if Analog Power Voltage Detector is enabled
-  * @rmtoll CR1    AVDEN       LL_PWR_IsEnabledAVD
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledAVD(void)
-{
-  return ((READ_BIT(PWR->CR1, PWR_CR1_AVDEN) == (PWR_CR1_AVDEN)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Configure the voltage threshold to be detected by the Analog Power Voltage Detector
-  * @rmtoll CR1    ALS       LL_PWR_SetAVDLevel
-  * @param  AVDLevel This parameter can be one of the following values:
-  *         @arg @ref LL_PWR_AVDLEVEL_0
-  *         @arg @ref LL_PWR_AVDLEVEL_1
-  *         @arg @ref LL_PWR_AVDLEVEL_2
-  *         @arg @ref LL_PWR_AVDLEVEL_3
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_SetAVDLevel(uint32_t AVDLevel)
-{
-  MODIFY_REG(PWR->CR1, PWR_CR1_ALS, AVDLevel);
-}
-
-/**
-  * @brief  Get the Analog Voltage threshold to be detected by the Analog Power Voltage Detector
-  * @rmtoll CR1    ALS       LL_PWR_GetAVDLevel
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_PWR_AVDLEVEL_0
-  *         @arg @ref LL_PWR_AVDLEVEL_1
-  *         @arg @ref LL_PWR_AVDLEVEL_2
-  *         @arg @ref LL_PWR_AVDLEVEL_3
-  */
-__STATIC_INLINE uint32_t LL_PWR_GetAVDLevel(void)
-{
-  return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_ALS));
-}
-
-#if defined (PWR_CR1_AXIRAM1SO)
-/**
-  * @brief  Enable the AXI RAM1 shut-off in DStop/DStop2 mode
-  * @rmtoll CR1    AXIRAM1SO     LL_PWR_EnableAXIRAM1ShutOff
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_EnableAXIRAM1ShutOff(void)
-{
-  SET_BIT(PWR->CR1, PWR_CR1_AXIRAM1SO);
-}
-
-/**
-  * @brief  Disable the AXI RAM1 shut-off in DStop/DStop2 mode
-  * @rmtoll CR1    AXIRAM1SO     LL_PWR_DisableAXIRAM1ShutOff
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_DisableAXIRAM1ShutOff(void)
-{
-  CLEAR_BIT(PWR->CR1, PWR_CR1_AXIRAM1SO);
-}
-
-/**
-  * @brief  Check if the AXI RAM1 shut-off in DStop/DStop2 mode is enabled
-  * @rmtoll CR1    AXIRAM1SO     LL_PWR_IsEnabledAXIRAM1ShutOff
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledAXIRAM1ShutOff(void)
-{
-  return ((READ_BIT(PWR->CR1, PWR_CR1_AXIRAM1SO) == (PWR_CR1_AXIRAM1SO)) ? 1UL : 0UL);
-}
-#endif /* PWR_CR1_AXIRAM1SO */
-
-#if defined (PWR_CR1_AXIRAM2SO)
-/**
-  * @brief  Enable the AXI RAM2 shut-off in DStop/DStop2 mode
-  * @rmtoll CR1    AXIRAM2SO     LL_PWR_EnableAXIRAM2ShutOff
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_EnableAXIRAM2ShutOff(void)
-{
-  SET_BIT(PWR->CR1, PWR_CR1_AXIRAM2SO);
-}
-
-/**
-  * @brief  Disable the AXI RAM2 shut-off in DStop/DStop2 mode
-  * @rmtoll CR1    AXIRAM2SO     LL_PWR_DisableAXIRAM2ShutOff
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_DisableAXIRAM2ShutOff(void)
-{
-  CLEAR_BIT(PWR->CR1, PWR_CR1_AXIRAM2SO);
-}
-
-/**
-  * @brief  Check if the AXI RAM2 shut-off in DStop/DStop2 mode is enabled
-  * @rmtoll CR1    AXIRAM2SO     LL_PWR_IsEnabledAXIRAM2ShutOff
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledAXIRAM2ShutOff(void)
-{
-  return ((READ_BIT(PWR->CR1, PWR_CR1_AXIRAM2SO) == (PWR_CR1_AXIRAM2SO)) ? 1UL : 0UL);
-}
-#endif /* PWR_CR1_AXIRAM2SO */
-
-#if defined (PWR_CR1_AXIRAM3SO)
-/**
-  * @brief  Enable the AXI RAM3 shut-off in DStop/DStop2 mode
-  * @rmtoll CR1    AXIRAM3SO     LL_PWR_EnableAXIRAM3ShutOff
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_EnableAXIRAM3ShutOff(void)
-{
-  SET_BIT(PWR->CR1, PWR_CR1_AXIRAM3SO);
-}
-
-/**
-  * @brief  Disable the AXI RAM3 shut-off in DStop/DStop2 mode
-  * @rmtoll CR1    AXIRAM3SO     LL_PWR_DisableAXIRAM3ShutOff
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_DisableAXIRAM3ShutOff(void)
-{
-  CLEAR_BIT(PWR->CR1, PWR_CR1_AXIRAM3SO);
-}
-
-/**
-  * @brief  Check if the AXI RAM3 shut-off in DStop/DStop2 mode is enabled
-  * @rmtoll CR1    AXIRAM3SO     LL_PWR_IsEnabledAXIRAM3ShutOff
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledAXIRAM3ShutOff(void)
-{
-  return ((READ_BIT(PWR->CR1, PWR_CR1_AXIRAM3SO) == (PWR_CR1_AXIRAM3SO)) ? 1UL : 0UL);
-}
-#endif /* PWR_CR1_AXIRAM3SO */
-
-#if defined (PWR_CR1_AHBRAM1SO)
-/**
-  * @brief  Enable the AHB RAM1 shut-off in DStop/DStop2 mode
-  * @rmtoll CR1    AHBRAM1SO     LL_PWR_EnableAHBRAM1ShutOff
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_EnableAHBRAM1ShutOff(void)
-{
-  SET_BIT(PWR->CR1, PWR_CR1_AHBRAM1SO);
-}
-
-/**
-  * @brief  Disable the AHB RAM1 shut-off in DStop/DStop2 mode
-  * @rmtoll CR1    AHBRAM1SO     LL_PWR_DisableAHBRAM1ShutOff
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_DisableAHBRAM1ShutOff(void)
-{
-  CLEAR_BIT(PWR->CR1, PWR_CR1_AHBRAM1SO);
-}
-
-/**
-  * @brief  Check if the AHB RAM1 shut-off in DStop/DStop2 mode is enabled
-  * @rmtoll CR1    AHBRAM1SO     LL_PWR_IsEnabledAHBRAM1ShutOff
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledAHBRAM1ShutOff(void)
-{
-  return ((READ_BIT(PWR->CR1, PWR_CR1_AHBRAM1SO) == (PWR_CR1_AHBRAM1SO)) ? 1UL : 0UL);
-}
-#endif /* PWR_CR1_AHBRAM1SO */
-
-#if defined (PWR_CR1_AHBRAM2SO)
-/**
-  * @brief  Enable the AHB RAM2 shut-off in DStop/DStop2 mode
-  * @rmtoll CR1    AHBRAM2SO     LL_PWR_EnableAHBRAM2ShutOff
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_EnableAHBRAM2ShutOff(void)
-{
-  SET_BIT(PWR->CR1, PWR_CR1_AHBRAM2SO);
-}
-
-/**
-  * @brief  Disable the AHB RAM2 shut-off in DStop/DStop2 mode
-  * @rmtoll CR1    AHBRAM2SO     LL_PWR_DisableAHBRAM2ShutOff
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_DisableAHBRAM2ShutOff(void)
-{
-  CLEAR_BIT(PWR->CR1, PWR_CR1_AHBRAM2SO);
-}
-
-/**
-  * @brief  Check if the AHB RAM2 shut-off in DStop/DStop2 mode is enabled
-  * @rmtoll CR1    AHBRAM2SO     LL_PWR_IsEnabledAHBRAM2ShutOff
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledAHBRAM2ShutOff(void)
-{
-  return ((READ_BIT(PWR->CR1, PWR_CR1_AHBRAM2SO) == (PWR_CR1_AHBRAM2SO)) ? 1UL : 0UL);
-}
-#endif /* PWR_CR1_AHBRAM2SO */
-
-#if defined (PWR_CR1_ITCMSO)
-/**
-  * @brief  Enable the ITCM shut-off in DStop/DStop2 mode
-  * @rmtoll CR1    ITCMSO     LL_PWR_EnableITCMSOShutOff
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_EnableITCMSOShutOff(void)
-{
-  SET_BIT(PWR->CR1, PWR_CR1_ITCMSO);
-}
-
-/**
-  * @brief  Disable the ITCM shut-off in DStop/DStop2 mode
-  * @rmtoll CR1    ITCMSO     LL_PWR_DisableITCMSOShutOff
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_DisableITCMSOShutOff(void)
-{
-  CLEAR_BIT(PWR->CR1, PWR_CR1_ITCMSO);
-}
-
-/**
-  * @brief  Check if the ITCM shut-off in DStop/DStop2 mode is enabled
-  * @rmtoll CR1    ITCMSO     LL_PWR_IsEnabledITCMShutOff
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledITCMShutOff(void)
-{
-  return ((READ_BIT(PWR->CR1, PWR_CR1_ITCMSO) == (PWR_CR1_ITCMSO)) ? 1UL : 0UL);
-}
-#endif /* PWR_CR1_ITCMSO */
-
-#if defined (PWR_CR1_HSITFSO)
-/**
-  * @brief  Enable the USB and FDCAN shut-off in DStop/DStop2 mode
-  * @rmtoll CR1    HSITFSO     LL_PWR_EnableHSITFShutOff
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_EnableHSITFShutOff(void)
-{
-  SET_BIT(PWR->CR1, PWR_CR1_HSITFSO);
-}
-
-/**
-  * @brief  Disable the USB and FDCAN shut-off in DStop/DStop2 mode
-  * @rmtoll CR1    HSITFSO     LL_PWR_DisableHSITFShutOff
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_DisableHSITFShutOff(void)
-{
-  CLEAR_BIT(PWR->CR1, PWR_CR1_HSITFSO);
-}
-
-/**
-  * @brief  Check if the USB and FDCAN shut-off in DStop/DStop2 mode is enabled
-  * @rmtoll CR1    HSITFSO     LL_PWR_IsEnabledHSITFShutOff
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledHSITFShutOff(void)
-{
-  return ((READ_BIT(PWR->CR1, PWR_CR1_HSITFSO) == (PWR_CR1_HSITFSO)) ? 1UL : 0UL);
-}
-#endif /* PWR_CR1_HSITFSO */
-
-#if defined (PWR_CR1_SRDRAMSO)
-/**
-  * @brief  Enable the SRD AHB RAM shut-off in DStop/DStop2 mode
-  * @rmtoll CR1    SRDRAMSO     LL_PWR_EnableSRDRAMShutOff
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_EnableSRDRAMShutOff(void)
-{
-  SET_BIT(PWR->CR1, PWR_CR1_SRDRAMSO);
-}
-
-/**
-  * @brief  Disable the SRD AHB RAM shut-off in DStop/DStop2 mode
-  * @rmtoll CR1    SRDRAMSO     LL_PWR_DisableSRDRAMShutOff
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_DisableSRDRAMShutOff(void)
-{
-  CLEAR_BIT(PWR->CR1, PWR_CR1_SRDRAMSO);
-}
-
-/**
-  * @brief  Check if the SRD AHB RAM shut-off in DStop/DStop2 mode is enabled
-  * @rmtoll CR1    SRDRAMSO     LL_PWR_IsEnabledSRDRAMShutOff
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledSRDRAMShutOff(void)
-{
-  return ((READ_BIT(PWR->CR1, PWR_CR1_SRDRAMSO) == (PWR_CR1_SRDRAMSO)) ? 1UL : 0UL);
-}
-#endif /* PWR_CR1_SRDRAMSO */
-
-/**
-  * @brief  Enable Backup Regulator
-  * @rmtoll CR2    BREN       LL_PWR_EnableBkUpRegulator
-  * @note When set, the Backup Regulator (used to maintain backup SRAM content in Standby and
-  *       VBAT modes) is enabled. If BRE is reset, the backup Regulator is switched off. The backup
-  *       SRAM can still be used but its content will be lost in the Standby and VBAT modes. Once set,
-  *       the application must wait that the Backup Regulator Ready flag (BRR) is set to indicate that
-  *       the data written into the RAM will be maintained in the Standby and VBAT modes.
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_EnableBkUpRegulator(void)
-{
-  SET_BIT(PWR->CR2, PWR_CR2_BREN);
-}
-
-/**
-  * @brief  Disable Backup Regulator
-  * @rmtoll CR2    BREN       LL_PWR_DisableBkUpRegulator
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_DisableBkUpRegulator(void)
-{
-  CLEAR_BIT(PWR->CR2, PWR_CR2_BREN);
-}
-
-/**
-  * @brief  Check if the backup Regulator is enabled
-  * @rmtoll CR2    BREN      LL_PWR_IsEnabledBkUpRegulator
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpRegulator(void)
-{
-  return ((READ_BIT(PWR->CR2, PWR_CR2_BREN) == (PWR_CR2_BREN)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable VBAT and Temperature monitoring
-  * @rmtoll CR2    MONEN       LL_PWR_EnableMonitoring
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_EnableMonitoring(void)
-{
-  SET_BIT(PWR->CR2, PWR_CR2_MONEN);
-}
-
-/**
-  * @brief  Disable VBAT and Temperature monitoring
-  * @rmtoll CR2    MONEN       LL_PWR_DisableMonitoring
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_DisableMonitoring(void)
-{
-  CLEAR_BIT(PWR->CR2, PWR_CR2_MONEN);
-}
-
-/**
-  * @brief  Check if the VBAT and Temperature monitoring is enabled
-  * @rmtoll CR2    MONEN      LL_PWR_IsEnabledMonitoring
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledMonitoring(void)
-{
-  return ((READ_BIT(PWR->CR2, PWR_CR2_MONEN) == (PWR_CR2_MONEN)) ? 1UL : 0UL);
-}
-
-#if defined (SMPS)
-/**
-  * @brief  Configure the PWR supply
-  * @rmtoll CR3          BYPASS          LL_PWR_ConfigSupply
-  * @rmtoll CR3          LDOEN           LL_PWR_ConfigSupply
-  * @rmtoll CR3          SMPSEN          LL_PWR_ConfigSupply
-  * @rmtoll CR3          SMPSEXTHP       LL_PWR_ConfigSupply
-  * @rmtoll CR3          SMPSLEVEL       LL_PWR_ConfigSupply
-  * @param  SupplySource This parameter can be one of the following values:
-  *         @arg @ref LL_PWR_LDO_SUPPLY
-  *         @arg @ref LL_PWR_DIRECT_SMPS_SUPPLY
-  *         @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_LDO
-  *         @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_LDO
-  *         @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO
-  *         @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO
-  *         @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_EXT
-  *         @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_EXT
-  *         @arg @ref LL_PWR_EXTERNAL_SOURCE_SUPPLY
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_ConfigSupply(uint32_t SupplySource)
-{
-  /* Set the power supply configuration */
-  MODIFY_REG(PWR->CR3, (PWR_CR3_SMPSLEVEL | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS), SupplySource);
-}
-#else
-/**
-  * @brief  Configure the PWR supply
-  * @rmtoll CR3          BYPASS          LL_PWR_ConfigSupply
-  * @rmtoll CR3          LDOEN           LL_PWR_ConfigSupply
-  * @rmtoll CR3          SCUEN           LL_PWR_ConfigSupply
-  * @param  SupplySource This parameter can be one of the following values:
-  *         @arg @ref LL_PWR_LDO_SUPPLY
-  *         @arg @ref LL_PWR_EXTERNAL_SOURCE_SUPPLY
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_ConfigSupply(uint32_t SupplySource)
-{
-  /* Set the power supply configuration */
-  MODIFY_REG(PWR->CR3, (PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS), SupplySource);
-}
-#endif /* defined (SMPS) */
-
-#if defined (SMPS)
-/**
-  * @brief  Get the PWR supply
-  * @rmtoll CR3          BYPASS          LL_PWR_GetSupply
-  * @rmtoll CR3          LDOEN           LL_PWR_GetSupply
-  * @rmtoll CR3          SMPSEN          LL_PWR_GetSupply
-  * @rmtoll CR3          SMPSEXTHP       LL_PWR_GetSupply
-  * @rmtoll CR3          SMPSLEVEL       LL_PWR_GetSupply
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_PWR_LDO_SUPPLY
-  *         @arg @ref LL_PWR_DIRECT_SMPS_SUPPLY
-  *         @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_LDO
-  *         @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_LDO
-  *         @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO
-  *         @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO
-  *         @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_EXT
-  *         @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_EXT
-  *         @arg @ref LL_PWR_EXTERNAL_SOURCE_SUPPLY
-  */
-__STATIC_INLINE uint32_t LL_PWR_GetSupply(void)
-{
-  /* Get the power supply configuration */
-  return(uint32_t)(READ_BIT(PWR->CR3, (PWR_CR3_SMPSLEVEL | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)));
-}
-#else
-/**
-  * @brief  Get the PWR supply
-  * @rmtoll CR3          BYPASS          LL_PWR_GetSupply
-  * @rmtoll CR3          LDOEN           LL_PWR_GetSupply
-  * @rmtoll CR3          SCUEN           LL_PWR_GetSupply
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_PWR_LDO_SUPPLY
-  *         @arg @ref LL_PWR_EXTERNAL_SOURCE_SUPPLY
-  */
-__STATIC_INLINE uint32_t LL_PWR_GetSupply(void)
-{
-  /* Get the power supply configuration */
-  return(uint32_t)(READ_BIT(PWR->CR3, (PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)));
-}
-#endif /* defined (SMPS) */
-
-/**
-  * @brief  Enable battery charging
-  * @rmtoll CR3          VBE           LL_PWR_EnableBatteryCharging
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_EnableBatteryCharging(void)
-{
-  SET_BIT(PWR->CR3, PWR_CR3_VBE);
-}
-
-/**
-  * @brief  Disable battery charging
-  * @rmtoll CR3          VBE           LL_PWR_DisableBatteryCharging
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_DisableBatteryCharging(void)
-{
-  CLEAR_BIT(PWR->CR3, PWR_CR3_VBE);
-}
-
-/**
-  * @brief  Check if battery charging is enabled
-  * @rmtoll CR3          VBE           LL_PWR_IsEnabledBatteryCharging
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledBatteryCharging(void)
-{
-  return ((READ_BIT(PWR->CR3, PWR_CR3_VBE) == (PWR_CR3_VBE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Set the Battery charge resistor impedance
-  * @rmtoll CR3          VBRS          LL_PWR_SetBattChargResistor
-  * @param  Resistor This parameter can be one of the following values:
-  *         @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
-  *         @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_SetBattChargResistor(uint32_t Resistor)
-{
-  MODIFY_REG(PWR->CR3, PWR_CR3_VBRS, Resistor);
-}
-
-/**
-  * @brief  Get the Battery charge resistor impedance
-  * @rmtoll CR3          VBRS          LL_PWR_GetBattChargResistor
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
-  *         @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K
-  */
-__STATIC_INLINE uint32_t LL_PWR_GetBattChargResistor(void)
-{
-  return (uint32_t)(READ_BIT(PWR->CR3, PWR_CR3_VBRS));
-}
-
-/**
-  * @brief  Enable the USB regulator
-  * @rmtoll CR3          USBREGEN           LL_PWR_EnableUSBReg
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_EnableUSBReg(void)
-{
-  SET_BIT(PWR->CR3, PWR_CR3_USBREGEN);
-}
-
-/**
-  * @brief  Disable the USB regulator
-  * @rmtoll CR3          USBREGEN           LL_PWR_DisableUSBReg
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_DisableUSBReg(void)
-{
-  CLEAR_BIT(PWR->CR3, PWR_CR3_USBREGEN);
-}
-
-/**
-  * @brief  Check if the USB regulator is enabled
-  * @rmtoll CR3          USBREGEN           LL_PWR_IsEnabledUSBReg
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledUSBReg(void)
-{
-  return ((READ_BIT(PWR->CR3, PWR_CR3_USBREGEN) == (PWR_CR3_USBREGEN)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable the USB voltage detector
-  * @rmtoll CR3          USB33DEN           LL_PWR_EnableUSBVoltageDetector
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_EnableUSBVoltageDetector(void)
-{
-  SET_BIT(PWR->CR3, PWR_CR3_USB33DEN);
-}
-
-/**
-  * @brief  Disable the USB voltage detector
-  * @rmtoll CR3          USB33DEN           LL_PWR_DisableUSBVoltageDetector
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_DisableUSBVoltageDetector(void)
-{
-  CLEAR_BIT(PWR->CR3, PWR_CR3_USB33DEN);
-}
-
-/**
-  * @brief  Check if the USB voltage detector is enabled
-  * @rmtoll CR3          USB33DEN           LL_PWR_IsEnabledUSBVoltageDetector
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledUSBVoltageDetector(void)
-{
-  return ((READ_BIT(PWR->CR3, PWR_CR3_USB33DEN) == (PWR_CR3_USB33DEN)) ? 1UL : 0UL);
-}
-
-#if defined (PWR_CPUCR_PDDS_D2)
-/**
-  * @brief  Set the D1 domain Power Down mode when the CPU enters deepsleep
-  * @rmtoll CPUCR     PDDS_D1       LL_PWR_CPU_SetD1PowerMode
-  * @param  PDMode This parameter can be one of the following values:
-  *         @arg @ref LL_PWR_CPU_MODE_D1STOP
-  *         @arg @ref LL_PWR_CPU_MODE_D1STANDBY
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_CPU_SetD1PowerMode(uint32_t PDMode)
-{
-  MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_D1, PDMode);
-}
-#else
-/**
-  * @brief  Set the CPU domain Power Down mode when the CPU enters deepsleep
-  * @rmtoll CPUCR     RETDS_CD       LL_PWR_CPU_SetCDPowerMode
-  * @param  PDMode This parameter can be one of the following values:
-  *         @arg @ref LL_PWR_CPU_MODE_CDSTOP
-  *         @arg @ref LL_PWR_CPU_MODE_CDSTOP2
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_CPU_SetCDPowerMode(uint32_t PDMode)
-{
-  MODIFY_REG(PWR->CPUCR, PWR_CPUCR_RETDS_CD, PDMode);
-}
-#endif /* PWR_CPUCR_PDDS_D2 */
-
-#if defined (DUAL_CORE)
-/**
-  * @brief  Set the D1 domain Power Down mode when the CPU2 enters deepsleep
-  * @rmtoll CPU2CR     PDDS_D1       LL_PWR_CPU2_SetD1PowerMode
-  * @param  PDMode This parameter can be one of the following values:
-  *         @arg @ref LL_PWR_CPU2_MODE_D1STOP
-  *         @arg @ref LL_PWR_CPU2_MODE_D1STANDBY
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_CPU2_SetD1PowerMode(uint32_t PDMode)
-{
-  MODIFY_REG(PWR->CPU2CR, PWR_CPU2CR_PDDS_D1, PDMode);
-}
-#endif /* DUAL_CORE */
-
-#if defined (PWR_CPUCR_PDDS_D2)
-/**
-  * @brief  Get the D1 Domain Power Down mode when the CPU enters deepsleep
-  * @rmtoll CPUCR     PDDS_D1       LL_PWR_CPU_GetD1PowerMode
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_PWR_CPU_MODE_D1STOP
-  *         @arg @ref LL_PWR_CPU_MODE_D1STANDBY
-  */
-__STATIC_INLINE uint32_t LL_PWR_CPU_GetD1PowerMode(void)
-{
-  return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D1));
-}
-#else
-/**
-  * @brief  Get the CD Domain Power Down mode when the CPU enters deepsleep
-  * @rmtoll CPUCR     RETDS_CD       LL_PWR_CPU_GetCDPowerMode
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_PWR_CPU_MODE_CDSTOP
-  *         @arg @ref LL_PWR_CPU_MODE_CDSTOP2
-  */
-__STATIC_INLINE uint32_t LL_PWR_CPU_GetCDPowerMode(void)
-{
-  return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_RETDS_CD));
-}
-#endif /* PWR_CPUCR_PDDS_D2 */
-
-#if defined (DUAL_CORE)
-/**
-  * @brief  Get the D1 Domain Power Down mode when the CPU2 enters deepsleep
-  * @rmtoll CPU2CR     PDDS_D1       LL_PWR_CPU2_GetD1PowerMode
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_PWR_CPU2_MODE_D1STOP
-  *         @arg @ref LL_PWR_CPU2_MODE_D1STANDBY
-  */
-__STATIC_INLINE uint32_t LL_PWR_CPU2_GetD1PowerMode(void)
-{
-  return (uint32_t)(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_PDDS_D1));
-}
-#endif /* DUAL_CORE */
-
-#if defined (PWR_CPUCR_PDDS_D2)
-/**
-  * @brief  Set the D2 domain Power Down mode when the CPU enters deepsleep
-  * @rmtoll CPUCR     PDDS_D2       LL_PWR_CPU_SetD2PowerMode
-  * @param  PDMode This parameter can be one of the following values:
-  *         @arg @ref LL_PWR_CPU_MODE_D2STOP
-  *         @arg @ref LL_PWR_CPU_MODE_D2STANDBY
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_CPU_SetD2PowerMode(uint32_t PDMode)
-{
-  MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_D2, PDMode);
-}
-#endif /* PWR_CPUCR_PDDS_D2 */
-
-#if defined (DUAL_CORE)
-/**
-  * @brief  Set the D2 domain Power Down mode when the CPU2 enters deepsleep
-  * @rmtoll CPU2CR     PDDS_D2       LL_PWR_CPU2_SetD2PowerMode
-  * @param  PDMode This parameter can be one of the following values:
-  *         @arg @ref LL_PWR_CPU2_MODE_D2STOP
-  *         @arg @ref LL_PWR_CPU2_MODE_D2STANDBY
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_CPU2_SetD2PowerMode(uint32_t PDMode)
-{
-  MODIFY_REG(PWR->CPU2CR, PWR_CPU2CR_PDDS_D2, PDMode);
-}
-#endif /* DUAL_CORE */
-
-#if defined (PWR_CPUCR_PDDS_D2)
-/**
-  * @brief  Get the D2 Domain Power Down mode when the CPU enters deepsleep
-  * @rmtoll CPUCR     PDDS_D2       LL_PWR_CPU_GetD2PowerMode
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_PWR_CPU_MODE_D2STOP
-  *         @arg @ref LL_PWR_CPU_MODE_D2STANDBY
-  */
-__STATIC_INLINE uint32_t LL_PWR_CPU_GetD2PowerMode(void)
-{
-  return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D2));
-}
-#endif /* PWR_CPUCR_PDDS_D2 */
-
-#if defined (DUAL_CORE)
-/**
-  * @brief  Get the D2 Domain Power Down mode when the CPU2 enters deepsleep
-  * @rmtoll CPU2CR     PDDS_D2       LL_PWR_CPU2_GetD2PowerMode
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_PWR_CPU2_MODE_D2STOP
-  *         @arg @ref LL_PWR_CPU2_MODE_D2STANDBY
-  */
-__STATIC_INLINE uint32_t LL_PWR_CPU2_GetD2PowerMode(void)
-{
-  return (uint32_t)(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_PDDS_D2));
-}
-#endif /* DUAL_CORE */
-
-#if defined (PWR_CPUCR_PDDS_D2)
-/**
-  * @brief  Set the D3 domain Power Down mode when the CPU enters deepsleep
-  * @rmtoll CPUCR     PDDS_D3       LL_PWR_CPU_SetD3PowerMode
-  * @param  PDMode This parameter can be one of the following values:
-  *         @arg @ref LL_PWR_CPU_MODE_D3STOP
-  *         @arg @ref LL_PWR_CPU_MODE_D3STANDBY
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_CPU_SetD3PowerMode(uint32_t PDMode)
-{
-  MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_D3 , PDMode);
-}
-#else
-/**
-  * @brief  Set the SRD domain Power Down mode when the CPU enters deepsleep
-  * @rmtoll CPUCR     PDDS_SRD       LL_PWR_CPU_SetSRDPowerMode
-  * @param  PDMode This parameter can be one of the following values:
-  *         @arg @ref LL_PWR_CPU_MODE_SRDSTOP
-  *         @arg @ref LL_PWR_CPU_MODE_SRDSTANDBY
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_CPU_SetSRDPowerMode(uint32_t PDMode)
-{
-  MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_SRD , PDMode);
-}
-#endif /* PWR_CPUCR_PDDS_D2 */
-
-#if defined (DUAL_CORE)
-/**
-  * @brief  Set the D3 domain Power Down mode when the CPU2 enters deepsleep
-  * @rmtoll CPU2CR     PDDS_D3       LL_PWR_CPU2_SetD3PowerMode
-  * @param  PDMode This parameter can be one of the following values:
-  *         @arg @ref LL_PWR_CPU2_MODE_D3STOP
-  *         @arg @ref LL_PWR_CPU2_MODE_D3STANDBY
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_CPU2_SetD3PowerMode(uint32_t PDMode)
-{
-  MODIFY_REG(PWR->CPU2CR, PWR_CPU2CR_PDDS_D3, PDMode);
-}
-#endif /* DUAL_CORE */
-
-#if defined (PWR_CPUCR_PDDS_D2)
-/**
-  * @brief  Get the D3 Domain Power Down mode when the CPU enters deepsleep
-  * @rmtoll CPUCR     PDDS_D3       LL_PWR_CPU_GetD3PowerMode
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_PWR_CPU_MODE_D3STOP
-  *         @arg @ref LL_PWR_CPU_MODE_D3STANDBY
-  */
-__STATIC_INLINE uint32_t LL_PWR_CPU_GetD3PowerMode(void)
-{
-  return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D3));
-}
-#else
-/**
-  * @brief  Get the SRD Domain Power Down mode when the CPU enters deepsleep
-  * @rmtoll CPUCR     PDDS_SRD       LL_PWR_CPU_GetSRDPowerMode
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_PWR_CPU_MODE_SRDSTOP
-  *         @arg @ref LL_PWR_CPU_MODE_SRDSTANDBY
-  */
-__STATIC_INLINE uint32_t LL_PWR_CPU_GetSRDPowerMode(void)
-{
-  return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_SRD));
-}
-#endif /* PWR_CPUCR_PDDS_D2 */
-
-#if defined (DUAL_CORE)
-/**
-  * @brief  Get the D3 Domain Power Down mode when the CPU2 enters deepsleep
-  * @rmtoll CPU2CR     PDDS_D3       LL_PWR_CPU2_GetD3PowerMode
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_PWR_CPU2_MODE_D3STOP
-  *         @arg @ref LL_PWR_CPU2_MODE_D3STANDBY
-  */
-__STATIC_INLINE uint32_t LL_PWR_CPU2_GetD3PowerMode(void)
-{
-  return (uint32_t)(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_PDDS_D3));
-}
-#endif /* DUAL_CORE */
-
-#if defined (DUAL_CORE)
-/**
-  * @brief  Hold the CPU1 and allocated peripherals when exiting from STOP mode
-  * @rmtoll CPU2CR     HOLD1       LL_PWR_HoldCPU1
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_HoldCPU1(void)
-{
-  SET_BIT(PWR->CPU2CR, PWR_CPU2CR_HOLD1);
-}
-
-/**
-  * @brief  Release the CPU1 and allocated peripherals
-  * @rmtoll CPU2CR     HOLD1       LL_PWR_ReleaseCPU1
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_ReleaseCPU1(void)
-{
-  CLEAR_BIT(PWR->CPU2CR, PWR_CPU2CR_HOLD1);
-}
-
-/**
-  * @brief  Ckeck if the CPU1 and allocated peripherals are held
-  * @rmtoll CPU2CR     HOLD1       LL_PWR_IsCPU1Held
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsCPU1Held(void)
-{
-  return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_HOLD1) == (PWR_CPU2CR_HOLD1))  ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Hold the CPU2 and allocated peripherals when exiting from STOP mode
-  * @rmtoll CPUCR     HOLD2       LL_PWR_HoldCPU2
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_HoldCPU2(void)
-{
-  SET_BIT(PWR->CPUCR, PWR_CPUCR_HOLD2);
-}
-
-/**
-  * @brief  Release the CPU2 and allocated peripherals
-  * @rmtoll CPUCR     HOLD2       LL_PWR_ReleaseCPU2
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_ReleaseCPU2(void)
-{
-  CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_HOLD2);
-}
-
-/**
-  * @brief  Ckeck if the CPU2 and allocated peripherals are held
-  * @rmtoll CPUCR     HOLD2       LL_PWR_IsCPU2Held
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsCPU2Held(void)
-{
-  return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_HOLD2) == (PWR_CPUCR_HOLD2)) ? 1UL : 0UL);
-}
-#endif /* DUAL_CORE */
-
-#if defined (PWR_CPUCR_PDDS_D2)
-/**
-  * @brief  D3 domain remains in Run mode regardless of CPU subsystem modes
-  * @rmtoll CPUCR     RUN_D3       LL_PWR_CPU_EnableD3RunInLowPowerMode
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_CPU_EnableD3RunInLowPowerMode(void)
-{
-  SET_BIT(PWR->CPUCR, PWR_CPUCR_RUN_D3);
-}
-#else
-/**
-  * @brief  SRD domain remains in Run mode regardless of CPU subsystem modes
-  * @rmtoll CPUCR     RUN_SRD      LL_PWR_CPU_EnableSRDRunInLowPowerMode
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_CPU_EnableSRDRunInLowPowerMode(void)
-{
-  SET_BIT(PWR->CPUCR, PWR_CPUCR_RUN_SRD);
-}
-#endif /* PWR_CPUCR_PDDS_D2 */
-
-#if defined (DUAL_CORE)
-/**
-  * @brief  D3 domain remains in Run mode regardless of CPU2 subsystem modes
-  * @rmtoll CPU2CR     RUN_D3       LL_PWR_CPU2_EnableD3RunInLowPowerMode
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_CPU2_EnableD3RunInLowPowerMode(void)
-{
-  SET_BIT(PWR->CPU2CR, PWR_CPU2CR_RUN_D3);
-}
-#endif /* DUAL_CORE */
-
-#if defined (PWR_CPUCR_PDDS_D2)
-/**
-  * @brief  D3 domain follows CPU subsystem modes
-  * @rmtoll CPUCR     RUN_D3       LL_PWR_CPU_DisableD3RunInLowPowerMode
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_CPU_DisableD3RunInLowPowerMode(void)
-{
-  CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_RUN_D3);
-}
-#else
-/**
-  * @brief  SRD domain follows CPU subsystem modes
-  * @rmtoll CPUCR     RUN_SRD      LL_PWR_CPU_DisableSRDRunInLowPowerMode
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_CPU_DisableSRDRunInLowPowerMode(void)
-{
-  CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_RUN_SRD);
-}
-#endif /* PWR_CPUCR_PDDS_D2 */
-
-#if defined (DUAL_CORE)
-/**
-  * @brief  D3 domain follows CPU2 subsystem modes
-  * @rmtoll CPU2CR     RUN_D3       LL_PWR_CPU2_DisableD3RunInLowPowerMode
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_CPU2_DisableD3RunInLowPowerMode(void)
-{
-  CLEAR_BIT(PWR->CPU2CR, PWR_CPU2CR_RUN_D3);
-}
-#endif /* DUAL_CORE */
-
-#if defined (PWR_CPUCR_PDDS_D2)
-/**
-  * @brief  Check if D3 is kept in Run mode when CPU enters low power mode
-  * @rmtoll CPUCR     RUN_D3    LL_PWR_CPU_IsEnabledD3RunInLowPowerMode
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_CPU_IsEnabledD3RunInLowPowerMode(void)
-{
-  return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_RUN_D3) == (PWR_CPUCR_RUN_D3)) ? 1UL : 0UL);
-}
-#else
-/**
-  * @brief  Check if SRD is kept in Run mode when CPU enters low power mode
-  * @rmtoll CPUCR     RUN_SRD    LL_PWR_CPU_IsEnabledSRDRunInLowPowerMode
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_CPU_IsEnabledSRDRunInLowPowerMode(void)
-{
-  return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_RUN_SRD) == (PWR_CPUCR_RUN_SRD)) ? 1UL : 0UL);
-}
-#endif /* PWR_CPUCR_PDDS_D2 */
-
-#if defined (DUAL_CORE)
-/**
-  * @brief  Check if D3 is kept in Run mode when CPU2 enters low power mode
-  * @rmtoll CPU2CR     RUN_D3    LL_PWR_CPU2_IsEnabledD3RunInLowPowerMode
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_CPU2_IsEnabledD3RunInLowPowerMode(void)
-{
-  return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_RUN_D3) == (PWR_CPU2CR_RUN_D3)) ? 1UL : 0UL);
-}
-#endif /* DUAL_CORE */
-
-/**
-  * @brief  Set the main internal Regulator output voltage
-  * @rmtoll D3CR    VOS       LL_PWR_SetRegulVoltageScaling
-  * @param  VoltageScaling This parameter can be one of the following values:
-  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE0
-  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
-  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
-  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
-  * @note   For all H7 lines except STM32H7Axxx and STM32H7Bxxx lines, VOS0
-  *         is applied when PWR_D3CR_VOS[1:0] = 0b11 and  SYSCFG_PWRCR_ODEN = 0b1.
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
-{
-#if defined (PWR_CPUCR_PDDS_D2)
-  MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, VoltageScaling);
-#else
-  MODIFY_REG(PWR->SRDCR, PWR_SRDCR_VOS, VoltageScaling);
-#endif /* PWR_CPUCR_PDDS_D2 */
-}
-
-/**
-  * @brief  Get the main internal Regulator output voltage
-  * @rmtoll D3CR    VOS       LL_PWR_GetRegulVoltageScaling
-  * @note   For all H7 lines except STM32H7Axxx and STM32H7Bxxx lines, checking
-  *         VOS0 need the check of PWR_D3CR_VOS[1:0] field and SYSCFG_PWRCR_ODEN bit.
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE0
-  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
-  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
-  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
-  */
-__STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void)
-{
-#if defined (PWR_CPUCR_PDDS_D2)
-  return (uint32_t)(READ_BIT(PWR->D3CR, PWR_D3CR_VOS));
-#else
-  return (uint32_t)(READ_BIT(PWR->SRDCR, PWR_SRDCR_VOS));
-#endif /* PWR_CPUCR_PDDS_D2 */
-}
-
-/**
-  * @brief  Enable the WakeUp PINx functionality
-  * @rmtoll WKUPEPR   WKUPEN1       LL_PWR_EnableWakeUpPin\n
-  *         WKUPEPR   WKUPEN2       LL_PWR_EnableWakeUpPin\n
-  *         WKUPEPR   WKUPEN3       LL_PWR_EnableWakeUpPin\n
-  *         WKUPEPR   WKUPEN4       LL_PWR_EnableWakeUpPin\n
-  *         WKUPEPR   WKUPEN5       LL_PWR_EnableWakeUpPin\n
-  *         WKUPEPR   WKUPEN6       LL_PWR_EnableWakeUpPin
-  * @param  WakeUpPin This parameter can be one of the following values:
-  *         @arg @ref LL_PWR_WAKEUP_PIN1
-  *         @arg @ref LL_PWR_WAKEUP_PIN2
-  *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
-  *         @arg @ref LL_PWR_WAKEUP_PIN4
-  *         @arg @ref LL_PWR_WAKEUP_PIN5 (*)
-  *         @arg @ref LL_PWR_WAKEUP_PIN6
-  *
-  *         (*) value not defined in all devices.
-  *
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
-{
-  SET_BIT(PWR->WKUPEPR, WakeUpPin);
-}
-
-/**
-  * @brief  Disable the WakeUp PINx functionality
-  * @rmtoll WKUPEPR   WKUPEN1       LL_PWR_DisableWakeUpPin\n
-  *         WKUPEPR   WKUPEN2       LL_PWR_DisableWakeUpPin\n
-  *         WKUPEPR   WKUPEN3       LL_PWR_DisableWakeUpPin\n
-  *         WKUPEPR   WKUPEN4       LL_PWR_DisableWakeUpPin\n
-  *         WKUPEPR   WKUPEN5       LL_PWR_DisableWakeUpPin\n
-  *         WKUPEPR   WKUPEN6       LL_PWR_DisableWakeUpPin
-  * @param  WakeUpPin This parameter can be one of the following values:
-  *         @arg @ref LL_PWR_WAKEUP_PIN1
-  *         @arg @ref LL_PWR_WAKEUP_PIN2
-  *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
-  *         @arg @ref LL_PWR_WAKEUP_PIN4
-  *         @arg @ref LL_PWR_WAKEUP_PIN5 (*)
-  *         @arg @ref LL_PWR_WAKEUP_PIN6
-  *
-  *         (*) value not defined in all devices.
-  *
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
-{
-  CLEAR_BIT(PWR->WKUPEPR, WakeUpPin);
-}
-
-/**
-  * @brief  Check if the WakeUp PINx functionality is enabled
-  * @rmtoll WKUPEPR   WKUPEN1       LL_PWR_IsEnabledWakeUpPin\n
-  *         WKUPEPR   WKUPEN2       LL_PWR_IsEnabledWakeUpPin\n
-  *         WKUPEPR   WKUPEN3       LL_PWR_IsEnabledWakeUpPin\n
-  *         WKUPEPR   WKUPEN4       LL_PWR_IsEnabledWakeUpPin\n
-  *         WKUPEPR   WKUPEN5       LL_PWR_IsEnabledWakeUpPin\n
-  *         WKUPEPR   WKUPEN6       LL_PWR_IsEnabledWakeUpPin
-  * @param  WakeUpPin This parameter can be one of the following values:
-  *         @arg @ref LL_PWR_WAKEUP_PIN1
-  *         @arg @ref LL_PWR_WAKEUP_PIN2
-  *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
-  *         @arg @ref LL_PWR_WAKEUP_PIN4
-  *         @arg @ref LL_PWR_WAKEUP_PIN5 (*)
-  *         @arg @ref LL_PWR_WAKEUP_PIN6
-  *
-  *         (*) value not defined in all devices.
-  *
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
-{
-  return ((READ_BIT(PWR->WKUPEPR, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Set the Wake-Up pin polarity low for the event detection
-  * @rmtoll WKUPEPR   WKUPP1       LL_PWR_SetWakeUpPinPolarityLow\n
-  *         WKUPEPR   WKUPP2       LL_PWR_SetWakeUpPinPolarityLow\n
-  *         WKUPEPR   WKUPP3       LL_PWR_SetWakeUpPinPolarityLow\n
-  *         WKUPEPR   WKUPP4       LL_PWR_SetWakeUpPinPolarityLow\n
-  *         WKUPEPR   WKUPP5       LL_PWR_SetWakeUpPinPolarityLow\n
-  *         WKUPEPR   WKUPP6       LL_PWR_SetWakeUpPinPolarityLow
-  * @param  WakeUpPin This parameter can be one of the following values:
-  *         @arg @ref LL_PWR_WAKEUP_PIN1
-  *         @arg @ref LL_PWR_WAKEUP_PIN2
-  *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
-  *         @arg @ref LL_PWR_WAKEUP_PIN4
-  *         @arg @ref LL_PWR_WAKEUP_PIN5 (*)
-  *         @arg @ref LL_PWR_WAKEUP_PIN6
-  *
-  *         (*) value not defined in all devices.
-  *
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)
-{
-  SET_BIT(PWR->WKUPEPR, (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos));
-}
-
-/**
-  * @brief  Set the Wake-Up pin polarity high for the event detection
-  * @rmtoll WKUPEPR   WKUPP1       LL_PWR_SetWakeUpPinPolarityHigh\n
-  *         WKUPEPR   WKUPP2       LL_PWR_SetWakeUpPinPolarityHigh\n
-  *         WKUPEPR   WKUPP3       LL_PWR_SetWakeUpPinPolarityHigh\n
-  *         WKUPEPR   WKUPP4       LL_PWR_SetWakeUpPinPolarityHigh\n
-  *         WKUPEPR   WKUPP5       LL_PWR_SetWakeUpPinPolarityHigh\n
-  *         WKUPEPR   WKUPP6       LL_PWR_SetWakeUpPinPolarityHigh
-  * @param  WakeUpPin This parameter can be one of the following values:
-  *         @arg @ref LL_PWR_WAKEUP_PIN1
-  *         @arg @ref LL_PWR_WAKEUP_PIN2
-  *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
-  *         @arg @ref LL_PWR_WAKEUP_PIN4
-  *         @arg @ref LL_PWR_WAKEUP_PIN5 (*)
-  *         @arg @ref LL_PWR_WAKEUP_PIN6
-  *
-  *         (*) value not defined in all devices.
-  *
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)
-{
-  CLEAR_BIT(PWR->WKUPEPR, (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos));
-}
-
-/**
-  * @brief  Get the Wake-Up pin polarity for the event detection
-  * @rmtoll WKUPEPR   WKUPP1       LL_PWR_IsWakeUpPinPolarityLow\n
-  *         WKUPEPR   WKUPP2       LL_PWR_IsWakeUpPinPolarityLow\n
-  *         WKUPEPR   WKUPP3       LL_PWR_IsWakeUpPinPolarityLow\n
-  *         WKUPEPR   WKUPP4       LL_PWR_IsWakeUpPinPolarityLow\n
-  *         WKUPEPR   WKUPP5       LL_PWR_IsWakeUpPinPolarityLow\n
-  *         WKUPEPR   WKUPP6       LL_PWR_IsWakeUpPinPolarityLow
-  * @param  WakeUpPin This parameter can be one of the following values:
-  *         @arg @ref LL_PWR_WAKEUP_PIN1
-  *         @arg @ref LL_PWR_WAKEUP_PIN2
-  *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
-  *         @arg @ref LL_PWR_WAKEUP_PIN4
-  *         @arg @ref LL_PWR_WAKEUP_PIN5 (*)
-  *         @arg @ref LL_PWR_WAKEUP_PIN6
-  *
-  *         (*) value not defined in all devices.
-  *
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)
-{
-  return ((READ_BIT(PWR->WKUPEPR, (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos)) == (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Set the Wake-Up pin Pull None
-  * @rmtoll WKUPEPR   WKUPPUPD1       LL_PWR_SetWakeUpPinPullNone\n
-  *         WKUPEPR   WKUPPUPD2       LL_PWR_SetWakeUpPinPullNone\n
-  *         WKUPEPR   WKUPPUPD3       LL_PWR_SetWakeUpPinPullNone\n
-  *         WKUPEPR   WKUPPUPD4       LL_PWR_SetWakeUpPinPullNone\n
-  *         WKUPEPR   WKUPPUPD5       LL_PWR_SetWakeUpPinPullNone\n
-  *         WKUPEPR   WKUPPUPD6       LL_PWR_SetWakeUpPinPullNone
-  * @param  WakeUpPin This parameter can be one of the following values:
-  *         @arg @ref LL_PWR_WAKEUP_PIN1
-  *         @arg @ref LL_PWR_WAKEUP_PIN2
-  *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
-  *         @arg @ref LL_PWR_WAKEUP_PIN4
-  *         @arg @ref LL_PWR_WAKEUP_PIN5 (*)
-  *         @arg @ref LL_PWR_WAKEUP_PIN6
-  *
-  *         (*) value not defined in all devices.
-  *
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_SetWakeUpPinPullNone(uint32_t WakeUpPin)
-{
-  MODIFY_REG(PWR->WKUPEPR, \
-            (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)), \
-            (LL_PWR_WAKEUP_PIN_NOPULL << ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));
-}
-
-/**
-  * @brief  Set the Wake-Up pin Pull Up
-  * @rmtoll WKUPEPR   WKUPPUPD1       LL_PWR_SetWakeUpPinPullUp\n
-  *         WKUPEPR   WKUPPUPD2       LL_PWR_SetWakeUpPinPullUp\n
-  *         WKUPEPR   WKUPPUPD3       LL_PWR_SetWakeUpPinPullUp\n
-  *         WKUPEPR   WKUPPUPD4       LL_PWR_SetWakeUpPinPullUp\n
-  *         WKUPEPR   WKUPPUPD5       LL_PWR_SetWakeUpPinPullUp\n
-  *         WKUPEPR   WKUPPUPD6       LL_PWR_SetWakeUpPinPullUp
-  * @param  WakeUpPin This parameter can be one of the following values:
-  *         @arg @ref LL_PWR_WAKEUP_PIN1
-  *         @arg @ref LL_PWR_WAKEUP_PIN2
-  *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
-  *         @arg @ref LL_PWR_WAKEUP_PIN4
-  *         @arg @ref LL_PWR_WAKEUP_PIN5 (*)
-  *         @arg @ref LL_PWR_WAKEUP_PIN6
-  *
-  *         (*) value not defined in all devices.
-  *
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_SetWakeUpPinPullUp(uint32_t WakeUpPin)
-{
-  MODIFY_REG(PWR->WKUPEPR, \
-            (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)), \
-            (LL_PWR_WAKEUP_PIN_PULLUP << ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));
-}
-
-/**
-  * @brief  Set the Wake-Up pin Pull Down
-  * @rmtoll WKUPEPR   WKUPPUPD1       LL_PWR_SetWakeUpPinPullDown\n
-  *         WKUPEPR   WKUPPUPD2       LL_PWR_SetWakeUpPinPullDown\n
-  *         WKUPEPR   WKUPPUPD3       LL_PWR_SetWakeUpPinPullDown\n
-  *         WKUPEPR   WKUPPUPD4       LL_PWR_SetWakeUpPinPullDown\n
-  *         WKUPEPR   WKUPPUPD5       LL_PWR_SetWakeUpPinPullDown\n
-  *         WKUPEPR   WKUPPUPD6       LL_PWR_SetWakeUpPinPullDown
-  * @param  WakeUpPin This parameter can be one of the following values:
-  *         @arg @ref LL_PWR_WAKEUP_PIN1
-  *         @arg @ref LL_PWR_WAKEUP_PIN2
-  *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
-  *         @arg @ref LL_PWR_WAKEUP_PIN4
-  *         @arg @ref LL_PWR_WAKEUP_PIN5 (*)
-  *         @arg @ref LL_PWR_WAKEUP_PIN6
-  *
-  *         (*) value not defined in all devices.
-  *
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_SetWakeUpPinPullDown(uint32_t WakeUpPin)
-{
-  MODIFY_REG(PWR->WKUPEPR, \
-            (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)), \
-            (LL_PWR_WAKEUP_PIN_PULLDOWN << ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));
-}
-
-/**
-  * @brief  Get the Wake-Up pin pull
-  * @rmtoll WKUPEPR   WKUPPUPD1       LL_PWR_GetWakeUpPinPull\n
-  *         WKUPEPR   WKUPPUPD2       LL_PWR_GetWakeUpPinPull\n
-  *         WKUPEPR   WKUPPUPD3       LL_PWR_GetWakeUpPinPull\n
-  *         WKUPEPR   WKUPPUPD4       LL_PWR_GetWakeUpPinPull\n
-  *         WKUPEPR   WKUPPUPD5       LL_PWR_GetWakeUpPinPull\n
-  *         WKUPEPR   WKUPPUPD6       LL_PWR_GetWakeUpPinPull
-  * @param  WakeUpPin This parameter can be one of the following values:
-  *         @arg @ref LL_PWR_WAKEUP_PIN1
-  *         @arg @ref LL_PWR_WAKEUP_PIN2
-  *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
-  *         @arg @ref LL_PWR_WAKEUP_PIN4
-  *         @arg @ref LL_PWR_WAKEUP_PIN5 (*)
-  *         @arg @ref LL_PWR_WAKEUP_PIN6
-  *
-  *         (*) value not defined in all devices.
-  *
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_PWR_WAKEUP_PIN_NOPULL
-  *         @arg @ref LL_PWR_WAKEUP_PIN_PULLUP
-  *         @arg @ref LL_PWR_WAKEUP_PIN_PULLDOWN
-  */
-__STATIC_INLINE uint32_t LL_PWR_GetWakeUpPinPull(uint32_t WakeUpPin)
-{
-  uint32_t regValue = READ_BIT(PWR->WKUPEPR, (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));
-
-  return (uint32_t)(regValue >> ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
-  * @{
-  */
-
-/**
-  * @brief  Indicate whether VDD voltage is below the selected PVD threshold
-  * @rmtoll CSR1   PVDO       LL_PWR_IsActiveFlag_PVDO
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
-{
-  return ((READ_BIT(PWR->CSR1, PWR_CSR1_PVDO) == (PWR_CSR1_PVDO)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicate whether the voltage level is ready for current actual used VOS
-  * @rmtoll CSR1   ACTVOSRDY       LL_PWR_IsActiveFlag_ACTVOS
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_ACTVOS(void)
-{
-  return ((READ_BIT(PWR->CSR1, PWR_CSR1_ACTVOSRDY) == (PWR_CSR1_ACTVOSRDY)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicate whether VDDA voltage is below the selected AVD threshold
-  * @rmtoll CSR1   AVDO       LL_PWR_IsActiveFlag_AVDO
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_AVDO(void)
-{
-  return ((READ_BIT(PWR->CSR1, PWR_CSR1_AVDO) == (PWR_CSR1_AVDO)) ? 1UL : 0UL);
-}
-
-#if defined (PWR_CSR1_MMCVDO)
-/**
-  * @brief  Indicate whether VDDMMC voltage is below 1V2
-  * @rmtoll CSR1   MMCVDO     LL_PWR_IsActiveFlag_MMCVDO
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_MMCVDO(void)
-{
-  return ((READ_BIT(PWR->CSR1, PWR_CSR1_MMCVDO) == (PWR_CSR1_MMCVDO)) ? 1UL : 0UL);
-}
-#endif /* PWR_CSR1_MMCVDO */
-
-/**
-  * @brief  Get Backup Regulator ready Flag
-  * @rmtoll CR2   BRRDY       LL_PWR_IsActiveFlag_BRR
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BRR(void)
-{
-  return ((READ_BIT(PWR->CR2, PWR_CR2_BRRDY) == (PWR_CR2_BRRDY)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicate whether the VBAT level is above or below low threshold
-  * @rmtoll CR2   VBATL       LL_PWR_IsActiveFlag_VBATL
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VBATL(void)
-{
-  return ((READ_BIT(PWR->CR2, PWR_CR2_VBATL) == (PWR_CR2_VBATL)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicate whether the VBAT level is above or below high threshold
-  * @rmtoll CR2   VBATH       LL_PWR_IsActiveFlag_VBATH
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VBATH(void)
-{
-  return ((READ_BIT(PWR->CR2, PWR_CR2_VBATH) == (PWR_CR2_VBATH)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicate whether the CPU temperature level is above or below low threshold
-  * @rmtoll CR2   TEMPL       LL_PWR_IsActiveFlag_TEMPL
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_TEMPL(void)
-{
-  return ((READ_BIT(PWR->CR2, PWR_CR2_TEMPL) == (PWR_CR2_TEMPL)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicate whether the CPU temperature level is above or below high threshold
-  * @rmtoll CR2   TEMPH       LL_PWR_IsActiveFlag_TEMPH
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_TEMPH(void)
-{
-  return ((READ_BIT(PWR->CR2, PWR_CR2_TEMPH) == (PWR_CR2_TEMPH)) ? 1UL : 0UL);
-}
-
-#if defined (SMPS)
-/**
-  * @brief  Indicate whether the SMPS external supply is ready or not
-  * @rmtoll CR3   SMPSEXTRDY       LL_PWR_IsActiveFlag_SMPSEXT
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SMPSEXT(void)
-{
-  return ((READ_BIT(PWR->CR3, PWR_CR3_SMPSEXTRDY) == (PWR_CR3_SMPSEXTRDY)) ? 1UL : 0UL);
-}
-#endif /* SMPS */
-
-/**
-  * @brief  Indicate whether the USB supply is ready or not
-  * @rmtoll CR3   USBRDY       LL_PWR_IsActiveFlag_USB
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_USB(void)
-{
-  return ((READ_BIT(PWR->CR3, PWR_CR3_USB33RDY) == (PWR_CR3_USB33RDY)) ? 1UL : 0UL);
-}
-
-#if defined (DUAL_CORE)
-/**
-  * @brief  Get HOLD2 Flag
-  * @rmtoll CPUCR   HOLD2F       LL_PWR_IsActiveFlag_HOLD2
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_HOLD2(void)
-{
-  return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_HOLD2F) == (PWR_CPUCR_HOLD2F)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get HOLD1 Flag
-  * @rmtoll CPU2CR   HOLD1F       LL_PWR_IsActiveFlag_HOLD1
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_HOLD1(void)
-{
-  return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_HOLD1F) == (PWR_CPU2CR_HOLD1F)) ? 1UL : 0UL);
-}
-#endif /* DUAL_CORE */
-
-/**
-  * @brief  Get CPU System Stop Flag
-  * @rmtoll CPUCR   STOPF       LL_PWR_CPU_IsActiveFlag_STOP
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_CPU_IsActiveFlag_STOP(void)
-{
-  return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_STOPF) == (PWR_CPUCR_STOPF)) ? 1UL : 0UL);
-}
-
-#if defined (DUAL_CORE)
-/**
-  * @brief  Get CPU2 System Stop Flag
-  * @rmtoll CPU2CR   STOPF       LL_PWR_CPU2_IsActiveFlag_STOP
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_CPU2_IsActiveFlag_STOP(void)
-{
-  return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_STOPF) == (PWR_CPU2CR_STOPF)) ? 1UL : 0UL);
-}
-#endif /* DUAL_CORE */
-
-/**
-  * @brief  Get CPU System Standby Flag
-  * @rmtoll CPUCR   SBF       LL_PWR_CPU_IsActiveFlag_SB
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_CPU_IsActiveFlag_SB(void)
-{
-  return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF) == (PWR_CPUCR_SBF)) ? 1UL : 0UL);
-}
-
-#if defined (DUAL_CORE)
-/**
-  * @brief  Get CPU2 System Standby Flag
-  * @rmtoll CPU2CR   SBF       LL_PWR_CPU2_IsActiveFlag_SB
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_CPU2_IsActiveFlag_SB(void)
-{
-  return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_SBF) == (PWR_CPU2CR_SBF)) ? 1UL : 0UL);
-}
-#endif /* DUAL_CORE */
-
-#if defined (PWR_CPUCR_SBF_D1)
-/**
-  * @brief  Get CPU D1 Domain Standby Flag
-  * @rmtoll CPUCR   SBF_D1       LL_PWR_CPU_IsActiveFlag_SB_D1
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_CPU_IsActiveFlag_SB_D1(void)
-{
-  return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF_D1) == (PWR_CPUCR_SBF_D1)) ? 1UL : 0UL);
-}
-#endif /* PWR_CPUCR_SBF_D1 */
-
-#if defined (DUAL_CORE)
-/**
-  * @brief  Get CPU2 D1 Domain Standby Flag
-  * @rmtoll CPU2CR   SBF_D1       LL_PWR_CPU2_IsActiveFlag_SB_D1
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_CPU2_IsActiveFlag_SB_D1(void)
-{
-  return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_SBF_D1) == (PWR_CPU2CR_SBF_D1)) ? 1UL : 0UL);
-}
-#endif /* DUAL_CORE */
-
-#if defined (PWR_CPUCR_SBF_D2)
-/**
-  * @brief  Get CPU D2 Domain Standby Flag
-  * @rmtoll CPUCR   SBF_D2       LL_PWR_CPU_IsActiveFlag_SB_D2
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_CPU_IsActiveFlag_SB_D2(void)
-{
-  return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF_D2) == (PWR_CPUCR_SBF_D2)) ? 1UL : 0UL);
-}
-#endif /* PWR_CPUCR_SBF_D2 */
-
-#if defined (DUAL_CORE)
-/**
-  * @brief  Get CPU2 D2 Domain Standby Flag
-  * @rmtoll CPU2CR   SBF_D2       LL_PWR_CPU2_IsActiveFlag_SB_D2
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_CPU2_IsActiveFlag_SB_D2(void)
-{
-  return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_SBF_D2) == (PWR_CPU2CR_SBF_D2)) ? 1UL : 0UL);
-}
-#endif /* DUAL_CORE */
-
-
-/**
-  * @brief  Indicate whether the Regulator is ready in the selected voltage range
-  *         or if its output voltage is still changing to the required voltage level
-  * @rmtoll D3CR   VOSRDY       LL_PWR_IsActiveFlag_VOS
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void)
-{
-#if defined (PWR_CPUCR_PDDS_D2)
-  return ((READ_BIT(PWR->D3CR, PWR_D3CR_VOSRDY) == (PWR_D3CR_VOSRDY)) ? 1UL : 0UL);
-#else
-  return ((READ_BIT(PWR->SRDCR, PWR_SRDCR_VOSRDY) == (PWR_SRDCR_VOSRDY)) ? 1UL : 0UL);
-#endif /* PWR_CPUCR_PDDS_D2 */
-}
-
-/**
-  * @brief  Get Wake-up Flag 6
-  * @rmtoll WKUPFR          WKUPF6          LL_PWR_IsActiveFlag_WU6
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU6(void)
-{
-  return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF6) == (PWR_WKUPFR_WKUPF6)) ? 1UL : 0UL);
-}
-
-#if defined (PWR_WKUPFR_WKUPF5)
-/**
-  * @brief  Get Wake-up Flag 5
-  * @rmtoll WKUPFR          WKUPF5          LL_PWR_IsActiveFlag_WU5
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void)
-{
-  return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF5) == (PWR_WKUPFR_WKUPF5)) ? 1UL : 0UL);
-}
-#endif /* defined (PWR_WKUPFR_WKUPF5) */
-
-/**
-  * @brief  Get Wake-up Flag 4
-  * @rmtoll WKUPFR          WKUPF4          LL_PWR_IsActiveFlag_WU4
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void)
-{
-  return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF4) == (PWR_WKUPFR_WKUPF4)) ? 1UL : 0UL);
-}
-
-#if defined (PWR_WKUPFR_WKUPF3)
-/**
-  * @brief  Get Wake-up Flag 3
-  * @rmtoll WKUPFR          WKUPF3          LL_PWR_IsActiveFlag_WU3
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void)
-{
-  return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF3) == (PWR_WKUPFR_WKUPF3)) ? 1UL : 0UL);
-}
-#endif /* defined (PWR_WKUPFR_WKUPF3) */
-
-/**
-  * @brief  Get Wake-up Flag 2
-  * @rmtoll WKUPFR          WKUPF2          LL_PWR_IsActiveFlag_WU2
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void)
-{
-  return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF2) == (PWR_WKUPFR_WKUPF2)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Wake-up Flag 1
-  * @rmtoll WKUPFR          WKUPF1          LL_PWR_IsActiveFlag_WU1
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void)
-{
-  return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF1) == (PWR_WKUPFR_WKUPF1)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear CPU STANDBY, STOP and HOLD flags
-  * @rmtoll CPUCR   CSSF       LL_PWR_ClearFlag_CPU
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_ClearFlag_CPU(void)
-{
-  SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF);
-}
-
-#if defined (DUAL_CORE)
-/**
-  * @brief  Clear CPU2 STANDBY, STOP and HOLD flags
-  * @rmtoll CPU2CR   CSSF       LL_PWR_ClearFlag_CPU2
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_ClearFlag_CPU2(void)
-{
-  SET_BIT(PWR->CPU2CR, PWR_CPU2CR_CSSF);
-}
-#endif /* DUAL_CORE */
-
-/**
-  * @brief  Clear Wake-up Flag 6
-  * @rmtoll WKUPCR          WKUPC6         LL_PWR_ClearFlag_WU6
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_ClearFlag_WU6(void)
-{
-  WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC6);
-}
-
-#if defined (PWR_WKUPCR_WKUPC5)
-/**
-  * @brief  Clear Wake-up Flag 5
-  * @rmtoll WKUPCR          WKUPC5         LL_PWR_ClearFlag_WU5
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_ClearFlag_WU5(void)
-{
-  WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC5);
-}
-#endif /* defined (PWR_WKUPCR_WKUPC5) */
-
-/**
-  * @brief  Clear Wake-up Flag 4
-  * @rmtoll WKUPCR          WKUPC4         LL_PWR_ClearFlag_WU4
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_ClearFlag_WU4(void)
-{
-  WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC4);
-}
-
-#if defined (PWR_WKUPCR_WKUPC3)
-/**
-  * @brief  Clear Wake-up Flag 3
-  * @rmtoll WKUPCR          WKUPC3         LL_PWR_ClearFlag_WU3
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_ClearFlag_WU3(void)
-{
-  WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC3);
-}
-#endif /* defined (PWR_WKUPCR_WKUPC3) */
-
-/**
-  * @brief  Clear Wake-up Flag 2
-  * @rmtoll WKUPCR          WKUPC2         LL_PWR_ClearFlag_WU2
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_ClearFlag_WU2(void)
-{
-  WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC2);
-}
-
-/**
-  * @brief  Clear Wake-up Flag 1
-  * @rmtoll WKUPCR          WKUPC1         LL_PWR_ClearFlag_WU1
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_ClearFlag_WU1(void)
-{
-  WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC1);
-}
-
-#if defined (USE_FULL_LL_DRIVER)
-/** @defgroup PWR_LL_EF_Init De-initialization function
-  * @{
-  */
-ErrorStatus LL_PWR_DeInit(void);
-/**
-  * @}
-  */
-#endif /* defined (USE_FULL_LL_DRIVER) */
-
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* defined (PWR) */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32H7xx_LL_PWR_H */
-
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_ll_pwr.h
+  * @author  MCD Application Team
+  * @brief   Header file of PWR LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_LL_PWR_H
+#define STM32H7xx_LL_PWR_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx.h"
+
+/** @addtogroup STM32H7xx_LL_Driver
+  * @{
+  */
+
+#if defined (PWR)
+
+/** @defgroup PWR_LL PWR
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup PWR_LL_Private_Constants PWR Private Constants
+  * @{
+  */
+
+/** @defgroup PWR_LL_WAKEUP_PIN_OFFSET Wake-Up Pins register offsets Defines
+  * @brief    Flags defines which can be used with LL_PWR_WriteReg function
+  * @{
+  */
+/* Wake-Up Pins PWR register offsets */
+#define LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET    2UL
+#define LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK       0x1FU
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+/* Private macros ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
+  * @{
+  */
+
+/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
+  * @brief    Flags defines which can be used with LL_PWR_WriteReg function
+  * @{
+  */
+#define LL_PWR_FLAG_CPU_CSSF          PWR_CPUCR_CSSF      /*!< Clear flags for CPU  */
+#if defined (DUAL_CORE)
+#define LL_PWR_FLAG_CPU2_CSSF         PWR_CPU2CR_CSSF     /*!< Clear flags for CPU2 */
+#endif /* DUAL_CORE */
+#define LL_PWR_FLAG_WKUPCR_WKUPC6     PWR_WKUPCR_WKUPC6   /*!< Clear PC1 WKUP flag  */
+#if defined (PWR_WKUPCR_WKUPC5)
+#define LL_PWR_FLAG_WKUPCR_WKUPC5     PWR_WKUPCR_WKUPC5   /*!< Clear PI11 WKUP flag */
+#endif /* defined (PWR_WKUPCR_WKUPC5) */
+#define LL_PWR_FLAG_WKUPCR_WKUPC4     PWR_WKUPCR_WKUPC4   /*!< Clear PC13 WKUP flag */
+#if defined (PWR_WKUPCR_WKUPC3)
+#define LL_PWR_FLAG_WKUPCR_WKUPC3     PWR_WKUPCR_WKUPC3   /*!< Clear PI8 WKUP flag  */
+#endif /* defined (PWR_WKUPCR_WKUPC3) */
+#define LL_PWR_FLAG_WKUPCR_WKUPC2     PWR_WKUPCR_WKUPC2   /*!< Clear PA2 WKUP flag  */
+#define LL_PWR_FLAG_WKUPCR_WKUPC1     PWR_WKUPCR_WKUPC1   /*!< Clear PA0 WKUP flag  */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_PWR_ReadReg function
+  * @{
+  */
+#define LL_PWR_FLAG_AVDO              PWR_CSR1_AVDO       /*!< Analog voltage detector output on VDDA flag                          */
+#define LL_PWR_FLAG_PVDO              PWR_CSR1_PVDO       /*!< Programmable voltage detect output flag                              */
+#define LL_PWR_FLAG_ACTVOS            PWR_CSR1_ACTVOS     /*!< Current VOS applied for VCORE voltage scaling flag                   */
+#define LL_PWR_FLAG_ACTVOSRDY         PWR_CSR1_ACTVOSRDY  /*!< Ready bit for current actual used VOS for VCORE voltage scaling flag */
+#if defined (PWR_CSR1_MMCVDO)
+#define LL_PWR_FLAG_MMCVDO            PWR_CSR1_MMCVDO     /*!< Voltage detector output on VDDMMC flag                               */
+#endif /* PWR_CSR1_MMCVDO */
+
+#define LL_PWR_FLAG_TEMPH             PWR_CR2_TEMPH       /*!< Temperature high threshold flag */
+#define LL_PWR_FLAG_TEMPL             PWR_CR2_TEMPL       /*!< Temperature low threshold flag  */
+#define LL_PWR_FLAG_VBATH             PWR_CR2_VBATH       /*!< VBAT high threshold flag        */
+#define LL_PWR_FLAG_VBATL             PWR_CR2_VBATL       /*!< VBAT low threshold flag         */
+#define LL_PWR_FLAG_BRRDY             PWR_CR2_BRRDY       /*!< Backup Regulator ready flag     */
+
+#define LL_PWR_FLAG_USBRDY            PWR_CR3_USB33RDY    /*!< USB supply ready flag           */
+#define LL_PWR_FLAG_SMPSEXTRDY        PWR_CR3_SMPSEXTRDY  /*!< SMPS External supply ready flag */
+
+#if defined (PWR_CPUCR_SBF_D2)
+#define LL_PWR_FLAG_CPU_SBF_D2        PWR_CPUCR_SBF_D2    /*!< D2 domain DSTANDBY Flag  */
+#endif /* PWR_CPUCR_SBF_D2 */
+#if defined (PWR_CPUCR_SBF_D1)
+#define LL_PWR_FLAG_CPU_SBF_D1        PWR_CPUCR_SBF_D1    /*!< D1 domain DSTANDBY Flag  */
+#endif /* PWR_CPUCR_SBF_D1 */
+#define LL_PWR_FLAG_CPU_SBF           PWR_CPUCR_SBF       /*!< System STANDBY Flag      */
+#define LL_PWR_FLAG_CPU_STOPF         PWR_CPUCR_STOPF     /*!< STOP Flag                */
+#if defined (DUAL_CORE)
+#define LL_PWR_FLAG_CPU_HOLD2F        PWR_CPUCR_HOLD2F    /*!< CPU2 in hold wakeup flag */
+#endif /* DUAL_CORE */
+
+#if defined (DUAL_CORE)
+#define LL_PWR_FLAG_CPU2_SBF_D2       PWR_CPU2CR_SBF_D2   /*!< D2 domain DSTANDBY Flag  */
+#define LL_PWR_FLAG_CPU2_SBF_D1       PWR_CPU2CR_SBF_D1   /*!< D1 domain DSTANDBY Flag  */
+#define LL_PWR_FLAG_CPU2_SBF          PWR_CPU2CR_SBF      /*!< System STANDBY Flag      */
+#define LL_PWR_FLAG_CPU2_STOPF        PWR_CPU2CR_STOPF    /*!< STOP Flag                */
+#define LL_PWR_FLAG_CPU2_HOLD1F       PWR_CPU2CR_HOLD1F   /*!< CPU1 in hold wakeup flag */
+#endif /* DUAL_CORE */
+
+#if defined (PWR_CPUCR_PDDS_D2)
+#define LL_PWR_D3CR_VOSRDY            PWR_D3CR_VOSRDY     /*!< Voltage scaling ready flag */
+#else
+#define LL_PWR_SRDCR_VOSRDY           PWR_SRDCR_VOSRDY    /*!< Voltage scaling ready flag */
+#endif /* PWR_CPUCR_PDDS_D2 */
+
+#define LL_PWR_WKUPFR_WKUPF6          PWR_WKUPFR_WKUPF6   /*!< Wakeup flag on PC1  */
+#if defined (PWR_WKUPFR_WKUPF5)
+#define LL_PWR_WKUPFR_WKUPF5          PWR_WKUPFR_WKUPF5   /*!< Wakeup flag on PI11 */
+#endif /* defined (PWR_WKUPFR_WKUPF5) */
+#define LL_PWR_WKUPFR_WKUPF4          PWR_WKUPFR_WKUPF4   /*!< Wakeup flag on PC13 */
+#if defined (PWR_WKUPFR_WKUPF3)
+#define LL_PWR_WKUPFR_WKUPF3          PWR_WKUPFR_WKUPF3   /*!< Wakeup flag on PI8  */
+#endif /* defined (PWR_WKUPFR_WKUPF3) */
+#define LL_PWR_WKUPFR_WKUPF2          PWR_WKUPFR_WKUPF2   /*!< Wakeup flag on PA2  */
+#define LL_PWR_WKUPFR_WKUPF1          PWR_WKUPFR_WKUPF1   /*!< Wakeup flag on PA0  */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_MODE_PWR Power mode
+  * @{
+  */
+#if defined (PWR_CPUCR_PDDS_D2)
+#define LL_PWR_CPU_MODE_D1STOP        0x00000000U           /*!< Enter D1 domain to Stop mode when the CPU enters deepsleep       */
+#define LL_PWR_CPU_MODE_D1STANDBY     PWR_CPUCR_PDDS_D1     /*!< Enter D1 domain to Standby mode when the CPU enters deepsleep    */
+#else
+#define LL_PWR_CPU_MODE_CDSTOP        0x00000000U           /*!< Enter CD domain to Stop mode when the CPU enters deepsleep       */
+#define LL_PWR_CPU_MODE_CDSTOP2       PWR_CPUCR_RETDS_CD    /*!< Enter CD domain to Stop2 mode when the CPU enters deepsleep      */
+#endif /* PWR_CPUCR_PDDS_D2 */
+
+#if defined (PWR_CPUCR_PDDS_D2)
+#define LL_PWR_CPU_MODE_D2STOP        0x00000000U           /*!< Enter D2 domain to Stop mode when the CPU enters deepsleep       */
+#define LL_PWR_CPU_MODE_D2STANDBY     PWR_CPUCR_PDDS_D2     /*!< Enter D2 domain to Standby mode when the CPU enters deepsleep    */
+#endif /* PWR_CPUCR_PDDS_D2 */
+
+#if defined (PWR_CPUCR_PDDS_D2)
+#define LL_PWR_CPU_MODE_D3RUN         PWR_CPUCR_RUN_D3      /*!< Keep system D3 domain in Run mode when the CPU enter deepsleep   */
+#define LL_PWR_CPU_MODE_D3STOP        0x00000000U           /*!< Enter D3 domain to Stop mode when the CPU enters deepsleep       */
+#define LL_PWR_CPU_MODE_D3STANDBY     PWR_CPUCR_PDDS_D3     /*!< Enter D3 domain to Standby mode when the CPU enters deepsleep    */
+#else
+#define LL_PWR_CPU_MODE_SRDRUN        PWR_CPUCR_RUN_SRD     /*!< Keep system SRD domain in Run mode when the CPU enter deepsleep  */
+#define LL_PWR_CPU_MODE_SRDSTOP       0x00000000U           /*!< Enter SRD domain to Stop mode when the CPU enters deepsleep      */
+#define LL_PWR_CPU_MODE_SRDSTANDBY    PWR_CPUCR_PDDS_SRD    /*!< Enter SRD domain to Standby mode when the CPU enters deepsleep   */
+#endif /* PWR_CPUCR_PDDS_D2 */
+
+#if defined (DUAL_CORE)
+#define LL_PWR_CPU2_MODE_D1STOP       0x00000000U           /*!< Enter D1 domain to Stop mode when the CPU2 enters deepsleep      */
+#define LL_PWR_CPU2_MODE_D1STANDBY    PWR_CPU2CR_PDDS_D1    /*!< Enter D1 domain to Standby mode when the CPU2 enters deepsleep   */
+#define LL_PWR_CPU2_MODE_D2STOP       0x00000000U           /*!< Enter D2 domain to Stop mode when the CPU2 enters deepsleep      */
+#define LL_PWR_CPU2_MODE_D2STANDBY    PWR_CPU2CR_PDDS_D2    /*!< Enter D2 domain to Standby mode when the CPU2 enters deepsleep   */
+#define LL_PWR_CPU2_MODE_D3RUN        PWR_CPU2CR_RUN_D3     /*!< Keep system D3 domain in RUN mode when the CPU2 enter deepsleep  */
+#define LL_PWR_CPU2_MODE_D3STOP       0x00000000U           /*!< Enter D3 domain to Stop mode when the CPU2 enters deepsleep      */
+#define LL_PWR_CPU2_MODE_D3STANDBY    PWR_CPU2CR_PDDS_D3    /*!< Enter D3 domain to Standby mode when the CPU2 enter deepsleep    */
+#endif /* DUAL_CORE */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_REGU_VOLTAGE Run mode Regulator Voltage Scaling
+  * @{
+  */
+#if defined (PWR_CPUCR_PDDS_D2)
+#define LL_PWR_REGU_VOLTAGE_SCALE3      PWR_D3CR_VOS_0                    /*!< Select voltage scale 3 */
+#define LL_PWR_REGU_VOLTAGE_SCALE2      PWR_D3CR_VOS_1                    /*!< Select voltage scale 2 */
+#define LL_PWR_REGU_VOLTAGE_SCALE1      (PWR_D3CR_VOS_0 | PWR_D3CR_VOS_1) /*!< Select voltage scale 1 */
+#if defined (SYSCFG_PWRCR_ODEN) /* STM32H74xxx and STM32H75xxx lines */
+#define LL_PWR_REGU_VOLTAGE_SCALE0      (PWR_D3CR_VOS_0 | PWR_D3CR_VOS_1) /*!< Select voltage scale 0 */
+#else
+#define LL_PWR_REGU_VOLTAGE_SCALE0      0x00000000U                       /*!< Select voltage scale 0 */
+#endif /* defined (SYSCFG_PWRCR_ODEN) */
+#else
+#define LL_PWR_REGU_VOLTAGE_SCALE3      0x00000000U                       /*!< Select voltage scale 3 */
+#define LL_PWR_REGU_VOLTAGE_SCALE2      PWR_D3CR_VOS_0                    /*!< Select voltage scale 2 */
+#define LL_PWR_REGU_VOLTAGE_SCALE1      PWR_D3CR_VOS_1                    /*!< Select voltage scale 1 */
+#define LL_PWR_REGU_VOLTAGE_SCALE0      (PWR_D3CR_VOS_0 | PWR_D3CR_VOS_1) /*!< Select voltage scale 0 */
+#endif /* PWR_CPUCR_PDDS_D2 */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_STOP_MODE_REGU_VOLTAGE Stop mode Regulator Voltage Scaling
+  * @{
+  */
+#define LL_PWR_REGU_VOLTAGE_SVOS_SCALE5   PWR_CR1_SVOS_0                    /*!< Select voltage scale 5 when system enters STOP mode */
+#define LL_PWR_REGU_VOLTAGE_SVOS_SCALE4   PWR_CR1_SVOS_1                    /*!< Select voltage scale 4 when system enters STOP mode */
+#define LL_PWR_REGU_VOLTAGE_SVOS_SCALE3   (PWR_CR1_SVOS_0 | PWR_CR1_SVOS_1) /*!< Select voltage scale 3 when system enters STOP mode */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE  Regulator Mode In Deep Sleep Mode
+  * @{
+  */
+#define LL_PWR_REGU_DSMODE_MAIN           0x00000000U   /*!< Voltage Regulator in main mode during deepsleep mode      */
+#define LL_PWR_REGU_DSMODE_LOW_POWER      PWR_CR1_LPDS  /*!< Voltage Regulator in low-power mode during deepsleep mode */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_PVDLEVEL Power Digital Voltage Level Detector
+  * @{
+  */
+#define LL_PWR_PVDLEVEL_0   PWR_CR1_PLS_LEV0  /*!< Voltage threshold detected by PVD 1.95 V */
+#define LL_PWR_PVDLEVEL_1   PWR_CR1_PLS_LEV1  /*!< Voltage threshold detected by PVD 2.1 V  */
+#define LL_PWR_PVDLEVEL_2   PWR_CR1_PLS_LEV2  /*!< Voltage threshold detected by PVD 2.25 V */
+#define LL_PWR_PVDLEVEL_3   PWR_CR1_PLS_LEV3  /*!< Voltage threshold detected by PVD 2.4 V  */
+#define LL_PWR_PVDLEVEL_4   PWR_CR1_PLS_LEV4  /*!< Voltage threshold detected by PVD 2.55 V */
+#define LL_PWR_PVDLEVEL_5   PWR_CR1_PLS_LEV5  /*!< Voltage threshold detected by PVD 2.7 V  */
+#define LL_PWR_PVDLEVEL_6   PWR_CR1_PLS_LEV6  /*!< Voltage threshold detected by PVD 2.85 V */
+#define LL_PWR_PVDLEVEL_7   PWR_CR1_PLS_LEV7  /*!< External voltage level on PVD_IN pin, compared to internal VREFINT level. */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_AVDLEVEL Power Analog Voltage Level Detector
+  * @{
+  */
+#define LL_PWR_AVDLEVEL_0   PWR_CR1_ALS_LEV0  /*!< Analog Voltage threshold detected by AVD 1.7 V */
+#define LL_PWR_AVDLEVEL_1   PWR_CR1_ALS_LEV1  /*!< Analog Voltage threshold detected by AVD 2.1 V */
+#define LL_PWR_AVDLEVEL_2   PWR_CR1_ALS_LEV2  /*!< Analog Voltage threshold detected by AVD 2.5 V */
+#define LL_PWR_AVDLEVEL_3   PWR_CR1_ALS_LEV3  /*!< Analog Voltage threshold detected by AVD 2.8 V */
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_BATT_CHARG_RESISTOR Battery Charge Resistor
+  * @{
+  */
+#define LL_PWR_BATT_CHARG_RESISTOR_5K     0x00000000U   /*!< Charge the Battery through a 5 kO resistor    */
+#define LL_PWR_BATT_CHARGRESISTOR_1_5K    PWR_CR3_VBRS  /*!< Charge the Battery through a 1.5 kO resistor  */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_WAKEUP_PIN  Wakeup Pins
+  * @{
+  */
+#define LL_PWR_WAKEUP_PIN1    PWR_WKUPEPR_WKUPEN1  /*!< Wake-Up pin 1 : PA0  */
+#define LL_PWR_WAKEUP_PIN2    PWR_WKUPEPR_WKUPEN2  /*!< Wake-Up pin 2 : PA2  */
+#if defined (PWR_WKUPEPR_WKUPEN3)
+#define LL_PWR_WAKEUP_PIN3    PWR_WKUPEPR_WKUPEN3  /*!< Wake-Up pin 3 : PI8  */
+#endif /* defined (PWR_WKUPEPR_WKUPEN3) */
+#define LL_PWR_WAKEUP_PIN4    PWR_WKUPEPR_WKUPEN4  /*!< Wake-Up pin 4 : PC13 */
+#if defined (PWR_WKUPEPR_WKUPEN5)
+#define LL_PWR_WAKEUP_PIN5    PWR_WKUPEPR_WKUPEN5  /*!< Wake-Up pin 5 : PI11 */
+#endif /* defined (PWR_WKUPEPR_WKUPEN5) */
+#define LL_PWR_WAKEUP_PIN6    PWR_WKUPEPR_WKUPEN6  /*!< Wake-Up pin 6 : PC1  */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_WAKEUP_PIN_PULL  Wakeup Pins pull configuration
+  * @{
+  */
+#define LL_PWR_WAKEUP_PIN_NOPULL      0x00000000UL   /*!< Configure Wake-Up pin in no pull   */
+#define LL_PWR_WAKEUP_PIN_PULLUP      0x00000001UL   /*!< Configure Wake-Up pin in pull Up   */
+#define LL_PWR_WAKEUP_PIN_PULLDOWN    0x00000002UL   /*!< Configure Wake-Up pin in pull Down */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_SUPPLY_PWR Power supply source configuration
+  * @{
+  */
+#define LL_PWR_LDO_SUPPLY                     PWR_CR3_LDOEN                                                               /*!< Core domains are supplied from the LDO                                                                     */
+#if defined (SMPS)
+#define LL_PWR_DIRECT_SMPS_SUPPLY             PWR_CR3_SMPSEN                                                              /*!< Core domains are supplied from the SMPS                                                                    */
+#define LL_PWR_SMPS_1V8_SUPPLIES_LDO          (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)                      /*!< The SMPS 1.8V output supplies the LDO which supplies the Core domains                                       */
+#define LL_PWR_SMPS_2V5_SUPPLIES_LDO          (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)                      /*!< The SMPS 2.5V output supplies the LDO which supplies the Core domains                                       */
+#define LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO  (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)  /*!< The SMPS 1.8V output supplies an external circuits and the LDO. The Core domains are supplied from the LDO */
+#define LL_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO  (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)  /*!< The SMPS 2.5V output supplies an external circuits and the LDO. The Core domains are supplied from the LDO */
+#define LL_PWR_SMPS_1V8_SUPPLIES_EXT          (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 1.8V output supplies an external source which supplies the Core domains                            */
+#define LL_PWR_SMPS_2V5_SUPPLIES_EXT          (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 2.5V output supplies an external source which supplies the Core domains                            */
+#endif /* SMPS */
+#define LL_PWR_EXTERNAL_SOURCE_SUPPLY         PWR_CR3_BYPASS                                                              /*!< The SMPS and the LDO are Bypassed. The Core domains are supplied from an external source                    */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
+  * @{
+  */
+
+/** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in PWR register
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in PWR register
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
+  * @{
+  */
+
+/** @defgroup PWR_LL_EF_Configuration Configuration
+  * @{
+  */
+
+  /**
+  * @brief  Set the voltage Regulator mode during deep sleep mode
+  * @rmtoll CR1    LPDS         LL_PWR_SetRegulModeDS
+  * @param  RegulMode This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_REGU_DSMODE_MAIN
+  *         @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode)
+{
+  MODIFY_REG(PWR->CR1, PWR_CR1_LPDS, RegulMode);
+}
+
+/**
+  * @brief  Get the voltage Regulator mode during deep sleep mode
+  * @rmtoll CR1    LPDS         LL_PWR_GetRegulModeDS
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_REGU_DSMODE_MAIN
+  *         @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
+  */
+__STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void)
+{
+  return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_LPDS));
+}
+
+/**
+  * @brief  Enable Power Voltage Detector
+  * @rmtoll CR1    PVDEN       LL_PWR_EnablePVD
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnablePVD(void)
+{
+  SET_BIT(PWR->CR1, PWR_CR1_PVDEN);
+}
+
+/**
+  * @brief  Disable Power Voltage Detector
+  * @rmtoll CR1    PVDEN       LL_PWR_DisablePVD
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisablePVD(void)
+{
+  CLEAR_BIT(PWR->CR1, PWR_CR1_PVDEN);
+}
+
+/**
+  * @brief  Check if Power Voltage Detector is enabled
+  * @rmtoll CR1    PVDEN       LL_PWR_IsEnabledPVD
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
+{
+  return ((READ_BIT(PWR->CR1, PWR_CR1_PVDEN) == (PWR_CR1_PVDEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Configure the voltage threshold detected by the Power Voltage Detector
+  * @rmtoll CR1    PLS       LL_PWR_SetPVDLevel
+  * @param  PVDLevel This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_PVDLEVEL_0
+  *         @arg @ref LL_PWR_PVDLEVEL_1
+  *         @arg @ref LL_PWR_PVDLEVEL_2
+  *         @arg @ref LL_PWR_PVDLEVEL_3
+  *         @arg @ref LL_PWR_PVDLEVEL_4
+  *         @arg @ref LL_PWR_PVDLEVEL_5
+  *         @arg @ref LL_PWR_PVDLEVEL_6
+  *         @arg @ref LL_PWR_PVDLEVEL_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
+{
+  MODIFY_REG(PWR->CR1, PWR_CR1_PLS, PVDLevel);
+}
+
+/**
+  * @brief  Get the voltage threshold detection
+  * @rmtoll CR1    PLS       LL_PWR_GetPVDLevel
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_PVDLEVEL_0
+  *         @arg @ref LL_PWR_PVDLEVEL_1
+  *         @arg @ref LL_PWR_PVDLEVEL_2
+  *         @arg @ref LL_PWR_PVDLEVEL_3
+  *         @arg @ref LL_PWR_PVDLEVEL_4
+  *         @arg @ref LL_PWR_PVDLEVEL_5
+  *         @arg @ref LL_PWR_PVDLEVEL_6
+  *         @arg @ref LL_PWR_PVDLEVEL_7
+  */
+__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
+{
+  return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_PLS));
+}
+
+/**
+  * @brief  Enable access to the backup domain
+  * @rmtoll CR1    DBP       LL_PWR_EnableBkUpAccess
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
+{
+  SET_BIT(PWR->CR1, PWR_CR1_DBP);
+}
+
+/**
+  * @brief  Disable access to the backup domain
+  * @rmtoll CR1    DBP       LL_PWR_DisableBkUpAccess
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
+{
+  CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
+}
+
+/**
+  * @brief  Check if the backup domain is enabled
+  * @rmtoll CR1    DBP       LL_PWR_IsEnabledBkUpAccess
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
+{
+  return ((READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the Flash Power Down in Stop Mode
+  * @rmtoll CR1    FLPS       LL_PWR_EnableFlashPowerDown
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableFlashPowerDown(void)
+{
+  SET_BIT(PWR->CR1, PWR_CR1_FLPS);
+}
+
+/**
+  * @brief  Disable the Flash Power Down in Stop Mode
+  * @rmtoll CR1    FLPS       LL_PWR_DisableFlashPowerDown
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableFlashPowerDown(void)
+{
+  CLEAR_BIT(PWR->CR1, PWR_CR1_FLPS);
+}
+
+/**
+  * @brief  Check if the Flash Power Down in Stop Mode is enabled
+  * @rmtoll CR1    FLPS       LL_PWR_IsEnabledFlashPowerDown
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledFlashPowerDown(void)
+{
+  return ((READ_BIT(PWR->CR1, PWR_CR1_FLPS) == (PWR_CR1_FLPS)) ? 1UL : 0UL);
+}
+
+#if defined (PWR_CR1_BOOSTE)
+/**
+  * @brief  Enable the Analog Voltage Booster (VDDA)
+  * @rmtoll CR1    BOOSTE     LL_PWR_EnableAnalogBooster
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableAnalogBooster(void)
+{
+  SET_BIT(PWR->CR1, PWR_CR1_BOOSTE);
+}
+
+/**
+  * @brief  Disable the Analog Voltage Booster (VDDA)
+  * @rmtoll CR1    BOOSTE     LL_PWR_DisableAnalogBooster
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableAnalogBooster(void)
+{
+  CLEAR_BIT(PWR->CR1, PWR_CR1_BOOSTE);
+}
+
+/**
+  * @brief  Check if the Analog Voltage Booster (VDDA) is enabled
+  * @rmtoll CR1    BOOSTE     LL_PWR_IsEnabledAnalogBooster
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledAnalogBooster(void)
+{
+  return ((READ_BIT(PWR->CR1, PWR_CR1_BOOSTE) == (PWR_CR1_BOOSTE)) ? 1UL : 0UL);
+}
+#endif /* PWR_CR1_BOOSTE */
+
+#if defined (PWR_CR1_AVD_READY)
+/**
+  * @brief  Enable the Analog Voltage Ready to isolate the BOOST IP until VDDA will be ready
+  * @rmtoll CR1    AVD_READY  LL_PWR_EnableAnalogVoltageReady
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableAnalogVoltageReady(void)
+{
+  SET_BIT(PWR->CR1, PWR_CR1_AVD_READY);
+}
+
+/**
+  * @brief  Disable the Analog Voltage Ready (VDDA)
+  * @rmtoll CR1    AVD_READY  LL_PWR_DisableAnalogVoltageReady
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableAnalogVoltageReady(void)
+{
+  CLEAR_BIT(PWR->CR1, PWR_CR1_AVD_READY);
+}
+
+/**
+  * @brief  Check if the Analog Voltage Booster (VDDA) is enabled
+  * @rmtoll CR1    AVD_READY  LL_PWR_IsEnabledAnalogVoltageReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledAnalogVoltageReady(void)
+{
+  return ((READ_BIT(PWR->CR1, PWR_CR1_AVD_READY) == (PWR_CR1_AVD_READY)) ? 1UL : 0UL);
+}
+#endif /* PWR_CR1_AVD_READY */
+
+/**
+  * @brief  Set the internal Regulator output voltage in STOP mode
+  * @rmtoll CR1    SVOS       LL_PWR_SetStopModeRegulVoltageScaling
+  * @param  VoltageScaling This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE3
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE4
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE5
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetStopModeRegulVoltageScaling(uint32_t VoltageScaling)
+{
+  MODIFY_REG(PWR->CR1, PWR_CR1_SVOS, VoltageScaling);
+}
+
+/**
+  * @brief  Get the internal Regulator output voltage in STOP mode
+  * @rmtoll CR1    SVOS       LL_PWR_GetStopModeRegulVoltageScaling
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE3
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE4
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE5
+  */
+__STATIC_INLINE uint32_t LL_PWR_GetStopModeRegulVoltageScaling(void)
+{
+  return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_SVOS));
+}
+
+/**
+  * @brief  Enable Analog Power Voltage Detector
+  * @rmtoll CR1    AVDEN       LL_PWR_EnableAVD
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableAVD(void)
+{
+  SET_BIT(PWR->CR1, PWR_CR1_AVDEN);
+}
+
+/**
+  * @brief  Disable Analog Power Voltage Detector
+  * @rmtoll CR1    AVDEN       LL_PWR_DisableAVD
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableAVD(void)
+{
+  CLEAR_BIT(PWR->CR1, PWR_CR1_AVDEN);
+}
+
+/**
+  * @brief  Check if Analog Power Voltage Detector is enabled
+  * @rmtoll CR1    AVDEN       LL_PWR_IsEnabledAVD
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledAVD(void)
+{
+  return ((READ_BIT(PWR->CR1, PWR_CR1_AVDEN) == (PWR_CR1_AVDEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Configure the voltage threshold to be detected by the Analog Power Voltage Detector
+  * @rmtoll CR1    ALS       LL_PWR_SetAVDLevel
+  * @param  AVDLevel This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_AVDLEVEL_0
+  *         @arg @ref LL_PWR_AVDLEVEL_1
+  *         @arg @ref LL_PWR_AVDLEVEL_2
+  *         @arg @ref LL_PWR_AVDLEVEL_3
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetAVDLevel(uint32_t AVDLevel)
+{
+  MODIFY_REG(PWR->CR1, PWR_CR1_ALS, AVDLevel);
+}
+
+/**
+  * @brief  Get the Analog Voltage threshold to be detected by the Analog Power Voltage Detector
+  * @rmtoll CR1    ALS       LL_PWR_GetAVDLevel
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_AVDLEVEL_0
+  *         @arg @ref LL_PWR_AVDLEVEL_1
+  *         @arg @ref LL_PWR_AVDLEVEL_2
+  *         @arg @ref LL_PWR_AVDLEVEL_3
+  */
+__STATIC_INLINE uint32_t LL_PWR_GetAVDLevel(void)
+{
+  return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_ALS));
+}
+
+#if defined (PWR_CR1_AXIRAM1SO)
+/**
+  * @brief  Enable the AXI RAM1 shut-off in DStop/DStop2 mode
+  * @rmtoll CR1    AXIRAM1SO     LL_PWR_EnableAXIRAM1ShutOff
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableAXIRAM1ShutOff(void)
+{
+  SET_BIT(PWR->CR1, PWR_CR1_AXIRAM1SO);
+}
+
+/**
+  * @brief  Disable the AXI RAM1 shut-off in DStop/DStop2 mode
+  * @rmtoll CR1    AXIRAM1SO     LL_PWR_DisableAXIRAM1ShutOff
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableAXIRAM1ShutOff(void)
+{
+  CLEAR_BIT(PWR->CR1, PWR_CR1_AXIRAM1SO);
+}
+
+/**
+  * @brief  Check if the AXI RAM1 shut-off in DStop/DStop2 mode is enabled
+  * @rmtoll CR1    AXIRAM1SO     LL_PWR_IsEnabledAXIRAM1ShutOff
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledAXIRAM1ShutOff(void)
+{
+  return ((READ_BIT(PWR->CR1, PWR_CR1_AXIRAM1SO) == (PWR_CR1_AXIRAM1SO)) ? 1UL : 0UL);
+}
+#endif /* PWR_CR1_AXIRAM1SO */
+
+#if defined (PWR_CR1_AXIRAM2SO)
+/**
+  * @brief  Enable the AXI RAM2 shut-off in DStop/DStop2 mode
+  * @rmtoll CR1    AXIRAM2SO     LL_PWR_EnableAXIRAM2ShutOff
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableAXIRAM2ShutOff(void)
+{
+  SET_BIT(PWR->CR1, PWR_CR1_AXIRAM2SO);
+}
+
+/**
+  * @brief  Disable the AXI RAM2 shut-off in DStop/DStop2 mode
+  * @rmtoll CR1    AXIRAM2SO     LL_PWR_DisableAXIRAM2ShutOff
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableAXIRAM2ShutOff(void)
+{
+  CLEAR_BIT(PWR->CR1, PWR_CR1_AXIRAM2SO);
+}
+
+/**
+  * @brief  Check if the AXI RAM2 shut-off in DStop/DStop2 mode is enabled
+  * @rmtoll CR1    AXIRAM2SO     LL_PWR_IsEnabledAXIRAM2ShutOff
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledAXIRAM2ShutOff(void)
+{
+  return ((READ_BIT(PWR->CR1, PWR_CR1_AXIRAM2SO) == (PWR_CR1_AXIRAM2SO)) ? 1UL : 0UL);
+}
+#endif /* PWR_CR1_AXIRAM2SO */
+
+#if defined (PWR_CR1_AXIRAM3SO)
+/**
+  * @brief  Enable the AXI RAM3 shut-off in DStop/DStop2 mode
+  * @rmtoll CR1    AXIRAM3SO     LL_PWR_EnableAXIRAM3ShutOff
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableAXIRAM3ShutOff(void)
+{
+  SET_BIT(PWR->CR1, PWR_CR1_AXIRAM3SO);
+}
+
+/**
+  * @brief  Disable the AXI RAM3 shut-off in DStop/DStop2 mode
+  * @rmtoll CR1    AXIRAM3SO     LL_PWR_DisableAXIRAM3ShutOff
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableAXIRAM3ShutOff(void)
+{
+  CLEAR_BIT(PWR->CR1, PWR_CR1_AXIRAM3SO);
+}
+
+/**
+  * @brief  Check if the AXI RAM3 shut-off in DStop/DStop2 mode is enabled
+  * @rmtoll CR1    AXIRAM3SO     LL_PWR_IsEnabledAXIRAM3ShutOff
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledAXIRAM3ShutOff(void)
+{
+  return ((READ_BIT(PWR->CR1, PWR_CR1_AXIRAM3SO) == (PWR_CR1_AXIRAM3SO)) ? 1UL : 0UL);
+}
+#endif /* PWR_CR1_AXIRAM3SO */
+
+#if defined (PWR_CR1_AHBRAM1SO)
+/**
+  * @brief  Enable the AHB RAM1 shut-off in DStop/DStop2 mode
+  * @rmtoll CR1    AHBRAM1SO     LL_PWR_EnableAHBRAM1ShutOff
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableAHBRAM1ShutOff(void)
+{
+  SET_BIT(PWR->CR1, PWR_CR1_AHBRAM1SO);
+}
+
+/**
+  * @brief  Disable the AHB RAM1 shut-off in DStop/DStop2 mode
+  * @rmtoll CR1    AHBRAM1SO     LL_PWR_DisableAHBRAM1ShutOff
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableAHBRAM1ShutOff(void)
+{
+  CLEAR_BIT(PWR->CR1, PWR_CR1_AHBRAM1SO);
+}
+
+/**
+  * @brief  Check if the AHB RAM1 shut-off in DStop/DStop2 mode is enabled
+  * @rmtoll CR1    AHBRAM1SO     LL_PWR_IsEnabledAHBRAM1ShutOff
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledAHBRAM1ShutOff(void)
+{
+  return ((READ_BIT(PWR->CR1, PWR_CR1_AHBRAM1SO) == (PWR_CR1_AHBRAM1SO)) ? 1UL : 0UL);
+}
+#endif /* PWR_CR1_AHBRAM1SO */
+
+#if defined (PWR_CR1_AHBRAM2SO)
+/**
+  * @brief  Enable the AHB RAM2 shut-off in DStop/DStop2 mode
+  * @rmtoll CR1    AHBRAM2SO     LL_PWR_EnableAHBRAM2ShutOff
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableAHBRAM2ShutOff(void)
+{
+  SET_BIT(PWR->CR1, PWR_CR1_AHBRAM2SO);
+}
+
+/**
+  * @brief  Disable the AHB RAM2 shut-off in DStop/DStop2 mode
+  * @rmtoll CR1    AHBRAM2SO     LL_PWR_DisableAHBRAM2ShutOff
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableAHBRAM2ShutOff(void)
+{
+  CLEAR_BIT(PWR->CR1, PWR_CR1_AHBRAM2SO);
+}
+
+/**
+  * @brief  Check if the AHB RAM2 shut-off in DStop/DStop2 mode is enabled
+  * @rmtoll CR1    AHBRAM2SO     LL_PWR_IsEnabledAHBRAM2ShutOff
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledAHBRAM2ShutOff(void)
+{
+  return ((READ_BIT(PWR->CR1, PWR_CR1_AHBRAM2SO) == (PWR_CR1_AHBRAM2SO)) ? 1UL : 0UL);
+}
+#endif /* PWR_CR1_AHBRAM2SO */
+
+#if defined (PWR_CR1_ITCMSO)
+/**
+  * @brief  Enable the ITCM shut-off in DStop/DStop2 mode
+  * @rmtoll CR1    ITCMSO     LL_PWR_EnableITCMSOShutOff
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableITCMSOShutOff(void)
+{
+  SET_BIT(PWR->CR1, PWR_CR1_ITCMSO);
+}
+
+/**
+  * @brief  Disable the ITCM shut-off in DStop/DStop2 mode
+  * @rmtoll CR1    ITCMSO     LL_PWR_DisableITCMSOShutOff
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableITCMSOShutOff(void)
+{
+  CLEAR_BIT(PWR->CR1, PWR_CR1_ITCMSO);
+}
+
+/**
+  * @brief  Check if the ITCM shut-off in DStop/DStop2 mode is enabled
+  * @rmtoll CR1    ITCMSO     LL_PWR_IsEnabledITCMShutOff
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledITCMShutOff(void)
+{
+  return ((READ_BIT(PWR->CR1, PWR_CR1_ITCMSO) == (PWR_CR1_ITCMSO)) ? 1UL : 0UL);
+}
+#endif /* PWR_CR1_ITCMSO */
+
+#if defined (PWR_CR1_HSITFSO)
+/**
+  * @brief  Enable the USB and FDCAN shut-off in DStop/DStop2 mode
+  * @rmtoll CR1    HSITFSO     LL_PWR_EnableHSITFShutOff
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableHSITFShutOff(void)
+{
+  SET_BIT(PWR->CR1, PWR_CR1_HSITFSO);
+}
+
+/**
+  * @brief  Disable the USB and FDCAN shut-off in DStop/DStop2 mode
+  * @rmtoll CR1    HSITFSO     LL_PWR_DisableHSITFShutOff
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableHSITFShutOff(void)
+{
+  CLEAR_BIT(PWR->CR1, PWR_CR1_HSITFSO);
+}
+
+/**
+  * @brief  Check if the USB and FDCAN shut-off in DStop/DStop2 mode is enabled
+  * @rmtoll CR1    HSITFSO     LL_PWR_IsEnabledHSITFShutOff
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledHSITFShutOff(void)
+{
+  return ((READ_BIT(PWR->CR1, PWR_CR1_HSITFSO) == (PWR_CR1_HSITFSO)) ? 1UL : 0UL);
+}
+#endif /* PWR_CR1_HSITFSO */
+
+#if defined (PWR_CR1_SRDRAMSO)
+/**
+  * @brief  Enable the SRD AHB RAM shut-off in DStop/DStop2 mode
+  * @rmtoll CR1    SRDRAMSO     LL_PWR_EnableSRDRAMShutOff
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableSRDRAMShutOff(void)
+{
+  SET_BIT(PWR->CR1, PWR_CR1_SRDRAMSO);
+}
+
+/**
+  * @brief  Disable the SRD AHB RAM shut-off in DStop/DStop2 mode
+  * @rmtoll CR1    SRDRAMSO     LL_PWR_DisableSRDRAMShutOff
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableSRDRAMShutOff(void)
+{
+  CLEAR_BIT(PWR->CR1, PWR_CR1_SRDRAMSO);
+}
+
+/**
+  * @brief  Check if the SRD AHB RAM shut-off in DStop/DStop2 mode is enabled
+  * @rmtoll CR1    SRDRAMSO     LL_PWR_IsEnabledSRDRAMShutOff
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledSRDRAMShutOff(void)
+{
+  return ((READ_BIT(PWR->CR1, PWR_CR1_SRDRAMSO) == (PWR_CR1_SRDRAMSO)) ? 1UL : 0UL);
+}
+#endif /* PWR_CR1_SRDRAMSO */
+
+/**
+  * @brief  Enable Backup Regulator
+  * @rmtoll CR2    BREN       LL_PWR_EnableBkUpRegulator
+  * @note When set, the Backup Regulator (used to maintain backup SRAM content in Standby and
+  *       VBAT modes) is enabled. If BRE is reset, the backup Regulator is switched off. The backup
+  *       SRAM can still be used but its content will be lost in the Standby and VBAT modes. Once set,
+  *       the application must wait that the Backup Regulator Ready flag (BRR) is set to indicate that
+  *       the data written into the RAM will be maintained in the Standby and VBAT modes.
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableBkUpRegulator(void)
+{
+  SET_BIT(PWR->CR2, PWR_CR2_BREN);
+}
+
+/**
+  * @brief  Disable Backup Regulator
+  * @rmtoll CR2    BREN       LL_PWR_DisableBkUpRegulator
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableBkUpRegulator(void)
+{
+  CLEAR_BIT(PWR->CR2, PWR_CR2_BREN);
+}
+
+/**
+  * @brief  Check if the backup Regulator is enabled
+  * @rmtoll CR2    BREN      LL_PWR_IsEnabledBkUpRegulator
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpRegulator(void)
+{
+  return ((READ_BIT(PWR->CR2, PWR_CR2_BREN) == (PWR_CR2_BREN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable VBAT and Temperature monitoring
+  * @rmtoll CR2    MONEN       LL_PWR_EnableMonitoring
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableMonitoring(void)
+{
+  SET_BIT(PWR->CR2, PWR_CR2_MONEN);
+}
+
+/**
+  * @brief  Disable VBAT and Temperature monitoring
+  * @rmtoll CR2    MONEN       LL_PWR_DisableMonitoring
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableMonitoring(void)
+{
+  CLEAR_BIT(PWR->CR2, PWR_CR2_MONEN);
+}
+
+/**
+  * @brief  Check if the VBAT and Temperature monitoring is enabled
+  * @rmtoll CR2    MONEN      LL_PWR_IsEnabledMonitoring
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledMonitoring(void)
+{
+  return ((READ_BIT(PWR->CR2, PWR_CR2_MONEN) == (PWR_CR2_MONEN)) ? 1UL : 0UL);
+}
+
+#if defined (SMPS)
+/**
+  * @brief  Configure the PWR supply
+  * @rmtoll CR3          BYPASS          LL_PWR_ConfigSupply
+  * @rmtoll CR3          LDOEN           LL_PWR_ConfigSupply
+  * @rmtoll CR3          SMPSEN          LL_PWR_ConfigSupply
+  * @rmtoll CR3          SMPSEXTHP       LL_PWR_ConfigSupply
+  * @rmtoll CR3          SMPSLEVEL       LL_PWR_ConfigSupply
+  * @param  SupplySource This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_LDO_SUPPLY
+  *         @arg @ref LL_PWR_DIRECT_SMPS_SUPPLY
+  *         @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_LDO
+  *         @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_LDO
+  *         @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO
+  *         @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO
+  *         @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_EXT
+  *         @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_EXT
+  *         @arg @ref LL_PWR_EXTERNAL_SOURCE_SUPPLY
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ConfigSupply(uint32_t SupplySource)
+{
+  /* Set the power supply configuration */
+  MODIFY_REG(PWR->CR3, (PWR_CR3_SMPSLEVEL | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS), SupplySource);
+}
+#else
+/**
+  * @brief  Configure the PWR supply
+  * @rmtoll CR3          BYPASS          LL_PWR_ConfigSupply
+  * @rmtoll CR3          LDOEN           LL_PWR_ConfigSupply
+  * @rmtoll CR3          SCUEN           LL_PWR_ConfigSupply
+  * @param  SupplySource This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_LDO_SUPPLY
+  *         @arg @ref LL_PWR_EXTERNAL_SOURCE_SUPPLY
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ConfigSupply(uint32_t SupplySource)
+{
+  /* Set the power supply configuration */
+  MODIFY_REG(PWR->CR3, (PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS), SupplySource);
+}
+#endif /* defined (SMPS) */
+
+#if defined (SMPS)
+/**
+  * @brief  Get the PWR supply
+  * @rmtoll CR3          BYPASS          LL_PWR_GetSupply
+  * @rmtoll CR3          LDOEN           LL_PWR_GetSupply
+  * @rmtoll CR3          SMPSEN          LL_PWR_GetSupply
+  * @rmtoll CR3          SMPSEXTHP       LL_PWR_GetSupply
+  * @rmtoll CR3          SMPSLEVEL       LL_PWR_GetSupply
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_LDO_SUPPLY
+  *         @arg @ref LL_PWR_DIRECT_SMPS_SUPPLY
+  *         @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_LDO
+  *         @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_LDO
+  *         @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO
+  *         @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO
+  *         @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_EXT
+  *         @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_EXT
+  *         @arg @ref LL_PWR_EXTERNAL_SOURCE_SUPPLY
+  */
+__STATIC_INLINE uint32_t LL_PWR_GetSupply(void)
+{
+  /* Get the power supply configuration */
+  return(uint32_t)(READ_BIT(PWR->CR3, (PWR_CR3_SMPSLEVEL | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)));
+}
+#else
+/**
+  * @brief  Get the PWR supply
+  * @rmtoll CR3          BYPASS          LL_PWR_GetSupply
+  * @rmtoll CR3          LDOEN           LL_PWR_GetSupply
+  * @rmtoll CR3          SCUEN           LL_PWR_GetSupply
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_LDO_SUPPLY
+  *         @arg @ref LL_PWR_EXTERNAL_SOURCE_SUPPLY
+  */
+__STATIC_INLINE uint32_t LL_PWR_GetSupply(void)
+{
+  /* Get the power supply configuration */
+  return(uint32_t)(READ_BIT(PWR->CR3, (PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)));
+}
+#endif /* defined (SMPS) */
+
+/**
+  * @brief  Enable battery charging
+  * @rmtoll CR3          VBE           LL_PWR_EnableBatteryCharging
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableBatteryCharging(void)
+{
+  SET_BIT(PWR->CR3, PWR_CR3_VBE);
+}
+
+/**
+  * @brief  Disable battery charging
+  * @rmtoll CR3          VBE           LL_PWR_DisableBatteryCharging
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableBatteryCharging(void)
+{
+  CLEAR_BIT(PWR->CR3, PWR_CR3_VBE);
+}
+
+/**
+  * @brief  Check if battery charging is enabled
+  * @rmtoll CR3          VBE           LL_PWR_IsEnabledBatteryCharging
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledBatteryCharging(void)
+{
+  return ((READ_BIT(PWR->CR3, PWR_CR3_VBE) == (PWR_CR3_VBE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the Battery charge resistor impedance
+  * @rmtoll CR3          VBRS          LL_PWR_SetBattChargResistor
+  * @param  Resistor This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
+  *         @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetBattChargResistor(uint32_t Resistor)
+{
+  MODIFY_REG(PWR->CR3, PWR_CR3_VBRS, Resistor);
+}
+
+/**
+  * @brief  Get the Battery charge resistor impedance
+  * @rmtoll CR3          VBRS          LL_PWR_GetBattChargResistor
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
+  *         @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K
+  */
+__STATIC_INLINE uint32_t LL_PWR_GetBattChargResistor(void)
+{
+  return (uint32_t)(READ_BIT(PWR->CR3, PWR_CR3_VBRS));
+}
+
+/**
+  * @brief  Enable the USB regulator
+  * @rmtoll CR3          USBREGEN           LL_PWR_EnableUSBReg
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableUSBReg(void)
+{
+  SET_BIT(PWR->CR3, PWR_CR3_USBREGEN);
+}
+
+/**
+  * @brief  Disable the USB regulator
+  * @rmtoll CR3          USBREGEN           LL_PWR_DisableUSBReg
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableUSBReg(void)
+{
+  CLEAR_BIT(PWR->CR3, PWR_CR3_USBREGEN);
+}
+
+/**
+  * @brief  Check if the USB regulator is enabled
+  * @rmtoll CR3          USBREGEN           LL_PWR_IsEnabledUSBReg
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledUSBReg(void)
+{
+  return ((READ_BIT(PWR->CR3, PWR_CR3_USBREGEN) == (PWR_CR3_USBREGEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the USB voltage detector
+  * @rmtoll CR3          USB33DEN           LL_PWR_EnableUSBVoltageDetector
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableUSBVoltageDetector(void)
+{
+  SET_BIT(PWR->CR3, PWR_CR3_USB33DEN);
+}
+
+/**
+  * @brief  Disable the USB voltage detector
+  * @rmtoll CR3          USB33DEN           LL_PWR_DisableUSBVoltageDetector
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableUSBVoltageDetector(void)
+{
+  CLEAR_BIT(PWR->CR3, PWR_CR3_USB33DEN);
+}
+
+/**
+  * @brief  Check if the USB voltage detector is enabled
+  * @rmtoll CR3          USB33DEN           LL_PWR_IsEnabledUSBVoltageDetector
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledUSBVoltageDetector(void)
+{
+  return ((READ_BIT(PWR->CR3, PWR_CR3_USB33DEN) == (PWR_CR3_USB33DEN)) ? 1UL : 0UL);
+}
+
+#if defined (PWR_CPUCR_PDDS_D2)
+/**
+  * @brief  Set the D1 domain Power Down mode when the CPU enters deepsleep
+  * @rmtoll CPUCR     PDDS_D1       LL_PWR_CPU_SetD1PowerMode
+  * @param  PDMode This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_CPU_MODE_D1STOP
+  *         @arg @ref LL_PWR_CPU_MODE_D1STANDBY
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_CPU_SetD1PowerMode(uint32_t PDMode)
+{
+  MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_D1, PDMode);
+}
+#else
+/**
+  * @brief  Set the CPU domain Power Down mode when the CPU enters deepsleep
+  * @rmtoll CPUCR     RETDS_CD       LL_PWR_CPU_SetCDPowerMode
+  * @param  PDMode This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_CPU_MODE_CDSTOP
+  *         @arg @ref LL_PWR_CPU_MODE_CDSTOP2
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_CPU_SetCDPowerMode(uint32_t PDMode)
+{
+  MODIFY_REG(PWR->CPUCR, PWR_CPUCR_RETDS_CD, PDMode);
+}
+#endif /* PWR_CPUCR_PDDS_D2 */
+
+#if defined (DUAL_CORE)
+/**
+  * @brief  Set the D1 domain Power Down mode when the CPU2 enters deepsleep
+  * @rmtoll CPU2CR     PDDS_D1       LL_PWR_CPU2_SetD1PowerMode
+  * @param  PDMode This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_CPU2_MODE_D1STOP
+  *         @arg @ref LL_PWR_CPU2_MODE_D1STANDBY
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_CPU2_SetD1PowerMode(uint32_t PDMode)
+{
+  MODIFY_REG(PWR->CPU2CR, PWR_CPU2CR_PDDS_D1, PDMode);
+}
+#endif /* DUAL_CORE */
+
+#if defined (PWR_CPUCR_PDDS_D2)
+/**
+  * @brief  Get the D1 Domain Power Down mode when the CPU enters deepsleep
+  * @rmtoll CPUCR     PDDS_D1       LL_PWR_CPU_GetD1PowerMode
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_CPU_MODE_D1STOP
+  *         @arg @ref LL_PWR_CPU_MODE_D1STANDBY
+  */
+__STATIC_INLINE uint32_t LL_PWR_CPU_GetD1PowerMode(void)
+{
+  return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D1));
+}
+#else
+/**
+  * @brief  Get the CD Domain Power Down mode when the CPU enters deepsleep
+  * @rmtoll CPUCR     RETDS_CD       LL_PWR_CPU_GetCDPowerMode
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_CPU_MODE_CDSTOP
+  *         @arg @ref LL_PWR_CPU_MODE_CDSTOP2
+  */
+__STATIC_INLINE uint32_t LL_PWR_CPU_GetCDPowerMode(void)
+{
+  return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_RETDS_CD));
+}
+#endif /* PWR_CPUCR_PDDS_D2 */
+
+#if defined (DUAL_CORE)
+/**
+  * @brief  Get the D1 Domain Power Down mode when the CPU2 enters deepsleep
+  * @rmtoll CPU2CR     PDDS_D1       LL_PWR_CPU2_GetD1PowerMode
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_CPU2_MODE_D1STOP
+  *         @arg @ref LL_PWR_CPU2_MODE_D1STANDBY
+  */
+__STATIC_INLINE uint32_t LL_PWR_CPU2_GetD1PowerMode(void)
+{
+  return (uint32_t)(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_PDDS_D1));
+}
+#endif /* DUAL_CORE */
+
+#if defined (PWR_CPUCR_PDDS_D2)
+/**
+  * @brief  Set the D2 domain Power Down mode when the CPU enters deepsleep
+  * @rmtoll CPUCR     PDDS_D2       LL_PWR_CPU_SetD2PowerMode
+  * @param  PDMode This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_CPU_MODE_D2STOP
+  *         @arg @ref LL_PWR_CPU_MODE_D2STANDBY
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_CPU_SetD2PowerMode(uint32_t PDMode)
+{
+  MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_D2, PDMode);
+}
+#endif /* PWR_CPUCR_PDDS_D2 */
+
+#if defined (DUAL_CORE)
+/**
+  * @brief  Set the D2 domain Power Down mode when the CPU2 enters deepsleep
+  * @rmtoll CPU2CR     PDDS_D2       LL_PWR_CPU2_SetD2PowerMode
+  * @param  PDMode This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_CPU2_MODE_D2STOP
+  *         @arg @ref LL_PWR_CPU2_MODE_D2STANDBY
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_CPU2_SetD2PowerMode(uint32_t PDMode)
+{
+  MODIFY_REG(PWR->CPU2CR, PWR_CPU2CR_PDDS_D2, PDMode);
+}
+#endif /* DUAL_CORE */
+
+#if defined (PWR_CPUCR_PDDS_D2)
+/**
+  * @brief  Get the D2 Domain Power Down mode when the CPU enters deepsleep
+  * @rmtoll CPUCR     PDDS_D2       LL_PWR_CPU_GetD2PowerMode
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_CPU_MODE_D2STOP
+  *         @arg @ref LL_PWR_CPU_MODE_D2STANDBY
+  */
+__STATIC_INLINE uint32_t LL_PWR_CPU_GetD2PowerMode(void)
+{
+  return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D2));
+}
+#endif /* PWR_CPUCR_PDDS_D2 */
+
+#if defined (DUAL_CORE)
+/**
+  * @brief  Get the D2 Domain Power Down mode when the CPU2 enters deepsleep
+  * @rmtoll CPU2CR     PDDS_D2       LL_PWR_CPU2_GetD2PowerMode
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_CPU2_MODE_D2STOP
+  *         @arg @ref LL_PWR_CPU2_MODE_D2STANDBY
+  */
+__STATIC_INLINE uint32_t LL_PWR_CPU2_GetD2PowerMode(void)
+{
+  return (uint32_t)(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_PDDS_D2));
+}
+#endif /* DUAL_CORE */
+
+#if defined (PWR_CPUCR_PDDS_D2)
+/**
+  * @brief  Set the D3 domain Power Down mode when the CPU enters deepsleep
+  * @rmtoll CPUCR     PDDS_D3       LL_PWR_CPU_SetD3PowerMode
+  * @param  PDMode This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_CPU_MODE_D3STOP
+  *         @arg @ref LL_PWR_CPU_MODE_D3STANDBY
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_CPU_SetD3PowerMode(uint32_t PDMode)
+{
+  MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_D3 , PDMode);
+}
+#else
+/**
+  * @brief  Set the SRD domain Power Down mode when the CPU enters deepsleep
+  * @rmtoll CPUCR     PDDS_SRD       LL_PWR_CPU_SetSRDPowerMode
+  * @param  PDMode This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_CPU_MODE_SRDSTOP
+  *         @arg @ref LL_PWR_CPU_MODE_SRDSTANDBY
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_CPU_SetSRDPowerMode(uint32_t PDMode)
+{
+  MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_SRD , PDMode);
+}
+#endif /* PWR_CPUCR_PDDS_D2 */
+
+#if defined (DUAL_CORE)
+/**
+  * @brief  Set the D3 domain Power Down mode when the CPU2 enters deepsleep
+  * @rmtoll CPU2CR     PDDS_D3       LL_PWR_CPU2_SetD3PowerMode
+  * @param  PDMode This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_CPU2_MODE_D3STOP
+  *         @arg @ref LL_PWR_CPU2_MODE_D3STANDBY
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_CPU2_SetD3PowerMode(uint32_t PDMode)
+{
+  MODIFY_REG(PWR->CPU2CR, PWR_CPU2CR_PDDS_D3, PDMode);
+}
+#endif /* DUAL_CORE */
+
+#if defined (PWR_CPUCR_PDDS_D2)
+/**
+  * @brief  Get the D3 Domain Power Down mode when the CPU enters deepsleep
+  * @rmtoll CPUCR     PDDS_D3       LL_PWR_CPU_GetD3PowerMode
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_CPU_MODE_D3STOP
+  *         @arg @ref LL_PWR_CPU_MODE_D3STANDBY
+  */
+__STATIC_INLINE uint32_t LL_PWR_CPU_GetD3PowerMode(void)
+{
+  return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D3));
+}
+#else
+/**
+  * @brief  Get the SRD Domain Power Down mode when the CPU enters deepsleep
+  * @rmtoll CPUCR     PDDS_SRD       LL_PWR_CPU_GetSRDPowerMode
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_CPU_MODE_SRDSTOP
+  *         @arg @ref LL_PWR_CPU_MODE_SRDSTANDBY
+  */
+__STATIC_INLINE uint32_t LL_PWR_CPU_GetSRDPowerMode(void)
+{
+  return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_SRD));
+}
+#endif /* PWR_CPUCR_PDDS_D2 */
+
+#if defined (DUAL_CORE)
+/**
+  * @brief  Get the D3 Domain Power Down mode when the CPU2 enters deepsleep
+  * @rmtoll CPU2CR     PDDS_D3       LL_PWR_CPU2_GetD3PowerMode
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_CPU2_MODE_D3STOP
+  *         @arg @ref LL_PWR_CPU2_MODE_D3STANDBY
+  */
+__STATIC_INLINE uint32_t LL_PWR_CPU2_GetD3PowerMode(void)
+{
+  return (uint32_t)(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_PDDS_D3));
+}
+#endif /* DUAL_CORE */
+
+#if defined (DUAL_CORE)
+/**
+  * @brief  Hold the CPU1 and allocated peripherals when exiting from STOP mode
+  * @rmtoll CPU2CR     HOLD1       LL_PWR_HoldCPU1
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_HoldCPU1(void)
+{
+  SET_BIT(PWR->CPU2CR, PWR_CPU2CR_HOLD1);
+}
+
+/**
+  * @brief  Release the CPU1 and allocated peripherals
+  * @rmtoll CPU2CR     HOLD1       LL_PWR_ReleaseCPU1
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ReleaseCPU1(void)
+{
+  CLEAR_BIT(PWR->CPU2CR, PWR_CPU2CR_HOLD1);
+}
+
+/**
+  * @brief  Ckeck if the CPU1 and allocated peripherals are held
+  * @rmtoll CPU2CR     HOLD1       LL_PWR_IsCPU1Held
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsCPU1Held(void)
+{
+  return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_HOLD1) == (PWR_CPU2CR_HOLD1))  ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Hold the CPU2 and allocated peripherals when exiting from STOP mode
+  * @rmtoll CPUCR     HOLD2       LL_PWR_HoldCPU2
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_HoldCPU2(void)
+{
+  SET_BIT(PWR->CPUCR, PWR_CPUCR_HOLD2);
+}
+
+/**
+  * @brief  Release the CPU2 and allocated peripherals
+  * @rmtoll CPUCR     HOLD2       LL_PWR_ReleaseCPU2
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ReleaseCPU2(void)
+{
+  CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_HOLD2);
+}
+
+/**
+  * @brief  Ckeck if the CPU2 and allocated peripherals are held
+  * @rmtoll CPUCR     HOLD2       LL_PWR_IsCPU2Held
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsCPU2Held(void)
+{
+  return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_HOLD2) == (PWR_CPUCR_HOLD2)) ? 1UL : 0UL);
+}
+#endif /* DUAL_CORE */
+
+#if defined (PWR_CPUCR_PDDS_D2)
+/**
+  * @brief  D3 domain remains in Run mode regardless of CPU subsystem modes
+  * @rmtoll CPUCR     RUN_D3       LL_PWR_CPU_EnableD3RunInLowPowerMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_CPU_EnableD3RunInLowPowerMode(void)
+{
+  SET_BIT(PWR->CPUCR, PWR_CPUCR_RUN_D3);
+}
+#else
+/**
+  * @brief  SRD domain remains in Run mode regardless of CPU subsystem modes
+  * @rmtoll CPUCR     RUN_SRD      LL_PWR_CPU_EnableSRDRunInLowPowerMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_CPU_EnableSRDRunInLowPowerMode(void)
+{
+  SET_BIT(PWR->CPUCR, PWR_CPUCR_RUN_SRD);
+}
+#endif /* PWR_CPUCR_PDDS_D2 */
+
+#if defined (DUAL_CORE)
+/**
+  * @brief  D3 domain remains in Run mode regardless of CPU2 subsystem modes
+  * @rmtoll CPU2CR     RUN_D3       LL_PWR_CPU2_EnableD3RunInLowPowerMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_CPU2_EnableD3RunInLowPowerMode(void)
+{
+  SET_BIT(PWR->CPU2CR, PWR_CPU2CR_RUN_D3);
+}
+#endif /* DUAL_CORE */
+
+#if defined (PWR_CPUCR_PDDS_D2)
+/**
+  * @brief  D3 domain follows CPU subsystem modes
+  * @rmtoll CPUCR     RUN_D3       LL_PWR_CPU_DisableD3RunInLowPowerMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_CPU_DisableD3RunInLowPowerMode(void)
+{
+  CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_RUN_D3);
+}
+#else
+/**
+  * @brief  SRD domain follows CPU subsystem modes
+  * @rmtoll CPUCR     RUN_SRD      LL_PWR_CPU_DisableSRDRunInLowPowerMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_CPU_DisableSRDRunInLowPowerMode(void)
+{
+  CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_RUN_SRD);
+}
+#endif /* PWR_CPUCR_PDDS_D2 */
+
+#if defined (DUAL_CORE)
+/**
+  * @brief  D3 domain follows CPU2 subsystem modes
+  * @rmtoll CPU2CR     RUN_D3       LL_PWR_CPU2_DisableD3RunInLowPowerMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_CPU2_DisableD3RunInLowPowerMode(void)
+{
+  CLEAR_BIT(PWR->CPU2CR, PWR_CPU2CR_RUN_D3);
+}
+#endif /* DUAL_CORE */
+
+#if defined (PWR_CPUCR_PDDS_D2)
+/**
+  * @brief  Check if D3 is kept in Run mode when CPU enters low power mode
+  * @rmtoll CPUCR     RUN_D3    LL_PWR_CPU_IsEnabledD3RunInLowPowerMode
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_CPU_IsEnabledD3RunInLowPowerMode(void)
+{
+  return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_RUN_D3) == (PWR_CPUCR_RUN_D3)) ? 1UL : 0UL);
+}
+#else
+/**
+  * @brief  Check if SRD is kept in Run mode when CPU enters low power mode
+  * @rmtoll CPUCR     RUN_SRD    LL_PWR_CPU_IsEnabledSRDRunInLowPowerMode
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_CPU_IsEnabledSRDRunInLowPowerMode(void)
+{
+  return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_RUN_SRD) == (PWR_CPUCR_RUN_SRD)) ? 1UL : 0UL);
+}
+#endif /* PWR_CPUCR_PDDS_D2 */
+
+#if defined (DUAL_CORE)
+/**
+  * @brief  Check if D3 is kept in Run mode when CPU2 enters low power mode
+  * @rmtoll CPU2CR     RUN_D3    LL_PWR_CPU2_IsEnabledD3RunInLowPowerMode
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_CPU2_IsEnabledD3RunInLowPowerMode(void)
+{
+  return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_RUN_D3) == (PWR_CPU2CR_RUN_D3)) ? 1UL : 0UL);
+}
+#endif /* DUAL_CORE */
+
+/**
+  * @brief  Set the main internal Regulator output voltage
+  * @rmtoll D3CR    VOS       LL_PWR_SetRegulVoltageScaling
+  * @param  VoltageScaling This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE0
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
+  * @note   For all H7 lines except STM32H7Axxx and STM32H7Bxxx lines, VOS0
+  *         is applied when PWR_D3CR_VOS[1:0] = 0b11 and  SYSCFG_PWRCR_ODEN = 0b1.
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
+{
+#if defined (PWR_CPUCR_PDDS_D2)
+  MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, VoltageScaling);
+#else
+  MODIFY_REG(PWR->SRDCR, PWR_SRDCR_VOS, VoltageScaling);
+#endif /* PWR_CPUCR_PDDS_D2 */
+}
+
+/**
+  * @brief  Get the main internal Regulator output voltage
+  * @rmtoll D3CR    VOS       LL_PWR_GetRegulVoltageScaling
+  * @note   For all H7 lines except STM32H7Axxx and STM32H7Bxxx lines, checking
+  *         VOS0 need the check of PWR_D3CR_VOS[1:0] field and SYSCFG_PWRCR_ODEN bit.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE0
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
+  */
+__STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void)
+{
+#if defined (PWR_CPUCR_PDDS_D2)
+  return (uint32_t)(READ_BIT(PWR->D3CR, PWR_D3CR_VOS));
+#else
+  return (uint32_t)(READ_BIT(PWR->SRDCR, PWR_SRDCR_VOS));
+#endif /* PWR_CPUCR_PDDS_D2 */
+}
+
+/**
+  * @brief  Enable the WakeUp PINx functionality
+  * @rmtoll WKUPEPR   WKUPEN1       LL_PWR_EnableWakeUpPin\n
+  *         WKUPEPR   WKUPEN2       LL_PWR_EnableWakeUpPin\n
+  *         WKUPEPR   WKUPEN3       LL_PWR_EnableWakeUpPin\n
+  *         WKUPEPR   WKUPEN4       LL_PWR_EnableWakeUpPin\n
+  *         WKUPEPR   WKUPEN5       LL_PWR_EnableWakeUpPin\n
+  *         WKUPEPR   WKUPEN6       LL_PWR_EnableWakeUpPin
+  * @param  WakeUpPin This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_WAKEUP_PIN1
+  *         @arg @ref LL_PWR_WAKEUP_PIN2
+  *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
+  *         @arg @ref LL_PWR_WAKEUP_PIN4
+  *         @arg @ref LL_PWR_WAKEUP_PIN5 (*)
+  *         @arg @ref LL_PWR_WAKEUP_PIN6
+  *
+  *         (*) value not defined in all devices.
+  *
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
+{
+  SET_BIT(PWR->WKUPEPR, WakeUpPin);
+}
+
+/**
+  * @brief  Disable the WakeUp PINx functionality
+  * @rmtoll WKUPEPR   WKUPEN1       LL_PWR_DisableWakeUpPin\n
+  *         WKUPEPR   WKUPEN2       LL_PWR_DisableWakeUpPin\n
+  *         WKUPEPR   WKUPEN3       LL_PWR_DisableWakeUpPin\n
+  *         WKUPEPR   WKUPEN4       LL_PWR_DisableWakeUpPin\n
+  *         WKUPEPR   WKUPEN5       LL_PWR_DisableWakeUpPin\n
+  *         WKUPEPR   WKUPEN6       LL_PWR_DisableWakeUpPin
+  * @param  WakeUpPin This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_WAKEUP_PIN1
+  *         @arg @ref LL_PWR_WAKEUP_PIN2
+  *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
+  *         @arg @ref LL_PWR_WAKEUP_PIN4
+  *         @arg @ref LL_PWR_WAKEUP_PIN5 (*)
+  *         @arg @ref LL_PWR_WAKEUP_PIN6
+  *
+  *         (*) value not defined in all devices.
+  *
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
+{
+  CLEAR_BIT(PWR->WKUPEPR, WakeUpPin);
+}
+
+/**
+  * @brief  Check if the WakeUp PINx functionality is enabled
+  * @rmtoll WKUPEPR   WKUPEN1       LL_PWR_IsEnabledWakeUpPin\n
+  *         WKUPEPR   WKUPEN2       LL_PWR_IsEnabledWakeUpPin\n
+  *         WKUPEPR   WKUPEN3       LL_PWR_IsEnabledWakeUpPin\n
+  *         WKUPEPR   WKUPEN4       LL_PWR_IsEnabledWakeUpPin\n
+  *         WKUPEPR   WKUPEN5       LL_PWR_IsEnabledWakeUpPin\n
+  *         WKUPEPR   WKUPEN6       LL_PWR_IsEnabledWakeUpPin
+  * @param  WakeUpPin This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_WAKEUP_PIN1
+  *         @arg @ref LL_PWR_WAKEUP_PIN2
+  *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
+  *         @arg @ref LL_PWR_WAKEUP_PIN4
+  *         @arg @ref LL_PWR_WAKEUP_PIN5 (*)
+  *         @arg @ref LL_PWR_WAKEUP_PIN6
+  *
+  *         (*) value not defined in all devices.
+  *
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
+{
+  return ((READ_BIT(PWR->WKUPEPR, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the Wake-Up pin polarity low for the event detection
+  * @rmtoll WKUPEPR   WKUPP1       LL_PWR_SetWakeUpPinPolarityLow\n
+  *         WKUPEPR   WKUPP2       LL_PWR_SetWakeUpPinPolarityLow\n
+  *         WKUPEPR   WKUPP3       LL_PWR_SetWakeUpPinPolarityLow\n
+  *         WKUPEPR   WKUPP4       LL_PWR_SetWakeUpPinPolarityLow\n
+  *         WKUPEPR   WKUPP5       LL_PWR_SetWakeUpPinPolarityLow\n
+  *         WKUPEPR   WKUPP6       LL_PWR_SetWakeUpPinPolarityLow
+  * @param  WakeUpPin This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_WAKEUP_PIN1
+  *         @arg @ref LL_PWR_WAKEUP_PIN2
+  *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
+  *         @arg @ref LL_PWR_WAKEUP_PIN4
+  *         @arg @ref LL_PWR_WAKEUP_PIN5 (*)
+  *         @arg @ref LL_PWR_WAKEUP_PIN6
+  *
+  *         (*) value not defined in all devices.
+  *
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)
+{
+  SET_BIT(PWR->WKUPEPR, (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos));
+}
+
+/**
+  * @brief  Set the Wake-Up pin polarity high for the event detection
+  * @rmtoll WKUPEPR   WKUPP1       LL_PWR_SetWakeUpPinPolarityHigh\n
+  *         WKUPEPR   WKUPP2       LL_PWR_SetWakeUpPinPolarityHigh\n
+  *         WKUPEPR   WKUPP3       LL_PWR_SetWakeUpPinPolarityHigh\n
+  *         WKUPEPR   WKUPP4       LL_PWR_SetWakeUpPinPolarityHigh\n
+  *         WKUPEPR   WKUPP5       LL_PWR_SetWakeUpPinPolarityHigh\n
+  *         WKUPEPR   WKUPP6       LL_PWR_SetWakeUpPinPolarityHigh
+  * @param  WakeUpPin This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_WAKEUP_PIN1
+  *         @arg @ref LL_PWR_WAKEUP_PIN2
+  *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
+  *         @arg @ref LL_PWR_WAKEUP_PIN4
+  *         @arg @ref LL_PWR_WAKEUP_PIN5 (*)
+  *         @arg @ref LL_PWR_WAKEUP_PIN6
+  *
+  *         (*) value not defined in all devices.
+  *
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)
+{
+  CLEAR_BIT(PWR->WKUPEPR, (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos));
+}
+
+/**
+  * @brief  Get the Wake-Up pin polarity for the event detection
+  * @rmtoll WKUPEPR   WKUPP1       LL_PWR_IsWakeUpPinPolarityLow\n
+  *         WKUPEPR   WKUPP2       LL_PWR_IsWakeUpPinPolarityLow\n
+  *         WKUPEPR   WKUPP3       LL_PWR_IsWakeUpPinPolarityLow\n
+  *         WKUPEPR   WKUPP4       LL_PWR_IsWakeUpPinPolarityLow\n
+  *         WKUPEPR   WKUPP5       LL_PWR_IsWakeUpPinPolarityLow\n
+  *         WKUPEPR   WKUPP6       LL_PWR_IsWakeUpPinPolarityLow
+  * @param  WakeUpPin This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_WAKEUP_PIN1
+  *         @arg @ref LL_PWR_WAKEUP_PIN2
+  *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
+  *         @arg @ref LL_PWR_WAKEUP_PIN4
+  *         @arg @ref LL_PWR_WAKEUP_PIN5 (*)
+  *         @arg @ref LL_PWR_WAKEUP_PIN6
+  *
+  *         (*) value not defined in all devices.
+  *
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)
+{
+  return ((READ_BIT(PWR->WKUPEPR, (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos)) == (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the Wake-Up pin Pull None
+  * @rmtoll WKUPEPR   WKUPPUPD1       LL_PWR_SetWakeUpPinPullNone\n
+  *         WKUPEPR   WKUPPUPD2       LL_PWR_SetWakeUpPinPullNone\n
+  *         WKUPEPR   WKUPPUPD3       LL_PWR_SetWakeUpPinPullNone\n
+  *         WKUPEPR   WKUPPUPD4       LL_PWR_SetWakeUpPinPullNone\n
+  *         WKUPEPR   WKUPPUPD5       LL_PWR_SetWakeUpPinPullNone\n
+  *         WKUPEPR   WKUPPUPD6       LL_PWR_SetWakeUpPinPullNone
+  * @param  WakeUpPin This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_WAKEUP_PIN1
+  *         @arg @ref LL_PWR_WAKEUP_PIN2
+  *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
+  *         @arg @ref LL_PWR_WAKEUP_PIN4
+  *         @arg @ref LL_PWR_WAKEUP_PIN5 (*)
+  *         @arg @ref LL_PWR_WAKEUP_PIN6
+  *
+  *         (*) value not defined in all devices.
+  *
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetWakeUpPinPullNone(uint32_t WakeUpPin)
+{
+  MODIFY_REG(PWR->WKUPEPR, \
+            (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)), \
+            (LL_PWR_WAKEUP_PIN_NOPULL << ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));
+}
+
+/**
+  * @brief  Set the Wake-Up pin Pull Up
+  * @rmtoll WKUPEPR   WKUPPUPD1       LL_PWR_SetWakeUpPinPullUp\n
+  *         WKUPEPR   WKUPPUPD2       LL_PWR_SetWakeUpPinPullUp\n
+  *         WKUPEPR   WKUPPUPD3       LL_PWR_SetWakeUpPinPullUp\n
+  *         WKUPEPR   WKUPPUPD4       LL_PWR_SetWakeUpPinPullUp\n
+  *         WKUPEPR   WKUPPUPD5       LL_PWR_SetWakeUpPinPullUp\n
+  *         WKUPEPR   WKUPPUPD6       LL_PWR_SetWakeUpPinPullUp
+  * @param  WakeUpPin This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_WAKEUP_PIN1
+  *         @arg @ref LL_PWR_WAKEUP_PIN2
+  *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
+  *         @arg @ref LL_PWR_WAKEUP_PIN4
+  *         @arg @ref LL_PWR_WAKEUP_PIN5 (*)
+  *         @arg @ref LL_PWR_WAKEUP_PIN6
+  *
+  *         (*) value not defined in all devices.
+  *
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetWakeUpPinPullUp(uint32_t WakeUpPin)
+{
+  MODIFY_REG(PWR->WKUPEPR, \
+            (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)), \
+            (LL_PWR_WAKEUP_PIN_PULLUP << ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));
+}
+
+/**
+  * @brief  Set the Wake-Up pin Pull Down
+  * @rmtoll WKUPEPR   WKUPPUPD1       LL_PWR_SetWakeUpPinPullDown\n
+  *         WKUPEPR   WKUPPUPD2       LL_PWR_SetWakeUpPinPullDown\n
+  *         WKUPEPR   WKUPPUPD3       LL_PWR_SetWakeUpPinPullDown\n
+  *         WKUPEPR   WKUPPUPD4       LL_PWR_SetWakeUpPinPullDown\n
+  *         WKUPEPR   WKUPPUPD5       LL_PWR_SetWakeUpPinPullDown\n
+  *         WKUPEPR   WKUPPUPD6       LL_PWR_SetWakeUpPinPullDown
+  * @param  WakeUpPin This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_WAKEUP_PIN1
+  *         @arg @ref LL_PWR_WAKEUP_PIN2
+  *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
+  *         @arg @ref LL_PWR_WAKEUP_PIN4
+  *         @arg @ref LL_PWR_WAKEUP_PIN5 (*)
+  *         @arg @ref LL_PWR_WAKEUP_PIN6
+  *
+  *         (*) value not defined in all devices.
+  *
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetWakeUpPinPullDown(uint32_t WakeUpPin)
+{
+  MODIFY_REG(PWR->WKUPEPR, \
+            (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)), \
+            (LL_PWR_WAKEUP_PIN_PULLDOWN << ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));
+}
+
+/**
+  * @brief  Get the Wake-Up pin pull
+  * @rmtoll WKUPEPR   WKUPPUPD1       LL_PWR_GetWakeUpPinPull\n
+  *         WKUPEPR   WKUPPUPD2       LL_PWR_GetWakeUpPinPull\n
+  *         WKUPEPR   WKUPPUPD3       LL_PWR_GetWakeUpPinPull\n
+  *         WKUPEPR   WKUPPUPD4       LL_PWR_GetWakeUpPinPull\n
+  *         WKUPEPR   WKUPPUPD5       LL_PWR_GetWakeUpPinPull\n
+  *         WKUPEPR   WKUPPUPD6       LL_PWR_GetWakeUpPinPull
+  * @param  WakeUpPin This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_WAKEUP_PIN1
+  *         @arg @ref LL_PWR_WAKEUP_PIN2
+  *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
+  *         @arg @ref LL_PWR_WAKEUP_PIN4
+  *         @arg @ref LL_PWR_WAKEUP_PIN5 (*)
+  *         @arg @ref LL_PWR_WAKEUP_PIN6
+  *
+  *         (*) value not defined in all devices.
+  *
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_WAKEUP_PIN_NOPULL
+  *         @arg @ref LL_PWR_WAKEUP_PIN_PULLUP
+  *         @arg @ref LL_PWR_WAKEUP_PIN_PULLDOWN
+  */
+__STATIC_INLINE uint32_t LL_PWR_GetWakeUpPinPull(uint32_t WakeUpPin)
+{
+  uint32_t regValue = READ_BIT(PWR->WKUPEPR, (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));
+
+  return (uint32_t)(regValue >> ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
+  * @{
+  */
+
+/**
+  * @brief  Indicate whether VDD voltage is below the selected PVD threshold
+  * @rmtoll CSR1   PVDO       LL_PWR_IsActiveFlag_PVDO
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
+{
+  return ((READ_BIT(PWR->CSR1, PWR_CSR1_PVDO) == (PWR_CSR1_PVDO)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate whether the voltage level is ready for current actual used VOS
+  * @rmtoll CSR1   ACTVOSRDY       LL_PWR_IsActiveFlag_ACTVOS
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_ACTVOS(void)
+{
+  return ((READ_BIT(PWR->CSR1, PWR_CSR1_ACTVOSRDY) == (PWR_CSR1_ACTVOSRDY)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate whether VDDA voltage is below the selected AVD threshold
+  * @rmtoll CSR1   AVDO       LL_PWR_IsActiveFlag_AVDO
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_AVDO(void)
+{
+  return ((READ_BIT(PWR->CSR1, PWR_CSR1_AVDO) == (PWR_CSR1_AVDO)) ? 1UL : 0UL);
+}
+
+#if defined (PWR_CSR1_MMCVDO)
+/**
+  * @brief  Indicate whether VDDMMC voltage is below 1V2
+  * @rmtoll CSR1   MMCVDO     LL_PWR_IsActiveFlag_MMCVDO
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_MMCVDO(void)
+{
+  return ((READ_BIT(PWR->CSR1, PWR_CSR1_MMCVDO) == (PWR_CSR1_MMCVDO)) ? 1UL : 0UL);
+}
+#endif /* PWR_CSR1_MMCVDO */
+
+/**
+  * @brief  Get Backup Regulator ready Flag
+  * @rmtoll CR2   BRRDY       LL_PWR_IsActiveFlag_BRR
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BRR(void)
+{
+  return ((READ_BIT(PWR->CR2, PWR_CR2_BRRDY) == (PWR_CR2_BRRDY)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate whether the VBAT level is above or below low threshold
+  * @rmtoll CR2   VBATL       LL_PWR_IsActiveFlag_VBATL
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VBATL(void)
+{
+  return ((READ_BIT(PWR->CR2, PWR_CR2_VBATL) == (PWR_CR2_VBATL)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate whether the VBAT level is above or below high threshold
+  * @rmtoll CR2   VBATH       LL_PWR_IsActiveFlag_VBATH
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VBATH(void)
+{
+  return ((READ_BIT(PWR->CR2, PWR_CR2_VBATH) == (PWR_CR2_VBATH)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate whether the CPU temperature level is above or below low threshold
+  * @rmtoll CR2   TEMPL       LL_PWR_IsActiveFlag_TEMPL
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_TEMPL(void)
+{
+  return ((READ_BIT(PWR->CR2, PWR_CR2_TEMPL) == (PWR_CR2_TEMPL)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate whether the CPU temperature level is above or below high threshold
+  * @rmtoll CR2   TEMPH       LL_PWR_IsActiveFlag_TEMPH
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_TEMPH(void)
+{
+  return ((READ_BIT(PWR->CR2, PWR_CR2_TEMPH) == (PWR_CR2_TEMPH)) ? 1UL : 0UL);
+}
+
+#if defined (SMPS)
+/**
+  * @brief  Indicate whether the SMPS external supply is ready or not
+  * @rmtoll CR3   SMPSEXTRDY       LL_PWR_IsActiveFlag_SMPSEXT
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SMPSEXT(void)
+{
+  return ((READ_BIT(PWR->CR3, PWR_CR3_SMPSEXTRDY) == (PWR_CR3_SMPSEXTRDY)) ? 1UL : 0UL);
+}
+#endif /* SMPS */
+
+/**
+  * @brief  Indicate whether the USB supply is ready or not
+  * @rmtoll CR3   USBRDY       LL_PWR_IsActiveFlag_USB
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_USB(void)
+{
+  return ((READ_BIT(PWR->CR3, PWR_CR3_USB33RDY) == (PWR_CR3_USB33RDY)) ? 1UL : 0UL);
+}
+
+#if defined (DUAL_CORE)
+/**
+  * @brief  Get HOLD2 Flag
+  * @rmtoll CPUCR   HOLD2F       LL_PWR_IsActiveFlag_HOLD2
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_HOLD2(void)
+{
+  return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_HOLD2F) == (PWR_CPUCR_HOLD2F)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get HOLD1 Flag
+  * @rmtoll CPU2CR   HOLD1F       LL_PWR_IsActiveFlag_HOLD1
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_HOLD1(void)
+{
+  return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_HOLD1F) == (PWR_CPU2CR_HOLD1F)) ? 1UL : 0UL);
+}
+#endif /* DUAL_CORE */
+
+/**
+  * @brief  Get CPU System Stop Flag
+  * @rmtoll CPUCR   STOPF       LL_PWR_CPU_IsActiveFlag_STOP
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_CPU_IsActiveFlag_STOP(void)
+{
+  return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_STOPF) == (PWR_CPUCR_STOPF)) ? 1UL : 0UL);
+}
+
+#if defined (DUAL_CORE)
+/**
+  * @brief  Get CPU2 System Stop Flag
+  * @rmtoll CPU2CR   STOPF       LL_PWR_CPU2_IsActiveFlag_STOP
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_CPU2_IsActiveFlag_STOP(void)
+{
+  return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_STOPF) == (PWR_CPU2CR_STOPF)) ? 1UL : 0UL);
+}
+#endif /* DUAL_CORE */
+
+/**
+  * @brief  Get CPU System Standby Flag
+  * @rmtoll CPUCR   SBF       LL_PWR_CPU_IsActiveFlag_SB
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_CPU_IsActiveFlag_SB(void)
+{
+  return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF) == (PWR_CPUCR_SBF)) ? 1UL : 0UL);
+}
+
+#if defined (DUAL_CORE)
+/**
+  * @brief  Get CPU2 System Standby Flag
+  * @rmtoll CPU2CR   SBF       LL_PWR_CPU2_IsActiveFlag_SB
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_CPU2_IsActiveFlag_SB(void)
+{
+  return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_SBF) == (PWR_CPU2CR_SBF)) ? 1UL : 0UL);
+}
+#endif /* DUAL_CORE */
+
+#if defined (PWR_CPUCR_SBF_D1)
+/**
+  * @brief  Get CPU D1 Domain Standby Flag
+  * @rmtoll CPUCR   SBF_D1       LL_PWR_CPU_IsActiveFlag_SB_D1
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_CPU_IsActiveFlag_SB_D1(void)
+{
+  return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF_D1) == (PWR_CPUCR_SBF_D1)) ? 1UL : 0UL);
+}
+#endif /* PWR_CPUCR_SBF_D1 */
+
+#if defined (DUAL_CORE)
+/**
+  * @brief  Get CPU2 D1 Domain Standby Flag
+  * @rmtoll CPU2CR   SBF_D1       LL_PWR_CPU2_IsActiveFlag_SB_D1
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_CPU2_IsActiveFlag_SB_D1(void)
+{
+  return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_SBF_D1) == (PWR_CPU2CR_SBF_D1)) ? 1UL : 0UL);
+}
+#endif /* DUAL_CORE */
+
+#if defined (PWR_CPUCR_SBF_D2)
+/**
+  * @brief  Get CPU D2 Domain Standby Flag
+  * @rmtoll CPUCR   SBF_D2       LL_PWR_CPU_IsActiveFlag_SB_D2
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_CPU_IsActiveFlag_SB_D2(void)
+{
+  return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF_D2) == (PWR_CPUCR_SBF_D2)) ? 1UL : 0UL);
+}
+#endif /* PWR_CPUCR_SBF_D2 */
+
+#if defined (DUAL_CORE)
+/**
+  * @brief  Get CPU2 D2 Domain Standby Flag
+  * @rmtoll CPU2CR   SBF_D2       LL_PWR_CPU2_IsActiveFlag_SB_D2
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_CPU2_IsActiveFlag_SB_D2(void)
+{
+  return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_SBF_D2) == (PWR_CPU2CR_SBF_D2)) ? 1UL : 0UL);
+}
+#endif /* DUAL_CORE */
+
+
+/**
+  * @brief  Indicate whether the Regulator is ready in the selected voltage range
+  *         or if its output voltage is still changing to the required voltage level
+  * @rmtoll D3CR   VOSRDY       LL_PWR_IsActiveFlag_VOS
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void)
+{
+#if defined (PWR_CPUCR_PDDS_D2)
+  return ((READ_BIT(PWR->D3CR, PWR_D3CR_VOSRDY) == (PWR_D3CR_VOSRDY)) ? 1UL : 0UL);
+#else
+  return ((READ_BIT(PWR->SRDCR, PWR_SRDCR_VOSRDY) == (PWR_SRDCR_VOSRDY)) ? 1UL : 0UL);
+#endif /* PWR_CPUCR_PDDS_D2 */
+}
+
+/**
+  * @brief  Get Wake-up Flag 6
+  * @rmtoll WKUPFR          WKUPF6          LL_PWR_IsActiveFlag_WU6
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU6(void)
+{
+  return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF6) == (PWR_WKUPFR_WKUPF6)) ? 1UL : 0UL);
+}
+
+#if defined (PWR_WKUPFR_WKUPF5)
+/**
+  * @brief  Get Wake-up Flag 5
+  * @rmtoll WKUPFR          WKUPF5          LL_PWR_IsActiveFlag_WU5
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void)
+{
+  return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF5) == (PWR_WKUPFR_WKUPF5)) ? 1UL : 0UL);
+}
+#endif /* defined (PWR_WKUPFR_WKUPF5) */
+
+/**
+  * @brief  Get Wake-up Flag 4
+  * @rmtoll WKUPFR          WKUPF4          LL_PWR_IsActiveFlag_WU4
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void)
+{
+  return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF4) == (PWR_WKUPFR_WKUPF4)) ? 1UL : 0UL);
+}
+
+#if defined (PWR_WKUPFR_WKUPF3)
+/**
+  * @brief  Get Wake-up Flag 3
+  * @rmtoll WKUPFR          WKUPF3          LL_PWR_IsActiveFlag_WU3
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void)
+{
+  return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF3) == (PWR_WKUPFR_WKUPF3)) ? 1UL : 0UL);
+}
+#endif /* defined (PWR_WKUPFR_WKUPF3) */
+
+/**
+  * @brief  Get Wake-up Flag 2
+  * @rmtoll WKUPFR          WKUPF2          LL_PWR_IsActiveFlag_WU2
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void)
+{
+  return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF2) == (PWR_WKUPFR_WKUPF2)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Wake-up Flag 1
+  * @rmtoll WKUPFR          WKUPF1          LL_PWR_IsActiveFlag_WU1
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void)
+{
+  return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF1) == (PWR_WKUPFR_WKUPF1)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear CPU STANDBY, STOP and HOLD flags
+  * @rmtoll CPUCR   CSSF       LL_PWR_ClearFlag_CPU
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ClearFlag_CPU(void)
+{
+  SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF);
+}
+
+#if defined (DUAL_CORE)
+/**
+  * @brief  Clear CPU2 STANDBY, STOP and HOLD flags
+  * @rmtoll CPU2CR   CSSF       LL_PWR_ClearFlag_CPU2
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ClearFlag_CPU2(void)
+{
+  SET_BIT(PWR->CPU2CR, PWR_CPU2CR_CSSF);
+}
+#endif /* DUAL_CORE */
+
+/**
+  * @brief  Clear Wake-up Flag 6
+  * @rmtoll WKUPCR          WKUPC6         LL_PWR_ClearFlag_WU6
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ClearFlag_WU6(void)
+{
+  WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC6);
+}
+
+#if defined (PWR_WKUPCR_WKUPC5)
+/**
+  * @brief  Clear Wake-up Flag 5
+  * @rmtoll WKUPCR          WKUPC5         LL_PWR_ClearFlag_WU5
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ClearFlag_WU5(void)
+{
+  WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC5);
+}
+#endif /* defined (PWR_WKUPCR_WKUPC5) */
+
+/**
+  * @brief  Clear Wake-up Flag 4
+  * @rmtoll WKUPCR          WKUPC4         LL_PWR_ClearFlag_WU4
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ClearFlag_WU4(void)
+{
+  WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC4);
+}
+
+#if defined (PWR_WKUPCR_WKUPC3)
+/**
+  * @brief  Clear Wake-up Flag 3
+  * @rmtoll WKUPCR          WKUPC3         LL_PWR_ClearFlag_WU3
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ClearFlag_WU3(void)
+{
+  WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC3);
+}
+#endif /* defined (PWR_WKUPCR_WKUPC3) */
+
+/**
+  * @brief  Clear Wake-up Flag 2
+  * @rmtoll WKUPCR          WKUPC2         LL_PWR_ClearFlag_WU2
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ClearFlag_WU2(void)
+{
+  WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC2);
+}
+
+/**
+  * @brief  Clear Wake-up Flag 1
+  * @rmtoll WKUPCR          WKUPC1         LL_PWR_ClearFlag_WU1
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ClearFlag_WU1(void)
+{
+  WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC1);
+}
+
+#if defined (USE_FULL_LL_DRIVER)
+/** @defgroup PWR_LL_EF_Init De-initialization function
+  * @{
+  */
+ErrorStatus LL_PWR_DeInit(void);
+/**
+  * @}
+  */
+#endif /* defined (USE_FULL_LL_DRIVER) */
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined (PWR) */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_LL_PWR_H */
+
diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_rcc.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_rcc.h
index 50230079..2dffcca0 100644
--- a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_rcc.h
+++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_rcc.h
@@ -1,6407 +1,6407 @@
-/**
-  ******************************************************************************
-  * @file    stm32h7xx_ll_rcc.h
-  * @author  MCD Application Team
-  * @brief   Header file of RCC LL module.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file in
-  * the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32H7xx_LL_RCC_H
-#define STM32H7xx_LL_RCC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx.h"
-#include <math.h>
-
-/** @addtogroup STM32H7xx_LL_Driver
-  * @{
-  */
-
-#if defined(RCC)
-
-/** @defgroup RCC_LL RCC
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup RCC_LL_Private_Variables RCC Private Variables
-  * @{
-  */
-extern const uint8_t LL_RCC_PrescTable[16];
-
-/**
-  * @}
-  */
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-#if !defined(UNUSED)
-#define UNUSED(x) ((void)(x))
-#endif
-
-/* 32            24           16            8             0
-   --------------------------------------------------------
-   | Mask        | ClkSource   |  Bit       | Register    |
-   |             |  Config     | Position   | Offset      |
-   --------------------------------------------------------*/
-
-#if defined(RCC_VER_2_0)
-/* Clock source register offset Vs CDCCIPR register */
-#define CDCCIP    0x0UL
-#define CDCCIP1   0x4UL
-#define CDCCIP2   0x8UL
-#define SRDCCIP   0xCUL
-#else
-/* Clock source register offset Vs D1CCIPR register */
-#define D1CCIP    0x0UL
-#define D2CCIP1   0x4UL
-#define D2CCIP2   0x8UL
-#define D3CCIP    0xCUL
-#endif /* RCC_VER_2_0 */
-
-#define LL_RCC_REG_SHIFT     0U
-#define LL_RCC_POS_SHIFT     8U
-#define LL_RCC_CONFIG_SHIFT  16U
-#define LL_RCC_MASK_SHIFT    24U
-
-#define LL_CLKSOURCE_SHIFT(__CLKSOURCE__)   (((__CLKSOURCE__) >> LL_RCC_POS_SHIFT   ) & 0x1FUL)
-
-#define LL_CLKSOURCE_MASK(__CLKSOURCE__)   ((((__CLKSOURCE__) >> LL_RCC_MASK_SHIFT  ) & 0xFFUL) << LL_CLKSOURCE_SHIFT(__CLKSOURCE__))
-
-#define LL_CLKSOURCE_CONFIG(__CLKSOURCE__) ((((__CLKSOURCE__) >> LL_RCC_CONFIG_SHIFT) & 0xFFUL) << LL_CLKSOURCE_SHIFT(__CLKSOURCE__))
-
-#define LL_CLKSOURCE_REG(__CLKSOURCE__)     (((__CLKSOURCE__) >> LL_RCC_REG_SHIFT   ) & 0xFFUL)
-
-#define LL_CLKSOURCE(__REG__, __MSK__, __POS__, __CLK__) ((uint32_t)((((__MSK__) >> (__POS__)) << LL_RCC_MASK_SHIFT) | \
-                                                                     (( __POS__              ) << LL_RCC_POS_SHIFT)  | \
-                                                                     (( __REG__              ) << LL_RCC_REG_SHIFT)  | \
-                                                                     (((__CLK__) >> (__POS__)) << LL_RCC_CONFIG_SHIFT)))
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup RCC_LL_Private_Macros RCC Private Macros
-  * @{
-  */
-/**
-  * @}
-  */
-#endif /*USE_FULL_LL_DRIVER*/
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup RCC_LL_Exported_Types RCC Exported Types
-  * @{
-  */
-
-/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
-  * @{
-  */
-
-/**
-  * @brief  RCC Clocks Frequency Structure
-  */
-typedef struct
-{
-  uint32_t SYSCLK_Frequency;
-  uint32_t CPUCLK_Frequency;
-  uint32_t HCLK_Frequency;
-  uint32_t PCLK1_Frequency;
-  uint32_t PCLK2_Frequency;
-  uint32_t PCLK3_Frequency;
-  uint32_t PCLK4_Frequency;
-} LL_RCC_ClocksTypeDef;
-
-/**
-  * @}
-  */
-
-/**
-  * @brief  PLL Clocks Frequency Structure
-  */
-typedef struct
-{
-  uint32_t PLL_P_Frequency;
-  uint32_t PLL_Q_Frequency;
-  uint32_t PLL_R_Frequency;
-} LL_PLL_ClocksTypeDef;
-
-/**
-  * @}
-  */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
-  * @{
-  */
-
-/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
-  * @brief    Defines used to adapt values of different oscillators
-  * @note     These values could be modified in the user environment according to
-  *           HW set-up.
-  * @{
-  */
-#if !defined  (HSE_VALUE)
-#if defined(RCC_VER_X) || defined(RCC_VER_3_0)
-#define HSE_VALUE    25000000U  /*!< Value of the HSE oscillator in Hz */
-#else
-#define HSE_VALUE    24000000U  /*!< Value of the HSE oscillator in Hz */
-#endif /* RCC_VER_X || RCC_VER_3_0 */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSI_VALUE)
-#define HSI_VALUE    64000000U  /*!< Value of the HSI oscillator in Hz */
-#endif /* HSI_VALUE */
-
-#if !defined  (CSI_VALUE)
-#define CSI_VALUE    4000000U   /*!< Value of the CSI oscillator in Hz */
-#endif /* CSI_VALUE */
-
-#if !defined  (LSE_VALUE)
-#define LSE_VALUE    32768U     /*!< Value of the LSE oscillator in Hz */
-#endif /* LSE_VALUE */
-
-#if !defined  (LSI_VALUE)
-#define LSI_VALUE    32000U     /*!< Value of the LSI oscillator in Hz */
-#endif /* LSI_VALUE */
-
-#if !defined  (EXTERNAL_CLOCK_VALUE)
-#define EXTERNAL_CLOCK_VALUE    12288000U /*!< Value of the I2S_CKIN external oscillator in Hz */
-#endif /* EXTERNAL_CLOCK_VALUE */
-
-#if !defined  (HSI48_VALUE)
-#define HSI48_VALUE  48000000U  /*!< Value of the HSI48 oscillator in Hz */
-#endif /* HSI48_VALUE */
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_HSIDIV  HSI oscillator divider
-  * @{
-  */
-#define LL_RCC_HSI_DIV1                   RCC_CR_HSIDIV_1
-#define LL_RCC_HSI_DIV2                   RCC_CR_HSIDIV_2
-#define LL_RCC_HSI_DIV4                   RCC_CR_HSIDIV_4
-#define LL_RCC_HSI_DIV8                   RCC_CR_HSIDIV_8
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_LSEDRIVE  LSE oscillator drive capability
-  * @{
-  */
-#define LL_RCC_LSEDRIVE_LOW                (uint32_t)(0x00000000U)
-#define LL_RCC_LSEDRIVE_MEDIUMLOW          (uint32_t)(RCC_BDCR_LSEDRV_0)
-#define LL_RCC_LSEDRIVE_MEDIUMHIGH         (uint32_t)(RCC_BDCR_LSEDRV_1)
-#define LL_RCC_LSEDRIVE_HIGH               (uint32_t)(RCC_BDCR_LSEDRV)
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_SYS_CLKSOURCE  System clock switch
-  * @{
-  */
-#define LL_RCC_SYS_CLKSOURCE_HSI           RCC_CFGR_SW_HSI
-#define LL_RCC_SYS_CLKSOURCE_CSI           RCC_CFGR_SW_CSI
-#define LL_RCC_SYS_CLKSOURCE_HSE           RCC_CFGR_SW_HSE
-#define LL_RCC_SYS_CLKSOURCE_PLL1          RCC_CFGR_SW_PLL1
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS  System clock switch status
-  * @{
-  */
-#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI    RCC_CFGR_SWS_HSI   /*!< HSI used as system clock */
-#define LL_RCC_SYS_CLKSOURCE_STATUS_CSI    RCC_CFGR_SWS_CSI   /*!< CSI used as system clock */
-#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE    RCC_CFGR_SWS_HSE   /*!< HSE used as system clock */
-#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL1   RCC_CFGR_SWS_PLL1  /*!< PLL1 used as system clock */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_SYSWAKEUP_CLKSOURCE  System wakeup clock source
-  * @{
-  */
-#define LL_RCC_SYSWAKEUP_CLKSOURCE_HSI     (uint32_t)(0x00000000U)
-#define LL_RCC_SYSWAKEUP_CLKSOURCE_CSI     (uint32_t)(RCC_CFGR_STOPWUCK)
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_KERWAKEUP_CLKSOURCE  Kernel wakeup clock source
-  * @{
-  */
-#define LL_RCC_KERWAKEUP_CLKSOURCE_HSI     (uint32_t)(0x00000000U)
-#define LL_RCC_KERWAKEUP_CLKSOURCE_CSI     (uint32_t)(RCC_CFGR_STOPKERWUCK)
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_SYSCLK_DIV  System prescaler
-  * @{
-  */
-#if defined(RCC_D1CFGR_D1CPRE_DIV1)
-#define LL_RCC_SYSCLK_DIV_1                RCC_D1CFGR_D1CPRE_DIV1
-#define LL_RCC_SYSCLK_DIV_2                RCC_D1CFGR_D1CPRE_DIV2
-#define LL_RCC_SYSCLK_DIV_4                RCC_D1CFGR_D1CPRE_DIV4
-#define LL_RCC_SYSCLK_DIV_8                RCC_D1CFGR_D1CPRE_DIV8
-#define LL_RCC_SYSCLK_DIV_16               RCC_D1CFGR_D1CPRE_DIV16
-#define LL_RCC_SYSCLK_DIV_64               RCC_D1CFGR_D1CPRE_DIV64
-#define LL_RCC_SYSCLK_DIV_128              RCC_D1CFGR_D1CPRE_DIV128
-#define LL_RCC_SYSCLK_DIV_256              RCC_D1CFGR_D1CPRE_DIV256
-#define LL_RCC_SYSCLK_DIV_512              RCC_D1CFGR_D1CPRE_DIV512
-#else
-#define LL_RCC_SYSCLK_DIV_1                RCC_CDCFGR1_CDCPRE_DIV1
-#define LL_RCC_SYSCLK_DIV_2                RCC_CDCFGR1_CDCPRE_DIV2
-#define LL_RCC_SYSCLK_DIV_4                RCC_CDCFGR1_CDCPRE_DIV4
-#define LL_RCC_SYSCLK_DIV_8                RCC_CDCFGR1_CDCPRE_DIV8
-#define LL_RCC_SYSCLK_DIV_16               RCC_CDCFGR1_CDCPRE_DIV16
-#define LL_RCC_SYSCLK_DIV_64               RCC_CDCFGR1_CDCPRE_DIV64
-#define LL_RCC_SYSCLK_DIV_128              RCC_CDCFGR1_CDCPRE_DIV128
-#define LL_RCC_SYSCLK_DIV_256              RCC_CDCFGR1_CDCPRE_DIV256
-#define LL_RCC_SYSCLK_DIV_512              RCC_CDCFGR1_CDCPRE_DIV512
-#endif /* RCC_D1CFGR_D1CPRE_DIV1 */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_AHB_DIV  AHB prescaler
-  * @{
-  */
-#if defined(RCC_D1CFGR_HPRE_DIV1)
-#define LL_RCC_AHB_DIV_1                   RCC_D1CFGR_HPRE_DIV1
-#define LL_RCC_AHB_DIV_2                   RCC_D1CFGR_HPRE_DIV2
-#define LL_RCC_AHB_DIV_4                   RCC_D1CFGR_HPRE_DIV4
-#define LL_RCC_AHB_DIV_8                   RCC_D1CFGR_HPRE_DIV8
-#define LL_RCC_AHB_DIV_16                  RCC_D1CFGR_HPRE_DIV16
-#define LL_RCC_AHB_DIV_64                  RCC_D1CFGR_HPRE_DIV64
-#define LL_RCC_AHB_DIV_128                 RCC_D1CFGR_HPRE_DIV128
-#define LL_RCC_AHB_DIV_256                 RCC_D1CFGR_HPRE_DIV256
-#define LL_RCC_AHB_DIV_512                 RCC_D1CFGR_HPRE_DIV512
-#else
-#define LL_RCC_AHB_DIV_1                   RCC_CDCFGR1_HPRE_DIV1
-#define LL_RCC_AHB_DIV_2                   RCC_CDCFGR1_HPRE_DIV2
-#define LL_RCC_AHB_DIV_4                   RCC_CDCFGR1_HPRE_DIV4
-#define LL_RCC_AHB_DIV_8                   RCC_CDCFGR1_HPRE_DIV8
-#define LL_RCC_AHB_DIV_16                  RCC_CDCFGR1_HPRE_DIV16
-#define LL_RCC_AHB_DIV_64                  RCC_CDCFGR1_HPRE_DIV64
-#define LL_RCC_AHB_DIV_128                 RCC_CDCFGR1_HPRE_DIV128
-#define LL_RCC_AHB_DIV_256                 RCC_CDCFGR1_HPRE_DIV256
-#define LL_RCC_AHB_DIV_512                 RCC_CDCFGR1_HPRE_DIV512
-#endif /* RCC_D1CFGR_HPRE_DIV1 */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_APB1_DIV  APB low-speed prescaler (APB1)
-  * @{
-  */
-#if defined(RCC_D2CFGR_D2PPRE1_DIV1)
-#define LL_RCC_APB1_DIV_1                  RCC_D2CFGR_D2PPRE1_DIV1
-#define LL_RCC_APB1_DIV_2                  RCC_D2CFGR_D2PPRE1_DIV2
-#define LL_RCC_APB1_DIV_4                  RCC_D2CFGR_D2PPRE1_DIV4
-#define LL_RCC_APB1_DIV_8                  RCC_D2CFGR_D2PPRE1_DIV8
-#define LL_RCC_APB1_DIV_16                 RCC_D2CFGR_D2PPRE1_DIV16
-#else
-#define LL_RCC_APB1_DIV_1                  RCC_CDCFGR2_CDPPRE1_DIV1
-#define LL_RCC_APB1_DIV_2                  RCC_CDCFGR2_CDPPRE1_DIV2
-#define LL_RCC_APB1_DIV_4                  RCC_CDCFGR2_CDPPRE1_DIV4
-#define LL_RCC_APB1_DIV_8                  RCC_CDCFGR2_CDPPRE1_DIV8
-#define LL_RCC_APB1_DIV_16                 RCC_CDCFGR2_CDPPRE1_DIV16
-#endif /* RCC_D2CFGR_D2PPRE1_DIV1 */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_APB2_DIV  APB low-speed prescaler (APB2)
-  * @{
-  */
-#if defined(RCC_D2CFGR_D2PPRE2_DIV1)
-#define LL_RCC_APB2_DIV_1                  RCC_D2CFGR_D2PPRE2_DIV1
-#define LL_RCC_APB2_DIV_2                  RCC_D2CFGR_D2PPRE2_DIV2
-#define LL_RCC_APB2_DIV_4                  RCC_D2CFGR_D2PPRE2_DIV4
-#define LL_RCC_APB2_DIV_8                  RCC_D2CFGR_D2PPRE2_DIV8
-#define LL_RCC_APB2_DIV_16                 RCC_D2CFGR_D2PPRE2_DIV16
-#else
-#define LL_RCC_APB2_DIV_1                  RCC_CDCFGR2_CDPPRE2_DIV1
-#define LL_RCC_APB2_DIV_2                  RCC_CDCFGR2_CDPPRE2_DIV2
-#define LL_RCC_APB2_DIV_4                  RCC_CDCFGR2_CDPPRE2_DIV4
-#define LL_RCC_APB2_DIV_8                  RCC_CDCFGR2_CDPPRE2_DIV8
-#define LL_RCC_APB2_DIV_16                 RCC_CDCFGR2_CDPPRE2_DIV16
-#endif /* RCC_D2CFGR_D2PPRE2_DIV1 */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_APB3_DIV  APB low-speed prescaler (APB3)
-  * @{
-  */
-#if defined(RCC_D1CFGR_D1PPRE_DIV1)
-#define LL_RCC_APB3_DIV_1                  RCC_D1CFGR_D1PPRE_DIV1
-#define LL_RCC_APB3_DIV_2                  RCC_D1CFGR_D1PPRE_DIV2
-#define LL_RCC_APB3_DIV_4                  RCC_D1CFGR_D1PPRE_DIV4
-#define LL_RCC_APB3_DIV_8                  RCC_D1CFGR_D1PPRE_DIV8
-#define LL_RCC_APB3_DIV_16                 RCC_D1CFGR_D1PPRE_DIV16
-#else
-#define LL_RCC_APB3_DIV_1                  RCC_CDCFGR1_CDPPRE_DIV1
-#define LL_RCC_APB3_DIV_2                  RCC_CDCFGR1_CDPPRE_DIV2
-#define LL_RCC_APB3_DIV_4                  RCC_CDCFGR1_CDPPRE_DIV4
-#define LL_RCC_APB3_DIV_8                  RCC_CDCFGR1_CDPPRE_DIV8
-#define LL_RCC_APB3_DIV_16                 RCC_CDCFGR1_CDPPRE_DIV16
-#endif /* RCC_D1CFGR_D1PPRE_DIV1 */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_APB4_DIV  APB low-speed prescaler (APB4)
-  * @{
-  */
-#if defined(RCC_D3CFGR_D3PPRE_DIV1)
-#define LL_RCC_APB4_DIV_1                  RCC_D3CFGR_D3PPRE_DIV1
-#define LL_RCC_APB4_DIV_2                  RCC_D3CFGR_D3PPRE_DIV2
-#define LL_RCC_APB4_DIV_4                  RCC_D3CFGR_D3PPRE_DIV4
-#define LL_RCC_APB4_DIV_8                  RCC_D3CFGR_D3PPRE_DIV8
-#define LL_RCC_APB4_DIV_16                 RCC_D3CFGR_D3PPRE_DIV16
-#else
-#define LL_RCC_APB4_DIV_1                  RCC_SRDCFGR_SRDPPRE_DIV1
-#define LL_RCC_APB4_DIV_2                  RCC_SRDCFGR_SRDPPRE_DIV2
-#define LL_RCC_APB4_DIV_4                  RCC_SRDCFGR_SRDPPRE_DIV4
-#define LL_RCC_APB4_DIV_8                  RCC_SRDCFGR_SRDPPRE_DIV8
-#define LL_RCC_APB4_DIV_16                 RCC_SRDCFGR_SRDPPRE_DIV16
-#endif /* RCC_D3CFGR_D3PPRE_DIV1 */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_MCOxSOURCE  MCO source selection
-  * @{
-  */
-#define LL_RCC_MCO1SOURCE_HSI              (uint32_t)((RCC_CFGR_MCO1>>16U) | 0x00000000U)
-#define LL_RCC_MCO1SOURCE_LSE              (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_0)
-#define LL_RCC_MCO1SOURCE_HSE              (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_1)
-#define LL_RCC_MCO1SOURCE_PLL1QCLK         (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_1|RCC_CFGR_MCO1_0)
-#define LL_RCC_MCO1SOURCE_HSI48            (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_2)
-#define LL_RCC_MCO2SOURCE_SYSCLK           (uint32_t)((RCC_CFGR_MCO2>>16U) | 0x00000000U)
-#define LL_RCC_MCO2SOURCE_PLL2PCLK         (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_0)
-#define LL_RCC_MCO2SOURCE_HSE              (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_1)
-#define LL_RCC_MCO2SOURCE_PLL1PCLK         (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_1|RCC_CFGR_MCO2_0)
-#define LL_RCC_MCO2SOURCE_CSI              (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_2)
-#define LL_RCC_MCO2SOURCE_LSI              (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_2|RCC_CFGR_MCO2_0)
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_MCOx_DIV  MCO prescaler
-  * @{
-  */
-#define LL_RCC_MCO1_DIV_1                  (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0)
-#define LL_RCC_MCO1_DIV_2                  (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1)
-#define LL_RCC_MCO1_DIV_3                  (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1)
-#define LL_RCC_MCO1_DIV_4                  (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_2)
-#define LL_RCC_MCO1_DIV_5                  (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
-#define LL_RCC_MCO1_DIV_6                  (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
-#define LL_RCC_MCO1_DIV_7                  (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
-#define LL_RCC_MCO1_DIV_8                  (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_3)
-#define LL_RCC_MCO1_DIV_9                  (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_3)
-#define LL_RCC_MCO1_DIV_10                 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3)
-#define LL_RCC_MCO1_DIV_11                 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3)
-#define LL_RCC_MCO1_DIV_12                 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
-#define LL_RCC_MCO1_DIV_13                 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
-#define LL_RCC_MCO1_DIV_14                 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
-#define LL_RCC_MCO1_DIV_15                 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE)
-#define LL_RCC_MCO2_DIV_1                  (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0)
-#define LL_RCC_MCO2_DIV_2                  (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1)
-#define LL_RCC_MCO2_DIV_3                  (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_1)
-#define LL_RCC_MCO2_DIV_4                  (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_2)
-#define LL_RCC_MCO2_DIV_5                  (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_2)
-#define LL_RCC_MCO2_DIV_6                  (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_2)
-#define LL_RCC_MCO2_DIV_7                  (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_2)
-#define LL_RCC_MCO2_DIV_8                  (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_3)
-#define LL_RCC_MCO2_DIV_9                  (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_3)
-#define LL_RCC_MCO2_DIV_10                 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_3)
-#define LL_RCC_MCO2_DIV_11                 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_3)
-#define LL_RCC_MCO2_DIV_12                 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_3)
-#define LL_RCC_MCO2_DIV_13                 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_3)
-#define LL_RCC_MCO2_DIV_14                 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_3)
-#define LL_RCC_MCO2_DIV_15                 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE)
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_RTC_HSEDIV  HSE prescaler for RTC clock
-  * @{
-  */
-#define LL_RCC_RTC_NOCLOCK                  (uint32_t)(0x00000000U)
-#define LL_RCC_RTC_HSE_DIV_2                (uint32_t)(RCC_CFGR_RTCPRE_1)
-#define LL_RCC_RTC_HSE_DIV_3                (uint32_t)(RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
-#define LL_RCC_RTC_HSE_DIV_4                (uint32_t)(RCC_CFGR_RTCPRE_2)
-#define LL_RCC_RTC_HSE_DIV_5                (uint32_t)(RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
-#define LL_RCC_RTC_HSE_DIV_6                (uint32_t)(RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
-#define LL_RCC_RTC_HSE_DIV_7                (uint32_t)(RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
-#define LL_RCC_RTC_HSE_DIV_8                (uint32_t)(RCC_CFGR_RTCPRE_3)
-#define LL_RCC_RTC_HSE_DIV_9                (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0)
-#define LL_RCC_RTC_HSE_DIV_10               (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1)
-#define LL_RCC_RTC_HSE_DIV_11               (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
-#define LL_RCC_RTC_HSE_DIV_12               (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2)
-#define LL_RCC_RTC_HSE_DIV_13               (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
-#define LL_RCC_RTC_HSE_DIV_14               (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
-#define LL_RCC_RTC_HSE_DIV_15               (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
-#define LL_RCC_RTC_HSE_DIV_16               (uint32_t)(RCC_CFGR_RTCPRE_4)
-#define LL_RCC_RTC_HSE_DIV_17               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_0)
-#define LL_RCC_RTC_HSE_DIV_18               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1)
-#define LL_RCC_RTC_HSE_DIV_19               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
-#define LL_RCC_RTC_HSE_DIV_20               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2)
-#define LL_RCC_RTC_HSE_DIV_21               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
-#define LL_RCC_RTC_HSE_DIV_22               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
-#define LL_RCC_RTC_HSE_DIV_23               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
-#define LL_RCC_RTC_HSE_DIV_24               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3)
-#define LL_RCC_RTC_HSE_DIV_25               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0)
-#define LL_RCC_RTC_HSE_DIV_26               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1)
-#define LL_RCC_RTC_HSE_DIV_27               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
-#define LL_RCC_RTC_HSE_DIV_28               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2)
-#define LL_RCC_RTC_HSE_DIV_29               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
-#define LL_RCC_RTC_HSE_DIV_30               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
-#define LL_RCC_RTC_HSE_DIV_31               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
-#define LL_RCC_RTC_HSE_DIV_32               (uint32_t)(RCC_CFGR_RTCPRE_5)
-#define LL_RCC_RTC_HSE_DIV_33               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_0)
-#define LL_RCC_RTC_HSE_DIV_34               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_1)
-#define LL_RCC_RTC_HSE_DIV_35               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
-#define LL_RCC_RTC_HSE_DIV_36               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2)
-#define LL_RCC_RTC_HSE_DIV_37               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
-#define LL_RCC_RTC_HSE_DIV_38               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
-#define LL_RCC_RTC_HSE_DIV_39               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
-#define LL_RCC_RTC_HSE_DIV_40               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3)
-#define LL_RCC_RTC_HSE_DIV_41               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0)
-#define LL_RCC_RTC_HSE_DIV_42               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1)
-#define LL_RCC_RTC_HSE_DIV_43               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
-#define LL_RCC_RTC_HSE_DIV_44               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2)
-#define LL_RCC_RTC_HSE_DIV_45               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
-#define LL_RCC_RTC_HSE_DIV_46               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
-#define LL_RCC_RTC_HSE_DIV_47               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
-#define LL_RCC_RTC_HSE_DIV_48               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4)
-#define LL_RCC_RTC_HSE_DIV_49               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_0)
-#define LL_RCC_RTC_HSE_DIV_50               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1)
-#define LL_RCC_RTC_HSE_DIV_51               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
-#define LL_RCC_RTC_HSE_DIV_52               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2)
-#define LL_RCC_RTC_HSE_DIV_53               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
-#define LL_RCC_RTC_HSE_DIV_54               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
-#define LL_RCC_RTC_HSE_DIV_55               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
-#define LL_RCC_RTC_HSE_DIV_56               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3)
-#define LL_RCC_RTC_HSE_DIV_57               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0)
-#define LL_RCC_RTC_HSE_DIV_58               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1)
-#define LL_RCC_RTC_HSE_DIV_59               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
-#define LL_RCC_RTC_HSE_DIV_60               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2)
-#define LL_RCC_RTC_HSE_DIV_61               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
-#define LL_RCC_RTC_HSE_DIV_62               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
-#define LL_RCC_RTC_HSE_DIV_63               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_USARTx_CLKSOURCE  Peripheral USART clock source selection
-  * @{
-  */
-#if defined(RCC_D2CCIP2R_USART16SEL)
-#define LL_RCC_USART16_CLKSOURCE_PCLK2         LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, 0x00000000U)
-#define LL_RCC_USART16_CLKSOURCE_PLL2Q         LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_0)
-#define LL_RCC_USART16_CLKSOURCE_PLL3Q         LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_1)
-#define LL_RCC_USART16_CLKSOURCE_HSI           LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_1)
-#define LL_RCC_USART16_CLKSOURCE_CSI           LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_2)
-#define LL_RCC_USART16_CLKSOURCE_LSE           LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_2)
-/*  Aliases */
-#define LL_RCC_USART16910_CLKSOURCE_PCLK2      LL_RCC_USART16_CLKSOURCE_PCLK2
-#define LL_RCC_USART16910_CLKSOURCE_PLL2Q      LL_RCC_USART16_CLKSOURCE_PLL2Q
-#define LL_RCC_USART16910_CLKSOURCE_PLL3Q      LL_RCC_USART16_CLKSOURCE_PLL3Q
-#define LL_RCC_USART16910_CLKSOURCE_HSI        LL_RCC_USART16_CLKSOURCE_HSI
-#define LL_RCC_USART16910_CLKSOURCE_CSI        LL_RCC_USART16_CLKSOURCE_CSI
-#define LL_RCC_USART16910_CLKSOURCE_LSE        LL_RCC_USART16_CLKSOURCE_LSE
-
-#elif defined(RCC_D2CCIP2R_USART16910SEL)
-#define LL_RCC_USART16910_CLKSOURCE_PCLK2      LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, 0x00000000U)
-#define LL_RCC_USART16910_CLKSOURCE_PLL2Q      LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, RCC_D2CCIP2R_USART16910SEL_0)
-#define LL_RCC_USART16910_CLKSOURCE_PLL3Q      LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, RCC_D2CCIP2R_USART16910SEL_1)
-#define LL_RCC_USART16910_CLKSOURCE_HSI        LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, RCC_D2CCIP2R_USART16910SEL_0 | RCC_D2CCIP2R_USART16910SEL_1)
-#define LL_RCC_USART16910_CLKSOURCE_CSI        LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, RCC_D2CCIP2R_USART16910SEL_2)
-#define LL_RCC_USART16910_CLKSOURCE_LSE        LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, RCC_D2CCIP2R_USART16910SEL_0 | RCC_D2CCIP2R_USART16910SEL_2)
-/*  Aliases */
-#define LL_RCC_USART16_CLKSOURCE_PCLK2         LL_RCC_USART16910_CLKSOURCE_PCLK2
-#define LL_RCC_USART16_CLKSOURCE_PLL2Q         LL_RCC_USART16910_CLKSOURCE_PLL2Q
-#define LL_RCC_USART16_CLKSOURCE_PLL3Q         LL_RCC_USART16910_CLKSOURCE_PLL3Q
-#define LL_RCC_USART16_CLKSOURCE_HSI           LL_RCC_USART16910_CLKSOURCE_HSI
-#define LL_RCC_USART16_CLKSOURCE_CSI           LL_RCC_USART16910_CLKSOURCE_CSI
-#define LL_RCC_USART16_CLKSOURCE_LSE           LL_RCC_USART16910_CLKSOURCE_LSE
-
-#else
-#define LL_RCC_USART16910_CLKSOURCE_PCLK2      LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, 0x00000000U)
-#define LL_RCC_USART16910_CLKSOURCE_PLL2Q      LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_0)
-#define LL_RCC_USART16910_CLKSOURCE_PLL3Q      LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_1)
-#define LL_RCC_USART16910_CLKSOURCE_HSI        LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_0 | RCC_CDCCIP2R_USART16910SEL_1)
-#define LL_RCC_USART16910_CLKSOURCE_CSI        LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_2)
-#define LL_RCC_USART16910_CLKSOURCE_LSE        LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_0 | RCC_CDCCIP2R_USART16910SEL_2)
-/*  Aliases */
-#define LL_RCC_USART16_CLKSOURCE_PCLK2         LL_RCC_USART16910_CLKSOURCE_PCLK2
-#define LL_RCC_USART16_CLKSOURCE_PLL2Q         LL_RCC_USART16910_CLKSOURCE_PLL2Q
-#define LL_RCC_USART16_CLKSOURCE_PLL3Q         LL_RCC_USART16910_CLKSOURCE_PLL3Q
-#define LL_RCC_USART16_CLKSOURCE_HSI           LL_RCC_USART16910_CLKSOURCE_HSI
-#define LL_RCC_USART16_CLKSOURCE_CSI           LL_RCC_USART16910_CLKSOURCE_CSI
-#define LL_RCC_USART16_CLKSOURCE_LSE           LL_RCC_USART16910_CLKSOURCE_LSE
-#endif  /* RCC_D2CCIP2R_USART16SEL */
-#if defined(RCC_D2CCIP2R_USART28SEL)
-#define LL_RCC_USART234578_CLKSOURCE_PCLK1     LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, 0x00000000U)
-#define LL_RCC_USART234578_CLKSOURCE_PLL2Q     LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_0)
-#define LL_RCC_USART234578_CLKSOURCE_PLL3Q     LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_1)
-#define LL_RCC_USART234578_CLKSOURCE_HSI       LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_1)
-#define LL_RCC_USART234578_CLKSOURCE_CSI       LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_2)
-#define LL_RCC_USART234578_CLKSOURCE_LSE       LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_2)
-#else
-#define LL_RCC_USART234578_CLKSOURCE_PCLK1     LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, 0x00000000U)
-#define LL_RCC_USART234578_CLKSOURCE_PLL2Q     LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_0)
-#define LL_RCC_USART234578_CLKSOURCE_PLL3Q     LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_1)
-#define LL_RCC_USART234578_CLKSOURCE_HSI       LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_0 | RCC_CDCCIP2R_USART234578SEL_1)
-#define LL_RCC_USART234578_CLKSOURCE_CSI       LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_2)
-#define LL_RCC_USART234578_CLKSOURCE_LSE       LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_0 | RCC_CDCCIP2R_USART234578SEL_2)
-#endif /* RCC_D2CCIP2R_USART28SEL */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_LPUARTx_CLKSOURCE  Peripheral LPUART clock source selection
-  * @{
-  */
-#if defined(RCC_D3CCIPR_LPUART1SEL)
-#define LL_RCC_LPUART1_CLKSOURCE_PCLK4         (0x00000000U)
-#define LL_RCC_LPUART1_CLKSOURCE_PLL2Q         (RCC_D3CCIPR_LPUART1SEL_0)
-#define LL_RCC_LPUART1_CLKSOURCE_PLL3Q         (RCC_D3CCIPR_LPUART1SEL_1)
-#define LL_RCC_LPUART1_CLKSOURCE_HSI           (RCC_D3CCIPR_LPUART1SEL_0 | RCC_D3CCIPR_LPUART1SEL_1)
-#define LL_RCC_LPUART1_CLKSOURCE_CSI           (RCC_D3CCIPR_LPUART1SEL_2)
-#define LL_RCC_LPUART1_CLKSOURCE_LSE           (RCC_D3CCIPR_LPUART1SEL_0 | RCC_D3CCIPR_LPUART1SEL_2)
-#else
-#define LL_RCC_LPUART1_CLKSOURCE_PCLK4         (0x00000000U)
-#define LL_RCC_LPUART1_CLKSOURCE_PLL2Q         (RCC_SRDCCIPR_LPUART1SEL_0)
-#define LL_RCC_LPUART1_CLKSOURCE_PLL3Q         (RCC_SRDCCIPR_LPUART1SEL_1)
-#define LL_RCC_LPUART1_CLKSOURCE_HSI           (RCC_SRDCCIPR_LPUART1SEL_0 | RCC_SRDCCIPR_LPUART1SEL_1)
-#define LL_RCC_LPUART1_CLKSOURCE_CSI           (RCC_SRDCCIPR_LPUART1SEL_2)
-#define LL_RCC_LPUART1_CLKSOURCE_LSE           (RCC_SRDCCIPR_LPUART1SEL_0 | RCC_SRDCCIPR_LPUART1SEL_2)
-#endif /* RCC_D3CCIPR_LPUART1SEL */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_I2Cx_CLKSOURCE  Peripheral I2C clock source selection
-  * @{
-  */
-#if defined (RCC_D2CCIP2R_I2C123SEL)
-#define LL_RCC_I2C123_CLKSOURCE_PCLK1          LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, 0x00000000U)
-#define LL_RCC_I2C123_CLKSOURCE_PLL3R          LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, RCC_D2CCIP2R_I2C123SEL_0)
-#define LL_RCC_I2C123_CLKSOURCE_HSI            LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, RCC_D2CCIP2R_I2C123SEL_1)
-#define LL_RCC_I2C123_CLKSOURCE_CSI            LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, RCC_D2CCIP2R_I2C123SEL_0 | RCC_D2CCIP2R_I2C123SEL_1)
-/*  Aliases */
-#define LL_RCC_I2C1235_CLKSOURCE_PCLK1         LL_RCC_I2C123_CLKSOURCE_PCLK1
-#define LL_RCC_I2C1235_CLKSOURCE_PLL3R         LL_RCC_I2C123_CLKSOURCE_PLL3R
-#define LL_RCC_I2C1235_CLKSOURCE_HSI           LL_RCC_I2C123_CLKSOURCE_HSI
-#define LL_RCC_I2C1235_CLKSOURCE_CSI           LL_RCC_I2C123_CLKSOURCE_CSI
-
-#elif defined (RCC_D2CCIP2R_I2C1235SEL)
-#define LL_RCC_I2C1235_CLKSOURCE_PCLK1         LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C1235SEL, RCC_D2CCIP2R_I2C1235SEL_Pos, 0x00000000U)
-#define LL_RCC_I2C1235_CLKSOURCE_PLL3R         LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C1235SEL, RCC_D2CCIP2R_I2C1235SEL_Pos, RCC_D2CCIP2R_I2C1235SEL_0)
-#define LL_RCC_I2C1235_CLKSOURCE_HSI           LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C1235SEL, RCC_D2CCIP2R_I2C1235SEL_Pos, RCC_D2CCIP2R_I2C1235SEL_1)
-#define LL_RCC_I2C1235_CLKSOURCE_CSI           LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C1235SEL, RCC_D2CCIP2R_I2C1235SEL_Pos, RCC_D2CCIP2R_I2C1235SEL_0 | RCC_D2CCIP2R_I2C1235SEL_1)
-/*  Aliases */
-#define LL_RCC_I2C123_CLKSOURCE_PCLK1          LL_RCC_I2C1235_CLKSOURCE_PCLK1
-#define LL_RCC_I2C123_CLKSOURCE_PLL3R          LL_RCC_I2C1235_CLKSOURCE_PLL3R
-#define LL_RCC_I2C123_CLKSOURCE_HSI            LL_RCC_I2C1235_CLKSOURCE_HSI
-#define LL_RCC_I2C123_CLKSOURCE_CSI            LL_RCC_I2C1235_CLKSOURCE_CSI
-
-#else
-#define LL_RCC_I2C123_CLKSOURCE_PCLK1          LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, 0x00000000U)
-#define LL_RCC_I2C123_CLKSOURCE_PLL3R          LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, RCC_CDCCIP2R_I2C123SEL_0)
-#define LL_RCC_I2C123_CLKSOURCE_HSI            LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, RCC_CDCCIP2R_I2C123SEL_1)
-#define LL_RCC_I2C123_CLKSOURCE_CSI            LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, RCC_CDCCIP2R_I2C123SEL_0 | RCC_CDCCIP2R_I2C123SEL_1)
-#endif /* RCC_D2CCIP2R_I2C123SEL */
-#if defined (RCC_D3CCIPR_I2C4SEL)
-#define LL_RCC_I2C4_CLKSOURCE_PCLK4            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_I2C4SEL,    RCC_D3CCIPR_I2C4SEL_Pos,    0x00000000U)
-#define LL_RCC_I2C4_CLKSOURCE_PLL3R            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_I2C4SEL,    RCC_D3CCIPR_I2C4SEL_Pos,    RCC_D3CCIPR_I2C4SEL_0)
-#define LL_RCC_I2C4_CLKSOURCE_HSI              LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_I2C4SEL,    RCC_D3CCIPR_I2C4SEL_Pos,    RCC_D3CCIPR_I2C4SEL_1)
-#define LL_RCC_I2C4_CLKSOURCE_CSI              LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_I2C4SEL,    RCC_D3CCIPR_I2C4SEL_Pos,    RCC_D3CCIPR_I2C4SEL_0 | RCC_D3CCIPR_I2C4SEL_1)
-#else
-#define LL_RCC_I2C4_CLKSOURCE_PCLK4            LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_I2C4SEL,    RCC_SRDCCIPR_I2C4SEL_Pos,    0x00000000U)
-#define LL_RCC_I2C4_CLKSOURCE_PLL3R            LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_I2C4SEL,    RCC_SRDCCIPR_I2C4SEL_Pos,    RCC_SRDCCIPR_I2C4SEL_0)
-#define LL_RCC_I2C4_CLKSOURCE_HSI              LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_I2C4SEL,    RCC_SRDCCIPR_I2C4SEL_Pos,    RCC_SRDCCIPR_I2C4SEL_1)
-#define LL_RCC_I2C4_CLKSOURCE_CSI              LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_I2C4SEL,    RCC_SRDCCIPR_I2C4SEL_Pos,    RCC_SRDCCIPR_I2C4SEL_0 | RCC_SRDCCIPR_I2C4SEL_1)
-#endif /* RCC_D3CCIPR_I2C4SEL */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_LPTIMx_CLKSOURCE  Peripheral LPTIM clock source selection
-  * @{
-  */
-#if defined(RCC_D2CCIP2R_LPTIM1SEL)
-#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1          LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL,  RCC_D2CCIP2R_LPTIM1SEL_Pos,  0x00000000U)
-#define LL_RCC_LPTIM1_CLKSOURCE_PLL2P          LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL,  RCC_D2CCIP2R_LPTIM1SEL_Pos,  RCC_D2CCIP2R_LPTIM1SEL_0)
-#define LL_RCC_LPTIM1_CLKSOURCE_PLL3R          LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL,  RCC_D2CCIP2R_LPTIM1SEL_Pos,  RCC_D2CCIP2R_LPTIM1SEL_1)
-#define LL_RCC_LPTIM1_CLKSOURCE_LSE            LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL,  RCC_D2CCIP2R_LPTIM1SEL_Pos,  RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_1)
-#define LL_RCC_LPTIM1_CLKSOURCE_LSI            LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL,  RCC_D2CCIP2R_LPTIM1SEL_Pos,  RCC_D2CCIP2R_LPTIM1SEL_2)
-#define LL_RCC_LPTIM1_CLKSOURCE_CLKP           LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL,  RCC_D2CCIP2R_LPTIM1SEL_Pos,  RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_2)
-#else
-#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1          LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL,  RCC_CDCCIP2R_LPTIM1SEL_Pos,  0x00000000U)
-#define LL_RCC_LPTIM1_CLKSOURCE_PLL2P          LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL,  RCC_CDCCIP2R_LPTIM1SEL_Pos,  RCC_CDCCIP2R_LPTIM1SEL_0)
-#define LL_RCC_LPTIM1_CLKSOURCE_PLL3R          LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL,  RCC_CDCCIP2R_LPTIM1SEL_Pos,  RCC_CDCCIP2R_LPTIM1SEL_1)
-#define LL_RCC_LPTIM1_CLKSOURCE_LSE            LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL,  RCC_CDCCIP2R_LPTIM1SEL_Pos,  RCC_CDCCIP2R_LPTIM1SEL_0 | RCC_CDCCIP2R_LPTIM1SEL_1)
-#define LL_RCC_LPTIM1_CLKSOURCE_LSI            LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL,  RCC_CDCCIP2R_LPTIM1SEL_Pos,  RCC_CDCCIP2R_LPTIM1SEL_2)
-#define LL_RCC_LPTIM1_CLKSOURCE_CLKP           LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL,  RCC_CDCCIP2R_LPTIM1SEL_Pos,  RCC_CDCCIP2R_LPTIM1SEL_0 | RCC_CDCCIP2R_LPTIM1SEL_2)
-#endif /* RCC_D2CCIP2R_LPTIM1SEL */
-#if defined(RCC_D3CCIPR_LPTIM2SEL)
-#define LL_RCC_LPTIM2_CLKSOURCE_PCLK4          LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM2SEL,   RCC_D3CCIPR_LPTIM2SEL_Pos,   0x00000000U)
-#define LL_RCC_LPTIM2_CLKSOURCE_PLL2P          LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM2SEL,   RCC_D3CCIPR_LPTIM2SEL_Pos,   RCC_D3CCIPR_LPTIM2SEL_0)
-#define LL_RCC_LPTIM2_CLKSOURCE_PLL3R          LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM2SEL,   RCC_D3CCIPR_LPTIM2SEL_Pos,   RCC_D3CCIPR_LPTIM2SEL_1)
-#define LL_RCC_LPTIM2_CLKSOURCE_LSE            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM2SEL,   RCC_D3CCIPR_LPTIM2SEL_Pos,   RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_1)
-#define LL_RCC_LPTIM2_CLKSOURCE_LSI            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM2SEL,   RCC_D3CCIPR_LPTIM2SEL_Pos,   RCC_D3CCIPR_LPTIM2SEL_2)
-#define LL_RCC_LPTIM2_CLKSOURCE_CLKP           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM2SEL,   RCC_D3CCIPR_LPTIM2SEL_Pos,   RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_2)
-#else
-#define LL_RCC_LPTIM2_CLKSOURCE_PCLK4          LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM2SEL,   RCC_SRDCCIPR_LPTIM2SEL_Pos,   0x00000000U)
-#define LL_RCC_LPTIM2_CLKSOURCE_PLL2P          LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM2SEL,   RCC_SRDCCIPR_LPTIM2SEL_Pos,   RCC_SRDCCIPR_LPTIM2SEL_0)
-#define LL_RCC_LPTIM2_CLKSOURCE_PLL3R          LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM2SEL,   RCC_SRDCCIPR_LPTIM2SEL_Pos,   RCC_SRDCCIPR_LPTIM2SEL_1)
-#define LL_RCC_LPTIM2_CLKSOURCE_LSE            LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM2SEL,   RCC_SRDCCIPR_LPTIM2SEL_Pos,   RCC_SRDCCIPR_LPTIM2SEL_0 | RCC_SRDCCIPR_LPTIM2SEL_1)
-#define LL_RCC_LPTIM2_CLKSOURCE_LSI            LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM2SEL,   RCC_SRDCCIPR_LPTIM2SEL_Pos,   RCC_SRDCCIPR_LPTIM2SEL_2)
-#define LL_RCC_LPTIM2_CLKSOURCE_CLKP           LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM2SEL,   RCC_SRDCCIPR_LPTIM2SEL_Pos,   RCC_SRDCCIPR_LPTIM2SEL_0 | RCC_SRDCCIPR_LPTIM2SEL_2)
-#endif /* RCC_D3CCIPR_LPTIM2SEL */
-#if defined(RCC_D3CCIPR_LPTIM345SEL)
-#define LL_RCC_LPTIM345_CLKSOURCE_PCLK4        LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, 0x00000000U)
-#define LL_RCC_LPTIM345_CLKSOURCE_PLL2P        LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_0)
-#define LL_RCC_LPTIM345_CLKSOURCE_PLL3R        LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_1)
-#define LL_RCC_LPTIM345_CLKSOURCE_LSE          LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_1)
-#define LL_RCC_LPTIM345_CLKSOURCE_LSI          LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_2)
-#define LL_RCC_LPTIM345_CLKSOURCE_CLKP         LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_2)
-#else
-#define LL_RCC_LPTIM345_CLKSOURCE_PCLK4        LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, 0x00000000U)
-#define LL_RCC_LPTIM345_CLKSOURCE_PLL2P        LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_0)
-#define LL_RCC_LPTIM345_CLKSOURCE_PLL3R        LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_1)
-#define LL_RCC_LPTIM345_CLKSOURCE_LSE          LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_1)
-#define LL_RCC_LPTIM345_CLKSOURCE_LSI          LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_2)
-#define LL_RCC_LPTIM345_CLKSOURCE_CLKP         LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_2)
-/* aliases*/
-#define LL_RCC_LPTIM3_CLKSOURCE_PCLK4          LL_RCC_LPTIM345_CLKSOURCE_PCLK4
-#define LL_RCC_LPTIM3_CLKSOURCE_PLL2P          LL_RCC_LPTIM345_CLKSOURCE_PLL2P
-#define LL_RCC_LPTIM3_CLKSOURCE_PLL3R          LL_RCC_LPTIM345_CLKSOURCE_PLL3R
-#define LL_RCC_LPTIM3_CLKSOURCE_LSE            LL_RCC_LPTIM345_CLKSOURCE_LSE
-#define LL_RCC_LPTIM3_CLKSOURCE_LSI            LL_RCC_LPTIM345_CLKSOURCE_LSI
-#define LL_RCC_LPTIM3_CLKSOURCE_CLKP           LL_RCC_LPTIM345_CLKSOURCE_CLKP
-#endif /* RCC_D3CCIPR_LPTIM345SEL */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_SAIx_CLKSOURCE  Peripheral SAI clock source selection
-  * @{
-  */
-#if defined(RCC_D2CCIP1R_SAI1SEL)
-#define LL_RCC_SAI1_CLKSOURCE_PLL1Q            LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL,  RCC_D2CCIP1R_SAI1SEL_Pos,  0x00000000U)
-#define LL_RCC_SAI1_CLKSOURCE_PLL2P            LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL,  RCC_D2CCIP1R_SAI1SEL_Pos,  RCC_D2CCIP1R_SAI1SEL_0)
-#define LL_RCC_SAI1_CLKSOURCE_PLL3P            LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL,  RCC_D2CCIP1R_SAI1SEL_Pos,  RCC_D2CCIP1R_SAI1SEL_1)
-#define LL_RCC_SAI1_CLKSOURCE_I2S_CKIN         LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL,  RCC_D2CCIP1R_SAI1SEL_Pos,  RCC_D2CCIP1R_SAI1SEL_0 | RCC_D2CCIP1R_SAI1SEL_1)
-#define LL_RCC_SAI1_CLKSOURCE_CLKP             LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL,  RCC_D2CCIP1R_SAI1SEL_Pos,  RCC_D2CCIP1R_SAI1SEL_2)
-#else
-#define LL_RCC_SAI1_CLKSOURCE_PLL1Q            LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL,  RCC_CDCCIP1R_SAI1SEL_Pos,  0x00000000U)
-#define LL_RCC_SAI1_CLKSOURCE_PLL2P            LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL,  RCC_CDCCIP1R_SAI1SEL_Pos,  RCC_CDCCIP1R_SAI1SEL_0)
-#define LL_RCC_SAI1_CLKSOURCE_PLL3P            LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL,  RCC_CDCCIP1R_SAI1SEL_Pos,  RCC_CDCCIP1R_SAI1SEL_1)
-#define LL_RCC_SAI1_CLKSOURCE_I2S_CKIN         LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL,  RCC_CDCCIP1R_SAI1SEL_Pos,  RCC_CDCCIP1R_SAI1SEL_0 | RCC_CDCCIP1R_SAI1SEL_1)
-#define LL_RCC_SAI1_CLKSOURCE_CLKP             LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL,  RCC_CDCCIP1R_SAI1SEL_Pos,  RCC_CDCCIP1R_SAI1SEL_2)
-#endif
-#if defined(SAI3)
-#define LL_RCC_SAI23_CLKSOURCE_PLL1Q           LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, 0x00000000U)
-#define LL_RCC_SAI23_CLKSOURCE_PLL2P           LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, RCC_D2CCIP1R_SAI23SEL_0)
-#define LL_RCC_SAI23_CLKSOURCE_PLL3P           LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, RCC_D2CCIP1R_SAI23SEL_1)
-#define LL_RCC_SAI23_CLKSOURCE_I2S_CKIN        LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, RCC_D2CCIP1R_SAI23SEL_0 | RCC_D2CCIP1R_SAI23SEL_1)
-#define LL_RCC_SAI23_CLKSOURCE_CLKP            LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, RCC_D2CCIP1R_SAI23SEL_2)
-#endif /* SAI3 */
-#if defined(RCC_CDCCIP1R_SAI2ASEL)
-#define LL_RCC_SAI2A_CLKSOURCE_PLL1Q           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2ASEL,  RCC_CDCCIP1R_SAI2ASEL_Pos,  0x00000000U)
-#define LL_RCC_SAI2A_CLKSOURCE_PLL2P           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2ASEL,  RCC_CDCCIP1R_SAI2ASEL_Pos,  RCC_CDCCIP1R_SAI2ASEL_0)
-#define LL_RCC_SAI2A_CLKSOURCE_PLL3P           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2ASEL,  RCC_CDCCIP1R_SAI2ASEL_Pos,  RCC_CDCCIP1R_SAI2ASEL_1)
-#define LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN        LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2ASEL,  RCC_CDCCIP1R_SAI2ASEL_Pos,  RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_1)
-#define LL_RCC_SAI2A_CLKSOURCE_CLKP            LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2ASEL,  RCC_CDCCIP1R_SAI2ASEL_Pos,  RCC_CDCCIP1R_SAI2ASEL_2)
-#define LL_RCC_SAI2A_CLKSOURCE_SPDIF           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2ASEL,  RCC_CDCCIP1R_SAI2ASEL_Pos,  RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_2)
-#endif /* RCC_CDCCIP1R_SAI2ASEL */
-#if defined(RCC_CDCCIP1R_SAI2BSEL)
-#define LL_RCC_SAI2B_CLKSOURCE_PLL1Q           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2BSEL,  RCC_CDCCIP1R_SAI2BSEL_Pos,  0x00000000U)
-#define LL_RCC_SAI2B_CLKSOURCE_PLL2P           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2BSEL,  RCC_CDCCIP1R_SAI2BSEL_Pos,  RCC_CDCCIP1R_SAI2BSEL_0)
-#define LL_RCC_SAI2B_CLKSOURCE_PLL3P           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2BSEL,  RCC_CDCCIP1R_SAI2BSEL_Pos,  RCC_CDCCIP1R_SAI2BSEL_1)
-#define LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN        LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2BSEL,  RCC_CDCCIP1R_SAI2BSEL_Pos,  RCC_CDCCIP1R_SAI2BSEL_0 | RCC_CDCCIP1R_SAI2BSEL_1)
-#define LL_RCC_SAI2B_CLKSOURCE_CLKP            LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2BSEL,  RCC_CDCCIP1R_SAI2BSEL_Pos,  RCC_CDCCIP1R_SAI2BSEL_2)
-#define LL_RCC_SAI2B_CLKSOURCE_SPDIF           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2BSEL,  RCC_CDCCIP1R_SAI2BSEL_Pos,  RCC_CDCCIP1R_SAI2BSEL_0 | RCC_CDCCIP1R_SAI2BSEL_2)
-#endif /* RCC_CDCCIP1R_SAI2BSEL */
-#if defined(SAI4_Block_A)
-#define LL_RCC_SAI4A_CLKSOURCE_PLL1Q           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4ASEL,  RCC_D3CCIPR_SAI4ASEL_Pos,  0x00000000U)
-#define LL_RCC_SAI4A_CLKSOURCE_PLL2P           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4ASEL,  RCC_D3CCIPR_SAI4ASEL_Pos,  RCC_D3CCIPR_SAI4ASEL_0)
-#define LL_RCC_SAI4A_CLKSOURCE_PLL3P           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4ASEL,  RCC_D3CCIPR_SAI4ASEL_Pos,  RCC_D3CCIPR_SAI4ASEL_1)
-#define LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN        LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4ASEL,  RCC_D3CCIPR_SAI4ASEL_Pos,  RCC_D3CCIPR_SAI4ASEL_0 | RCC_D3CCIPR_SAI4ASEL_1)
-#define LL_RCC_SAI4A_CLKSOURCE_CLKP            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4ASEL,  RCC_D3CCIPR_SAI4ASEL_Pos,  RCC_D3CCIPR_SAI4ASEL_2)
-#if defined(RCC_VER_3_0)
-#define LL_RCC_SAI4A_CLKSOURCE_SPDIF           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4ASEL,  RCC_D3CCIPR_SAI4ASEL_Pos,  RCC_D3CCIPR_SAI4ASEL_2 | RCC_D3CCIPR_SAI4ASEL_0)
-#endif /* RCC_VER_3_0 */
-#endif /* SAI4_Block_A */
-#if defined(SAI4_Block_B)
-#define LL_RCC_SAI4B_CLKSOURCE_PLL1Q           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4BSEL,  RCC_D3CCIPR_SAI4BSEL_Pos,  0x00000000U)
-#define LL_RCC_SAI4B_CLKSOURCE_PLL2P           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4BSEL,  RCC_D3CCIPR_SAI4BSEL_Pos,  RCC_D3CCIPR_SAI4BSEL_0)
-#define LL_RCC_SAI4B_CLKSOURCE_PLL3P           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4BSEL,  RCC_D3CCIPR_SAI4BSEL_Pos,  RCC_D3CCIPR_SAI4BSEL_1)
-#define LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN        LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4BSEL,  RCC_D3CCIPR_SAI4BSEL_Pos,  RCC_D3CCIPR_SAI4BSEL_0 | RCC_D3CCIPR_SAI4BSEL_1)
-#define LL_RCC_SAI4B_CLKSOURCE_CLKP            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4BSEL,  RCC_D3CCIPR_SAI4BSEL_Pos,  RCC_D3CCIPR_SAI4BSEL_2)
-#if defined(RCC_VER_3_0)
-#define LL_RCC_SAI4B_CLKSOURCE_SPDIF           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4BSEL,  RCC_D3CCIPR_SAI4BSEL_Pos,  RCC_D3CCIPR_SAI4BSEL_2 | RCC_D3CCIPR_SAI4BSEL_0)
-#endif /* RCC_VER_3_0 */
-#endif /* SAI4_Block_B */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_SDMMC_CLKSOURCE  Peripheral SDMMC clock source selection
-  * @{
-  */
-#if defined(RCC_D1CCIPR_SDMMCSEL)
-#define LL_RCC_SDMMC_CLKSOURCE_PLL1Q           (0x00000000U)
-#define LL_RCC_SDMMC_CLKSOURCE_PLL2R           (RCC_D1CCIPR_SDMMCSEL)
-#else
-#define LL_RCC_SDMMC_CLKSOURCE_PLL1Q           (0x00000000U)
-#define LL_RCC_SDMMC_CLKSOURCE_PLL2R           (RCC_CDCCIPR_SDMMCSEL)
-#endif /* RCC_D1CCIPR_SDMMCSEL */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_RNG_CLKSOURCE  Peripheral RNG clock source selection
-  * @{
-  */
-#if defined(RCC_D2CCIP2R_RNGSEL)
-#define LL_RCC_RNG_CLKSOURCE_HSI48             (0x00000000U)
-#define LL_RCC_RNG_CLKSOURCE_PLL1Q             (RCC_D2CCIP2R_RNGSEL_0)
-#define LL_RCC_RNG_CLKSOURCE_LSE               (RCC_D2CCIP2R_RNGSEL_1)
-#define LL_RCC_RNG_CLKSOURCE_LSI               (RCC_D2CCIP2R_RNGSEL_1 | RCC_D2CCIP2R_RNGSEL_0)
-#else
-#define LL_RCC_RNG_CLKSOURCE_HSI48             (0x00000000U)
-#define LL_RCC_RNG_CLKSOURCE_PLL1Q             (RCC_CDCCIP2R_RNGSEL_0)
-#define LL_RCC_RNG_CLKSOURCE_LSE               (RCC_CDCCIP2R_RNGSEL_1)
-#define LL_RCC_RNG_CLKSOURCE_LSI               (RCC_CDCCIP2R_RNGSEL_1 | RCC_CDCCIP2R_RNGSEL_0)
-#endif /* RCC_D2CCIP2R_RNGSEL */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_USB_CLKSOURCE  Peripheral USB clock source selection
-  * @{
-  */
-#if defined(RCC_D2CCIP2R_USBSEL)
-#define LL_RCC_USB_CLKSOURCE_DISABLE           (0x00000000U)
-#define LL_RCC_USB_CLKSOURCE_PLL1Q             (RCC_D2CCIP2R_USBSEL_0)
-#define LL_RCC_USB_CLKSOURCE_PLL3Q             (RCC_D2CCIP2R_USBSEL_1)
-#define LL_RCC_USB_CLKSOURCE_HSI48             (RCC_D2CCIP2R_USBSEL_1 | RCC_D2CCIP2R_USBSEL_0)
-#else
-#define LL_RCC_USB_CLKSOURCE_DISABLE           (0x00000000U)
-#define LL_RCC_USB_CLKSOURCE_PLL1Q             (RCC_CDCCIP2R_USBSEL_0)
-#define LL_RCC_USB_CLKSOURCE_PLL3Q             (RCC_CDCCIP2R_USBSEL_1)
-#define LL_RCC_USB_CLKSOURCE_HSI48             (RCC_CDCCIP2R_USBSEL_1 | RCC_CDCCIP2R_USBSEL_0)
-#endif /* RCC_D2CCIP2R_USBSEL */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_CEC_CLKSOURCE  Peripheral CEC clock source selection
-  * @{
-  */
-#if defined(RCC_D2CCIP2R_CECSEL)
-#define LL_RCC_CEC_CLKSOURCE_LSE               (0x00000000U)
-#define LL_RCC_CEC_CLKSOURCE_LSI               (RCC_D2CCIP2R_CECSEL_0)
-#define LL_RCC_CEC_CLKSOURCE_CSI_DIV122        (RCC_D2CCIP2R_CECSEL_1)
-#else
-#define LL_RCC_CEC_CLKSOURCE_LSE               (0x00000000U)
-#define LL_RCC_CEC_CLKSOURCE_LSI               (RCC_CDCCIP2R_CECSEL_0)
-#define LL_RCC_CEC_CLKSOURCE_CSI_DIV122        (RCC_CDCCIP2R_CECSEL_1)
-#endif
-/**
-  * @}
-  */
-
-#if defined(DSI)
-/** @defgroup RCC_LL_EC_DSI_CLKSOURCE  Peripheral DSI clock source selection
-  * @{
-  */
-#define LL_RCC_DSI_CLKSOURCE_PHY               (0x00000000U)
-#define LL_RCC_DSI_CLKSOURCE_PLL2Q             (RCC_D1CCIPR_DSISEL)
-/**
-  * @}
-  */
-#endif /* DSI */
-
-/** @defgroup RCC_LL_EC_DFSDM_CLKSOURCE  Peripheral DFSDM clock source selection
-  * @{
-  */
-#if defined(RCC_D2CCIP1R_DFSDM1SEL)
-#define LL_RCC_DFSDM1_CLKSOURCE_PCLK2          (0x00000000U)
-#define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK         (RCC_D2CCIP1R_DFSDM1SEL)
-#else
-#define LL_RCC_DFSDM1_CLKSOURCE_PCLK2          (0x00000000U)
-#define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK         (RCC_CDCCIP1R_DFSDM1SEL)
-#endif /* RCC_D2CCIP1R_DFSDM1SEL */
-/**
-  * @}
-  */
-
-#if defined(DFSDM2_BASE)
-/** @defgroup RCC_LL_EC_DFSDM2_CLKSOURCE  Peripheral DFSDM2 clock source selection
-  * @{
-  */
-#define LL_RCC_DFSDM2_CLKSOURCE_PCLK4          (0x00000000U)
-#define LL_RCC_DFSDM2_CLKSOURCE_SYSCLK         (RCC_SRDCCIPR_DFSDM2SEL)
-/**
-  * @}
-  */
-#endif /* DFSDM2_BASE */
-
-/** @defgroup RCC_LL_EC_FMC_CLKSOURCE  Peripheral FMC clock source selection
-  * @{
-  */
-#if defined(RCC_D1CCIPR_FMCSEL)
-#define LL_RCC_FMC_CLKSOURCE_HCLK              (0x00000000U)
-#define LL_RCC_FMC_CLKSOURCE_PLL1Q             (RCC_D1CCIPR_FMCSEL_0)
-#define LL_RCC_FMC_CLKSOURCE_PLL2R             (RCC_D1CCIPR_FMCSEL_1)
-#define LL_RCC_FMC_CLKSOURCE_CLKP              (RCC_D1CCIPR_FMCSEL_0 | RCC_D1CCIPR_FMCSEL_1)
-#else
-#define LL_RCC_FMC_CLKSOURCE_HCLK              (0x00000000U)
-#define LL_RCC_FMC_CLKSOURCE_PLL1Q             (RCC_CDCCIPR_FMCSEL_0)
-#define LL_RCC_FMC_CLKSOURCE_PLL2R             (RCC_CDCCIPR_FMCSEL_1)
-#define LL_RCC_FMC_CLKSOURCE_CLKP              (RCC_CDCCIPR_FMCSEL_0 | RCC_CDCCIPR_FMCSEL_1)
-#endif /* RCC_D1CCIPR_FMCSEL */
-/**
-  * @}
-  */
-
-#if defined(QUADSPI)
-/** @defgroup RCC_LL_EC_QSPI_CLKSOURCE  Peripheral QSPI clock source selection
-  * @{
-  */
-#define LL_RCC_QSPI_CLKSOURCE_HCLK             (0x00000000U)
-#define LL_RCC_QSPI_CLKSOURCE_PLL1Q            (RCC_D1CCIPR_QSPISEL_0)
-#define LL_RCC_QSPI_CLKSOURCE_PLL2R            (RCC_D1CCIPR_QSPISEL_1)
-#define LL_RCC_QSPI_CLKSOURCE_CLKP             (RCC_D1CCIPR_QSPISEL_0 | RCC_D1CCIPR_QSPISEL_1)
-/**
-  * @}
-  */
-#endif /* QUADSPI */
-
-
-#if defined(OCTOSPI1) || defined(OCTOSPI2)
-/** @defgroup RCC_LL_EC_OSPI_CLKSOURCE  Peripheral OSPI clock source selection
-  * @{
-  */
-#if defined(RCC_D1CCIPR_OCTOSPISEL)
-#define LL_RCC_OSPI_CLKSOURCE_HCLK             (0x00000000U)
-#define LL_RCC_OSPI_CLKSOURCE_PLL1Q            (RCC_D1CCIPR_OCTOSPISEL_0)
-#define LL_RCC_OSPI_CLKSOURCE_PLL2R            (RCC_D1CCIPR_OCTOSPISEL_1)
-#define LL_RCC_OSPI_CLKSOURCE_CLKP             (RCC_D1CCIPR_OCTOSPISEL_0 | RCC_D1CCIPR_OCTOSPISEL_1)
-#else
-#define LL_RCC_OSPI_CLKSOURCE_HCLK             (0x00000000U)
-#define LL_RCC_OSPI_CLKSOURCE_PLL1Q            (RCC_CDCCIPR_OCTOSPISEL_0)
-#define LL_RCC_OSPI_CLKSOURCE_PLL2R            (RCC_CDCCIPR_OCTOSPISEL_1)
-#define LL_RCC_OSPI_CLKSOURCE_CLKP             (RCC_CDCCIPR_OCTOSPISEL_0 | RCC_CDCCIPR_OCTOSPISEL_1)
-#endif /* RCC_D1CCIPR_OCTOSPISEL */
-/**
-  * @}
-  */
-#endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */
-
-
-/** @defgroup RCC_LL_EC_CLKP_CLKSOURCE  Peripheral CLKP clock source selection
-  * @{
-  */
-#if defined(RCC_D1CCIPR_CKPERSEL)
-#define LL_RCC_CLKP_CLKSOURCE_HSI              (0x00000000U)
-#define LL_RCC_CLKP_CLKSOURCE_CSI              (RCC_D1CCIPR_CKPERSEL_0)
-#define LL_RCC_CLKP_CLKSOURCE_HSE              (RCC_D1CCIPR_CKPERSEL_1)
-#else
-#define LL_RCC_CLKP_CLKSOURCE_HSI              (0x00000000U)
-#define LL_RCC_CLKP_CLKSOURCE_CSI              (RCC_CDCCIPR_CKPERSEL_0)
-#define LL_RCC_CLKP_CLKSOURCE_HSE              (RCC_CDCCIPR_CKPERSEL_1)
-#endif /* RCC_D1CCIPR_CKPERSEL */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_SPIx_CLKSOURCE  Peripheral SPI clock source selection
-  * @{
-  */
-#if defined(RCC_D2CCIP1R_SPI123SEL)
-#define LL_RCC_SPI123_CLKSOURCE_PLL1Q          LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, 0x00000000U)
-#define LL_RCC_SPI123_CLKSOURCE_PLL2P          LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, RCC_D2CCIP1R_SPI123SEL_0)
-#define LL_RCC_SPI123_CLKSOURCE_PLL3P          LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, RCC_D2CCIP1R_SPI123SEL_1)
-#define LL_RCC_SPI123_CLKSOURCE_I2S_CKIN       LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, RCC_D2CCIP1R_SPI123SEL_0 | RCC_D2CCIP1R_SPI123SEL_1)
-#define LL_RCC_SPI123_CLKSOURCE_CLKP           LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, RCC_D2CCIP1R_SPI123SEL_2)
-#else
-#define LL_RCC_SPI123_CLKSOURCE_PLL1Q          LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, 0x00000000U)
-#define LL_RCC_SPI123_CLKSOURCE_PLL2P          LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, RCC_CDCCIP1R_SPI123SEL_0)
-#define LL_RCC_SPI123_CLKSOURCE_PLL3P          LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, RCC_CDCCIP1R_SPI123SEL_1)
-#define LL_RCC_SPI123_CLKSOURCE_I2S_CKIN       LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, RCC_CDCCIP1R_SPI123SEL_0 | RCC_CDCCIP1R_SPI123SEL_1)
-#define LL_RCC_SPI123_CLKSOURCE_CLKP           LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, RCC_CDCCIP1R_SPI123SEL_2)
-#endif /* RCC_D2CCIP1R_SPI123SEL */
-#if defined(RCC_D2CCIP1R_SPI45SEL)
-#define LL_RCC_SPI45_CLKSOURCE_PCLK2           LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL,  RCC_D2CCIP1R_SPI45SEL_Pos,  0x00000000U)
-#define LL_RCC_SPI45_CLKSOURCE_PLL2Q           LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL,  RCC_D2CCIP1R_SPI45SEL_Pos,  RCC_D2CCIP1R_SPI45SEL_0)
-#define LL_RCC_SPI45_CLKSOURCE_PLL3Q           LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL,  RCC_D2CCIP1R_SPI45SEL_Pos,  RCC_D2CCIP1R_SPI45SEL_1)
-#define LL_RCC_SPI45_CLKSOURCE_HSI             LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL,  RCC_D2CCIP1R_SPI45SEL_Pos,  RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_1)
-#define LL_RCC_SPI45_CLKSOURCE_CSI             LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL,  RCC_D2CCIP1R_SPI45SEL_Pos,  RCC_D2CCIP1R_SPI45SEL_2)
-#define LL_RCC_SPI45_CLKSOURCE_HSE             LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL,  RCC_D2CCIP1R_SPI45SEL_Pos,  RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_2)
-#else
-#define LL_RCC_SPI45_CLKSOURCE_PCLK2           LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL,  RCC_CDCCIP1R_SPI45SEL_Pos,  0x00000000U)
-#define LL_RCC_SPI45_CLKSOURCE_PLL2Q           LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL,  RCC_CDCCIP1R_SPI45SEL_Pos,  RCC_CDCCIP1R_SPI45SEL_0)
-#define LL_RCC_SPI45_CLKSOURCE_PLL3Q           LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL,  RCC_CDCCIP1R_SPI45SEL_Pos,  RCC_CDCCIP1R_SPI45SEL_1)
-#define LL_RCC_SPI45_CLKSOURCE_HSI             LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL,  RCC_CDCCIP1R_SPI45SEL_Pos,  RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_1)
-#define LL_RCC_SPI45_CLKSOURCE_CSI             LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL,  RCC_CDCCIP1R_SPI45SEL_Pos,  RCC_CDCCIP1R_SPI45SEL_2)
-#define LL_RCC_SPI45_CLKSOURCE_HSE             LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL,  RCC_CDCCIP1R_SPI45SEL_Pos,  RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_2)
-#endif /* (RCC_D2CCIP1R_SPI45SEL */
-#if defined(RCC_D3CCIPR_SPI6SEL)
-#define LL_RCC_SPI6_CLKSOURCE_PCLK4            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SPI6SEL,    RCC_D3CCIPR_SPI6SEL_Pos,    0x00000000U)
-#define LL_RCC_SPI6_CLKSOURCE_PLL2Q            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SPI6SEL,    RCC_D3CCIPR_SPI6SEL_Pos,    RCC_D3CCIPR_SPI6SEL_0)
-#define LL_RCC_SPI6_CLKSOURCE_PLL3Q            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SPI6SEL,    RCC_D3CCIPR_SPI6SEL_Pos,    RCC_D3CCIPR_SPI6SEL_1)
-#define LL_RCC_SPI6_CLKSOURCE_HSI              LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SPI6SEL,    RCC_D3CCIPR_SPI6SEL_Pos,    RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_1)
-#define LL_RCC_SPI6_CLKSOURCE_CSI              LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SPI6SEL,    RCC_D3CCIPR_SPI6SEL_Pos,    RCC_D3CCIPR_SPI6SEL_2)
-#define LL_RCC_SPI6_CLKSOURCE_HSE              LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SPI6SEL,    RCC_D3CCIPR_SPI6SEL_Pos,    RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_2)
-#else
-#define LL_RCC_SPI6_CLKSOURCE_PCLK4            LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_SPI6SEL,    RCC_SRDCCIPR_SPI6SEL_Pos,    0x00000000U)
-#define LL_RCC_SPI6_CLKSOURCE_PLL2Q            LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_SPI6SEL,    RCC_SRDCCIPR_SPI6SEL_Pos,    RCC_SRDCCIPR_SPI6SEL_0)
-#define LL_RCC_SPI6_CLKSOURCE_PLL3Q            LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_SPI6SEL,    RCC_SRDCCIPR_SPI6SEL_Pos,    RCC_SRDCCIPR_SPI6SEL_1)
-#define LL_RCC_SPI6_CLKSOURCE_HSI              LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_SPI6SEL,    RCC_SRDCCIPR_SPI6SEL_Pos,    RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_1)
-#define LL_RCC_SPI6_CLKSOURCE_CSI              LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_SPI6SEL,    RCC_SRDCCIPR_SPI6SEL_Pos,    RCC_SRDCCIPR_SPI6SEL_2)
-#define LL_RCC_SPI6_CLKSOURCE_HSE              LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_SPI6SEL,    RCC_SRDCCIPR_SPI6SEL_Pos,    RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_2)
-#define LL_RCC_SPI6_CLKSOURCE_I2S_CKIN         LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_SPI6SEL,    RCC_SRDCCIPR_SPI6SEL_Pos,    RCC_SRDCCIPR_SPI6SEL_1 | RCC_SRDCCIPR_SPI6SEL_2)
-#endif /* RCC_D3CCIPR_SPI6SEL */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_SPDIF_CLKSOURCE  Peripheral SPDIF clock source selection
-  * @{
-  */
-#if defined(RCC_D2CCIP1R_SPDIFSEL)
-#define LL_RCC_SPDIF_CLKSOURCE_PLL1Q           (0x00000000U)
-#define LL_RCC_SPDIF_CLKSOURCE_PLL2R           (RCC_D2CCIP1R_SPDIFSEL_0)
-#define LL_RCC_SPDIF_CLKSOURCE_PLL3R           (RCC_D2CCIP1R_SPDIFSEL_1)
-#define LL_RCC_SPDIF_CLKSOURCE_HSI             (RCC_D2CCIP1R_SPDIFSEL_0 | RCC_D2CCIP1R_SPDIFSEL_1)
-#else
-#define LL_RCC_SPDIF_CLKSOURCE_PLL1Q           (0x00000000U)
-#define LL_RCC_SPDIF_CLKSOURCE_PLL2R           (RCC_CDCCIP1R_SPDIFSEL_0)
-#define LL_RCC_SPDIF_CLKSOURCE_PLL3R           (RCC_CDCCIP1R_SPDIFSEL_1)
-#define LL_RCC_SPDIF_CLKSOURCE_HSI             (RCC_CDCCIP1R_SPDIFSEL_0 | RCC_CDCCIP1R_SPDIFSEL_1)
-#endif /* RCC_D2CCIP1R_SPDIFSEL */
-/**
-  * @}
-  */
-
-#if defined(FDCAN1) || defined(FDCAN2)
-/** @defgroup RCC_LL_EC_FDCAN_CLKSOURCE  Peripheral FDCAN clock source selection
-  * @{
-  */
-#if defined(RCC_D2CCIP1R_FDCANSEL)
-#define LL_RCC_FDCAN_CLKSOURCE_HSE             (0x00000000U)
-#define LL_RCC_FDCAN_CLKSOURCE_PLL1Q           (RCC_D2CCIP1R_FDCANSEL_0)
-#define LL_RCC_FDCAN_CLKSOURCE_PLL2Q           (RCC_D2CCIP1R_FDCANSEL_1)
-#else
-#define LL_RCC_FDCAN_CLKSOURCE_HSE             (0x00000000U)
-#define LL_RCC_FDCAN_CLKSOURCE_PLL1Q           (RCC_CDCCIP1R_FDCANSEL_0)
-#define LL_RCC_FDCAN_CLKSOURCE_PLL2Q           (RCC_CDCCIP1R_FDCANSEL_1)
-#endif /* RCC_D2CCIP1R_FDCANSEL */
-/**
-  * @}
-  */
-#endif /*FDCAN1 || FDCAN2*/
-
-/** @defgroup RCC_LL_EC_SWP_CLKSOURCE  Peripheral SWP clock source selection
-  * @{
-  */
-#if defined(RCC_D2CCIP1R_SWPSEL)
-#define LL_RCC_SWP_CLKSOURCE_PCLK1             (0x00000000U)
-#define LL_RCC_SWP_CLKSOURCE_HSI               (RCC_D2CCIP1R_SWPSEL)
-#else
-#define LL_RCC_SWP_CLKSOURCE_PCLK1             (0x00000000U)
-#define LL_RCC_SWP_CLKSOURCE_HSI               (RCC_CDCCIP1R_SWPSEL)
-#endif /* RCC_D2CCIP1R_SWPSEL */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_ADC_CLKSOURCE  Peripheral ADC clock source selection
-  * @{
-  */
-#if defined(RCC_D3CCIPR_ADCSEL)
-#define LL_RCC_ADC_CLKSOURCE_PLL2P             (0x00000000U)
-#define LL_RCC_ADC_CLKSOURCE_PLL3R             (RCC_D3CCIPR_ADCSEL_0)
-#define LL_RCC_ADC_CLKSOURCE_CLKP              (RCC_D3CCIPR_ADCSEL_1)
-#else
-#define LL_RCC_ADC_CLKSOURCE_PLL2P             (0x00000000U)
-#define LL_RCC_ADC_CLKSOURCE_PLL3R             (RCC_SRDCCIPR_ADCSEL_0)
-#define LL_RCC_ADC_CLKSOURCE_CLKP              (RCC_SRDCCIPR_ADCSEL_1)
-#endif /* RCC_D3CCIPR_ADCSEL */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_USARTx  Peripheral USART get clock source
-  * @{
-  */
-#if defined (RCC_D2CCIP2R_USART16SEL)
-#define LL_RCC_USART16_CLKSOURCE         LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, 0x00000000U)
-#elif defined (RCC_D2CCIP2R_USART16910SEL)
-#define LL_RCC_USART16_CLKSOURCE         LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, 0x00000000U)
-/* alias*/
-#define LL_RCC_USART16910_CLKSOURCE      LL_RCC_USART16_CLKSOURCE
-#else
-#define LL_RCC_USART16_CLKSOURCE         LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, 0x00000000U)
-/* alias*/
-#define LL_RCC_USART16910_CLKSOURCE      LL_RCC_USART16_CLKSOURCE
-#endif /* RCC_D2CCIP2R_USART16SEL */
-#if defined (RCC_D2CCIP2R_USART28SEL)
-#define LL_RCC_USART234578_CLKSOURCE     LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, 0x00000000U)
-#else
-#define LL_RCC_USART234578_CLKSOURCE     LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, 0x00000000U)
-#endif /* RCC_D2CCIP2R_USART28SEL */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_LPUARTx  Peripheral LPUART get clock source
-  * @{
-  */
-#if defined(RCC_D3CCIPR_LPUART1SEL)
-#define LL_RCC_LPUART1_CLKSOURCE         RCC_D3CCIPR_LPUART1SEL
-#else
-#define LL_RCC_LPUART1_CLKSOURCE         RCC_SRDCCIPR_LPUART1SEL
-#endif /* RCC_D3CCIPR_LPUART1SEL */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_I2Cx  Peripheral I2C get clock source
-  * @{
-  */
-#if defined(RCC_D2CCIP2R_I2C123SEL)
-#define LL_RCC_I2C123_CLKSOURCE          LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, 0x00000000U)
-/* alias */
-#define LL_RCC_I2C1235_CLKSOURCE         LL_RCC_I2C123_CLKSOURCE
-#elif defined(RCC_D2CCIP2R_I2C1235SEL)
-#define LL_RCC_I2C1235_CLKSOURCE         LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C1235SEL, RCC_D2CCIP2R_I2C1235SEL_Pos, 0x00000000U)
-/* alias */
-#define LL_RCC_I2C123_CLKSOURCE          LL_RCC_I2C1235_CLKSOURCE
-#else
-#define LL_RCC_I2C123_CLKSOURCE          LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, 0x00000000U)
-/* alias */
-#define LL_RCC_I2C1235_CLKSOURCE         LL_RCC_I2C123_CLKSOURCE
-#endif /* RCC_D2CCIP2R_I2C123SEL */
-#if defined(RCC_D3CCIPR_I2C4SEL)
-#define LL_RCC_I2C4_CLKSOURCE            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_I2C4SEL,    RCC_D3CCIPR_I2C4SEL_Pos,    0x00000000U)
-#else
-#define LL_RCC_I2C4_CLKSOURCE            LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_I2C4SEL,   RCC_SRDCCIPR_I2C4SEL_Pos,   0x00000000U)
-#endif /* RCC_D3CCIPR_I2C4SEL */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_LPTIMx  Peripheral LPTIM get clock source
-  * @{
-  */
-#if defined(RCC_D2CCIP2R_LPTIM1SEL)
-#define LL_RCC_LPTIM1_CLKSOURCE          LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL,  RCC_D2CCIP2R_LPTIM1SEL_Pos,      0x00000000U)
-#else
-#define LL_RCC_LPTIM1_CLKSOURCE          LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL,  RCC_CDCCIP2R_LPTIM1SEL_Pos,      0x00000000U)
-#endif /* RCC_D2CCIP2R_LPTIM1SEL) */
-#if defined(RCC_D3CCIPR_LPTIM2SEL)
-#define LL_RCC_LPTIM2_CLKSOURCE          LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM2SEL,   RCC_D3CCIPR_LPTIM2SEL_Pos,       0x00000000U)
-#else
-#define LL_RCC_LPTIM2_CLKSOURCE          LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL,  RCC_SRDCCIPR_LPTIM2SEL_Pos,      0x00000000U)
-#endif /* RCC_D3CCIPR_LPTIM2SEL */
-#if defined(RCC_D3CCIPR_LPTIM345SEL)
-#define LL_RCC_LPTIM345_CLKSOURCE        LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos,     0x00000000U)
-#else
-#define LL_RCC_LPTIM345_CLKSOURCE        LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos,      0x00000000U)
-#define LL_RCC_LPTIM3_CLKSOURCE          LL_RCC_LPTIM345_CLKSOURCE  /* alias */
-#endif /* RCC_D3CCIPR_LPTIM345SEL */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_SAIx  Peripheral SAI get clock source
-  * @{
-  */
-#if defined(RCC_D2CCIP1R_SAI1SEL)
-#define LL_RCC_SAI1_CLKSOURCE            LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL,  RCC_D2CCIP1R_SAI1SEL_Pos,  0x00000000U)
-#else
-#define LL_RCC_SAI1_CLKSOURCE            LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL,  RCC_CDCCIP1R_SAI1SEL_Pos,  0x00000000U)
-#endif /* RCC_D2CCIP1R_SAI1SEL */
-#if defined(RCC_D2CCIP1R_SAI23SEL)
-#define LL_RCC_SAI23_CLKSOURCE           LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, 0x00000000U)
-#endif /* RCC_D2CCIP1R_SAI23SEL */
-#if defined(RCC_CDCCIP1R_SAI2ASEL)
-#define LL_RCC_SAI2A_CLKSOURCE           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2ASEL,  RCC_CDCCIP1R_SAI2ASEL_Pos,  0x00000000U)
-#endif /* RCC_CDCCIP1R_SAI2ASEL */
-#if defined(RCC_CDCCIP1R_SAI2BSEL)
-#define LL_RCC_SAI2B_CLKSOURCE           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2BSEL,  RCC_CDCCIP1R_SAI2BSEL_Pos,  0x00000000U)
-#endif /*  RCC_CDCCIP1R_SAI2BSEL */
-#if defined(RCC_D3CCIPR_SAI4ASEL)
-#define LL_RCC_SAI4A_CLKSOURCE           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4ASEL,  RCC_D3CCIPR_SAI4ASEL_Pos,  0x00000000U)
-#endif /* RCC_D3CCIPR_SAI4ASEL */
-#if defined(RCC_D3CCIPR_SAI4BSEL)
-#define LL_RCC_SAI4B_CLKSOURCE           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4BSEL,  RCC_D3CCIPR_SAI4BSEL_Pos,  0x00000000U)
-#endif /*  RCC_D3CCIPR_SAI4BSEL */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_SDMMC  Peripheral SDMMC get clock source
-  * @{
-  */
-#if defined(RCC_D1CCIPR_SDMMCSEL)
-#define LL_RCC_SDMMC_CLKSOURCE           RCC_D1CCIPR_SDMMCSEL
-#else
-#define LL_RCC_SDMMC_CLKSOURCE           RCC_CDCCIPR_SDMMCSEL
-#endif /* RCC_D1CCIPR_SDMMCSEL */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source
-  * @{
-  */
-#if (RCC_D2CCIP2R_RNGSEL)
-#define LL_RCC_RNG_CLKSOURCE             RCC_D2CCIP2R_RNGSEL
-#else
-#define LL_RCC_RNG_CLKSOURCE             RCC_CDCCIP2R_RNGSEL
-#endif /* RCC_D2CCIP2R_RNGSEL */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_USB  Peripheral USB get clock source
-  * @{
-  */
-#if (RCC_D2CCIP2R_USBSEL)
-#define LL_RCC_USB_CLKSOURCE             RCC_D2CCIP2R_USBSEL
-#else
-#define LL_RCC_USB_CLKSOURCE             RCC_CDCCIP2R_USBSEL
-#endif  /* RCC_D2CCIP2R_USBSEL */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_CEC  Peripheral CEC get clock source
-  * @{
-  */
-#if (RCC_D2CCIP2R_CECSEL)
-#define LL_RCC_CEC_CLKSOURCE             RCC_D2CCIP2R_CECSEL
-#else
-#define LL_RCC_CEC_CLKSOURCE             RCC_CDCCIP2R_CECSEL
-#endif /* RCC_D2CCIP2R_CECSEL */
-/**
-  * @}
-  */
-
-#if defined(DSI)
-/** @defgroup RCC_LL_EC_DSI  Peripheral DSI get clock source
-  * @{
-  */
-#define LL_RCC_DSI_CLKSOURCE             RCC_D1CCIPR_DSISEL
-/**
-  * @}
-  */
-#endif /* DSI */
-
-/** @defgroup RCC_LL_EC_DFSDM  Peripheral DFSDM get clock source
-  * @{
-  */
-#if defined(RCC_D2CCIP1R_DFSDM1SEL)
-#define LL_RCC_DFSDM1_CLKSOURCE          RCC_D2CCIP1R_DFSDM1SEL
-#else
-#define LL_RCC_DFSDM1_CLKSOURCE          RCC_CDCCIP1R_DFSDM1SEL
-#endif /* RCC_D2CCIP1R_DFSDM1SEL */
-/**
-  * @}
-  */
-
-#if defined(DFSDM2_BASE)
-/** @defgroup RCC_LL_EC_DFSDM2  Peripheral DFSDM2 get clock source
-  * @{
-  */
-#define LL_RCC_DFSDM2_CLKSOURCE          RCC_SRDCCIPR_DFSDM2SEL
-/**
-  * @}
-  */
-#endif /* DFSDM2_BASE */
-
-
-
-/** @defgroup RCC_LL_EC_FMC  Peripheral FMC get clock source
-  * @{
-  */
-#if defined(RCC_D1CCIPR_FMCSEL)
-#define LL_RCC_FMC_CLKSOURCE             RCC_D1CCIPR_FMCSEL
-#else
-#define LL_RCC_FMC_CLKSOURCE             RCC_CDCCIPR_FMCSEL
-#endif
-/**
-  * @}
-  */
-
-#if defined(QUADSPI)
-/** @defgroup RCC_LL_EC_QSPI  Peripheral QSPI get clock source
-  * @{
-  */
-#define LL_RCC_QSPI_CLKSOURCE            RCC_D1CCIPR_QSPISEL
-/**
-  * @}
-  */
-#endif /* QUADSPI */
-
-#if defined(OCTOSPI1) || defined(OCTOSPI2)
-/** @defgroup RCC_LL_EC_OSPI Peripheral OSPI get clock source
-  * @{
-  */
-#if defined(RCC_CDCCIPR_OCTOSPISEL)
-#define LL_RCC_OSPI_CLKSOURCE            RCC_CDCCIPR_OCTOSPISEL
-#else
-#define LL_RCC_OSPI_CLKSOURCE            RCC_D1CCIPR_OCTOSPISEL
-#endif /* RCC_CDCCIPR_OCTOSPISEL */
-/**
-  * @}
-  */
-#endif /* OCTOSPI1 || OCTOSPI2 */
-
-/** @defgroup RCC_LL_EC_CLKP Peripheral CLKP get clock source
-  * @{
-  */
-#if defined(RCC_D1CCIPR_CKPERSEL)
-#define LL_RCC_CLKP_CLKSOURCE            RCC_D1CCIPR_CKPERSEL
-#else
-#define LL_RCC_CLKP_CLKSOURCE            RCC_CDCCIPR_CKPERSEL
-#endif /* RCC_D1CCIPR_CKPERSEL */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_SPIx  Peripheral SPI get clock source
-  * @{
-  */
-#if defined(RCC_D2CCIP1R_SPI123SEL)
-#define LL_RCC_SPI123_CLKSOURCE          LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, 0x00000000U)
-#else
-#define LL_RCC_SPI123_CLKSOURCE          LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, 0x00000000U)
-#endif /* RCC_D2CCIP1R_SPI123SEL */
-#if defined(RCC_D2CCIP1R_SPI45SEL)
-#define LL_RCC_SPI45_CLKSOURCE           LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL,  RCC_D2CCIP1R_SPI45SEL_Pos,  0x00000000U)
-#else
-#define LL_RCC_SPI45_CLKSOURCE           LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL,  RCC_CDCCIP1R_SPI45SEL_Pos,  0x00000000U)
-#endif /* RCC_D2CCIP1R_SPI45SEL */
-#if defined(RCC_D3CCIPR_SPI6SEL)
-#define LL_RCC_SPI6_CLKSOURCE            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SPI6SEL,    RCC_D3CCIPR_SPI6SEL_Pos,    0x00000000U)
-#else
-#define LL_RCC_SPI6_CLKSOURCE            LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_SPI6SEL,   RCC_SRDCCIPR_SPI6SEL_Pos,  0x00000000U)
-#endif /* RCC_D3CCIPR_SPI6SEL */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_SPDIF  Peripheral SPDIF get clock source
-  * @{
-  */
-#if defined(RCC_D2CCIP1R_SPDIFSEL)
-#define LL_RCC_SPDIF_CLKSOURCE           RCC_D2CCIP1R_SPDIFSEL
-#else
-#define LL_RCC_SPDIF_CLKSOURCE           RCC_CDCCIP1R_SPDIFSEL
-#endif /* RCC_D2CCIP1R_SPDIFSEL */
-/**
-  * @}
-  */
-
-#if defined(FDCAN1) || defined(FDCAN2)
-/** @defgroup RCC_LL_EC_FDCAN  Peripheral FDCAN get clock source
-  * @{
-  */
-#if defined(RCC_D2CCIP1R_FDCANSEL)
-#define LL_RCC_FDCAN_CLKSOURCE           RCC_D2CCIP1R_FDCANSEL
-#else
-#define LL_RCC_FDCAN_CLKSOURCE           RCC_CDCCIP1R_FDCANSEL
-#endif
-/**
-  * @}
-  */
-#endif /*FDCAN1 || FDCAN2*/
-
-/** @defgroup RCC_LL_EC_SWP  Peripheral SWP get clock source
-  * @{
-  */
-#if defined(RCC_D2CCIP1R_SWPSEL)
-#define LL_RCC_SWP_CLKSOURCE             RCC_D2CCIP1R_SWPSEL
-#else
-#define LL_RCC_SWP_CLKSOURCE             RCC_CDCCIP1R_SWPSEL
-#endif /* RCC_D2CCIP1R_SWPSEL */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_ADC  Peripheral ADC get clock source
-  * @{
-  */
-#if defined(RCC_D3CCIPR_ADCSEL)
-#define LL_RCC_ADC_CLKSOURCE             RCC_D3CCIPR_ADCSEL
-#else
-#define LL_RCC_ADC_CLKSOURCE             RCC_SRDCCIPR_ADCSEL
-#endif /* RCC_D3CCIPR_ADCSEL */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_RTC_CLKSOURCE  RTC clock source selection
-  * @{
-  */
-#define LL_RCC_RTC_CLKSOURCE_NONE          (uint32_t)(0x00000000U)
-#define LL_RCC_RTC_CLKSOURCE_LSE           (uint32_t)(RCC_BDCR_RTCSEL_0)
-#define LL_RCC_RTC_CLKSOURCE_LSI           (uint32_t)(RCC_BDCR_RTCSEL_1)
-#define LL_RCC_RTC_CLKSOURCE_HSE           (uint32_t)(RCC_BDCR_RTCSEL_0 | RCC_BDCR_RTCSEL_1)
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_TIM_CLKPRESCALER  Timers clocks prescalers selection
-  * @{
-  */
-#define LL_RCC_TIM_PRESCALER_TWICE          (uint32_t)(0x00000000U)
-#define LL_RCC_TIM_PRESCALER_FOUR_TIMES     (uint32_t)(RCC_CFGR_TIMPRE)
-/**
-  * @}
-  */
-
-#if defined(HRTIM1)
-/** @defgroup RCC_LL_EC_HRTIM_CLKSOURCE  High Resolution Timers clock selection
-  * @{
-  */
-#define LL_RCC_HRTIM_CLKSOURCE_TIM          (uint32_t)(0x00000000U)           /* HRTIM Clock source is same as other timers */
-#define LL_RCC_HRTIM_CLKSOURCE_CPU          (uint32_t)(RCC_CFGR_HRTIMSEL)     /* HRTIM Clock source is the CPU clock */
-/**
-  * @}
-  */
-#endif /* HRTIM1 */
-
-/** @defgroup RCC_LL_EC_PLLSOURCE   All PLLs entry clock source
-  * @{
-  */
-#define LL_RCC_PLLSOURCE_HSI               RCC_PLLCKSELR_PLLSRC_HSI
-#define LL_RCC_PLLSOURCE_CSI               RCC_PLLCKSELR_PLLSRC_CSI
-#define LL_RCC_PLLSOURCE_HSE               RCC_PLLCKSELR_PLLSRC_HSE
-#define LL_RCC_PLLSOURCE_NONE              RCC_PLLCKSELR_PLLSRC_NONE
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_PLLINPUTRANGE   All PLLs input range
-  * @{
-  */
-#define LL_RCC_PLLINPUTRANGE_1_2           (uint32_t)(0x00000000U)
-#define LL_RCC_PLLINPUTRANGE_2_4           (uint32_t)(0x00000001)
-#define LL_RCC_PLLINPUTRANGE_4_8           (uint32_t)(0x00000002)
-#define LL_RCC_PLLINPUTRANGE_8_16          (uint32_t)(0x00000003)
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_PLLVCORANGE   All PLLs VCO range
-  * @{
-  */
-#define LL_RCC_PLLVCORANGE_WIDE            (uint32_t)(0x00000000U)      /* VCO output range: 192 to 836 MHz   OR  128 to 544 MHz (*) */
-#define LL_RCC_PLLVCORANGE_MEDIUM          (uint32_t)(0x00000001)       /* VCO output range: 150 to 420 MHz */
-/**
-  * (*) : For stm32h7a3xx and stm32h7b3xx family lines.
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
-  * @{
-  */
-
-/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
-  * @{
-  */
-
-/**
-  * @brief  Write a value in RCC register
-  * @param  __REG__ Register to be written
-  * @param  __VALUE__ Value to be written in the register
-  * @retval None
-  */
-#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
-
-/**
-  * @brief  Read a value in RCC register
-  * @param  __REG__ Register to be read
-  * @retval Register value
-  */
-#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
-  * @{
-  */
-
-/**
-  * @brief  Helper macro to calculate the SYSCLK frequency
-  * @param  __SYSINPUTCLKFREQ__ Frequency of the input of sys_ck (based on HSE/CSI/HSI/PLL1P)
-  * @param  __SYSPRESCALER__ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_SYSCLK_DIV_1
-  *         @arg @ref LL_RCC_SYSCLK_DIV_2
-  *         @arg @ref LL_RCC_SYSCLK_DIV_4
-  *         @arg @ref LL_RCC_SYSCLK_DIV_8
-  *         @arg @ref LL_RCC_SYSCLK_DIV_16
-  *         @arg @ref LL_RCC_SYSCLK_DIV_64
-  *         @arg @ref LL_RCC_SYSCLK_DIV_128
-  *         @arg @ref LL_RCC_SYSCLK_DIV_256
-  *         @arg @ref LL_RCC_SYSCLK_DIV_512
-  * @retval SYSCLK clock frequency (in Hz)
-  */
-#if defined(RCC_D1CFGR_D1CPRE)
-#define LL_RCC_CALC_SYSCLK_FREQ(__SYSINPUTCLKFREQ__, __SYSPRESCALER__) ((__SYSINPUTCLKFREQ__) >> ((LL_RCC_PrescTable[((__SYSPRESCALER__) & RCC_D1CFGR_D1CPRE) >>  RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU))
-#else
-#define LL_RCC_CALC_SYSCLK_FREQ(__SYSINPUTCLKFREQ__, __SYSPRESCALER__) ((__SYSINPUTCLKFREQ__) >> ((LL_RCC_PrescTable[((__SYSPRESCALER__) & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU))
-#endif /* RCC_D1CFGR_D1CPRE */
-
-/**
-  * @brief  Helper macro to calculate the HCLK frequency
-  * @param  __SYSCLKFREQ__ SYSCLK frequency.
-  * @param  __HPRESCALER__ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_AHB_DIV_1
-  *         @arg @ref LL_RCC_AHB_DIV_2
-  *         @arg @ref LL_RCC_AHB_DIV_4
-  *         @arg @ref LL_RCC_AHB_DIV_8
-  *         @arg @ref LL_RCC_AHB_DIV_16
-  *         @arg @ref LL_RCC_AHB_DIV_64
-  *         @arg @ref LL_RCC_AHB_DIV_128
-  *         @arg @ref LL_RCC_AHB_DIV_256
-  *         @arg @ref LL_RCC_AHB_DIV_512
-  * @retval HCLK clock frequency (in Hz)
-  */
-#if defined(RCC_D1CFGR_HPRE)
-#define LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __HPRESCALER__) ((__SYSCLKFREQ__) >> ((LL_RCC_PrescTable[((__HPRESCALER__) & RCC_D1CFGR_HPRE) >>  RCC_D1CFGR_HPRE_Pos]) & 0x1FU))
-#else
-#define LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __HPRESCALER__) ((__SYSCLKFREQ__) >> ((LL_RCC_PrescTable[((__HPRESCALER__) & RCC_CDCFGR1_HPRE) >>  RCC_CDCFGR1_HPRE_Pos]) & 0x1FU))
-#endif  /* RCC_D1CFGR_HPRE */
-
-/**
-  * @brief  Helper macro to calculate the PCLK1 frequency (ABP1)
-  * @param  __HCLKFREQ__ HCLK frequency
-  * @param  __APB1PRESCALER__ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_APB1_DIV_1
-  *         @arg @ref LL_RCC_APB1_DIV_2
-  *         @arg @ref LL_RCC_APB1_DIV_4
-  *         @arg @ref LL_RCC_APB1_DIV_8
-  *         @arg @ref LL_RCC_APB1_DIV_16
-  * @retval PCLK1 clock frequency (in Hz)
-  */
-#if defined(RCC_D2CFGR_D2PPRE1)
-#define LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB1PRESCALER__) & RCC_D2CFGR_D2PPRE1) >>  RCC_D2CFGR_D2PPRE1_Pos]) & 0x1FU))
-#else
-#define LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB1PRESCALER__) & RCC_CDCFGR2_CDPPRE1) >>  RCC_CDCFGR2_CDPPRE1_Pos]) & 0x1FU))
-#endif /* RCC_D2CFGR_D2PPRE1 */
-
-/**
-  * @brief  Helper macro to calculate the PCLK2 frequency (ABP2)
-  * @param  __HCLKFREQ__ HCLK frequency
-  * @param  __APB2PRESCALER__ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_APB2_DIV_1
-  *         @arg @ref LL_RCC_APB2_DIV_2
-  *         @arg @ref LL_RCC_APB2_DIV_4
-  *         @arg @ref LL_RCC_APB2_DIV_8
-  *         @arg @ref LL_RCC_APB2_DIV_16
-  * @retval PCLK2 clock frequency (in Hz)
-  */
-#if defined(RCC_D2CFGR_D2PPRE2)
-#define LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB2PRESCALER__) & RCC_D2CFGR_D2PPRE2) >>  RCC_D2CFGR_D2PPRE2_Pos]) & 0x1FU))
-#else
-#define LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB2PRESCALER__) & RCC_CDCFGR2_CDPPRE2) >> RCC_CDCFGR2_CDPPRE2_Pos]) & 0x1FU))
-#endif /* RCC_D2CFGR_D2PPRE2 */
-
-/**
-  * @brief  Helper macro to calculate the PCLK3 frequency (APB3)
-  * @param  __HCLKFREQ__ HCLK frequency
-  * @param  __APB3PRESCALER__ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_APB3_DIV_1
-  *         @arg @ref LL_RCC_APB3_DIV_2
-  *         @arg @ref LL_RCC_APB3_DIV_4
-  *         @arg @ref LL_RCC_APB3_DIV_8
-  *         @arg @ref LL_RCC_APB3_DIV_16
-  * @retval PCLK1 clock frequency (in Hz)
-  */
-#if defined(RCC_D1CFGR_D1PPRE)
-#define LL_RCC_CALC_PCLK3_FREQ(__HCLKFREQ__, __APB3PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB3PRESCALER__) & RCC_D1CFGR_D1PPRE) >>  RCC_D1CFGR_D1PPRE_Pos]) & 0x1FU))
-#else
-#define LL_RCC_CALC_PCLK3_FREQ(__HCLKFREQ__, __APB3PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB3PRESCALER__) & RCC_CDCFGR1_CDPPRE) >> RCC_CDCFGR1_CDPPRE_Pos]) & 0x1FU))
-#endif /* RCC_D1CFGR_D1PPRE */
-
-/**
-  * @brief  Helper macro to calculate the PCLK4 frequency (ABP4)
-  * @param  __HCLKFREQ__ HCLK frequency
-  * @param  __APB4PRESCALER__ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_APB4_DIV_1
-  *         @arg @ref LL_RCC_APB4_DIV_2
-  *         @arg @ref LL_RCC_APB4_DIV_4
-  *         @arg @ref LL_RCC_APB4_DIV_8
-  *         @arg @ref LL_RCC_APB4_DIV_16
-  * @retval PCLK1 clock frequency (in Hz)
-  */
-#if defined(RCC_D3CFGR_D3PPRE)
-#define LL_RCC_CALC_PCLK4_FREQ(__HCLKFREQ__, __APB4PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB4PRESCALER__) & RCC_D3CFGR_D3PPRE) >>  RCC_D3CFGR_D3PPRE_Pos]) & 0x1FU))
-#else
-#define LL_RCC_CALC_PCLK4_FREQ(__HCLKFREQ__, __APB4PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB4PRESCALER__) & RCC_SRDCFGR_SRDPPRE) >>  RCC_SRDCFGR_SRDPPRE_Pos]) & 0x1FU))
-#endif /* RCC_D3CFGR_D3PPRE */
-
-/**
-  * @}
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
-  * @{
-  */
-#define LL_RCC_PERIPH_FREQUENCY_NO         0x00000000U                 /*!< No clock enabled for the peripheral            */
-#define LL_RCC_PERIPH_FREQUENCY_NA         0xFFFFFFFFU                 /*!< Frequency cannot be provided as external clock */
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
-  * @{
-  */
-
-/** @defgroup RCC_LL_EF_HSE HSE
-  * @{
-  */
-
-/**
-  * @brief  Enable the Clock Security System.
-  * @note Once HSE Clock Security System is enabled it cannot be changed anymore unless
-  *       a reset occurs or system enter in standby mode.
-  * @rmtoll CR           CSSHSEON         LL_RCC_HSE_EnableCSS
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
-{
-  SET_BIT(RCC->CR, RCC_CR_CSSHSEON);
-}
-
-/**
-  * @brief  Enable HSE external oscillator (HSE Bypass)
-  * @rmtoll CR           HSEBYP        LL_RCC_HSE_EnableBypass
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
-{
-  SET_BIT(RCC->CR, RCC_CR_HSEBYP);
-}
-
-/**
-  * @brief  Disable HSE external oscillator (HSE Bypass)
-  * @rmtoll CR           HSEBYP        LL_RCC_HSE_DisableBypass
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
-{
-  CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
-}
-
-#if defined(RCC_CR_HSEEXT)
-/**
-  * @brief  Select the Analog HSE external clock type in Bypass mode
-  * @rmtoll CR           HSEEXT        LL_RCC_HSE_SelectAnalogClock
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_HSE_SelectAnalogClock(void)
-{
-  CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT);
-}
-
-/**
-  * @brief  Select the Digital HSE external clock type in Bypass mode
-  * @rmtoll CR           HSEEXT        LL_RCC_HSE_SelectDigitalClock
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_HSE_SelectDigitalClock(void)
-{
-  SET_BIT(RCC->CR, RCC_CR_HSEEXT);
-}
-#endif /* RCC_CR_HSEEXT */
-
-/**
-  * @brief  Enable HSE crystal oscillator (HSE ON)
-  * @rmtoll CR           HSEON         LL_RCC_HSE_Enable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_HSE_Enable(void)
-{
-  SET_BIT(RCC->CR, RCC_CR_HSEON);
-}
-
-/**
-  * @brief  Disable HSE crystal oscillator (HSE ON)
-  * @rmtoll CR           HSEON         LL_RCC_HSE_Disable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_HSE_Disable(void)
-{
-  CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
-}
-
-/**
-  * @brief  Check if HSE oscillator Ready
-  * @rmtoll CR           HSERDY        LL_RCC_HSE_IsReady
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
-{
-  return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY))?1UL:0UL);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EF_HSI HSI
-  * @{
-  */
-
-/**
-  * @brief  Enable HSI oscillator
-  * @rmtoll CR           HSION         LL_RCC_HSI_Enable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_HSI_Enable(void)
-{
-  SET_BIT(RCC->CR, RCC_CR_HSION);
-}
-
-/**
-  * @brief  Disable HSI oscillator
-  * @rmtoll CR           HSION         LL_RCC_HSI_Disable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_HSI_Disable(void)
-{
-  CLEAR_BIT(RCC->CR, RCC_CR_HSION);
-}
-
-/**
-  * @brief  Check if HSI clock is ready
-  * @rmtoll CR           HSIRDY        LL_RCC_HSI_IsReady
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
-{
-  return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY))?1UL:0UL);
-}
-
-/**
-  * @brief  Check if HSI new divider applied and ready
-  * @rmtoll CR           HSIDIVF        LL_RCC_HSI_IsDividerReady
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_HSI_IsDividerReady(void)
-{
-  return ((READ_BIT(RCC->CR, RCC_CR_HSIDIVF) == (RCC_CR_HSIDIVF))?1UL:0UL);
-}
-
-/**
-  * @brief  Set HSI divider
-  * @rmtoll CR           HSIDIV        LL_RCC_HSI_SetDivider
-  * @param  Divider This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_HSI_DIV1
-  *         @arg @ref LL_RCC_HSI_DIV2
-  *         @arg @ref LL_RCC_HSI_DIV4
-  *         @arg @ref LL_RCC_HSI_DIV8
-  * @retval None.
-  */
-__STATIC_INLINE void LL_RCC_HSI_SetDivider(uint32_t Divider)
-{
-  MODIFY_REG(RCC->CR, RCC_CR_HSIDIV, Divider);
-}
-
-/**
-  * @brief  Get HSI divider
-  * @rmtoll CR           HSIDIV        LL_RCC_HSI_GetDivider
-  * @retval can be one of the following values:
-  *         @arg @ref LL_RCC_HSI_DIV1
-  *         @arg @ref LL_RCC_HSI_DIV2
-  *         @arg @ref LL_RCC_HSI_DIV4
-  *         @arg @ref LL_RCC_HSI_DIV8
-  */
-__STATIC_INLINE uint32_t LL_RCC_HSI_GetDivider(void)
-{
-  return (READ_BIT(RCC->CR, RCC_CR_HSIDIV));
-}
-
-/**
-  * @brief  Enable HSI oscillator in Stop mode
-  * @rmtoll CR           HSIKERON         LL_RCC_HSI_EnableStopMode
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_HSI_EnableStopMode(void)
-{
-  SET_BIT(RCC->CR, RCC_CR_HSIKERON);
-}
-
-/**
-  * @brief  Disable HSI oscillator in Stop mode
-  * @rmtoll CR           HSION         LL_RCC_HSI_DisableStopMode
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_HSI_DisableStopMode(void)
-{
-  CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON);
-}
-
-/**
-  * @brief  Get HSI Calibration value
-  * @note When HSITRIM is written, HSICAL is updated with the sum of
-  *       HSITRIM and the factory trim value
-  * @rmtoll HSICFGR        HSICAL        LL_RCC_HSI_GetCalibration
-  * @retval A value between 0 and 4095 (0xFFF)
-  */
-__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
-{
-  return (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSICAL) >> RCC_HSICFGR_HSICAL_Pos);
-}
-
-/**
-  * @brief  Set HSI Calibration trimming
-  * @note user-programmable trimming value that is added to the HSICAL
-  * @note Default value is 64 (32 for Cut1.x), which, when added to the HSICAL value,
-  *       should trim the HSI to 64 MHz +/- 1 %
-  * @rmtoll HSICFGR        HSITRIM       LL_RCC_HSI_SetCalibTrimming
-  * @param  Value can be a value between 0 and 127 (63 for Cut1.x)
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
-{
-#if defined(RCC_VER_X)
-  if ((DBGMCU->IDCODE & 0xF0000000U) == 0x10000000U)
-  {
-    /* STM32H7 Rev.Y */
-    MODIFY_REG(RCC->HSICFGR, 0x3F000U, Value << 12U);
-  }
-  else
-  {
-    /* STM32H7 Rev.V */
-    MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, Value << RCC_HSICFGR_HSITRIM_Pos);
-  }
-#else
-    MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, Value << RCC_HSICFGR_HSITRIM_Pos);
-#endif /* RCC_VER_X */
-}
-
-/**
-  * @brief  Get HSI Calibration trimming
-  * @rmtoll HSICFGR        HSITRIM       LL_RCC_HSI_GetCalibTrimming
-  * @retval A value between 0 and 127 (63 for Cut1.x)
-  */
-__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
-{
-#if defined(RCC_VER_X)
-  if ((DBGMCU->IDCODE & 0xF0000000U) == 0x10000000U)
-  {
-    /* STM32H7 Rev.Y */
-    return (uint32_t)(READ_BIT(RCC->HSICFGR, 0x3F000U) >> 12U);
-  }
-  else
-  {
-    /* STM32H7 Rev.V */
-    return (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos);
-  }
-#else
-    return (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos);
-#endif /* RCC_VER_X */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EF_CSI CSI
-  * @{
-  */
-
-/**
-  * @brief  Enable CSI oscillator
-  * @rmtoll CR           CSION         LL_RCC_CSI_Enable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_CSI_Enable(void)
-{
-  SET_BIT(RCC->CR, RCC_CR_CSION);
-}
-
-/**
-  * @brief  Disable CSI oscillator
-  * @rmtoll CR           CSION         LL_RCC_CSI_Disable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_CSI_Disable(void)
-{
-  CLEAR_BIT(RCC->CR, RCC_CR_CSION);
-}
-
-/**
-  * @brief  Check if CSI clock is ready
-  * @rmtoll CR           CSIRDY        LL_RCC_CSI_IsReady
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_CSI_IsReady(void)
-{
-  return ((READ_BIT(RCC->CR, RCC_CR_CSIRDY) == (RCC_CR_CSIRDY))?1UL:0UL);
-}
-
-/**
-  * @brief  Enable CSI oscillator in Stop mode
-  * @rmtoll CR           CSIKERON         LL_RCC_CSI_EnableStopMode
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_CSI_EnableStopMode(void)
-{
-  SET_BIT(RCC->CR, RCC_CR_CSIKERON);
-}
-
-/**
-  * @brief  Disable CSI oscillator in Stop mode
-  * @rmtoll CR           CSIKERON         LL_RCC_CSI_DisableStopMode
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_CSI_DisableStopMode(void)
-{
-  CLEAR_BIT(RCC->CR, RCC_CR_CSIKERON);
-}
-
-/**
-  * @brief  Get CSI Calibration value
-  * @note When CSITRIM is written, CSICAL is updated with the sum of
-  *       CSITRIM and the factory trim value
-  * @rmtoll CSICFGR        CSICAL        LL_RCC_CSI_GetCalibration
-  * @retval A value between 0 and 255 (0xFF)
-  */
-__STATIC_INLINE uint32_t LL_RCC_CSI_GetCalibration(void)
-{
-#if defined(RCC_VER_X)
-  if ((DBGMCU->IDCODE & 0xF0000000U) == 0x10000000U)
-  {
-    /* STM32H7 Rev.Y */
-    return (uint32_t)(READ_BIT(RCC->HSICFGR, 0x3FC0000U) >> 18U);
-  }
-  else
-  {
-    /* STM32H7 Rev.V */
-    return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSICAL) >> RCC_CSICFGR_CSICAL_Pos);
-  }
-#else
-    return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSICAL) >> RCC_CSICFGR_CSICAL_Pos);
-#endif /* RCC_VER_X */
-}
-
-/**
-  * @brief  Set CSI Calibration trimming
-  * @note user-programmable trimming value that is added to the CSICAL
-  * @note Default value is 16, which, when added to the CSICAL value,
-  *       should trim the CSI to 4 MHz +/- 1 %
-  * @rmtoll CSICFGR        CSITRIM       LL_RCC_CSI_SetCalibTrimming
-  * @param  Value can be a value between 0 and 31
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_CSI_SetCalibTrimming(uint32_t Value)
-{
-#if defined(RCC_VER_X)
-  if ((DBGMCU->IDCODE & 0xF0000000U) == 0x10000000U)
-  {
-    /* STM32H7 Rev.Y */
-    MODIFY_REG(RCC->HSICFGR, 0x7C000000U, Value << 26U);
-  }
-  else
-  {
-    /* STM32H7 Rev.V */
-    MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, Value << RCC_CSICFGR_CSITRIM_Pos);
-  }
-#else
-    MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, Value << RCC_CSICFGR_CSITRIM_Pos);
-#endif /* RCC_VER_X */
-}
-
-/**
-  * @brief  Get CSI Calibration trimming
-  * @rmtoll CSICFGR        CSITRIM       LL_RCC_CSI_GetCalibTrimming
-  * @retval A value between 0 and 31
-  */
-__STATIC_INLINE uint32_t LL_RCC_CSI_GetCalibTrimming(void)
-{
-#if defined(RCC_VER_X)
-  if ((DBGMCU->IDCODE & 0xF0000000U) == 0x10000000U)
-  {
-    /* STM32H7 Rev.Y */
-    return (uint32_t)(READ_BIT(RCC->HSICFGR, 0x7C000000U) >> 26U);
-  }
-  else
-  {
-    /* STM32H7 Rev.V */
-    return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos);
-  }
-#else
-    return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos);
-#endif /* RCC_VER_X */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EF_HSI48 HSI48
-  * @{
-  */
-
-/**
-  * @brief  Enable HSI48 oscillator
-  * @rmtoll CR           HSI48ON         LL_RCC_HSI48_Enable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_HSI48_Enable(void)
-{
-  SET_BIT(RCC->CR, RCC_CR_HSI48ON);
-}
-
-/**
-  * @brief  Disable HSI48 oscillator
-  * @rmtoll CR           HSI48ON         LL_RCC_HSI48_Disable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_HSI48_Disable(void)
-{
-  CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON);
-}
-
-/**
-  * @brief  Check if HSI48 clock is ready
-  * @rmtoll CR           HSI48RDY        LL_RCC_HSI48_IsReady
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void)
-{
-  return ((READ_BIT(RCC->CR, RCC_CR_HSI48RDY) == (RCC_CR_HSI48RDY))?1UL:0UL);
-}
-
-/**
-  * @brief  Get HSI48 Calibration value
-  * @note When HSI48TRIM is written, HSI48CAL is updated with the sum of
-  *       HSI48TRIM and the factory trim value
-  * @rmtoll CRRCR        HSI48CAL        LL_RCC_HSI48_GetCalibration
-  * @retval A value between 0 and 1023 (0x3FF)
-  */
-__STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void)
-{
-  return (uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48CAL) >> RCC_CRRCR_HSI48CAL_Pos);
-}
-/**
-  * @}
-  */
-
-#if defined(RCC_CR_D1CKRDY)
-
-/** @defgroup RCC_LL_EF_D1CLK D1CKREADY
-  * @{
-  */
-
-/**
-  * @brief  Check if D1 clock is ready
-  * @rmtoll CR           D1CKRDY        LL_RCC_D1CK_IsReady
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_D1CK_IsReady(void)
-{
-  return ((READ_BIT(RCC->CR, RCC_CR_D1CKRDY) == (RCC_CR_D1CKRDY))?1UL:0UL);
-}
-
-/**
-  * @}
-  */
-#else
-
-/** @defgroup RCC_LL_EF_CPUCLK CPUCKREADY
-  * @{
-  */
-
-/**
-  * @brief  Check if CPU clock is ready
-  * @rmtoll CR           CPUCKRDY        LL_RCC_CPUCK_IsReady
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_CPUCK_IsReady(void)
-{
-  return ((READ_BIT(RCC->CR, RCC_CR_CPUCKRDY) == (RCC_CR_CPUCKRDY))?1UL:0UL);
-}
- /* alias */
-#define LL_RCC_D1CK_IsReady  LL_RCC_CPUCK_IsReady
-/**
-  * @}
-  */
-#endif /* RCC_CR_D1CKRDY */
-
-#if defined(RCC_CR_D2CKRDY)
-
-/** @defgroup RCC_LL_EF_D2CLK D2CKREADY
-  * @{
-  */
-
-/**
-  * @brief  Check if D2 clock is ready
-  * @rmtoll CR           D2CKRDY        LL_RCC_D2CK_IsReady
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_D2CK_IsReady(void)
-{
-  return ((READ_BIT(RCC->CR, RCC_CR_D2CKRDY) == (RCC_CR_D2CKRDY))?1UL:0UL);
-}
-/**
-  * @}
-  */
-#else
-
-/** @defgroup RCC_LL_EF_CDCLK CDCKREADY
-  * @{
-  */
-
-/**
-  * @brief  Check if CD clock is ready
-  * @rmtoll CR           CDCKRDY        LL_RCC_CDCK_IsReady
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_CDCK_IsReady(void)
-{
-  return ((READ_BIT(RCC->CR, RCC_CR_CDCKRDY) == (RCC_CR_CDCKRDY))?1UL:0UL);
-}
-#define LL_RCC_D2CK_IsReady LL_RCC_CDCK_IsReady
-/**
-  * @}
-  */
-#endif /* RCC_CR_D2CKRDY */
-
-/** @defgroup RCC_LL_EF_SYSTEM_WIDE_RESET RESET
-  * @{
-  */
-#if defined(RCC_GCR_WW1RSC)
-
-/**
-  * @brief  Enable system wide reset for Window Watch Dog 1
-  * @rmtoll GCR          WW1RSC        LL_RCC_WWDG1_EnableSystemReset
-  * @retval None.
-  */
-__STATIC_INLINE void LL_RCC_WWDG1_EnableSystemReset(void)
-{
-  SET_BIT(RCC->GCR, RCC_GCR_WW1RSC);
-}
-
-/**
-  * @brief  Check if Window Watch Dog 1 reset is system wide
-  * @rmtoll GCR          WW1RSC        LL_RCC_WWDG1_IsSystemReset
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_WWDG1_IsSystemReset(void)
-{
-  return ((READ_BIT(RCC->GCR, RCC_GCR_WW1RSC) == RCC_GCR_WW1RSC)?1UL:0UL);
-}
-#endif  /* RCC_GCR_WW1RSC */
-
-#if defined(DUAL_CORE)
-/**
-  * @brief  Enable system wide reset for Window Watch Dog 2
-  * @rmtoll GCR          WW1RSC        LL_RCC_WWDG2_EnableSystemReset
-  * @retval None.
-  */
-__STATIC_INLINE void LL_RCC_WWDG2_EnableSystemReset(void)
-{
-  SET_BIT(RCC->GCR, RCC_GCR_WW2RSC);
-}
-
-/**
-  * @brief  Check if Window Watch Dog 2 reset is system wide
-  * @rmtoll GCR          WW2RSC        LL_RCC_WWDG2_IsSystemReset
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_WWDG2_IsSystemReset(void)
-{
-  return ((READ_BIT(RCC->GCR, RCC_GCR_WW2RSC) == RCC_GCR_WW2RSC)?1UL:0UL);
-}
-#endif  /*DUAL_CORE*/
-/**
-  * @}
-  */
-
-#if defined(DUAL_CORE)
-/** @defgroup RCC_LL_EF_BOOT_CPU CPU
-  * @{
-  */
-
-/**
-  * @brief  Force CM4 boot (if hold by option byte BCM4 = 0)
-  * @rmtoll GCR          BOOT_C2        LL_RCC_ForceCM4Boot
-  * @retval None.
-  */
-__STATIC_INLINE void LL_RCC_ForceCM4Boot(void)
-{
-  SET_BIT(RCC->GCR, RCC_GCR_BOOT_C2);
-}
-
-/**
-  * @brief  Check if CM4 boot is forced
-  * @rmtoll GCR          BOOT_C2        LL_RCC_IsCM4BootForced
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsCM4BootForced(void)
-{
-  return ((READ_BIT(RCC->GCR, RCC_GCR_BOOT_C2) == RCC_GCR_BOOT_C2)?1UL:0UL);
-}
-
-/**
-  * @brief  Force CM7 boot (if hold by option byte BCM7 = 0)
-  * @rmtoll GCR          BOOT_C1        LL_RCC_ForceCM7Boot
-  * @retval None.
-  */
-__STATIC_INLINE void LL_RCC_ForceCM7Boot(void)
-{
-  SET_BIT(RCC->GCR, RCC_GCR_BOOT_C1);
-}
-
-/**
-  * @brief  Check if CM7 boot is forced
-  * @rmtoll GCR          BOOT_C1        LL_RCC_IsCM7BootForced
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsCM7BootForced(void)
-{
-  return ((READ_BIT(RCC->GCR, RCC_GCR_BOOT_C1) == RCC_GCR_BOOT_C1)?1UL:0UL);
-}
-
-/**
-  * @}
-  */
-#endif  /*DUAL_CORE*/
-
-/** @defgroup RCC_LL_EF_LSE LSE
-  * @{
-  */
-
-/**
-  * @brief  Enable the Clock Security System on LSE.
-  * @note Once LSE Clock Security System is enabled it cannot be changed anymore unless
-  *       a clock failure is detected.
-  * @rmtoll BDCR          LSECSSON         LL_RCC_LSE_EnableCSS
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_LSE_EnableCSS(void)
-{
-  SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
-}
-
-/**
-  * @brief  Check if LSE failure is detected by Clock Security System
-  * @rmtoll BDCR         LSECSSD       LL_RCC_LSE_IsFailureDetected
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_LSE_IsFailureDetected(void)
-{
-  return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == (RCC_BDCR_LSECSSD))?1UL:0UL);
-}
-
-/**
-  * @brief  Enable  Low Speed External (LSE) crystal.
-  * @rmtoll BDCR         LSEON         LL_RCC_LSE_Enable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_LSE_Enable(void)
-{
-  SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
-}
-
-/**
-  * @brief  Disable  Low Speed External (LSE) crystal.
-  * @rmtoll BDCR         LSEON         LL_RCC_LSE_Disable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_LSE_Disable(void)
-{
-  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
-}
-
-/**
-  * @brief  Enable external clock source (LSE bypass).
-  * @rmtoll BDCR         LSEBYP        LL_RCC_LSE_EnableBypass
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
-{
-  SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
-}
-
-/**
-  * @brief  Disable external clock source (LSE bypass).
-  * @rmtoll BDCR         LSEBYP        LL_RCC_LSE_DisableBypass
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
-{
-  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
-}
-
-#if defined(RCC_BDCR_LSEEXT)
-/**
-  * @brief  Enable Low-speed external DIGITAL clock type in Bypass mode (not to be used if RTC is active).
-  * @note   The external clock must be enabled with the LSEON bit, to be used by the device.
-  *         The LSEEXT bit can be written only if the LSE oscillator is disabled.
-  * @rmtoll BDCR         LSEEXT        LL_RCC_LSE_SelectDigitalClock
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_LSE_SelectDigitalClock(void)
-{
-  SET_BIT(RCC->BDCR, RCC_BDCR_LSEEXT);
-}
-
-/**
-  * @brief  Enable Low-speed external ANALOG clock type in Bypass mode (default after Backup domain reset).
-  * @note   The external clock must be enabled with the LSEON bit, to be used by the device.
-  *         The LSEEXT bit can be written only if the LSE oscillator is disabled.
-  * @rmtoll BDCR         LSEEXT        LL_RCC_LSE_SelectAnalogClock
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_LSE_SelectAnalogClock(void)
-{
-  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT);
-}
-#endif /* RCC_BDCR_LSEEXT */
-
-/**
-  * @brief  Set LSE oscillator drive capability
-  * @note The oscillator is in Xtal mode when it is not in bypass mode.
-  * @rmtoll BDCR         LSEDRV        LL_RCC_LSE_SetDriveCapability
-  * @param  LSEDrive This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_LSEDRIVE_LOW
-  *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
-  *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
-  *         @arg @ref LL_RCC_LSEDRIVE_HIGH
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
-{
-  MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
-}
-
-/**
-  * @brief  Get LSE oscillator drive capability
-  * @rmtoll BDCR         LSEDRV        LL_RCC_LSE_GetDriveCapability
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_LSEDRIVE_LOW
-  *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
-  *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
-  *         @arg @ref LL_RCC_LSEDRIVE_HIGH
-  */
-__STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
-{
-  return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV));
-}
-
-/**
-  * @brief  Check if LSE oscillator Ready
-  * @rmtoll BDCR         LSERDY        LL_RCC_LSE_IsReady
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
-{
-  return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY))?1UL:0UL);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EF_LSI LSI
-  * @{
-  */
-
-/**
-  * @brief  Enable LSI Oscillator
-  * @rmtoll CSR          LSION         LL_RCC_LSI_Enable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_LSI_Enable(void)
-{
-  SET_BIT(RCC->CSR, RCC_CSR_LSION);
-}
-
-/**
-  * @brief  Disable LSI Oscillator
-  * @rmtoll CSR          LSION         LL_RCC_LSI_Disable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_LSI_Disable(void)
-{
-  CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
-}
-
-/**
-  * @brief  Check if LSI is Ready
-  * @rmtoll CSR          LSIRDY        LL_RCC_LSI_IsReady
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
-{
-  return ((READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY))?1UL:0UL);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EF_System System
-  * @{
-  */
-
-/**
-  * @brief  Configure the system clock source
-  * @rmtoll CFGR         SW            LL_RCC_SetSysClkSource
-  * @param  Source This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
-  *         @arg @ref LL_RCC_SYS_CLKSOURCE_CSI
-  *         @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
-  *         @arg @ref LL_RCC_SYS_CLKSOURCE_PLL1
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
-{
-  MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
-}
-
-/**
-  * @brief  Get the system clock source
-  * @rmtoll CFGR         SWS           LL_RCC_GetSysClkSource
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
-  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_CSI
-  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
-  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL1
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
-{
-  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
-}
-
-/**
-  * @brief  Configure the system wakeup clock source
-  * @rmtoll CFGR         STOPWUCK       LL_RCC_SetSysWakeUpClkSource
-  * @param  Source This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_HSI
-  *         @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_CSI
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetSysWakeUpClkSource(uint32_t Source)
-{
-  MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, Source);
-}
-
-/**
-  * @brief  Get the system wakeup clock source
-  * @rmtoll CFGR         STOPWUCK           LL_RCC_GetSysWakeUpClkSource
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_HSI
-  *         @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_CSI
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetSysWakeUpClkSource(void)
-{
-  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_STOPWUCK));
-}
-
-/**
-  * @brief  Configure the kernel wakeup clock source
-  * @rmtoll CFGR         STOPKERWUCK       LL_RCC_SetKerWakeUpClkSource
-  * @param  Source This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_HSI
-  *         @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_CSI
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetKerWakeUpClkSource(uint32_t Source)
-{
-  MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPKERWUCK, Source);
-}
-
-/**
-  * @brief  Get the kernel wakeup clock source
-  * @rmtoll CFGR         STOPKERWUCK           LL_RCC_GetKerWakeUpClkSource
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_HSI
-  *         @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_CSI
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetKerWakeUpClkSource(void)
-{
-  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_STOPKERWUCK));
-}
-
-/**
-  * @brief  Set System prescaler
-  * @rmtoll D1CFGR/CDCFGR1        D1CPRE/CDCPRE          LL_RCC_SetSysPrescaler
-  * @param  Prescaler This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_SYSCLK_DIV_1
-  *         @arg @ref LL_RCC_SYSCLK_DIV_2
-  *         @arg @ref LL_RCC_SYSCLK_DIV_4
-  *         @arg @ref LL_RCC_SYSCLK_DIV_8
-  *         @arg @ref LL_RCC_SYSCLK_DIV_16
-  *         @arg @ref LL_RCC_SYSCLK_DIV_64
-  *         @arg @ref LL_RCC_SYSCLK_DIV_128
-  *         @arg @ref LL_RCC_SYSCLK_DIV_256
-  *         @arg @ref LL_RCC_SYSCLK_DIV_512
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetSysPrescaler(uint32_t Prescaler)
-{
-#if defined(RCC_D1CFGR_D1CPRE)
-  MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1CPRE, Prescaler);
-#else
-  MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDCPRE, Prescaler);
-#endif /* RCC_D1CFGR_D1CPRE */
-}
-
-/**
-  * @brief  Set AHB prescaler
-  * @rmtoll D1CFGR/CDCFGR1        HPRE         LL_RCC_SetAHBPrescaler
-  * @param  Prescaler This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_AHB_DIV_1
-  *         @arg @ref LL_RCC_AHB_DIV_2
-  *         @arg @ref LL_RCC_AHB_DIV_4
-  *         @arg @ref LL_RCC_AHB_DIV_8
-  *         @arg @ref LL_RCC_AHB_DIV_16
-  *         @arg @ref LL_RCC_AHB_DIV_64
-  *         @arg @ref LL_RCC_AHB_DIV_128
-  *         @arg @ref LL_RCC_AHB_DIV_256
-  *         @arg @ref LL_RCC_AHB_DIV_512
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
-{
-#if defined(RCC_D1CFGR_HPRE)
-  MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, Prescaler);
-#else
-  MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_HPRE, Prescaler);
-#endif /* RCC_D1CFGR_HPRE */
-}
-
-/**
-  * @brief  Set APB1 prescaler
-  * @rmtoll D2CFGR/CDCFGR2         D2PPRE1/CDPPRE1         LL_RCC_SetAPB1Prescaler
-  * @param  Prescaler This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_APB1_DIV_1
-  *         @arg @ref LL_RCC_APB1_DIV_2
-  *         @arg @ref LL_RCC_APB1_DIV_4
-  *         @arg @ref LL_RCC_APB1_DIV_8
-  *         @arg @ref LL_RCC_APB1_DIV_16
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
-{
-#if defined(RCC_D2CFGR_D2PPRE1)
-  MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, Prescaler);
-#else
-  MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, Prescaler);
-#endif /* RCC_D2CFGR_D2PPRE1 */
-}
-
-/**
-  * @brief  Set APB2 prescaler
-  * @rmtoll D2CFGR/CDCFGR2         D2PPRE2/CDPPRE2         LL_RCC_SetAPB2Prescaler
-  * @param  Prescaler This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_APB2_DIV_1
-  *         @arg @ref LL_RCC_APB2_DIV_2
-  *         @arg @ref LL_RCC_APB2_DIV_4
-  *         @arg @ref LL_RCC_APB2_DIV_8
-  *         @arg @ref LL_RCC_APB2_DIV_16
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
-{
-#if defined(RCC_D2CFGR_D2PPRE2)
-  MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, Prescaler);
-#else
-  MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE2, Prescaler);
-#endif /* RCC_D2CFGR_D2PPRE2 */
-}
-
-/**
-  * @brief  Set APB3 prescaler
-  * @rmtoll D1CFGR/CDCFGR1         D1PPRE/CDPPRE         LL_RCC_SetAPB3Prescaler
-  * @param  Prescaler This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_APB3_DIV_1
-  *         @arg @ref LL_RCC_APB3_DIV_2
-  *         @arg @ref LL_RCC_APB3_DIV_4
-  *         @arg @ref LL_RCC_APB3_DIV_8
-  *         @arg @ref LL_RCC_APB3_DIV_16
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetAPB3Prescaler(uint32_t Prescaler)
-{
-#if defined(RCC_D1CFGR_D1PPRE)
-  MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, Prescaler);
-#else
-  MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDPPRE, Prescaler);
-#endif /* RCC_D1CFGR_D1PPRE */
-}
-
-/**
-  * @brief  Set APB4 prescaler
-  * @rmtoll D3CFGR/SRDCFGR         D3PPRE/SRDPPRE         LL_RCC_SetAPB4Prescaler
-  * @param  Prescaler This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_APB4_DIV_1
-  *         @arg @ref LL_RCC_APB4_DIV_2
-  *         @arg @ref LL_RCC_APB4_DIV_4
-  *         @arg @ref LL_RCC_APB4_DIV_8
-  *         @arg @ref LL_RCC_APB4_DIV_16
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetAPB4Prescaler(uint32_t Prescaler)
-{
-#if defined(RCC_D3CFGR_D3PPRE)
-  MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, Prescaler);
-#else
-  MODIFY_REG(RCC->SRDCFGR, RCC_SRDCFGR_SRDPPRE, Prescaler);
-#endif /* RCC_D3CFGR_D3PPRE */
-}
-
-/**
-  * @brief  Get System prescaler
-  * @rmtoll D1CFGR/CDCFGR1        D1CPRE/CDCPRE          LL_RCC_GetSysPrescaler
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_SYSCLK_DIV_1
-  *         @arg @ref LL_RCC_SYSCLK_DIV_2
-  *         @arg @ref LL_RCC_SYSCLK_DIV_4
-  *         @arg @ref LL_RCC_SYSCLK_DIV_8
-  *         @arg @ref LL_RCC_SYSCLK_DIV_16
-  *         @arg @ref LL_RCC_SYSCLK_DIV_64
-  *         @arg @ref LL_RCC_SYSCLK_DIV_128
-  *         @arg @ref LL_RCC_SYSCLK_DIV_256
-  *         @arg @ref LL_RCC_SYSCLK_DIV_512
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetSysPrescaler(void)
-{
-#if defined(RCC_D1CFGR_D1CPRE)
-  return (uint32_t)(READ_BIT(RCC->D1CFGR, RCC_D1CFGR_D1CPRE));
-#else
-  return (uint32_t)(READ_BIT(RCC->CDCFGR1, RCC_CDCFGR1_CDCPRE));
-#endif /* RCC_D1CFGR_D1CPRE */
-}
-
-/**
-  * @brief  Get AHB prescaler
-  * @rmtoll D1CFGR/ CDCFGR1       HPRE         LL_RCC_GetAHBPrescaler
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_AHB_DIV_1
-  *         @arg @ref LL_RCC_AHB_DIV_2
-  *         @arg @ref LL_RCC_AHB_DIV_4
-  *         @arg @ref LL_RCC_AHB_DIV_8
-  *         @arg @ref LL_RCC_AHB_DIV_16
-  *         @arg @ref LL_RCC_AHB_DIV_64
-  *         @arg @ref LL_RCC_AHB_DIV_128
-  *         @arg @ref LL_RCC_AHB_DIV_256
-  *         @arg @ref LL_RCC_AHB_DIV_512
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
-{
-#if defined(RCC_D1CFGR_HPRE)
-  return (uint32_t)(READ_BIT(RCC->D1CFGR, RCC_D1CFGR_HPRE));
-#else
-  return (uint32_t)(READ_BIT(RCC->CDCFGR1, RCC_CDCFGR1_HPRE));
-#endif /* RCC_D1CFGR_HPRE */
-}
-
-/**
-  * @brief  Get APB1 prescaler
-  * @rmtoll D2CFGR/CDCFGR2         D2PPRE1/CDPPRE1         LL_RCC_GetAPB1Prescaler
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_APB1_DIV_1
-  *         @arg @ref LL_RCC_APB1_DIV_2
-  *         @arg @ref LL_RCC_APB1_DIV_4
-  *         @arg @ref LL_RCC_APB1_DIV_8
-  *         @arg @ref LL_RCC_APB1_DIV_16
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
-{
-#if defined(RCC_D2CFGR_D2PPRE1)
-  return (uint32_t)(READ_BIT(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1));
-#else
-  return (uint32_t)(READ_BIT(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1));
-#endif /* RCC_D2CFGR_D2PPRE1 */
-}
-
-/**
-  * @brief  Get APB2 prescaler
-  * @rmtoll D2CFGR/CDCFGR2         D2PPRE2/CDPPRE2         LL_RCC_GetAPB2Prescaler
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_APB2_DIV_1
-  *         @arg @ref LL_RCC_APB2_DIV_2
-  *         @arg @ref LL_RCC_APB2_DIV_4
-  *         @arg @ref LL_RCC_APB2_DIV_8
-  *         @arg @ref LL_RCC_APB2_DIV_16
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
-{
-#if defined(RCC_D2CFGR_D2PPRE2)
-  return (uint32_t)(READ_BIT(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2));
-#else
-  return (uint32_t)(READ_BIT(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE2));
-#endif /* RCC_D2CFGR_D2PPRE2 */
-}
-
-/**
-  * @brief  Get APB3 prescaler
-  * @rmtoll D1CFGR/CDCFGR1         D1PPRE/CDPPRE         LL_RCC_GetAPB3Prescaler
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_APB3_DIV_1
-  *         @arg @ref LL_RCC_APB3_DIV_2
-  *         @arg @ref LL_RCC_APB3_DIV_4
-  *         @arg @ref LL_RCC_APB3_DIV_8
-  *         @arg @ref LL_RCC_APB3_DIV_16
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetAPB3Prescaler(void)
-{
-#if defined(RCC_D1CFGR_D1PPRE)
-  return (uint32_t)(READ_BIT(RCC->D1CFGR, RCC_D1CFGR_D1PPRE));
-#else
-  return (uint32_t)(READ_BIT(RCC->CDCFGR1, RCC_CDCFGR1_CDPPRE));
-#endif /* RCC_D1CFGR_D1PPRE */
-}
-
-/**
-  * @brief  Get APB4 prescaler
-  * @rmtoll D3CFGR/SRDCFGR         D3PPRE/SRDPPRE         LL_RCC_GetAPB4Prescaler
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_APB4_DIV_1
-  *         @arg @ref LL_RCC_APB4_DIV_2
-  *         @arg @ref LL_RCC_APB4_DIV_4
-  *         @arg @ref LL_RCC_APB4_DIV_8
-  *         @arg @ref LL_RCC_APB4_DIV_16
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetAPB4Prescaler(void)
-{
-#if defined(RCC_D3CFGR_D3PPRE)
-  return (uint32_t)(READ_BIT(RCC->D3CFGR, RCC_D3CFGR_D3PPRE));
-#else
-  return (uint32_t)(READ_BIT(RCC->SRDCFGR, RCC_SRDCFGR_SRDPPRE));
-#endif /* RCC_D3CFGR_D3PPRE */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EF_MCO MCO
-  * @{
-  */
-
-/**
-  * @brief  Configure MCOx
-  * @rmtoll CFGR         MCO1          LL_RCC_ConfigMCO\n
-  *         CFGR         MCO1PRE       LL_RCC_ConfigMCO\n
-  *         CFGR         MCO2          LL_RCC_ConfigMCO\n
-  *         CFGR         MCO2PRE       LL_RCC_ConfigMCO
-  * @param  MCOxSource This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_MCO1SOURCE_HSI
-  *         @arg @ref LL_RCC_MCO1SOURCE_LSE
-  *         @arg @ref LL_RCC_MCO1SOURCE_HSE
-  *         @arg @ref LL_RCC_MCO1SOURCE_PLL1QCLK
-  *         @arg @ref LL_RCC_MCO1SOURCE_HSI48
-  *         @arg @ref LL_RCC_MCO2SOURCE_SYSCLK
-  *         @arg @ref LL_RCC_MCO2SOURCE_PLL2PCLK
-  *         @arg @ref LL_RCC_MCO2SOURCE_HSE
-  *         @arg @ref LL_RCC_MCO2SOURCE_PLL1PCLK
-  *         @arg @ref LL_RCC_MCO2SOURCE_CSI
-  *         @arg @ref LL_RCC_MCO2SOURCE_LSI
-  * @param  MCOxPrescaler This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_MCO1_DIV_1
-  *         @arg @ref LL_RCC_MCO1_DIV_2
-  *         @arg @ref LL_RCC_MCO1_DIV_3
-  *         @arg @ref LL_RCC_MCO1_DIV_4
-  *         @arg @ref LL_RCC_MCO1_DIV_5
-  *         @arg @ref LL_RCC_MCO1_DIV_6
-  *         @arg @ref LL_RCC_MCO1_DIV_7
-  *         @arg @ref LL_RCC_MCO1_DIV_8
-  *         @arg @ref LL_RCC_MCO1_DIV_9
-  *         @arg @ref LL_RCC_MCO1_DIV_10
-  *         @arg @ref LL_RCC_MCO1_DIV_11
-  *         @arg @ref LL_RCC_MCO1_DIV_12
-  *         @arg @ref LL_RCC_MCO1_DIV_13
-  *         @arg @ref LL_RCC_MCO1_DIV_14
-  *         @arg @ref LL_RCC_MCO1_DIV_15
-  *         @arg @ref LL_RCC_MCO2_DIV_1
-  *         @arg @ref LL_RCC_MCO2_DIV_2
-  *         @arg @ref LL_RCC_MCO2_DIV_3
-  *         @arg @ref LL_RCC_MCO2_DIV_4
-  *         @arg @ref LL_RCC_MCO2_DIV_5
-  *         @arg @ref LL_RCC_MCO2_DIV_6
-  *         @arg @ref LL_RCC_MCO2_DIV_7
-  *         @arg @ref LL_RCC_MCO2_DIV_8
-  *         @arg @ref LL_RCC_MCO2_DIV_9
-  *         @arg @ref LL_RCC_MCO2_DIV_10
-  *         @arg @ref LL_RCC_MCO2_DIV_11
-  *         @arg @ref LL_RCC_MCO2_DIV_12
-  *         @arg @ref LL_RCC_MCO2_DIV_13
-  *         @arg @ref LL_RCC_MCO2_DIV_14
-  *         @arg @ref LL_RCC_MCO2_DIV_15
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
-{
-  MODIFY_REG(RCC->CFGR,  (MCOxSource << 16U) | (MCOxPrescaler << 16U), (MCOxSource & 0xFFFF0000U) | (MCOxPrescaler & 0xFFFF0000U));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
-  * @{
-  */
-
-/**
-  * @brief  Configure periph clock source
-  * @rmtoll D2CCIP1R/CDCCIP1R        *     LL_RCC_SetClockSource\n
-  *         D2CCIP2R/CDCCIP2R        *     LL_RCC_SetClockSource\n
-  *         D3CCIPR/SRDCCIPR         *     LL_RCC_SetClockSource
-  * @param  ClkSource This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_USART16_CLKSOURCE_PCLK2
-  *         @arg @ref LL_RCC_USART16_CLKSOURCE_PLL2Q
-  *         @arg @ref LL_RCC_USART16_CLKSOURCE_PLL3Q
-  *         @arg @ref LL_RCC_USART16_CLKSOURCE_HSI
-  *         @arg @ref LL_RCC_USART16_CLKSOURCE_CSI
-  *         @arg @ref LL_RCC_USART16_CLKSOURCE_LSE
-  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PCLK1
-  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL2Q
-  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL3Q
-  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_HSI
-  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_CSI
-  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_LSE
-  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_PCLK1
-  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_PLL3R
-  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_HSI
-  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_CSI
-  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK4
-  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_PLL3R
-  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI
-  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_CSI
-  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
-  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P
-  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R
-  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
-  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
-  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP
-  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK4
-  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL2P
-  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL3R
-  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
-  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
-  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP
-  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PCLK4
-  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL2P
-  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL3R
-  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSE
-  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSI
-  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_CLKP
-  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q
-  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P
-  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P
-  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN
-  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP
-  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL1Q (*)
-  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL2P (*) 
-  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL3P (*)
-  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_I2S_CKIN (*)
-  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_CLKP (*)
-  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL1Q (*)
-  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL2P  (*)
-  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL3P  (*)
-  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN  (*)
-  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_SPDIF  (*)
-  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL1Q  (*)
-  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL2P  (*)
-  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL3P  (*)
-  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN  (*)
-  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_CLKP  (*)
-  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_SPDIF  (*)
-  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL1Q  (*)
-  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL2P (*)
-  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL3P (*)
-  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN (*)
-  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_CLKP (*)
-  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_SPDIF (*)
-  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL1Q (*)
-  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL2P (*)
-  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL3P (*)
-  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN (*)
-  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_CLKP (*)
-  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_SPDIF  (*)
-  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL1Q
-  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL2P
-  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL3P
-  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_I2S_CKIN
-  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_CLKP
-  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PCLK2
-  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL2Q
-  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL3Q
-  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_HSI
-  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_CSI
-  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_HSE
-  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4
-  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q
-  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q
-  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI
-  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI
-  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE
-  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_I2S_CKIN (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetClockSource(uint32_t ClkSource)
-{
-#if defined(RCC_D1CCIPR_FMCSEL)
-  uint32_t * pReg = (uint32_t *)((uint32_t)&RCC->D1CCIPR + LL_CLKSOURCE_REG(ClkSource));
-#else
-  uint32_t * pReg = (uint32_t *)((uint32_t)&RCC->CDCCIPR + LL_CLKSOURCE_REG(ClkSource));
-#endif /*  */
-  MODIFY_REG(*pReg, LL_CLKSOURCE_MASK(ClkSource), LL_CLKSOURCE_CONFIG(ClkSource));
-}
-
-/**
-  * @brief  Configure USARTx clock source
-  * @rmtoll D2CCIP2R / D2CCIP2R        USART16SEL     LL_RCC_SetUSARTClockSource\n
-  *         D2CCIP2R / D2CCIP2R        USART28SEL     LL_RCC_SetUSARTClockSource
-  * @param  ClkSource This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_USART16_CLKSOURCE_PCLK2
-  *         @arg @ref LL_RCC_USART16_CLKSOURCE_PLL2Q
-  *         @arg @ref LL_RCC_USART16_CLKSOURCE_PLL3Q
-  *         @arg @ref LL_RCC_USART16_CLKSOURCE_HSI
-  *         @arg @ref LL_RCC_USART16_CLKSOURCE_CSI
-  *         @arg @ref LL_RCC_USART16_CLKSOURCE_LSE
-  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PCLK1
-  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL2Q
-  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL3Q
-  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_HSI
-  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_CSI
-  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_LSE
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t ClkSource)
-{
-  LL_RCC_SetClockSource(ClkSource);
-}
-
-/**
-  * @brief  Configure LPUARTx clock source
-  * @rmtoll D3CCIPR / SRDCCIPR        LPUART1SEL     LL_RCC_SetLPUARTClockSource
-  * @param  ClkSource This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK4
-  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL2Q
-  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL3Q
-  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
-  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_CSI
-  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t ClkSource)
-{
-#if defined(RCC_D3CCIPR_LPUART1SEL)
-  MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL, ClkSource);
-#else
-  MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL, ClkSource);
-#endif /* RCC_D3CCIPR_LPUART1SEL */
-}
-
-/**
-  * @brief  Configure I2Cx clock source
-  * @rmtoll D2CCIP2R / CDCCIP2R       I2C123SEL       LL_RCC_SetI2CClockSource\n
-  *         D3CCIPR / SRDCCIPR        I2C4SEL         LL_RCC_SetI2CClockSource
-  * @param  ClkSource This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_PCLK1
-  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_PLL3R
-  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_HSI
-  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_CSI
-  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK4
-  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_PLL3R
-  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI
-  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_CSI
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t ClkSource)
-{
-  LL_RCC_SetClockSource(ClkSource);
-}
-
-/**
-  * @brief  Configure LPTIMx clock source
-  * @rmtoll D2CCIP2R / CDCCIP2R      LPTIM1SEL     LL_RCC_SetLPTIMClockSource
-  *         D3CCIPR  / SRDCCIPR      LPTIM2SEL     LL_RCC_SetLPTIMClockSource\n
-  *         D3CCIPR  / SRDCCIPR      LPTIM345SEL   LL_RCC_SetLPTIMClockSource
-  * @param  ClkSource This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
-  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P
-  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R
-  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
-  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
-  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP
-  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK4
-  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL2P
-  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL3R
-  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
-  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
-  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP
-  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PCLK4
-  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL2P
-  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL3R
-  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSE
-  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSI
-  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_CLKP
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t ClkSource)
-{
-  LL_RCC_SetClockSource(ClkSource);
-}
-
-/**
-  * @brief  Configure SAIx clock source
-  * @rmtoll D2CCIP1R / CDCCIP1R       SAI1SEL       LL_RCC_SetSAIClockSource\n
-  *         D2CCIP1R / CDCCIP1R       SAI23SEL      LL_RCC_SetSAIClockSource
-  *         D3CCIPR  / SRDCCIPR       SAI4ASEL      LL_RCC_SetSAI4xClockSource\n
-  *         D3CCIPR  / SRDCCIPR       SAI4BSEL      LL_RCC_SetSAI4xClockSource
-  * @param  ClkSource This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q
-  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P
-  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P
-  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN
-  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP
-  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL1Q (*)
-  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL2P (*)
-  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL3P (*)
-  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_I2S_CKIN (*) 
-  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_CLKP (*)
-  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL1Q (*)
-  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL2P  (*)
-  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL3P  (*)
-  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN  (*)
-  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_SPDIF  (*)
-  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL1Q  (*)
-  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL2P  (*)
-  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL3P  (*)
-  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN  (*)
-  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_CLKP  (*)
-  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_SPDIF  (*)
-  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL1Q  (*)
-  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL2P (*)
-  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL3P (*)
-  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN (*)
-  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_CLKP (*)
-  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_SPDIF  (*)
-  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL1Q (*)
-  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL2P (*)
-  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL3P (*)
-  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN (*)
-  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_CLKP (*)
-  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_SPDIF  (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t ClkSource)
-{
-  LL_RCC_SetClockSource(ClkSource);
-}
-
-/**
-  * @brief  Configure SDMMCx clock source
-  * @rmtoll D1CCIPR / CDCCIPR       SDMMCSEL      LL_RCC_SetSDMMCClockSource
-  * @param  ClkSource This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_SDMMC_CLKSOURCE_PLL1Q
-  *         @arg @ref LL_RCC_SDMMC_CLKSOURCE_PLL2R
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetSDMMCClockSource(uint32_t ClkSource)
-{
-#if defined(RCC_D1CCIPR_SDMMCSEL)
-  MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL, ClkSource);
-#else
-  MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL, ClkSource);
-#endif /* RCC_D1CCIPR_SDMMCSEL */
-}
-
-/**
-  * @brief  Configure RNGx clock source
-  * @rmtoll D2CCIP2R / CDCCIP2R       RNGSEL      LL_RCC_SetRNGClockSource
-  * @param  ClkSource This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48
-  *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLL1Q
-  *         @arg @ref LL_RCC_RNG_CLKSOURCE_LSE
-  *         @arg @ref LL_RCC_RNG_CLKSOURCE_LSI
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t ClkSource)
-{
-#if defined(RCC_D2CCIP2R_RNGSEL)
-  MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL, ClkSource);
-#else
-  MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL, ClkSource);
-#endif /* RCC_D2CCIP2R_RNGSEL */
-}
-
-/**
-  * @brief  Configure USBx clock source
-  * @rmtoll D2CCIP2R / CDCCIP2R      USBSEL      LL_RCC_SetUSBClockSource
-  * @param  ClkSource This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_USB_CLKSOURCE_DISABLE
-  *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL1Q
-  *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL3Q
-  *         @arg @ref LL_RCC_USB_CLKSOURCE_HSI48
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t ClkSource)
-{
-#if defined(RCC_D2CCIP2R_USBSEL)
-  MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL, ClkSource);
-#else
-  MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL, ClkSource);
-#endif /* RCC_D2CCIP2R_USBSEL */
-}
-
-/**
-  * @brief  Configure CECx clock source
-  * @rmtoll D2CCIP2R / CDCCIP2R         CECSEL        LL_RCC_SetCECClockSource
-  * @param  ClkSource This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
-  *         @arg @ref LL_RCC_CEC_CLKSOURCE_LSI
-  *         @arg @ref LL_RCC_CEC_CLKSOURCE_CSI_DIV122
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t ClkSource)
-{
-#if defined(RCC_D2CCIP2R_CECSEL)
-  MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL, ClkSource);
-#else
-  MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_CECSEL, ClkSource);
-#endif /* RCC_D2CCIP2R_CECSEL */
-}
-
-#if defined(DSI)
-/**
-  * @brief  Configure DSIx clock source
-  * @rmtoll D1CCIPR         DSISEL        LL_RCC_SetDSIClockSource
-  * @param  ClkSource This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
-  *         @arg @ref LL_RCC_DSI_CLKSOURCE_PLL2Q
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetDSIClockSource(uint32_t ClkSource)
-{
-  MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_DSISEL, ClkSource);
-}
-#endif /* DSI */
-
-/**
-  * @brief  Configure DFSDMx Kernel clock source
-  * @rmtoll D2CCIP1R / CDCCIP1R         DFSDM1SEL        LL_RCC_SetDFSDMClockSource
-  * @param  ClkSource This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
-  *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t ClkSource)
-{
-#if defined(RCC_D2CCIP1R_DFSDM1SEL)
-   MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL, ClkSource);
-#else
-   MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL, ClkSource);
-#endif /* RCC_D2CCIP1R_DFSDM1SEL */
-}
-
-#if defined(DFSDM2_BASE)
-/**
-  * @brief  Configure DFSDMx Kernel clock source
-  * @rmtoll SRDCCIPR                   DFSDM2SEL        LL_RCC_SetDFSDM2ClockSource
-  * @param  ClkSource This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_DFSDM2_CLKSOURCE_PCLK4
-  *         @arg @ref LL_RCC_DFSDM2_CLKSOURCE_SYSCLK
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetDFSDM2ClockSource(uint32_t ClkSource)
-{
-   MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL, ClkSource);
-}
-#endif /* DFSDM2_BASE */
-
-/**
-  * @brief  Configure FMCx Kernel clock source
-  * @rmtoll D1CCIPR /  CDCCIPR        FMCSEL        LL_RCC_SetFMCClockSource
-  * @param  ClkSource This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_FMC_CLKSOURCE_HCLK
-  *         @arg @ref LL_RCC_FMC_CLKSOURCE_PLL1Q
-  *         @arg @ref LL_RCC_FMC_CLKSOURCE_PLL2R
-  *         @arg @ref LL_RCC_FMC_CLKSOURCE_CLKP
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetFMCClockSource(uint32_t ClkSource)
-{
-#if defined(RCC_D1CCIPR_FMCSEL)
-  MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL, ClkSource);
-#else
-  MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL, ClkSource);
-#endif /* RCC_D1CCIPR_FMCSEL */
-}
-
-#if defined(QUADSPI)
-/**
-  * @brief  Configure QSPIx Kernel clock source
-  * @rmtoll D1CCIPR         QSPISEL        LL_RCC_SetQSPIClockSource
-  * @param  ClkSource This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_QSPI_CLKSOURCE_HCLK
-  *         @arg @ref LL_RCC_QSPI_CLKSOURCE_PLL1Q
-  *         @arg @ref LL_RCC_QSPI_CLKSOURCE_PLL2R
-  *         @arg @ref LL_RCC_QSPI_CLKSOURCE_CLKP
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetQSPIClockSource(uint32_t ClkSource)
-{
-  MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL, ClkSource);
-}
-#endif /* QUADSPI */
-
-#if defined(OCTOSPI1) || defined(OCTOSPI2)
-/**
-  * @brief  Configure OSPIx Kernel clock source
-  * @rmtoll D1CCIPR         OPISEL        LL_RCC_SetOSPIClockSource
-  * @param  ClkSource This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_OSPI_CLKSOURCE_HCLK
-  *         @arg @ref LL_RCC_OSPI_CLKSOURCE_PLL1Q
-  *         @arg @ref LL_RCC_OSPI_CLKSOURCE_PLL2R
-  *         @arg @ref LL_RCC_OSPI_CLKSOURCE_CLKP
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetOSPIClockSource(uint32_t ClkSource)
-{
-#if defined(RCC_D1CCIPR_OCTOSPISEL)
-  MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_OCTOSPISEL, ClkSource);
-#else
-  MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL, ClkSource);
-#endif /* RCC_D1CCIPR_OCTOSPISEL */
-}
-#endif /* OCTOSPI1 || OCTOSPI2 */
-
-/**
-  * @brief  Configure CLKP Kernel clock source
-  * @rmtoll D1CCIPR / CDCCIPR         CKPERSEL        LL_RCC_SetCLKPClockSource
-  * @param  ClkSource This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_CLKP_CLKSOURCE_HSI
-  *         @arg @ref LL_RCC_CLKP_CLKSOURCE_CSI
-  *         @arg @ref LL_RCC_CLKP_CLKSOURCE_HSE
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetCLKPClockSource(uint32_t ClkSource)
-{
-#if defined(RCC_D1CCIPR_CKPERSEL)
-  MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL, ClkSource);
-#else
-  MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL, ClkSource);
-#endif /* RCC_D1CCIPR_CKPERSEL */
-}
-
-/**
-  * @brief  Configure SPIx Kernel clock source
-  * @rmtoll D2CCIP1R / CDCCIP1R       SPI123SEL        LL_RCC_SetSPIClockSource\n
-  *         D2CCIP1R / CDCCIP1R       SPI45SEL         LL_RCC_SetSPIClockSource\n
-  *         D3CCIPR  / SRDCCIPR       SPI6SEL          LL_RCC_SetSPIClockSource
-  * @param  ClkSource This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL1Q
-  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL2P
-  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL3P
-  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_I2S_CKIN
-  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_CLKP
-  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PCLK2
-  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL2Q
-  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL3Q
-  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_HSI
-  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_CSI
-  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_HSE
-  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4
-  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q
-  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q
-  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI
-  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI
-  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE
-  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_I2S_CKIN (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetSPIClockSource(uint32_t ClkSource)
-{
-  LL_RCC_SetClockSource(ClkSource);
-}
-
-/**
-  * @brief  Configure SPDIFx Kernel clock source
-  * @rmtoll D2CCIP1R / CDCCIP1R       SPDIFSEL        LL_RCC_SetSPDIFClockSource
-  * @param  ClkSource This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL1Q
-  *         @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL2R
-  *         @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL3R
-  *         @arg @ref LL_RCC_SPDIF_CLKSOURCE_HSI
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetSPDIFClockSource(uint32_t ClkSource)
-{
-#if defined(RCC_D2CCIP1R_SPDIFSEL)
-  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL, ClkSource);
-#else
-  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL, ClkSource);
-#endif /* RCC_D2CCIP1R_SPDIFSEL */
-}
-
-/**
-  * @brief  Configure FDCANx Kernel clock source
-  * @rmtoll D2CCIP1R / CDCCIP1R      FDCANSEL        LL_RCC_SetFDCANClockSource
-  * @param  ClkSource This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE
-  *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL1Q
-  *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL2Q
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetFDCANClockSource(uint32_t ClkSource)
-{
-#if defined(RCC_D2CCIP1R_FDCANSEL)
-  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL, ClkSource);
-#else
-  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_FDCANSEL, ClkSource);
-#endif /* RCC_D2CCIP1R_FDCANSEL */
-}
-
-/**
-  * @brief  Configure SWPx Kernel clock source
-  * @rmtoll D2CCIP1R /  CDCCIP1R       SWPSEL        LL_RCC_SetSWPClockSource
-  * @param  ClkSource This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_SWP_CLKSOURCE_PCLK1
-  *         @arg @ref LL_RCC_SWP_CLKSOURCE_HSI
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetSWPClockSource(uint32_t ClkSource)
-{
-#if defined(RCC_D2CCIP1R_SWPSEL)
-  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL, ClkSource);
-#else
-  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL, ClkSource);
-#endif /* RCC_D2CCIP1R_SWPSEL */
-}
-
-/**
-  * @brief  Configure ADCx Kernel clock source
-  * @rmtoll D3CCIPR / SRDCCIPR        ADCSEL        LL_RCC_SetADCClockSource
-  * @param  ClkSource This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_ADC_CLKSOURCE_PLL2P
-  *         @arg @ref LL_RCC_ADC_CLKSOURCE_PLL3R
-  *         @arg @ref LL_RCC_ADC_CLKSOURCE_CLKP
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ClkSource)
-{
-#if defined(RCC_D3CCIPR_ADCSEL)
-  MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL, ClkSource);
-#else
-  MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL, ClkSource);
-#endif /* RCC_D3CCIPR_ADCSEL */
-}
-
-/**
-  * @brief  Get periph clock source
-  * @rmtoll D1CCIPR  / CDCCIPR       *     LL_RCC_GetClockSource\n
-  *         D2CCIP1R / CDCCIP1R      *     LL_RCC_GetClockSource\n
-  *         D2CCIP2R / CDCCIP2R      *     LL_RCC_GetClockSource\n
-  *         D3CCIPR  / SRDCCIPR      *     LL_RCC_GetClockSource
-  * @param  Periph This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_USART16_CLKSOURCE
-  *         @arg @ref LL_RCC_USART234578_CLKSOURCE
-  *         @arg @ref LL_RCC_I2C123_CLKSOURCE
-  *         @arg @ref LL_RCC_I2C4_CLKSOURCE
-  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE
-  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE
-  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE
-  *         @arg @ref LL_RCC_SAI1_CLKSOURCE
-  *         @arg @ref LL_RCC_SAI23_CLKSOURCE
-  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE (*)
-  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE (*)
-  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE (*)
-  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE (*)
-  *         @arg @ref LL_RCC_SPI123_CLKSOURCE (*)
-  *         @arg @ref LL_RCC_SPI45_CLKSOURCE (*)
-  *         @arg @ref LL_RCC_SPI6_CLKSOURCE (*)
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_USART16_CLKSOURCE_PCLK2
-  *         @arg @ref LL_RCC_USART16_CLKSOURCE_PLL2Q
-  *         @arg @ref LL_RCC_USART16_CLKSOURCE_PLL3Q
-  *         @arg @ref LL_RCC_USART16_CLKSOURCE_HSI
-  *         @arg @ref LL_RCC_USART16_CLKSOURCE_CSI
-  *         @arg @ref LL_RCC_USART16_CLKSOURCE_LSE
-  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PCLK1
-  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL2Q
-  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL3Q
-  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_HSI
-  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_CSI
-  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_LSE
-  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_PCLK1
-  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_PLL3R
-  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_HSI
-  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_CSI
-  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK4
-  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_PLL3R
-  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI
-  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_CSI
-  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
-  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P
-  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R
-  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
-  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
-  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP
-  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK4
-  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL2P
-  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL3R
-  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
-  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
-  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP
-  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PCLK4
-  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL2P
-  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL3R
-  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSE
-  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSI
-  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_CLKP
-  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q
-  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P
-  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P
-  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN
-  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP
-  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL1Q (*)
-  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL2P (*)
-  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL3P (*)
-  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_I2S_CKIN (*)
-  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_CLKP (*)
-  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL1Q (*)
-  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL2P (*)
-  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL3P (*)
-  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN (*)
-  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_CLKP (*)
-  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL1Q (*)
-  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL2P (*)
-  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL3P (*)
-  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN (*)
-  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_CLKP (*)
-  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL1Q (*)
-  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL2P (*)
-  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL3P (*)
-  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN (*)
-  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_CLKP (*)
-  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_SPDIF (*)
-  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL1Q (*)
-  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL2P (*)
-  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL3P (*)
-  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN (*)
-  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_CLKP (*)
-  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_SPDIF (*)
-  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL1Q
-  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL2P
-  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL3P
-  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_I2S_CKIN
-  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_CLKP
-  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PCLK2
-  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL2Q
-  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL3Q
-  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_HSI
-  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_CSI
-  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_HSE
-  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4
-  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q
-  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q
-  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI
-  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI
-  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE
-  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_I2S_CKIN (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetClockSource(uint32_t Periph)
-{
-#if defined(RCC_D1CCIPR_FMCSEL)
-  const uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&RCC->D1CCIPR) + LL_CLKSOURCE_REG(Periph)));
-#else
-  const uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&RCC->CDCCIPR) + LL_CLKSOURCE_REG(Periph)));
-#endif /* RCC_D1CCIPR_FMCSEL */
-  return (uint32_t) (Periph | (((READ_BIT(*pReg, LL_CLKSOURCE_MASK(Periph))) >> LL_CLKSOURCE_SHIFT(Periph)) << LL_RCC_CONFIG_SHIFT) );
-}
-
-/**
-  * @brief  Get USARTx clock source
-  * @rmtoll D2CCIP2R / CDCCIP2R      USART16SEL     LL_RCC_GetUSARTClockSource\n
-  *         D2CCIP2R / CDCCIP2R      USART28SEL     LL_RCC_GetUSARTClockSource
-  * @param  Periph This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_USART16_CLKSOURCE
-  *         @arg @ref LL_RCC_USART234578_CLKSOURCE
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_USART16_CLKSOURCE_PCLK2
-  *         @arg @ref LL_RCC_USART16_CLKSOURCE_PLL2Q
-  *         @arg @ref LL_RCC_USART16_CLKSOURCE_PLL3Q
-  *         @arg @ref LL_RCC_USART16_CLKSOURCE_HSI
-  *         @arg @ref LL_RCC_USART16_CLKSOURCE_CSI
-  *         @arg @ref LL_RCC_USART16_CLKSOURCE_LSE
-  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PCLK1
-  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL2Q
-  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL3Q
-  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_HSI
-  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_CSI
-  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_LSE
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t Periph)
-{
-  return LL_RCC_GetClockSource(Periph);
-}
-
-/**
-  * @brief  Get LPUART clock source
-  * @rmtoll D3CCIPR / SRDCCIPR       LPUART1SEL     LL_RCC_GetLPUARTClockSource
-  * @param  Periph This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK4
-  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL2Q
-  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL3Q
-  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
-  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_CSI
-  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t Periph)
-{
-  UNUSED(Periph);
-#if defined(RCC_D3CCIPR_LPUART1SEL)
-  return (uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL));
-#else
-  return (uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL));
-#endif  /* RCC_D3CCIPR_LPUART1SEL */
-}
-
-/**
-  * @brief  Get I2Cx clock source
-  * @rmtoll D2CCIP2R / CDCCIP2R     I2C123SEL       LL_RCC_GetI2CClockSource\n
-  *         D3CCIPR  / SRDCCIPR     I2C4SEL         LL_RCC_GetI2CClockSource
-  * @param  Periph This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_I2C123_CLKSOURCE
-  *         @arg @ref LL_RCC_I2C4_CLKSOURCE
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_PCLK1
-  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_PLL3R
-  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_HSI
-  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_CSI
-  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK4
-  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_PLL3R
-  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI
-  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_CSI
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t Periph)
-{
-  return LL_RCC_GetClockSource(Periph);
-}
-
-/**
-  * @brief  Get LPTIM clock source
-  * @rmtoll D2CCIP2R / CDCCIP2R      LPTIM1SEL     LL_RCC_GetLPTIMClockSource\n
-  *         D3CCIPR  / SRDCCIPR      LPTIM2SEL     LL_RCC_GetLPTIMClockSource\n
-  *         D3CCIPR  / SRDCCIPR      LPTIM345SEL   LL_RCC_GetLPTIMClockSource
-  * @param  Periph This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE
-  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE
-  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
-  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P
-  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R
-  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
-  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
-  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP
-  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK4
-  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL2P
-  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL3R
-  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
-  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
-  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP
-  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PCLK4
-  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL2P
-  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL3R
-  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSE
-  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSI
-  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_CLKP
-  * @retval None
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t Periph)
-{
-  return LL_RCC_GetClockSource(Periph);
-}
-
-/**
-  * @brief  Get SAIx clock source
-  * @rmtoll D2CCIP1R / CDCCIP1R     SAI1SEL       LL_RCC_GetSAIClockSource\n
-  *         D2CCIP1R / CDCCIP1R     SAI23SEL      LL_RCC_GetSAIClockSource
-  *         D3CCIPR  / SRDCCIPR     SAI4ASEL      LL_RCC_GetSAIClockSource\n
-  *         D3CCIPR  / SRDCCIPR     SAI4BSEL      LL_RCC_GetSAIClockSource
-  * @param  Periph This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_SAI1_CLKSOURCE    (*)
-  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE  (*)
-   *         @arg @ref LL_RCC_SAI2B_CLKSOURCE  (*)
-  *         @arg @ref LL_RCC_SAI23_CLKSOURCE   (*)
-  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE   (*)
-  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE   (*)
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q
-  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P
-  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P
-  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN
-  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP
-  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL1Q (*)
-  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL2P (*)
-  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL3P (*)
-  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_I2S_CKIN (*)
-  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_CLKP (*)
-  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL1Q (*)
-  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL2P (*)
-  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL3P (*)
-  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN (*)
-  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_CLKP (*)
-  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_SPDIF (*)
-  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL1Q (*)
-  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL2P (*)
-  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL3P (*)
-  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN (*)
-  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_CLKP (*)
-  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_SPDIF (*)
-  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL1Q (*)
-  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL2P (*)
-  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL3P (*)
-  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN (*)
-  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_CLKP (*)
-  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL1Q (*)
-  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL2P (*)
-  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL3P (*)
-  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN (*)
-  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_CLKP (*)
-  *
-  *  (*) value not defined in all devices.
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t Periph)
-{
-  return LL_RCC_GetClockSource(Periph);
-}
-
-/**
-  * @brief  Get SDMMC clock source
-  * @rmtoll D1CCIPR / CDCCIPR      SDMMCSEL      LL_RCC_GetSDMMCClockSource
-  * @param  Periph This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_SDMMC_CLKSOURCE
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_SDMMC_CLKSOURCE_PLL1Q
-  *         @arg @ref LL_RCC_SDMMC_CLKSOURCE_PLL2R
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetSDMMCClockSource(uint32_t Periph)
-{
-  UNUSED(Periph);
-#if defined(RCC_D1CCIPR_SDMMCSEL)
-  return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL));
-#else
-  return (uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL));
-#endif /* RCC_D1CCIPR_SDMMCSEL */
-}
-
-/**
-  * @brief  Get RNG clock source
-  * @rmtoll D2CCIP2R        RNGSEL      LL_RCC_GetRNGClockSource
-  * @param  Periph This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_RNG_CLKSOURCE
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48
-  *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLL1Q
-  *         @arg @ref LL_RCC_RNG_CLKSOURCE_LSE
-  *         @arg @ref LL_RCC_RNG_CLKSOURCE_LSI
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t Periph)
-{
-  UNUSED(Periph);
-#if defined(RCC_D2CCIP2R_RNGSEL)
-  return (uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL));
-#else
-  return (uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL));
-#endif /* RCC_D2CCIP2R_RNGSEL */
-}
-
-/**
-  * @brief  Get USB clock source
-  * @rmtoll D2CCIP2R / CDCCIP2R      USBSEL      LL_RCC_GetUSBClockSource
-  * @param  Periph This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_USB_CLKSOURCE
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_USB_CLKSOURCE_DISABLE
-  *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL1Q
-  *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL3Q
-  *         @arg @ref LL_RCC_USB_CLKSOURCE_HSI48
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t Periph)
-{
-  UNUSED(Periph);
-#if defined(RCC_D2CCIP2R_USBSEL)
-  return (uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL));
-#else
-  return (uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL));
-#endif /* RCC_D2CCIP2R_USBSEL */
-}
-
-/**
-  * @brief  Get CEC clock source
-  * @rmtoll D2CCIP2R / CDCCIP2R        CECSEL        LL_RCC_GetCECClockSource
-  * @param  Periph This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_CEC_CLKSOURCE
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
-  *         @arg @ref LL_RCC_CEC_CLKSOURCE_LSI
-  *         @arg @ref LL_RCC_CEC_CLKSOURCE_CSI_DIV122
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t Periph)
-{
-  UNUSED(Periph);
-#if defined(RCC_D2CCIP2R_CECSEL)
-  return (uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL));
-#else
-  return (uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_CECSEL));
-#endif  /* RCC_D2CCIP2R_CECSEL */
-}
-
-#if defined(DSI)
-/**
-  * @brief  Get DSI clock source
-  * @rmtoll D1CCIPR         DSISEL        LL_RCC_GetDSIClockSource
-  * @param  Periph This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_DSI_CLKSOURCE
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
-  *         @arg @ref LL_RCC_DSI_CLKSOURCE_PLL2Q
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetDSIClockSource(uint32_t Periph)
-{
-  UNUSED(Periph);
-  return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_DSISEL));
-}
-#endif /* DSI */
-
-/**
-  * @brief  Get DFSDM Kernel clock source
-  * @rmtoll D2CCIP1R / CDCCIP1R         DFSDM1SEL        LL_RCC_GetDFSDMClockSource
-  * @param  Periph This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
-  *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource(uint32_t Periph)
-{
-  UNUSED(Periph);
-#if defined(RCC_D2CCIP1R_DFSDM1SEL)
-  return (uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL));
-#else
-  return (uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL));
-#endif /* RCC_D2CCIP1R_DFSDM1SEL */
-}
-
-#if defined(DFSDM2_BASE)
-/**
-  * @brief  Get DFSDM2 Kernel clock source
-  * @rmtoll SRDCCIPR         DFSDM2SEL        LL_RCC_GetDFSDM2ClockSource
-  * @param  Periph This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_DFSDM2_CLKSOURCE
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_DFSDM2_CLKSOURCE_PCLK4
-  *         @arg @ref LL_RCC_DFSDM2_CLKSOURCE_SYSCLK
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetDFSDM2ClockSource(uint32_t Periph)
-{
-  UNUSED(Periph);
-  return (uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL));
-}
-#endif /* DFSDM2_BASE */
-
-/**
-  * @brief  Get FMC Kernel clock source
-  * @rmtoll D1CCIPR / D1CCIPR         FMCSEL        LL_RCC_GetFMCClockSource
-  * @param  Periph This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_FMC_CLKSOURCE
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_FMC_CLKSOURCE_HCLK
-  *         @arg @ref LL_RCC_FMC_CLKSOURCE_PLL1Q
-  *         @arg @ref LL_RCC_FMC_CLKSOURCE_PLL2R
-  *         @arg @ref LL_RCC_FMC_CLKSOURCE_CLKP
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetFMCClockSource(uint32_t Periph)
-{
-  UNUSED(Periph);
-#if defined(RCC_D1CCIPR_FMCSEL)
-  return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL));
-#else
-  return (uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL));
-#endif /* RCC_D1CCIPR_FMCSEL */
-}
-
-#if defined(QUADSPI)
-/**
-  * @brief  Get QSPI Kernel clock source
-  * @rmtoll D1CCIPR  /  CDCCIPR      QSPISEL        LL_RCC_GetQSPIClockSource
-  * @param  Periph This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_QSPI_CLKSOURCE
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_QSPI_CLKSOURCE_HCLK
-  *         @arg @ref LL_RCC_QSPI_CLKSOURCE_PLL1Q
-  *         @arg @ref LL_RCC_QSPI_CLKSOURCE_PLL2R
-  *         @arg @ref LL_RCC_QSPI_CLKSOURCE_CLKP
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetQSPIClockSource(uint32_t Periph)
-{
-  UNUSED(Periph);
-  return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL));
-}
-#endif /* QUADSPI */
-
-#if defined(OCTOSPI1) || defined(OCTOSPI2)
-/**
-  * @brief  Get OSPI Kernel clock source
-  * @rmtoll CDCCIPR      OSPISEL        LL_RCC_GetOSPIClockSource
-  * @param  Periph This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_OSPI_CLKSOURCE
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_OSPI_CLKSOURCE_HCLK
-  *         @arg @ref LL_RCC_OSPI_CLKSOURCE_PLL1Q
-  *         @arg @ref LL_RCC_OSPI_CLKSOURCE_PLL2R
-  *         @arg @ref LL_RCC_OSPI_CLKSOURCE_CLKP
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetOSPIClockSource(uint32_t Periph)
-{
-  UNUSED(Periph);
-#if defined(RCC_D1CCIPR_OCTOSPISEL)
-  return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_OCTOSPISEL));
-#else
-  return (uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL));
-#endif /* RCC_D1CCIPR_OCTOSPISEL */
-}
-#endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */
-
-/**
-  * @brief  Get CLKP Kernel clock source
-  * @rmtoll D1CCIPR /  CDCCIPR       CKPERSEL        LL_RCC_GetCLKPClockSource
-  * @param  Periph This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_CLKP_CLKSOURCE
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_CLKP_CLKSOURCE_HSI
-  *         @arg @ref LL_RCC_CLKP_CLKSOURCE_CSI
-  *         @arg @ref LL_RCC_CLKP_CLKSOURCE_HSE
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetCLKPClockSource(uint32_t Periph)
-{
-  UNUSED(Periph);
-#if defined(RCC_D1CCIPR_CKPERSEL)
-  return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL));
-#else
-  return (uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL));
-#endif /* RCC_D1CCIPR_CKPERSEL */
-}
-
-/**
-  * @brief  Get SPIx Kernel clock source
-  * @rmtoll D2CCIP1R / CDCCIP1R     SPI123SEL       LL_RCC_GetSPIClockSource\n
-  *         D2CCIP1R / CDCCIP1R     SPI45SEL        LL_RCC_GetSPIClockSource\n
-  *         D3CCIPR  / SRDCCIPR     SPI6SEL         LL_RCC_GetSPIClockSource
-  * @param  Periph This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_SPI123_CLKSOURCE
-  *         @arg @ref LL_RCC_SPI45_CLKSOURCE
-  *         @arg @ref LL_RCC_SPI6_CLKSOURCE
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL1Q
-  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL2P
-  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL3P
-  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_I2S_CKIN
-  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_CLKP
-  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PCLK2
-  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL2Q
-  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL3Q
-  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_HSI
-  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_CSI
-  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_HSE
-  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4
-  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q
-  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q
-  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI
-  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI
-  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE
-  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_I2S_CKIN (*)
-  *
-  *         (*) value not defined in all stm32h7xx lines.
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetSPIClockSource(uint32_t Periph)
-{
-  return LL_RCC_GetClockSource(Periph);
-}
-
-/**
-  * @brief  Get SPDIF Kernel clock source
-  * @rmtoll D2CCIP1R / CDCCIP1R      SPDIFSEL        LL_RCC_GetSPDIFClockSource
-  * @param  Periph This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_SPDIF_CLKSOURCE
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL1Q
-  *         @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL2R
-  *         @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL3R
-  *         @arg @ref LL_RCC_SPDIF_CLKSOURCE_HSI
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetSPDIFClockSource(uint32_t Periph)
-{
-  UNUSED(Periph);
-#if defined(RCC_D2CCIP1R_SPDIFSEL)
-  return (uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL));
-#else
-  return (uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL));
-#endif /* RCC_D2CCIP1R_SPDIFSEL */
-}
-
-/**
-  * @brief  Get FDCAN Kernel clock source
-  * @rmtoll D2CCIP1R / CDCCIP1R       FDCANSEL        LL_RCC_GetFDCANClockSource
-  * @param  Periph This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_FDCAN_CLKSOURCE
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE
-  *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL1Q
-  *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL2Q
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetFDCANClockSource(uint32_t Periph)
-{
-  UNUSED(Periph);
-#if defined(RCC_D2CCIP1R_FDCANSEL)
-  return (uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL));
-#else
-  return (uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_FDCANSEL));
-#endif /* RCC_D2CCIP1R_FDCANSEL */
-}
-
-/**
-  * @brief  Get SWP Kernel clock source
-  * @rmtoll D2CCIP1R / CDCCIP1R       SWPSEL        LL_RCC_GetSWPClockSource
-  * @param  Periph This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_SWP_CLKSOURCE
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_SWP_CLKSOURCE_PCLK1
-  *         @arg @ref LL_RCC_SWP_CLKSOURCE_HSI
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetSWPClockSource(uint32_t Periph)
-{
-  UNUSED(Periph);
-#if defined(RCC_D2CCIP1R_SWPSEL)
-  return (uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL));
-#else
-  return (uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL));
-#endif /* RCC_D2CCIP1R_SWPSEL */
-}
-
-/**
-  * @brief  Get ADC Kernel clock source
-  * @rmtoll D3CCIPR / SRDCCIPR       ADCSEL        LL_RCC_GetADCClockSource
-  * @param  Periph This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_ADC_CLKSOURCE
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_ADC_CLKSOURCE_PLL2P
-  *         @arg @ref LL_RCC_ADC_CLKSOURCE_PLL3R
-  *         @arg @ref LL_RCC_ADC_CLKSOURCE_CLKP
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t Periph)
-{
-  UNUSED(Periph);
-#if defined (RCC_D3CCIPR_ADCSEL)
-  return (uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL));
-#else
-  return (uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL));
-#endif /* RCC_D3CCIPR_ADCSEL */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EF_RTC RTC
-  * @{
-  */
-
-/**
-  * @brief  Set RTC Clock Source
-  * @note   Once the RTC clock source has been selected, it cannot be changed anymore unless
-  *         the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
-  *         set). The BDRST bit can be used to reset them.
-  * @rmtoll BDCR         RTCSEL        LL_RCC_SetRTCClockSource
-  * @param  Source This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
-  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
-  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
-  *         @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
-{
-  MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
-}
-
-/**
-  * @brief  Get RTC Clock Source
-  * @rmtoll BDCR         RTCSEL        LL_RCC_GetRTCClockSource
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
-  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
-  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
-  *         @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
-{
-  return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
-}
-
-/**
-  * @brief  Enable RTC
-  * @rmtoll BDCR         RTCEN         LL_RCC_EnableRTC
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_EnableRTC(void)
-{
-  SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
-}
-
-/**
-  * @brief  Disable RTC
-  * @rmtoll BDCR         RTCEN         LL_RCC_DisableRTC
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_DisableRTC(void)
-{
-  CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
-}
-
-/**
-  * @brief  Check if RTC has been enabled or not
-  * @rmtoll BDCR         RTCEN         LL_RCC_IsEnabledRTC
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
-{
-  return ((READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN))?1UL:0UL);
-}
-
-/**
-  * @brief  Force the Backup domain reset
-  * @rmtoll BDCR         BDRST / VSWRST         LL_RCC_ForceBackupDomainReset
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
-{
-  SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
-}
-
-/**
-  * @brief  Release the Backup domain reset
-  * @rmtoll BDCR         BDRST / VSWRST          LL_RCC_ReleaseBackupDomainReset
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
-{
-#if defined(RCC_BDCR_BDRST)
-  CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
-#else
-  CLEAR_BIT(RCC->BDCR, RCC_BDCR_VSWRST);
-#endif /* RCC_BDCR_BDRST */
-}
-
-/**
-  * @brief  Set HSE Prescalers for RTC Clock
-  * @rmtoll CFGR         RTCPRE        LL_RCC_SetRTC_HSEPrescaler
-  * @param  Prescaler This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_RTC_NOCLOCK
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_2
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_3
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_4
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_5
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_6
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_7
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_8
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_9
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_10
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_11
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_12
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_13
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_14
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_15
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_16
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_17
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_18
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_19
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_20
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_21
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_22
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_23
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_24
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_25
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_26
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_27
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_28
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_29
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_30
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_31
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_32
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_33
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_34
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_35
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_36
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_37
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_38
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_39
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_40
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_41
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_42
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_43
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_44
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_45
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_46
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_47
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_48
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_49
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_50
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_51
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_52
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_53
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_54
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_55
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_56
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_57
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_58
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_59
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_60
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_61
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_62
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_63
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler)
-{
-  MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, Prescaler);
-}
-
-/**
-  * @brief  Get HSE Prescalers for RTC Clock
-  * @rmtoll CFGR         RTCPRE        LL_RCC_GetRTC_HSEPrescaler
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_RTC_NOCLOCK
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_2
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_3
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_4
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_5
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_6
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_7
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_8
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_9
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_10
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_11
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_12
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_13
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_14
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_15
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_16
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_17
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_18
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_19
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_20
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_21
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_22
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_23
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_24
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_25
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_26
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_27
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_28
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_29
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_30
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_31
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_32
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_33
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_34
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_35
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_36
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_37
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_38
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_39
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_40
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_41
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_42
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_43
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_44
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_45
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_46
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_47
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_48
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_49
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_50
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_51
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_52
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_53
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_54
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_55
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_56
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_57
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_58
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_59
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_60
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_61
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_62
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_63
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void)
-{
-  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EF_TIM_CLOCK_PRESCALER TIM
-  * @{
-  */
-
-/**
-  * @brief  Set Timers Clock Prescalers
-  * @rmtoll CFGR         TIMPRE        LL_RCC_SetTIMPrescaler
-  * @param  Prescaler This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_TIM_PRESCALER_TWICE
-  *         @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetTIMPrescaler(uint32_t Prescaler)
-{
-  MODIFY_REG(RCC->CFGR, RCC_CFGR_TIMPRE, Prescaler);
-}
-
-/**
-  * @brief  Get Timers Clock Prescalers
-  * @rmtoll CFGR         TIMPRE        LL_RCC_GetTIMPrescaler
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_TIM_PRESCALER_TWICE
-  *         @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetTIMPrescaler(void)
-{
-  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_TIMPRE));
-}
-
-/**
-  * @}
-  */
-
-#if defined(HRTIM1)
-/** @defgroup RCC_LL_EF_HRTIM_SET_CLOCK_SOURCE HRTIM
-  * @{
-  */
-
-/**
-  * @brief  Set High Resolution Timers Clock Source
-  * @rmtoll CFGR         HRTIMSEL        LL_RCC_SetHRTIMClockSource
-  * @param  Prescaler This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_HRTIM_CLKSOURCE_TIM
-  *         @arg @ref LL_RCC_HRTIM_CLKSOURCE_CPU
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetHRTIMClockSource(uint32_t Prescaler)
-{
-  MODIFY_REG(RCC->CFGR, RCC_CFGR_HRTIMSEL, Prescaler);
-}
-#endif /* HRTIM1 */
-
-#if defined(HRTIM1)
-/**
-  * @brief  Get High Resolution Timers Clock Source
-  * @rmtoll CFGR         HRTIMSEL        LL_RCC_GetHRTIMClockSource
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_HRTIM_CLKSOURCE_TIM
-  *         @arg @ref LL_RCC_HRTIM_CLKSOURCE_CPU
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetHRTIMClockSource(void)
-{
-  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HRTIMSEL));
-}
-/**
-  * @}
-  */
-#endif /* HRTIM1 */
-
-/** @defgroup RCC_LL_EF_PLL PLL
-  * @{
-  */
-
-/**
-  * @brief  Set the oscillator used as PLL clock source.
-  * @note   PLLSRC can be written only when All PLLs are disabled.
-  * @rmtoll PLLCKSELR      PLLSRC        LL_RCC_PLL_SetSource
-  * @param  PLLSource parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLSOURCE_HSI
-  *         @arg @ref LL_RCC_PLLSOURCE_CSI
-  *         @arg @ref LL_RCC_PLLSOURCE_HSE
-  *         @arg @ref LL_RCC_PLLSOURCE_NONE
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL_SetSource(uint32_t PLLSource)
-{
-  MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC, PLLSource);
-}
-
-/**
-  * @brief  Get the oscillator used as PLL clock source.
-  * @rmtoll PLLCKSELR      PLLSRC        LL_RCC_PLL_GetSource
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_PLLSOURCE_HSI
-  *         @arg @ref LL_RCC_PLLSOURCE_CSI
-  *         @arg @ref LL_RCC_PLLSOURCE_HSE
-  *         @arg @ref LL_RCC_PLLSOURCE_NONE
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLL_GetSource(void)
-{
-  return (uint32_t)(READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC));
-}
-
-/**
-  * @brief  Enable PLL1
-  * @rmtoll CR           PLL1ON         LL_RCC_PLL1_Enable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL1_Enable(void)
-{
-  SET_BIT(RCC->CR, RCC_CR_PLL1ON);
-}
-
-/**
-  * @brief  Disable PLL1
-  * @note Cannot be disabled if the PLL1 clock is used as the system clock
-  * @rmtoll CR           PLL1ON         LL_RCC_PLL1_Disable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL1_Disable(void)
-{
-  CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON);
-}
-
-/**
-  * @brief  Check if PLL1 Ready
-  * @rmtoll CR           PLL1RDY        LL_RCC_PLL1_IsReady
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLL1_IsReady(void)
-{
-  return ((READ_BIT(RCC->CR, RCC_CR_PLL1RDY) == (RCC_CR_PLL1RDY))?1UL:0UL);
-}
-
-/**
-  * @brief  Enable PLL1P
-  * @note   This API shall be called only when PLL1 is disabled.
-  * @rmtoll PLLCFGR           DIVP1EN         LL_RCC_PLL1P_Enable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL1P_Enable(void)
-{
-  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP1EN);
-}
-
-/**
-  * @brief  Enable PLL1Q
-  * @note   This API shall be called only when PLL1 is disabled.
-  * @rmtoll PLLCFGR           DIVQ1EN         LL_RCC_PLL1Q_Enable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL1Q_Enable(void)
-{
-  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ1EN);
-}
-
-/**
-  * @brief  Enable PLL1R
-  * @note   This API shall be called only when PLL1 is disabled.
-  * @rmtoll PLLCFGR           DIVR1EN         LL_RCC_PLL1R_Enable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL1R_Enable(void)
-{
-  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR1EN);
-}
-
-/**
-  * @brief  Enable PLL1 FRACN
-  * @rmtoll PLLCFGR           PLL1FRACEN         LL_RCC_PLL1FRACN_Enable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL1FRACN_Enable(void)
-{
-  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN);
-}
-
-/**
-  * @brief  Check if PLL1 P is enabled
-  * @rmtoll PLLCFGR           DIVP1EN         LL_RCC_PLL1P_IsEnabled
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLL1P_IsEnabled(void)
-{
-  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP1EN) == RCC_PLLCFGR_DIVP1EN)?1UL:0UL);
-}
-
-/**
-  * @brief  Check if PLL1 Q is enabled
-  * @rmtoll PLLCFGR           DIVQ1EN         LL_RCC_PLL1Q_IsEnabled
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLL1Q_IsEnabled(void)
-{
-  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ1EN) == RCC_PLLCFGR_DIVQ1EN)?1UL:0UL);
-}
-
-/**
-  * @brief  Check if PLL1 R is enabled
-  * @rmtoll PLLCFGR           DIVR1EN         LL_RCC_PLL1R_IsEnabled
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLL1R_IsEnabled(void)
-{
-  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR1EN) == RCC_PLLCFGR_DIVR1EN)?1UL:0UL);
-}
-
-/**
-  * @brief  Check if PLL1 FRACN is enabled
-  * @rmtoll PLLCFGR           PLL1FRACEN         LL_RCC_PLL1FRACN_IsEnabled
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLL1FRACN_IsEnabled(void)
-{
-  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN) == RCC_PLLCFGR_PLL1FRACEN)?1UL:0UL);
-}
-
-/**
-  * @brief  Disable PLL1P
-  * @note   This API shall be called only when PLL1 is disabled.
-  * @rmtoll PLLCFGR           DIVP1EN         LL_RCC_PLL1P_Disable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL1P_Disable(void)
-{
-  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP1EN);
-}
-
-/**
-  * @brief  Disable PLL1Q
-  * @note   This API shall be called only when PLL1 is disabled.
-  * @rmtoll PLLCFGR           DIVQ1EN         LL_RCC_PLL1Q_Disable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL1Q_Disable(void)
-{
-  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ1EN);
-}
-
-/**
-  * @brief  Disable PLL1R
-  * @note   This API shall be called only when PLL1 is disabled.
-  * @rmtoll PLLCFGR           DIVR1EN         LL_RCC_PLL1R_Disable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL1R_Disable(void)
-{
-  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR1EN);
-}
-
-/**
-  * @brief  Disable PLL1 FRACN
-  * @rmtoll PLLCFGR           PLL1FRACEN         LL_RCC_PLL1FRACN_Enable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL1FRACN_Disable(void)
-{
-  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN);
-}
-
-/**
-  * @brief  Set PLL1 VCO OutputRange
-  * @note   This API shall be called only when PLL1 is disabled.
-  * @rmtoll PLLCFGR        PLL1VCOSEL       LL_RCC_PLL1_SetVCOOuputRange
-  * @param  VCORange This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLVCORANGE_WIDE
-  *         @arg @ref LL_RCC_PLLVCORANGE_MEDIUM
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL1_SetVCOOutputRange(uint32_t VCORange)
-{
-  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1VCOSEL, VCORange << RCC_PLLCFGR_PLL1VCOSEL_Pos);
-}
-
-/**
-  * @brief  Set PLL1 VCO Input Range
-  * @note   This API shall be called only when PLL1 is disabled.
-  * @rmtoll PLLCFGR        PLL1RGE       LL_RCC_PLL1_SetVCOInputRange
-  * @param  InputRange This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLINPUTRANGE_1_2
-  *         @arg @ref LL_RCC_PLLINPUTRANGE_2_4
-  *         @arg @ref LL_RCC_PLLINPUTRANGE_4_8
-  *         @arg @ref LL_RCC_PLLINPUTRANGE_8_16
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL1_SetVCOInputRange(uint32_t InputRange)
-{
-  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1RGE, InputRange << RCC_PLLCFGR_PLL1RGE_Pos);
-}
-
-/**
-  * @brief  Get PLL1 N Coefficient
-  * @rmtoll PLL1DIVR        N1          LL_RCC_PLL1_GetN
-  * @retval A value between 4 and 512
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLL1_GetN(void)
-{
-  return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_N1) >>  RCC_PLL1DIVR_N1_Pos) + 1UL);
-}
-
-/**
-  * @brief  Get PLL1 M Coefficient
-  * @rmtoll PLLCKSELR       DIVM1          LL_RCC_PLL1_GetM
-  * @retval A value between 0 and 63
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLL1_GetM(void)
-{
-  return (uint32_t)(READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM1) >>  RCC_PLLCKSELR_DIVM1_Pos);
-}
-
-/**
-  * @brief  Get PLL1 P Coefficient
-  * @rmtoll PLL1DIVR        P1          LL_RCC_PLL1_GetP
-  * @retval A value between 2 and 128
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLL1_GetP(void)
-{
-  return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_P1) >>  RCC_PLL1DIVR_P1_Pos) + 1UL);
-}
-
-/**
-  * @brief  Get PLL1 Q Coefficient
-  * @rmtoll PLL1DIVR        Q1          LL_RCC_PLL1_GetQ
-  * @retval A value between 1 and 128
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLL1_GetQ(void)
-{
-  return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_Q1) >>  RCC_PLL1DIVR_Q1_Pos) + 1UL);
-}
-
-/**
-  * @brief  Get PLL1 R Coefficient
-  * @rmtoll PLL1DIVR        R1          LL_RCC_PLL1_GetR
-  * @retval A value between 1 and 128
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLL1_GetR(void)
-{
-  return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_R1) >>  RCC_PLL1DIVR_R1_Pos) + 1UL);
-}
-
-/**
-  * @brief  Get PLL1 FRACN Coefficient
-  * @rmtoll PLL1FRACR      FRACN1          LL_RCC_PLL1_GetFRACN
-  * @retval A value between 0 and 8191 (0x1FFF)
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLL1_GetFRACN(void)
-{
-  return (uint32_t)(READ_BIT(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACN1) >>  RCC_PLL1FRACR_FRACN1_Pos);
-}
-
-/**
-  * @brief  Set PLL1 N Coefficient
-  * @note   This API shall be called only when PLL1 is disabled.
-  * @rmtoll PLL1DIVR        N1          LL_RCC_PLL1_SetN
-  * @param  N parameter can be a value between 4 and 512
-  */
-__STATIC_INLINE void LL_RCC_PLL1_SetN(uint32_t N)
-{
-  MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_N1, (N-1UL) << RCC_PLL1DIVR_N1_Pos);
-}
-
-/**
-  * @brief  Set PLL1 M Coefficient
-  * @note   This API shall be called only when PLL1 is disabled.
-  * @rmtoll PLLCKSELR       DIVM1          LL_RCC_PLL1_SetM
-  * @param  M parameter can be a value between 0 and 63
-  */
-__STATIC_INLINE void LL_RCC_PLL1_SetM(uint32_t M)
-{
-  MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM1, M << RCC_PLLCKSELR_DIVM1_Pos);
-}
-
-/**
-  * @brief  Set PLL1 P Coefficient
-  * @note   This API shall be called only when PLL1 is disabled.
-  * @rmtoll PLL1DIVR        P1          LL_RCC_PLL1_SetP
-  * @param  P parameter can be a value between 2 (or 1*) and 128 (ODD division factor not supported)
-  *
-  * (*) : For stm32h72xxx and stm32h73xxx family lines.
-  */
-__STATIC_INLINE void LL_RCC_PLL1_SetP(uint32_t P)
-{
-  MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_P1, (P-1UL) << RCC_PLL1DIVR_P1_Pos);
-}
-
-/**
-  * @brief  Set PLL1 Q Coefficient
-  * @note   This API shall be called only when PLL1 is disabled.
-  * @rmtoll PLL1DIVR        Q1          LL_RCC_PLL1_SetQ
-  * @param  Q parameter can be a value between 1 and 128
-  */
-__STATIC_INLINE void LL_RCC_PLL1_SetQ(uint32_t Q)
-{
-  MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_Q1, (Q-1UL) << RCC_PLL1DIVR_Q1_Pos);
-}
-
-/**
-  * @brief  Set PLL1 R Coefficient
-  * @note   This API shall be called only when PLL1 is disabled.
-  * @rmtoll PLL1DIVR        R1          LL_RCC_PLL1_SetR
-  * @param  R parameter can be a value between 1 and 128
-  */
-__STATIC_INLINE void LL_RCC_PLL1_SetR(uint32_t R)
-{
-  MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_R1, (R-1UL) << RCC_PLL1DIVR_R1_Pos);
-}
-
-/**
-  * @brief  Set PLL1 FRACN Coefficient
-  * @rmtoll PLL1FRACR        FRACN1          LL_RCC_PLL1_SetFRACN
-  * @param  FRACN parameter can be a value between 0 and 8191 (0x1FFF)
-  */
-__STATIC_INLINE void LL_RCC_PLL1_SetFRACN(uint32_t FRACN)
-{
-  MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACN1, FRACN << RCC_PLL1FRACR_FRACN1_Pos);
-}
-
-/**
-  * @brief  Enable PLL2
-  * @rmtoll CR           PLL2ON         LL_RCC_PLL2_Enable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL2_Enable(void)
-{
-  SET_BIT(RCC->CR, RCC_CR_PLL2ON);
-}
-
-/**
-  * @brief  Disable PLL2
-  * @note Cannot be disabled if the PLL2 clock is used as the system clock
-  * @rmtoll CR           PLL2ON         LL_RCC_PLL2_Disable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL2_Disable(void)
-{
-  CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON);
-}
-
-/**
-  * @brief  Check if PLL2 Ready
-  * @rmtoll CR           PLL2RDY        LL_RCC_PLL2_IsReady
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLL2_IsReady(void)
-{
-  return ((READ_BIT(RCC->CR, RCC_CR_PLL2RDY) == (RCC_CR_PLL2RDY))?1UL:0UL);
-}
-
-/**
-  * @brief  Enable PLL2P
-  * @note   This API shall be called only when PLL2 is disabled.
-  * @rmtoll PLLCFGR           DIVP2EN         LL_RCC_PLL2P_Enable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL2P_Enable(void)
-{
-  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP2EN);
-}
-
-/**
-  * @brief  Enable PLL2Q
-  * @note   This API shall be called only when PLL2 is disabled.
-  * @rmtoll PLLCFGR           DIVQ2EN         LL_RCC_PLL2Q_Enable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL2Q_Enable(void)
-{
-  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ2EN);
-}
-
-/**
-  * @brief  Enable PLL2R
-  * @note   This API shall be called only when PLL2 is disabled.
-  * @rmtoll PLLCFGR           DIVR2EN         LL_RCC_PLL2R_Enable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL2R_Enable(void)
-{
-  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR2EN);
-}
-
-/**
-  * @brief  Enable PLL2 FRACN
-  * @rmtoll PLLCFGR           PLL2FRACEN         LL_RCC_PLL2FRACN_Enable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL2FRACN_Enable(void)
-{
-  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN);
-}
-
-/**
-  * @brief  Check if PLL2 P is enabled
-  * @rmtoll PLLCFGR           DIVP2EN         LL_RCC_PLL2P_IsEnabled
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLL2P_IsEnabled(void)
-{
-  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP2EN) == RCC_PLLCFGR_DIVP2EN)?1UL:0UL);
-}
-
-/**
-  * @brief  Check if PLL2 Q is enabled
-  * @rmtoll PLLCFGR           DIVQ2EN         LL_RCC_PLL2Q_IsEnabled
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLL2Q_IsEnabled(void)
-{
-  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ2EN) == RCC_PLLCFGR_DIVQ2EN)?1UL:0UL);
-}
-
-/**
-  * @brief  Check if PLL2 R is enabled
-  * @rmtoll PLLCFGR           DIVR2EN         LL_RCC_PLL2R_IsEnabled
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLL2R_IsEnabled(void)
-{
-  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR2EN) == RCC_PLLCFGR_DIVR2EN)?1UL:0UL);
-}
-
-/**
-  * @brief  Check if PLL2 FRACN is enabled
-  * @rmtoll PLLCFGR           PLL2FRACEN         LL_RCC_PLL2FRACN_IsEnabled
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLL2FRACN_IsEnabled(void)
-{
-  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN) == RCC_PLLCFGR_PLL2FRACEN)?1UL:0UL);
-}
-
-/**
-  * @brief  Disable PLL2P
-  * @note   This API shall be called only when PLL2 is disabled.
-  * @rmtoll PLLCFGR           DIVP2EN         LL_RCC_PLL2P_Disable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL2P_Disable(void)
-{
-  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP2EN);
-}
-
-/**
-  * @brief  Disable PLL2Q
-  * @note   This API shall be called only when PLL2 is disabled.
-  * @rmtoll PLLCFGR           DIVQ2EN         LL_RCC_PLL2Q_Disable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL2Q_Disable(void)
-{
-  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ2EN);
-}
-
-/**
-  * @brief  Disable PLL2R
-  * @note   This API shall be called only when PLL2 is disabled.
-  * @rmtoll PLLCFGR           DIVR2EN         LL_RCC_PLL2R_Disable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL2R_Disable(void)
-{
-  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR2EN);
-}
-
-/**
-  * @brief  Disable PLL2 FRACN
-  * @rmtoll PLLCFGR           PLL2FRACEN         LL_RCC_PLL2FRACN_Enable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL2FRACN_Disable(void)
-{
-  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN);
-}
-
-/**
-  * @brief  Set PLL2 VCO OutputRange
-  * @note   This API shall be called only when PLL2 is disabled.
-  * @rmtoll PLLCFGR        PLL2VCOSEL       LL_RCC_PLL2_SetVCOOuputRange
-  * @param  VCORange This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLVCORANGE_WIDE
-  *         @arg @ref LL_RCC_PLLVCORANGE_MEDIUM
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL2_SetVCOOutputRange(uint32_t VCORange)
-{
-  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2VCOSEL, VCORange << RCC_PLLCFGR_PLL2VCOSEL_Pos);
-}
-
-/**
-  * @brief  Set PLL2 VCO Input Range
-  * @note   This API shall be called only when PLL2 is disabled.
-  * @rmtoll PLLCFGR        PLL2RGE       LL_RCC_PLL2_SetVCOInputRange
-  * @param  InputRange This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLINPUTRANGE_1_2
-  *         @arg @ref LL_RCC_PLLINPUTRANGE_2_4
-  *         @arg @ref LL_RCC_PLLINPUTRANGE_4_8
-  *         @arg @ref LL_RCC_PLLINPUTRANGE_8_16
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL2_SetVCOInputRange(uint32_t InputRange)
-{
-  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2RGE, InputRange << RCC_PLLCFGR_PLL2RGE_Pos);
-}
-
-/**
-  * @brief  Get PLL2 N Coefficient
-  * @rmtoll PLL2DIVR        N2          LL_RCC_PLL2_GetN
-  * @retval A value between 4 and 512
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLL2_GetN(void)
-{
-  return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_N2) >>  RCC_PLL2DIVR_N2_Pos) + 1UL);
-}
-
-/**
-  * @brief  Get PLL2 M Coefficient
-  * @rmtoll PLLCKSELR       DIVM2          LL_RCC_PLL2_GetM
-  * @retval A value between 0 and 63
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLL2_GetM(void)
-{
-  return (uint32_t)(READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM2) >>  RCC_PLLCKSELR_DIVM2_Pos);
-}
-
-/**
-  * @brief  Get PLL2 P Coefficient
-  * @rmtoll PLL2DIVR        P2          LL_RCC_PLL2_GetP
-  * @retval A value between 1 and 128
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLL2_GetP(void)
-{
-  return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_P2) >>  RCC_PLL2DIVR_P2_Pos) + 1UL);
-}
-
-/**
-  * @brief  Get PLL2 Q Coefficient
-  * @rmtoll PLL2DIVR        Q2          LL_RCC_PLL2_GetQ
-  * @retval A value between 1 and 128
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLL2_GetQ(void)
-{
-  return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_Q2) >>  RCC_PLL2DIVR_Q2_Pos) + 1UL);
-}
-
-/**
-  * @brief  Get PLL2 R Coefficient
-  * @rmtoll PLL2DIVR        R2          LL_RCC_PLL2_GetR
-  * @retval A value between 1 and 128
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLL2_GetR(void)
-{
-  return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_R2) >>  RCC_PLL2DIVR_R2_Pos) + 1UL);
-}
-
-/**
-  * @brief  Get PLL2 FRACN Coefficient
-  * @rmtoll PLL2FRACR      FRACN2          LL_RCC_PLL2_GetFRACN
-  * @retval A value between 0 and 8191 (0x1FFF)
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLL2_GetFRACN(void)
-{
-  return (uint32_t)(READ_BIT(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN2) >>  RCC_PLL2FRACR_FRACN2_Pos);
-}
-
-/**
-  * @brief  Set PLL2 N Coefficient
-  * @note   This API shall be called only when PLL2 is disabled.
-  * @rmtoll PLL2DIVR        N2          LL_RCC_PLL2_SetN
-  * @param  N parameter can be a value between 4 and 512
-  */
-__STATIC_INLINE void LL_RCC_PLL2_SetN(uint32_t N)
-{
-  MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_N2, (N-1UL) << RCC_PLL2DIVR_N2_Pos);
-}
-
-/**
-  * @brief  Set PLL2 M Coefficient
-  * @note   This API shall be called only when PLL2 is disabled.
-  * @rmtoll PLLCKSELR       DIVM2          LL_RCC_PLL2_SetM
-  * @param  M parameter can be a value between 0 and 63
-  */
-__STATIC_INLINE void LL_RCC_PLL2_SetM(uint32_t M)
-{
-  MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM2, M << RCC_PLLCKSELR_DIVM2_Pos);
-}
-
-/**
-  * @brief  Set PLL2 P Coefficient
-  * @note   This API shall be called only when PLL2 is disabled.
-  * @rmtoll PLL2DIVR        P2          LL_RCC_PLL2_SetP
-  * @param  P parameter can be a value between 1 and 128
-  */
-__STATIC_INLINE void LL_RCC_PLL2_SetP(uint32_t P)
-{
-  MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_P2, (P-1UL) << RCC_PLL2DIVR_P2_Pos);
-}
-
-/**
-  * @brief  Set PLL2 Q Coefficient
-  * @note   This API shall be called only when PLL2 is disabled.
-  * @rmtoll PLL2DIVR        Q2          LL_RCC_PLL2_SetQ
-  * @param  Q parameter can be a value between 1 and 128
-  */
-__STATIC_INLINE void LL_RCC_PLL2_SetQ(uint32_t Q)
-{
-  MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_Q2, (Q-1UL) << RCC_PLL2DIVR_Q2_Pos);
-}
-
-/**
-  * @brief  Set PLL2 R Coefficient
-  * @note   This API shall be called only when PLL2 is disabled.
-  * @rmtoll PLL2DIVR        R2          LL_RCC_PLL2_SetR
-  * @param  R parameter can be a value between 1 and 128
-  */
-__STATIC_INLINE void LL_RCC_PLL2_SetR(uint32_t R)
-{
-  MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_R2, (R-1UL) << RCC_PLL2DIVR_R2_Pos);
-}
-
-/**
-  * @brief  Set PLL2 FRACN Coefficient
-  * @rmtoll PLL2FRACR        FRACN2          LL_RCC_PLL2_SetFRACN
-  * @param  FRACN parameter can be a value between 0 and 8191 (0x1FFF)
-  */
-__STATIC_INLINE void LL_RCC_PLL2_SetFRACN(uint32_t FRACN)
-{
-  MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN2, FRACN << RCC_PLL2FRACR_FRACN2_Pos);
-}
-
-/**
-  * @brief  Enable PLL3
-  * @rmtoll CR           PLL3ON         LL_RCC_PLL3_Enable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL3_Enable(void)
-{
-  SET_BIT(RCC->CR, RCC_CR_PLL3ON);
-}
-
-/**
-  * @brief  Disable PLL3
-  * @note Cannot be disabled if the PLL3 clock is used as the system clock
-  * @rmtoll CR           PLL3ON         LL_RCC_PLL3_Disable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL3_Disable(void)
-{
-  CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON);
-}
-
-/**
-  * @brief  Check if PLL3 Ready
-  * @rmtoll CR           PLL3RDY        LL_RCC_PLL3_IsReady
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLL3_IsReady(void)
-{
-  return ((READ_BIT(RCC->CR, RCC_CR_PLL3RDY) == (RCC_CR_PLL3RDY))?1UL:0UL);
-}
-
-/**
-  * @brief  Enable PLL3P
-  * @note   This API shall be called only when PLL3 is disabled.
-  * @rmtoll PLLCFGR           DIVP3EN         LL_RCC_PLL3P_Enable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL3P_Enable(void)
-{
-  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP3EN);
-}
-
-/**
-  * @brief  Enable PLL3Q
-  * @note   This API shall be called only when PLL3 is disabled.
-  * @rmtoll PLLCFGR           DIVQ3EN         LL_RCC_PLL3Q_Enable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL3Q_Enable(void)
-{
-  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ3EN);
-}
-
-/**
-  * @brief  Enable PLL3R
-  * @note   This API shall be called only when PLL3 is disabled.
-  * @rmtoll PLLCFGR           DIVR3EN         LL_RCC_PLL3R_Enable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL3R_Enable(void)
-{
-  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR3EN);
-}
-
-/**
-  * @brief  Enable PLL3 FRACN
-  * @rmtoll PLLCFGR           PLL3FRACEN         LL_RCC_PLL3FRACN_Enable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL3FRACN_Enable(void)
-{
-  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN);
-}
-
-/**
-  * @brief  Check if PLL3 P is enabled
-  * @rmtoll PLLCFGR           DIVP3EN         LL_RCC_PLL3P_IsEnabled
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLL3P_IsEnabled(void)
-{
-  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP3EN) == RCC_PLLCFGR_DIVP3EN)?1UL:0UL);
-}
-
-/**
-  * @brief  Check if PLL3 Q is enabled
-  * @rmtoll PLLCFGR           DIVQ3EN         LL_RCC_PLL3Q_IsEnabled
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLL3Q_IsEnabled(void)
-{
-  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ3EN) == RCC_PLLCFGR_DIVQ3EN)?1UL:0UL);
-}
-
-/**
-  * @brief  Check if PLL3 R is enabled
-  * @rmtoll PLLCFGR           DIVR3EN         LL_RCC_PLL3R_IsEnabled
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLL3R_IsEnabled(void)
-{
-  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR3EN) == RCC_PLLCFGR_DIVR3EN)?1UL:0UL);
-}
-
-/**
-  * @brief  Check if PLL3 FRACN is enabled
-  * @rmtoll PLLCFGR           PLL3FRACEN         LL_RCC_PLL3FRACN_IsEnabled
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLL3FRACN_IsEnabled(void)
-{
-  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN) == RCC_PLLCFGR_PLL3FRACEN)?1UL:0UL);
-}
-
-/**
-  * @brief  Disable PLL3P
-  * @note   This API shall be called only when PLL3 is disabled.
-  * @rmtoll PLLCFGR           DIVP2EN         LL_RCC_PLL3P_Disable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL3P_Disable(void)
-{
-  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP3EN);
-}
-
-/**
-  * @brief  Disable PLL3Q
-  * @note   This API shall be called only when PLL3 is disabled.
-  * @rmtoll PLLCFGR           DIVQ3EN         LL_RCC_PLL3Q_Disable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL3Q_Disable(void)
-{
-  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ3EN);
-}
-
-/**
-  * @brief  Disable PLL3R
-  * @note   This API shall be called only when PLL3 is disabled.
-  * @rmtoll PLLCFGR           DIVR3EN         LL_RCC_PLL3R_Disable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL3R_Disable(void)
-{
-  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR3EN);
-}
-
-/**
-  * @brief  Disable PLL3 FRACN
-  * @rmtoll PLLCFGR           PLL3FRACEN         LL_RCC_PLL3FRACN_Enable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL3FRACN_Disable(void)
-{
-  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN);
-}
-
-/**
-  * @brief  Set PLL3 VCO OutputRange
-  * @note   This API shall be called only when PLL3 is disabled.
-  * @rmtoll PLLCFGR        PLL3VCOSEL       LL_RCC_PLL3_SetVCOOuputRange
-  * @param  VCORange This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLVCORANGE_WIDE
-  *         @arg @ref LL_RCC_PLLVCORANGE_MEDIUM
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL3_SetVCOOutputRange(uint32_t VCORange)
-{
-  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3VCOSEL, VCORange << RCC_PLLCFGR_PLL3VCOSEL_Pos);
-}
-
-/**
-  * @brief  Set PLL3 VCO Input Range
-  * @note   This API shall be called only when PLL3 is disabled.
-  * @rmtoll PLLCFGR        PLL3RGE       LL_RCC_PLL3_SetVCOInputRange
-  * @param  InputRange This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLINPUTRANGE_1_2
-  *         @arg @ref LL_RCC_PLLINPUTRANGE_2_4
-  *         @arg @ref LL_RCC_PLLINPUTRANGE_4_8
-  *         @arg @ref LL_RCC_PLLINPUTRANGE_8_16
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL3_SetVCOInputRange(uint32_t InputRange)
-{
-  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3RGE, InputRange << RCC_PLLCFGR_PLL3RGE_Pos);
-}
-
-/**
-  * @brief  Get PLL3 N Coefficient
-  * @rmtoll PLL3DIVR        N3          LL_RCC_PLL3_GetN
-  * @retval A value between 4 and 512
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLL3_GetN(void)
-{
-  return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_N3) >>  RCC_PLL3DIVR_N3_Pos) + 1UL);
-}
-
-/**
-  * @brief  Get PLL3 M Coefficient
-  * @rmtoll PLLCKSELR       DIVM3          LL_RCC_PLL3_GetM
-  * @retval A value between 0 and 63
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLL3_GetM(void)
-{
-  return (uint32_t)(READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM3) >>  RCC_PLLCKSELR_DIVM3_Pos);
-}
-
-/**
-  * @brief  Get PLL3 P Coefficient
-  * @rmtoll PLL3DIVR        P3          LL_RCC_PLL3_GetP
-  * @retval A value between 1 and 128
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLL3_GetP(void)
-{
-  return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_P3) >>  RCC_PLL3DIVR_P3_Pos) + 1UL);
-}
-
-/**
-  * @brief  Get PLL3 Q Coefficient
-  * @rmtoll PLL3DIVR        Q3          LL_RCC_PLL3_GetQ
-  * @retval A value between 1 and 128
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLL3_GetQ(void)
-{
-  return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_Q3) >>  RCC_PLL3DIVR_Q3_Pos) + 1UL);
-}
-
-/**
-  * @brief  Get PLL3 R Coefficient
-  * @rmtoll PLL3DIVR        R3          LL_RCC_PLL3_GetR
-  * @retval A value between 1 and 128
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLL3_GetR(void)
-{
-  return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_R3) >>  RCC_PLL3DIVR_R3_Pos) + 1UL);
-}
-
-/**
-  * @brief  Get PLL3 FRACN Coefficient
-  * @rmtoll PLL3FRACR      FRACN3          LL_RCC_PLL3_GetFRACN
-  * @retval A value between 0 and 8191 (0x1FFF)
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLL3_GetFRACN(void)
-{
-  return (uint32_t)(READ_BIT(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3) >>  RCC_PLL3FRACR_FRACN3_Pos);
-}
-
-/**
-  * @brief  Set PLL3 N Coefficient
-  * @note   This API shall be called only when PLL3 is disabled.
-  * @rmtoll PLL3DIVR        N3          LL_RCC_PLL3_SetN
-  * @param  N parameter can be a value between 4 and 512
-  */
-__STATIC_INLINE void LL_RCC_PLL3_SetN(uint32_t N)
-{
-  MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_N3, (N-1UL) << RCC_PLL3DIVR_N3_Pos);
-}
-
-/**
-  * @brief  Set PLL3 M Coefficient
-  * @note   This API shall be called only when PLL3 is disabled.
-  * @rmtoll PLLCKSELR       DIVM3          LL_RCC_PLL3_SetM
-  * @param  M parameter can be a value between 0 and 63
-  */
-__STATIC_INLINE void LL_RCC_PLL3_SetM(uint32_t M)
-{
-  MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM3, M << RCC_PLLCKSELR_DIVM3_Pos);
-}
-
-/**
-  * @brief  Set PLL3 P Coefficient
-  * @note   This API shall be called only when PLL3 is disabled.
-  * @rmtoll PLL3DIVR        P3          LL_RCC_PLL3_SetP
-  * @param  P parameter can be a value between 1 and 128
-  */
-__STATIC_INLINE void LL_RCC_PLL3_SetP(uint32_t P)
-{
-  MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_P3, (P-1UL) << RCC_PLL3DIVR_P3_Pos);
-}
-
-/**
-  * @brief  Set PLL3 Q Coefficient
-  * @note   This API shall be called only when PLL3 is disabled.
-  * @rmtoll PLL3DIVR        Q3          LL_RCC_PLL3_SetQ
-  * @param  Q parameter can be a value between 1 and 128
-  */
-__STATIC_INLINE void LL_RCC_PLL3_SetQ(uint32_t Q)
-{
-  MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_Q3, (Q-1UL) << RCC_PLL3DIVR_Q3_Pos);
-}
-
-/**
-  * @brief  Set PLL3 R Coefficient
-  * @note   This API shall be called only when PLL3 is disabled.
-  * @rmtoll PLL3DIVR        R3          LL_RCC_PLL3_SetR
-  * @param  R parameter can be a value between 1 and 128
-  */
-__STATIC_INLINE void LL_RCC_PLL3_SetR(uint32_t R)
-{
-  MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_R3, (R-1UL) << RCC_PLL3DIVR_R3_Pos);
-}
-
-/**
-  * @brief  Set PLL3 FRACN Coefficient
-  * @rmtoll PLL3FRACR        FRACN3          LL_RCC_PLL3_SetFRACN
-  * @param  FRACN parameter can be a value between 0 and 8191 (0x1FFF)
-  */
-__STATIC_INLINE void LL_RCC_PLL3_SetFRACN(uint32_t FRACN)
-{
-  MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3, FRACN << RCC_PLL3FRACR_FRACN3_Pos);
-}
-
-
-/**
-  * @}
-  */
-
-
-/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
-  * @{
-  */
-
-/**
-  * @brief  Clear LSI ready interrupt flag
-  * @rmtoll CICR         LSIRDYC       LL_RCC_ClearFlag_LSIRDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
-{
-  SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC);
-}
-
-/**
-  * @brief  Clear LSE ready interrupt flag
-  * @rmtoll CICR         LSERDYC       LL_RCC_ClearFlag_LSERDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
-{
-  SET_BIT(RCC->CICR, RCC_CICR_LSERDYC);
-}
-
-/**
-  * @brief  Clear HSI ready interrupt flag
-  * @rmtoll CICR         HSIRDYC       LL_RCC_ClearFlag_HSIRDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
-{
-  SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC);
-}
-
-/**
-  * @brief  Clear HSE ready interrupt flag
-  * @rmtoll CICR         HSERDYC       LL_RCC_ClearFlag_HSERDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
-{
-  SET_BIT(RCC->CICR, RCC_CICR_HSERDYC);
-}
-
-/**
-  * @brief  Clear CSI ready interrupt flag
-  * @rmtoll CICR         CSIRDYC       LL_RCC_ClearFlag_CSIRDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_ClearFlag_CSIRDY(void)
-{
-  SET_BIT(RCC->CICR, RCC_CICR_CSIRDYC);
-}
-
-/**
-  * @brief  Clear HSI48 ready interrupt flag
-  * @rmtoll CICR         HSI48RDYC       LL_RCC_ClearFlag_HSI48RDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void)
-{
-  SET_BIT(RCC->CICR, RCC_CICR_HSI48RDYC);
-}
-
-/**
-  * @brief  Clear PLL1 ready interrupt flag
-  * @rmtoll CICR         PLL1RDYC       LL_RCC_ClearFlag_PLL1RDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_ClearFlag_PLL1RDY(void)
-{
-  SET_BIT(RCC->CICR, RCC_CICR_PLLRDYC);
-}
-
-/**
-  * @brief  Clear PLL2 ready interrupt flag
-  * @rmtoll CICR         PLL2RDYC       LL_RCC_ClearFlag_PLL2RDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_ClearFlag_PLL2RDY(void)
-{
-  SET_BIT(RCC->CICR, RCC_CICR_PLL2RDYC);
-}
-
-/**
-  * @brief  Clear PLL3 ready interrupt flag
-  * @rmtoll CICR         PLL3RDYC       LL_RCC_ClearFlag_PLL3RDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_ClearFlag_PLL3RDY(void)
-{
-  SET_BIT(RCC->CICR, RCC_CICR_PLL3RDYC);
-}
-
-/**
-  * @brief  Clear LSE Clock security system interrupt flag
-  * @rmtoll CICR         LSECSSC         LL_RCC_ClearFlag_LSECSS
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void)
-{
-  SET_BIT(RCC->CICR, RCC_CICR_LSECSSC);
-}
-
-/**
-  * @brief  Clear HSE Clock security system interrupt flag
-  * @rmtoll CICR         HSECSSC         LL_RCC_ClearFlag_HSECSS
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
-{
-  SET_BIT(RCC->CICR, RCC_CICR_HSECSSC);
-}
-
-/**
-  * @brief  Check if LSI ready interrupt occurred or not
-  * @rmtoll CIFR         LSIRDYF       LL_RCC_IsActiveFlag_LSIRDY
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
-{
-  return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == (RCC_CIFR_LSIRDYF))?1UL:0UL);
-}
-
-/**
-  * @brief  Check if LSE ready interrupt occurred or not
-  * @rmtoll CIFR         LSERDYF       LL_RCC_IsActiveFlag_LSERDY
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
-{
-  return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == (RCC_CIFR_LSERDYF))?1UL:0UL);
-}
-
-/**
-  * @brief  Check if HSI ready interrupt occurred or not
-  * @rmtoll CIFR         HSIRDYF       LL_RCC_IsActiveFlag_HSIRDY
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
-{
-  return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == (RCC_CIFR_HSIRDYF))?1UL:0UL);
-}
-
-/**
-  * @brief  Check if HSE ready interrupt occurred or not
-  * @rmtoll CIFR         HSERDYF       LL_RCC_IsActiveFlag_HSERDY
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
-{
-  return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == (RCC_CIFR_HSERDYF))?1UL:0UL);
-}
-
-/**
-  * @brief  Check if CSI ready interrupt occurred or not
-  * @rmtoll CIFR         CSIRDYF       LL_RCC_IsActiveFlag_CSIRDY
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CSIRDY(void)
-{
-  return ((READ_BIT(RCC->CIFR, RCC_CIFR_CSIRDYF) == (RCC_CIFR_CSIRDYF))?1UL:0UL);
-}
-
-/**
-  * @brief  Check if HSI48 ready interrupt occurred or not
-  * @rmtoll CIFR         HSI48RDYF       LL_RCC_IsActiveFlag_HSI48RDY
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void)
-{
-  return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == (RCC_CIFR_HSI48RDYF))?1UL:0UL);
-}
-
-/**
-  * @brief  Check if PLL1 ready interrupt occurred or not
-  * @rmtoll CIFR         PLLRDYF       LL_RCC_IsActiveFlag_PLL1RDY
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL1RDY(void)
-{
-  return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLRDYF) == (RCC_CIFR_PLLRDYF))?1UL:0UL);
-}
-
-/**
-  * @brief  Check if PLL2 ready interrupt occurred or not
-  * @rmtoll CIFR         PLL2RDYF       LL_RCC_IsActiveFlag_PLL2RDY
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL2RDY(void)
-{
-  return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL2RDYF) == (RCC_CIFR_PLL2RDYF))?1UL:0UL);
-}
-
-/**
-  * @brief  Check if PLL3 ready interrupt occurred or not
-  * @rmtoll CIFR         PLL3RDYF       LL_RCC_IsActiveFlag_PLL3RDY
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL3RDY(void)
-{
-  return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL3RDYF) == (RCC_CIFR_PLL3RDYF))?1UL:0UL);
-}
-
-/**
-  * @brief  Check if LSE Clock security system interrupt occurred or not
-  * @rmtoll CIFR         LSECSSF          LL_RCC_IsActiveFlag_LSECSS
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void)
-{
-  return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == (RCC_CIFR_LSECSSF))?1UL:0UL);
-}
-
-/**
-  * @brief  Check if HSE Clock security system interrupt occurred or not
-  * @rmtoll CIFR         HSECSSF          LL_RCC_IsActiveFlag_HSECSS
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
-{
-  return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSECSSF) == (RCC_CIFR_HSECSSF))?1UL:0UL);
-}
-
-/**
-  * @brief  Check if RCC flag Low Power D1 reset is set or not.
-  * @rmtoll RSR          LPWRRSTF       LL_RCC_IsActiveFlag_LPWRRST (*)\n
-  *         RSR          LPWR1RSTF      LL_RCC_IsActiveFlag_LPWRRST (**)
-  *
-  * (*) Only available for single core devices
-  * (**) Only available for Dual core devices
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
-{
-#if defined(DUAL_CORE)
-  return ((READ_BIT(RCC->RSR, RCC_RSR_LPWR1RSTF) == (RCC_RSR_LPWR1RSTF))?1UL:0UL);
-#else
-  return ((READ_BIT(RCC->RSR, RCC_RSR_LPWRRSTF) == (RCC_RSR_LPWRRSTF))?1UL:0UL);
-#endif /*DUAL_CORE*/
-}
-
-#if defined(DUAL_CORE)
-/**
-  * @brief  Check if RCC flag Low Power D2 reset is set or not.
-  * @rmtoll RSR          LPWR2RSTF      LL_RCC_IsActiveFlag_LPWR2RST
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWR2RST(void)
-{
-  return ((READ_BIT(RCC->RSR, RCC_RSR_LPWR2RSTF) == (RCC_RSR_LPWR2RSTF))?1UL:0UL);
-}
-#endif  /*DUAL_CORE*/
-
-/**
-  * @brief  Check if RCC flag Window Watchdog 1 reset is set or not.
-  * @rmtoll RSR          WWDG1RSTF      LL_RCC_IsActiveFlag_WWDG1RST
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDG1RST(void)
-{
-  return ((READ_BIT(RCC->RSR, RCC_RSR_WWDG1RSTF) == (RCC_RSR_WWDG1RSTF))?1UL:0UL);
-}
-
-#if defined(DUAL_CORE)
-/**
-  * @brief  Check if RCC flag Window Watchdog 2 reset is set or not.
-  * @rmtoll RSR          WWDG2RSTF      LL_RCC_IsActiveFlag_WWDG2RST
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDG2RST(void)
-{
-  return ((READ_BIT(RCC->RSR, RCC_RSR_WWDG2RSTF) == (RCC_RSR_WWDG2RSTF))?1UL:0UL);
-}
-#endif  /*DUAL_CORE*/
-
-/**
-  * @brief  Check if RCC flag Independent Watchdog 1 reset is set or not.
-  * @rmtoll RSR          IWDG1RSTF      LL_RCC_IsActiveFlag_IWDG1RST
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDG1RST(void)
-{
-  return ((READ_BIT(RCC->RSR, RCC_RSR_IWDG1RSTF) == (RCC_RSR_IWDG1RSTF))?1UL:0UL);
-}
-
-#if defined(DUAL_CORE)
-/**
-  * @brief  Check if RCC flag Independent Watchdog 2 reset is set or not.
-  * @rmtoll RSR          IWDG2RSTF      LL_RCC_IsActiveFlag_IWDG2RST
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDG2RST(void)
-{
-  return ((READ_BIT(RCC->RSR, RCC_RSR_IWDG2RSTF) == (RCC_RSR_IWDG2RSTF))?1UL:0UL);
-}
-#endif  /*DUAL_CORE*/
-
-/**
-  * @brief  Check if RCC flag Software reset is set or not.
-  * @rmtoll RSR          SFTRSTF        LL_RCC_IsActiveFlag_SFTRST (*)\n
-  *         RSR          SFT1RSTF       LL_RCC_IsActiveFlag_SFTRST (**)
-  *
-  * (*) Only available for single core devices
-  * (**) Only available for Dual core devices
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
-{
-#if defined(DUAL_CORE)
-  return ((READ_BIT(RCC->RSR, RCC_RSR_SFT1RSTF) == (RCC_RSR_SFT1RSTF))?1UL:0UL);
-#else
-  return ((READ_BIT(RCC->RSR, RCC_RSR_SFTRSTF) == (RCC_RSR_SFTRSTF))?1UL:0UL);
-#endif  /*DUAL_CORE*/
-}
-
-#if defined(DUAL_CORE)
-/**
-  * @brief  Check if RCC flag Software reset is set or not.
-  * @rmtoll RSR          SFT2RSTF       LL_RCC_IsActiveFlag_SFT2RST
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFT2RST(void)
-{
-  return ((READ_BIT(RCC->RSR, RCC_RSR_SFT2RSTF) == (RCC_RSR_SFT2RSTF))?1UL:0UL);
-}
-#endif  /*DUAL_CORE*/
-
-/**
-  * @brief  Check if RCC flag POR/PDR reset is set or not.
-  * @rmtoll RSR          PORRSTF       LL_RCC_IsActiveFlag_PORRST
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)
-{
-  return ((READ_BIT(RCC->RSR, RCC_RSR_PORRSTF) == (RCC_RSR_PORRSTF))?1UL:0UL);
-}
-
-/**
-  * @brief  Check if RCC flag Pin reset is set or not.
-  * @rmtoll RSR          PINRSTF       LL_RCC_IsActiveFlag_PINRST
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
-{
-  return ((READ_BIT(RCC->RSR, RCC_RSR_PINRSTF) == (RCC_RSR_PINRSTF))?1UL:0UL);
-}
-
-/**
-  * @brief  Check if RCC flag BOR reset is set or not.
-  * @rmtoll RSR          BORRSTF       LL_RCC_IsActiveFlag_BORRST
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)
-{
-  return ((READ_BIT(RCC->RSR, RCC_RSR_BORRSTF) == (RCC_RSR_BORRSTF))?1UL:0UL);
-}
-
-#if defined(RCC_RSR_D1RSTF)
-/**
-  * @brief  Check if RCC flag D1 reset is set or not.
-  * @rmtoll RSR          D1RSTF       LL_RCC_IsActiveFlag_D1RST
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_D1RST(void)
-{
-  return ((READ_BIT(RCC->RSR, RCC_RSR_D1RSTF) == (RCC_RSR_D1RSTF))?1UL:0UL);
-}
-#endif /* RCC_RSR_D1RSTF */
-
-#if defined(RCC_RSR_CDRSTF)
-/**
-  * @brief  Check if RCC flag CD reset is set or not.
-  * @rmtoll RSR          CDRSTF       LL_RCC_IsActiveFlag_CDRST
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CDRST(void)
-{
-  return ((READ_BIT(RCC->RSR, RCC_RSR_CDRSTF) == (RCC_RSR_CDRSTF))?1UL:0UL);
-}
-#endif /* RCC_RSR_CDRSTF */
-
-#if defined(RCC_RSR_D2RSTF)
-/**
-  * @brief  Check if RCC flag D2 reset is set or not.
-  * @rmtoll RSR          D2RSTF       LL_RCC_IsActiveFlag_D2RST
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_D2RST(void)
-{
-  return ((READ_BIT(RCC->RSR, RCC_RSR_D2RSTF) == (RCC_RSR_D2RSTF))?1UL:0UL);
-}
-#endif /* RCC_RSR_D2RSTF */
-
-#if defined(RCC_RSR_C1RSTF) || defined(RCC_RSR_CPURSTF)
-/**
-  * @brief  Check if RCC flag CPU reset is set or not.
-  * @rmtoll RSR          CPURSTF       LL_RCC_IsActiveFlag_CPURST (*)\n
-  *         RSR          C1RSTF        LL_RCC_IsActiveFlag_CPURST (**)
-  *
-  * (*) Only available for single core devices
-  * (**) Only available for Dual core devices
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CPURST(void)
-{
-#if defined(DUAL_CORE)
-  return ((READ_BIT(RCC->RSR, RCC_RSR_C1RSTF) == (RCC_RSR_C1RSTF))?1UL:0UL);
-#else
-  return ((READ_BIT(RCC->RSR, RCC_RSR_CPURSTF) == (RCC_RSR_CPURSTF))?1UL:0UL);
-#endif/*DUAL_CORE*/
-}
-#endif /* defined(RCC_RSR_C1RSTF) || defined(RCC_RSR_CPURSTF) */
-
-#if defined(DUAL_CORE)
-/**
-  * @brief  Check if RCC flag CPU2 reset is set or not.
-  * @rmtoll RSR          C2RSTF       LL_RCC_IsActiveFlag_CPU2RST
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CPU2RST(void)
-{
-  return ((READ_BIT(RCC->RSR, RCC_RSR_C2RSTF) == (RCC_RSR_C2RSTF))?1UL:0UL);
-}
-#endif  /*DUAL_CORE*/
-
-/**
-  * @brief  Set RMVF bit to clear all reset flags.
-  * @rmtoll RSR          RMVF          LL_RCC_ClearResetFlags
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_ClearResetFlags(void)
-{
-  SET_BIT(RCC->RSR, RCC_RSR_RMVF);
-}
-
-#if defined(DUAL_CORE)
-/**
-  * @brief  Check if RCC_C1 flag Low Power D1 reset is set or not.
-  * @rmtoll RSR          LPWR1RSTF      LL_C1_RCC_IsActiveFlag_LPWRRST
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_LPWRRST(void)
-{
-  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_LPWR1RSTF) == (RCC_RSR_LPWR1RSTF))?1UL:0UL);
-}
-
-/**
-  * @brief  Check if RCC_C1 flag Low Power D2 reset is set or not.
-  * @rmtoll RSR          LPWR2RSTF      LL_C1_RCC_IsActiveFlag_LPWR2RST
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_LPWR2RST(void)
-{
-  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_LPWR2RSTF) == (RCC_RSR_LPWR2RSTF))?1UL:0UL);
-}
-
-/**
-  * @brief  Check if RCC_C1 flag Window Watchdog 1 reset is set or not.
-  * @rmtoll RSR          WWDG1RSTF      LL_C1_RCC_IsActiveFlag_WWDG1RST
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_WWDG1RST(void)
-{
-  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_WWDG1RSTF) == (RCC_RSR_WWDG1RSTF))?1UL:0UL);
-}
-
-/**
-  * @brief  Check if RCC_C1 flag Window Watchdog 2 reset is set or not.
-  * @rmtoll RSR          WWDG2RSTF      LL_C1_RCC_IsActiveFlag_WWDG2RST
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_WWDG2RST(void)
-{
-  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_WWDG2RSTF) == (RCC_RSR_WWDG2RSTF))?1UL:0UL);
-}
-
-/**
-  * @brief  Check if RCC_C1 flag Independent Watchdog 1 reset is set or not.
-  * @rmtoll RSR          IWDG1RSTF      LL_C1_RCC_IsActiveFlag_IWDG1RST
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_IWDG1RST(void)
-{
-  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_IWDG1RSTF) == (RCC_RSR_IWDG1RSTF))?1UL:0UL);
-}
-
-/**
-  * @brief  Check if RCC_C1 flag Independent Watchdog 2 reset is set or not.
-  * @rmtoll RSR          IWDG2RSTF      LL_C1_RCC_IsActiveFlag_IWDG2RST
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_IWDG2RST(void)
-{
-  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_IWDG2RSTF) == (RCC_RSR_IWDG2RSTF))?1UL:0UL);
-}
-
-/**
-  * @brief  Check if RCC_C1 flag Software reset is set or not.
-  * @rmtoll RSR          SFT1RSTF       LL_C1_RCC_IsActiveFlag_SFTRST
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_SFTRST(void)
-{
-  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_SFT1RSTF) == (RCC_RSR_SFT1RSTF))?1UL:0UL);
-}
-
-/**
-  * @brief  Check if RCC_C1 flag Software reset is set or not.
-  * @rmtoll RSR          SFT2RSTF       LL_C1_RCC_IsActiveFlag_SFT2RST
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_SFT2RST(void)
-{
-  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_SFT2RSTF) == (RCC_RSR_SFT2RSTF))?1UL:0UL);
-}
-
-/**
-  * @brief  Check if RCC_C1 flag POR/PDR reset is set or not.
-  * @rmtoll RSR          PORRSTF       LL_C1_RCC_IsActiveFlag_PORRST
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_PORRST(void)
-{
-  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_PORRSTF) == (RCC_RSR_PORRSTF))?1UL:0UL);
-}
-
-/**
-  * @brief  Check if RCC_C1 flag Pin reset is set or not.
-  * @rmtoll RSR          PINRSTF       LL_C1_RCC_IsActiveFlag_PINRST
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_PINRST(void)
-{
-  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_PINRSTF) == (RCC_RSR_PINRSTF))?1UL:0UL);
-}
-
-/**
-  * @brief  Check if RCC_C1 flag BOR reset is set or not.
-  * @rmtoll RSR          BORRSTF       LL_C1_RCC_IsActiveFlag_BORRST
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_BORRST(void)
-{
-  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_BORRSTF) == (RCC_RSR_BORRSTF))?1UL:0UL);
-}
-
-/**
-  * @brief  Check if RCC_C1 flag D1 reset is set or not.
-  * @rmtoll RSR          D1RSTF       LL_C1_RCC_IsActiveFlag_D1RST
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_D1RST(void)
-{
-  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_D1RSTF) == (RCC_RSR_D1RSTF))?1UL:0UL);
-}
-
-/**
-  * @brief  Check if RCC_C1 flag D2 reset is set or not.
-  * @rmtoll RSR          D2RSTF       LL_C1_RCC_IsActiveFlag_D2RST
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_D2RST(void)
-{
-  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_D2RSTF) == (RCC_RSR_D2RSTF))?1UL:0UL);
-}
-
-/**
-  * @brief  Check if RCC_C1 flag CPU reset is set or not.
-  * @rmtoll RSR          C1RSTF       LL_C1_RCC_IsActiveFlag_CPURST
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_CPURST(void)
-{
-  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_C1RSTF) == (RCC_RSR_C1RSTF))?1UL:0UL);
-}
-
-/**
-  * @brief  Check if RCC_C1 flag CPU2 reset is set or not.
-  * @rmtoll RSR          C2RSTF       LL_C1_RCC_IsActiveFlag_CPU2RST
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_CPU2RST(void)
-{
-  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_C2RSTF) == (RCC_RSR_C2RSTF))?1UL:0UL);
-}
-
-/**
-  * @brief  Set RMVF bit to clear the reset flags.
-  * @rmtoll RSR          RMVF          LL_C1_RCC_ClearResetFlags
-  * @retval None
-  */
-__STATIC_INLINE void LL_C1_RCC_ClearResetFlags(void)
-{
-  SET_BIT(RCC_C1->RSR, RCC_RSR_RMVF);
-}
-
-/**
-  * @brief  Check if RCC_C2 flag Low Power D1 reset is set or not.
-  * @rmtoll RSR          LPWR1RSTF      LL_C2_RCC_IsActiveFlag_LPWRRST
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_LPWRRST(void)
-{
-  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_LPWR1RSTF) == (RCC_RSR_LPWR1RSTF))?1UL:0UL);
-}
-
-/**
-  * @brief  Check if RCC_C2 flag Low Power D2 reset is set or not.
-  * @rmtoll RSR          LPWR2RSTF      LL_C2_RCC_IsActiveFlag_LPWR2RST
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_LPWR2RST(void)
-{
-  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_LPWR2RSTF) == (RCC_RSR_LPWR2RSTF))?1UL:0UL);
-}
-
-/**
-  * @brief  Check if RCC_C2 flag Window Watchdog 1 reset is set or not.
-  * @rmtoll RSR          WWDG1RSTF      LL_C2_RCC_IsActiveFlag_WWDG1RST
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_WWDG1RST(void)
-{
-  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_WWDG1RSTF) == (RCC_RSR_WWDG1RSTF))?1UL:0UL);
-}
-
-/**
-  * @brief  Check if RCC_C2 flag Window Watchdog 2 reset is set or not.
-  * @rmtoll RSR          WWDG2RSTF      LL_C2_RCC_IsActiveFlag_WWDG2RST
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_WWDG2RST(void)
-{
-  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_WWDG2RSTF) == (RCC_RSR_WWDG2RSTF))?1UL:0UL);
-}
-
-/**
-  * @brief  Check if RCC_C2 flag Independent Watchdog 1 reset is set or not.
-  * @rmtoll RSR          IWDG1RSTF      LL_C2_RCC_IsActiveFlag_IWDG1RST
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_IWDG1RST(void)
-{
-  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_IWDG1RSTF) == (RCC_RSR_IWDG1RSTF))?1UL:0UL);
-}
-
-/**
-  * @brief  Check if RCC_C2 flag Independent Watchdog 2 reset is set or not.
-  * @rmtoll RSR          IWDG2RSTF      LL_C2_RCC_IsActiveFlag_IWDG2RST
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_IWDG2RST(void)
-{
-  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_IWDG2RSTF) == (RCC_RSR_IWDG2RSTF))?1UL:0UL);
-}
-
-/**
-  * @brief  Check if RCC_C2 flag Software reset is set or not.
-  * @rmtoll RSR          SFT1RSTF       LL_C2_RCC_IsActiveFlag_SFTRST
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_SFTRST(void)
-{
-  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_SFT1RSTF) == (RCC_RSR_SFT1RSTF))?1UL:0UL);
-}
-
-/**
-  * @brief  Check if RCC_C2 flag Software reset is set or not.
-  * @rmtoll RSR          SFT2RSTF       LL_C2_RCC_IsActiveFlag_SFT2RST
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_SFT2RST(void)
-{
-  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_SFT2RSTF) == (RCC_RSR_SFT2RSTF))?1UL:0UL);
-}
-
-/**
-  * @brief  Check if RCC_C2 flag POR/PDR reset is set or not.
-  * @rmtoll RSR          PORRSTF       LL_C2_RCC_IsActiveFlag_PORRST
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_PORRST(void)
-{
-  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_PORRSTF) == (RCC_RSR_PORRSTF))?1UL:0UL);
-}
-
-/**
-  * @brief  Check if RCC_C2 flag Pin reset is set or not.
-  * @rmtoll RSR          PINRSTF       LL_C2_RCC_IsActiveFlag_PINRST
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_PINRST(void)
-{
-  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_PINRSTF) == (RCC_RSR_PINRSTF))?1UL:0UL);
-}
-
-/**
-  * @brief  Check if RCC_C2 flag BOR reset is set or not.
-  * @rmtoll RSR          BORRSTF       LL_C2_RCC_IsActiveFlag_BORRST
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_BORRST(void)
-{
-  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_BORRSTF) == (RCC_RSR_BORRSTF))?1UL:0UL);
-}
-
-/**
-  * @brief  Check if RCC_C2 flag D1 reset is set or not.
-  * @rmtoll RSR          D1RSTF       LL_C2_RCC_IsActiveFlag_D1RST
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_D1RST(void)
-{
-  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_D1RSTF) == (RCC_RSR_D1RSTF))?1UL:0UL);
-}
-
-/**
-  * @brief  Check if RCC_C2 flag D2 reset is set or not.
-  * @rmtoll RSR          D2RSTF       LL_C2_RCC_IsActiveFlag_D2RST
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_D2RST(void)
-{
-  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_D2RSTF) == (RCC_RSR_D2RSTF))?1UL:0UL);
-}
-
-/**
-  * @brief  Check if RCC_C2 flag CPU reset is set or not.
-  * @rmtoll RSR          C1RSTF       LL_C2_RCC_IsActiveFlag_CPURST
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_CPURST(void)
-{
-  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_C1RSTF) == (RCC_RSR_C1RSTF))?1UL:0UL);
-}
-
-/**
-  * @brief  Check if RCC_C2 flag CPU2 reset is set or not.
-  * @rmtoll RSR          C2RSTF       LL_C2_RCC_IsActiveFlag_CPU2RST
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_CPU2RST(void)
-{
-  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_C2RSTF) == (RCC_RSR_C2RSTF))?1UL:0UL);
-}
-
-/**
-  * @brief  Set RMVF bit to clear the reset flags.
-  * @rmtoll RSR          RMVF          LL_C2_RCC_ClearResetFlags
-  * @retval None
-  */
-__STATIC_INLINE void LL_C2_RCC_ClearResetFlags(void)
-{
-  SET_BIT(RCC_C2->RSR, RCC_RSR_RMVF);
-}
-#endif /*DUAL_CORE*/
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EF_IT_Management IT Management
-  * @{
-  */
-
-/**
-  * @brief  Enable LSI ready interrupt
-  * @rmtoll CIER         LSIRDYIE      LL_RCC_EnableIT_LSIRDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
-{
-  SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
-}
-
-/**
-  * @brief  Enable LSE ready interrupt
-  * @rmtoll CIER         LSERDYIE      LL_RCC_EnableIT_LSERDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
-{
-  SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
-}
-
-/**
-  * @brief  Enable HSI ready interrupt
-  * @rmtoll CIER         HSIRDYIE      LL_RCC_EnableIT_HSIRDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
-{
-  SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
-}
-
-/**
-  * @brief  Enable HSE ready interrupt
-  * @rmtoll CIER         HSERDYIE      LL_RCC_EnableIT_HSERDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
-{
-  SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
-}
-
-/**
-  * @brief  Enable CSI ready interrupt
-  * @rmtoll CIER         CSIRDYIE      LL_RCC_EnableIT_CSIRDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_EnableIT_CSIRDY(void)
-{
-  SET_BIT(RCC->CIER, RCC_CIER_CSIRDYIE);
-}
-
-/**
-  * @brief  Enable HSI48 ready interrupt
-  * @rmtoll CIER         HSI48RDYIE      LL_RCC_EnableIT_HSI48RDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void)
-{
-  SET_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
-}
-
-/**
-  * @brief  Enable PLL1 ready interrupt
-  * @rmtoll CIER         PLL1RDYIE      LL_RCC_EnableIT_PLL1RDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_EnableIT_PLL1RDY(void)
-{
-  SET_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE);
-}
-
-/**
-  * @brief  Enable PLL2 ready interrupt
-  * @rmtoll CIER         PLL2RDYIE  LL_RCC_EnableIT_PLL2RDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_EnableIT_PLL2RDY(void)
-{
-  SET_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE);
-}
-
-/**
-  * @brief  Enable PLL3 ready interrupt
-  * @rmtoll CIER         PLL3RDYIE  LL_RCC_EnableIT_PLL3RDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_EnableIT_PLL3RDY(void)
-{
-  SET_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE);
-}
-
-/**
-  * @brief  Enable LSECSS interrupt
-  * @rmtoll CIER         LSECSSIE  LL_RCC_EnableIT_LSECSS
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_EnableIT_LSECSS(void)
-{
-  SET_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
-}
-
-/**
-  * @brief  Disable LSI ready interrupt
-  * @rmtoll CIER         LSIRDYIE      LL_RCC_DisableIT_LSIRDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
-{
-  CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
-}
-
-/**
-  * @brief  Disable LSE ready interrupt
-  * @rmtoll CIER         LSERDYIE      LL_RCC_DisableIT_LSERDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
-{
-  CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
-}
-
-/**
-  * @brief  Disable HSI ready interrupt
-  * @rmtoll CIER         HSIRDYIE      LL_RCC_DisableIT_HSIRDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
-{
-  CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
-}
-
-/**
-  * @brief  Disable HSE ready interrupt
-  * @rmtoll CIER         HSERDYIE      LL_RCC_DisableIT_HSERDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
-{
-  CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
-}
-
-/**
-  * @brief  Disable CSI ready interrupt
-  * @rmtoll CIER         CSIRDYIE      LL_RCC_DisableIT_CSIRDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_DisableIT_CSIRDY(void)
-{
-  CLEAR_BIT(RCC->CIER, RCC_CIER_CSIRDYIE);
-}
-
-/**
-  * @brief  Disable HSI48 ready interrupt
-  * @rmtoll CIER         HSI48RDYIE      LL_RCC_DisableIT_HSI48RDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void)
-{
-  CLEAR_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
-}
-
-/**
-  * @brief  Disable PLL1 ready interrupt
-  * @rmtoll CIER         PLL1RDYIE      LL_RCC_DisableIT_PLL1RDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_DisableIT_PLL1RDY(void)
-{
-  CLEAR_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE);
-}
-
-/**
-  * @brief  Disable PLL2 ready interrupt
-  * @rmtoll CIER         PLL2RDYIE  LL_RCC_DisableIT_PLL2RDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_DisableIT_PLL2RDY(void)
-{
-  CLEAR_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE);
-}
-
-/**
-  * @brief  Disable PLL3 ready interrupt
-  * @rmtoll CIER         PLL3RDYIE  LL_RCC_DisableIT_PLL3RDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_DisableIT_PLL3RDY(void)
-{
-  CLEAR_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE);
-}
-
-/**
-  * @brief  Disable LSECSS interrupt
-  * @rmtoll CIER         LSECSSIE  LL_RCC_DisableIT_LSECSS
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_DisableIT_LSECSS(void)
-{
-  CLEAR_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
-}
-
-/**
-  * @brief  Checks if LSI ready interrupt source is enabled or disabled.
-  * @rmtoll CIER         LSIRDYIE      LL_RCC_IsEnableIT_LSIRDY
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_LSIRDY(void)
-{
-  return ((READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == RCC_CIER_LSIRDYIE)?1UL:0UL);
-}
-
-/**
-  * @brief  Checks if LSE ready interrupt source is enabled or disabled.
-  * @rmtoll CIER         LSERDYIE      LL_RCC_IsEnableIT_LSERDY
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_LSERDY(void)
-{
-  return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == RCC_CIER_LSERDYIE)?1UL:0UL);
-}
-
-/**
-  * @brief  Checks if HSI ready interrupt source is enabled or disabled.
-  * @rmtoll CIER         HSIRDYIE      LL_RCC_IsEnableIT_HSIRDY
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_HSIRDY(void)
-{
-  return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == RCC_CIER_HSIRDYIE)?1UL:0UL);
-}
-
-/**
-  * @brief  Checks if HSE ready interrupt source is enabled or disabled.
-  * @rmtoll CIER         HSERDYIE      LL_RCC_IsEnableIT_HSERDY
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_HSERDY(void)
-{
-  return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == RCC_CIER_HSERDYIE)?1UL:0UL);
-}
-
-/**
-  * @brief  Checks if CSI ready interrupt source is enabled or disabled.
-  * @rmtoll CIER         CSIRDYIE      LL_RCC_IsEnableIT_CSIRDY
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_CSIRDY(void)
-{
-  return ((READ_BIT(RCC->CIER, RCC_CIER_CSIRDYIE) == RCC_CIER_CSIRDYIE)?1UL:0UL);
-}
-
-/**
-  * @brief  Checks if HSI48 ready interrupt source is enabled or disabled.
-  * @rmtoll CIER         HSI48RDYIE      LL_RCC_IsEnableIT_HSI48RDY
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_HSI48RDY(void)
-{
-  return ((READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == RCC_CIER_HSI48RDYIE)?1UL:0UL);
-}
-
-/**
-  * @brief  Checks if PLL1 ready interrupt source is enabled or disabled.
-  * @rmtoll CIER         PLL1RDYIE      LL_RCC_IsEnableIT_PLL1RDY
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_PLL1RDY(void)
-{
-  return ((READ_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE) == RCC_CIER_PLL1RDYIE)?1UL:0UL);
-}
-
-/**
-  * @brief  Checks if PLL2 ready interrupt source is enabled or disabled.
-  * @rmtoll CIER         PLL2RDYIE  LL_RCC_IsEnableIT_PLL2RDY
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_PLL2RDY(void)
-{
-  return ((READ_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE) == RCC_CIER_PLL2RDYIE)?1UL:0UL);
-}
-
-/**
-  * @brief  Checks if PLL3 ready interrupt source is enabled or disabled.
-  * @rmtoll CIER         PLL3RDYIE  LL_RCC_IsEnableIT_PLL3RDY
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_PLL3RDY(void)
-{
-  return ((READ_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE) == RCC_CIER_PLL3RDYIE)?1UL:0UL);
-}
-
-/**
-  * @brief  Checks if LSECSS interrupt source is enabled or disabled.
-  * @rmtoll CIER         LSECSSIE  LL_RCC_IsEnableIT_LSECSS
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_LSECSS(void)
-{
-  return ((READ_BIT(RCC->CIER, RCC_CIER_LSECSSIE) == RCC_CIER_LSECSSIE)?1UL:0UL);
-}
-/**
-  * @}
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup RCC_LL_EF_Init De-initialization function
-  * @{
-  */
-void LL_RCC_DeInit(void);
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
-  * @{
-  */
-uint32_t    LL_RCC_CalcPLLClockFreq(uint32_t PLLInputFreq, uint32_t M, uint32_t N, uint32_t FRACN, uint32_t PQR);
-
-void        LL_RCC_GetPLL1ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks);
-void        LL_RCC_GetPLL2ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks);
-void        LL_RCC_GetPLL3ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks);
-void        LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
-
-uint32_t    LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
-uint32_t    LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource);
-uint32_t    LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
-uint32_t    LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
-uint32_t    LL_RCC_GetSAIClockFreq(uint32_t SAIxSource);
-uint32_t    LL_RCC_GetADCClockFreq(uint32_t ADCxSource);
-uint32_t    LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource);
-uint32_t    LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);
-uint32_t    LL_RCC_GetCECClockFreq(uint32_t CECxSource);
-uint32_t    LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
-uint32_t    LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource);
-#if defined(DFSDM2_BASE)
-uint32_t    LL_RCC_GetDFSDM2ClockFreq(uint32_t DFSDMxSource);
-#endif /* DFSDM2_BASE */
-#if defined(DSI)
-uint32_t    LL_RCC_GetDSIClockFreq(uint32_t DSIxSource);
-#endif /* DSI */
-uint32_t    LL_RCC_GetSPDIFClockFreq(uint32_t SPDIFxSource);
-uint32_t    LL_RCC_GetSPIClockFreq(uint32_t SPIxSource);
-uint32_t    LL_RCC_GetSWPClockFreq(uint32_t SWPxSource);
-uint32_t    LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource);
-uint32_t    LL_RCC_GetFMCClockFreq(uint32_t FMCxSource);
-#if defined(QUADSPI)
-uint32_t    LL_RCC_GetQSPIClockFreq(uint32_t QSPIxSource);
-#endif /* QUADSPI */
-#if defined(OCTOSPI1) || defined(OCTOSPI2)
-uint32_t    LL_RCC_GetOSPIClockFreq(uint32_t OSPIxSource);
-#endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */
-uint32_t    LL_RCC_GetCLKPClockFreq(uint32_t CLKPxSource);
-
-
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */
-#endif /* defined(RCC) */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32H7xx_LL_RCC_H */
-
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_ll_rcc.h
+  * @author  MCD Application Team
+  * @brief   Header file of RCC LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_LL_RCC_H
+#define STM32H7xx_LL_RCC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx.h"
+#include <math.h>
+
+/** @addtogroup STM32H7xx_LL_Driver
+  * @{
+  */
+
+#if defined(RCC)
+
+/** @defgroup RCC_LL RCC
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup RCC_LL_Private_Variables RCC Private Variables
+  * @{
+  */
+extern const uint8_t LL_RCC_PrescTable[16];
+
+/**
+  * @}
+  */
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+#if !defined(UNUSED)
+#define UNUSED(x) ((void)(x))
+#endif
+
+/* 32            24           16            8             0
+   --------------------------------------------------------
+   | Mask        | ClkSource   |  Bit       | Register    |
+   |             |  Config     | Position   | Offset      |
+   --------------------------------------------------------*/
+
+#if defined(RCC_VER_2_0)
+/* Clock source register offset Vs CDCCIPR register */
+#define CDCCIP    0x0UL
+#define CDCCIP1   0x4UL
+#define CDCCIP2   0x8UL
+#define SRDCCIP   0xCUL
+#else
+/* Clock source register offset Vs D1CCIPR register */
+#define D1CCIP    0x0UL
+#define D2CCIP1   0x4UL
+#define D2CCIP2   0x8UL
+#define D3CCIP    0xCUL
+#endif /* RCC_VER_2_0 */
+
+#define LL_RCC_REG_SHIFT     0U
+#define LL_RCC_POS_SHIFT     8U
+#define LL_RCC_CONFIG_SHIFT  16U
+#define LL_RCC_MASK_SHIFT    24U
+
+#define LL_CLKSOURCE_SHIFT(__CLKSOURCE__)   (((__CLKSOURCE__) >> LL_RCC_POS_SHIFT   ) & 0x1FUL)
+
+#define LL_CLKSOURCE_MASK(__CLKSOURCE__)   ((((__CLKSOURCE__) >> LL_RCC_MASK_SHIFT  ) & 0xFFUL) << LL_CLKSOURCE_SHIFT(__CLKSOURCE__))
+
+#define LL_CLKSOURCE_CONFIG(__CLKSOURCE__) ((((__CLKSOURCE__) >> LL_RCC_CONFIG_SHIFT) & 0xFFUL) << LL_CLKSOURCE_SHIFT(__CLKSOURCE__))
+
+#define LL_CLKSOURCE_REG(__CLKSOURCE__)     (((__CLKSOURCE__) >> LL_RCC_REG_SHIFT   ) & 0xFFUL)
+
+#define LL_CLKSOURCE(__REG__, __MSK__, __POS__, __CLK__) ((uint32_t)((((__MSK__) >> (__POS__)) << LL_RCC_MASK_SHIFT) | \
+                                                                     (( __POS__              ) << LL_RCC_POS_SHIFT)  | \
+                                                                     (( __REG__              ) << LL_RCC_REG_SHIFT)  | \
+                                                                     (((__CLK__) >> (__POS__)) << LL_RCC_CONFIG_SHIFT)))
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RCC_LL_Private_Macros RCC Private Macros
+  * @{
+  */
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RCC_LL_Exported_Types RCC Exported Types
+  * @{
+  */
+
+/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
+  * @{
+  */
+
+/**
+  * @brief  RCC Clocks Frequency Structure
+  */
+typedef struct
+{
+  uint32_t SYSCLK_Frequency;
+  uint32_t CPUCLK_Frequency;
+  uint32_t HCLK_Frequency;
+  uint32_t PCLK1_Frequency;
+  uint32_t PCLK2_Frequency;
+  uint32_t PCLK3_Frequency;
+  uint32_t PCLK4_Frequency;
+} LL_RCC_ClocksTypeDef;
+
+/**
+  * @}
+  */
+
+/**
+  * @brief  PLL Clocks Frequency Structure
+  */
+typedef struct
+{
+  uint32_t PLL_P_Frequency;
+  uint32_t PLL_Q_Frequency;
+  uint32_t PLL_R_Frequency;
+} LL_PLL_ClocksTypeDef;
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
+  * @{
+  */
+
+/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
+  * @brief    Defines used to adapt values of different oscillators
+  * @note     These values could be modified in the user environment according to
+  *           HW set-up.
+  * @{
+  */
+#if !defined  (HSE_VALUE)
+#if defined(RCC_VER_X) || defined(RCC_VER_3_0)
+#define HSE_VALUE    25000000U  /*!< Value of the HSE oscillator in Hz */
+#else
+#define HSE_VALUE    24000000U  /*!< Value of the HSE oscillator in Hz */
+#endif /* RCC_VER_X || RCC_VER_3_0 */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    64000000U  /*!< Value of the HSI oscillator in Hz */
+#endif /* HSI_VALUE */
+
+#if !defined  (CSI_VALUE)
+#define CSI_VALUE    4000000U   /*!< Value of the CSI oscillator in Hz */
+#endif /* CSI_VALUE */
+
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    32768U     /*!< Value of the LSE oscillator in Hz */
+#endif /* LSE_VALUE */
+
+#if !defined  (LSI_VALUE)
+#define LSI_VALUE    32000U     /*!< Value of the LSI oscillator in Hz */
+#endif /* LSI_VALUE */
+
+#if !defined  (EXTERNAL_CLOCK_VALUE)
+#define EXTERNAL_CLOCK_VALUE    12288000U /*!< Value of the I2S_CKIN external oscillator in Hz */
+#endif /* EXTERNAL_CLOCK_VALUE */
+
+#if !defined  (HSI48_VALUE)
+#define HSI48_VALUE  48000000U  /*!< Value of the HSI48 oscillator in Hz */
+#endif /* HSI48_VALUE */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_HSIDIV  HSI oscillator divider
+  * @{
+  */
+#define LL_RCC_HSI_DIV1                   RCC_CR_HSIDIV_1
+#define LL_RCC_HSI_DIV2                   RCC_CR_HSIDIV_2
+#define LL_RCC_HSI_DIV4                   RCC_CR_HSIDIV_4
+#define LL_RCC_HSI_DIV8                   RCC_CR_HSIDIV_8
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_LSEDRIVE  LSE oscillator drive capability
+  * @{
+  */
+#define LL_RCC_LSEDRIVE_LOW                (uint32_t)(0x00000000U)
+#define LL_RCC_LSEDRIVE_MEDIUMLOW          (uint32_t)(RCC_BDCR_LSEDRV_0)
+#define LL_RCC_LSEDRIVE_MEDIUMHIGH         (uint32_t)(RCC_BDCR_LSEDRV_1)
+#define LL_RCC_LSEDRIVE_HIGH               (uint32_t)(RCC_BDCR_LSEDRV)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_SYS_CLKSOURCE  System clock switch
+  * @{
+  */
+#define LL_RCC_SYS_CLKSOURCE_HSI           RCC_CFGR_SW_HSI
+#define LL_RCC_SYS_CLKSOURCE_CSI           RCC_CFGR_SW_CSI
+#define LL_RCC_SYS_CLKSOURCE_HSE           RCC_CFGR_SW_HSE
+#define LL_RCC_SYS_CLKSOURCE_PLL1          RCC_CFGR_SW_PLL1
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS  System clock switch status
+  * @{
+  */
+#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI    RCC_CFGR_SWS_HSI   /*!< HSI used as system clock */
+#define LL_RCC_SYS_CLKSOURCE_STATUS_CSI    RCC_CFGR_SWS_CSI   /*!< CSI used as system clock */
+#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE    RCC_CFGR_SWS_HSE   /*!< HSE used as system clock */
+#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL1   RCC_CFGR_SWS_PLL1  /*!< PLL1 used as system clock */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_SYSWAKEUP_CLKSOURCE  System wakeup clock source
+  * @{
+  */
+#define LL_RCC_SYSWAKEUP_CLKSOURCE_HSI     (uint32_t)(0x00000000U)
+#define LL_RCC_SYSWAKEUP_CLKSOURCE_CSI     (uint32_t)(RCC_CFGR_STOPWUCK)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_KERWAKEUP_CLKSOURCE  Kernel wakeup clock source
+  * @{
+  */
+#define LL_RCC_KERWAKEUP_CLKSOURCE_HSI     (uint32_t)(0x00000000U)
+#define LL_RCC_KERWAKEUP_CLKSOURCE_CSI     (uint32_t)(RCC_CFGR_STOPKERWUCK)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_SYSCLK_DIV  System prescaler
+  * @{
+  */
+#if defined(RCC_D1CFGR_D1CPRE_DIV1)
+#define LL_RCC_SYSCLK_DIV_1                RCC_D1CFGR_D1CPRE_DIV1
+#define LL_RCC_SYSCLK_DIV_2                RCC_D1CFGR_D1CPRE_DIV2
+#define LL_RCC_SYSCLK_DIV_4                RCC_D1CFGR_D1CPRE_DIV4
+#define LL_RCC_SYSCLK_DIV_8                RCC_D1CFGR_D1CPRE_DIV8
+#define LL_RCC_SYSCLK_DIV_16               RCC_D1CFGR_D1CPRE_DIV16
+#define LL_RCC_SYSCLK_DIV_64               RCC_D1CFGR_D1CPRE_DIV64
+#define LL_RCC_SYSCLK_DIV_128              RCC_D1CFGR_D1CPRE_DIV128
+#define LL_RCC_SYSCLK_DIV_256              RCC_D1CFGR_D1CPRE_DIV256
+#define LL_RCC_SYSCLK_DIV_512              RCC_D1CFGR_D1CPRE_DIV512
+#else
+#define LL_RCC_SYSCLK_DIV_1                RCC_CDCFGR1_CDCPRE_DIV1
+#define LL_RCC_SYSCLK_DIV_2                RCC_CDCFGR1_CDCPRE_DIV2
+#define LL_RCC_SYSCLK_DIV_4                RCC_CDCFGR1_CDCPRE_DIV4
+#define LL_RCC_SYSCLK_DIV_8                RCC_CDCFGR1_CDCPRE_DIV8
+#define LL_RCC_SYSCLK_DIV_16               RCC_CDCFGR1_CDCPRE_DIV16
+#define LL_RCC_SYSCLK_DIV_64               RCC_CDCFGR1_CDCPRE_DIV64
+#define LL_RCC_SYSCLK_DIV_128              RCC_CDCFGR1_CDCPRE_DIV128
+#define LL_RCC_SYSCLK_DIV_256              RCC_CDCFGR1_CDCPRE_DIV256
+#define LL_RCC_SYSCLK_DIV_512              RCC_CDCFGR1_CDCPRE_DIV512
+#endif /* RCC_D1CFGR_D1CPRE_DIV1 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_AHB_DIV  AHB prescaler
+  * @{
+  */
+#if defined(RCC_D1CFGR_HPRE_DIV1)
+#define LL_RCC_AHB_DIV_1                   RCC_D1CFGR_HPRE_DIV1
+#define LL_RCC_AHB_DIV_2                   RCC_D1CFGR_HPRE_DIV2
+#define LL_RCC_AHB_DIV_4                   RCC_D1CFGR_HPRE_DIV4
+#define LL_RCC_AHB_DIV_8                   RCC_D1CFGR_HPRE_DIV8
+#define LL_RCC_AHB_DIV_16                  RCC_D1CFGR_HPRE_DIV16
+#define LL_RCC_AHB_DIV_64                  RCC_D1CFGR_HPRE_DIV64
+#define LL_RCC_AHB_DIV_128                 RCC_D1CFGR_HPRE_DIV128
+#define LL_RCC_AHB_DIV_256                 RCC_D1CFGR_HPRE_DIV256
+#define LL_RCC_AHB_DIV_512                 RCC_D1CFGR_HPRE_DIV512
+#else
+#define LL_RCC_AHB_DIV_1                   RCC_CDCFGR1_HPRE_DIV1
+#define LL_RCC_AHB_DIV_2                   RCC_CDCFGR1_HPRE_DIV2
+#define LL_RCC_AHB_DIV_4                   RCC_CDCFGR1_HPRE_DIV4
+#define LL_RCC_AHB_DIV_8                   RCC_CDCFGR1_HPRE_DIV8
+#define LL_RCC_AHB_DIV_16                  RCC_CDCFGR1_HPRE_DIV16
+#define LL_RCC_AHB_DIV_64                  RCC_CDCFGR1_HPRE_DIV64
+#define LL_RCC_AHB_DIV_128                 RCC_CDCFGR1_HPRE_DIV128
+#define LL_RCC_AHB_DIV_256                 RCC_CDCFGR1_HPRE_DIV256
+#define LL_RCC_AHB_DIV_512                 RCC_CDCFGR1_HPRE_DIV512
+#endif /* RCC_D1CFGR_HPRE_DIV1 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_APB1_DIV  APB low-speed prescaler (APB1)
+  * @{
+  */
+#if defined(RCC_D2CFGR_D2PPRE1_DIV1)
+#define LL_RCC_APB1_DIV_1                  RCC_D2CFGR_D2PPRE1_DIV1
+#define LL_RCC_APB1_DIV_2                  RCC_D2CFGR_D2PPRE1_DIV2
+#define LL_RCC_APB1_DIV_4                  RCC_D2CFGR_D2PPRE1_DIV4
+#define LL_RCC_APB1_DIV_8                  RCC_D2CFGR_D2PPRE1_DIV8
+#define LL_RCC_APB1_DIV_16                 RCC_D2CFGR_D2PPRE1_DIV16
+#else
+#define LL_RCC_APB1_DIV_1                  RCC_CDCFGR2_CDPPRE1_DIV1
+#define LL_RCC_APB1_DIV_2                  RCC_CDCFGR2_CDPPRE1_DIV2
+#define LL_RCC_APB1_DIV_4                  RCC_CDCFGR2_CDPPRE1_DIV4
+#define LL_RCC_APB1_DIV_8                  RCC_CDCFGR2_CDPPRE1_DIV8
+#define LL_RCC_APB1_DIV_16                 RCC_CDCFGR2_CDPPRE1_DIV16
+#endif /* RCC_D2CFGR_D2PPRE1_DIV1 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_APB2_DIV  APB low-speed prescaler (APB2)
+  * @{
+  */
+#if defined(RCC_D2CFGR_D2PPRE2_DIV1)
+#define LL_RCC_APB2_DIV_1                  RCC_D2CFGR_D2PPRE2_DIV1
+#define LL_RCC_APB2_DIV_2                  RCC_D2CFGR_D2PPRE2_DIV2
+#define LL_RCC_APB2_DIV_4                  RCC_D2CFGR_D2PPRE2_DIV4
+#define LL_RCC_APB2_DIV_8                  RCC_D2CFGR_D2PPRE2_DIV8
+#define LL_RCC_APB2_DIV_16                 RCC_D2CFGR_D2PPRE2_DIV16
+#else
+#define LL_RCC_APB2_DIV_1                  RCC_CDCFGR2_CDPPRE2_DIV1
+#define LL_RCC_APB2_DIV_2                  RCC_CDCFGR2_CDPPRE2_DIV2
+#define LL_RCC_APB2_DIV_4                  RCC_CDCFGR2_CDPPRE2_DIV4
+#define LL_RCC_APB2_DIV_8                  RCC_CDCFGR2_CDPPRE2_DIV8
+#define LL_RCC_APB2_DIV_16                 RCC_CDCFGR2_CDPPRE2_DIV16
+#endif /* RCC_D2CFGR_D2PPRE2_DIV1 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_APB3_DIV  APB low-speed prescaler (APB3)
+  * @{
+  */
+#if defined(RCC_D1CFGR_D1PPRE_DIV1)
+#define LL_RCC_APB3_DIV_1                  RCC_D1CFGR_D1PPRE_DIV1
+#define LL_RCC_APB3_DIV_2                  RCC_D1CFGR_D1PPRE_DIV2
+#define LL_RCC_APB3_DIV_4                  RCC_D1CFGR_D1PPRE_DIV4
+#define LL_RCC_APB3_DIV_8                  RCC_D1CFGR_D1PPRE_DIV8
+#define LL_RCC_APB3_DIV_16                 RCC_D1CFGR_D1PPRE_DIV16
+#else
+#define LL_RCC_APB3_DIV_1                  RCC_CDCFGR1_CDPPRE_DIV1
+#define LL_RCC_APB3_DIV_2                  RCC_CDCFGR1_CDPPRE_DIV2
+#define LL_RCC_APB3_DIV_4                  RCC_CDCFGR1_CDPPRE_DIV4
+#define LL_RCC_APB3_DIV_8                  RCC_CDCFGR1_CDPPRE_DIV8
+#define LL_RCC_APB3_DIV_16                 RCC_CDCFGR1_CDPPRE_DIV16
+#endif /* RCC_D1CFGR_D1PPRE_DIV1 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_APB4_DIV  APB low-speed prescaler (APB4)
+  * @{
+  */
+#if defined(RCC_D3CFGR_D3PPRE_DIV1)
+#define LL_RCC_APB4_DIV_1                  RCC_D3CFGR_D3PPRE_DIV1
+#define LL_RCC_APB4_DIV_2                  RCC_D3CFGR_D3PPRE_DIV2
+#define LL_RCC_APB4_DIV_4                  RCC_D3CFGR_D3PPRE_DIV4
+#define LL_RCC_APB4_DIV_8                  RCC_D3CFGR_D3PPRE_DIV8
+#define LL_RCC_APB4_DIV_16                 RCC_D3CFGR_D3PPRE_DIV16
+#else
+#define LL_RCC_APB4_DIV_1                  RCC_SRDCFGR_SRDPPRE_DIV1
+#define LL_RCC_APB4_DIV_2                  RCC_SRDCFGR_SRDPPRE_DIV2
+#define LL_RCC_APB4_DIV_4                  RCC_SRDCFGR_SRDPPRE_DIV4
+#define LL_RCC_APB4_DIV_8                  RCC_SRDCFGR_SRDPPRE_DIV8
+#define LL_RCC_APB4_DIV_16                 RCC_SRDCFGR_SRDPPRE_DIV16
+#endif /* RCC_D3CFGR_D3PPRE_DIV1 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_MCOxSOURCE  MCO source selection
+  * @{
+  */
+#define LL_RCC_MCO1SOURCE_HSI              (uint32_t)((RCC_CFGR_MCO1>>16U) | 0x00000000U)
+#define LL_RCC_MCO1SOURCE_LSE              (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_0)
+#define LL_RCC_MCO1SOURCE_HSE              (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_1)
+#define LL_RCC_MCO1SOURCE_PLL1QCLK         (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_1|RCC_CFGR_MCO1_0)
+#define LL_RCC_MCO1SOURCE_HSI48            (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_2)
+#define LL_RCC_MCO2SOURCE_SYSCLK           (uint32_t)((RCC_CFGR_MCO2>>16U) | 0x00000000U)
+#define LL_RCC_MCO2SOURCE_PLL2PCLK         (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_0)
+#define LL_RCC_MCO2SOURCE_HSE              (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_1)
+#define LL_RCC_MCO2SOURCE_PLL1PCLK         (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_1|RCC_CFGR_MCO2_0)
+#define LL_RCC_MCO2SOURCE_CSI              (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_2)
+#define LL_RCC_MCO2SOURCE_LSI              (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_2|RCC_CFGR_MCO2_0)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_MCOx_DIV  MCO prescaler
+  * @{
+  */
+#define LL_RCC_MCO1_DIV_1                  (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0)
+#define LL_RCC_MCO1_DIV_2                  (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1)
+#define LL_RCC_MCO1_DIV_3                  (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1)
+#define LL_RCC_MCO1_DIV_4                  (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_2)
+#define LL_RCC_MCO1_DIV_5                  (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
+#define LL_RCC_MCO1_DIV_6                  (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
+#define LL_RCC_MCO1_DIV_7                  (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
+#define LL_RCC_MCO1_DIV_8                  (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_3)
+#define LL_RCC_MCO1_DIV_9                  (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_3)
+#define LL_RCC_MCO1_DIV_10                 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3)
+#define LL_RCC_MCO1_DIV_11                 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3)
+#define LL_RCC_MCO1_DIV_12                 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
+#define LL_RCC_MCO1_DIV_13                 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
+#define LL_RCC_MCO1_DIV_14                 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
+#define LL_RCC_MCO1_DIV_15                 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE)
+#define LL_RCC_MCO2_DIV_1                  (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0)
+#define LL_RCC_MCO2_DIV_2                  (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1)
+#define LL_RCC_MCO2_DIV_3                  (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_1)
+#define LL_RCC_MCO2_DIV_4                  (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_2)
+#define LL_RCC_MCO2_DIV_5                  (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_2)
+#define LL_RCC_MCO2_DIV_6                  (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_2)
+#define LL_RCC_MCO2_DIV_7                  (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_2)
+#define LL_RCC_MCO2_DIV_8                  (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_3)
+#define LL_RCC_MCO2_DIV_9                  (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_3)
+#define LL_RCC_MCO2_DIV_10                 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_3)
+#define LL_RCC_MCO2_DIV_11                 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_3)
+#define LL_RCC_MCO2_DIV_12                 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_3)
+#define LL_RCC_MCO2_DIV_13                 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_3)
+#define LL_RCC_MCO2_DIV_14                 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_3)
+#define LL_RCC_MCO2_DIV_15                 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_RTC_HSEDIV  HSE prescaler for RTC clock
+  * @{
+  */
+#define LL_RCC_RTC_NOCLOCK                  (uint32_t)(0x00000000U)
+#define LL_RCC_RTC_HSE_DIV_2                (uint32_t)(RCC_CFGR_RTCPRE_1)
+#define LL_RCC_RTC_HSE_DIV_3                (uint32_t)(RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_4                (uint32_t)(RCC_CFGR_RTCPRE_2)
+#define LL_RCC_RTC_HSE_DIV_5                (uint32_t)(RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_6                (uint32_t)(RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
+#define LL_RCC_RTC_HSE_DIV_7                (uint32_t)(RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_8                (uint32_t)(RCC_CFGR_RTCPRE_3)
+#define LL_RCC_RTC_HSE_DIV_9                (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_10               (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1)
+#define LL_RCC_RTC_HSE_DIV_11               (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_12               (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2)
+#define LL_RCC_RTC_HSE_DIV_13               (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_14               (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
+#define LL_RCC_RTC_HSE_DIV_15               (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_16               (uint32_t)(RCC_CFGR_RTCPRE_4)
+#define LL_RCC_RTC_HSE_DIV_17               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_18               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1)
+#define LL_RCC_RTC_HSE_DIV_19               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_20               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2)
+#define LL_RCC_RTC_HSE_DIV_21               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_22               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
+#define LL_RCC_RTC_HSE_DIV_23               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_24               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3)
+#define LL_RCC_RTC_HSE_DIV_25               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_26               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1)
+#define LL_RCC_RTC_HSE_DIV_27               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_28               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2)
+#define LL_RCC_RTC_HSE_DIV_29               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_30               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
+#define LL_RCC_RTC_HSE_DIV_31               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_32               (uint32_t)(RCC_CFGR_RTCPRE_5)
+#define LL_RCC_RTC_HSE_DIV_33               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_34               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_1)
+#define LL_RCC_RTC_HSE_DIV_35               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_36               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2)
+#define LL_RCC_RTC_HSE_DIV_37               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_38               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
+#define LL_RCC_RTC_HSE_DIV_39               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_40               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3)
+#define LL_RCC_RTC_HSE_DIV_41               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_42               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1)
+#define LL_RCC_RTC_HSE_DIV_43               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_44               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2)
+#define LL_RCC_RTC_HSE_DIV_45               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_46               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
+#define LL_RCC_RTC_HSE_DIV_47               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_48               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4)
+#define LL_RCC_RTC_HSE_DIV_49               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_50               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1)
+#define LL_RCC_RTC_HSE_DIV_51               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_52               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2)
+#define LL_RCC_RTC_HSE_DIV_53               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_54               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
+#define LL_RCC_RTC_HSE_DIV_55               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_56               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3)
+#define LL_RCC_RTC_HSE_DIV_57               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_58               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1)
+#define LL_RCC_RTC_HSE_DIV_59               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_60               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2)
+#define LL_RCC_RTC_HSE_DIV_61               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_62               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
+#define LL_RCC_RTC_HSE_DIV_63               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_USARTx_CLKSOURCE  Peripheral USART clock source selection
+  * @{
+  */
+#if defined(RCC_D2CCIP2R_USART16SEL)
+#define LL_RCC_USART16_CLKSOURCE_PCLK2         LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, 0x00000000U)
+#define LL_RCC_USART16_CLKSOURCE_PLL2Q         LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_0)
+#define LL_RCC_USART16_CLKSOURCE_PLL3Q         LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_1)
+#define LL_RCC_USART16_CLKSOURCE_HSI           LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_1)
+#define LL_RCC_USART16_CLKSOURCE_CSI           LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_2)
+#define LL_RCC_USART16_CLKSOURCE_LSE           LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_2)
+/*  Aliases */
+#define LL_RCC_USART16910_CLKSOURCE_PCLK2      LL_RCC_USART16_CLKSOURCE_PCLK2
+#define LL_RCC_USART16910_CLKSOURCE_PLL2Q      LL_RCC_USART16_CLKSOURCE_PLL2Q
+#define LL_RCC_USART16910_CLKSOURCE_PLL3Q      LL_RCC_USART16_CLKSOURCE_PLL3Q
+#define LL_RCC_USART16910_CLKSOURCE_HSI        LL_RCC_USART16_CLKSOURCE_HSI
+#define LL_RCC_USART16910_CLKSOURCE_CSI        LL_RCC_USART16_CLKSOURCE_CSI
+#define LL_RCC_USART16910_CLKSOURCE_LSE        LL_RCC_USART16_CLKSOURCE_LSE
+
+#elif defined(RCC_D2CCIP2R_USART16910SEL)
+#define LL_RCC_USART16910_CLKSOURCE_PCLK2      LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, 0x00000000U)
+#define LL_RCC_USART16910_CLKSOURCE_PLL2Q      LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, RCC_D2CCIP2R_USART16910SEL_0)
+#define LL_RCC_USART16910_CLKSOURCE_PLL3Q      LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, RCC_D2CCIP2R_USART16910SEL_1)
+#define LL_RCC_USART16910_CLKSOURCE_HSI        LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, RCC_D2CCIP2R_USART16910SEL_0 | RCC_D2CCIP2R_USART16910SEL_1)
+#define LL_RCC_USART16910_CLKSOURCE_CSI        LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, RCC_D2CCIP2R_USART16910SEL_2)
+#define LL_RCC_USART16910_CLKSOURCE_LSE        LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, RCC_D2CCIP2R_USART16910SEL_0 | RCC_D2CCIP2R_USART16910SEL_2)
+/*  Aliases */
+#define LL_RCC_USART16_CLKSOURCE_PCLK2         LL_RCC_USART16910_CLKSOURCE_PCLK2
+#define LL_RCC_USART16_CLKSOURCE_PLL2Q         LL_RCC_USART16910_CLKSOURCE_PLL2Q
+#define LL_RCC_USART16_CLKSOURCE_PLL3Q         LL_RCC_USART16910_CLKSOURCE_PLL3Q
+#define LL_RCC_USART16_CLKSOURCE_HSI           LL_RCC_USART16910_CLKSOURCE_HSI
+#define LL_RCC_USART16_CLKSOURCE_CSI           LL_RCC_USART16910_CLKSOURCE_CSI
+#define LL_RCC_USART16_CLKSOURCE_LSE           LL_RCC_USART16910_CLKSOURCE_LSE
+
+#else
+#define LL_RCC_USART16910_CLKSOURCE_PCLK2      LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, 0x00000000U)
+#define LL_RCC_USART16910_CLKSOURCE_PLL2Q      LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_0)
+#define LL_RCC_USART16910_CLKSOURCE_PLL3Q      LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_1)
+#define LL_RCC_USART16910_CLKSOURCE_HSI        LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_0 | RCC_CDCCIP2R_USART16910SEL_1)
+#define LL_RCC_USART16910_CLKSOURCE_CSI        LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_2)
+#define LL_RCC_USART16910_CLKSOURCE_LSE        LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_0 | RCC_CDCCIP2R_USART16910SEL_2)
+/*  Aliases */
+#define LL_RCC_USART16_CLKSOURCE_PCLK2         LL_RCC_USART16910_CLKSOURCE_PCLK2
+#define LL_RCC_USART16_CLKSOURCE_PLL2Q         LL_RCC_USART16910_CLKSOURCE_PLL2Q
+#define LL_RCC_USART16_CLKSOURCE_PLL3Q         LL_RCC_USART16910_CLKSOURCE_PLL3Q
+#define LL_RCC_USART16_CLKSOURCE_HSI           LL_RCC_USART16910_CLKSOURCE_HSI
+#define LL_RCC_USART16_CLKSOURCE_CSI           LL_RCC_USART16910_CLKSOURCE_CSI
+#define LL_RCC_USART16_CLKSOURCE_LSE           LL_RCC_USART16910_CLKSOURCE_LSE
+#endif  /* RCC_D2CCIP2R_USART16SEL */
+#if defined(RCC_D2CCIP2R_USART28SEL)
+#define LL_RCC_USART234578_CLKSOURCE_PCLK1     LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, 0x00000000U)
+#define LL_RCC_USART234578_CLKSOURCE_PLL2Q     LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_0)
+#define LL_RCC_USART234578_CLKSOURCE_PLL3Q     LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_1)
+#define LL_RCC_USART234578_CLKSOURCE_HSI       LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_1)
+#define LL_RCC_USART234578_CLKSOURCE_CSI       LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_2)
+#define LL_RCC_USART234578_CLKSOURCE_LSE       LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_2)
+#else
+#define LL_RCC_USART234578_CLKSOURCE_PCLK1     LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, 0x00000000U)
+#define LL_RCC_USART234578_CLKSOURCE_PLL2Q     LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_0)
+#define LL_RCC_USART234578_CLKSOURCE_PLL3Q     LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_1)
+#define LL_RCC_USART234578_CLKSOURCE_HSI       LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_0 | RCC_CDCCIP2R_USART234578SEL_1)
+#define LL_RCC_USART234578_CLKSOURCE_CSI       LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_2)
+#define LL_RCC_USART234578_CLKSOURCE_LSE       LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_0 | RCC_CDCCIP2R_USART234578SEL_2)
+#endif /* RCC_D2CCIP2R_USART28SEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_LPUARTx_CLKSOURCE  Peripheral LPUART clock source selection
+  * @{
+  */
+#if defined(RCC_D3CCIPR_LPUART1SEL)
+#define LL_RCC_LPUART1_CLKSOURCE_PCLK4         (0x00000000U)
+#define LL_RCC_LPUART1_CLKSOURCE_PLL2Q         (RCC_D3CCIPR_LPUART1SEL_0)
+#define LL_RCC_LPUART1_CLKSOURCE_PLL3Q         (RCC_D3CCIPR_LPUART1SEL_1)
+#define LL_RCC_LPUART1_CLKSOURCE_HSI           (RCC_D3CCIPR_LPUART1SEL_0 | RCC_D3CCIPR_LPUART1SEL_1)
+#define LL_RCC_LPUART1_CLKSOURCE_CSI           (RCC_D3CCIPR_LPUART1SEL_2)
+#define LL_RCC_LPUART1_CLKSOURCE_LSE           (RCC_D3CCIPR_LPUART1SEL_0 | RCC_D3CCIPR_LPUART1SEL_2)
+#else
+#define LL_RCC_LPUART1_CLKSOURCE_PCLK4         (0x00000000U)
+#define LL_RCC_LPUART1_CLKSOURCE_PLL2Q         (RCC_SRDCCIPR_LPUART1SEL_0)
+#define LL_RCC_LPUART1_CLKSOURCE_PLL3Q         (RCC_SRDCCIPR_LPUART1SEL_1)
+#define LL_RCC_LPUART1_CLKSOURCE_HSI           (RCC_SRDCCIPR_LPUART1SEL_0 | RCC_SRDCCIPR_LPUART1SEL_1)
+#define LL_RCC_LPUART1_CLKSOURCE_CSI           (RCC_SRDCCIPR_LPUART1SEL_2)
+#define LL_RCC_LPUART1_CLKSOURCE_LSE           (RCC_SRDCCIPR_LPUART1SEL_0 | RCC_SRDCCIPR_LPUART1SEL_2)
+#endif /* RCC_D3CCIPR_LPUART1SEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_I2Cx_CLKSOURCE  Peripheral I2C clock source selection
+  * @{
+  */
+#if defined (RCC_D2CCIP2R_I2C123SEL)
+#define LL_RCC_I2C123_CLKSOURCE_PCLK1          LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, 0x00000000U)
+#define LL_RCC_I2C123_CLKSOURCE_PLL3R          LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, RCC_D2CCIP2R_I2C123SEL_0)
+#define LL_RCC_I2C123_CLKSOURCE_HSI            LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, RCC_D2CCIP2R_I2C123SEL_1)
+#define LL_RCC_I2C123_CLKSOURCE_CSI            LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, RCC_D2CCIP2R_I2C123SEL_0 | RCC_D2CCIP2R_I2C123SEL_1)
+/*  Aliases */
+#define LL_RCC_I2C1235_CLKSOURCE_PCLK1         LL_RCC_I2C123_CLKSOURCE_PCLK1
+#define LL_RCC_I2C1235_CLKSOURCE_PLL3R         LL_RCC_I2C123_CLKSOURCE_PLL3R
+#define LL_RCC_I2C1235_CLKSOURCE_HSI           LL_RCC_I2C123_CLKSOURCE_HSI
+#define LL_RCC_I2C1235_CLKSOURCE_CSI           LL_RCC_I2C123_CLKSOURCE_CSI
+
+#elif defined (RCC_D2CCIP2R_I2C1235SEL)
+#define LL_RCC_I2C1235_CLKSOURCE_PCLK1         LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C1235SEL, RCC_D2CCIP2R_I2C1235SEL_Pos, 0x00000000U)
+#define LL_RCC_I2C1235_CLKSOURCE_PLL3R         LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C1235SEL, RCC_D2CCIP2R_I2C1235SEL_Pos, RCC_D2CCIP2R_I2C1235SEL_0)
+#define LL_RCC_I2C1235_CLKSOURCE_HSI           LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C1235SEL, RCC_D2CCIP2R_I2C1235SEL_Pos, RCC_D2CCIP2R_I2C1235SEL_1)
+#define LL_RCC_I2C1235_CLKSOURCE_CSI           LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C1235SEL, RCC_D2CCIP2R_I2C1235SEL_Pos, RCC_D2CCIP2R_I2C1235SEL_0 | RCC_D2CCIP2R_I2C1235SEL_1)
+/*  Aliases */
+#define LL_RCC_I2C123_CLKSOURCE_PCLK1          LL_RCC_I2C1235_CLKSOURCE_PCLK1
+#define LL_RCC_I2C123_CLKSOURCE_PLL3R          LL_RCC_I2C1235_CLKSOURCE_PLL3R
+#define LL_RCC_I2C123_CLKSOURCE_HSI            LL_RCC_I2C1235_CLKSOURCE_HSI
+#define LL_RCC_I2C123_CLKSOURCE_CSI            LL_RCC_I2C1235_CLKSOURCE_CSI
+
+#else
+#define LL_RCC_I2C123_CLKSOURCE_PCLK1          LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, 0x00000000U)
+#define LL_RCC_I2C123_CLKSOURCE_PLL3R          LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, RCC_CDCCIP2R_I2C123SEL_0)
+#define LL_RCC_I2C123_CLKSOURCE_HSI            LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, RCC_CDCCIP2R_I2C123SEL_1)
+#define LL_RCC_I2C123_CLKSOURCE_CSI            LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, RCC_CDCCIP2R_I2C123SEL_0 | RCC_CDCCIP2R_I2C123SEL_1)
+#endif /* RCC_D2CCIP2R_I2C123SEL */
+#if defined (RCC_D3CCIPR_I2C4SEL)
+#define LL_RCC_I2C4_CLKSOURCE_PCLK4            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_I2C4SEL,    RCC_D3CCIPR_I2C4SEL_Pos,    0x00000000U)
+#define LL_RCC_I2C4_CLKSOURCE_PLL3R            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_I2C4SEL,    RCC_D3CCIPR_I2C4SEL_Pos,    RCC_D3CCIPR_I2C4SEL_0)
+#define LL_RCC_I2C4_CLKSOURCE_HSI              LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_I2C4SEL,    RCC_D3CCIPR_I2C4SEL_Pos,    RCC_D3CCIPR_I2C4SEL_1)
+#define LL_RCC_I2C4_CLKSOURCE_CSI              LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_I2C4SEL,    RCC_D3CCIPR_I2C4SEL_Pos,    RCC_D3CCIPR_I2C4SEL_0 | RCC_D3CCIPR_I2C4SEL_1)
+#else
+#define LL_RCC_I2C4_CLKSOURCE_PCLK4            LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_I2C4SEL,    RCC_SRDCCIPR_I2C4SEL_Pos,    0x00000000U)
+#define LL_RCC_I2C4_CLKSOURCE_PLL3R            LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_I2C4SEL,    RCC_SRDCCIPR_I2C4SEL_Pos,    RCC_SRDCCIPR_I2C4SEL_0)
+#define LL_RCC_I2C4_CLKSOURCE_HSI              LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_I2C4SEL,    RCC_SRDCCIPR_I2C4SEL_Pos,    RCC_SRDCCIPR_I2C4SEL_1)
+#define LL_RCC_I2C4_CLKSOURCE_CSI              LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_I2C4SEL,    RCC_SRDCCIPR_I2C4SEL_Pos,    RCC_SRDCCIPR_I2C4SEL_0 | RCC_SRDCCIPR_I2C4SEL_1)
+#endif /* RCC_D3CCIPR_I2C4SEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_LPTIMx_CLKSOURCE  Peripheral LPTIM clock source selection
+  * @{
+  */
+#if defined(RCC_D2CCIP2R_LPTIM1SEL)
+#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1          LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL,  RCC_D2CCIP2R_LPTIM1SEL_Pos,  0x00000000U)
+#define LL_RCC_LPTIM1_CLKSOURCE_PLL2P          LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL,  RCC_D2CCIP2R_LPTIM1SEL_Pos,  RCC_D2CCIP2R_LPTIM1SEL_0)
+#define LL_RCC_LPTIM1_CLKSOURCE_PLL3R          LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL,  RCC_D2CCIP2R_LPTIM1SEL_Pos,  RCC_D2CCIP2R_LPTIM1SEL_1)
+#define LL_RCC_LPTIM1_CLKSOURCE_LSE            LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL,  RCC_D2CCIP2R_LPTIM1SEL_Pos,  RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_1)
+#define LL_RCC_LPTIM1_CLKSOURCE_LSI            LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL,  RCC_D2CCIP2R_LPTIM1SEL_Pos,  RCC_D2CCIP2R_LPTIM1SEL_2)
+#define LL_RCC_LPTIM1_CLKSOURCE_CLKP           LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL,  RCC_D2CCIP2R_LPTIM1SEL_Pos,  RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_2)
+#else
+#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1          LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL,  RCC_CDCCIP2R_LPTIM1SEL_Pos,  0x00000000U)
+#define LL_RCC_LPTIM1_CLKSOURCE_PLL2P          LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL,  RCC_CDCCIP2R_LPTIM1SEL_Pos,  RCC_CDCCIP2R_LPTIM1SEL_0)
+#define LL_RCC_LPTIM1_CLKSOURCE_PLL3R          LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL,  RCC_CDCCIP2R_LPTIM1SEL_Pos,  RCC_CDCCIP2R_LPTIM1SEL_1)
+#define LL_RCC_LPTIM1_CLKSOURCE_LSE            LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL,  RCC_CDCCIP2R_LPTIM1SEL_Pos,  RCC_CDCCIP2R_LPTIM1SEL_0 | RCC_CDCCIP2R_LPTIM1SEL_1)
+#define LL_RCC_LPTIM1_CLKSOURCE_LSI            LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL,  RCC_CDCCIP2R_LPTIM1SEL_Pos,  RCC_CDCCIP2R_LPTIM1SEL_2)
+#define LL_RCC_LPTIM1_CLKSOURCE_CLKP           LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL,  RCC_CDCCIP2R_LPTIM1SEL_Pos,  RCC_CDCCIP2R_LPTIM1SEL_0 | RCC_CDCCIP2R_LPTIM1SEL_2)
+#endif /* RCC_D2CCIP2R_LPTIM1SEL */
+#if defined(RCC_D3CCIPR_LPTIM2SEL)
+#define LL_RCC_LPTIM2_CLKSOURCE_PCLK4          LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM2SEL,   RCC_D3CCIPR_LPTIM2SEL_Pos,   0x00000000U)
+#define LL_RCC_LPTIM2_CLKSOURCE_PLL2P          LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM2SEL,   RCC_D3CCIPR_LPTIM2SEL_Pos,   RCC_D3CCIPR_LPTIM2SEL_0)
+#define LL_RCC_LPTIM2_CLKSOURCE_PLL3R          LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM2SEL,   RCC_D3CCIPR_LPTIM2SEL_Pos,   RCC_D3CCIPR_LPTIM2SEL_1)
+#define LL_RCC_LPTIM2_CLKSOURCE_LSE            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM2SEL,   RCC_D3CCIPR_LPTIM2SEL_Pos,   RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_1)
+#define LL_RCC_LPTIM2_CLKSOURCE_LSI            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM2SEL,   RCC_D3CCIPR_LPTIM2SEL_Pos,   RCC_D3CCIPR_LPTIM2SEL_2)
+#define LL_RCC_LPTIM2_CLKSOURCE_CLKP           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM2SEL,   RCC_D3CCIPR_LPTIM2SEL_Pos,   RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_2)
+#else
+#define LL_RCC_LPTIM2_CLKSOURCE_PCLK4          LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM2SEL,   RCC_SRDCCIPR_LPTIM2SEL_Pos,   0x00000000U)
+#define LL_RCC_LPTIM2_CLKSOURCE_PLL2P          LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM2SEL,   RCC_SRDCCIPR_LPTIM2SEL_Pos,   RCC_SRDCCIPR_LPTIM2SEL_0)
+#define LL_RCC_LPTIM2_CLKSOURCE_PLL3R          LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM2SEL,   RCC_SRDCCIPR_LPTIM2SEL_Pos,   RCC_SRDCCIPR_LPTIM2SEL_1)
+#define LL_RCC_LPTIM2_CLKSOURCE_LSE            LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM2SEL,   RCC_SRDCCIPR_LPTIM2SEL_Pos,   RCC_SRDCCIPR_LPTIM2SEL_0 | RCC_SRDCCIPR_LPTIM2SEL_1)
+#define LL_RCC_LPTIM2_CLKSOURCE_LSI            LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM2SEL,   RCC_SRDCCIPR_LPTIM2SEL_Pos,   RCC_SRDCCIPR_LPTIM2SEL_2)
+#define LL_RCC_LPTIM2_CLKSOURCE_CLKP           LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM2SEL,   RCC_SRDCCIPR_LPTIM2SEL_Pos,   RCC_SRDCCIPR_LPTIM2SEL_0 | RCC_SRDCCIPR_LPTIM2SEL_2)
+#endif /* RCC_D3CCIPR_LPTIM2SEL */
+#if defined(RCC_D3CCIPR_LPTIM345SEL)
+#define LL_RCC_LPTIM345_CLKSOURCE_PCLK4        LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, 0x00000000U)
+#define LL_RCC_LPTIM345_CLKSOURCE_PLL2P        LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_0)
+#define LL_RCC_LPTIM345_CLKSOURCE_PLL3R        LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_1)
+#define LL_RCC_LPTIM345_CLKSOURCE_LSE          LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_1)
+#define LL_RCC_LPTIM345_CLKSOURCE_LSI          LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_2)
+#define LL_RCC_LPTIM345_CLKSOURCE_CLKP         LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_2)
+#else
+#define LL_RCC_LPTIM345_CLKSOURCE_PCLK4        LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, 0x00000000U)
+#define LL_RCC_LPTIM345_CLKSOURCE_PLL2P        LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_0)
+#define LL_RCC_LPTIM345_CLKSOURCE_PLL3R        LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_1)
+#define LL_RCC_LPTIM345_CLKSOURCE_LSE          LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_1)
+#define LL_RCC_LPTIM345_CLKSOURCE_LSI          LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_2)
+#define LL_RCC_LPTIM345_CLKSOURCE_CLKP         LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_2)
+/* aliases*/
+#define LL_RCC_LPTIM3_CLKSOURCE_PCLK4          LL_RCC_LPTIM345_CLKSOURCE_PCLK4
+#define LL_RCC_LPTIM3_CLKSOURCE_PLL2P          LL_RCC_LPTIM345_CLKSOURCE_PLL2P
+#define LL_RCC_LPTIM3_CLKSOURCE_PLL3R          LL_RCC_LPTIM345_CLKSOURCE_PLL3R
+#define LL_RCC_LPTIM3_CLKSOURCE_LSE            LL_RCC_LPTIM345_CLKSOURCE_LSE
+#define LL_RCC_LPTIM3_CLKSOURCE_LSI            LL_RCC_LPTIM345_CLKSOURCE_LSI
+#define LL_RCC_LPTIM3_CLKSOURCE_CLKP           LL_RCC_LPTIM345_CLKSOURCE_CLKP
+#endif /* RCC_D3CCIPR_LPTIM345SEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_SAIx_CLKSOURCE  Peripheral SAI clock source selection
+  * @{
+  */
+#if defined(RCC_D2CCIP1R_SAI1SEL)
+#define LL_RCC_SAI1_CLKSOURCE_PLL1Q            LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL,  RCC_D2CCIP1R_SAI1SEL_Pos,  0x00000000U)
+#define LL_RCC_SAI1_CLKSOURCE_PLL2P            LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL,  RCC_D2CCIP1R_SAI1SEL_Pos,  RCC_D2CCIP1R_SAI1SEL_0)
+#define LL_RCC_SAI1_CLKSOURCE_PLL3P            LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL,  RCC_D2CCIP1R_SAI1SEL_Pos,  RCC_D2CCIP1R_SAI1SEL_1)
+#define LL_RCC_SAI1_CLKSOURCE_I2S_CKIN         LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL,  RCC_D2CCIP1R_SAI1SEL_Pos,  RCC_D2CCIP1R_SAI1SEL_0 | RCC_D2CCIP1R_SAI1SEL_1)
+#define LL_RCC_SAI1_CLKSOURCE_CLKP             LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL,  RCC_D2CCIP1R_SAI1SEL_Pos,  RCC_D2CCIP1R_SAI1SEL_2)
+#else
+#define LL_RCC_SAI1_CLKSOURCE_PLL1Q            LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL,  RCC_CDCCIP1R_SAI1SEL_Pos,  0x00000000U)
+#define LL_RCC_SAI1_CLKSOURCE_PLL2P            LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL,  RCC_CDCCIP1R_SAI1SEL_Pos,  RCC_CDCCIP1R_SAI1SEL_0)
+#define LL_RCC_SAI1_CLKSOURCE_PLL3P            LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL,  RCC_CDCCIP1R_SAI1SEL_Pos,  RCC_CDCCIP1R_SAI1SEL_1)
+#define LL_RCC_SAI1_CLKSOURCE_I2S_CKIN         LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL,  RCC_CDCCIP1R_SAI1SEL_Pos,  RCC_CDCCIP1R_SAI1SEL_0 | RCC_CDCCIP1R_SAI1SEL_1)
+#define LL_RCC_SAI1_CLKSOURCE_CLKP             LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL,  RCC_CDCCIP1R_SAI1SEL_Pos,  RCC_CDCCIP1R_SAI1SEL_2)
+#endif
+#if defined(SAI3)
+#define LL_RCC_SAI23_CLKSOURCE_PLL1Q           LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, 0x00000000U)
+#define LL_RCC_SAI23_CLKSOURCE_PLL2P           LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, RCC_D2CCIP1R_SAI23SEL_0)
+#define LL_RCC_SAI23_CLKSOURCE_PLL3P           LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, RCC_D2CCIP1R_SAI23SEL_1)
+#define LL_RCC_SAI23_CLKSOURCE_I2S_CKIN        LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, RCC_D2CCIP1R_SAI23SEL_0 | RCC_D2CCIP1R_SAI23SEL_1)
+#define LL_RCC_SAI23_CLKSOURCE_CLKP            LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, RCC_D2CCIP1R_SAI23SEL_2)
+#endif /* SAI3 */
+#if defined(RCC_CDCCIP1R_SAI2ASEL)
+#define LL_RCC_SAI2A_CLKSOURCE_PLL1Q           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2ASEL,  RCC_CDCCIP1R_SAI2ASEL_Pos,  0x00000000U)
+#define LL_RCC_SAI2A_CLKSOURCE_PLL2P           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2ASEL,  RCC_CDCCIP1R_SAI2ASEL_Pos,  RCC_CDCCIP1R_SAI2ASEL_0)
+#define LL_RCC_SAI2A_CLKSOURCE_PLL3P           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2ASEL,  RCC_CDCCIP1R_SAI2ASEL_Pos,  RCC_CDCCIP1R_SAI2ASEL_1)
+#define LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN        LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2ASEL,  RCC_CDCCIP1R_SAI2ASEL_Pos,  RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_1)
+#define LL_RCC_SAI2A_CLKSOURCE_CLKP            LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2ASEL,  RCC_CDCCIP1R_SAI2ASEL_Pos,  RCC_CDCCIP1R_SAI2ASEL_2)
+#define LL_RCC_SAI2A_CLKSOURCE_SPDIF           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2ASEL,  RCC_CDCCIP1R_SAI2ASEL_Pos,  RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_2)
+#endif /* RCC_CDCCIP1R_SAI2ASEL */
+#if defined(RCC_CDCCIP1R_SAI2BSEL)
+#define LL_RCC_SAI2B_CLKSOURCE_PLL1Q           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2BSEL,  RCC_CDCCIP1R_SAI2BSEL_Pos,  0x00000000U)
+#define LL_RCC_SAI2B_CLKSOURCE_PLL2P           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2BSEL,  RCC_CDCCIP1R_SAI2BSEL_Pos,  RCC_CDCCIP1R_SAI2BSEL_0)
+#define LL_RCC_SAI2B_CLKSOURCE_PLL3P           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2BSEL,  RCC_CDCCIP1R_SAI2BSEL_Pos,  RCC_CDCCIP1R_SAI2BSEL_1)
+#define LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN        LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2BSEL,  RCC_CDCCIP1R_SAI2BSEL_Pos,  RCC_CDCCIP1R_SAI2BSEL_0 | RCC_CDCCIP1R_SAI2BSEL_1)
+#define LL_RCC_SAI2B_CLKSOURCE_CLKP            LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2BSEL,  RCC_CDCCIP1R_SAI2BSEL_Pos,  RCC_CDCCIP1R_SAI2BSEL_2)
+#define LL_RCC_SAI2B_CLKSOURCE_SPDIF           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2BSEL,  RCC_CDCCIP1R_SAI2BSEL_Pos,  RCC_CDCCIP1R_SAI2BSEL_0 | RCC_CDCCIP1R_SAI2BSEL_2)
+#endif /* RCC_CDCCIP1R_SAI2BSEL */
+#if defined(SAI4_Block_A)
+#define LL_RCC_SAI4A_CLKSOURCE_PLL1Q           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4ASEL,  RCC_D3CCIPR_SAI4ASEL_Pos,  0x00000000U)
+#define LL_RCC_SAI4A_CLKSOURCE_PLL2P           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4ASEL,  RCC_D3CCIPR_SAI4ASEL_Pos,  RCC_D3CCIPR_SAI4ASEL_0)
+#define LL_RCC_SAI4A_CLKSOURCE_PLL3P           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4ASEL,  RCC_D3CCIPR_SAI4ASEL_Pos,  RCC_D3CCIPR_SAI4ASEL_1)
+#define LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN        LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4ASEL,  RCC_D3CCIPR_SAI4ASEL_Pos,  RCC_D3CCIPR_SAI4ASEL_0 | RCC_D3CCIPR_SAI4ASEL_1)
+#define LL_RCC_SAI4A_CLKSOURCE_CLKP            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4ASEL,  RCC_D3CCIPR_SAI4ASEL_Pos,  RCC_D3CCIPR_SAI4ASEL_2)
+#if defined(RCC_VER_3_0)
+#define LL_RCC_SAI4A_CLKSOURCE_SPDIF           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4ASEL,  RCC_D3CCIPR_SAI4ASEL_Pos,  RCC_D3CCIPR_SAI4ASEL_2 | RCC_D3CCIPR_SAI4ASEL_0)
+#endif /* RCC_VER_3_0 */
+#endif /* SAI4_Block_A */
+#if defined(SAI4_Block_B)
+#define LL_RCC_SAI4B_CLKSOURCE_PLL1Q           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4BSEL,  RCC_D3CCIPR_SAI4BSEL_Pos,  0x00000000U)
+#define LL_RCC_SAI4B_CLKSOURCE_PLL2P           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4BSEL,  RCC_D3CCIPR_SAI4BSEL_Pos,  RCC_D3CCIPR_SAI4BSEL_0)
+#define LL_RCC_SAI4B_CLKSOURCE_PLL3P           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4BSEL,  RCC_D3CCIPR_SAI4BSEL_Pos,  RCC_D3CCIPR_SAI4BSEL_1)
+#define LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN        LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4BSEL,  RCC_D3CCIPR_SAI4BSEL_Pos,  RCC_D3CCIPR_SAI4BSEL_0 | RCC_D3CCIPR_SAI4BSEL_1)
+#define LL_RCC_SAI4B_CLKSOURCE_CLKP            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4BSEL,  RCC_D3CCIPR_SAI4BSEL_Pos,  RCC_D3CCIPR_SAI4BSEL_2)
+#if defined(RCC_VER_3_0)
+#define LL_RCC_SAI4B_CLKSOURCE_SPDIF           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4BSEL,  RCC_D3CCIPR_SAI4BSEL_Pos,  RCC_D3CCIPR_SAI4BSEL_2 | RCC_D3CCIPR_SAI4BSEL_0)
+#endif /* RCC_VER_3_0 */
+#endif /* SAI4_Block_B */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_SDMMC_CLKSOURCE  Peripheral SDMMC clock source selection
+  * @{
+  */
+#if defined(RCC_D1CCIPR_SDMMCSEL)
+#define LL_RCC_SDMMC_CLKSOURCE_PLL1Q           (0x00000000U)
+#define LL_RCC_SDMMC_CLKSOURCE_PLL2R           (RCC_D1CCIPR_SDMMCSEL)
+#else
+#define LL_RCC_SDMMC_CLKSOURCE_PLL1Q           (0x00000000U)
+#define LL_RCC_SDMMC_CLKSOURCE_PLL2R           (RCC_CDCCIPR_SDMMCSEL)
+#endif /* RCC_D1CCIPR_SDMMCSEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_RNG_CLKSOURCE  Peripheral RNG clock source selection
+  * @{
+  */
+#if defined(RCC_D2CCIP2R_RNGSEL)
+#define LL_RCC_RNG_CLKSOURCE_HSI48             (0x00000000U)
+#define LL_RCC_RNG_CLKSOURCE_PLL1Q             (RCC_D2CCIP2R_RNGSEL_0)
+#define LL_RCC_RNG_CLKSOURCE_LSE               (RCC_D2CCIP2R_RNGSEL_1)
+#define LL_RCC_RNG_CLKSOURCE_LSI               (RCC_D2CCIP2R_RNGSEL_1 | RCC_D2CCIP2R_RNGSEL_0)
+#else
+#define LL_RCC_RNG_CLKSOURCE_HSI48             (0x00000000U)
+#define LL_RCC_RNG_CLKSOURCE_PLL1Q             (RCC_CDCCIP2R_RNGSEL_0)
+#define LL_RCC_RNG_CLKSOURCE_LSE               (RCC_CDCCIP2R_RNGSEL_1)
+#define LL_RCC_RNG_CLKSOURCE_LSI               (RCC_CDCCIP2R_RNGSEL_1 | RCC_CDCCIP2R_RNGSEL_0)
+#endif /* RCC_D2CCIP2R_RNGSEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_USB_CLKSOURCE  Peripheral USB clock source selection
+  * @{
+  */
+#if defined(RCC_D2CCIP2R_USBSEL)
+#define LL_RCC_USB_CLKSOURCE_DISABLE           (0x00000000U)
+#define LL_RCC_USB_CLKSOURCE_PLL1Q             (RCC_D2CCIP2R_USBSEL_0)
+#define LL_RCC_USB_CLKSOURCE_PLL3Q             (RCC_D2CCIP2R_USBSEL_1)
+#define LL_RCC_USB_CLKSOURCE_HSI48             (RCC_D2CCIP2R_USBSEL_1 | RCC_D2CCIP2R_USBSEL_0)
+#else
+#define LL_RCC_USB_CLKSOURCE_DISABLE           (0x00000000U)
+#define LL_RCC_USB_CLKSOURCE_PLL1Q             (RCC_CDCCIP2R_USBSEL_0)
+#define LL_RCC_USB_CLKSOURCE_PLL3Q             (RCC_CDCCIP2R_USBSEL_1)
+#define LL_RCC_USB_CLKSOURCE_HSI48             (RCC_CDCCIP2R_USBSEL_1 | RCC_CDCCIP2R_USBSEL_0)
+#endif /* RCC_D2CCIP2R_USBSEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_CEC_CLKSOURCE  Peripheral CEC clock source selection
+  * @{
+  */
+#if defined(RCC_D2CCIP2R_CECSEL)
+#define LL_RCC_CEC_CLKSOURCE_LSE               (0x00000000U)
+#define LL_RCC_CEC_CLKSOURCE_LSI               (RCC_D2CCIP2R_CECSEL_0)
+#define LL_RCC_CEC_CLKSOURCE_CSI_DIV122        (RCC_D2CCIP2R_CECSEL_1)
+#else
+#define LL_RCC_CEC_CLKSOURCE_LSE               (0x00000000U)
+#define LL_RCC_CEC_CLKSOURCE_LSI               (RCC_CDCCIP2R_CECSEL_0)
+#define LL_RCC_CEC_CLKSOURCE_CSI_DIV122        (RCC_CDCCIP2R_CECSEL_1)
+#endif
+/**
+  * @}
+  */
+
+#if defined(DSI)
+/** @defgroup RCC_LL_EC_DSI_CLKSOURCE  Peripheral DSI clock source selection
+  * @{
+  */
+#define LL_RCC_DSI_CLKSOURCE_PHY               (0x00000000U)
+#define LL_RCC_DSI_CLKSOURCE_PLL2Q             (RCC_D1CCIPR_DSISEL)
+/**
+  * @}
+  */
+#endif /* DSI */
+
+/** @defgroup RCC_LL_EC_DFSDM_CLKSOURCE  Peripheral DFSDM clock source selection
+  * @{
+  */
+#if defined(RCC_D2CCIP1R_DFSDM1SEL)
+#define LL_RCC_DFSDM1_CLKSOURCE_PCLK2          (0x00000000U)
+#define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK         (RCC_D2CCIP1R_DFSDM1SEL)
+#else
+#define LL_RCC_DFSDM1_CLKSOURCE_PCLK2          (0x00000000U)
+#define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK         (RCC_CDCCIP1R_DFSDM1SEL)
+#endif /* RCC_D2CCIP1R_DFSDM1SEL */
+/**
+  * @}
+  */
+
+#if defined(DFSDM2_BASE)
+/** @defgroup RCC_LL_EC_DFSDM2_CLKSOURCE  Peripheral DFSDM2 clock source selection
+  * @{
+  */
+#define LL_RCC_DFSDM2_CLKSOURCE_PCLK4          (0x00000000U)
+#define LL_RCC_DFSDM2_CLKSOURCE_SYSCLK         (RCC_SRDCCIPR_DFSDM2SEL)
+/**
+  * @}
+  */
+#endif /* DFSDM2_BASE */
+
+/** @defgroup RCC_LL_EC_FMC_CLKSOURCE  Peripheral FMC clock source selection
+  * @{
+  */
+#if defined(RCC_D1CCIPR_FMCSEL)
+#define LL_RCC_FMC_CLKSOURCE_HCLK              (0x00000000U)
+#define LL_RCC_FMC_CLKSOURCE_PLL1Q             (RCC_D1CCIPR_FMCSEL_0)
+#define LL_RCC_FMC_CLKSOURCE_PLL2R             (RCC_D1CCIPR_FMCSEL_1)
+#define LL_RCC_FMC_CLKSOURCE_CLKP              (RCC_D1CCIPR_FMCSEL_0 | RCC_D1CCIPR_FMCSEL_1)
+#else
+#define LL_RCC_FMC_CLKSOURCE_HCLK              (0x00000000U)
+#define LL_RCC_FMC_CLKSOURCE_PLL1Q             (RCC_CDCCIPR_FMCSEL_0)
+#define LL_RCC_FMC_CLKSOURCE_PLL2R             (RCC_CDCCIPR_FMCSEL_1)
+#define LL_RCC_FMC_CLKSOURCE_CLKP              (RCC_CDCCIPR_FMCSEL_0 | RCC_CDCCIPR_FMCSEL_1)
+#endif /* RCC_D1CCIPR_FMCSEL */
+/**
+  * @}
+  */
+
+#if defined(QUADSPI)
+/** @defgroup RCC_LL_EC_QSPI_CLKSOURCE  Peripheral QSPI clock source selection
+  * @{
+  */
+#define LL_RCC_QSPI_CLKSOURCE_HCLK             (0x00000000U)
+#define LL_RCC_QSPI_CLKSOURCE_PLL1Q            (RCC_D1CCIPR_QSPISEL_0)
+#define LL_RCC_QSPI_CLKSOURCE_PLL2R            (RCC_D1CCIPR_QSPISEL_1)
+#define LL_RCC_QSPI_CLKSOURCE_CLKP             (RCC_D1CCIPR_QSPISEL_0 | RCC_D1CCIPR_QSPISEL_1)
+/**
+  * @}
+  */
+#endif /* QUADSPI */
+
+
+#if defined(OCTOSPI1) || defined(OCTOSPI2)
+/** @defgroup RCC_LL_EC_OSPI_CLKSOURCE  Peripheral OSPI clock source selection
+  * @{
+  */
+#if defined(RCC_D1CCIPR_OCTOSPISEL)
+#define LL_RCC_OSPI_CLKSOURCE_HCLK             (0x00000000U)
+#define LL_RCC_OSPI_CLKSOURCE_PLL1Q            (RCC_D1CCIPR_OCTOSPISEL_0)
+#define LL_RCC_OSPI_CLKSOURCE_PLL2R            (RCC_D1CCIPR_OCTOSPISEL_1)
+#define LL_RCC_OSPI_CLKSOURCE_CLKP             (RCC_D1CCIPR_OCTOSPISEL_0 | RCC_D1CCIPR_OCTOSPISEL_1)
+#else
+#define LL_RCC_OSPI_CLKSOURCE_HCLK             (0x00000000U)
+#define LL_RCC_OSPI_CLKSOURCE_PLL1Q            (RCC_CDCCIPR_OCTOSPISEL_0)
+#define LL_RCC_OSPI_CLKSOURCE_PLL2R            (RCC_CDCCIPR_OCTOSPISEL_1)
+#define LL_RCC_OSPI_CLKSOURCE_CLKP             (RCC_CDCCIPR_OCTOSPISEL_0 | RCC_CDCCIPR_OCTOSPISEL_1)
+#endif /* RCC_D1CCIPR_OCTOSPISEL */
+/**
+  * @}
+  */
+#endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */
+
+
+/** @defgroup RCC_LL_EC_CLKP_CLKSOURCE  Peripheral CLKP clock source selection
+  * @{
+  */
+#if defined(RCC_D1CCIPR_CKPERSEL)
+#define LL_RCC_CLKP_CLKSOURCE_HSI              (0x00000000U)
+#define LL_RCC_CLKP_CLKSOURCE_CSI              (RCC_D1CCIPR_CKPERSEL_0)
+#define LL_RCC_CLKP_CLKSOURCE_HSE              (RCC_D1CCIPR_CKPERSEL_1)
+#else
+#define LL_RCC_CLKP_CLKSOURCE_HSI              (0x00000000U)
+#define LL_RCC_CLKP_CLKSOURCE_CSI              (RCC_CDCCIPR_CKPERSEL_0)
+#define LL_RCC_CLKP_CLKSOURCE_HSE              (RCC_CDCCIPR_CKPERSEL_1)
+#endif /* RCC_D1CCIPR_CKPERSEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_SPIx_CLKSOURCE  Peripheral SPI clock source selection
+  * @{
+  */
+#if defined(RCC_D2CCIP1R_SPI123SEL)
+#define LL_RCC_SPI123_CLKSOURCE_PLL1Q          LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, 0x00000000U)
+#define LL_RCC_SPI123_CLKSOURCE_PLL2P          LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, RCC_D2CCIP1R_SPI123SEL_0)
+#define LL_RCC_SPI123_CLKSOURCE_PLL3P          LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, RCC_D2CCIP1R_SPI123SEL_1)
+#define LL_RCC_SPI123_CLKSOURCE_I2S_CKIN       LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, RCC_D2CCIP1R_SPI123SEL_0 | RCC_D2CCIP1R_SPI123SEL_1)
+#define LL_RCC_SPI123_CLKSOURCE_CLKP           LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, RCC_D2CCIP1R_SPI123SEL_2)
+#else
+#define LL_RCC_SPI123_CLKSOURCE_PLL1Q          LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, 0x00000000U)
+#define LL_RCC_SPI123_CLKSOURCE_PLL2P          LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, RCC_CDCCIP1R_SPI123SEL_0)
+#define LL_RCC_SPI123_CLKSOURCE_PLL3P          LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, RCC_CDCCIP1R_SPI123SEL_1)
+#define LL_RCC_SPI123_CLKSOURCE_I2S_CKIN       LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, RCC_CDCCIP1R_SPI123SEL_0 | RCC_CDCCIP1R_SPI123SEL_1)
+#define LL_RCC_SPI123_CLKSOURCE_CLKP           LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, RCC_CDCCIP1R_SPI123SEL_2)
+#endif /* RCC_D2CCIP1R_SPI123SEL */
+#if defined(RCC_D2CCIP1R_SPI45SEL)
+#define LL_RCC_SPI45_CLKSOURCE_PCLK2           LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL,  RCC_D2CCIP1R_SPI45SEL_Pos,  0x00000000U)
+#define LL_RCC_SPI45_CLKSOURCE_PLL2Q           LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL,  RCC_D2CCIP1R_SPI45SEL_Pos,  RCC_D2CCIP1R_SPI45SEL_0)
+#define LL_RCC_SPI45_CLKSOURCE_PLL3Q           LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL,  RCC_D2CCIP1R_SPI45SEL_Pos,  RCC_D2CCIP1R_SPI45SEL_1)
+#define LL_RCC_SPI45_CLKSOURCE_HSI             LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL,  RCC_D2CCIP1R_SPI45SEL_Pos,  RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_1)
+#define LL_RCC_SPI45_CLKSOURCE_CSI             LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL,  RCC_D2CCIP1R_SPI45SEL_Pos,  RCC_D2CCIP1R_SPI45SEL_2)
+#define LL_RCC_SPI45_CLKSOURCE_HSE             LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL,  RCC_D2CCIP1R_SPI45SEL_Pos,  RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_2)
+#else
+#define LL_RCC_SPI45_CLKSOURCE_PCLK2           LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL,  RCC_CDCCIP1R_SPI45SEL_Pos,  0x00000000U)
+#define LL_RCC_SPI45_CLKSOURCE_PLL2Q           LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL,  RCC_CDCCIP1R_SPI45SEL_Pos,  RCC_CDCCIP1R_SPI45SEL_0)
+#define LL_RCC_SPI45_CLKSOURCE_PLL3Q           LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL,  RCC_CDCCIP1R_SPI45SEL_Pos,  RCC_CDCCIP1R_SPI45SEL_1)
+#define LL_RCC_SPI45_CLKSOURCE_HSI             LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL,  RCC_CDCCIP1R_SPI45SEL_Pos,  RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_1)
+#define LL_RCC_SPI45_CLKSOURCE_CSI             LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL,  RCC_CDCCIP1R_SPI45SEL_Pos,  RCC_CDCCIP1R_SPI45SEL_2)
+#define LL_RCC_SPI45_CLKSOURCE_HSE             LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL,  RCC_CDCCIP1R_SPI45SEL_Pos,  RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_2)
+#endif /* (RCC_D2CCIP1R_SPI45SEL */
+#if defined(RCC_D3CCIPR_SPI6SEL)
+#define LL_RCC_SPI6_CLKSOURCE_PCLK4            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SPI6SEL,    RCC_D3CCIPR_SPI6SEL_Pos,    0x00000000U)
+#define LL_RCC_SPI6_CLKSOURCE_PLL2Q            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SPI6SEL,    RCC_D3CCIPR_SPI6SEL_Pos,    RCC_D3CCIPR_SPI6SEL_0)
+#define LL_RCC_SPI6_CLKSOURCE_PLL3Q            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SPI6SEL,    RCC_D3CCIPR_SPI6SEL_Pos,    RCC_D3CCIPR_SPI6SEL_1)
+#define LL_RCC_SPI6_CLKSOURCE_HSI              LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SPI6SEL,    RCC_D3CCIPR_SPI6SEL_Pos,    RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_1)
+#define LL_RCC_SPI6_CLKSOURCE_CSI              LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SPI6SEL,    RCC_D3CCIPR_SPI6SEL_Pos,    RCC_D3CCIPR_SPI6SEL_2)
+#define LL_RCC_SPI6_CLKSOURCE_HSE              LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SPI6SEL,    RCC_D3CCIPR_SPI6SEL_Pos,    RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_2)
+#else
+#define LL_RCC_SPI6_CLKSOURCE_PCLK4            LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_SPI6SEL,    RCC_SRDCCIPR_SPI6SEL_Pos,    0x00000000U)
+#define LL_RCC_SPI6_CLKSOURCE_PLL2Q            LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_SPI6SEL,    RCC_SRDCCIPR_SPI6SEL_Pos,    RCC_SRDCCIPR_SPI6SEL_0)
+#define LL_RCC_SPI6_CLKSOURCE_PLL3Q            LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_SPI6SEL,    RCC_SRDCCIPR_SPI6SEL_Pos,    RCC_SRDCCIPR_SPI6SEL_1)
+#define LL_RCC_SPI6_CLKSOURCE_HSI              LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_SPI6SEL,    RCC_SRDCCIPR_SPI6SEL_Pos,    RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_1)
+#define LL_RCC_SPI6_CLKSOURCE_CSI              LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_SPI6SEL,    RCC_SRDCCIPR_SPI6SEL_Pos,    RCC_SRDCCIPR_SPI6SEL_2)
+#define LL_RCC_SPI6_CLKSOURCE_HSE              LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_SPI6SEL,    RCC_SRDCCIPR_SPI6SEL_Pos,    RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_2)
+#define LL_RCC_SPI6_CLKSOURCE_I2S_CKIN         LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_SPI6SEL,    RCC_SRDCCIPR_SPI6SEL_Pos,    RCC_SRDCCIPR_SPI6SEL_1 | RCC_SRDCCIPR_SPI6SEL_2)
+#endif /* RCC_D3CCIPR_SPI6SEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_SPDIF_CLKSOURCE  Peripheral SPDIF clock source selection
+  * @{
+  */
+#if defined(RCC_D2CCIP1R_SPDIFSEL)
+#define LL_RCC_SPDIF_CLKSOURCE_PLL1Q           (0x00000000U)
+#define LL_RCC_SPDIF_CLKSOURCE_PLL2R           (RCC_D2CCIP1R_SPDIFSEL_0)
+#define LL_RCC_SPDIF_CLKSOURCE_PLL3R           (RCC_D2CCIP1R_SPDIFSEL_1)
+#define LL_RCC_SPDIF_CLKSOURCE_HSI             (RCC_D2CCIP1R_SPDIFSEL_0 | RCC_D2CCIP1R_SPDIFSEL_1)
+#else
+#define LL_RCC_SPDIF_CLKSOURCE_PLL1Q           (0x00000000U)
+#define LL_RCC_SPDIF_CLKSOURCE_PLL2R           (RCC_CDCCIP1R_SPDIFSEL_0)
+#define LL_RCC_SPDIF_CLKSOURCE_PLL3R           (RCC_CDCCIP1R_SPDIFSEL_1)
+#define LL_RCC_SPDIF_CLKSOURCE_HSI             (RCC_CDCCIP1R_SPDIFSEL_0 | RCC_CDCCIP1R_SPDIFSEL_1)
+#endif /* RCC_D2CCIP1R_SPDIFSEL */
+/**
+  * @}
+  */
+
+#if defined(FDCAN1) || defined(FDCAN2)
+/** @defgroup RCC_LL_EC_FDCAN_CLKSOURCE  Peripheral FDCAN clock source selection
+  * @{
+  */
+#if defined(RCC_D2CCIP1R_FDCANSEL)
+#define LL_RCC_FDCAN_CLKSOURCE_HSE             (0x00000000U)
+#define LL_RCC_FDCAN_CLKSOURCE_PLL1Q           (RCC_D2CCIP1R_FDCANSEL_0)
+#define LL_RCC_FDCAN_CLKSOURCE_PLL2Q           (RCC_D2CCIP1R_FDCANSEL_1)
+#else
+#define LL_RCC_FDCAN_CLKSOURCE_HSE             (0x00000000U)
+#define LL_RCC_FDCAN_CLKSOURCE_PLL1Q           (RCC_CDCCIP1R_FDCANSEL_0)
+#define LL_RCC_FDCAN_CLKSOURCE_PLL2Q           (RCC_CDCCIP1R_FDCANSEL_1)
+#endif /* RCC_D2CCIP1R_FDCANSEL */
+/**
+  * @}
+  */
+#endif /*FDCAN1 || FDCAN2*/
+
+/** @defgroup RCC_LL_EC_SWP_CLKSOURCE  Peripheral SWP clock source selection
+  * @{
+  */
+#if defined(RCC_D2CCIP1R_SWPSEL)
+#define LL_RCC_SWP_CLKSOURCE_PCLK1             (0x00000000U)
+#define LL_RCC_SWP_CLKSOURCE_HSI               (RCC_D2CCIP1R_SWPSEL)
+#else
+#define LL_RCC_SWP_CLKSOURCE_PCLK1             (0x00000000U)
+#define LL_RCC_SWP_CLKSOURCE_HSI               (RCC_CDCCIP1R_SWPSEL)
+#endif /* RCC_D2CCIP1R_SWPSEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_ADC_CLKSOURCE  Peripheral ADC clock source selection
+  * @{
+  */
+#if defined(RCC_D3CCIPR_ADCSEL)
+#define LL_RCC_ADC_CLKSOURCE_PLL2P             (0x00000000U)
+#define LL_RCC_ADC_CLKSOURCE_PLL3R             (RCC_D3CCIPR_ADCSEL_0)
+#define LL_RCC_ADC_CLKSOURCE_CLKP              (RCC_D3CCIPR_ADCSEL_1)
+#else
+#define LL_RCC_ADC_CLKSOURCE_PLL2P             (0x00000000U)
+#define LL_RCC_ADC_CLKSOURCE_PLL3R             (RCC_SRDCCIPR_ADCSEL_0)
+#define LL_RCC_ADC_CLKSOURCE_CLKP              (RCC_SRDCCIPR_ADCSEL_1)
+#endif /* RCC_D3CCIPR_ADCSEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_USARTx  Peripheral USART get clock source
+  * @{
+  */
+#if defined (RCC_D2CCIP2R_USART16SEL)
+#define LL_RCC_USART16_CLKSOURCE         LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, 0x00000000U)
+#elif defined (RCC_D2CCIP2R_USART16910SEL)
+#define LL_RCC_USART16_CLKSOURCE         LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, 0x00000000U)
+/* alias*/
+#define LL_RCC_USART16910_CLKSOURCE      LL_RCC_USART16_CLKSOURCE
+#else
+#define LL_RCC_USART16_CLKSOURCE         LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, 0x00000000U)
+/* alias*/
+#define LL_RCC_USART16910_CLKSOURCE      LL_RCC_USART16_CLKSOURCE
+#endif /* RCC_D2CCIP2R_USART16SEL */
+#if defined (RCC_D2CCIP2R_USART28SEL)
+#define LL_RCC_USART234578_CLKSOURCE     LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, 0x00000000U)
+#else
+#define LL_RCC_USART234578_CLKSOURCE     LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, 0x00000000U)
+#endif /* RCC_D2CCIP2R_USART28SEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_LPUARTx  Peripheral LPUART get clock source
+  * @{
+  */
+#if defined(RCC_D3CCIPR_LPUART1SEL)
+#define LL_RCC_LPUART1_CLKSOURCE         RCC_D3CCIPR_LPUART1SEL
+#else
+#define LL_RCC_LPUART1_CLKSOURCE         RCC_SRDCCIPR_LPUART1SEL
+#endif /* RCC_D3CCIPR_LPUART1SEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_I2Cx  Peripheral I2C get clock source
+  * @{
+  */
+#if defined(RCC_D2CCIP2R_I2C123SEL)
+#define LL_RCC_I2C123_CLKSOURCE          LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, 0x00000000U)
+/* alias */
+#define LL_RCC_I2C1235_CLKSOURCE         LL_RCC_I2C123_CLKSOURCE
+#elif defined(RCC_D2CCIP2R_I2C1235SEL)
+#define LL_RCC_I2C1235_CLKSOURCE         LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C1235SEL, RCC_D2CCIP2R_I2C1235SEL_Pos, 0x00000000U)
+/* alias */
+#define LL_RCC_I2C123_CLKSOURCE          LL_RCC_I2C1235_CLKSOURCE
+#else
+#define LL_RCC_I2C123_CLKSOURCE          LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, 0x00000000U)
+/* alias */
+#define LL_RCC_I2C1235_CLKSOURCE         LL_RCC_I2C123_CLKSOURCE
+#endif /* RCC_D2CCIP2R_I2C123SEL */
+#if defined(RCC_D3CCIPR_I2C4SEL)
+#define LL_RCC_I2C4_CLKSOURCE            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_I2C4SEL,    RCC_D3CCIPR_I2C4SEL_Pos,    0x00000000U)
+#else
+#define LL_RCC_I2C4_CLKSOURCE            LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_I2C4SEL,   RCC_SRDCCIPR_I2C4SEL_Pos,   0x00000000U)
+#endif /* RCC_D3CCIPR_I2C4SEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_LPTIMx  Peripheral LPTIM get clock source
+  * @{
+  */
+#if defined(RCC_D2CCIP2R_LPTIM1SEL)
+#define LL_RCC_LPTIM1_CLKSOURCE          LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL,  RCC_D2CCIP2R_LPTIM1SEL_Pos,      0x00000000U)
+#else
+#define LL_RCC_LPTIM1_CLKSOURCE          LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL,  RCC_CDCCIP2R_LPTIM1SEL_Pos,      0x00000000U)
+#endif /* RCC_D2CCIP2R_LPTIM1SEL) */
+#if defined(RCC_D3CCIPR_LPTIM2SEL)
+#define LL_RCC_LPTIM2_CLKSOURCE          LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM2SEL,   RCC_D3CCIPR_LPTIM2SEL_Pos,       0x00000000U)
+#else
+#define LL_RCC_LPTIM2_CLKSOURCE          LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL,  RCC_SRDCCIPR_LPTIM2SEL_Pos,      0x00000000U)
+#endif /* RCC_D3CCIPR_LPTIM2SEL */
+#if defined(RCC_D3CCIPR_LPTIM345SEL)
+#define LL_RCC_LPTIM345_CLKSOURCE        LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos,     0x00000000U)
+#else
+#define LL_RCC_LPTIM345_CLKSOURCE        LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos,      0x00000000U)
+#define LL_RCC_LPTIM3_CLKSOURCE          LL_RCC_LPTIM345_CLKSOURCE  /* alias */
+#endif /* RCC_D3CCIPR_LPTIM345SEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_SAIx  Peripheral SAI get clock source
+  * @{
+  */
+#if defined(RCC_D2CCIP1R_SAI1SEL)
+#define LL_RCC_SAI1_CLKSOURCE            LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL,  RCC_D2CCIP1R_SAI1SEL_Pos,  0x00000000U)
+#else
+#define LL_RCC_SAI1_CLKSOURCE            LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL,  RCC_CDCCIP1R_SAI1SEL_Pos,  0x00000000U)
+#endif /* RCC_D2CCIP1R_SAI1SEL */
+#if defined(RCC_D2CCIP1R_SAI23SEL)
+#define LL_RCC_SAI23_CLKSOURCE           LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, 0x00000000U)
+#endif /* RCC_D2CCIP1R_SAI23SEL */
+#if defined(RCC_CDCCIP1R_SAI2ASEL)
+#define LL_RCC_SAI2A_CLKSOURCE           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2ASEL,  RCC_CDCCIP1R_SAI2ASEL_Pos,  0x00000000U)
+#endif /* RCC_CDCCIP1R_SAI2ASEL */
+#if defined(RCC_CDCCIP1R_SAI2BSEL)
+#define LL_RCC_SAI2B_CLKSOURCE           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2BSEL,  RCC_CDCCIP1R_SAI2BSEL_Pos,  0x00000000U)
+#endif /*  RCC_CDCCIP1R_SAI2BSEL */
+#if defined(RCC_D3CCIPR_SAI4ASEL)
+#define LL_RCC_SAI4A_CLKSOURCE           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4ASEL,  RCC_D3CCIPR_SAI4ASEL_Pos,  0x00000000U)
+#endif /* RCC_D3CCIPR_SAI4ASEL */
+#if defined(RCC_D3CCIPR_SAI4BSEL)
+#define LL_RCC_SAI4B_CLKSOURCE           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4BSEL,  RCC_D3CCIPR_SAI4BSEL_Pos,  0x00000000U)
+#endif /*  RCC_D3CCIPR_SAI4BSEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_SDMMC  Peripheral SDMMC get clock source
+  * @{
+  */
+#if defined(RCC_D1CCIPR_SDMMCSEL)
+#define LL_RCC_SDMMC_CLKSOURCE           RCC_D1CCIPR_SDMMCSEL
+#else
+#define LL_RCC_SDMMC_CLKSOURCE           RCC_CDCCIPR_SDMMCSEL
+#endif /* RCC_D1CCIPR_SDMMCSEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source
+  * @{
+  */
+#if (RCC_D2CCIP2R_RNGSEL)
+#define LL_RCC_RNG_CLKSOURCE             RCC_D2CCIP2R_RNGSEL
+#else
+#define LL_RCC_RNG_CLKSOURCE             RCC_CDCCIP2R_RNGSEL
+#endif /* RCC_D2CCIP2R_RNGSEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_USB  Peripheral USB get clock source
+  * @{
+  */
+#if (RCC_D2CCIP2R_USBSEL)
+#define LL_RCC_USB_CLKSOURCE             RCC_D2CCIP2R_USBSEL
+#else
+#define LL_RCC_USB_CLKSOURCE             RCC_CDCCIP2R_USBSEL
+#endif  /* RCC_D2CCIP2R_USBSEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_CEC  Peripheral CEC get clock source
+  * @{
+  */
+#if (RCC_D2CCIP2R_CECSEL)
+#define LL_RCC_CEC_CLKSOURCE             RCC_D2CCIP2R_CECSEL
+#else
+#define LL_RCC_CEC_CLKSOURCE             RCC_CDCCIP2R_CECSEL
+#endif /* RCC_D2CCIP2R_CECSEL */
+/**
+  * @}
+  */
+
+#if defined(DSI)
+/** @defgroup RCC_LL_EC_DSI  Peripheral DSI get clock source
+  * @{
+  */
+#define LL_RCC_DSI_CLKSOURCE             RCC_D1CCIPR_DSISEL
+/**
+  * @}
+  */
+#endif /* DSI */
+
+/** @defgroup RCC_LL_EC_DFSDM  Peripheral DFSDM get clock source
+  * @{
+  */
+#if defined(RCC_D2CCIP1R_DFSDM1SEL)
+#define LL_RCC_DFSDM1_CLKSOURCE          RCC_D2CCIP1R_DFSDM1SEL
+#else
+#define LL_RCC_DFSDM1_CLKSOURCE          RCC_CDCCIP1R_DFSDM1SEL
+#endif /* RCC_D2CCIP1R_DFSDM1SEL */
+/**
+  * @}
+  */
+
+#if defined(DFSDM2_BASE)
+/** @defgroup RCC_LL_EC_DFSDM2  Peripheral DFSDM2 get clock source
+  * @{
+  */
+#define LL_RCC_DFSDM2_CLKSOURCE          RCC_SRDCCIPR_DFSDM2SEL
+/**
+  * @}
+  */
+#endif /* DFSDM2_BASE */
+
+
+
+/** @defgroup RCC_LL_EC_FMC  Peripheral FMC get clock source
+  * @{
+  */
+#if defined(RCC_D1CCIPR_FMCSEL)
+#define LL_RCC_FMC_CLKSOURCE             RCC_D1CCIPR_FMCSEL
+#else
+#define LL_RCC_FMC_CLKSOURCE             RCC_CDCCIPR_FMCSEL
+#endif
+/**
+  * @}
+  */
+
+#if defined(QUADSPI)
+/** @defgroup RCC_LL_EC_QSPI  Peripheral QSPI get clock source
+  * @{
+  */
+#define LL_RCC_QSPI_CLKSOURCE            RCC_D1CCIPR_QSPISEL
+/**
+  * @}
+  */
+#endif /* QUADSPI */
+
+#if defined(OCTOSPI1) || defined(OCTOSPI2)
+/** @defgroup RCC_LL_EC_OSPI Peripheral OSPI get clock source
+  * @{
+  */
+#if defined(RCC_CDCCIPR_OCTOSPISEL)
+#define LL_RCC_OSPI_CLKSOURCE            RCC_CDCCIPR_OCTOSPISEL
+#else
+#define LL_RCC_OSPI_CLKSOURCE            RCC_D1CCIPR_OCTOSPISEL
+#endif /* RCC_CDCCIPR_OCTOSPISEL */
+/**
+  * @}
+  */
+#endif /* OCTOSPI1 || OCTOSPI2 */
+
+/** @defgroup RCC_LL_EC_CLKP Peripheral CLKP get clock source
+  * @{
+  */
+#if defined(RCC_D1CCIPR_CKPERSEL)
+#define LL_RCC_CLKP_CLKSOURCE            RCC_D1CCIPR_CKPERSEL
+#else
+#define LL_RCC_CLKP_CLKSOURCE            RCC_CDCCIPR_CKPERSEL
+#endif /* RCC_D1CCIPR_CKPERSEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_SPIx  Peripheral SPI get clock source
+  * @{
+  */
+#if defined(RCC_D2CCIP1R_SPI123SEL)
+#define LL_RCC_SPI123_CLKSOURCE          LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, 0x00000000U)
+#else
+#define LL_RCC_SPI123_CLKSOURCE          LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, 0x00000000U)
+#endif /* RCC_D2CCIP1R_SPI123SEL */
+#if defined(RCC_D2CCIP1R_SPI45SEL)
+#define LL_RCC_SPI45_CLKSOURCE           LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL,  RCC_D2CCIP1R_SPI45SEL_Pos,  0x00000000U)
+#else
+#define LL_RCC_SPI45_CLKSOURCE           LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL,  RCC_CDCCIP1R_SPI45SEL_Pos,  0x00000000U)
+#endif /* RCC_D2CCIP1R_SPI45SEL */
+#if defined(RCC_D3CCIPR_SPI6SEL)
+#define LL_RCC_SPI6_CLKSOURCE            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SPI6SEL,    RCC_D3CCIPR_SPI6SEL_Pos,    0x00000000U)
+#else
+#define LL_RCC_SPI6_CLKSOURCE            LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_SPI6SEL,   RCC_SRDCCIPR_SPI6SEL_Pos,  0x00000000U)
+#endif /* RCC_D3CCIPR_SPI6SEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_SPDIF  Peripheral SPDIF get clock source
+  * @{
+  */
+#if defined(RCC_D2CCIP1R_SPDIFSEL)
+#define LL_RCC_SPDIF_CLKSOURCE           RCC_D2CCIP1R_SPDIFSEL
+#else
+#define LL_RCC_SPDIF_CLKSOURCE           RCC_CDCCIP1R_SPDIFSEL
+#endif /* RCC_D2CCIP1R_SPDIFSEL */
+/**
+  * @}
+  */
+
+#if defined(FDCAN1) || defined(FDCAN2)
+/** @defgroup RCC_LL_EC_FDCAN  Peripheral FDCAN get clock source
+  * @{
+  */
+#if defined(RCC_D2CCIP1R_FDCANSEL)
+#define LL_RCC_FDCAN_CLKSOURCE           RCC_D2CCIP1R_FDCANSEL
+#else
+#define LL_RCC_FDCAN_CLKSOURCE           RCC_CDCCIP1R_FDCANSEL
+#endif
+/**
+  * @}
+  */
+#endif /*FDCAN1 || FDCAN2*/
+
+/** @defgroup RCC_LL_EC_SWP  Peripheral SWP get clock source
+  * @{
+  */
+#if defined(RCC_D2CCIP1R_SWPSEL)
+#define LL_RCC_SWP_CLKSOURCE             RCC_D2CCIP1R_SWPSEL
+#else
+#define LL_RCC_SWP_CLKSOURCE             RCC_CDCCIP1R_SWPSEL
+#endif /* RCC_D2CCIP1R_SWPSEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_ADC  Peripheral ADC get clock source
+  * @{
+  */
+#if defined(RCC_D3CCIPR_ADCSEL)
+#define LL_RCC_ADC_CLKSOURCE             RCC_D3CCIPR_ADCSEL
+#else
+#define LL_RCC_ADC_CLKSOURCE             RCC_SRDCCIPR_ADCSEL
+#endif /* RCC_D3CCIPR_ADCSEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_RTC_CLKSOURCE  RTC clock source selection
+  * @{
+  */
+#define LL_RCC_RTC_CLKSOURCE_NONE          (uint32_t)(0x00000000U)
+#define LL_RCC_RTC_CLKSOURCE_LSE           (uint32_t)(RCC_BDCR_RTCSEL_0)
+#define LL_RCC_RTC_CLKSOURCE_LSI           (uint32_t)(RCC_BDCR_RTCSEL_1)
+#define LL_RCC_RTC_CLKSOURCE_HSE           (uint32_t)(RCC_BDCR_RTCSEL_0 | RCC_BDCR_RTCSEL_1)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_TIM_CLKPRESCALER  Timers clocks prescalers selection
+  * @{
+  */
+#define LL_RCC_TIM_PRESCALER_TWICE          (uint32_t)(0x00000000U)
+#define LL_RCC_TIM_PRESCALER_FOUR_TIMES     (uint32_t)(RCC_CFGR_TIMPRE)
+/**
+  * @}
+  */
+
+#if defined(HRTIM1)
+/** @defgroup RCC_LL_EC_HRTIM_CLKSOURCE  High Resolution Timers clock selection
+  * @{
+  */
+#define LL_RCC_HRTIM_CLKSOURCE_TIM          (uint32_t)(0x00000000U)           /* HRTIM Clock source is same as other timers */
+#define LL_RCC_HRTIM_CLKSOURCE_CPU          (uint32_t)(RCC_CFGR_HRTIMSEL)     /* HRTIM Clock source is the CPU clock */
+/**
+  * @}
+  */
+#endif /* HRTIM1 */
+
+/** @defgroup RCC_LL_EC_PLLSOURCE   All PLLs entry clock source
+  * @{
+  */
+#define LL_RCC_PLLSOURCE_HSI               RCC_PLLCKSELR_PLLSRC_HSI
+#define LL_RCC_PLLSOURCE_CSI               RCC_PLLCKSELR_PLLSRC_CSI
+#define LL_RCC_PLLSOURCE_HSE               RCC_PLLCKSELR_PLLSRC_HSE
+#define LL_RCC_PLLSOURCE_NONE              RCC_PLLCKSELR_PLLSRC_NONE
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_PLLINPUTRANGE   All PLLs input range
+  * @{
+  */
+#define LL_RCC_PLLINPUTRANGE_1_2           (uint32_t)(0x00000000U)
+#define LL_RCC_PLLINPUTRANGE_2_4           (uint32_t)(0x00000001)
+#define LL_RCC_PLLINPUTRANGE_4_8           (uint32_t)(0x00000002)
+#define LL_RCC_PLLINPUTRANGE_8_16          (uint32_t)(0x00000003)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_PLLVCORANGE   All PLLs VCO range
+  * @{
+  */
+#define LL_RCC_PLLVCORANGE_WIDE            (uint32_t)(0x00000000U)      /* VCO output range: 192 to 836 MHz   OR  128 to 544 MHz (*) */
+#define LL_RCC_PLLVCORANGE_MEDIUM          (uint32_t)(0x00000001)       /* VCO output range: 150 to 420 MHz */
+/**
+  * (*) : For stm32h7a3xx and stm32h7b3xx family lines.
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
+  * @{
+  */
+
+/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in RCC register
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in RCC register
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
+  * @{
+  */
+
+/**
+  * @brief  Helper macro to calculate the SYSCLK frequency
+  * @param  __SYSINPUTCLKFREQ__ Frequency of the input of sys_ck (based on HSE/CSI/HSI/PLL1P)
+  * @param  __SYSPRESCALER__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SYSCLK_DIV_1
+  *         @arg @ref LL_RCC_SYSCLK_DIV_2
+  *         @arg @ref LL_RCC_SYSCLK_DIV_4
+  *         @arg @ref LL_RCC_SYSCLK_DIV_8
+  *         @arg @ref LL_RCC_SYSCLK_DIV_16
+  *         @arg @ref LL_RCC_SYSCLK_DIV_64
+  *         @arg @ref LL_RCC_SYSCLK_DIV_128
+  *         @arg @ref LL_RCC_SYSCLK_DIV_256
+  *         @arg @ref LL_RCC_SYSCLK_DIV_512
+  * @retval SYSCLK clock frequency (in Hz)
+  */
+#if defined(RCC_D1CFGR_D1CPRE)
+#define LL_RCC_CALC_SYSCLK_FREQ(__SYSINPUTCLKFREQ__, __SYSPRESCALER__) ((__SYSINPUTCLKFREQ__) >> ((LL_RCC_PrescTable[((__SYSPRESCALER__) & RCC_D1CFGR_D1CPRE) >>  RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU))
+#else
+#define LL_RCC_CALC_SYSCLK_FREQ(__SYSINPUTCLKFREQ__, __SYSPRESCALER__) ((__SYSINPUTCLKFREQ__) >> ((LL_RCC_PrescTable[((__SYSPRESCALER__) & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU))
+#endif /* RCC_D1CFGR_D1CPRE */
+
+/**
+  * @brief  Helper macro to calculate the HCLK frequency
+  * @param  __SYSCLKFREQ__ SYSCLK frequency.
+  * @param  __HPRESCALER__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_AHB_DIV_1
+  *         @arg @ref LL_RCC_AHB_DIV_2
+  *         @arg @ref LL_RCC_AHB_DIV_4
+  *         @arg @ref LL_RCC_AHB_DIV_8
+  *         @arg @ref LL_RCC_AHB_DIV_16
+  *         @arg @ref LL_RCC_AHB_DIV_64
+  *         @arg @ref LL_RCC_AHB_DIV_128
+  *         @arg @ref LL_RCC_AHB_DIV_256
+  *         @arg @ref LL_RCC_AHB_DIV_512
+  * @retval HCLK clock frequency (in Hz)
+  */
+#if defined(RCC_D1CFGR_HPRE)
+#define LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __HPRESCALER__) ((__SYSCLKFREQ__) >> ((LL_RCC_PrescTable[((__HPRESCALER__) & RCC_D1CFGR_HPRE) >>  RCC_D1CFGR_HPRE_Pos]) & 0x1FU))
+#else
+#define LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __HPRESCALER__) ((__SYSCLKFREQ__) >> ((LL_RCC_PrescTable[((__HPRESCALER__) & RCC_CDCFGR1_HPRE) >>  RCC_CDCFGR1_HPRE_Pos]) & 0x1FU))
+#endif  /* RCC_D1CFGR_HPRE */
+
+/**
+  * @brief  Helper macro to calculate the PCLK1 frequency (ABP1)
+  * @param  __HCLKFREQ__ HCLK frequency
+  * @param  __APB1PRESCALER__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_APB1_DIV_1
+  *         @arg @ref LL_RCC_APB1_DIV_2
+  *         @arg @ref LL_RCC_APB1_DIV_4
+  *         @arg @ref LL_RCC_APB1_DIV_8
+  *         @arg @ref LL_RCC_APB1_DIV_16
+  * @retval PCLK1 clock frequency (in Hz)
+  */
+#if defined(RCC_D2CFGR_D2PPRE1)
+#define LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB1PRESCALER__) & RCC_D2CFGR_D2PPRE1) >>  RCC_D2CFGR_D2PPRE1_Pos]) & 0x1FU))
+#else
+#define LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB1PRESCALER__) & RCC_CDCFGR2_CDPPRE1) >>  RCC_CDCFGR2_CDPPRE1_Pos]) & 0x1FU))
+#endif /* RCC_D2CFGR_D2PPRE1 */
+
+/**
+  * @brief  Helper macro to calculate the PCLK2 frequency (ABP2)
+  * @param  __HCLKFREQ__ HCLK frequency
+  * @param  __APB2PRESCALER__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_APB2_DIV_1
+  *         @arg @ref LL_RCC_APB2_DIV_2
+  *         @arg @ref LL_RCC_APB2_DIV_4
+  *         @arg @ref LL_RCC_APB2_DIV_8
+  *         @arg @ref LL_RCC_APB2_DIV_16
+  * @retval PCLK2 clock frequency (in Hz)
+  */
+#if defined(RCC_D2CFGR_D2PPRE2)
+#define LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB2PRESCALER__) & RCC_D2CFGR_D2PPRE2) >>  RCC_D2CFGR_D2PPRE2_Pos]) & 0x1FU))
+#else
+#define LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB2PRESCALER__) & RCC_CDCFGR2_CDPPRE2) >> RCC_CDCFGR2_CDPPRE2_Pos]) & 0x1FU))
+#endif /* RCC_D2CFGR_D2PPRE2 */
+
+/**
+  * @brief  Helper macro to calculate the PCLK3 frequency (APB3)
+  * @param  __HCLKFREQ__ HCLK frequency
+  * @param  __APB3PRESCALER__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_APB3_DIV_1
+  *         @arg @ref LL_RCC_APB3_DIV_2
+  *         @arg @ref LL_RCC_APB3_DIV_4
+  *         @arg @ref LL_RCC_APB3_DIV_8
+  *         @arg @ref LL_RCC_APB3_DIV_16
+  * @retval PCLK1 clock frequency (in Hz)
+  */
+#if defined(RCC_D1CFGR_D1PPRE)
+#define LL_RCC_CALC_PCLK3_FREQ(__HCLKFREQ__, __APB3PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB3PRESCALER__) & RCC_D1CFGR_D1PPRE) >>  RCC_D1CFGR_D1PPRE_Pos]) & 0x1FU))
+#else
+#define LL_RCC_CALC_PCLK3_FREQ(__HCLKFREQ__, __APB3PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB3PRESCALER__) & RCC_CDCFGR1_CDPPRE) >> RCC_CDCFGR1_CDPPRE_Pos]) & 0x1FU))
+#endif /* RCC_D1CFGR_D1PPRE */
+
+/**
+  * @brief  Helper macro to calculate the PCLK4 frequency (ABP4)
+  * @param  __HCLKFREQ__ HCLK frequency
+  * @param  __APB4PRESCALER__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_APB4_DIV_1
+  *         @arg @ref LL_RCC_APB4_DIV_2
+  *         @arg @ref LL_RCC_APB4_DIV_4
+  *         @arg @ref LL_RCC_APB4_DIV_8
+  *         @arg @ref LL_RCC_APB4_DIV_16
+  * @retval PCLK1 clock frequency (in Hz)
+  */
+#if defined(RCC_D3CFGR_D3PPRE)
+#define LL_RCC_CALC_PCLK4_FREQ(__HCLKFREQ__, __APB4PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB4PRESCALER__) & RCC_D3CFGR_D3PPRE) >>  RCC_D3CFGR_D3PPRE_Pos]) & 0x1FU))
+#else
+#define LL_RCC_CALC_PCLK4_FREQ(__HCLKFREQ__, __APB4PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB4PRESCALER__) & RCC_SRDCFGR_SRDPPRE) >>  RCC_SRDCFGR_SRDPPRE_Pos]) & 0x1FU))
+#endif /* RCC_D3CFGR_D3PPRE */
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
+  * @{
+  */
+#define LL_RCC_PERIPH_FREQUENCY_NO         0x00000000U                 /*!< No clock enabled for the peripheral            */
+#define LL_RCC_PERIPH_FREQUENCY_NA         0xFFFFFFFFU                 /*!< Frequency cannot be provided as external clock */
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
+  * @{
+  */
+
+/** @defgroup RCC_LL_EF_HSE HSE
+  * @{
+  */
+
+/**
+  * @brief  Enable the Clock Security System.
+  * @note Once HSE Clock Security System is enabled it cannot be changed anymore unless
+  *       a reset occurs or system enter in standby mode.
+  * @rmtoll CR           CSSHSEON         LL_RCC_HSE_EnableCSS
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_CSSHSEON);
+}
+
+/**
+  * @brief  Enable HSE external oscillator (HSE Bypass)
+  * @rmtoll CR           HSEBYP        LL_RCC_HSE_EnableBypass
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_HSEBYP);
+}
+
+/**
+  * @brief  Disable HSE external oscillator (HSE Bypass)
+  * @rmtoll CR           HSEBYP        LL_RCC_HSE_DisableBypass
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
+}
+
+#if defined(RCC_CR_HSEEXT)
+/**
+  * @brief  Select the Analog HSE external clock type in Bypass mode
+  * @rmtoll CR           HSEEXT        LL_RCC_HSE_SelectAnalogClock
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSE_SelectAnalogClock(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT);
+}
+
+/**
+  * @brief  Select the Digital HSE external clock type in Bypass mode
+  * @rmtoll CR           HSEEXT        LL_RCC_HSE_SelectDigitalClock
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSE_SelectDigitalClock(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_HSEEXT);
+}
+#endif /* RCC_CR_HSEEXT */
+
+/**
+  * @brief  Enable HSE crystal oscillator (HSE ON)
+  * @rmtoll CR           HSEON         LL_RCC_HSE_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSE_Enable(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_HSEON);
+}
+
+/**
+  * @brief  Disable HSE crystal oscillator (HSE ON)
+  * @rmtoll CR           HSEON         LL_RCC_HSE_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSE_Disable(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
+}
+
+/**
+  * @brief  Check if HSE oscillator Ready
+  * @rmtoll CR           HSERDY        LL_RCC_HSE_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
+{
+  return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY))?1UL:0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_HSI HSI
+  * @{
+  */
+
+/**
+  * @brief  Enable HSI oscillator
+  * @rmtoll CR           HSION         LL_RCC_HSI_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSI_Enable(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_HSION);
+}
+
+/**
+  * @brief  Disable HSI oscillator
+  * @rmtoll CR           HSION         LL_RCC_HSI_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSI_Disable(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_HSION);
+}
+
+/**
+  * @brief  Check if HSI clock is ready
+  * @rmtoll CR           HSIRDY        LL_RCC_HSI_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
+{
+  return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if HSI new divider applied and ready
+  * @rmtoll CR           HSIDIVF        LL_RCC_HSI_IsDividerReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_HSI_IsDividerReady(void)
+{
+  return ((READ_BIT(RCC->CR, RCC_CR_HSIDIVF) == (RCC_CR_HSIDIVF))?1UL:0UL);
+}
+
+/**
+  * @brief  Set HSI divider
+  * @rmtoll CR           HSIDIV        LL_RCC_HSI_SetDivider
+  * @param  Divider This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_HSI_DIV1
+  *         @arg @ref LL_RCC_HSI_DIV2
+  *         @arg @ref LL_RCC_HSI_DIV4
+  *         @arg @ref LL_RCC_HSI_DIV8
+  * @retval None.
+  */
+__STATIC_INLINE void LL_RCC_HSI_SetDivider(uint32_t Divider)
+{
+  MODIFY_REG(RCC->CR, RCC_CR_HSIDIV, Divider);
+}
+
+/**
+  * @brief  Get HSI divider
+  * @rmtoll CR           HSIDIV        LL_RCC_HSI_GetDivider
+  * @retval can be one of the following values:
+  *         @arg @ref LL_RCC_HSI_DIV1
+  *         @arg @ref LL_RCC_HSI_DIV2
+  *         @arg @ref LL_RCC_HSI_DIV4
+  *         @arg @ref LL_RCC_HSI_DIV8
+  */
+__STATIC_INLINE uint32_t LL_RCC_HSI_GetDivider(void)
+{
+  return (READ_BIT(RCC->CR, RCC_CR_HSIDIV));
+}
+
+/**
+  * @brief  Enable HSI oscillator in Stop mode
+  * @rmtoll CR           HSIKERON         LL_RCC_HSI_EnableStopMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSI_EnableStopMode(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_HSIKERON);
+}
+
+/**
+  * @brief  Disable HSI oscillator in Stop mode
+  * @rmtoll CR           HSION         LL_RCC_HSI_DisableStopMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSI_DisableStopMode(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON);
+}
+
+/**
+  * @brief  Get HSI Calibration value
+  * @note When HSITRIM is written, HSICAL is updated with the sum of
+  *       HSITRIM and the factory trim value
+  * @rmtoll HSICFGR        HSICAL        LL_RCC_HSI_GetCalibration
+  * @retval A value between 0 and 4095 (0xFFF)
+  */
+__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
+{
+  return (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSICAL) >> RCC_HSICFGR_HSICAL_Pos);
+}
+
+/**
+  * @brief  Set HSI Calibration trimming
+  * @note user-programmable trimming value that is added to the HSICAL
+  * @note Default value is 64 (32 for Cut1.x), which, when added to the HSICAL value,
+  *       should trim the HSI to 64 MHz +/- 1 %
+  * @rmtoll HSICFGR        HSITRIM       LL_RCC_HSI_SetCalibTrimming
+  * @param  Value can be a value between 0 and 127 (63 for Cut1.x)
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
+{
+#if defined(RCC_VER_X)
+  if ((DBGMCU->IDCODE & 0xF0000000U) == 0x10000000U)
+  {
+    /* STM32H7 Rev.Y */
+    MODIFY_REG(RCC->HSICFGR, 0x3F000U, Value << 12U);
+  }
+  else
+  {
+    /* STM32H7 Rev.V */
+    MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, Value << RCC_HSICFGR_HSITRIM_Pos);
+  }
+#else
+    MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, Value << RCC_HSICFGR_HSITRIM_Pos);
+#endif /* RCC_VER_X */
+}
+
+/**
+  * @brief  Get HSI Calibration trimming
+  * @rmtoll HSICFGR        HSITRIM       LL_RCC_HSI_GetCalibTrimming
+  * @retval A value between 0 and 127 (63 for Cut1.x)
+  */
+__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
+{
+#if defined(RCC_VER_X)
+  if ((DBGMCU->IDCODE & 0xF0000000U) == 0x10000000U)
+  {
+    /* STM32H7 Rev.Y */
+    return (uint32_t)(READ_BIT(RCC->HSICFGR, 0x3F000U) >> 12U);
+  }
+  else
+  {
+    /* STM32H7 Rev.V */
+    return (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos);
+  }
+#else
+    return (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos);
+#endif /* RCC_VER_X */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_CSI CSI
+  * @{
+  */
+
+/**
+  * @brief  Enable CSI oscillator
+  * @rmtoll CR           CSION         LL_RCC_CSI_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_CSI_Enable(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_CSION);
+}
+
+/**
+  * @brief  Disable CSI oscillator
+  * @rmtoll CR           CSION         LL_RCC_CSI_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_CSI_Disable(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_CSION);
+}
+
+/**
+  * @brief  Check if CSI clock is ready
+  * @rmtoll CR           CSIRDY        LL_RCC_CSI_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_CSI_IsReady(void)
+{
+  return ((READ_BIT(RCC->CR, RCC_CR_CSIRDY) == (RCC_CR_CSIRDY))?1UL:0UL);
+}
+
+/**
+  * @brief  Enable CSI oscillator in Stop mode
+  * @rmtoll CR           CSIKERON         LL_RCC_CSI_EnableStopMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_CSI_EnableStopMode(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_CSIKERON);
+}
+
+/**
+  * @brief  Disable CSI oscillator in Stop mode
+  * @rmtoll CR           CSIKERON         LL_RCC_CSI_DisableStopMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_CSI_DisableStopMode(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_CSIKERON);
+}
+
+/**
+  * @brief  Get CSI Calibration value
+  * @note When CSITRIM is written, CSICAL is updated with the sum of
+  *       CSITRIM and the factory trim value
+  * @rmtoll CSICFGR        CSICAL        LL_RCC_CSI_GetCalibration
+  * @retval A value between 0 and 255 (0xFF)
+  */
+__STATIC_INLINE uint32_t LL_RCC_CSI_GetCalibration(void)
+{
+#if defined(RCC_VER_X)
+  if ((DBGMCU->IDCODE & 0xF0000000U) == 0x10000000U)
+  {
+    /* STM32H7 Rev.Y */
+    return (uint32_t)(READ_BIT(RCC->HSICFGR, 0x3FC0000U) >> 18U);
+  }
+  else
+  {
+    /* STM32H7 Rev.V */
+    return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSICAL) >> RCC_CSICFGR_CSICAL_Pos);
+  }
+#else
+    return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSICAL) >> RCC_CSICFGR_CSICAL_Pos);
+#endif /* RCC_VER_X */
+}
+
+/**
+  * @brief  Set CSI Calibration trimming
+  * @note user-programmable trimming value that is added to the CSICAL
+  * @note Default value is 16, which, when added to the CSICAL value,
+  *       should trim the CSI to 4 MHz +/- 1 %
+  * @rmtoll CSICFGR        CSITRIM       LL_RCC_CSI_SetCalibTrimming
+  * @param  Value can be a value between 0 and 31
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_CSI_SetCalibTrimming(uint32_t Value)
+{
+#if defined(RCC_VER_X)
+  if ((DBGMCU->IDCODE & 0xF0000000U) == 0x10000000U)
+  {
+    /* STM32H7 Rev.Y */
+    MODIFY_REG(RCC->HSICFGR, 0x7C000000U, Value << 26U);
+  }
+  else
+  {
+    /* STM32H7 Rev.V */
+    MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, Value << RCC_CSICFGR_CSITRIM_Pos);
+  }
+#else
+    MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, Value << RCC_CSICFGR_CSITRIM_Pos);
+#endif /* RCC_VER_X */
+}
+
+/**
+  * @brief  Get CSI Calibration trimming
+  * @rmtoll CSICFGR        CSITRIM       LL_RCC_CSI_GetCalibTrimming
+  * @retval A value between 0 and 31
+  */
+__STATIC_INLINE uint32_t LL_RCC_CSI_GetCalibTrimming(void)
+{
+#if defined(RCC_VER_X)
+  if ((DBGMCU->IDCODE & 0xF0000000U) == 0x10000000U)
+  {
+    /* STM32H7 Rev.Y */
+    return (uint32_t)(READ_BIT(RCC->HSICFGR, 0x7C000000U) >> 26U);
+  }
+  else
+  {
+    /* STM32H7 Rev.V */
+    return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos);
+  }
+#else
+    return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos);
+#endif /* RCC_VER_X */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_HSI48 HSI48
+  * @{
+  */
+
+/**
+  * @brief  Enable HSI48 oscillator
+  * @rmtoll CR           HSI48ON         LL_RCC_HSI48_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSI48_Enable(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_HSI48ON);
+}
+
+/**
+  * @brief  Disable HSI48 oscillator
+  * @rmtoll CR           HSI48ON         LL_RCC_HSI48_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSI48_Disable(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON);
+}
+
+/**
+  * @brief  Check if HSI48 clock is ready
+  * @rmtoll CR           HSI48RDY        LL_RCC_HSI48_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void)
+{
+  return ((READ_BIT(RCC->CR, RCC_CR_HSI48RDY) == (RCC_CR_HSI48RDY))?1UL:0UL);
+}
+
+/**
+  * @brief  Get HSI48 Calibration value
+  * @note When HSI48TRIM is written, HSI48CAL is updated with the sum of
+  *       HSI48TRIM and the factory trim value
+  * @rmtoll CRRCR        HSI48CAL        LL_RCC_HSI48_GetCalibration
+  * @retval A value between 0 and 1023 (0x3FF)
+  */
+__STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48CAL) >> RCC_CRRCR_HSI48CAL_Pos);
+}
+/**
+  * @}
+  */
+
+#if defined(RCC_CR_D1CKRDY)
+
+/** @defgroup RCC_LL_EF_D1CLK D1CKREADY
+  * @{
+  */
+
+/**
+  * @brief  Check if D1 clock is ready
+  * @rmtoll CR           D1CKRDY        LL_RCC_D1CK_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_D1CK_IsReady(void)
+{
+  return ((READ_BIT(RCC->CR, RCC_CR_D1CKRDY) == (RCC_CR_D1CKRDY))?1UL:0UL);
+}
+
+/**
+  * @}
+  */
+#else
+
+/** @defgroup RCC_LL_EF_CPUCLK CPUCKREADY
+  * @{
+  */
+
+/**
+  * @brief  Check if CPU clock is ready
+  * @rmtoll CR           CPUCKRDY        LL_RCC_CPUCK_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_CPUCK_IsReady(void)
+{
+  return ((READ_BIT(RCC->CR, RCC_CR_CPUCKRDY) == (RCC_CR_CPUCKRDY))?1UL:0UL);
+}
+ /* alias */
+#define LL_RCC_D1CK_IsReady  LL_RCC_CPUCK_IsReady
+/**
+  * @}
+  */
+#endif /* RCC_CR_D1CKRDY */
+
+#if defined(RCC_CR_D2CKRDY)
+
+/** @defgroup RCC_LL_EF_D2CLK D2CKREADY
+  * @{
+  */
+
+/**
+  * @brief  Check if D2 clock is ready
+  * @rmtoll CR           D2CKRDY        LL_RCC_D2CK_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_D2CK_IsReady(void)
+{
+  return ((READ_BIT(RCC->CR, RCC_CR_D2CKRDY) == (RCC_CR_D2CKRDY))?1UL:0UL);
+}
+/**
+  * @}
+  */
+#else
+
+/** @defgroup RCC_LL_EF_CDCLK CDCKREADY
+  * @{
+  */
+
+/**
+  * @brief  Check if CD clock is ready
+  * @rmtoll CR           CDCKRDY        LL_RCC_CDCK_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_CDCK_IsReady(void)
+{
+  return ((READ_BIT(RCC->CR, RCC_CR_CDCKRDY) == (RCC_CR_CDCKRDY))?1UL:0UL);
+}
+#define LL_RCC_D2CK_IsReady LL_RCC_CDCK_IsReady
+/**
+  * @}
+  */
+#endif /* RCC_CR_D2CKRDY */
+
+/** @defgroup RCC_LL_EF_SYSTEM_WIDE_RESET RESET
+  * @{
+  */
+#if defined(RCC_GCR_WW1RSC)
+
+/**
+  * @brief  Enable system wide reset for Window Watch Dog 1
+  * @rmtoll GCR          WW1RSC        LL_RCC_WWDG1_EnableSystemReset
+  * @retval None.
+  */
+__STATIC_INLINE void LL_RCC_WWDG1_EnableSystemReset(void)
+{
+  SET_BIT(RCC->GCR, RCC_GCR_WW1RSC);
+}
+
+/**
+  * @brief  Check if Window Watch Dog 1 reset is system wide
+  * @rmtoll GCR          WW1RSC        LL_RCC_WWDG1_IsSystemReset
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_WWDG1_IsSystemReset(void)
+{
+  return ((READ_BIT(RCC->GCR, RCC_GCR_WW1RSC) == RCC_GCR_WW1RSC)?1UL:0UL);
+}
+#endif  /* RCC_GCR_WW1RSC */
+
+#if defined(DUAL_CORE)
+/**
+  * @brief  Enable system wide reset for Window Watch Dog 2
+  * @rmtoll GCR          WW1RSC        LL_RCC_WWDG2_EnableSystemReset
+  * @retval None.
+  */
+__STATIC_INLINE void LL_RCC_WWDG2_EnableSystemReset(void)
+{
+  SET_BIT(RCC->GCR, RCC_GCR_WW2RSC);
+}
+
+/**
+  * @brief  Check if Window Watch Dog 2 reset is system wide
+  * @rmtoll GCR          WW2RSC        LL_RCC_WWDG2_IsSystemReset
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_WWDG2_IsSystemReset(void)
+{
+  return ((READ_BIT(RCC->GCR, RCC_GCR_WW2RSC) == RCC_GCR_WW2RSC)?1UL:0UL);
+}
+#endif  /*DUAL_CORE*/
+/**
+  * @}
+  */
+
+#if defined(DUAL_CORE)
+/** @defgroup RCC_LL_EF_BOOT_CPU CPU
+  * @{
+  */
+
+/**
+  * @brief  Force CM4 boot (if hold by option byte BCM4 = 0)
+  * @rmtoll GCR          BOOT_C2        LL_RCC_ForceCM4Boot
+  * @retval None.
+  */
+__STATIC_INLINE void LL_RCC_ForceCM4Boot(void)
+{
+  SET_BIT(RCC->GCR, RCC_GCR_BOOT_C2);
+}
+
+/**
+  * @brief  Check if CM4 boot is forced
+  * @rmtoll GCR          BOOT_C2        LL_RCC_IsCM4BootForced
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsCM4BootForced(void)
+{
+  return ((READ_BIT(RCC->GCR, RCC_GCR_BOOT_C2) == RCC_GCR_BOOT_C2)?1UL:0UL);
+}
+
+/**
+  * @brief  Force CM7 boot (if hold by option byte BCM7 = 0)
+  * @rmtoll GCR          BOOT_C1        LL_RCC_ForceCM7Boot
+  * @retval None.
+  */
+__STATIC_INLINE void LL_RCC_ForceCM7Boot(void)
+{
+  SET_BIT(RCC->GCR, RCC_GCR_BOOT_C1);
+}
+
+/**
+  * @brief  Check if CM7 boot is forced
+  * @rmtoll GCR          BOOT_C1        LL_RCC_IsCM7BootForced
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsCM7BootForced(void)
+{
+  return ((READ_BIT(RCC->GCR, RCC_GCR_BOOT_C1) == RCC_GCR_BOOT_C1)?1UL:0UL);
+}
+
+/**
+  * @}
+  */
+#endif  /*DUAL_CORE*/
+
+/** @defgroup RCC_LL_EF_LSE LSE
+  * @{
+  */
+
+/**
+  * @brief  Enable the Clock Security System on LSE.
+  * @note Once LSE Clock Security System is enabled it cannot be changed anymore unless
+  *       a clock failure is detected.
+  * @rmtoll BDCR          LSECSSON         LL_RCC_LSE_EnableCSS
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSE_EnableCSS(void)
+{
+  SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
+}
+
+/**
+  * @brief  Check if LSE failure is detected by Clock Security System
+  * @rmtoll BDCR         LSECSSD       LL_RCC_LSE_IsFailureDetected
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_LSE_IsFailureDetected(void)
+{
+  return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == (RCC_BDCR_LSECSSD))?1UL:0UL);
+}
+
+/**
+  * @brief  Enable  Low Speed External (LSE) crystal.
+  * @rmtoll BDCR         LSEON         LL_RCC_LSE_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSE_Enable(void)
+{
+  SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
+}
+
+/**
+  * @brief  Disable  Low Speed External (LSE) crystal.
+  * @rmtoll BDCR         LSEON         LL_RCC_LSE_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSE_Disable(void)
+{
+  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
+}
+
+/**
+  * @brief  Enable external clock source (LSE bypass).
+  * @rmtoll BDCR         LSEBYP        LL_RCC_LSE_EnableBypass
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
+{
+  SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
+}
+
+/**
+  * @brief  Disable external clock source (LSE bypass).
+  * @rmtoll BDCR         LSEBYP        LL_RCC_LSE_DisableBypass
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
+{
+  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
+}
+
+#if defined(RCC_BDCR_LSEEXT)
+/**
+  * @brief  Enable Low-speed external DIGITAL clock type in Bypass mode (not to be used if RTC is active).
+  * @note   The external clock must be enabled with the LSEON bit, to be used by the device.
+  *         The LSEEXT bit can be written only if the LSE oscillator is disabled.
+  * @rmtoll BDCR         LSEEXT        LL_RCC_LSE_SelectDigitalClock
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSE_SelectDigitalClock(void)
+{
+  SET_BIT(RCC->BDCR, RCC_BDCR_LSEEXT);
+}
+
+/**
+  * @brief  Enable Low-speed external ANALOG clock type in Bypass mode (default after Backup domain reset).
+  * @note   The external clock must be enabled with the LSEON bit, to be used by the device.
+  *         The LSEEXT bit can be written only if the LSE oscillator is disabled.
+  * @rmtoll BDCR         LSEEXT        LL_RCC_LSE_SelectAnalogClock
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSE_SelectAnalogClock(void)
+{
+  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT);
+}
+#endif /* RCC_BDCR_LSEEXT */
+
+/**
+  * @brief  Set LSE oscillator drive capability
+  * @note The oscillator is in Xtal mode when it is not in bypass mode.
+  * @rmtoll BDCR         LSEDRV        LL_RCC_LSE_SetDriveCapability
+  * @param  LSEDrive This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_LSEDRIVE_LOW
+  *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
+  *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
+  *         @arg @ref LL_RCC_LSEDRIVE_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
+{
+  MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
+}
+
+/**
+  * @brief  Get LSE oscillator drive capability
+  * @rmtoll BDCR         LSEDRV        LL_RCC_LSE_GetDriveCapability
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_LSEDRIVE_LOW
+  *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
+  *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
+  *         @arg @ref LL_RCC_LSEDRIVE_HIGH
+  */
+__STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
+{
+  return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV));
+}
+
+/**
+  * @brief  Check if LSE oscillator Ready
+  * @rmtoll BDCR         LSERDY        LL_RCC_LSE_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
+{
+  return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY))?1UL:0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_LSI LSI
+  * @{
+  */
+
+/**
+  * @brief  Enable LSI Oscillator
+  * @rmtoll CSR          LSION         LL_RCC_LSI_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSI_Enable(void)
+{
+  SET_BIT(RCC->CSR, RCC_CSR_LSION);
+}
+
+/**
+  * @brief  Disable LSI Oscillator
+  * @rmtoll CSR          LSION         LL_RCC_LSI_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSI_Disable(void)
+{
+  CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
+}
+
+/**
+  * @brief  Check if LSI is Ready
+  * @rmtoll CSR          LSIRDY        LL_RCC_LSI_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
+{
+  return ((READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY))?1UL:0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_System System
+  * @{
+  */
+
+/**
+  * @brief  Configure the system clock source
+  * @rmtoll CFGR         SW            LL_RCC_SetSysClkSource
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_PLL1
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
+{
+  MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
+}
+
+/**
+  * @brief  Get the system clock source
+  * @rmtoll CFGR         SWS           LL_RCC_GetSysClkSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_CSI
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL1
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
+}
+
+/**
+  * @brief  Configure the system wakeup clock source
+  * @rmtoll CFGR         STOPWUCK       LL_RCC_SetSysWakeUpClkSource
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_CSI
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetSysWakeUpClkSource(uint32_t Source)
+{
+  MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, Source);
+}
+
+/**
+  * @brief  Get the system wakeup clock source
+  * @rmtoll CFGR         STOPWUCK           LL_RCC_GetSysWakeUpClkSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_CSI
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetSysWakeUpClkSource(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_STOPWUCK));
+}
+
+/**
+  * @brief  Configure the kernel wakeup clock source
+  * @rmtoll CFGR         STOPKERWUCK       LL_RCC_SetKerWakeUpClkSource
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_CSI
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetKerWakeUpClkSource(uint32_t Source)
+{
+  MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPKERWUCK, Source);
+}
+
+/**
+  * @brief  Get the kernel wakeup clock source
+  * @rmtoll CFGR         STOPKERWUCK           LL_RCC_GetKerWakeUpClkSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_CSI
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetKerWakeUpClkSource(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_STOPKERWUCK));
+}
+
+/**
+  * @brief  Set System prescaler
+  * @rmtoll D1CFGR/CDCFGR1        D1CPRE/CDCPRE          LL_RCC_SetSysPrescaler
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SYSCLK_DIV_1
+  *         @arg @ref LL_RCC_SYSCLK_DIV_2
+  *         @arg @ref LL_RCC_SYSCLK_DIV_4
+  *         @arg @ref LL_RCC_SYSCLK_DIV_8
+  *         @arg @ref LL_RCC_SYSCLK_DIV_16
+  *         @arg @ref LL_RCC_SYSCLK_DIV_64
+  *         @arg @ref LL_RCC_SYSCLK_DIV_128
+  *         @arg @ref LL_RCC_SYSCLK_DIV_256
+  *         @arg @ref LL_RCC_SYSCLK_DIV_512
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetSysPrescaler(uint32_t Prescaler)
+{
+#if defined(RCC_D1CFGR_D1CPRE)
+  MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1CPRE, Prescaler);
+#else
+  MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDCPRE, Prescaler);
+#endif /* RCC_D1CFGR_D1CPRE */
+}
+
+/**
+  * @brief  Set AHB prescaler
+  * @rmtoll D1CFGR/CDCFGR1        HPRE         LL_RCC_SetAHBPrescaler
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_AHB_DIV_1
+  *         @arg @ref LL_RCC_AHB_DIV_2
+  *         @arg @ref LL_RCC_AHB_DIV_4
+  *         @arg @ref LL_RCC_AHB_DIV_8
+  *         @arg @ref LL_RCC_AHB_DIV_16
+  *         @arg @ref LL_RCC_AHB_DIV_64
+  *         @arg @ref LL_RCC_AHB_DIV_128
+  *         @arg @ref LL_RCC_AHB_DIV_256
+  *         @arg @ref LL_RCC_AHB_DIV_512
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
+{
+#if defined(RCC_D1CFGR_HPRE)
+  MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, Prescaler);
+#else
+  MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_HPRE, Prescaler);
+#endif /* RCC_D1CFGR_HPRE */
+}
+
+/**
+  * @brief  Set APB1 prescaler
+  * @rmtoll D2CFGR/CDCFGR2         D2PPRE1/CDPPRE1         LL_RCC_SetAPB1Prescaler
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_APB1_DIV_1
+  *         @arg @ref LL_RCC_APB1_DIV_2
+  *         @arg @ref LL_RCC_APB1_DIV_4
+  *         @arg @ref LL_RCC_APB1_DIV_8
+  *         @arg @ref LL_RCC_APB1_DIV_16
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
+{
+#if defined(RCC_D2CFGR_D2PPRE1)
+  MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, Prescaler);
+#else
+  MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, Prescaler);
+#endif /* RCC_D2CFGR_D2PPRE1 */
+}
+
+/**
+  * @brief  Set APB2 prescaler
+  * @rmtoll D2CFGR/CDCFGR2         D2PPRE2/CDPPRE2         LL_RCC_SetAPB2Prescaler
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_APB2_DIV_1
+  *         @arg @ref LL_RCC_APB2_DIV_2
+  *         @arg @ref LL_RCC_APB2_DIV_4
+  *         @arg @ref LL_RCC_APB2_DIV_8
+  *         @arg @ref LL_RCC_APB2_DIV_16
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
+{
+#if defined(RCC_D2CFGR_D2PPRE2)
+  MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, Prescaler);
+#else
+  MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE2, Prescaler);
+#endif /* RCC_D2CFGR_D2PPRE2 */
+}
+
+/**
+  * @brief  Set APB3 prescaler
+  * @rmtoll D1CFGR/CDCFGR1         D1PPRE/CDPPRE         LL_RCC_SetAPB3Prescaler
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_APB3_DIV_1
+  *         @arg @ref LL_RCC_APB3_DIV_2
+  *         @arg @ref LL_RCC_APB3_DIV_4
+  *         @arg @ref LL_RCC_APB3_DIV_8
+  *         @arg @ref LL_RCC_APB3_DIV_16
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetAPB3Prescaler(uint32_t Prescaler)
+{
+#if defined(RCC_D1CFGR_D1PPRE)
+  MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, Prescaler);
+#else
+  MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDPPRE, Prescaler);
+#endif /* RCC_D1CFGR_D1PPRE */
+}
+
+/**
+  * @brief  Set APB4 prescaler
+  * @rmtoll D3CFGR/SRDCFGR         D3PPRE/SRDPPRE         LL_RCC_SetAPB4Prescaler
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_APB4_DIV_1
+  *         @arg @ref LL_RCC_APB4_DIV_2
+  *         @arg @ref LL_RCC_APB4_DIV_4
+  *         @arg @ref LL_RCC_APB4_DIV_8
+  *         @arg @ref LL_RCC_APB4_DIV_16
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetAPB4Prescaler(uint32_t Prescaler)
+{
+#if defined(RCC_D3CFGR_D3PPRE)
+  MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, Prescaler);
+#else
+  MODIFY_REG(RCC->SRDCFGR, RCC_SRDCFGR_SRDPPRE, Prescaler);
+#endif /* RCC_D3CFGR_D3PPRE */
+}
+
+/**
+  * @brief  Get System prescaler
+  * @rmtoll D1CFGR/CDCFGR1        D1CPRE/CDCPRE          LL_RCC_GetSysPrescaler
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_SYSCLK_DIV_1
+  *         @arg @ref LL_RCC_SYSCLK_DIV_2
+  *         @arg @ref LL_RCC_SYSCLK_DIV_4
+  *         @arg @ref LL_RCC_SYSCLK_DIV_8
+  *         @arg @ref LL_RCC_SYSCLK_DIV_16
+  *         @arg @ref LL_RCC_SYSCLK_DIV_64
+  *         @arg @ref LL_RCC_SYSCLK_DIV_128
+  *         @arg @ref LL_RCC_SYSCLK_DIV_256
+  *         @arg @ref LL_RCC_SYSCLK_DIV_512
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetSysPrescaler(void)
+{
+#if defined(RCC_D1CFGR_D1CPRE)
+  return (uint32_t)(READ_BIT(RCC->D1CFGR, RCC_D1CFGR_D1CPRE));
+#else
+  return (uint32_t)(READ_BIT(RCC->CDCFGR1, RCC_CDCFGR1_CDCPRE));
+#endif /* RCC_D1CFGR_D1CPRE */
+}
+
+/**
+  * @brief  Get AHB prescaler
+  * @rmtoll D1CFGR/ CDCFGR1       HPRE         LL_RCC_GetAHBPrescaler
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_AHB_DIV_1
+  *         @arg @ref LL_RCC_AHB_DIV_2
+  *         @arg @ref LL_RCC_AHB_DIV_4
+  *         @arg @ref LL_RCC_AHB_DIV_8
+  *         @arg @ref LL_RCC_AHB_DIV_16
+  *         @arg @ref LL_RCC_AHB_DIV_64
+  *         @arg @ref LL_RCC_AHB_DIV_128
+  *         @arg @ref LL_RCC_AHB_DIV_256
+  *         @arg @ref LL_RCC_AHB_DIV_512
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
+{
+#if defined(RCC_D1CFGR_HPRE)
+  return (uint32_t)(READ_BIT(RCC->D1CFGR, RCC_D1CFGR_HPRE));
+#else
+  return (uint32_t)(READ_BIT(RCC->CDCFGR1, RCC_CDCFGR1_HPRE));
+#endif /* RCC_D1CFGR_HPRE */
+}
+
+/**
+  * @brief  Get APB1 prescaler
+  * @rmtoll D2CFGR/CDCFGR2         D2PPRE1/CDPPRE1         LL_RCC_GetAPB1Prescaler
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_APB1_DIV_1
+  *         @arg @ref LL_RCC_APB1_DIV_2
+  *         @arg @ref LL_RCC_APB1_DIV_4
+  *         @arg @ref LL_RCC_APB1_DIV_8
+  *         @arg @ref LL_RCC_APB1_DIV_16
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
+{
+#if defined(RCC_D2CFGR_D2PPRE1)
+  return (uint32_t)(READ_BIT(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1));
+#else
+  return (uint32_t)(READ_BIT(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1));
+#endif /* RCC_D2CFGR_D2PPRE1 */
+}
+
+/**
+  * @brief  Get APB2 prescaler
+  * @rmtoll D2CFGR/CDCFGR2         D2PPRE2/CDPPRE2         LL_RCC_GetAPB2Prescaler
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_APB2_DIV_1
+  *         @arg @ref LL_RCC_APB2_DIV_2
+  *         @arg @ref LL_RCC_APB2_DIV_4
+  *         @arg @ref LL_RCC_APB2_DIV_8
+  *         @arg @ref LL_RCC_APB2_DIV_16
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
+{
+#if defined(RCC_D2CFGR_D2PPRE2)
+  return (uint32_t)(READ_BIT(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2));
+#else
+  return (uint32_t)(READ_BIT(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE2));
+#endif /* RCC_D2CFGR_D2PPRE2 */
+}
+
+/**
+  * @brief  Get APB3 prescaler
+  * @rmtoll D1CFGR/CDCFGR1         D1PPRE/CDPPRE         LL_RCC_GetAPB3Prescaler
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_APB3_DIV_1
+  *         @arg @ref LL_RCC_APB3_DIV_2
+  *         @arg @ref LL_RCC_APB3_DIV_4
+  *         @arg @ref LL_RCC_APB3_DIV_8
+  *         @arg @ref LL_RCC_APB3_DIV_16
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetAPB3Prescaler(void)
+{
+#if defined(RCC_D1CFGR_D1PPRE)
+  return (uint32_t)(READ_BIT(RCC->D1CFGR, RCC_D1CFGR_D1PPRE));
+#else
+  return (uint32_t)(READ_BIT(RCC->CDCFGR1, RCC_CDCFGR1_CDPPRE));
+#endif /* RCC_D1CFGR_D1PPRE */
+}
+
+/**
+  * @brief  Get APB4 prescaler
+  * @rmtoll D3CFGR/SRDCFGR         D3PPRE/SRDPPRE         LL_RCC_GetAPB4Prescaler
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_APB4_DIV_1
+  *         @arg @ref LL_RCC_APB4_DIV_2
+  *         @arg @ref LL_RCC_APB4_DIV_4
+  *         @arg @ref LL_RCC_APB4_DIV_8
+  *         @arg @ref LL_RCC_APB4_DIV_16
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetAPB4Prescaler(void)
+{
+#if defined(RCC_D3CFGR_D3PPRE)
+  return (uint32_t)(READ_BIT(RCC->D3CFGR, RCC_D3CFGR_D3PPRE));
+#else
+  return (uint32_t)(READ_BIT(RCC->SRDCFGR, RCC_SRDCFGR_SRDPPRE));
+#endif /* RCC_D3CFGR_D3PPRE */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_MCO MCO
+  * @{
+  */
+
+/**
+  * @brief  Configure MCOx
+  * @rmtoll CFGR         MCO1          LL_RCC_ConfigMCO\n
+  *         CFGR         MCO1PRE       LL_RCC_ConfigMCO\n
+  *         CFGR         MCO2          LL_RCC_ConfigMCO\n
+  *         CFGR         MCO2PRE       LL_RCC_ConfigMCO
+  * @param  MCOxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_MCO1SOURCE_HSI
+  *         @arg @ref LL_RCC_MCO1SOURCE_LSE
+  *         @arg @ref LL_RCC_MCO1SOURCE_HSE
+  *         @arg @ref LL_RCC_MCO1SOURCE_PLL1QCLK
+  *         @arg @ref LL_RCC_MCO1SOURCE_HSI48
+  *         @arg @ref LL_RCC_MCO2SOURCE_SYSCLK
+  *         @arg @ref LL_RCC_MCO2SOURCE_PLL2PCLK
+  *         @arg @ref LL_RCC_MCO2SOURCE_HSE
+  *         @arg @ref LL_RCC_MCO2SOURCE_PLL1PCLK
+  *         @arg @ref LL_RCC_MCO2SOURCE_CSI
+  *         @arg @ref LL_RCC_MCO2SOURCE_LSI
+  * @param  MCOxPrescaler This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_MCO1_DIV_1
+  *         @arg @ref LL_RCC_MCO1_DIV_2
+  *         @arg @ref LL_RCC_MCO1_DIV_3
+  *         @arg @ref LL_RCC_MCO1_DIV_4
+  *         @arg @ref LL_RCC_MCO1_DIV_5
+  *         @arg @ref LL_RCC_MCO1_DIV_6
+  *         @arg @ref LL_RCC_MCO1_DIV_7
+  *         @arg @ref LL_RCC_MCO1_DIV_8
+  *         @arg @ref LL_RCC_MCO1_DIV_9
+  *         @arg @ref LL_RCC_MCO1_DIV_10
+  *         @arg @ref LL_RCC_MCO1_DIV_11
+  *         @arg @ref LL_RCC_MCO1_DIV_12
+  *         @arg @ref LL_RCC_MCO1_DIV_13
+  *         @arg @ref LL_RCC_MCO1_DIV_14
+  *         @arg @ref LL_RCC_MCO1_DIV_15
+  *         @arg @ref LL_RCC_MCO2_DIV_1
+  *         @arg @ref LL_RCC_MCO2_DIV_2
+  *         @arg @ref LL_RCC_MCO2_DIV_3
+  *         @arg @ref LL_RCC_MCO2_DIV_4
+  *         @arg @ref LL_RCC_MCO2_DIV_5
+  *         @arg @ref LL_RCC_MCO2_DIV_6
+  *         @arg @ref LL_RCC_MCO2_DIV_7
+  *         @arg @ref LL_RCC_MCO2_DIV_8
+  *         @arg @ref LL_RCC_MCO2_DIV_9
+  *         @arg @ref LL_RCC_MCO2_DIV_10
+  *         @arg @ref LL_RCC_MCO2_DIV_11
+  *         @arg @ref LL_RCC_MCO2_DIV_12
+  *         @arg @ref LL_RCC_MCO2_DIV_13
+  *         @arg @ref LL_RCC_MCO2_DIV_14
+  *         @arg @ref LL_RCC_MCO2_DIV_15
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
+{
+  MODIFY_REG(RCC->CFGR,  (MCOxSource << 16U) | (MCOxPrescaler << 16U), (MCOxSource & 0xFFFF0000U) | (MCOxPrescaler & 0xFFFF0000U));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
+  * @{
+  */
+
+/**
+  * @brief  Configure periph clock source
+  * @rmtoll D2CCIP1R/CDCCIP1R        *     LL_RCC_SetClockSource\n
+  *         D2CCIP2R/CDCCIP2R        *     LL_RCC_SetClockSource\n
+  *         D3CCIPR/SRDCCIPR         *     LL_RCC_SetClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_PLL2Q
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_PLL3Q
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL2Q
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL3Q
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_PLL3R
+  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_PLL3R
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL2P
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL3R
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL2P
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL3R
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL1Q (*)
+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL2P (*) 
+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL3P (*)
+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_I2S_CKIN (*)
+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_CLKP (*)
+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL1Q (*)
+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL2P  (*)
+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL3P  (*)
+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN  (*)
+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_SPDIF  (*)
+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL1Q  (*)
+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL2P  (*)
+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL3P  (*)
+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN  (*)
+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_CLKP  (*)
+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_SPDIF  (*)
+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL1Q  (*)
+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL2P (*)
+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL3P (*)
+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN (*)
+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_CLKP (*)
+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_SPDIF (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL1Q (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL2P (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL3P (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_CLKP (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_SPDIF  (*)
+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL2P
+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL3P
+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_I2S_CKIN
+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL2Q
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL3Q
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_HSE
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_I2S_CKIN (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetClockSource(uint32_t ClkSource)
+{
+#if defined(RCC_D1CCIPR_FMCSEL)
+  uint32_t * pReg = (uint32_t *)((uint32_t)&RCC->D1CCIPR + LL_CLKSOURCE_REG(ClkSource));
+#else
+  uint32_t * pReg = (uint32_t *)((uint32_t)&RCC->CDCCIPR + LL_CLKSOURCE_REG(ClkSource));
+#endif /*  */
+  MODIFY_REG(*pReg, LL_CLKSOURCE_MASK(ClkSource), LL_CLKSOURCE_CONFIG(ClkSource));
+}
+
+/**
+  * @brief  Configure USARTx clock source
+  * @rmtoll D2CCIP2R / D2CCIP2R        USART16SEL     LL_RCC_SetUSARTClockSource\n
+  *         D2CCIP2R / D2CCIP2R        USART28SEL     LL_RCC_SetUSARTClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_PLL2Q
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_PLL3Q
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL2Q
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL3Q
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_LSE
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t ClkSource)
+{
+  LL_RCC_SetClockSource(ClkSource);
+}
+
+/**
+  * @brief  Configure LPUARTx clock source
+  * @rmtoll D3CCIPR / SRDCCIPR        LPUART1SEL     LL_RCC_SetLPUARTClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL2Q
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL3Q
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t ClkSource)
+{
+#if defined(RCC_D3CCIPR_LPUART1SEL)
+  MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL, ClkSource);
+#else
+  MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL, ClkSource);
+#endif /* RCC_D3CCIPR_LPUART1SEL */
+}
+
+/**
+  * @brief  Configure I2Cx clock source
+  * @rmtoll D2CCIP2R / CDCCIP2R       I2C123SEL       LL_RCC_SetI2CClockSource\n
+  *         D3CCIPR / SRDCCIPR        I2C4SEL         LL_RCC_SetI2CClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_PLL3R
+  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_PLL3R
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_CSI
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t ClkSource)
+{
+  LL_RCC_SetClockSource(ClkSource);
+}
+
+/**
+  * @brief  Configure LPTIMx clock source
+  * @rmtoll D2CCIP2R / CDCCIP2R      LPTIM1SEL     LL_RCC_SetLPTIMClockSource
+  *         D3CCIPR  / SRDCCIPR      LPTIM2SEL     LL_RCC_SetLPTIMClockSource\n
+  *         D3CCIPR  / SRDCCIPR      LPTIM345SEL   LL_RCC_SetLPTIMClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL2P
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL3R
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL2P
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL3R
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_CLKP
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t ClkSource)
+{
+  LL_RCC_SetClockSource(ClkSource);
+}
+
+/**
+  * @brief  Configure SAIx clock source
+  * @rmtoll D2CCIP1R / CDCCIP1R       SAI1SEL       LL_RCC_SetSAIClockSource\n
+  *         D2CCIP1R / CDCCIP1R       SAI23SEL      LL_RCC_SetSAIClockSource
+  *         D3CCIPR  / SRDCCIPR       SAI4ASEL      LL_RCC_SetSAI4xClockSource\n
+  *         D3CCIPR  / SRDCCIPR       SAI4BSEL      LL_RCC_SetSAI4xClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL1Q (*)
+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL2P (*)
+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL3P (*)
+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_I2S_CKIN (*) 
+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_CLKP (*)
+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL1Q (*)
+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL2P  (*)
+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL3P  (*)
+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN  (*)
+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_SPDIF  (*)
+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL1Q  (*)
+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL2P  (*)
+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL3P  (*)
+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN  (*)
+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_CLKP  (*)
+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_SPDIF  (*)
+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL1Q  (*)
+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL2P (*)
+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL3P (*)
+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN (*)
+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_CLKP (*)
+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_SPDIF  (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL1Q (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL2P (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL3P (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_CLKP (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_SPDIF  (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t ClkSource)
+{
+  LL_RCC_SetClockSource(ClkSource);
+}
+
+/**
+  * @brief  Configure SDMMCx clock source
+  * @rmtoll D1CCIPR / CDCCIPR       SDMMCSEL      LL_RCC_SetSDMMCClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SDMMC_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_SDMMC_CLKSOURCE_PLL2R
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetSDMMCClockSource(uint32_t ClkSource)
+{
+#if defined(RCC_D1CCIPR_SDMMCSEL)
+  MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL, ClkSource);
+#else
+  MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL, ClkSource);
+#endif /* RCC_D1CCIPR_SDMMCSEL */
+}
+
+/**
+  * @brief  Configure RNGx clock source
+  * @rmtoll D2CCIP2R / CDCCIP2R       RNGSEL      LL_RCC_SetRNGClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48
+  *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_RNG_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_RNG_CLKSOURCE_LSI
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t ClkSource)
+{
+#if defined(RCC_D2CCIP2R_RNGSEL)
+  MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL, ClkSource);
+#else
+  MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL, ClkSource);
+#endif /* RCC_D2CCIP2R_RNGSEL */
+}
+
+/**
+  * @brief  Configure USBx clock source
+  * @rmtoll D2CCIP2R / CDCCIP2R      USBSEL      LL_RCC_SetUSBClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_USB_CLKSOURCE_DISABLE
+  *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL3Q
+  *         @arg @ref LL_RCC_USB_CLKSOURCE_HSI48
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t ClkSource)
+{
+#if defined(RCC_D2CCIP2R_USBSEL)
+  MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL, ClkSource);
+#else
+  MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL, ClkSource);
+#endif /* RCC_D2CCIP2R_USBSEL */
+}
+
+/**
+  * @brief  Configure CECx clock source
+  * @rmtoll D2CCIP2R / CDCCIP2R         CECSEL        LL_RCC_SetCECClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_CEC_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_CEC_CLKSOURCE_CSI_DIV122
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t ClkSource)
+{
+#if defined(RCC_D2CCIP2R_CECSEL)
+  MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL, ClkSource);
+#else
+  MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_CECSEL, ClkSource);
+#endif /* RCC_D2CCIP2R_CECSEL */
+}
+
+#if defined(DSI)
+/**
+  * @brief  Configure DSIx clock source
+  * @rmtoll D1CCIPR         DSISEL        LL_RCC_SetDSIClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
+  *         @arg @ref LL_RCC_DSI_CLKSOURCE_PLL2Q
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetDSIClockSource(uint32_t ClkSource)
+{
+  MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_DSISEL, ClkSource);
+}
+#endif /* DSI */
+
+/**
+  * @brief  Configure DFSDMx Kernel clock source
+  * @rmtoll D2CCIP1R / CDCCIP1R         DFSDM1SEL        LL_RCC_SetDFSDMClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t ClkSource)
+{
+#if defined(RCC_D2CCIP1R_DFSDM1SEL)
+   MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL, ClkSource);
+#else
+   MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL, ClkSource);
+#endif /* RCC_D2CCIP1R_DFSDM1SEL */
+}
+
+#if defined(DFSDM2_BASE)
+/**
+  * @brief  Configure DFSDMx Kernel clock source
+  * @rmtoll SRDCCIPR                   DFSDM2SEL        LL_RCC_SetDFSDM2ClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_DFSDM2_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_DFSDM2_CLKSOURCE_SYSCLK
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetDFSDM2ClockSource(uint32_t ClkSource)
+{
+   MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL, ClkSource);
+}
+#endif /* DFSDM2_BASE */
+
+/**
+  * @brief  Configure FMCx Kernel clock source
+  * @rmtoll D1CCIPR /  CDCCIPR        FMCSEL        LL_RCC_SetFMCClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_FMC_CLKSOURCE_HCLK
+  *         @arg @ref LL_RCC_FMC_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_FMC_CLKSOURCE_PLL2R
+  *         @arg @ref LL_RCC_FMC_CLKSOURCE_CLKP
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetFMCClockSource(uint32_t ClkSource)
+{
+#if defined(RCC_D1CCIPR_FMCSEL)
+  MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL, ClkSource);
+#else
+  MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL, ClkSource);
+#endif /* RCC_D1CCIPR_FMCSEL */
+}
+
+#if defined(QUADSPI)
+/**
+  * @brief  Configure QSPIx Kernel clock source
+  * @rmtoll D1CCIPR         QSPISEL        LL_RCC_SetQSPIClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_QSPI_CLKSOURCE_HCLK
+  *         @arg @ref LL_RCC_QSPI_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_QSPI_CLKSOURCE_PLL2R
+  *         @arg @ref LL_RCC_QSPI_CLKSOURCE_CLKP
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetQSPIClockSource(uint32_t ClkSource)
+{
+  MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL, ClkSource);
+}
+#endif /* QUADSPI */
+
+#if defined(OCTOSPI1) || defined(OCTOSPI2)
+/**
+  * @brief  Configure OSPIx Kernel clock source
+  * @rmtoll D1CCIPR         OPISEL        LL_RCC_SetOSPIClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_OSPI_CLKSOURCE_HCLK
+  *         @arg @ref LL_RCC_OSPI_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_OSPI_CLKSOURCE_PLL2R
+  *         @arg @ref LL_RCC_OSPI_CLKSOURCE_CLKP
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetOSPIClockSource(uint32_t ClkSource)
+{
+#if defined(RCC_D1CCIPR_OCTOSPISEL)
+  MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_OCTOSPISEL, ClkSource);
+#else
+  MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL, ClkSource);
+#endif /* RCC_D1CCIPR_OCTOSPISEL */
+}
+#endif /* OCTOSPI1 || OCTOSPI2 */
+
+/**
+  * @brief  Configure CLKP Kernel clock source
+  * @rmtoll D1CCIPR / CDCCIPR         CKPERSEL        LL_RCC_SetCLKPClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_CLKP_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_CLKP_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_CLKP_CLKSOURCE_HSE
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetCLKPClockSource(uint32_t ClkSource)
+{
+#if defined(RCC_D1CCIPR_CKPERSEL)
+  MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL, ClkSource);
+#else
+  MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL, ClkSource);
+#endif /* RCC_D1CCIPR_CKPERSEL */
+}
+
+/**
+  * @brief  Configure SPIx Kernel clock source
+  * @rmtoll D2CCIP1R / CDCCIP1R       SPI123SEL        LL_RCC_SetSPIClockSource\n
+  *         D2CCIP1R / CDCCIP1R       SPI45SEL         LL_RCC_SetSPIClockSource\n
+  *         D3CCIPR  / SRDCCIPR       SPI6SEL          LL_RCC_SetSPIClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL2P
+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL3P
+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_I2S_CKIN
+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL2Q
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL3Q
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_HSE
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_I2S_CKIN (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetSPIClockSource(uint32_t ClkSource)
+{
+  LL_RCC_SetClockSource(ClkSource);
+}
+
+/**
+  * @brief  Configure SPDIFx Kernel clock source
+  * @rmtoll D2CCIP1R / CDCCIP1R       SPDIFSEL        LL_RCC_SetSPDIFClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL2R
+  *         @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL3R
+  *         @arg @ref LL_RCC_SPDIF_CLKSOURCE_HSI
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetSPDIFClockSource(uint32_t ClkSource)
+{
+#if defined(RCC_D2CCIP1R_SPDIFSEL)
+  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL, ClkSource);
+#else
+  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL, ClkSource);
+#endif /* RCC_D2CCIP1R_SPDIFSEL */
+}
+
+/**
+  * @brief  Configure FDCANx Kernel clock source
+  * @rmtoll D2CCIP1R / CDCCIP1R      FDCANSEL        LL_RCC_SetFDCANClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE
+  *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL2Q
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetFDCANClockSource(uint32_t ClkSource)
+{
+#if defined(RCC_D2CCIP1R_FDCANSEL)
+  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL, ClkSource);
+#else
+  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_FDCANSEL, ClkSource);
+#endif /* RCC_D2CCIP1R_FDCANSEL */
+}
+
+/**
+  * @brief  Configure SWPx Kernel clock source
+  * @rmtoll D2CCIP1R /  CDCCIP1R       SWPSEL        LL_RCC_SetSWPClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SWP_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_SWP_CLKSOURCE_HSI
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetSWPClockSource(uint32_t ClkSource)
+{
+#if defined(RCC_D2CCIP1R_SWPSEL)
+  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL, ClkSource);
+#else
+  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL, ClkSource);
+#endif /* RCC_D2CCIP1R_SWPSEL */
+}
+
+/**
+  * @brief  Configure ADCx Kernel clock source
+  * @rmtoll D3CCIPR / SRDCCIPR        ADCSEL        LL_RCC_SetADCClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_ADC_CLKSOURCE_PLL2P
+  *         @arg @ref LL_RCC_ADC_CLKSOURCE_PLL3R
+  *         @arg @ref LL_RCC_ADC_CLKSOURCE_CLKP
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ClkSource)
+{
+#if defined(RCC_D3CCIPR_ADCSEL)
+  MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL, ClkSource);
+#else
+  MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL, ClkSource);
+#endif /* RCC_D3CCIPR_ADCSEL */
+}
+
+/**
+  * @brief  Get periph clock source
+  * @rmtoll D1CCIPR  / CDCCIPR       *     LL_RCC_GetClockSource\n
+  *         D2CCIP1R / CDCCIP1R      *     LL_RCC_GetClockSource\n
+  *         D2CCIP2R / CDCCIP2R      *     LL_RCC_GetClockSource\n
+  *         D3CCIPR  / SRDCCIPR      *     LL_RCC_GetClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE
+  *         @arg @ref LL_RCC_I2C123_CLKSOURCE
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE
+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE
+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE (*)
+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE (*)
+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE (*)
+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE (*)
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE (*)
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE (*)
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_PLL2Q
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_PLL3Q
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL2Q
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL3Q
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_PLL3R
+  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_PLL3R
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL2P
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL3R
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL2P
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL3R
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL1Q (*)
+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL2P (*)
+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL3P (*)
+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_I2S_CKIN (*)
+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_CLKP (*)
+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL1Q (*)
+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL2P (*)
+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL3P (*)
+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN (*)
+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_CLKP (*)
+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL1Q (*)
+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL2P (*)
+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL3P (*)
+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN (*)
+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_CLKP (*)
+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL1Q (*)
+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL2P (*)
+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL3P (*)
+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN (*)
+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_CLKP (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_SPDIF (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL1Q (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL2P (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL3P (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_CLKP (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_SPDIF (*)
+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL2P
+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL3P
+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_I2S_CKIN
+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL2Q
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL3Q
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_HSE
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_I2S_CKIN (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetClockSource(uint32_t Periph)
+{
+#if defined(RCC_D1CCIPR_FMCSEL)
+  const uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&RCC->D1CCIPR) + LL_CLKSOURCE_REG(Periph)));
+#else
+  const uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&RCC->CDCCIPR) + LL_CLKSOURCE_REG(Periph)));
+#endif /* RCC_D1CCIPR_FMCSEL */
+  return (uint32_t) (Periph | (((READ_BIT(*pReg, LL_CLKSOURCE_MASK(Periph))) >> LL_CLKSOURCE_SHIFT(Periph)) << LL_RCC_CONFIG_SHIFT) );
+}
+
+/**
+  * @brief  Get USARTx clock source
+  * @rmtoll D2CCIP2R / CDCCIP2R      USART16SEL     LL_RCC_GetUSARTClockSource\n
+  *         D2CCIP2R / CDCCIP2R      USART28SEL     LL_RCC_GetUSARTClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_PLL2Q
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_PLL3Q
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL2Q
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL3Q
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_LSE
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t Periph)
+{
+  return LL_RCC_GetClockSource(Periph);
+}
+
+/**
+  * @brief  Get LPUART clock source
+  * @rmtoll D3CCIPR / SRDCCIPR       LPUART1SEL     LL_RCC_GetLPUARTClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL2Q
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL3Q
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t Periph)
+{
+  UNUSED(Periph);
+#if defined(RCC_D3CCIPR_LPUART1SEL)
+  return (uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL));
+#else
+  return (uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL));
+#endif  /* RCC_D3CCIPR_LPUART1SEL */
+}
+
+/**
+  * @brief  Get I2Cx clock source
+  * @rmtoll D2CCIP2R / CDCCIP2R     I2C123SEL       LL_RCC_GetI2CClockSource\n
+  *         D3CCIPR  / SRDCCIPR     I2C4SEL         LL_RCC_GetI2CClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_I2C123_CLKSOURCE
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_PLL3R
+  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_PLL3R
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_CSI
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t Periph)
+{
+  return LL_RCC_GetClockSource(Periph);
+}
+
+/**
+  * @brief  Get LPTIM clock source
+  * @rmtoll D2CCIP2R / CDCCIP2R      LPTIM1SEL     LL_RCC_GetLPTIMClockSource\n
+  *         D3CCIPR  / SRDCCIPR      LPTIM2SEL     LL_RCC_GetLPTIMClockSource\n
+  *         D3CCIPR  / SRDCCIPR      LPTIM345SEL   LL_RCC_GetLPTIMClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL2P
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL3R
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL2P
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL3R
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_CLKP
+  * @retval None
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t Periph)
+{
+  return LL_RCC_GetClockSource(Periph);
+}
+
+/**
+  * @brief  Get SAIx clock source
+  * @rmtoll D2CCIP1R / CDCCIP1R     SAI1SEL       LL_RCC_GetSAIClockSource\n
+  *         D2CCIP1R / CDCCIP1R     SAI23SEL      LL_RCC_GetSAIClockSource
+  *         D3CCIPR  / SRDCCIPR     SAI4ASEL      LL_RCC_GetSAIClockSource\n
+  *         D3CCIPR  / SRDCCIPR     SAI4BSEL      LL_RCC_GetSAIClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE    (*)
+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE  (*)
+   *         @arg @ref LL_RCC_SAI2B_CLKSOURCE  (*)
+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE   (*)
+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE   (*)
+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE   (*)
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL1Q (*)
+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL2P (*)
+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL3P (*)
+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_I2S_CKIN (*)
+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_CLKP (*)
+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL1Q (*)
+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL2P (*)
+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL3P (*)
+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN (*)
+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_CLKP (*)
+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_SPDIF (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL1Q (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL2P (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL3P (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_CLKP (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_SPDIF (*)
+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL1Q (*)
+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL2P (*)
+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL3P (*)
+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN (*)
+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_CLKP (*)
+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL1Q (*)
+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL2P (*)
+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL3P (*)
+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN (*)
+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_CLKP (*)
+  *
+  *  (*) value not defined in all devices.
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t Periph)
+{
+  return LL_RCC_GetClockSource(Periph);
+}
+
+/**
+  * @brief  Get SDMMC clock source
+  * @rmtoll D1CCIPR / CDCCIPR      SDMMCSEL      LL_RCC_GetSDMMCClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SDMMC_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_SDMMC_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_SDMMC_CLKSOURCE_PLL2R
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetSDMMCClockSource(uint32_t Periph)
+{
+  UNUSED(Periph);
+#if defined(RCC_D1CCIPR_SDMMCSEL)
+  return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL));
+#else
+  return (uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL));
+#endif /* RCC_D1CCIPR_SDMMCSEL */
+}
+
+/**
+  * @brief  Get RNG clock source
+  * @rmtoll D2CCIP2R        RNGSEL      LL_RCC_GetRNGClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_RNG_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48
+  *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_RNG_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_RNG_CLKSOURCE_LSI
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t Periph)
+{
+  UNUSED(Periph);
+#if defined(RCC_D2CCIP2R_RNGSEL)
+  return (uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL));
+#else
+  return (uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL));
+#endif /* RCC_D2CCIP2R_RNGSEL */
+}
+
+/**
+  * @brief  Get USB clock source
+  * @rmtoll D2CCIP2R / CDCCIP2R      USBSEL      LL_RCC_GetUSBClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_USB_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_USB_CLKSOURCE_DISABLE
+  *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL3Q
+  *         @arg @ref LL_RCC_USB_CLKSOURCE_HSI48
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t Periph)
+{
+  UNUSED(Periph);
+#if defined(RCC_D2CCIP2R_USBSEL)
+  return (uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL));
+#else
+  return (uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL));
+#endif /* RCC_D2CCIP2R_USBSEL */
+}
+
+/**
+  * @brief  Get CEC clock source
+  * @rmtoll D2CCIP2R / CDCCIP2R        CECSEL        LL_RCC_GetCECClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_CEC_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_CEC_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_CEC_CLKSOURCE_CSI_DIV122
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t Periph)
+{
+  UNUSED(Periph);
+#if defined(RCC_D2CCIP2R_CECSEL)
+  return (uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL));
+#else
+  return (uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_CECSEL));
+#endif  /* RCC_D2CCIP2R_CECSEL */
+}
+
+#if defined(DSI)
+/**
+  * @brief  Get DSI clock source
+  * @rmtoll D1CCIPR         DSISEL        LL_RCC_GetDSIClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_DSI_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
+  *         @arg @ref LL_RCC_DSI_CLKSOURCE_PLL2Q
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetDSIClockSource(uint32_t Periph)
+{
+  UNUSED(Periph);
+  return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_DSISEL));
+}
+#endif /* DSI */
+
+/**
+  * @brief  Get DFSDM Kernel clock source
+  * @rmtoll D2CCIP1R / CDCCIP1R         DFSDM1SEL        LL_RCC_GetDFSDMClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource(uint32_t Periph)
+{
+  UNUSED(Periph);
+#if defined(RCC_D2CCIP1R_DFSDM1SEL)
+  return (uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL));
+#else
+  return (uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL));
+#endif /* RCC_D2CCIP1R_DFSDM1SEL */
+}
+
+#if defined(DFSDM2_BASE)
+/**
+  * @brief  Get DFSDM2 Kernel clock source
+  * @rmtoll SRDCCIPR         DFSDM2SEL        LL_RCC_GetDFSDM2ClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_DFSDM2_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_DFSDM2_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_DFSDM2_CLKSOURCE_SYSCLK
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetDFSDM2ClockSource(uint32_t Periph)
+{
+  UNUSED(Periph);
+  return (uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL));
+}
+#endif /* DFSDM2_BASE */
+
+/**
+  * @brief  Get FMC Kernel clock source
+  * @rmtoll D1CCIPR / D1CCIPR         FMCSEL        LL_RCC_GetFMCClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_FMC_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_FMC_CLKSOURCE_HCLK
+  *         @arg @ref LL_RCC_FMC_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_FMC_CLKSOURCE_PLL2R
+  *         @arg @ref LL_RCC_FMC_CLKSOURCE_CLKP
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetFMCClockSource(uint32_t Periph)
+{
+  UNUSED(Periph);
+#if defined(RCC_D1CCIPR_FMCSEL)
+  return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL));
+#else
+  return (uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL));
+#endif /* RCC_D1CCIPR_FMCSEL */
+}
+
+#if defined(QUADSPI)
+/**
+  * @brief  Get QSPI Kernel clock source
+  * @rmtoll D1CCIPR  /  CDCCIPR      QSPISEL        LL_RCC_GetQSPIClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_QSPI_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_QSPI_CLKSOURCE_HCLK
+  *         @arg @ref LL_RCC_QSPI_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_QSPI_CLKSOURCE_PLL2R
+  *         @arg @ref LL_RCC_QSPI_CLKSOURCE_CLKP
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetQSPIClockSource(uint32_t Periph)
+{
+  UNUSED(Periph);
+  return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL));
+}
+#endif /* QUADSPI */
+
+#if defined(OCTOSPI1) || defined(OCTOSPI2)
+/**
+  * @brief  Get OSPI Kernel clock source
+  * @rmtoll CDCCIPR      OSPISEL        LL_RCC_GetOSPIClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_OSPI_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_OSPI_CLKSOURCE_HCLK
+  *         @arg @ref LL_RCC_OSPI_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_OSPI_CLKSOURCE_PLL2R
+  *         @arg @ref LL_RCC_OSPI_CLKSOURCE_CLKP
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetOSPIClockSource(uint32_t Periph)
+{
+  UNUSED(Periph);
+#if defined(RCC_D1CCIPR_OCTOSPISEL)
+  return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_OCTOSPISEL));
+#else
+  return (uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL));
+#endif /* RCC_D1CCIPR_OCTOSPISEL */
+}
+#endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */
+
+/**
+  * @brief  Get CLKP Kernel clock source
+  * @rmtoll D1CCIPR /  CDCCIPR       CKPERSEL        LL_RCC_GetCLKPClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_CLKP_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_CLKP_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_CLKP_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_CLKP_CLKSOURCE_HSE
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetCLKPClockSource(uint32_t Periph)
+{
+  UNUSED(Periph);
+#if defined(RCC_D1CCIPR_CKPERSEL)
+  return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL));
+#else
+  return (uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL));
+#endif /* RCC_D1CCIPR_CKPERSEL */
+}
+
+/**
+  * @brief  Get SPIx Kernel clock source
+  * @rmtoll D2CCIP1R / CDCCIP1R     SPI123SEL       LL_RCC_GetSPIClockSource\n
+  *         D2CCIP1R / CDCCIP1R     SPI45SEL        LL_RCC_GetSPIClockSource\n
+  *         D3CCIPR  / SRDCCIPR     SPI6SEL         LL_RCC_GetSPIClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL2P
+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL3P
+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_I2S_CKIN
+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL2Q
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL3Q
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_HSE
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_I2S_CKIN (*)
+  *
+  *         (*) value not defined in all stm32h7xx lines.
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetSPIClockSource(uint32_t Periph)
+{
+  return LL_RCC_GetClockSource(Periph);
+}
+
+/**
+  * @brief  Get SPDIF Kernel clock source
+  * @rmtoll D2CCIP1R / CDCCIP1R      SPDIFSEL        LL_RCC_GetSPDIFClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SPDIF_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL2R
+  *         @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL3R
+  *         @arg @ref LL_RCC_SPDIF_CLKSOURCE_HSI
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetSPDIFClockSource(uint32_t Periph)
+{
+  UNUSED(Periph);
+#if defined(RCC_D2CCIP1R_SPDIFSEL)
+  return (uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL));
+#else
+  return (uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL));
+#endif /* RCC_D2CCIP1R_SPDIFSEL */
+}
+
+/**
+  * @brief  Get FDCAN Kernel clock source
+  * @rmtoll D2CCIP1R / CDCCIP1R       FDCANSEL        LL_RCC_GetFDCANClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_FDCAN_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE
+  *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL2Q
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetFDCANClockSource(uint32_t Periph)
+{
+  UNUSED(Periph);
+#if defined(RCC_D2CCIP1R_FDCANSEL)
+  return (uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL));
+#else
+  return (uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_FDCANSEL));
+#endif /* RCC_D2CCIP1R_FDCANSEL */
+}
+
+/**
+  * @brief  Get SWP Kernel clock source
+  * @rmtoll D2CCIP1R / CDCCIP1R       SWPSEL        LL_RCC_GetSWPClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SWP_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_SWP_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_SWP_CLKSOURCE_HSI
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetSWPClockSource(uint32_t Periph)
+{
+  UNUSED(Periph);
+#if defined(RCC_D2CCIP1R_SWPSEL)
+  return (uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL));
+#else
+  return (uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL));
+#endif /* RCC_D2CCIP1R_SWPSEL */
+}
+
+/**
+  * @brief  Get ADC Kernel clock source
+  * @rmtoll D3CCIPR / SRDCCIPR       ADCSEL        LL_RCC_GetADCClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_ADC_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_ADC_CLKSOURCE_PLL2P
+  *         @arg @ref LL_RCC_ADC_CLKSOURCE_PLL3R
+  *         @arg @ref LL_RCC_ADC_CLKSOURCE_CLKP
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t Periph)
+{
+  UNUSED(Periph);
+#if defined (RCC_D3CCIPR_ADCSEL)
+  return (uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL));
+#else
+  return (uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL));
+#endif /* RCC_D3CCIPR_ADCSEL */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_RTC RTC
+  * @{
+  */
+
+/**
+  * @brief  Set RTC Clock Source
+  * @note   Once the RTC clock source has been selected, it cannot be changed anymore unless
+  *         the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
+  *         set). The BDRST bit can be used to reset them.
+  * @rmtoll BDCR         RTCSEL        LL_RCC_SetRTCClockSource
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
+{
+  MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
+}
+
+/**
+  * @brief  Get RTC Clock Source
+  * @rmtoll BDCR         RTCSEL        LL_RCC_GetRTCClockSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
+{
+  return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
+}
+
+/**
+  * @brief  Enable RTC
+  * @rmtoll BDCR         RTCEN         LL_RCC_EnableRTC
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableRTC(void)
+{
+  SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
+}
+
+/**
+  * @brief  Disable RTC
+  * @rmtoll BDCR         RTCEN         LL_RCC_DisableRTC
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableRTC(void)
+{
+  CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
+}
+
+/**
+  * @brief  Check if RTC has been enabled or not
+  * @rmtoll BDCR         RTCEN         LL_RCC_IsEnabledRTC
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
+{
+  return ((READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN))?1UL:0UL);
+}
+
+/**
+  * @brief  Force the Backup domain reset
+  * @rmtoll BDCR         BDRST / VSWRST         LL_RCC_ForceBackupDomainReset
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
+{
+  SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
+}
+
+/**
+  * @brief  Release the Backup domain reset
+  * @rmtoll BDCR         BDRST / VSWRST          LL_RCC_ReleaseBackupDomainReset
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
+{
+#if defined(RCC_BDCR_BDRST)
+  CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
+#else
+  CLEAR_BIT(RCC->BDCR, RCC_BDCR_VSWRST);
+#endif /* RCC_BDCR_BDRST */
+}
+
+/**
+  * @brief  Set HSE Prescalers for RTC Clock
+  * @rmtoll CFGR         RTCPRE        LL_RCC_SetRTC_HSEPrescaler
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_RTC_NOCLOCK
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_2
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_3
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_4
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_5
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_6
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_7
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_8
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_9
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_10
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_11
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_12
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_13
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_14
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_15
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_16
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_17
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_18
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_19
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_20
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_21
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_22
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_23
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_24
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_25
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_26
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_27
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_28
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_29
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_30
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_31
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_32
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_33
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_34
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_35
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_36
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_37
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_38
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_39
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_40
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_41
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_42
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_43
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_44
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_45
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_46
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_47
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_48
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_49
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_50
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_51
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_52
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_53
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_54
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_55
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_56
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_57
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_58
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_59
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_60
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_61
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_62
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_63
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler)
+{
+  MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, Prescaler);
+}
+
+/**
+  * @brief  Get HSE Prescalers for RTC Clock
+  * @rmtoll CFGR         RTCPRE        LL_RCC_GetRTC_HSEPrescaler
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_RTC_NOCLOCK
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_2
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_3
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_4
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_5
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_6
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_7
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_8
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_9
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_10
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_11
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_12
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_13
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_14
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_15
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_16
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_17
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_18
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_19
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_20
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_21
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_22
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_23
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_24
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_25
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_26
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_27
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_28
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_29
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_30
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_31
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_32
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_33
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_34
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_35
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_36
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_37
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_38
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_39
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_40
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_41
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_42
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_43
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_44
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_45
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_46
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_47
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_48
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_49
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_50
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_51
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_52
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_53
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_54
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_55
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_56
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_57
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_58
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_59
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_60
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_61
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_62
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_63
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_TIM_CLOCK_PRESCALER TIM
+  * @{
+  */
+
+/**
+  * @brief  Set Timers Clock Prescalers
+  * @rmtoll CFGR         TIMPRE        LL_RCC_SetTIMPrescaler
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_TIM_PRESCALER_TWICE
+  *         @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetTIMPrescaler(uint32_t Prescaler)
+{
+  MODIFY_REG(RCC->CFGR, RCC_CFGR_TIMPRE, Prescaler);
+}
+
+/**
+  * @brief  Get Timers Clock Prescalers
+  * @rmtoll CFGR         TIMPRE        LL_RCC_GetTIMPrescaler
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_TIM_PRESCALER_TWICE
+  *         @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetTIMPrescaler(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_TIMPRE));
+}
+
+/**
+  * @}
+  */
+
+#if defined(HRTIM1)
+/** @defgroup RCC_LL_EF_HRTIM_SET_CLOCK_SOURCE HRTIM
+  * @{
+  */
+
+/**
+  * @brief  Set High Resolution Timers Clock Source
+  * @rmtoll CFGR         HRTIMSEL        LL_RCC_SetHRTIMClockSource
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_HRTIM_CLKSOURCE_TIM
+  *         @arg @ref LL_RCC_HRTIM_CLKSOURCE_CPU
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetHRTIMClockSource(uint32_t Prescaler)
+{
+  MODIFY_REG(RCC->CFGR, RCC_CFGR_HRTIMSEL, Prescaler);
+}
+#endif /* HRTIM1 */
+
+#if defined(HRTIM1)
+/**
+  * @brief  Get High Resolution Timers Clock Source
+  * @rmtoll CFGR         HRTIMSEL        LL_RCC_GetHRTIMClockSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_HRTIM_CLKSOURCE_TIM
+  *         @arg @ref LL_RCC_HRTIM_CLKSOURCE_CPU
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetHRTIMClockSource(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HRTIMSEL));
+}
+/**
+  * @}
+  */
+#endif /* HRTIM1 */
+
+/** @defgroup RCC_LL_EF_PLL PLL
+  * @{
+  */
+
+/**
+  * @brief  Set the oscillator used as PLL clock source.
+  * @note   PLLSRC can be written only when All PLLs are disabled.
+  * @rmtoll PLLCKSELR      PLLSRC        LL_RCC_PLL_SetSource
+  * @param  PLLSource parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSOURCE_HSI
+  *         @arg @ref LL_RCC_PLLSOURCE_CSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSE
+  *         @arg @ref LL_RCC_PLLSOURCE_NONE
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL_SetSource(uint32_t PLLSource)
+{
+  MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC, PLLSource);
+}
+
+/**
+  * @brief  Get the oscillator used as PLL clock source.
+  * @rmtoll PLLCKSELR      PLLSRC        LL_RCC_PLL_GetSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSOURCE_HSI
+  *         @arg @ref LL_RCC_PLLSOURCE_CSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSE
+  *         @arg @ref LL_RCC_PLLSOURCE_NONE
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetSource(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC));
+}
+
+/**
+  * @brief  Enable PLL1
+  * @rmtoll CR           PLL1ON         LL_RCC_PLL1_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL1_Enable(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_PLL1ON);
+}
+
+/**
+  * @brief  Disable PLL1
+  * @note Cannot be disabled if the PLL1 clock is used as the system clock
+  * @rmtoll CR           PLL1ON         LL_RCC_PLL1_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL1_Disable(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON);
+}
+
+/**
+  * @brief  Check if PLL1 Ready
+  * @rmtoll CR           PLL1RDY        LL_RCC_PLL1_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL1_IsReady(void)
+{
+  return ((READ_BIT(RCC->CR, RCC_CR_PLL1RDY) == (RCC_CR_PLL1RDY))?1UL:0UL);
+}
+
+/**
+  * @brief  Enable PLL1P
+  * @note   This API shall be called only when PLL1 is disabled.
+  * @rmtoll PLLCFGR           DIVP1EN         LL_RCC_PLL1P_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL1P_Enable(void)
+{
+  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP1EN);
+}
+
+/**
+  * @brief  Enable PLL1Q
+  * @note   This API shall be called only when PLL1 is disabled.
+  * @rmtoll PLLCFGR           DIVQ1EN         LL_RCC_PLL1Q_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL1Q_Enable(void)
+{
+  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ1EN);
+}
+
+/**
+  * @brief  Enable PLL1R
+  * @note   This API shall be called only when PLL1 is disabled.
+  * @rmtoll PLLCFGR           DIVR1EN         LL_RCC_PLL1R_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL1R_Enable(void)
+{
+  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR1EN);
+}
+
+/**
+  * @brief  Enable PLL1 FRACN
+  * @rmtoll PLLCFGR           PLL1FRACEN         LL_RCC_PLL1FRACN_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL1FRACN_Enable(void)
+{
+  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN);
+}
+
+/**
+  * @brief  Check if PLL1 P is enabled
+  * @rmtoll PLLCFGR           DIVP1EN         LL_RCC_PLL1P_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL1P_IsEnabled(void)
+{
+  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP1EN) == RCC_PLLCFGR_DIVP1EN)?1UL:0UL);
+}
+
+/**
+  * @brief  Check if PLL1 Q is enabled
+  * @rmtoll PLLCFGR           DIVQ1EN         LL_RCC_PLL1Q_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL1Q_IsEnabled(void)
+{
+  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ1EN) == RCC_PLLCFGR_DIVQ1EN)?1UL:0UL);
+}
+
+/**
+  * @brief  Check if PLL1 R is enabled
+  * @rmtoll PLLCFGR           DIVR1EN         LL_RCC_PLL1R_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL1R_IsEnabled(void)
+{
+  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR1EN) == RCC_PLLCFGR_DIVR1EN)?1UL:0UL);
+}
+
+/**
+  * @brief  Check if PLL1 FRACN is enabled
+  * @rmtoll PLLCFGR           PLL1FRACEN         LL_RCC_PLL1FRACN_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL1FRACN_IsEnabled(void)
+{
+  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN) == RCC_PLLCFGR_PLL1FRACEN)?1UL:0UL);
+}
+
+/**
+  * @brief  Disable PLL1P
+  * @note   This API shall be called only when PLL1 is disabled.
+  * @rmtoll PLLCFGR           DIVP1EN         LL_RCC_PLL1P_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL1P_Disable(void)
+{
+  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP1EN);
+}
+
+/**
+  * @brief  Disable PLL1Q
+  * @note   This API shall be called only when PLL1 is disabled.
+  * @rmtoll PLLCFGR           DIVQ1EN         LL_RCC_PLL1Q_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL1Q_Disable(void)
+{
+  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ1EN);
+}
+
+/**
+  * @brief  Disable PLL1R
+  * @note   This API shall be called only when PLL1 is disabled.
+  * @rmtoll PLLCFGR           DIVR1EN         LL_RCC_PLL1R_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL1R_Disable(void)
+{
+  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR1EN);
+}
+
+/**
+  * @brief  Disable PLL1 FRACN
+  * @rmtoll PLLCFGR           PLL1FRACEN         LL_RCC_PLL1FRACN_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL1FRACN_Disable(void)
+{
+  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN);
+}
+
+/**
+  * @brief  Set PLL1 VCO OutputRange
+  * @note   This API shall be called only when PLL1 is disabled.
+  * @rmtoll PLLCFGR        PLL1VCOSEL       LL_RCC_PLL1_SetVCOOuputRange
+  * @param  VCORange This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLVCORANGE_WIDE
+  *         @arg @ref LL_RCC_PLLVCORANGE_MEDIUM
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL1_SetVCOOutputRange(uint32_t VCORange)
+{
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1VCOSEL, VCORange << RCC_PLLCFGR_PLL1VCOSEL_Pos);
+}
+
+/**
+  * @brief  Set PLL1 VCO Input Range
+  * @note   This API shall be called only when PLL1 is disabled.
+  * @rmtoll PLLCFGR        PLL1RGE       LL_RCC_PLL1_SetVCOInputRange
+  * @param  InputRange This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLINPUTRANGE_1_2
+  *         @arg @ref LL_RCC_PLLINPUTRANGE_2_4
+  *         @arg @ref LL_RCC_PLLINPUTRANGE_4_8
+  *         @arg @ref LL_RCC_PLLINPUTRANGE_8_16
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL1_SetVCOInputRange(uint32_t InputRange)
+{
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1RGE, InputRange << RCC_PLLCFGR_PLL1RGE_Pos);
+}
+
+/**
+  * @brief  Get PLL1 N Coefficient
+  * @rmtoll PLL1DIVR        N1          LL_RCC_PLL1_GetN
+  * @retval A value between 4 and 512
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL1_GetN(void)
+{
+  return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_N1) >>  RCC_PLL1DIVR_N1_Pos) + 1UL);
+}
+
+/**
+  * @brief  Get PLL1 M Coefficient
+  * @rmtoll PLLCKSELR       DIVM1          LL_RCC_PLL1_GetM
+  * @retval A value between 0 and 63
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL1_GetM(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM1) >>  RCC_PLLCKSELR_DIVM1_Pos);
+}
+
+/**
+  * @brief  Get PLL1 P Coefficient
+  * @rmtoll PLL1DIVR        P1          LL_RCC_PLL1_GetP
+  * @retval A value between 2 and 128
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL1_GetP(void)
+{
+  return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_P1) >>  RCC_PLL1DIVR_P1_Pos) + 1UL);
+}
+
+/**
+  * @brief  Get PLL1 Q Coefficient
+  * @rmtoll PLL1DIVR        Q1          LL_RCC_PLL1_GetQ
+  * @retval A value between 1 and 128
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL1_GetQ(void)
+{
+  return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_Q1) >>  RCC_PLL1DIVR_Q1_Pos) + 1UL);
+}
+
+/**
+  * @brief  Get PLL1 R Coefficient
+  * @rmtoll PLL1DIVR        R1          LL_RCC_PLL1_GetR
+  * @retval A value between 1 and 128
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL1_GetR(void)
+{
+  return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_R1) >>  RCC_PLL1DIVR_R1_Pos) + 1UL);
+}
+
+/**
+  * @brief  Get PLL1 FRACN Coefficient
+  * @rmtoll PLL1FRACR      FRACN1          LL_RCC_PLL1_GetFRACN
+  * @retval A value between 0 and 8191 (0x1FFF)
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL1_GetFRACN(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACN1) >>  RCC_PLL1FRACR_FRACN1_Pos);
+}
+
+/**
+  * @brief  Set PLL1 N Coefficient
+  * @note   This API shall be called only when PLL1 is disabled.
+  * @rmtoll PLL1DIVR        N1          LL_RCC_PLL1_SetN
+  * @param  N parameter can be a value between 4 and 512
+  */
+__STATIC_INLINE void LL_RCC_PLL1_SetN(uint32_t N)
+{
+  MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_N1, (N-1UL) << RCC_PLL1DIVR_N1_Pos);
+}
+
+/**
+  * @brief  Set PLL1 M Coefficient
+  * @note   This API shall be called only when PLL1 is disabled.
+  * @rmtoll PLLCKSELR       DIVM1          LL_RCC_PLL1_SetM
+  * @param  M parameter can be a value between 0 and 63
+  */
+__STATIC_INLINE void LL_RCC_PLL1_SetM(uint32_t M)
+{
+  MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM1, M << RCC_PLLCKSELR_DIVM1_Pos);
+}
+
+/**
+  * @brief  Set PLL1 P Coefficient
+  * @note   This API shall be called only when PLL1 is disabled.
+  * @rmtoll PLL1DIVR        P1          LL_RCC_PLL1_SetP
+  * @param  P parameter can be a value between 2 (or 1*) and 128 (ODD division factor not supported)
+  *
+  * (*) : For stm32h72xxx and stm32h73xxx family lines.
+  */
+__STATIC_INLINE void LL_RCC_PLL1_SetP(uint32_t P)
+{
+  MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_P1, (P-1UL) << RCC_PLL1DIVR_P1_Pos);
+}
+
+/**
+  * @brief  Set PLL1 Q Coefficient
+  * @note   This API shall be called only when PLL1 is disabled.
+  * @rmtoll PLL1DIVR        Q1          LL_RCC_PLL1_SetQ
+  * @param  Q parameter can be a value between 1 and 128
+  */
+__STATIC_INLINE void LL_RCC_PLL1_SetQ(uint32_t Q)
+{
+  MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_Q1, (Q-1UL) << RCC_PLL1DIVR_Q1_Pos);
+}
+
+/**
+  * @brief  Set PLL1 R Coefficient
+  * @note   This API shall be called only when PLL1 is disabled.
+  * @rmtoll PLL1DIVR        R1          LL_RCC_PLL1_SetR
+  * @param  R parameter can be a value between 1 and 128
+  */
+__STATIC_INLINE void LL_RCC_PLL1_SetR(uint32_t R)
+{
+  MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_R1, (R-1UL) << RCC_PLL1DIVR_R1_Pos);
+}
+
+/**
+  * @brief  Set PLL1 FRACN Coefficient
+  * @rmtoll PLL1FRACR        FRACN1          LL_RCC_PLL1_SetFRACN
+  * @param  FRACN parameter can be a value between 0 and 8191 (0x1FFF)
+  */
+__STATIC_INLINE void LL_RCC_PLL1_SetFRACN(uint32_t FRACN)
+{
+  MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACN1, FRACN << RCC_PLL1FRACR_FRACN1_Pos);
+}
+
+/**
+  * @brief  Enable PLL2
+  * @rmtoll CR           PLL2ON         LL_RCC_PLL2_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL2_Enable(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_PLL2ON);
+}
+
+/**
+  * @brief  Disable PLL2
+  * @note Cannot be disabled if the PLL2 clock is used as the system clock
+  * @rmtoll CR           PLL2ON         LL_RCC_PLL2_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL2_Disable(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON);
+}
+
+/**
+  * @brief  Check if PLL2 Ready
+  * @rmtoll CR           PLL2RDY        LL_RCC_PLL2_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL2_IsReady(void)
+{
+  return ((READ_BIT(RCC->CR, RCC_CR_PLL2RDY) == (RCC_CR_PLL2RDY))?1UL:0UL);
+}
+
+/**
+  * @brief  Enable PLL2P
+  * @note   This API shall be called only when PLL2 is disabled.
+  * @rmtoll PLLCFGR           DIVP2EN         LL_RCC_PLL2P_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL2P_Enable(void)
+{
+  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP2EN);
+}
+
+/**
+  * @brief  Enable PLL2Q
+  * @note   This API shall be called only when PLL2 is disabled.
+  * @rmtoll PLLCFGR           DIVQ2EN         LL_RCC_PLL2Q_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL2Q_Enable(void)
+{
+  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ2EN);
+}
+
+/**
+  * @brief  Enable PLL2R
+  * @note   This API shall be called only when PLL2 is disabled.
+  * @rmtoll PLLCFGR           DIVR2EN         LL_RCC_PLL2R_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL2R_Enable(void)
+{
+  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR2EN);
+}
+
+/**
+  * @brief  Enable PLL2 FRACN
+  * @rmtoll PLLCFGR           PLL2FRACEN         LL_RCC_PLL2FRACN_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL2FRACN_Enable(void)
+{
+  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN);
+}
+
+/**
+  * @brief  Check if PLL2 P is enabled
+  * @rmtoll PLLCFGR           DIVP2EN         LL_RCC_PLL2P_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL2P_IsEnabled(void)
+{
+  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP2EN) == RCC_PLLCFGR_DIVP2EN)?1UL:0UL);
+}
+
+/**
+  * @brief  Check if PLL2 Q is enabled
+  * @rmtoll PLLCFGR           DIVQ2EN         LL_RCC_PLL2Q_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL2Q_IsEnabled(void)
+{
+  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ2EN) == RCC_PLLCFGR_DIVQ2EN)?1UL:0UL);
+}
+
+/**
+  * @brief  Check if PLL2 R is enabled
+  * @rmtoll PLLCFGR           DIVR2EN         LL_RCC_PLL2R_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL2R_IsEnabled(void)
+{
+  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR2EN) == RCC_PLLCFGR_DIVR2EN)?1UL:0UL);
+}
+
+/**
+  * @brief  Check if PLL2 FRACN is enabled
+  * @rmtoll PLLCFGR           PLL2FRACEN         LL_RCC_PLL2FRACN_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL2FRACN_IsEnabled(void)
+{
+  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN) == RCC_PLLCFGR_PLL2FRACEN)?1UL:0UL);
+}
+
+/**
+  * @brief  Disable PLL2P
+  * @note   This API shall be called only when PLL2 is disabled.
+  * @rmtoll PLLCFGR           DIVP2EN         LL_RCC_PLL2P_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL2P_Disable(void)
+{
+  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP2EN);
+}
+
+/**
+  * @brief  Disable PLL2Q
+  * @note   This API shall be called only when PLL2 is disabled.
+  * @rmtoll PLLCFGR           DIVQ2EN         LL_RCC_PLL2Q_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL2Q_Disable(void)
+{
+  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ2EN);
+}
+
+/**
+  * @brief  Disable PLL2R
+  * @note   This API shall be called only when PLL2 is disabled.
+  * @rmtoll PLLCFGR           DIVR2EN         LL_RCC_PLL2R_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL2R_Disable(void)
+{
+  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR2EN);
+}
+
+/**
+  * @brief  Disable PLL2 FRACN
+  * @rmtoll PLLCFGR           PLL2FRACEN         LL_RCC_PLL2FRACN_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL2FRACN_Disable(void)
+{
+  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN);
+}
+
+/**
+  * @brief  Set PLL2 VCO OutputRange
+  * @note   This API shall be called only when PLL2 is disabled.
+  * @rmtoll PLLCFGR        PLL2VCOSEL       LL_RCC_PLL2_SetVCOOuputRange
+  * @param  VCORange This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLVCORANGE_WIDE
+  *         @arg @ref LL_RCC_PLLVCORANGE_MEDIUM
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL2_SetVCOOutputRange(uint32_t VCORange)
+{
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2VCOSEL, VCORange << RCC_PLLCFGR_PLL2VCOSEL_Pos);
+}
+
+/**
+  * @brief  Set PLL2 VCO Input Range
+  * @note   This API shall be called only when PLL2 is disabled.
+  * @rmtoll PLLCFGR        PLL2RGE       LL_RCC_PLL2_SetVCOInputRange
+  * @param  InputRange This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLINPUTRANGE_1_2
+  *         @arg @ref LL_RCC_PLLINPUTRANGE_2_4
+  *         @arg @ref LL_RCC_PLLINPUTRANGE_4_8
+  *         @arg @ref LL_RCC_PLLINPUTRANGE_8_16
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL2_SetVCOInputRange(uint32_t InputRange)
+{
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2RGE, InputRange << RCC_PLLCFGR_PLL2RGE_Pos);
+}
+
+/**
+  * @brief  Get PLL2 N Coefficient
+  * @rmtoll PLL2DIVR        N2          LL_RCC_PLL2_GetN
+  * @retval A value between 4 and 512
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL2_GetN(void)
+{
+  return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_N2) >>  RCC_PLL2DIVR_N2_Pos) + 1UL);
+}
+
+/**
+  * @brief  Get PLL2 M Coefficient
+  * @rmtoll PLLCKSELR       DIVM2          LL_RCC_PLL2_GetM
+  * @retval A value between 0 and 63
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL2_GetM(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM2) >>  RCC_PLLCKSELR_DIVM2_Pos);
+}
+
+/**
+  * @brief  Get PLL2 P Coefficient
+  * @rmtoll PLL2DIVR        P2          LL_RCC_PLL2_GetP
+  * @retval A value between 1 and 128
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL2_GetP(void)
+{
+  return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_P2) >>  RCC_PLL2DIVR_P2_Pos) + 1UL);
+}
+
+/**
+  * @brief  Get PLL2 Q Coefficient
+  * @rmtoll PLL2DIVR        Q2          LL_RCC_PLL2_GetQ
+  * @retval A value between 1 and 128
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL2_GetQ(void)
+{
+  return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_Q2) >>  RCC_PLL2DIVR_Q2_Pos) + 1UL);
+}
+
+/**
+  * @brief  Get PLL2 R Coefficient
+  * @rmtoll PLL2DIVR        R2          LL_RCC_PLL2_GetR
+  * @retval A value between 1 and 128
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL2_GetR(void)
+{
+  return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_R2) >>  RCC_PLL2DIVR_R2_Pos) + 1UL);
+}
+
+/**
+  * @brief  Get PLL2 FRACN Coefficient
+  * @rmtoll PLL2FRACR      FRACN2          LL_RCC_PLL2_GetFRACN
+  * @retval A value between 0 and 8191 (0x1FFF)
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL2_GetFRACN(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN2) >>  RCC_PLL2FRACR_FRACN2_Pos);
+}
+
+/**
+  * @brief  Set PLL2 N Coefficient
+  * @note   This API shall be called only when PLL2 is disabled.
+  * @rmtoll PLL2DIVR        N2          LL_RCC_PLL2_SetN
+  * @param  N parameter can be a value between 4 and 512
+  */
+__STATIC_INLINE void LL_RCC_PLL2_SetN(uint32_t N)
+{
+  MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_N2, (N-1UL) << RCC_PLL2DIVR_N2_Pos);
+}
+
+/**
+  * @brief  Set PLL2 M Coefficient
+  * @note   This API shall be called only when PLL2 is disabled.
+  * @rmtoll PLLCKSELR       DIVM2          LL_RCC_PLL2_SetM
+  * @param  M parameter can be a value between 0 and 63
+  */
+__STATIC_INLINE void LL_RCC_PLL2_SetM(uint32_t M)
+{
+  MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM2, M << RCC_PLLCKSELR_DIVM2_Pos);
+}
+
+/**
+  * @brief  Set PLL2 P Coefficient
+  * @note   This API shall be called only when PLL2 is disabled.
+  * @rmtoll PLL2DIVR        P2          LL_RCC_PLL2_SetP
+  * @param  P parameter can be a value between 1 and 128
+  */
+__STATIC_INLINE void LL_RCC_PLL2_SetP(uint32_t P)
+{
+  MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_P2, (P-1UL) << RCC_PLL2DIVR_P2_Pos);
+}
+
+/**
+  * @brief  Set PLL2 Q Coefficient
+  * @note   This API shall be called only when PLL2 is disabled.
+  * @rmtoll PLL2DIVR        Q2          LL_RCC_PLL2_SetQ
+  * @param  Q parameter can be a value between 1 and 128
+  */
+__STATIC_INLINE void LL_RCC_PLL2_SetQ(uint32_t Q)
+{
+  MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_Q2, (Q-1UL) << RCC_PLL2DIVR_Q2_Pos);
+}
+
+/**
+  * @brief  Set PLL2 R Coefficient
+  * @note   This API shall be called only when PLL2 is disabled.
+  * @rmtoll PLL2DIVR        R2          LL_RCC_PLL2_SetR
+  * @param  R parameter can be a value between 1 and 128
+  */
+__STATIC_INLINE void LL_RCC_PLL2_SetR(uint32_t R)
+{
+  MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_R2, (R-1UL) << RCC_PLL2DIVR_R2_Pos);
+}
+
+/**
+  * @brief  Set PLL2 FRACN Coefficient
+  * @rmtoll PLL2FRACR        FRACN2          LL_RCC_PLL2_SetFRACN
+  * @param  FRACN parameter can be a value between 0 and 8191 (0x1FFF)
+  */
+__STATIC_INLINE void LL_RCC_PLL2_SetFRACN(uint32_t FRACN)
+{
+  MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN2, FRACN << RCC_PLL2FRACR_FRACN2_Pos);
+}
+
+/**
+  * @brief  Enable PLL3
+  * @rmtoll CR           PLL3ON         LL_RCC_PLL3_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL3_Enable(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_PLL3ON);
+}
+
+/**
+  * @brief  Disable PLL3
+  * @note Cannot be disabled if the PLL3 clock is used as the system clock
+  * @rmtoll CR           PLL3ON         LL_RCC_PLL3_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL3_Disable(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON);
+}
+
+/**
+  * @brief  Check if PLL3 Ready
+  * @rmtoll CR           PLL3RDY        LL_RCC_PLL3_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL3_IsReady(void)
+{
+  return ((READ_BIT(RCC->CR, RCC_CR_PLL3RDY) == (RCC_CR_PLL3RDY))?1UL:0UL);
+}
+
+/**
+  * @brief  Enable PLL3P
+  * @note   This API shall be called only when PLL3 is disabled.
+  * @rmtoll PLLCFGR           DIVP3EN         LL_RCC_PLL3P_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL3P_Enable(void)
+{
+  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP3EN);
+}
+
+/**
+  * @brief  Enable PLL3Q
+  * @note   This API shall be called only when PLL3 is disabled.
+  * @rmtoll PLLCFGR           DIVQ3EN         LL_RCC_PLL3Q_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL3Q_Enable(void)
+{
+  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ3EN);
+}
+
+/**
+  * @brief  Enable PLL3R
+  * @note   This API shall be called only when PLL3 is disabled.
+  * @rmtoll PLLCFGR           DIVR3EN         LL_RCC_PLL3R_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL3R_Enable(void)
+{
+  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR3EN);
+}
+
+/**
+  * @brief  Enable PLL3 FRACN
+  * @rmtoll PLLCFGR           PLL3FRACEN         LL_RCC_PLL3FRACN_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL3FRACN_Enable(void)
+{
+  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN);
+}
+
+/**
+  * @brief  Check if PLL3 P is enabled
+  * @rmtoll PLLCFGR           DIVP3EN         LL_RCC_PLL3P_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL3P_IsEnabled(void)
+{
+  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP3EN) == RCC_PLLCFGR_DIVP3EN)?1UL:0UL);
+}
+
+/**
+  * @brief  Check if PLL3 Q is enabled
+  * @rmtoll PLLCFGR           DIVQ3EN         LL_RCC_PLL3Q_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL3Q_IsEnabled(void)
+{
+  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ3EN) == RCC_PLLCFGR_DIVQ3EN)?1UL:0UL);
+}
+
+/**
+  * @brief  Check if PLL3 R is enabled
+  * @rmtoll PLLCFGR           DIVR3EN         LL_RCC_PLL3R_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL3R_IsEnabled(void)
+{
+  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR3EN) == RCC_PLLCFGR_DIVR3EN)?1UL:0UL);
+}
+
+/**
+  * @brief  Check if PLL3 FRACN is enabled
+  * @rmtoll PLLCFGR           PLL3FRACEN         LL_RCC_PLL3FRACN_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL3FRACN_IsEnabled(void)
+{
+  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN) == RCC_PLLCFGR_PLL3FRACEN)?1UL:0UL);
+}
+
+/**
+  * @brief  Disable PLL3P
+  * @note   This API shall be called only when PLL3 is disabled.
+  * @rmtoll PLLCFGR           DIVP2EN         LL_RCC_PLL3P_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL3P_Disable(void)
+{
+  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP3EN);
+}
+
+/**
+  * @brief  Disable PLL3Q
+  * @note   This API shall be called only when PLL3 is disabled.
+  * @rmtoll PLLCFGR           DIVQ3EN         LL_RCC_PLL3Q_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL3Q_Disable(void)
+{
+  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ3EN);
+}
+
+/**
+  * @brief  Disable PLL3R
+  * @note   This API shall be called only when PLL3 is disabled.
+  * @rmtoll PLLCFGR           DIVR3EN         LL_RCC_PLL3R_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL3R_Disable(void)
+{
+  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR3EN);
+}
+
+/**
+  * @brief  Disable PLL3 FRACN
+  * @rmtoll PLLCFGR           PLL3FRACEN         LL_RCC_PLL3FRACN_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL3FRACN_Disable(void)
+{
+  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN);
+}
+
+/**
+  * @brief  Set PLL3 VCO OutputRange
+  * @note   This API shall be called only when PLL3 is disabled.
+  * @rmtoll PLLCFGR        PLL3VCOSEL       LL_RCC_PLL3_SetVCOOuputRange
+  * @param  VCORange This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLVCORANGE_WIDE
+  *         @arg @ref LL_RCC_PLLVCORANGE_MEDIUM
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL3_SetVCOOutputRange(uint32_t VCORange)
+{
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3VCOSEL, VCORange << RCC_PLLCFGR_PLL3VCOSEL_Pos);
+}
+
+/**
+  * @brief  Set PLL3 VCO Input Range
+  * @note   This API shall be called only when PLL3 is disabled.
+  * @rmtoll PLLCFGR        PLL3RGE       LL_RCC_PLL3_SetVCOInputRange
+  * @param  InputRange This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLINPUTRANGE_1_2
+  *         @arg @ref LL_RCC_PLLINPUTRANGE_2_4
+  *         @arg @ref LL_RCC_PLLINPUTRANGE_4_8
+  *         @arg @ref LL_RCC_PLLINPUTRANGE_8_16
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL3_SetVCOInputRange(uint32_t InputRange)
+{
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3RGE, InputRange << RCC_PLLCFGR_PLL3RGE_Pos);
+}
+
+/**
+  * @brief  Get PLL3 N Coefficient
+  * @rmtoll PLL3DIVR        N3          LL_RCC_PLL3_GetN
+  * @retval A value between 4 and 512
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL3_GetN(void)
+{
+  return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_N3) >>  RCC_PLL3DIVR_N3_Pos) + 1UL);
+}
+
+/**
+  * @brief  Get PLL3 M Coefficient
+  * @rmtoll PLLCKSELR       DIVM3          LL_RCC_PLL3_GetM
+  * @retval A value between 0 and 63
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL3_GetM(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM3) >>  RCC_PLLCKSELR_DIVM3_Pos);
+}
+
+/**
+  * @brief  Get PLL3 P Coefficient
+  * @rmtoll PLL3DIVR        P3          LL_RCC_PLL3_GetP
+  * @retval A value between 1 and 128
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL3_GetP(void)
+{
+  return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_P3) >>  RCC_PLL3DIVR_P3_Pos) + 1UL);
+}
+
+/**
+  * @brief  Get PLL3 Q Coefficient
+  * @rmtoll PLL3DIVR        Q3          LL_RCC_PLL3_GetQ
+  * @retval A value between 1 and 128
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL3_GetQ(void)
+{
+  return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_Q3) >>  RCC_PLL3DIVR_Q3_Pos) + 1UL);
+}
+
+/**
+  * @brief  Get PLL3 R Coefficient
+  * @rmtoll PLL3DIVR        R3          LL_RCC_PLL3_GetR
+  * @retval A value between 1 and 128
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL3_GetR(void)
+{
+  return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_R3) >>  RCC_PLL3DIVR_R3_Pos) + 1UL);
+}
+
+/**
+  * @brief  Get PLL3 FRACN Coefficient
+  * @rmtoll PLL3FRACR      FRACN3          LL_RCC_PLL3_GetFRACN
+  * @retval A value between 0 and 8191 (0x1FFF)
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL3_GetFRACN(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3) >>  RCC_PLL3FRACR_FRACN3_Pos);
+}
+
+/**
+  * @brief  Set PLL3 N Coefficient
+  * @note   This API shall be called only when PLL3 is disabled.
+  * @rmtoll PLL3DIVR        N3          LL_RCC_PLL3_SetN
+  * @param  N parameter can be a value between 4 and 512
+  */
+__STATIC_INLINE void LL_RCC_PLL3_SetN(uint32_t N)
+{
+  MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_N3, (N-1UL) << RCC_PLL3DIVR_N3_Pos);
+}
+
+/**
+  * @brief  Set PLL3 M Coefficient
+  * @note   This API shall be called only when PLL3 is disabled.
+  * @rmtoll PLLCKSELR       DIVM3          LL_RCC_PLL3_SetM
+  * @param  M parameter can be a value between 0 and 63
+  */
+__STATIC_INLINE void LL_RCC_PLL3_SetM(uint32_t M)
+{
+  MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM3, M << RCC_PLLCKSELR_DIVM3_Pos);
+}
+
+/**
+  * @brief  Set PLL3 P Coefficient
+  * @note   This API shall be called only when PLL3 is disabled.
+  * @rmtoll PLL3DIVR        P3          LL_RCC_PLL3_SetP
+  * @param  P parameter can be a value between 1 and 128
+  */
+__STATIC_INLINE void LL_RCC_PLL3_SetP(uint32_t P)
+{
+  MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_P3, (P-1UL) << RCC_PLL3DIVR_P3_Pos);
+}
+
+/**
+  * @brief  Set PLL3 Q Coefficient
+  * @note   This API shall be called only when PLL3 is disabled.
+  * @rmtoll PLL3DIVR        Q3          LL_RCC_PLL3_SetQ
+  * @param  Q parameter can be a value between 1 and 128
+  */
+__STATIC_INLINE void LL_RCC_PLL3_SetQ(uint32_t Q)
+{
+  MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_Q3, (Q-1UL) << RCC_PLL3DIVR_Q3_Pos);
+}
+
+/**
+  * @brief  Set PLL3 R Coefficient
+  * @note   This API shall be called only when PLL3 is disabled.
+  * @rmtoll PLL3DIVR        R3          LL_RCC_PLL3_SetR
+  * @param  R parameter can be a value between 1 and 128
+  */
+__STATIC_INLINE void LL_RCC_PLL3_SetR(uint32_t R)
+{
+  MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_R3, (R-1UL) << RCC_PLL3DIVR_R3_Pos);
+}
+
+/**
+  * @brief  Set PLL3 FRACN Coefficient
+  * @rmtoll PLL3FRACR        FRACN3          LL_RCC_PLL3_SetFRACN
+  * @param  FRACN parameter can be a value between 0 and 8191 (0x1FFF)
+  */
+__STATIC_INLINE void LL_RCC_PLL3_SetFRACN(uint32_t FRACN)
+{
+  MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3, FRACN << RCC_PLL3FRACR_FRACN3_Pos);
+}
+
+
+/**
+  * @}
+  */
+
+
+/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
+  * @{
+  */
+
+/**
+  * @brief  Clear LSI ready interrupt flag
+  * @rmtoll CICR         LSIRDYC       LL_RCC_ClearFlag_LSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
+{
+  SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC);
+}
+
+/**
+  * @brief  Clear LSE ready interrupt flag
+  * @rmtoll CICR         LSERDYC       LL_RCC_ClearFlag_LSERDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
+{
+  SET_BIT(RCC->CICR, RCC_CICR_LSERDYC);
+}
+
+/**
+  * @brief  Clear HSI ready interrupt flag
+  * @rmtoll CICR         HSIRDYC       LL_RCC_ClearFlag_HSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
+{
+  SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC);
+}
+
+/**
+  * @brief  Clear HSE ready interrupt flag
+  * @rmtoll CICR         HSERDYC       LL_RCC_ClearFlag_HSERDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
+{
+  SET_BIT(RCC->CICR, RCC_CICR_HSERDYC);
+}
+
+/**
+  * @brief  Clear CSI ready interrupt flag
+  * @rmtoll CICR         CSIRDYC       LL_RCC_ClearFlag_CSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_CSIRDY(void)
+{
+  SET_BIT(RCC->CICR, RCC_CICR_CSIRDYC);
+}
+
+/**
+  * @brief  Clear HSI48 ready interrupt flag
+  * @rmtoll CICR         HSI48RDYC       LL_RCC_ClearFlag_HSI48RDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void)
+{
+  SET_BIT(RCC->CICR, RCC_CICR_HSI48RDYC);
+}
+
+/**
+  * @brief  Clear PLL1 ready interrupt flag
+  * @rmtoll CICR         PLL1RDYC       LL_RCC_ClearFlag_PLL1RDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_PLL1RDY(void)
+{
+  SET_BIT(RCC->CICR, RCC_CICR_PLLRDYC);
+}
+
+/**
+  * @brief  Clear PLL2 ready interrupt flag
+  * @rmtoll CICR         PLL2RDYC       LL_RCC_ClearFlag_PLL2RDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_PLL2RDY(void)
+{
+  SET_BIT(RCC->CICR, RCC_CICR_PLL2RDYC);
+}
+
+/**
+  * @brief  Clear PLL3 ready interrupt flag
+  * @rmtoll CICR         PLL3RDYC       LL_RCC_ClearFlag_PLL3RDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_PLL3RDY(void)
+{
+  SET_BIT(RCC->CICR, RCC_CICR_PLL3RDYC);
+}
+
+/**
+  * @brief  Clear LSE Clock security system interrupt flag
+  * @rmtoll CICR         LSECSSC         LL_RCC_ClearFlag_LSECSS
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void)
+{
+  SET_BIT(RCC->CICR, RCC_CICR_LSECSSC);
+}
+
+/**
+  * @brief  Clear HSE Clock security system interrupt flag
+  * @rmtoll CICR         HSECSSC         LL_RCC_ClearFlag_HSECSS
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
+{
+  SET_BIT(RCC->CICR, RCC_CICR_HSECSSC);
+}
+
+/**
+  * @brief  Check if LSI ready interrupt occurred or not
+  * @rmtoll CIFR         LSIRDYF       LL_RCC_IsActiveFlag_LSIRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
+{
+  return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == (RCC_CIFR_LSIRDYF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if LSE ready interrupt occurred or not
+  * @rmtoll CIFR         LSERDYF       LL_RCC_IsActiveFlag_LSERDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
+{
+  return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == (RCC_CIFR_LSERDYF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if HSI ready interrupt occurred or not
+  * @rmtoll CIFR         HSIRDYF       LL_RCC_IsActiveFlag_HSIRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
+{
+  return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == (RCC_CIFR_HSIRDYF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if HSE ready interrupt occurred or not
+  * @rmtoll CIFR         HSERDYF       LL_RCC_IsActiveFlag_HSERDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
+{
+  return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == (RCC_CIFR_HSERDYF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if CSI ready interrupt occurred or not
+  * @rmtoll CIFR         CSIRDYF       LL_RCC_IsActiveFlag_CSIRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CSIRDY(void)
+{
+  return ((READ_BIT(RCC->CIFR, RCC_CIFR_CSIRDYF) == (RCC_CIFR_CSIRDYF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if HSI48 ready interrupt occurred or not
+  * @rmtoll CIFR         HSI48RDYF       LL_RCC_IsActiveFlag_HSI48RDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void)
+{
+  return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == (RCC_CIFR_HSI48RDYF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if PLL1 ready interrupt occurred or not
+  * @rmtoll CIFR         PLLRDYF       LL_RCC_IsActiveFlag_PLL1RDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL1RDY(void)
+{
+  return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLRDYF) == (RCC_CIFR_PLLRDYF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if PLL2 ready interrupt occurred or not
+  * @rmtoll CIFR         PLL2RDYF       LL_RCC_IsActiveFlag_PLL2RDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL2RDY(void)
+{
+  return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL2RDYF) == (RCC_CIFR_PLL2RDYF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if PLL3 ready interrupt occurred or not
+  * @rmtoll CIFR         PLL3RDYF       LL_RCC_IsActiveFlag_PLL3RDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL3RDY(void)
+{
+  return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL3RDYF) == (RCC_CIFR_PLL3RDYF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if LSE Clock security system interrupt occurred or not
+  * @rmtoll CIFR         LSECSSF          LL_RCC_IsActiveFlag_LSECSS
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void)
+{
+  return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == (RCC_CIFR_LSECSSF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if HSE Clock security system interrupt occurred or not
+  * @rmtoll CIFR         HSECSSF          LL_RCC_IsActiveFlag_HSECSS
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
+{
+  return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSECSSF) == (RCC_CIFR_HSECSSF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC flag Low Power D1 reset is set or not.
+  * @rmtoll RSR          LPWRRSTF       LL_RCC_IsActiveFlag_LPWRRST (*)\n
+  *         RSR          LPWR1RSTF      LL_RCC_IsActiveFlag_LPWRRST (**)
+  *
+  * (*) Only available for single core devices
+  * (**) Only available for Dual core devices
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
+{
+#if defined(DUAL_CORE)
+  return ((READ_BIT(RCC->RSR, RCC_RSR_LPWR1RSTF) == (RCC_RSR_LPWR1RSTF))?1UL:0UL);
+#else
+  return ((READ_BIT(RCC->RSR, RCC_RSR_LPWRRSTF) == (RCC_RSR_LPWRRSTF))?1UL:0UL);
+#endif /*DUAL_CORE*/
+}
+
+#if defined(DUAL_CORE)
+/**
+  * @brief  Check if RCC flag Low Power D2 reset is set or not.
+  * @rmtoll RSR          LPWR2RSTF      LL_RCC_IsActiveFlag_LPWR2RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWR2RST(void)
+{
+  return ((READ_BIT(RCC->RSR, RCC_RSR_LPWR2RSTF) == (RCC_RSR_LPWR2RSTF))?1UL:0UL);
+}
+#endif  /*DUAL_CORE*/
+
+/**
+  * @brief  Check if RCC flag Window Watchdog 1 reset is set or not.
+  * @rmtoll RSR          WWDG1RSTF      LL_RCC_IsActiveFlag_WWDG1RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDG1RST(void)
+{
+  return ((READ_BIT(RCC->RSR, RCC_RSR_WWDG1RSTF) == (RCC_RSR_WWDG1RSTF))?1UL:0UL);
+}
+
+#if defined(DUAL_CORE)
+/**
+  * @brief  Check if RCC flag Window Watchdog 2 reset is set or not.
+  * @rmtoll RSR          WWDG2RSTF      LL_RCC_IsActiveFlag_WWDG2RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDG2RST(void)
+{
+  return ((READ_BIT(RCC->RSR, RCC_RSR_WWDG2RSTF) == (RCC_RSR_WWDG2RSTF))?1UL:0UL);
+}
+#endif  /*DUAL_CORE*/
+
+/**
+  * @brief  Check if RCC flag Independent Watchdog 1 reset is set or not.
+  * @rmtoll RSR          IWDG1RSTF      LL_RCC_IsActiveFlag_IWDG1RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDG1RST(void)
+{
+  return ((READ_BIT(RCC->RSR, RCC_RSR_IWDG1RSTF) == (RCC_RSR_IWDG1RSTF))?1UL:0UL);
+}
+
+#if defined(DUAL_CORE)
+/**
+  * @brief  Check if RCC flag Independent Watchdog 2 reset is set or not.
+  * @rmtoll RSR          IWDG2RSTF      LL_RCC_IsActiveFlag_IWDG2RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDG2RST(void)
+{
+  return ((READ_BIT(RCC->RSR, RCC_RSR_IWDG2RSTF) == (RCC_RSR_IWDG2RSTF))?1UL:0UL);
+}
+#endif  /*DUAL_CORE*/
+
+/**
+  * @brief  Check if RCC flag Software reset is set or not.
+  * @rmtoll RSR          SFTRSTF        LL_RCC_IsActiveFlag_SFTRST (*)\n
+  *         RSR          SFT1RSTF       LL_RCC_IsActiveFlag_SFTRST (**)
+  *
+  * (*) Only available for single core devices
+  * (**) Only available for Dual core devices
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
+{
+#if defined(DUAL_CORE)
+  return ((READ_BIT(RCC->RSR, RCC_RSR_SFT1RSTF) == (RCC_RSR_SFT1RSTF))?1UL:0UL);
+#else
+  return ((READ_BIT(RCC->RSR, RCC_RSR_SFTRSTF) == (RCC_RSR_SFTRSTF))?1UL:0UL);
+#endif  /*DUAL_CORE*/
+}
+
+#if defined(DUAL_CORE)
+/**
+  * @brief  Check if RCC flag Software reset is set or not.
+  * @rmtoll RSR          SFT2RSTF       LL_RCC_IsActiveFlag_SFT2RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFT2RST(void)
+{
+  return ((READ_BIT(RCC->RSR, RCC_RSR_SFT2RSTF) == (RCC_RSR_SFT2RSTF))?1UL:0UL);
+}
+#endif  /*DUAL_CORE*/
+
+/**
+  * @brief  Check if RCC flag POR/PDR reset is set or not.
+  * @rmtoll RSR          PORRSTF       LL_RCC_IsActiveFlag_PORRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)
+{
+  return ((READ_BIT(RCC->RSR, RCC_RSR_PORRSTF) == (RCC_RSR_PORRSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC flag Pin reset is set or not.
+  * @rmtoll RSR          PINRSTF       LL_RCC_IsActiveFlag_PINRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
+{
+  return ((READ_BIT(RCC->RSR, RCC_RSR_PINRSTF) == (RCC_RSR_PINRSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC flag BOR reset is set or not.
+  * @rmtoll RSR          BORRSTF       LL_RCC_IsActiveFlag_BORRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)
+{
+  return ((READ_BIT(RCC->RSR, RCC_RSR_BORRSTF) == (RCC_RSR_BORRSTF))?1UL:0UL);
+}
+
+#if defined(RCC_RSR_D1RSTF)
+/**
+  * @brief  Check if RCC flag D1 reset is set or not.
+  * @rmtoll RSR          D1RSTF       LL_RCC_IsActiveFlag_D1RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_D1RST(void)
+{
+  return ((READ_BIT(RCC->RSR, RCC_RSR_D1RSTF) == (RCC_RSR_D1RSTF))?1UL:0UL);
+}
+#endif /* RCC_RSR_D1RSTF */
+
+#if defined(RCC_RSR_CDRSTF)
+/**
+  * @brief  Check if RCC flag CD reset is set or not.
+  * @rmtoll RSR          CDRSTF       LL_RCC_IsActiveFlag_CDRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CDRST(void)
+{
+  return ((READ_BIT(RCC->RSR, RCC_RSR_CDRSTF) == (RCC_RSR_CDRSTF))?1UL:0UL);
+}
+#endif /* RCC_RSR_CDRSTF */
+
+#if defined(RCC_RSR_D2RSTF)
+/**
+  * @brief  Check if RCC flag D2 reset is set or not.
+  * @rmtoll RSR          D2RSTF       LL_RCC_IsActiveFlag_D2RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_D2RST(void)
+{
+  return ((READ_BIT(RCC->RSR, RCC_RSR_D2RSTF) == (RCC_RSR_D2RSTF))?1UL:0UL);
+}
+#endif /* RCC_RSR_D2RSTF */
+
+#if defined(RCC_RSR_C1RSTF) || defined(RCC_RSR_CPURSTF)
+/**
+  * @brief  Check if RCC flag CPU reset is set or not.
+  * @rmtoll RSR          CPURSTF       LL_RCC_IsActiveFlag_CPURST (*)\n
+  *         RSR          C1RSTF        LL_RCC_IsActiveFlag_CPURST (**)
+  *
+  * (*) Only available for single core devices
+  * (**) Only available for Dual core devices
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CPURST(void)
+{
+#if defined(DUAL_CORE)
+  return ((READ_BIT(RCC->RSR, RCC_RSR_C1RSTF) == (RCC_RSR_C1RSTF))?1UL:0UL);
+#else
+  return ((READ_BIT(RCC->RSR, RCC_RSR_CPURSTF) == (RCC_RSR_CPURSTF))?1UL:0UL);
+#endif/*DUAL_CORE*/
+}
+#endif /* defined(RCC_RSR_C1RSTF) || defined(RCC_RSR_CPURSTF) */
+
+#if defined(DUAL_CORE)
+/**
+  * @brief  Check if RCC flag CPU2 reset is set or not.
+  * @rmtoll RSR          C2RSTF       LL_RCC_IsActiveFlag_CPU2RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CPU2RST(void)
+{
+  return ((READ_BIT(RCC->RSR, RCC_RSR_C2RSTF) == (RCC_RSR_C2RSTF))?1UL:0UL);
+}
+#endif  /*DUAL_CORE*/
+
+/**
+  * @brief  Set RMVF bit to clear all reset flags.
+  * @rmtoll RSR          RMVF          LL_RCC_ClearResetFlags
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearResetFlags(void)
+{
+  SET_BIT(RCC->RSR, RCC_RSR_RMVF);
+}
+
+#if defined(DUAL_CORE)
+/**
+  * @brief  Check if RCC_C1 flag Low Power D1 reset is set or not.
+  * @rmtoll RSR          LPWR1RSTF      LL_C1_RCC_IsActiveFlag_LPWRRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_LPWRRST(void)
+{
+  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_LPWR1RSTF) == (RCC_RSR_LPWR1RSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C1 flag Low Power D2 reset is set or not.
+  * @rmtoll RSR          LPWR2RSTF      LL_C1_RCC_IsActiveFlag_LPWR2RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_LPWR2RST(void)
+{
+  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_LPWR2RSTF) == (RCC_RSR_LPWR2RSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C1 flag Window Watchdog 1 reset is set or not.
+  * @rmtoll RSR          WWDG1RSTF      LL_C1_RCC_IsActiveFlag_WWDG1RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_WWDG1RST(void)
+{
+  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_WWDG1RSTF) == (RCC_RSR_WWDG1RSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C1 flag Window Watchdog 2 reset is set or not.
+  * @rmtoll RSR          WWDG2RSTF      LL_C1_RCC_IsActiveFlag_WWDG2RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_WWDG2RST(void)
+{
+  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_WWDG2RSTF) == (RCC_RSR_WWDG2RSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C1 flag Independent Watchdog 1 reset is set or not.
+  * @rmtoll RSR          IWDG1RSTF      LL_C1_RCC_IsActiveFlag_IWDG1RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_IWDG1RST(void)
+{
+  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_IWDG1RSTF) == (RCC_RSR_IWDG1RSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C1 flag Independent Watchdog 2 reset is set or not.
+  * @rmtoll RSR          IWDG2RSTF      LL_C1_RCC_IsActiveFlag_IWDG2RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_IWDG2RST(void)
+{
+  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_IWDG2RSTF) == (RCC_RSR_IWDG2RSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C1 flag Software reset is set or not.
+  * @rmtoll RSR          SFT1RSTF       LL_C1_RCC_IsActiveFlag_SFTRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_SFTRST(void)
+{
+  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_SFT1RSTF) == (RCC_RSR_SFT1RSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C1 flag Software reset is set or not.
+  * @rmtoll RSR          SFT2RSTF       LL_C1_RCC_IsActiveFlag_SFT2RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_SFT2RST(void)
+{
+  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_SFT2RSTF) == (RCC_RSR_SFT2RSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C1 flag POR/PDR reset is set or not.
+  * @rmtoll RSR          PORRSTF       LL_C1_RCC_IsActiveFlag_PORRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_PORRST(void)
+{
+  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_PORRSTF) == (RCC_RSR_PORRSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C1 flag Pin reset is set or not.
+  * @rmtoll RSR          PINRSTF       LL_C1_RCC_IsActiveFlag_PINRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_PINRST(void)
+{
+  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_PINRSTF) == (RCC_RSR_PINRSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C1 flag BOR reset is set or not.
+  * @rmtoll RSR          BORRSTF       LL_C1_RCC_IsActiveFlag_BORRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_BORRST(void)
+{
+  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_BORRSTF) == (RCC_RSR_BORRSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C1 flag D1 reset is set or not.
+  * @rmtoll RSR          D1RSTF       LL_C1_RCC_IsActiveFlag_D1RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_D1RST(void)
+{
+  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_D1RSTF) == (RCC_RSR_D1RSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C1 flag D2 reset is set or not.
+  * @rmtoll RSR          D2RSTF       LL_C1_RCC_IsActiveFlag_D2RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_D2RST(void)
+{
+  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_D2RSTF) == (RCC_RSR_D2RSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C1 flag CPU reset is set or not.
+  * @rmtoll RSR          C1RSTF       LL_C1_RCC_IsActiveFlag_CPURST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_CPURST(void)
+{
+  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_C1RSTF) == (RCC_RSR_C1RSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C1 flag CPU2 reset is set or not.
+  * @rmtoll RSR          C2RSTF       LL_C1_RCC_IsActiveFlag_CPU2RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_CPU2RST(void)
+{
+  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_C2RSTF) == (RCC_RSR_C2RSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Set RMVF bit to clear the reset flags.
+  * @rmtoll RSR          RMVF          LL_C1_RCC_ClearResetFlags
+  * @retval None
+  */
+__STATIC_INLINE void LL_C1_RCC_ClearResetFlags(void)
+{
+  SET_BIT(RCC_C1->RSR, RCC_RSR_RMVF);
+}
+
+/**
+  * @brief  Check if RCC_C2 flag Low Power D1 reset is set or not.
+  * @rmtoll RSR          LPWR1RSTF      LL_C2_RCC_IsActiveFlag_LPWRRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_LPWRRST(void)
+{
+  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_LPWR1RSTF) == (RCC_RSR_LPWR1RSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C2 flag Low Power D2 reset is set or not.
+  * @rmtoll RSR          LPWR2RSTF      LL_C2_RCC_IsActiveFlag_LPWR2RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_LPWR2RST(void)
+{
+  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_LPWR2RSTF) == (RCC_RSR_LPWR2RSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C2 flag Window Watchdog 1 reset is set or not.
+  * @rmtoll RSR          WWDG1RSTF      LL_C2_RCC_IsActiveFlag_WWDG1RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_WWDG1RST(void)
+{
+  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_WWDG1RSTF) == (RCC_RSR_WWDG1RSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C2 flag Window Watchdog 2 reset is set or not.
+  * @rmtoll RSR          WWDG2RSTF      LL_C2_RCC_IsActiveFlag_WWDG2RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_WWDG2RST(void)
+{
+  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_WWDG2RSTF) == (RCC_RSR_WWDG2RSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C2 flag Independent Watchdog 1 reset is set or not.
+  * @rmtoll RSR          IWDG1RSTF      LL_C2_RCC_IsActiveFlag_IWDG1RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_IWDG1RST(void)
+{
+  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_IWDG1RSTF) == (RCC_RSR_IWDG1RSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C2 flag Independent Watchdog 2 reset is set or not.
+  * @rmtoll RSR          IWDG2RSTF      LL_C2_RCC_IsActiveFlag_IWDG2RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_IWDG2RST(void)
+{
+  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_IWDG2RSTF) == (RCC_RSR_IWDG2RSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C2 flag Software reset is set or not.
+  * @rmtoll RSR          SFT1RSTF       LL_C2_RCC_IsActiveFlag_SFTRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_SFTRST(void)
+{
+  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_SFT1RSTF) == (RCC_RSR_SFT1RSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C2 flag Software reset is set or not.
+  * @rmtoll RSR          SFT2RSTF       LL_C2_RCC_IsActiveFlag_SFT2RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_SFT2RST(void)
+{
+  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_SFT2RSTF) == (RCC_RSR_SFT2RSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C2 flag POR/PDR reset is set or not.
+  * @rmtoll RSR          PORRSTF       LL_C2_RCC_IsActiveFlag_PORRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_PORRST(void)
+{
+  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_PORRSTF) == (RCC_RSR_PORRSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C2 flag Pin reset is set or not.
+  * @rmtoll RSR          PINRSTF       LL_C2_RCC_IsActiveFlag_PINRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_PINRST(void)
+{
+  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_PINRSTF) == (RCC_RSR_PINRSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C2 flag BOR reset is set or not.
+  * @rmtoll RSR          BORRSTF       LL_C2_RCC_IsActiveFlag_BORRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_BORRST(void)
+{
+  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_BORRSTF) == (RCC_RSR_BORRSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C2 flag D1 reset is set or not.
+  * @rmtoll RSR          D1RSTF       LL_C2_RCC_IsActiveFlag_D1RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_D1RST(void)
+{
+  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_D1RSTF) == (RCC_RSR_D1RSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C2 flag D2 reset is set or not.
+  * @rmtoll RSR          D2RSTF       LL_C2_RCC_IsActiveFlag_D2RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_D2RST(void)
+{
+  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_D2RSTF) == (RCC_RSR_D2RSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C2 flag CPU reset is set or not.
+  * @rmtoll RSR          C1RSTF       LL_C2_RCC_IsActiveFlag_CPURST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_CPURST(void)
+{
+  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_C1RSTF) == (RCC_RSR_C1RSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C2 flag CPU2 reset is set or not.
+  * @rmtoll RSR          C2RSTF       LL_C2_RCC_IsActiveFlag_CPU2RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_CPU2RST(void)
+{
+  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_C2RSTF) == (RCC_RSR_C2RSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Set RMVF bit to clear the reset flags.
+  * @rmtoll RSR          RMVF          LL_C2_RCC_ClearResetFlags
+  * @retval None
+  */
+__STATIC_INLINE void LL_C2_RCC_ClearResetFlags(void)
+{
+  SET_BIT(RCC_C2->RSR, RCC_RSR_RMVF);
+}
+#endif /*DUAL_CORE*/
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_IT_Management IT Management
+  * @{
+  */
+
+/**
+  * @brief  Enable LSI ready interrupt
+  * @rmtoll CIER         LSIRDYIE      LL_RCC_EnableIT_LSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
+{
+  SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
+}
+
+/**
+  * @brief  Enable LSE ready interrupt
+  * @rmtoll CIER         LSERDYIE      LL_RCC_EnableIT_LSERDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
+{
+  SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
+}
+
+/**
+  * @brief  Enable HSI ready interrupt
+  * @rmtoll CIER         HSIRDYIE      LL_RCC_EnableIT_HSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
+{
+  SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
+}
+
+/**
+  * @brief  Enable HSE ready interrupt
+  * @rmtoll CIER         HSERDYIE      LL_RCC_EnableIT_HSERDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
+{
+  SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
+}
+
+/**
+  * @brief  Enable CSI ready interrupt
+  * @rmtoll CIER         CSIRDYIE      LL_RCC_EnableIT_CSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_CSIRDY(void)
+{
+  SET_BIT(RCC->CIER, RCC_CIER_CSIRDYIE);
+}
+
+/**
+  * @brief  Enable HSI48 ready interrupt
+  * @rmtoll CIER         HSI48RDYIE      LL_RCC_EnableIT_HSI48RDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void)
+{
+  SET_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
+}
+
+/**
+  * @brief  Enable PLL1 ready interrupt
+  * @rmtoll CIER         PLL1RDYIE      LL_RCC_EnableIT_PLL1RDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_PLL1RDY(void)
+{
+  SET_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE);
+}
+
+/**
+  * @brief  Enable PLL2 ready interrupt
+  * @rmtoll CIER         PLL2RDYIE  LL_RCC_EnableIT_PLL2RDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_PLL2RDY(void)
+{
+  SET_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE);
+}
+
+/**
+  * @brief  Enable PLL3 ready interrupt
+  * @rmtoll CIER         PLL3RDYIE  LL_RCC_EnableIT_PLL3RDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_PLL3RDY(void)
+{
+  SET_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE);
+}
+
+/**
+  * @brief  Enable LSECSS interrupt
+  * @rmtoll CIER         LSECSSIE  LL_RCC_EnableIT_LSECSS
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_LSECSS(void)
+{
+  SET_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
+}
+
+/**
+  * @brief  Disable LSI ready interrupt
+  * @rmtoll CIER         LSIRDYIE      LL_RCC_DisableIT_LSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
+{
+  CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
+}
+
+/**
+  * @brief  Disable LSE ready interrupt
+  * @rmtoll CIER         LSERDYIE      LL_RCC_DisableIT_LSERDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
+{
+  CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
+}
+
+/**
+  * @brief  Disable HSI ready interrupt
+  * @rmtoll CIER         HSIRDYIE      LL_RCC_DisableIT_HSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
+{
+  CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
+}
+
+/**
+  * @brief  Disable HSE ready interrupt
+  * @rmtoll CIER         HSERDYIE      LL_RCC_DisableIT_HSERDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
+{
+  CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
+}
+
+/**
+  * @brief  Disable CSI ready interrupt
+  * @rmtoll CIER         CSIRDYIE      LL_RCC_DisableIT_CSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_CSIRDY(void)
+{
+  CLEAR_BIT(RCC->CIER, RCC_CIER_CSIRDYIE);
+}
+
+/**
+  * @brief  Disable HSI48 ready interrupt
+  * @rmtoll CIER         HSI48RDYIE      LL_RCC_DisableIT_HSI48RDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void)
+{
+  CLEAR_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
+}
+
+/**
+  * @brief  Disable PLL1 ready interrupt
+  * @rmtoll CIER         PLL1RDYIE      LL_RCC_DisableIT_PLL1RDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_PLL1RDY(void)
+{
+  CLEAR_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE);
+}
+
+/**
+  * @brief  Disable PLL2 ready interrupt
+  * @rmtoll CIER         PLL2RDYIE  LL_RCC_DisableIT_PLL2RDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_PLL2RDY(void)
+{
+  CLEAR_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE);
+}
+
+/**
+  * @brief  Disable PLL3 ready interrupt
+  * @rmtoll CIER         PLL3RDYIE  LL_RCC_DisableIT_PLL3RDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_PLL3RDY(void)
+{
+  CLEAR_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE);
+}
+
+/**
+  * @brief  Disable LSECSS interrupt
+  * @rmtoll CIER         LSECSSIE  LL_RCC_DisableIT_LSECSS
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_LSECSS(void)
+{
+  CLEAR_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
+}
+
+/**
+  * @brief  Checks if LSI ready interrupt source is enabled or disabled.
+  * @rmtoll CIER         LSIRDYIE      LL_RCC_IsEnableIT_LSIRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_LSIRDY(void)
+{
+  return ((READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == RCC_CIER_LSIRDYIE)?1UL:0UL);
+}
+
+/**
+  * @brief  Checks if LSE ready interrupt source is enabled or disabled.
+  * @rmtoll CIER         LSERDYIE      LL_RCC_IsEnableIT_LSERDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_LSERDY(void)
+{
+  return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == RCC_CIER_LSERDYIE)?1UL:0UL);
+}
+
+/**
+  * @brief  Checks if HSI ready interrupt source is enabled or disabled.
+  * @rmtoll CIER         HSIRDYIE      LL_RCC_IsEnableIT_HSIRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_HSIRDY(void)
+{
+  return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == RCC_CIER_HSIRDYIE)?1UL:0UL);
+}
+
+/**
+  * @brief  Checks if HSE ready interrupt source is enabled or disabled.
+  * @rmtoll CIER         HSERDYIE      LL_RCC_IsEnableIT_HSERDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_HSERDY(void)
+{
+  return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == RCC_CIER_HSERDYIE)?1UL:0UL);
+}
+
+/**
+  * @brief  Checks if CSI ready interrupt source is enabled or disabled.
+  * @rmtoll CIER         CSIRDYIE      LL_RCC_IsEnableIT_CSIRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_CSIRDY(void)
+{
+  return ((READ_BIT(RCC->CIER, RCC_CIER_CSIRDYIE) == RCC_CIER_CSIRDYIE)?1UL:0UL);
+}
+
+/**
+  * @brief  Checks if HSI48 ready interrupt source is enabled or disabled.
+  * @rmtoll CIER         HSI48RDYIE      LL_RCC_IsEnableIT_HSI48RDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_HSI48RDY(void)
+{
+  return ((READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == RCC_CIER_HSI48RDYIE)?1UL:0UL);
+}
+
+/**
+  * @brief  Checks if PLL1 ready interrupt source is enabled or disabled.
+  * @rmtoll CIER         PLL1RDYIE      LL_RCC_IsEnableIT_PLL1RDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_PLL1RDY(void)
+{
+  return ((READ_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE) == RCC_CIER_PLL1RDYIE)?1UL:0UL);
+}
+
+/**
+  * @brief  Checks if PLL2 ready interrupt source is enabled or disabled.
+  * @rmtoll CIER         PLL2RDYIE  LL_RCC_IsEnableIT_PLL2RDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_PLL2RDY(void)
+{
+  return ((READ_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE) == RCC_CIER_PLL2RDYIE)?1UL:0UL);
+}
+
+/**
+  * @brief  Checks if PLL3 ready interrupt source is enabled or disabled.
+  * @rmtoll CIER         PLL3RDYIE  LL_RCC_IsEnableIT_PLL3RDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_PLL3RDY(void)
+{
+  return ((READ_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE) == RCC_CIER_PLL3RDYIE)?1UL:0UL);
+}
+
+/**
+  * @brief  Checks if LSECSS interrupt source is enabled or disabled.
+  * @rmtoll CIER         LSECSSIE  LL_RCC_IsEnableIT_LSECSS
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_LSECSS(void)
+{
+  return ((READ_BIT(RCC->CIER, RCC_CIER_LSECSSIE) == RCC_CIER_LSECSSIE)?1UL:0UL);
+}
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RCC_LL_EF_Init De-initialization function
+  * @{
+  */
+void LL_RCC_DeInit(void);
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
+  * @{
+  */
+uint32_t    LL_RCC_CalcPLLClockFreq(uint32_t PLLInputFreq, uint32_t M, uint32_t N, uint32_t FRACN, uint32_t PQR);
+
+void        LL_RCC_GetPLL1ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks);
+void        LL_RCC_GetPLL2ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks);
+void        LL_RCC_GetPLL3ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks);
+void        LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
+
+uint32_t    LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
+uint32_t    LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource);
+uint32_t    LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
+uint32_t    LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
+uint32_t    LL_RCC_GetSAIClockFreq(uint32_t SAIxSource);
+uint32_t    LL_RCC_GetADCClockFreq(uint32_t ADCxSource);
+uint32_t    LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource);
+uint32_t    LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);
+uint32_t    LL_RCC_GetCECClockFreq(uint32_t CECxSource);
+uint32_t    LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
+uint32_t    LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource);
+#if defined(DFSDM2_BASE)
+uint32_t    LL_RCC_GetDFSDM2ClockFreq(uint32_t DFSDMxSource);
+#endif /* DFSDM2_BASE */
+#if defined(DSI)
+uint32_t    LL_RCC_GetDSIClockFreq(uint32_t DSIxSource);
+#endif /* DSI */
+uint32_t    LL_RCC_GetSPDIFClockFreq(uint32_t SPDIFxSource);
+uint32_t    LL_RCC_GetSPIClockFreq(uint32_t SPIxSource);
+uint32_t    LL_RCC_GetSWPClockFreq(uint32_t SWPxSource);
+uint32_t    LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource);
+uint32_t    LL_RCC_GetFMCClockFreq(uint32_t FMCxSource);
+#if defined(QUADSPI)
+uint32_t    LL_RCC_GetQSPIClockFreq(uint32_t QSPIxSource);
+#endif /* QUADSPI */
+#if defined(OCTOSPI1) || defined(OCTOSPI2)
+uint32_t    LL_RCC_GetOSPIClockFreq(uint32_t OSPIxSource);
+#endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */
+uint32_t    LL_RCC_GetCLKPClockFreq(uint32_t CLKPxSource);
+
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+#endif /* defined(RCC) */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_LL_RCC_H */
+
diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_system.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_system.h
index e42fe8c8..1182e8ee 100644
--- a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_system.h
+++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_system.h
@@ -1,2442 +1,2442 @@
-/**
-  ******************************************************************************
-  * @file    stm32h7xx_ll_system.h
-  * @author  MCD Application Team
-  * @brief   Header file of SYSTEM LL module.
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  @verbatim
-  ==============================================================================
-                     ##### How to use this driver #####
-  ==============================================================================
-    [..]
-    The LL SYSTEM driver contains a set of generic APIs that can be
-    used by user:
-      (+) Some of the FLASH features need to be handled in the SYSTEM file.
-      (+) Access to DBGCMU registers
-      (+) Access to SYSCFG registers
-
-  @endverbatim
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_LL_SYSTEM_H
-#define __STM32H7xx_LL_SYSTEM_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx.h"
-
-/** @addtogroup STM32H7xx_LL_Driver
-  * @{
-  */
-
-#if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU)
-
-/** @defgroup SYSTEM_LL SYSTEM
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
-  * @{
-  */
-/** @defgroup SYSTEM_LL_EC_FLASH_BANK1_SECTORS SYSCFG Flash Bank1 sectors bits status
-  * @{
-  */
-#define LL_SYSCFG_FLASH_B1_SECTOR0_STATUS_BIT   0x10000U
-#define LL_SYSCFG_FLASH_B1_SECTOR1_STATUS_BIT   0x20000U
-#define LL_SYSCFG_FLASH_B1_SECTOR2_STATUS_BIT   0x40000U
-#define LL_SYSCFG_FLASH_B1_SECTOR3_STATUS_BIT   0x80000U
-#define LL_SYSCFG_FLASH_B1_SECTOR4_STATUS_BIT   0x100000U
-#define LL_SYSCFG_FLASH_B1_SECTOR5_STATUS_BIT   0x200000U
-#define LL_SYSCFG_FLASH_B1_SECTOR6_STATUS_BIT   0x400000U
-#define LL_SYSCFG_FLASH_B1_SECTOR7_STATUS_BIT   0x800000U
-/**
-  * @}
-  */
-
-/** @defgroup SYSTEM_LL_EC_FLASH_BANK2_SECTORS SYSCFG Flash Bank2 sectors bits status
-  * @{
-  */
-#define LL_SYSCFG_FLASH_B2_SECTOR0_STATUS_BIT   0x10000U
-#define LL_SYSCFG_FLASH_B2_SECTOR1_STATUS_BIT   0x20000U
-#define LL_SYSCFG_FLASH_B2_SECTOR2_STATUS_BIT   0x40000U
-#define LL_SYSCFG_FLASH_B2_SECTOR3_STATUS_BIT   0x80000U
-#define LL_SYSCFG_FLASH_B2_SECTOR4_STATUS_BIT   0x100000U
-#define LL_SYSCFG_FLASH_B2_SECTOR5_STATUS_BIT   0x200000U
-#define LL_SYSCFG_FLASH_B2_SECTOR6_STATUS_BIT   0x400000U
-#define LL_SYSCFG_FLASH_B2_SECTOR7_STATUS_BIT   0x800000U
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
-  * @{
-  */
-
-/** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
-  * @{
-  */
-#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1        SYSCFG_PMCR_I2C1_FMP       /*!< Enable Fast Mode Plus for I2C1      */
-#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2        SYSCFG_PMCR_I2C2_FMP       /*!< Enable Fast Mode Plus for I2C2      */
-#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3        SYSCFG_PMCR_I2C3_FMP       /*!< Enable Fast Mode Plus for I2C3      */
-#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C4        SYSCFG_PMCR_I2C4_FMP       /*!< Enable Fast Mode Plus for I2C4      */
-#if defined(I2C5)
-#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C5        SYSCFG_PMCR_I2C5_FMP       /*!< Enable Fast Mode Plus for I2C5      */
-#endif /*I2C5*/
-#define LL_SYSCFG_I2C_FASTMODEPLUS_PB6         SYSCFG_PMCR_I2C_PB6_FMP    /*!< Enable Fast Mode Plus on PB6        */
-#define LL_SYSCFG_I2C_FASTMODEPLUS_PB7         SYSCFG_PMCR_I2C_PB7_FMP    /*!< Enable Fast Mode Plus on PB7        */
-#define LL_SYSCFG_I2C_FASTMODEPLUS_PB8         SYSCFG_PMCR_I2C_PB8_FMP    /*!< Enable Fast Mode Plus on PB8        */
-#define LL_SYSCFG_I2C_FASTMODEPLUS_PB9         SYSCFG_PMCR_I2C_PB9_FMP    /*!< Enable Fast Mode Plus on PB9        */
-/**
-  * @}
-  */
-
-/** @defgroup SYSTEM_LL_EC_ANALOG_SWITCH Analog Switch control
-* @{
-*/
-#if defined(SYSCFG_PMCR_BOOSTEN)
-#define LL_SYSCFG_ANALOG_SWITCH_BOOSTEN           SYSCFG_PMCR_BOOSTEN               /*!< I/O analog switch voltage booster enable */
-#endif /*SYSCFG_PMCR_BOOSTEN*/
-#define LL_SYSCFG_ANALOG_SWITCH_PA0               SYSCFG_PMCR_PA0SO                 /*!< PA0 Switch Open */
-#define LL_SYSCFG_ANALOG_SWITCH_PA1               SYSCFG_PMCR_PA1SO                 /*!< PA1 Switch Open */
-#define LL_SYSCFG_ANALOG_SWITCH_PC2               SYSCFG_PMCR_PC2SO                 /*!< PC2 Switch Open */
-#define LL_SYSCFG_ANALOG_SWITCH_PC3               SYSCFG_PMCR_PC3SO                 /*!< PC3 Switch Open */
-/**
-  * @}
-  */
-
-#if defined(SYSCFG_PMCR_EPIS_SEL)
-/** @defgroup SYSTEM_LL_EC_EPIS Ethernet PHY Interface Selection
-* @{
-*/
-#define LL_SYSCFG_ETH_MII               0x00000000U                           /*!< ETH Media MII interface */
-#define LL_SYSCFG_ETH_RMII              SYSCFG_PMCR_EPIS_SEL_2                /*!< ETH Media RMII interface */
-/**
-  * @}
-  */
-#endif /* SYSCFG_PMCR_EPIS_SEL */
-
-/** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT
-  * @{
-  */
-#define LL_SYSCFG_EXTI_PORTA               0U               /*!< EXTI PORT A                        */
-#define LL_SYSCFG_EXTI_PORTB               1U               /*!< EXTI PORT B                        */
-#define LL_SYSCFG_EXTI_PORTC               2U               /*!< EXTI PORT C                        */
-#define LL_SYSCFG_EXTI_PORTD               3U               /*!< EXTI PORT D                        */
-#define LL_SYSCFG_EXTI_PORTE               4U               /*!< EXTI PORT E                        */
-#define LL_SYSCFG_EXTI_PORTF               5U               /*!< EXTI PORT F                        */
-#define LL_SYSCFG_EXTI_PORTG               6U               /*!< EXTI PORT G                        */
-#define LL_SYSCFG_EXTI_PORTH               7U               /*!< EXTI PORT H                        */
-#if defined(GPIOI)
-#define LL_SYSCFG_EXTI_PORTI               8U               /*!< EXTI PORT I                        */
-#endif /*GPIOI*/
-#define LL_SYSCFG_EXTI_PORTJ               9U               /*!< EXTI PORT J                        */
-#define LL_SYSCFG_EXTI_PORTK               10U              /*!< EXTI PORT k                        */
-/**
-  * @}
-  */
-
-/** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE
-  * @{
-  */
-#define LL_SYSCFG_EXTI_LINE0               ((0x000FUL << 16U) | 0U)  /*!< EXTI_POSITION_0  | EXTICR[0] */
-#define LL_SYSCFG_EXTI_LINE1               ((0x00F0UL << 16U) | 0U)  /*!< EXTI_POSITION_4  | EXTICR[0] */
-#define LL_SYSCFG_EXTI_LINE2               ((0x0F00UL << 16U) | 0U)  /*!< EXTI_POSITION_8  | EXTICR[0] */
-#define LL_SYSCFG_EXTI_LINE3               ((0xF000UL << 16U) | 0U)  /*!< EXTI_POSITION_12 | EXTICR[0] */
-#define LL_SYSCFG_EXTI_LINE4               ((0x000FUL << 16U) | 1U)  /*!< EXTI_POSITION_0  | EXTICR[1] */
-#define LL_SYSCFG_EXTI_LINE5               ((0x00F0UL << 16U) | 1U)  /*!< EXTI_POSITION_4  | EXTICR[1] */
-#define LL_SYSCFG_EXTI_LINE6               ((0x0F00UL << 16U) | 1U)  /*!< EXTI_POSITION_8  | EXTICR[1] */
-#define LL_SYSCFG_EXTI_LINE7               ((0xF000UL << 16U) | 1U)  /*!< EXTI_POSITION_12 | EXTICR[1] */
-#define LL_SYSCFG_EXTI_LINE8               ((0x000FUL << 16U) | 2U)  /*!< EXTI_POSITION_0  | EXTICR[2] */
-#define LL_SYSCFG_EXTI_LINE9               ((0x00F0UL << 16U) | 2U)  /*!< EXTI_POSITION_4  | EXTICR[2] */
-#define LL_SYSCFG_EXTI_LINE10              ((0x0F00UL << 16U) | 2U)  /*!< EXTI_POSITION_8  | EXTICR[2] */
-#define LL_SYSCFG_EXTI_LINE11              ((0xF000UL << 16U) | 2U)  /*!< EXTI_POSITION_12 | EXTICR[2] */
-#define LL_SYSCFG_EXTI_LINE12              ((0x000FUL << 16U) | 3U)  /*!< EXTI_POSITION_0  | EXTICR[3] */
-#define LL_SYSCFG_EXTI_LINE13              ((0x00F0UL << 16U) | 3U)  /*!< EXTI_POSITION_4  | EXTICR[3] */
-#define LL_SYSCFG_EXTI_LINE14              ((0x0F00UL << 16U) | 3U)  /*!< EXTI_POSITION_8  | EXTICR[3] */
-#define LL_SYSCFG_EXTI_LINE15              ((0xF000UL << 16U) | 3U)  /*!< EXTI_POSITION_12 | EXTICR[3] */
-/**
-  * @}
-  */
-
-/** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
-  * @{
-  */
-#define LL_SYSCFG_TIMBREAK_AXISRAM_DBL_ECC SYSCFG_CFGR_AXISRAML /*!< Enables and locks the AXIRAM double ECC error signal
-                                                                     with Break Input of TIM1/8/15/16/17 and HRTIM        */
-
-#define LL_SYSCFG_TIMBREAK_ITCM_DBL_ECC    SYSCFG_CFGR_ITCML    /*!< Enables and locks the ITCM double ECC error signal
-                                                                     with Break Input of TIM1/8/15/16/17 and HRTIM        */
-
-#define LL_SYSCFG_TIMBREAK_DTCM_DBL_ECC    SYSCFG_CFGR_DTCML    /*!< Enables and locks the DTCM double ECC error signal
-                                                                     with Break Input of TIM1/8/15/16/17 and HRTIM        */
-
-#define LL_SYSCFG_TIMBREAK_SRAM1_DBL_ECC   SYSCFG_CFGR_SRAM1L   /*!< Enables and locks the SRAM1 double ECC error signal
-                                                                     with Break Input of TIM1/8/15/16/17 and HRTIM        */
-
-#define LL_SYSCFG_TIMBREAK_SRAM2_DBL_ECC   SYSCFG_CFGR_SRAM2L   /*!< Enables and locks the SRAM2 double ECC error signal
-                                                                     with Break Input of TIM1/8/15/16/17 and HRTIM        */
-
-#if defined(SYSCFG_CFGR_SRAM3L)
-#define LL_SYSCFG_TIMBREAK_SRAM3_DBL_ECC   SYSCFG_CFGR_SRAM3L   /*!< Enables and locks the SRAM3 double ECC error signal
-                                                                     with Break Input of TIM1/8/15/16/17 and HRTIM        */
-#endif /*SYSCFG_CFGR_SRAM3L*/
-
-#define LL_SYSCFG_TIMBREAK_SRAM4_DBL_ECC   SYSCFG_CFGR_SRAM4L   /*!< Enables and locks the SRAM4 double ECC error signal
-                                                                     with Break Input of TIM1/8/15/16/17 and HRTIM        */
-
-#define LL_SYSCFG_TIMBREAK_BKRAM_DBL_ECC   SYSCFG_CFGR_BKRAML   /*!< Enables and locks the BKRAM double ECC error signal
-                                                                     with Break Input of TIM1/8/15/16/17 and HRTIM        */
-
-#define LL_SYSCFG_TIMBREAK_CM7_LOCKUP      SYSCFG_CFGR_CM7L     /*!< Enables and locks the Cortex-M7 LOCKUP signal
-                                                                     with Break Input of TIM1/8/15/16/17 and HRTIM        */
-
-#define LL_SYSCFG_TIMBREAK_FLASH_DBL_ECC   SYSCFG_CFGR_FLASHL   /*!< Enables and locks the FLASH double ECC error signal
-                                                                     with Break Input of TIM1/8/15/16/17 and HRTIM        */
-
-#define LL_SYSCFG_TIMBREAK_PVD             SYSCFG_CFGR_PVDL     /*!< Enables and locks the PVD connection
-                                                                     with TIM1/8/15/16/17 and HRTIM Break Input
-                                                                     and also the PVDE and PLS bits of the Power Control Interface */
-#if defined(DUAL_CORE)
-#define LL_SYSCFG_TIMBREAK_CM4_LOCKUP      SYSCFG_CFGR_CM4L     /*!< Enables and locks the Cortex-M4 LOCKUP signal
-                                                                     with Break Input of TIM1/8/15/16/17 and HRTIM        */
-#endif /* DUAL_CORE */
-/**
-  * @}
-  */
-
-/** @defgroup SYSTEM_LL_EC_CS SYSCFG I/O compensation cell Code selection
-  * @{
-  */
-#define LL_SYSCFG_CELL_CODE               0U
-#define LL_SYSCFG_REGISTER_CODE           SYSCFG_CCCSR_CS
-/**
-  * @}
-  */
-
-/** @defgroup SYSTEM_LL_IWDG1_CONTROL_MODES SYSCFG IWDG1 control modes
-  * @{
-  */
-#define LL_SYSCFG_IWDG1_SW_CONTROL_MODE   0U
-#define LL_SYSCFG_IWDG1_HW_CONTROL_MODE   SYSCFG_UR11_IWDG1M
-/**
-  * @}
-  */
-
-#if defined (DUAL_CORE)
-/** @defgroup SYSTEM_LL_IWDG2_CONTROL_MODES SYSCFG IWDG2 control modes
-  * @{
-  */
-#define LL_SYSCFG_IWDG2_SW_CONTROL_MODE   0U
-#define LL_SYSCFG_IWDG2_HW_CONTROL_MODE   SYSCFG_UR12_IWDG2M
-/**
-  * @}
-  */
-#endif /* DUAL_CORE */
-
-/** @defgroup SYSTEM_LL_DTCM_RAM_SIZE SYSCFG DTCM RAM size configuration
-  * @{
-  */
-#define LL_SYSCFG_DTCM_RAM_SIZE_2KB     0U
-#define LL_SYSCFG_DTCM_RAM_SIZE_4KB     1U
-#define LL_SYSCFG_DTCM_RAM_SIZE_8KB     2U
-#define LL_SYSCFG_DTCM_RAM_SIZE_16KB    3U
-/**
-  * @}
-  */
-#ifdef SYSCFG_UR17_TCM_AXI_CFG
-/** @defgroup SYSTEM_LL_PACKAGE SYSCFG device package
-  * @{
-  */
-#define LL_SYSCFG_ITCM_AXI_64KB_320KB     0U
-#define LL_SYSCFG_ITCM_AXI_128KB_256KB    1U
-#define LL_SYSCFG_ITCM_AXI_192KB_192KB    2U
-#define LL_SYSCFG_ITCM_AXI_256KB_128KB    3U
-/**
-  * @}
-  */
-#endif /* #ifdef SYSCFG_UR17_TCM_AXI_CFG */
-#if defined(SYSCFG_PKGR_PKG)
-/** @defgroup SYSTEM_LL_PACKAGE SYSCFG device package
-  * @{
-  */
-#if (STM32H7_DEV_ID == 0x450UL)
-#define LL_SYSCFG_LQFP100_PACKAGE             0U
-#define LL_SYSCFG_TQFP144_PACKAGE             2U
-#define LL_SYSCFG_TQFP176_UFBGA176_PACKAGE    5U
-#define LL_SYSCFG_LQFP208_TFBGA240_PACKAGE    8U
-#elif (STM32H7_DEV_ID == 0x483UL)
-#define LL_SYSCFG_VFQFPN68_INDUS_PACKAGE       0U
-#define LL_SYSCFG_TFBGA100_LQFP100_PACKAGE    1U
-#define LL_SYSCFG_LQFP100_INDUS_PACKAGE        2U
-#define LL_SYSCFG_TFBGA100_INDUS_PACKAGE       3U
-#define LL_SYSCFG_WLCSP115_INDUS_PACKAGE       4U
-#define LL_SYSCFG_LQFP144_PACKAGE             5U
-#define LL_SYSCFG_UFBGA144_PACKAGE            6U
-#define LL_SYSCFG_LQFP144_INDUS_PACKAGE        7U
-#define LL_SYSCFG_UFBGA169_INDUS_PACKAGE       8U
-#define LL_SYSCFG_UFBGA176PLUS25_INDUS_PACKAGE 9U
-#define LL_SYSCFG_LQFP176_INDUS_PACKAGE        10U
-#endif /* STM32H7_DEV_ID == 0x450UL */
-/**
-  * @}
-  */
-#endif /* SYSCFG_PKGR_PKG */
-  
-/** @defgroup SYSTEM_LL_SYSCFG_BOR SYSCFG Brownout Reset Threshold Level
-  * @{
-  */
-#define LL_SYSCFG_BOR_OFF_RESET_LEVEL      0x00000000U
-#define LL_SYSCFG_BOR_LOW_RESET_LEVEL      SYSCFG_UR2_BORH_0
-#define LL_SYSCFG_BOR_MEDIUM_RESET_LEVEL   SYSCFG_UR2_BORH_1
-#define LL_SYSCFG_BOR_HIGH_RESET_LEVEL     SYSCFG_UR2_BORH
-
-/**
-  * @}
-  */
-
-/** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
-  * @{
-  */
-#define LL_DBGMCU_TRACE_NONE               0x00000000U                                     /*!< TRACE pins not assigned (default state) */
-#define LL_DBGMCU_TRACE_ASYNCH             DBGMCU_CR_TRACE_IOEN                            /*!< TRACE pin assignment for Asynchronous Mode */
-#define LL_DBGMCU_TRACE_SYNCH_SIZE1        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */
-#define LL_DBGMCU_TRACE_SYNCH_SIZE2        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */
-#define LL_DBGMCU_TRACE_SYNCH_SIZE4        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)   /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */
-/**
-  * @}
-  */
-
-/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
-  * @{
-  */
-#define LL_DBGMCU_APB1_GRP1_TIM2_STOP      DBGMCU_APB1LFZ1_DBG_TIM2     /*!< TIM2 counter stopped when core is halted */
-#define LL_DBGMCU_APB1_GRP1_TIM3_STOP      DBGMCU_APB1LFZ1_DBG_TIM3     /*!< TIM3 counter stopped when core is halted */
-#define LL_DBGMCU_APB1_GRP1_TIM4_STOP      DBGMCU_APB1LFZ1_DBG_TIM4     /*!< TIM4 counter stopped when core is halted */
-#define LL_DBGMCU_APB1_GRP1_TIM5_STOP      DBGMCU_APB1LFZ1_DBG_TIM5     /*!< TIM5 counter stopped when core is halted */
-#define LL_DBGMCU_APB1_GRP1_TIM6_STOP      DBGMCU_APB1LFZ1_DBG_TIM6     /*!< TIM6 counter stopped when core is halted */
-#define LL_DBGMCU_APB1_GRP1_TIM7_STOP      DBGMCU_APB1LFZ1_DBG_TIM7     /*!< TIM7 counter stopped when core is halted */
-#define LL_DBGMCU_APB1_GRP1_TIM12_STOP     DBGMCU_APB1LFZ1_DBG_TIM12    /*!< TIM12 counter stopped when core is halted */
-#define LL_DBGMCU_APB1_GRP1_TIM13_STOP     DBGMCU_APB1LFZ1_DBG_TIM13    /*!< TIM13 counter stopped when core is halted */
-#define LL_DBGMCU_APB1_GRP1_TIM14_STOP     DBGMCU_APB1LFZ1_DBG_TIM14    /*!< TIM14 counter stopped when core is halted */
-#define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP    DBGMCU_APB1LFZ1_DBG_LPTIM1   /*!< LPTIM1 counter stopped when core is halted */
-#define LL_DBGMCU_APB1_GRP1_I2C1_STOP      DBGMCU_APB1LFZ1_DBG_I2C1     /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
-#define LL_DBGMCU_APB1_GRP1_I2C2_STOP      DBGMCU_APB1LFZ1_DBG_I2C2     /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
-#define LL_DBGMCU_APB1_GRP1_I2C3_STOP      DBGMCU_APB1LFZ1_DBG_I2C3     /*!< I2C3 SMBUS timeout mode stopped when Core is halted */
-#if defined(I2C5)
-#define LL_DBGMCU_APB1_GRP1_I2C5_STOP      DBGMCU_APB1LFZ1_DBG_I2C5     /*!< I2C5 SMBUS timeout mode stopped when Core is halted */
-#endif /*I2C5*/
-/**
-  * @}
-  */
-
-
-/** @defgroup SYSTEM_LL_EC_APB1_GRP2_STOP_IP DBGMCU APB1 GRP2 STOP IP
-  * @{
-  */
-#if defined(DBGMCU_APB1HFZ1_DBG_FDCAN)
-#define LL_DBGMCU_APB1_GRP2_FDCAN_STOP    DBGMCU_APB1HFZ1_DBG_FDCAN    /*!< FDCAN is frozen while the core is in debug mode */
-#endif /*DBGMCU_APB1HFZ1_DBG_FDCAN*/
-#if defined(TIM23)
-#define LL_DBGMCU_APB1_GRP2_TIM23_STOP    DBGMCU_APB1HFZ1_DBG_TIM23    /*!< TIM23 is frozen while the core is in debug mode */
-#endif /*TIM23*/
-#if defined(TIM24)
-#define LL_DBGMCU_APB1_GRP2_TIM24_STOP    DBGMCU_APB1HFZ1_DBG_TIM24    /*!< TIM24 is frozen while the core is in debug mode */
-#endif /*TIM24*/
-/**
-  * @}
-  */
-
-/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
-  * @{
-  */
-#define LL_DBGMCU_APB2_GRP1_TIM1_STOP      DBGMCU_APB2FZ1_DBG_TIM1    /*!< TIM1 counter stopped when core is halted */
-#define LL_DBGMCU_APB2_GRP1_TIM8_STOP      DBGMCU_APB2FZ1_DBG_TIM8    /*!< TIM8 counter stopped when core is halted */
-#define LL_DBGMCU_APB2_GRP1_TIM15_STOP     DBGMCU_APB2FZ1_DBG_TIM15   /*!< TIM15 counter stopped when core is halted */
-#define LL_DBGMCU_APB2_GRP1_TIM16_STOP     DBGMCU_APB2FZ1_DBG_TIM16   /*!< TIM16 counter stopped when core is halted */
-#define LL_DBGMCU_APB2_GRP1_TIM17_STOP     DBGMCU_APB2FZ1_DBG_TIM17   /*!< TIM17 counter stopped when core is halted */
-#if defined(HRTIM1)
-#define LL_DBGMCU_APB2_GRP1_HRTIM_STOP     DBGMCU_APB2FZ1_DBG_HRTIM   /*!< HRTIM counter stopped when core is halted */
-#endif /*HRTIM1*/
-/**
-  * @}
-  */
-
-/** @defgroup SYSTEM_LL_EC_APB3_GRP1_STOP_IP DBGMCU APB3 GRP1 STOP IP
-  * @{
-  */
-#define LL_DBGMCU_APB3_GRP1_WWDG1_STOP      DBGMCU_APB3FZ1_DBG_WWDG1   /*!< WWDG1 is frozen while the core is in debug mode */
-/**
-  * @}
-  */
-
-/** @defgroup SYSTEM_LL_EC_APB4_GRP1_STOP_IP DBGMCU APB4 GRP1 STOP IP
-  * @{
-  */
-#define LL_DBGMCU_APB4_GRP1_I2C4_STOP       DBGMCU_APB4FZ1_DBG_I2C4     /*!< I2C4 is frozen while the core is in debug mode */
-#define LL_DBGMCU_APB4_GRP1_LPTIM2_STOP     DBGMCU_APB4FZ1_DBG_LPTIM2   /*!< LPTIM2 is frozen while the core is in debug mode */
-#define LL_DBGMCU_APB4_GRP1_LPTIM3_STOP     DBGMCU_APB4FZ1_DBG_LPTIM3   /*!< LPTIM3 is frozen while the core is in debug mode */
-#define LL_DBGMCU_APB4_GRP1_LPTIM4_STOP     DBGMCU_APB4FZ1_DBG_LPTIM4   /*!< LPTIM4 is frozen while the core is in debug mode */
-#define LL_DBGMCU_APB4_GRP1_LPTIM5_STOP     DBGMCU_APB4FZ1_DBG_LPTIM5   /*!< LPTIM5 is frozen while the core is in debug mode */
-#define LL_DBGMCU_APB4_GRP1_RTC_STOP        DBGMCU_APB4FZ1_DBG_RTC      /*!< RTC is frozen while the core is in debug mode */
-#define LL_DBGMCU_APB4_GRP1_IWDG1_STOP      DBGMCU_APB4FZ1_DBG_IWDG1    /*!< IWDG1 is frozen while the core is in debug mode */
-/**
-  * @}
-  */
-
-/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
-  * @{
-  */
-#define LL_FLASH_LATENCY_0                 FLASH_ACR_LATENCY_0WS   /*!< FLASH Zero wait state */
-#define LL_FLASH_LATENCY_1                 FLASH_ACR_LATENCY_1WS   /*!< FLASH One wait state */
-#define LL_FLASH_LATENCY_2                 FLASH_ACR_LATENCY_2WS   /*!< FLASH Two wait states */
-#define LL_FLASH_LATENCY_3                 FLASH_ACR_LATENCY_3WS   /*!< FLASH Three wait states */
-#define LL_FLASH_LATENCY_4                 FLASH_ACR_LATENCY_4WS   /*!< FLASH Four wait states */
-#define LL_FLASH_LATENCY_5                 FLASH_ACR_LATENCY_5WS   /*!< FLASH five wait state */
-#define LL_FLASH_LATENCY_6                 FLASH_ACR_LATENCY_6WS   /*!< FLASH six wait state */
-#define LL_FLASH_LATENCY_7                 FLASH_ACR_LATENCY_7WS   /*!< FLASH seven wait states */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
-  * @{
-  */
-
-/** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
-  * @{
-  */
-
-#if defined(SYSCFG_PMCR_EPIS_SEL)
-/**
-  * @brief  Select Ethernet PHY interface
-  * @rmtoll PMCR    EPIS_SEL    LL_SYSCFG_SetPHYInterface
-  * @param  Interface This parameter can be one of the following values:
-  *         @arg @ref LL_SYSCFG_ETH_MII
-  *         @arg @ref LL_SYSCFG_ETH_RMII
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_SetPHYInterface(uint32_t Interface)
-{
-  MODIFY_REG(SYSCFG->PMCR, SYSCFG_PMCR_EPIS_SEL, Interface);
-}
-
-/**
-  * @brief  Get Ethernet PHY interface
-  * @rmtoll PMCR    EPIS_SEL    LL_SYSCFG_GetPHYInterface
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SYSCFG_ETH_MII
-  *         @arg @ref LL_SYSCFG_ETH_RMII
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_GetPHYInterface(void)
-{
-  return (uint32_t)(READ_BIT(SYSCFG->PMCR, SYSCFG_PMCR_EPIS_SEL));
-}
-
-#endif /* SYSCFG_PMCR_EPIS_SEL */
-/**
-  * @brief  Open an Analog Switch
-  * @rmtoll PMCR    PA0SO   LL_SYSCFG_OpenAnalogSwitch
-  * @rmtoll PMCR    PA1SO   LL_SYSCFG_OpenAnalogSwitch
-  * @rmtoll PMCR    PC2SO   LL_SYSCFG_OpenAnalogSwitch
-  * @rmtoll PMCR    PC3SO   LL_SYSCFG_OpenAnalogSwitch
-  * @param  AnalogSwitch This parameter can be one of the following values:
-  *         @arg LL_SYSCFG_ANALOG_SWITCH_PA0 : PA0 analog switch
-  *         @arg LL_SYSCFG_ANALOG_SWITCH_PA1:  PA1 analog switch
-  *         @arg LL_SYSCFG_ANALOG_SWITCH_PC2 : PC2 analog switch
-  *         @arg LL_SYSCFG_ANALOG_SWITCH_PC3:  PC3 analog switch
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_OpenAnalogSwitch(uint32_t AnalogSwitch)
-{
-  SET_BIT(SYSCFG->PMCR, AnalogSwitch);
-}
-
-/**
-  * @brief  Close an Analog Switch
-  * @rmtoll PMCR    PA0SO   LL_SYSCFG_CloseAnalogSwitch
-  * @rmtoll PMCR    PA1SO   LL_SYSCFG_CloseAnalogSwitch
-  * @rmtoll PMCR    PC2SO   LL_SYSCFG_CloseAnalogSwitch
-  * @rmtoll PMCR    PC3SO   LL_SYSCFG_CloseAnalogSwitch
-  * @param  AnalogSwitch This parameter can be one of the following values:
-  *         @arg LL_SYSCFG_ANALOG_SWITCH_PA0 : PA0 analog switch
-  *         @arg LL_SYSCFG_ANALOG_SWITCH_PA1:  PA1 analog switch
-  *         @arg LL_SYSCFG_ANALOG_SWITCH_PC2 : PC2 analog switch
-  *         @arg LL_SYSCFG_ANALOG_SWITCH_PC3:  PC3 analog switch
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_CloseAnalogSwitch(uint32_t AnalogSwitch)
-{
-  CLEAR_BIT(SYSCFG->PMCR, AnalogSwitch);
-}
-#ifdef SYSCFG_PMCR_BOOSTEN
-/**
-  * @brief  Enable the Analog booster to reduce the total harmonic distortion
-  *         of the analog switch when the supply voltage is lower than 2.7 V
-  * @rmtoll PMCR    BOOSTEN   LL_SYSCFG_EnableAnalogBooster
-  * @note   Activating the booster allows to guaranty the analog switch AC performance
-  *         when the supply voltage is below 2.7 V: in this case, the analog switch
-  *         performance is the same on the full voltage range
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_EnableAnalogBooster(void)
-{
- SET_BIT(SYSCFG->PMCR, SYSCFG_PMCR_BOOSTEN) ;
-}
-
-/**
-  * @brief  Disable the Analog booster
-  * @rmtoll PMCR    BOOSTEN   LL_SYSCFG_DisableAnalogBooster
-  * @note   Activating the booster allows to guaranty the analog switch AC performance
-  *         when the supply voltage is below 2.7 V: in this case, the analog switch
-  *         performance is the same on the full voltage range
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_DisableAnalogBooster(void)
-{
- CLEAR_BIT(SYSCFG->PMCR, SYSCFG_PMCR_BOOSTEN) ;
-}
-#endif /*SYSCFG_PMCR_BOOSTEN*/
-/**
-  * @brief  Enable the I2C fast mode plus driving capability.
-  * @rmtoll SYSCFG_PMCR   I2C_PBx_FMP   LL_SYSCFG_EnableFastModePlus\n
-  *         SYSCFG_PMCR   I2Cx_FMP      LL_SYSCFG_EnableFastModePlus
-  * @param  ConfigFastModePlus This parameter can be a combination of the following values:
-  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
-  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
-  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)
-  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)
-  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
-  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
-  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
-  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4(*)
-  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C5(*)
-  *
-  *         (*) value not defined in all devices
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
-{
-  SET_BIT(SYSCFG->PMCR, ConfigFastModePlus);
-}
-
-/**
-  * @brief  Disable the I2C fast mode plus driving capability.
-  * @rmtoll SYSCFG_PMCR    I2C_PBx_FMP   LL_SYSCFG_DisableFastModePlus\n
-  *         SYSCFG_PMCR    I2Cx_FMP      LL_SYSCFG_DisableFastModePlus
-  * @param  ConfigFastModePlus This parameter can be a combination of the following values:
-  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
-  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
-  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)
-  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)
-  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
-  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
-  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
-  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4
-  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C5 (*)
-  *
-  *         (*) value not defined in all devices
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
-{
-  CLEAR_BIT(SYSCFG->PMCR, ConfigFastModePlus);
-}
-
-/**
-  * @brief  Configure source input for the EXTI external interrupt.
-  * @rmtoll SYSCFG_EXTICR1  EXTIx         LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR2 EXTIx         LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR3 EXTIx         LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR4 EXTIx         LL_SYSCFG_SetEXTISource
-  * @param  Port This parameter can be one of the following values:
-  *         @arg @ref LL_SYSCFG_EXTI_PORTA
-  *         @arg @ref LL_SYSCFG_EXTI_PORTB
-  *         @arg @ref LL_SYSCFG_EXTI_PORTC
-  *         @arg @ref LL_SYSCFG_EXTI_PORTD
-  *         @arg @ref LL_SYSCFG_EXTI_PORTE
-  *         @arg @ref LL_SYSCFG_EXTI_PORTF
-  *         @arg @ref LL_SYSCFG_EXTI_PORTG
-  *         @arg @ref LL_SYSCFG_EXTI_PORTH
-  *         @arg @ref LL_SYSCFG_EXTI_PORTI (*)
-  *         @arg @ref LL_SYSCFG_EXTI_PORTJ
-  *         @arg @ref LL_SYSCFG_EXTI_PORTK
-  *
-  *         (*) value not defined in all devices
-  * @param  Line This parameter can be one of the following values:
-  *         @arg @ref LL_SYSCFG_EXTI_LINE0
-  *         @arg @ref LL_SYSCFG_EXTI_LINE1
-  *         @arg @ref LL_SYSCFG_EXTI_LINE2
-  *         @arg @ref LL_SYSCFG_EXTI_LINE3
-  *         @arg @ref LL_SYSCFG_EXTI_LINE4
-  *         @arg @ref LL_SYSCFG_EXTI_LINE5
-  *         @arg @ref LL_SYSCFG_EXTI_LINE6
-  *         @arg @ref LL_SYSCFG_EXTI_LINE7
-  *         @arg @ref LL_SYSCFG_EXTI_LINE8
-  *         @arg @ref LL_SYSCFG_EXTI_LINE9
-  *         @arg @ref LL_SYSCFG_EXTI_LINE10
-  *         @arg @ref LL_SYSCFG_EXTI_LINE11
-  *         @arg @ref LL_SYSCFG_EXTI_LINE12
-  *         @arg @ref LL_SYSCFG_EXTI_LINE13
-  *         @arg @ref LL_SYSCFG_EXTI_LINE14
-  *         @arg @ref LL_SYSCFG_EXTI_LINE15
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
-{
-  MODIFY_REG(SYSCFG->EXTICR[Line & 0x3U], (Line >> 16U), Port << ((POSITION_VAL(Line >> 16U)) & 31U));
-}
-
-/**
-  * @brief  Get the configured defined for specific EXTI Line
-  * @rmtoll SYSCFG_EXTICR1 EXTIx         LL_SYSCFG_GetEXTISource\n
-  *         SYSCFG_EXTICR2 EXTIx         LL_SYSCFG_GetEXTISource\n
-  *         SYSCFG_EXTICR3 EXTIx         LL_SYSCFG_GetEXTISource\n
-  *         SYSCFG_EXTICR4 EXTIx         LL_SYSCFG_GetEXTISource
-  * @param  Line This parameter can be one of the following values:
-  *         @arg @ref LL_SYSCFG_EXTI_LINE0
-  *         @arg @ref LL_SYSCFG_EXTI_LINE1
-  *         @arg @ref LL_SYSCFG_EXTI_LINE2
-  *         @arg @ref LL_SYSCFG_EXTI_LINE3
-  *         @arg @ref LL_SYSCFG_EXTI_LINE4
-  *         @arg @ref LL_SYSCFG_EXTI_LINE5
-  *         @arg @ref LL_SYSCFG_EXTI_LINE6
-  *         @arg @ref LL_SYSCFG_EXTI_LINE7
-  *         @arg @ref LL_SYSCFG_EXTI_LINE8
-  *         @arg @ref LL_SYSCFG_EXTI_LINE9
-  *         @arg @ref LL_SYSCFG_EXTI_LINE10
-  *         @arg @ref LL_SYSCFG_EXTI_LINE11
-  *         @arg @ref LL_SYSCFG_EXTI_LINE12
-  *         @arg @ref LL_SYSCFG_EXTI_LINE13
-  *         @arg @ref LL_SYSCFG_EXTI_LINE14
-  *         @arg @ref LL_SYSCFG_EXTI_LINE15
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SYSCFG_EXTI_PORTA
-  *         @arg @ref LL_SYSCFG_EXTI_PORTB
-  *         @arg @ref LL_SYSCFG_EXTI_PORTC
-  *         @arg @ref LL_SYSCFG_EXTI_PORTD
-  *         @arg @ref LL_SYSCFG_EXTI_PORTE
-  *         @arg @ref LL_SYSCFG_EXTI_PORTF
-  *         @arg @ref LL_SYSCFG_EXTI_PORTG
-  *         @arg @ref LL_SYSCFG_EXTI_PORTH
-  *         @arg @ref LL_SYSCFG_EXTI_PORTI (*)
-  *         @arg @ref LL_SYSCFG_EXTI_PORTJ
-  *         @arg @ref LL_SYSCFG_EXTI_PORTK
-  *         (*) value not defined in all devices
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
-{
-  return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0x3U], (Line >> 16U)) >> (POSITION_VAL(Line >> 16U) & 31U));
-}
-
-/**
-  * @brief  Set connections to TIM1/8/15/16/17 and HRTIM Break inputs
-  * @note this feature is available on STM32H7 rev.B and above
-  * @rmtoll SYSCFG_CFGR AXISRAML       LL_SYSCFG_SetTIMBreakInputs\n
-  *         SYSCFG_CFGR ITCML          LL_SYSCFG_SetTIMBreakInputs\n
-  *         SYSCFG_CFGR DTCML          LL_SYSCFG_SetTIMBreakInputs\n
-  *         SYSCFG_CFGR SRAM1L         LL_SYSCFG_SetTIMBreakInputs\n
-  *         SYSCFG_CFGR SRAM2L         LL_SYSCFG_SetTIMBreakInputs\n
-  *         SYSCFG_CFGR SRAM3L         LL_SYSCFG_SetTIMBreakInputs\n
-  *         SYSCFG_CFGR SRAM4L         LL_SYSCFG_SetTIMBreakInputs\n
-  *         SYSCFG_CFGR BKRAML         LL_SYSCFG_SetTIMBreakInputs\n
-  *         SYSCFG_CFGR CM7L           LL_SYSCFG_SetTIMBreakInputs\n
-  *         SYSCFG_CFGR FLASHL         LL_SYSCFG_SetTIMBreakInputs\n
-  *         SYSCFG_CFGR PVDL           LL_SYSCFG_SetTIMBreakInputs\n
-  *         SYSCFG_CFGR_CM4L           LL_SYSCFG_SetTIMBreakInputs
-  * @param  Break This parameter can be a combination of the following values:
-  *         @arg @ref LL_SYSCFG_TIMBREAK_AXISRAM_DBL_ECC
-  *         @arg @ref LL_SYSCFG_TIMBREAK_ITCM_DBL_ECC
-  *         @arg @ref LL_SYSCFG_TIMBREAK_DTCM_DBL_ECC
-  *         @arg @ref LL_SYSCFG_TIMBREAK_SRAM1_DBL_ECC
-  *         @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_DBL_ECC
-  *         @arg @ref LL_SYSCFG_TIMBREAK_SRAM3_DBL_ECC (*)
-  *         @arg @ref LL_SYSCFG_TIMBREAK_SRAM4_DBL_ECC
-  *         @arg @ref LL_SYSCFG_TIMBREAK_BKRAM_DBL_ECC
-  *         @arg @ref LL_SYSCFG_TIMBREAK_CM7_LOCKUP
-  *         @arg @ref LL_SYSCFG_TIMBREAK_FLASH_DBL_ECC
-  *         @arg @ref LL_SYSCFG_TIMBREAK_PVD
-  *         @arg @ref LL_SYSCFG_TIMBREAK_CM4_LOCKUP (available for dual core lines only)
-  * @retval None
-  *         (*) value not defined in all devices
-  */
-__STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
-{
-#if defined(DUAL_CORE)
-  MODIFY_REG(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML  | SYSCFG_CFGR_DTCML  | SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | \
-                           SYSCFG_CFGR_SRAM3L   | SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L   | SYSCFG_CFGR_FLASHL | \
-                           SYSCFG_CFGR_PVDL     | SYSCFG_CFGR_CM4L, Break);
-#elif defined(SYSCFG_CFGR_AXISRAML) && defined(SYSCFG_CFGR_SRAM3L)
-  MODIFY_REG(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML  | SYSCFG_CFGR_DTCML  | SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | \
-                           SYSCFG_CFGR_SRAM3L   | SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L   | SYSCFG_CFGR_FLASHL | \
-                           SYSCFG_CFGR_PVDL, Break);
-#elif defined(SYSCFG_CFGR_AXISRAML)
-  MODIFY_REG(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML  | SYSCFG_CFGR_DTCML  | SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | \
-                           SYSCFG_CFGR_SRAM4L   | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L   | SYSCFG_CFGR_FLASHL | SYSCFG_CFGR_PVDL,\
-                           Break);
-#else
-  MODIFY_REG(SYSCFG->CFGR, SYSCFG_CFGR_ITCML  | SYSCFG_CFGR_DTCML  |\
-                           SYSCFG_CFGR_CM7L   | SYSCFG_CFGR_FLASHL | \
-                           SYSCFG_CFGR_PVDL, Break);
-#endif /* DUAL_CORE */
-}
-
-/**
-  * @brief  Get connections to TIM1/8/15/16/17 and HRTIM Break inputs
-  * @note this feature is available on STM32H7 rev.B and above
-  * @rmtoll SYSCFG_CFGR AXISRAML       LL_SYSCFG_GetTIMBreakInputs\n
-  *         SYSCFG_CFGR ITCML          LL_SYSCFG_GetTIMBreakInputs\n
-  *         SYSCFG_CFGR DTCML          LL_SYSCFG_GetTIMBreakInputs\n
-  *         SYSCFG_CFGR SRAM1L         LL_SYSCFG_GetTIMBreakInputs\n
-  *         SYSCFG_CFGR SRAM2L         LL_SYSCFG_GetTIMBreakInputs\n
-  *         SYSCFG_CFGR SRAM3L         LL_SYSCFG_GetTIMBreakInputs\n
-  *         SYSCFG_CFGR SRAM4L         LL_SYSCFG_GetTIMBreakInputs\n
-  *         SYSCFG_CFGR BKRAML         LL_SYSCFG_GetTIMBreakInputs\n
-  *         SYSCFG_CFGR CM7L           LL_SYSCFG_GetTIMBreakInputs\n
-  *         SYSCFG_CFGR FLASHL         LL_SYSCFG_GetTIMBreakInputs\n
-  *         SYSCFG_CFGR PVDL           LL_SYSCFG_GetTIMBreakInputs\n
-  *         SYSCFG_CFGR_CM4L           LL_SYSCFG_GetTIMBreakInputs
-  * @retval Returned value can be can be a combination of the following values:
-  *         @arg @ref LL_SYSCFG_TIMBREAK_AXISRAM_DBL_ECC
-  *         @arg @ref LL_SYSCFG_TIMBREAK_ITCM_DBL_ECC
-  *         @arg @ref LL_SYSCFG_TIMBREAK_DTCM_DBL_ECC
-  *         @arg @ref LL_SYSCFG_TIMBREAK_SRAM1_DBL_ECC
-  *         @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_DBL_ECC
-  *         @arg @ref LL_SYSCFG_TIMBREAK_SRAM3_DBL_ECC (*)
-  *         @arg @ref LL_SYSCFG_TIMBREAK_SRAM4_DBL_ECC
-  *         @arg @ref LL_SYSCFG_TIMBREAK_BKRAM_DBL_ECC
-  *         @arg @ref LL_SYSCFG_TIMBREAK_CM7_LOCKUP
-  *         @arg @ref LL_SYSCFG_TIMBREAK_FLASH_DBL_ECC
-  *         @arg @ref LL_SYSCFG_TIMBREAK_PVD
-  *         @arg @ref LL_SYSCFG_TIMBREAK_CM4_LOCKUP (available for dual core lines only)
-  *         (*) value not defined in all devices
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
-{
-#if defined(DUAL_CORE)
-  return (uint32_t)(READ_BIT(SYSCFG->CFGR,  SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML  | SYSCFG_CFGR_DTCML  | \
-                                            SYSCFG_CFGR_SRAM1L   | SYSCFG_CFGR_SRAM2L | SYSCFG_CFGR_SRAM3L | \
-                                            SYSCFG_CFGR_SRAM4L   | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L   | \
-                                            SYSCFG_CFGR_FLASHL   | SYSCFG_CFGR_PVDL   | SYSCFG_CFGR_CM4L));
-#elif defined (SYSCFG_CFGR_AXISRAML) && defined(SYSCFG_CFGR_SRAM3L)
-  return (uint32_t)(READ_BIT(SYSCFG->CFGR,  SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML  | SYSCFG_CFGR_DTCML  | \
-                                            SYSCFG_CFGR_SRAM1L   | SYSCFG_CFGR_SRAM2L | SYSCFG_CFGR_SRAM3L | \
-                                            SYSCFG_CFGR_SRAM4L   | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L   | \
-                                            SYSCFG_CFGR_FLASHL   | SYSCFG_CFGR_PVDL ));
-#elif defined (SYSCFG_CFGR_AXISRAML)
-  return (uint32_t)(READ_BIT(SYSCFG->CFGR,  SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML  | SYSCFG_CFGR_DTCML  | \
-                                            SYSCFG_CFGR_SRAM1L   | SYSCFG_CFGR_SRAM2L | \
-                                            SYSCFG_CFGR_SRAM4L   | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L   | \
-                                            SYSCFG_CFGR_FLASHL   | SYSCFG_CFGR_PVDL ));
-#else
-  return (uint32_t)(READ_BIT(SYSCFG->CFGR,  SYSCFG_CFGR_ITCML    | SYSCFG_CFGR_DTCML  | SYSCFG_CFGR_CM7L   | \
-                                            SYSCFG_CFGR_FLASHL   | SYSCFG_CFGR_PVDL ));
-#endif /* DUAL_CORE */
-}
-
-/**
-  * @brief  Enable the Compensation Cell
-  * @rmtoll CCCSR   EN    LL_SYSCFG_EnableCompensationCell
-  * @note   The I/O compensation cell can be used only when the device supply
-  *         voltage ranges from 1.62 to 2.0 V and from 2.7 to 3.6 V.
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_EnableCompensationCell(void)
-{
-  SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN);
-}
-
-/**
-  * @brief  Disable the Compensation Cell
-  * @rmtoll CCCSR   EN    LL_SYSCFG_DisableCompensationCell
-  * @note   The I/O compensation cell can be used only when the device supply
-  *         voltage ranges from 1.62 to 2.0 V and from 2.7 to 3.6 V.
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_DisableCompensationCell(void)
-{
-  CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN);
-}
-
-/**
-  * @brief  Check if the Compensation Cell is enabled
-  * @rmtoll CCCSR   EN    LL_SYSCFG_IsEnabledCompensationCell
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledCompensationCell(void)
-{
-  return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN) == SYSCFG_CCCSR_EN) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Compensation Cell ready Flag
-  * @rmtoll CCCSR   READY   LL_SYSCFG_IsActiveFlag_CMPCR
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CMPCR(void)
-{
-  return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_READY) == (SYSCFG_CCCSR_READY)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable the I/O speed optimization when the product voltage is low.
-  * @rmtoll CCCSR   HSLV    LL_SYSCFG_EnableIOSpeedOptimize
-  * @note   This bit is active only if IO_HSLV user option bit is set. It must be used only if the
-  *         product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
-  *         might be destructive.
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimization(void)
-{
-#if defined(SYSCFG_CCCSR_HSLV)
-  SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV);
-#else
-  SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV0);
-#endif   /* SYSCFG_CCCSR_HSLV */
-}
-
-#if defined(SYSCFG_CCCSR_HSLV1)
-/**
-  * @brief  Enable the I/O speed optimization when the product voltage is low.
-  * @rmtoll CCCSR   HSLV1    LL_SYSCFG_EnableIOSpeedOptimize
-  * @note   This bit is active only if IO_HSLV user option bit is set. It must be used only if the
-  *         product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
-  *         might be destructive.
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimization1(void)
-{
-  SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV1);
-}
-
-/**
-  * @brief  Enable the I/O speed optimization when the product voltage is low.
-  * @rmtoll CCCSR   HSLV2    LL_SYSCFG_EnableIOSpeedOptimize
-  * @note   This bit is active only if IO_HSLV user option bit is set. It must be used only if the
-  *         product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
-  *         might be destructive.
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimization2(void)
-{
-  SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV2);
-}
-
-/**
-  * @brief  Enable the I/O speed optimization when the product voltage is low.
-  * @rmtoll CCCSR   HSLV3    LL_SYSCFG_EnableIOSpeedOptimize
-  * @note   This bit is active only if IO_HSLV user option bit is set. It must be used only if the
-  *         product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
-  *         might be destructive.
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimization3(void)
-{
-  SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV3);
-}
-#endif /*SYSCFG_CCCSR_HSLV1*/
-
-
-/**
-  * @brief  To Disable optimize the I/O speed when the product voltage is low.
-  * @rmtoll CCCSR   HSLV    LL_SYSCFG_DisableIOSpeedOptimize
-  * @note   This bit is active only if IO_HSLV user option bit is set. It must be used only if the
-  *         product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
-  *         might be destructive.
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimization(void)
-{
-#if defined(SYSCFG_CCCSR_HSLV)
-  CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV);
-#else
-  CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV0);
-#endif   /* SYSCFG_CCCSR_HSLV */
-}
-
-#if defined(SYSCFG_CCCSR_HSLV1)
-/**
-  * @brief  To Disable optimize the I/O speed when the product voltage is low.
-  * @rmtoll CCCSR   HSLV1    LL_SYSCFG_DisableIOSpeedOptimize
-  * @note   This bit is active only if IO_HSLV user option bit is set. It must be used only if the
-  *         product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
-  *         might be destructive.
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimization1(void)
-{
-  CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV1);
-}
-
-/**
-  * @brief  To Disable optimize the I/O speed when the product voltage is low.
-  * @rmtoll CCCSR   HSLV2    LL_SYSCFG_DisableIOSpeedOptimize
-  * @note   This bit is active only if IO_HSLV user option bit is set. It must be used only if the
-  *         product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
-  *         might be destructive.
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimization2(void)
-{
-  CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV2);
-}
-
-/**
-  * @brief  To Disable optimize the I/O speed when the product voltage is low.
-  * @rmtoll CCCSR   HSLV3    LL_SYSCFG_DisableIOSpeedOptimize
-  * @note   This bit is active only if IO_HSLV user option bit is set. It must be used only if the
-  *         product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
-  *         might be destructive.
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimization3(void)
-{
-  CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV3);
-}
-#endif /*SYSCFG_CCCSR_HSLV1*/
-
-/**
-  * @brief  Check if the I/O speed optimization is enabled
-  * @rmtoll CCCSR   HSLV    LL_SYSCFG_IsEnabledIOSpeedOptimization
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimization(void)
-{
-#if defined(SYSCFG_CCCSR_HSLV)
-  return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV) == SYSCFG_CCCSR_HSLV) ? 1UL : 0UL);
-#else
-  return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV0) == SYSCFG_CCCSR_HSLV0) ? 1UL : 0UL);
-#endif /*SYSCFG_CCCSR_HSLV*/
-}
-
-#if defined(SYSCFG_CCCSR_HSLV1)
-/**
-  * @brief  Check if the I/O speed optimization is enabled
-  * @rmtoll CCCSR   HSLV1    LL_SYSCFG_IsEnabledIOSpeedOptimization
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimization1(void)
-{
-  return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV1) == SYSCFG_CCCSR_HSLV1) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the I/O speed optimization is enabled
-  * @rmtoll CCCSR   HSLV2    LL_SYSCFG_IsEnabledIOSpeedOptimization
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimization2(void)
-{
-  return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV2) == SYSCFG_CCCSR_HSLV2) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the I/O speed optimization is enabled
-  * @rmtoll CCCSR   HSLV3    LL_SYSCFG_IsEnabledIOSpeedOptimization
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimization3(void)
-{
-  return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV3) == SYSCFG_CCCSR_HSLV3) ? 1UL : 0UL);
-}
-#endif /*SYSCFG_CCCSR_HSLV1*/
-
-/**
-  * @brief  Set the code selection for the I/O Compensation cell
-  * @rmtoll CCCSR   CS    LL_SYSCFG_SetCellCompensationCode
-  * @param  CompCode: Selects the code to be applied for the I/O compensation cell
-  *   This parameter can be one of the following values:
-  *   @arg LL_SYSCFG_CELL_CODE : Select Code from the cell (available in the SYSCFG_CCVR)
-  *   @arg LL_SYSCFG_REGISTER_CODE: Select Code from the SYSCFG compensation cell code register (SYSCFG_CCCR)
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_SetCellCompensationCode(uint32_t CompCode)
-{
-  SET_BIT(SYSCFG->CCCSR, CompCode);
-}
-
-/**
-  * @brief  Get the code selected for the I/O Compensation cell
-  * @rmtoll CCCSR   CS    LL_SYSCFG_GetCellCompensationCode
-  * @retval Returned value can be one of the following values:
-  *   @arg LL_SYSCFG_CELL_CODE : Selected Code is from the cell (available in the SYSCFG_CCVR)
-  *   @arg LL_SYSCFG_REGISTER_CODE: Selected Code is from the SYSCFG compensation cell code register (SYSCFG_CCCR)
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_GetCellCompensationCode(void)
-{
-  return (uint32_t)(READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_CS));
-}
-
-#ifdef SYSCFG_CCCSR_CS_MMC
-
-/**
-  * @brief  Get the code selected for the I/O Compensation cell on the VDDMMC power rail
-  * @rmtoll CCCSR   CS    LL_SYSCFG_GetCellCompensationCode
-  * @retval Returned value can be one of the following values:
-  *   @arg LL_SYSCFG_CELL_CODE : Selected Code is from the cell (available in the SYSCFG_CCVR)
-  *   @arg LL_SYSCFG_REGISTER_CODE: Selected Code is from the SYSCFG compensation cell code register (SYSCFG_CCCR)
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_MMCGetCellCompensationCode(void)
-{
-  return (uint32_t)(READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_CS_MMC));
-}
-#endif /*SYSCFG_CCCSR_CS_MMC*/
-
-/**
-  * @brief  Get I/O compensation cell value for PMOS transistors
-  * @rmtoll CCVR    PCV   LL_SYSCFG_GetPMOSCompensationValue
-  * @retval Returned value is the I/O compensation cell value for PMOS transistors
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSCompensationValue(void)
-{
-  return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_PCV));
-}
-
-/**
-  * @brief  Get I/O compensation cell value for NMOS transistors
-  * @rmtoll CCVR    NCV   LL_SYSCFG_GetNMOSCompensationValue
-  * @retval Returned value is the I/O compensation cell value for NMOS transistors
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSCompensationValue(void)
-{
-  return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_NCV));
-}
-
-/**
-  * @brief  Set I/O compensation cell code for PMOS transistors
-  * @rmtoll CCCR    PCC   LL_SYSCFG_SetPMOSCompensationCode
-  * @param  PMOSCode PMOS compensation code
-  *         This code is applied to the I/O compensation cell when the CS bit of the
-  *         SYSCFG_CMPCR is set
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_SetPMOSCompensationCode(uint32_t PMOSCode)
-{
-  MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_PCC, PMOSCode);
-}
-
-/**
-  * @brief  Get I/O compensation cell code for PMOS transistors
-  * @rmtoll CCCR    PCC   LL_SYSCFG_GetPMOSCompensationCode
-  * @retval Returned value is the I/O compensation cell code for PMOS transistors
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSCompensationCode(void)
-{
-  return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_PCC));
-}
-
-#ifdef SYSCFG_CCCR_PCC_MMC
-
-/**
-  * @brief  Set I/O compensation cell code for PMOS transistors corresponding to the VDDMMC power rail
-  * @rmtoll CCCR    PCC   LL_SYSCFG_SetPMOSCompensationCode
-  * @param  PMOSCode PMOS compensation code
-  *         This code is applied to the I/O compensation cell when the CS bit of the
-  *         SYSCFG_CMPCR is set
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_MMCSetPMOSCompensationCode(uint32_t PMOSCode)
-{
-  MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_PCC_MMC, PMOSCode);
-}
-
-/**
-  * @brief  Get I/O compensation cell code for PMOS transistors corresponding to the VDDMMC power rail
-  * @rmtoll CCCR    PCC   LL_SYSCFG_GetPMOSCompensationCode
-  * @retval Returned value is the I/O compensation cell code for PMOS transistors
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_MMCGetPMOSCompensationCode(void)
-{
-  return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_PCC_MMC));
-}
-#endif /* SYSCFG_CCCR_PCC_MMC */
-
-/**
-  * @brief  Set I/O compensation cell code for NMOS transistors
-  * @rmtoll CCCR    NCC   LL_SYSCFG_SetNMOSCompensationCode
-  * @param  NMOSCode NMOS compensation code
-  *         This code is applied to the I/O compensation cell when the CS bit of the
-  *         SYSCFG_CMPCR is set
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_SetNMOSCompensationCode(uint32_t NMOSCode)
-{
-  MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC, NMOSCode);
-}
-
-/**
-  * @brief  Get I/O compensation cell code for NMOS transistors
-  * @rmtoll CCCR    NCC   LL_SYSCFG_GetNMOSCompensationCode
-  * @retval Returned value is the I/O compensation cell code for NMOS transistors
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSCompensationCode(void)
-{
-  return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_NCC));
-}
-
-#ifdef SYSCFG_CCCR_NCC_MMC
-
-/**
-  * @brief  Set I/O compensation cell code for NMOS transistors on the VDDMMC power rail.
-  * @rmtoll CCCR    NCC   LL_SYSCFG_SetNMOSCompensationCode
-  * @param  NMOSCode: NMOS compensation code
-  *         This code is applied to the I/O compensation cell when the CS bit of the
-  *         SYSCFG_CMPCR is set
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_VDMMCSetNMOSCompensationCode(uint32_t NMOSCode)
-{
-  MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC_MMC, NMOSCode);
-}
-
-/**
-  * @brief  Get I/O compensation cell code for NMOS transistors on the VDDMMC power rail.
-  * @rmtoll CCCR    NCC   LL_SYSCFG_GetNMOSCompensationCode
-  * @retval Returned value is the I/O compensation cell code for NMOS transistors
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_VDMMCGetNMOSCompensationCode(void)
-{
-  return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_NCC_MMC));
-}
-#endif /*SYSCFG_CCCR_NCC_MMC*/
-
-#ifdef SYSCFG_PKGR_PKG
-/**
-  * @brief  Get the device package
-  * @rmtoll PKGR    PKG   LL_SYSCFG_GetPackage
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SYSCFG_LQFP100_PACKAGE (*)
-  *         @arg @ref LL_SYSCFG_TQFP144_PACKAGE (*)
-  *         @arg @ref LL_SYSCFG_TQFP176_UFBGA176_PACKAGE (*)
-  *         @arg @ref LL_SYSCFG_LQFP208_TFBGA240_PACKAGE (*)
-  *         @arg @ref LL_SYSCFG_VFQFPN68_INDUS_PACKAGE (*)
-  *         @arg @ref LL_SYSCFG_TFBGA100_LQFP100_PACKAGE (*)
-  *         @arg @ref LL_SYSCFG_LQFP100_INDUS_PACKAGE (**)
-  *         @arg @ref LL_SYSCFG_TFBGA100_INDUS_PACKAGE (**)
-  *         @arg @ref LL_SYSCFG_WLCSP115_INDUS_PACKAGE (**)
-  *         @arg @ref LL_SYSCFG_LQFP144_PACKAGE (**)
-  *         @arg @ref LL_SYSCFG_UFBGA144_PACKAGE (**)
-  *         @arg @ref LL_SYSCFG_LQFP144_INDUS_PACKAGE (**)
-  *         @arg @ref LL_SYSCFG_UFBGA169_INDUS_PACKAGE (**)
-  *         @arg @ref LL_SYSCFG_UFBGA176PLUS25_INDUS_PACKAGE (**)
-  *         @arg @ref LL_SYSCFG_LQFP176_INDUS_PACKAGE (**)
-  *
-  * (*) : For stm32h74xxx and stm32h75xxx family lines.
-  * (**): For stm32h72xxx and stm32h73xxx family lines.
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_GetPackage(void)
-{
-  return (uint32_t)(READ_BIT(SYSCFG->PKGR, SYSCFG_PKGR_PKG));
-}
-#endif /*SYSCFG_PKGR_PKG*/
-
-#ifdef SYSCFG_UR0_RDP
-/**
-  * @brief  Get the Flash memory protection level
-  * @rmtoll UR0   RDP   LL_SYSCFG_GetFLashProtectionLevel
-  * @retval Returned value can be one of the following values:
-  *         0xAA : RDP level 0
-  *         0xCC : RDP level 2
-  *         Any other value : RDP level 1
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_GetFLashProtectionLevel(void)
-{
-  return (uint32_t)(READ_BIT(SYSCFG->UR0, SYSCFG_UR0_RDP));
-}
-#ifdef SYSCFG_UR0_BKS
-/**
-  * @brief  Indicate if the Flash memory bank addresses are inverted or not
-  * @rmtoll UR0   BKS   LL_SYSCFG_IsFLashBankAddressesSwaped
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsFLashBankAddressesSwaped(void)
-{
-  return ((READ_BIT(SYSCFG->UR0, SYSCFG_UR0_BKS) == 0U) ? 1UL : 0UL);
-}
-#endif /*SYSCFG_UR0_BKS*/
-
-/**
-  * @brief  Get the BOR Threshold Reset Level
-  * @rmtoll UR2   BORH    LL_SYSCFG_GetBrownoutResetLevel
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SYSCFG_BOR_HIGH_RESET_LEVEL
-  *         @arg @ref LL_SYSCFG_BOR_MEDIUM_RESET_LEVEL
-  *         @arg @ref LL_SYSCFG_BOR_LOW_RESET_LEVEL
-  *         @arg @ref LL_SYSCFG_BOR_OFF_RESET_LEVEL
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_GetBrownoutResetLevel(void)
-{
-  return (uint32_t)(READ_BIT(SYSCFG->UR2, SYSCFG_UR2_BORH));
-}
-/**
-  * @brief  BootCM7 address 0 configuration
-  * @rmtoll UR2   BOOT_ADD0   LL_SYSCFG_SetCM7BootAddress0
-  * @param  BootAddress :Specifies the CM7 Boot Address to be loaded in Address0
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_SetCM7BootAddress0(uint16_t BootAddress)
-{
-  /* Configure CM7 BOOT ADD0 */
-#if defined(DUAL_CORE)
-  MODIFY_REG(SYSCFG->UR2, SYSCFG_UR2_BCM7_ADD0, ((uint32_t)BootAddress << SYSCFG_UR2_BCM7_ADD0_Pos));
-#else
-  MODIFY_REG(SYSCFG->UR2, SYSCFG_UR2_BOOT_ADD0, ((uint32_t)BootAddress << SYSCFG_UR2_BOOT_ADD0_Pos));
-#endif /*DUAL_CORE*/
-
-}
-
-/**
-  * @brief  Get BootCM7 address 0
-  * @rmtoll UR2   BOOT_ADD0   LL_SYSCFG_GetCM7BootAddress0
-  * @retval Returned the CM7 Boot Address0
-  */
-__STATIC_INLINE uint16_t LL_SYSCFG_GetCM7BootAddress0(void)
-{
-  /* Get CM7 BOOT ADD0 */
-#if defined(DUAL_CORE)
-  return (uint16_t)((uint32_t)READ_BIT(SYSCFG->UR2, SYSCFG_UR2_BCM7_ADD0) >> SYSCFG_UR2_BCM7_ADD0_Pos);
-#else
-  return (uint16_t)((uint32_t)READ_BIT(SYSCFG->UR2, SYSCFG_UR2_BOOT_ADD0) >> SYSCFG_UR2_BOOT_ADD0_Pos);
-#endif /*DUAL_CORE*/
-}
-
-/**
-  * @brief  BootCM7 address 1 configuration
-  * @rmtoll UR3   BOOT_ADD1   LL_SYSCFG_SetCM7BootAddress1
-  * @param  BootAddress :Specifies the CM7 Boot Address to be loaded in Address1
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_SetCM7BootAddress1(uint16_t BootAddress)
-{
-  /* Configure CM7 BOOT ADD1 */
-#if defined(DUAL_CORE)
-  MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BCM7_ADD1, BootAddress);
-#else
-  MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BOOT_ADD1, BootAddress);
-#endif /*DUAL_CORE*/
-}
-
-/**
-  * @brief  Get BootCM7 address 1
-  * @rmtoll UR3   BOOT_ADD1   LL_SYSCFG_GetCM7BootAddress1
-  * @retval Returned the CM7 Boot Address0
-  */
-__STATIC_INLINE uint16_t LL_SYSCFG_GetCM7BootAddress1(void)
-{
-  /* Get CM7 BOOT ADD0 */
-#if defined(DUAL_CORE)
-  return (uint16_t)(READ_BIT(SYSCFG->UR3, SYSCFG_UR3_BCM7_ADD1));
-#else
-  return (uint16_t)(READ_BIT(SYSCFG->UR3, SYSCFG_UR3_BOOT_ADD1));
-#endif /* DUAL_CORE */
-}
-
-#if defined(DUAL_CORE)
-/**
-  * @brief  BootCM4 address 0 configuration
-  * @rmtoll UR3   BCM4_ADD0   LL_SYSCFG_SetCM4BootAddress0
-  * @param  BootAddress :Specifies the CM4 Boot Address to be loaded in Address0
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_SetCM4BootAddress0(uint16_t BootAddress)
-{
-  /* Configure CM4 BOOT ADD0 */
-  MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BCM4_ADD0, ((uint32_t)BootAddress << SYSCFG_UR3_BCM4_ADD0_Pos));
-}
-
-/**
-  * @brief  Get BootCM4 address 0
-  * @rmtoll UR3   BCM4_ADD0   LL_SYSCFG_GetCM4BootAddress0
-  * @retval Returned the CM4 Boot Address0
-  */
-__STATIC_INLINE uint16_t LL_SYSCFG_GetCM4BootAddress0(void)
-{
-  /* Get CM4 BOOT ADD0 */
-  return (uint16_t)((uint32_t)READ_BIT(SYSCFG->UR3, SYSCFG_UR3_BCM4_ADD0) >> SYSCFG_UR3_BCM4_ADD0_Pos);
-}
-
-/**
-  * @brief  BootCM4 address 1 configuration
-  * @rmtoll UR4   BCM4_ADD1   LL_SYSCFG_SetCM4BootAddress1
-  * @param  BootAddress :Specifies the CM4 Boot Address to be loaded in Address1
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_SetCM4BootAddress1(uint16_t BootAddress)
-{
-  /* Configure CM4 BOOT ADD1 */
-  MODIFY_REG(SYSCFG->UR4, SYSCFG_UR4_BCM4_ADD1, BootAddress);
-}
-
-/**
-  * @brief  Get BootCM4 address 1
-  * @rmtoll UR4   BCM4_ADD1   LL_SYSCFG_GetCM4BootAddress1
-  * @retval Returned the CM4 Boot Address0
-  */
-__STATIC_INLINE uint16_t LL_SYSCFG_GetCM4BootAddress1(void)
-{
-  /* Get CM4 BOOT ADD0 */
-  return (uint16_t)(READ_BIT(SYSCFG->UR4, SYSCFG_UR4_BCM4_ADD1));
-}
-#endif /*DUAL_CORE*/
-
-/**
-  * @brief  Indicates if the flash protected area (Bank 1) is erased by a mass erase
-  * @rmtoll UR4   MEPAD_BANK1   LL_SYSCFG_IsFlashB1ProtectedAreaErasable
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1ProtectedAreaErasable(void)
-{
-  return ((READ_BIT(SYSCFG->UR4, SYSCFG_UR4_MEPAD_BANK1) == SYSCFG_UR4_MEPAD_BANK1) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicates if the flash secured area (Bank 1) is erased by a mass erase
-  * @rmtoll UR5   MESAD_BANK1   LL_SYSCFG_IsFlashB1SecuredAreaErasable
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1SecuredAreaErasable(void)
-{
-  return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_MESAD_BANK1) == SYSCFG_UR5_MESAD_BANK1) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicates if the sector 0 of the Flash memory bank 1 is write protected
-  * @rmtoll UR5   WRPN_BANK1    LL_SYSCFG_IsFlashB1Sector0WriteProtected
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector0WriteProtected(void)
-{
-  return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR0_STATUS_BIT)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicates if the sector 1 of the Flash memory bank 1 is write protected
-  * @rmtoll UR5   WRPN_BANK1    LL_SYSCFG_IsFlashB1Sector1WriteProtected
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector1WriteProtected(void)
-{
-  return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR1_STATUS_BIT)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicates if the sector 2 of the Flash memory bank 1 is write protected
-  * @rmtoll UR5   WRPN_BANK1    LL_SYSCFG_IsFlashB1Sector2WriteProtected
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector2WriteProtected(void)
-{
-  return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR2_STATUS_BIT)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicates if the sector 3 of the Flash memory bank 1 is write protected
-  * @rmtoll UR5   WRPN_BANK1    LL_SYSCFG_IsFlashB1Sector3WriteProtected
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector3WriteProtected(void)
-{
-  return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR3_STATUS_BIT)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicates if the sector 4 of the Flash memory bank 1 is write protected
-  * @rmtoll UR5   WRPN_BANK1    LL_SYSCFG_IsFlashB1Sector4WriteProtected
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector4WriteProtected(void)
-{
-  return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR4_STATUS_BIT)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicates if the sector 5 of the Flash memory bank 1 is write protected
-  * @rmtoll UR5   WRPN_BANK1    LL_SYSCFG_IsFlashB1Sector5WriteProtected
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector5WriteProtected(void)
-{
-  return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR5_STATUS_BIT)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicates if the sector 6 of the Flash memory bank 1 is write protected
-  * @rmtoll UR5   WRPN_BANK1    LL_SYSCFG_IsFlashB1Sector6WriteProtected
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector6WriteProtected(void)
-{
-  return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR6_STATUS_BIT)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicates if the sector 7 of the Flash memory bank 1 is write protected
-  * @rmtoll UR5   WRPN_BANK1    LL_SYSCFG_IsFlashB1Sector7WriteProtected
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector7WriteProtected(void)
-{
-  return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR7_STATUS_BIT)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get the protected area start address for Flash bank 1
-  * @rmtoll UR6   PABEG_BANK1    LL_SYSCFG_GetFlashB1ProtectedAreaStartAddress
-  * @retval Returned the protected area start address for Flash bank 1
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB1ProtectedAreaStartAddress(void)
-{
-  return (uint32_t)(READ_BIT(SYSCFG->UR6, SYSCFG_UR6_PABEG_BANK1));
-}
-
-/**
-  * @brief  Get the protected area end address for Flash bank 1
-  * @rmtoll UR6   PAEND_BANK1   LL_SYSCFG_GetFlashB1ProtectedAreaEndAddress
-  * @retval Returned the protected area end address for Flash bank 1
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB1ProtectedAreaEndAddress(void)
-{
-  return (uint32_t)(READ_BIT(SYSCFG->UR6, SYSCFG_UR6_PAEND_BANK1));
-}
-
-/**
-  * @brief  Get the secured area start address for Flash bank 1
-  * @rmtoll UR7   SABEG_BANK1   LL_SYSCFG_GetFlashB1SecuredAreaStartAddress
-  * @retval Returned the secured area start address for Flash bank 1
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB1SecuredAreaStartAddress(void)
-{
-  return (uint32_t)(READ_BIT(SYSCFG->UR7, SYSCFG_UR7_SABEG_BANK1));
-}
-
-/**
-  * @brief  Get the secured area end address for Flash bank 1
-  * @rmtoll UR7   SAEND_BANK1   LL_SYSCFG_GetFlashB1SecuredAreaEndAddress
-  * @retval Returned the secured area end address for Flash bank 1
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB1SecuredAreaEndAddress(void)
-{
-  return (uint32_t)(READ_BIT(SYSCFG->UR7, SYSCFG_UR7_SAEND_BANK1));
-}
-
-#ifdef SYSCFG_UR8_MEPAD_BANK2
-/**
-  * @brief  Indicates if the flash protected area (Bank 2) is erased by a mass erase
-  * @rmtoll UR8   MEPAD_BANK2   LL_SYSCFG_IsFlashB2ProtectedAreaErasable
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2ProtectedAreaErasable(void)
-{
-  return ((READ_BIT(SYSCFG->UR8, SYSCFG_UR8_MEPAD_BANK2) == SYSCFG_UR8_MEPAD_BANK2) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicates if the flash secured area (Bank 2) is erased by a mass erase
-  * @rmtoll UR8   MESAD_BANK2   LL_SYSCFG_IsFlashB2SecuredAreaErasable
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2SecuredAreaErasable(void)
-{
-  return ((READ_BIT(SYSCFG->UR8, SYSCFG_UR8_MESAD_BANK2) == SYSCFG_UR8_MESAD_BANK2) ? 1UL : 0UL);
-}
-#endif /*SYSCFG_UR8_MEPAD_BANK2*/
-
-#ifdef SYSCFG_UR9_WRPN_BANK2
-/**
-  * @brief  Indicates if the sector 0 of the Flash memory bank 2 is write protected
-  * @rmtoll UR9   WRPN_BANK2    LL_SYSCFG_IsFlashB2Sector0WriteProtected
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector0WriteProtected(void)
-{
-  return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR0_STATUS_BIT)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicates if the sector 1 of the Flash memory bank 2 is write protected
-  * @rmtoll UR9   WRPN_BANK2    LL_SYSCFG_IsFlashB2Sector1WriteProtected
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector1WriteProtected(void)
-{
-  return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR1_STATUS_BIT)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicates if the sector 2 of the Flash memory bank 2 is write protected
-  * @rmtoll UR9   WRPN_BANK2    LL_SYSCFG_IsFlashB2Sector2WriteProtected
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector2WriteProtected(void)
-{
-  return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR2_STATUS_BIT)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicates if the sector 3 of the Flash memory bank 2 is write protected
-  * @rmtoll UR9   WRPN_BANK2    LL_SYSCFG_IsFlashB2Sector3WriteProtected
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector3WriteProtected(void)
-{
-  return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR3_STATUS_BIT)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicates if the sector 4 of the Flash memory bank 2 is write protected
-  * @rmtoll UR9   WRPN_BANK2    LL_SYSCFG_IsFlashB2Sector4WriteProtected
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector4WriteProtected(void)
-{
-  return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR4_STATUS_BIT)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicates if the sector 5 of the Flash memory bank 2 is write protected
-  * @rmtoll UR9   WRPN_BANK2    LL_SYSCFG_IsFlashB2Sector5WriteProtected
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector5WriteProtected(void)
-{
-  return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR5_STATUS_BIT)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicates if the sector 6 of the Flash memory bank 2 is write protected
-  * @rmtoll UR9   WRPN_BANK2    LL_SYSCFG_IsFlashB2Sector6WriteProtected
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector6WriteProtected(void)
-{
-  return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR6_STATUS_BIT)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicates if the sector 7 of the Flash memory bank 2 is write protected
-  * @rmtoll UR9   WRPN_BANK2    LL_SYSCFG_IsFlashB2Sector7WriteProtected
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector7WriteProtected(void)
-{
-  return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR7_STATUS_BIT)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get the protected area start address for Flash bank 2
-  * @rmtoll UR9   PABEG_BANK2   LL_SYSCFG_GetFlashB2ProtectedAreaStartAddress
-  * @retval Returned the protected area start address for Flash bank 2
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB2ProtectedAreaStartAddress(void)
-{
-  return (uint32_t)(READ_BIT(SYSCFG->UR9, SYSCFG_UR9_PABEG_BANK2));
-}
-#endif /*SYSCFG_UR9_WRPN_BANK2*/
-
-#ifdef SYSCFG_UR10_PAEND_BANK2
-/**
-  * @brief  Get the protected area end address for Flash bank 2
-  * @rmtoll UR10    PAEND_BANK2   LL_SYSCFG_GetFlashB2ProtectedAreaEndAddress
-  * @retval Returned the protected area end address for Flash bank 2
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB2ProtectedAreaEndAddress(void)
-{
-  return (uint32_t)(READ_BIT(SYSCFG->UR10, SYSCFG_UR10_PAEND_BANK2));
-}
-
-/**
-  * @brief  Get the secured area start address for Flash bank 2
-  * @rmtoll UR10    SABEG_BANK2   LL_SYSCFG_GetFlashB2SecuredAreaStartAddress
-  * @retval Returned the secured area start address for Flash bank 2
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB2SecuredAreaStartAddress(void)
-{
-  return (uint32_t)(READ_BIT(SYSCFG->UR10, SYSCFG_UR10_SABEG_BANK2));
-}
-#endif /*SYSCFG_UR10_PAEND_BANK2*/
-
-#ifdef SYSCFG_UR11_SAEND_BANK2
-/**
-  * @brief  Get the secured area end address for Flash bank 2
-  * @rmtoll UR11    SAEND_BANK2   LL_SYSCFG_GetFlashB2SecuredAreaEndAddress
-  * @retval Returned the secured area end address for Flash bank 2
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB2SecuredAreaEndAddress(void)
-{
-  return (uint32_t)(READ_BIT(SYSCFG->UR11, SYSCFG_UR11_SAEND_BANK2));
-}
-#endif /*SYSCFG_UR11_SAEND_BANK2*/
-
-/**
-  * @brief  Get the Independent Watchdog 1 control mode (Software or Hardware)
-  * @rmtoll UR11    IWDG1M    LL_SYSCFG_GetIWDG1ControlMode
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SYSCFG_IWDG1_SW_CONTROL_MODE
-  *         @arg @ref LL_SYSCFG_IWDG1_HW_CONTROL_MODE
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_GetIWDG1ControlMode(void)
-{
-  return (uint32_t)(READ_BIT(SYSCFG->UR11, SYSCFG_UR11_IWDG1M));
-}
-
-#if defined (DUAL_CORE)
-/**
-  * @brief  Get the Independent Watchdog 2 control mode (Software or Hardware)
-  * @rmtoll UR12    IWDG2M    LL_SYSCFG_GetIWDG2ControlMode
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SYSCFG_IWDG2_SW_CONTROL_MODE
-  *         @arg @ref LL_SYSCFG_IWDG2_HW_CONTROL_MODE
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_GetIWDG2ControlMode(void)
-{
-  return (uint32_t)(READ_BIT(SYSCFG->UR12, SYSCFG_UR12_IWDG2M));
-}
-#endif /* DUAL_CORE */
-
-/**
-  * @brief  Indicates the Secure mode status
-  * @rmtoll UR12    SECURE    LL_SYSCFG_IsSecureModeEnabled
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsSecureModeEnabled(void)
-{
-  return ((READ_BIT(SYSCFG->UR12, SYSCFG_UR12_SECURE) == SYSCFG_UR12_SECURE) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicates if a reset is generated when D1 domain enters DStandby mode
-  * @rmtoll UR13    D1SBRST   LL_SYSCFG_IsD1StandbyGenerateReset
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsD1StandbyGenerateReset(void)
-{
-  return ((READ_BIT(SYSCFG->UR13, SYSCFG_UR13_D1SBRST) == 0U) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get the secured DTCM RAM size
-  * @rmtoll UR13    SDRS    LL_SYSCFG_GetSecuredDTCMSize
-  * @retval Returned value can be one of the following values:
-  *           @arg @ref LL_SYSCFG_DTCM_RAM_SIZE_2KB
-  *           @arg @ref LL_SYSCFG_DTCM_RAM_SIZE_4KB
-  *           @arg @ref LL_SYSCFG_DTCM_RAM_SIZE_8KB
-  *           @arg @ref LL_SYSCFG_DTCM_RAM_SIZE_16KB
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_GetSecuredDTCMSize(void)
-{
-  return (uint32_t)(READ_BIT(SYSCFG->UR13, SYSCFG_UR13_SDRS));
-}
-
-/**
-  * @brief  Indicates if a reset is generated when D1 domain enters DStop mode
-  * @rmtoll UR14    D1STPRST    LL_SYSCFG_IsD1StopGenerateReset
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsD1StopGenerateReset(void)
-{
-  return ((READ_BIT(SYSCFG->UR14, SYSCFG_UR14_D1STPRST) == 0U) ? 1UL : 0UL);
-}
-
-#if defined (DUAL_CORE)
-/**
-  * @brief  Indicates if a reset is generated when D2 domain enters DStandby mode
-  * @rmtoll UR14    D2SBRST   LL_SYSCFG_IsD2StandbyGenerateReset
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsD2StandbyGenerateReset(void)
-{
-  return ((READ_BIT(SYSCFG->UR14, SYSCFG_UR14_D2SBRST) == 0U) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicates if a reset is generated when D2 domain enters DStop mode
-  * @rmtoll UR15    D2STPRST    LL_SYSCFG_IsD2StopGenerateReset
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsD2StopGenerateReset(void)
-{
-  return ((READ_BIT(SYSCFG->UR15, SYSCFG_UR15_D2STPRST) == 0U) ? 1UL : 0UL);
-}
-#endif /* DUAL_CORE */
-
-/**
-  * @brief  Indicates if the independent watchdog is frozen in Standby mode
-  * @rmtoll UR15    FZIWDGSTB   LL_SYSCFG_IsIWDGFrozenInStandbyMode
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsIWDGFrozenInStandbyMode(void)
-{
-  return ((READ_BIT(SYSCFG->UR15, SYSCFG_UR15_FZIWDGSTB) == 0U) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicates if the independent watchdog is frozen in Stop mode
-  * @rmtoll UR16    FZIWDGSTP   LL_SYSCFG_IsIWDGFrozenInStopMode
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsIWDGFrozenInStopMode(void)
-{
-  return ((READ_BIT(SYSCFG->UR16, SYSCFG_UR16_FZIWDGSTP) == 0U) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicates if the device private key is programmed
-  * @rmtoll UR16    PKP   LL_SYSCFG_IsPrivateKeyProgrammed
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsPrivateKeyProgrammed(void)
-{
-  return ((READ_BIT(SYSCFG->UR16, SYSCFG_UR16_PKP) == SYSCFG_UR16_PKP) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicates if the Product is working on the full voltage range or not
-  * @rmtoll UR17    IOHSLV    LL_SYSCFG_IsActiveFlag_IOHSLV
-  * @note   When the IOHSLV option bit is set the Product is working below 2.7 V.
-  *         When the IOHSLV option bit is reset the Product is working on the
-  *         full voltage range.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_IOHSLV(void)
-{
-  return ((READ_BIT(SYSCFG->UR17, SYSCFG_UR17_IOHSLV) == SYSCFG_UR17_IOHSLV) ? 1UL : 0UL);
-}
-
-#ifdef SYSCFG_UR17_TCM_AXI_CFG
-/**
-  * @brief  Get the size of ITCM-RAM and AXI-SRAM
-  * @rmtoll UR17    TCM_AXI_CFG    LL_SYSCFG_Get_ITCM_AXI_RAM_Size
-  * @retval Returned value can be one of the following values:
-  *           @arg @ref LL_SYSCFG_ITCM_AXI_64KB_320KB
-  *           @arg @ref LL_SYSCFG_ITCM_AXI_128KB_256KB
-  *           @arg @ref LL_SYSCFG_ITCM_AXI_192KB_192KB
-  *           @arg @ref LL_SYSCFG_ITCM_AXI_256KB_128KB
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_Get_ITCM_AXI_RAM_Size(void)
-{
-  return (uint32_t)(READ_BIT(SYSCFG->UR17, SYSCFG_UR17_TCM_AXI_CFG));
-}
-#endif /*SYSCFG_UR17_TCM_AXI_CFG*/
-
-#ifdef SYSCFG_UR18_CPU_FREQ_BOOST
-/**
-  * @brief  Indicates if the CPU maximum frequency boost is enabled
-  * @rmtoll UR18    CPU_FREQ_BOOST   LL_SYSCFG_IsCpuFreqBoostEnabled
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsCpuFreqBoostEnabled(void)
-{
-  return ((READ_BIT(SYSCFG->UR18, SYSCFG_UR18_CPU_FREQ_BOOST) == SYSCFG_UR18_CPU_FREQ_BOOST) ? 1UL : 0UL);
-}
-#endif /*SYSCFG_UR18_CPU_FREQ_BOOST*/
-
-#endif /*SYSCFG_UR0_RDP*/
-
-/**
-  * @}
-  */
-
-/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
-  * @{
-  */
-
-/**
-  * @brief  Return the device identifier
-  * @rmtoll DBGMCU_IDCODE DEV_ID        LL_DBGMCU_GetDeviceID
-  * @retval Values between Min_Data=0x00 and Max_Data=0xFFF
-  */
-__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
-{
-  return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
-}
-
-/**
-  * @brief  Return the device revision identifier
-  * @note This field indicates the revision of the device.
-          For example, it is read as RevA -> 0x1000, Cat 2 revZ -> 0x1001
-  * @rmtoll DBGMCU_IDCODE REV_ID        LL_DBGMCU_GetRevisionID
-  * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
-  */
-__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
-{
-  return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
-}
-
-/**
-  * @brief  Enable D1 Domain/CDomain debug during SLEEP mode
-  * @rmtoll DBGMCU_CR    DBGSLEEP_D1/DBGSLEEP_CD     LL_DBGMCU_EnableD1DebugInSleepMode
-  * @retval None
-  */
-__STATIC_INLINE void LL_DBGMCU_EnableD1DebugInSleepMode(void)
-{
-  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1);
-}
-
-/**
-  * @brief  Disable D1 Domain/CDomain debug during SLEEP mode
-  * @rmtoll DBGMCU_CR    DBGSLEEP_D1/DBGSLEEP_CD     LL_DBGMCU_DisableD1DebugInSleepMode
-  * @retval None
-  */
-__STATIC_INLINE void LL_DBGMCU_DisableD1DebugInSleepMode(void)
-{
-  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1);
-}
-
-/**
-  * @brief  Enable D1 Domain/CDomain debug during STOP mode
-  * @rmtoll DBGMCU_CR    DBGSTOP_D1/DBGSLEEP_CD     LL_DBGMCU_EnableD1DebugInStopMode
-  * @retval None
-  */
-__STATIC_INLINE void LL_DBGMCU_EnableD1DebugInStopMode(void)
-{
-  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD1);
-}
-
-/**
-  * @brief  Disable D1 Domain/CDomain debug during STOP mode
-  * @rmtoll DBGMCU_CR    DBGSTOP_D1/DBGSLEEP_CD     LL_DBGMCU_DisableD1DebugInStopMode
-  * @retval None
-  */
-__STATIC_INLINE void LL_DBGMCU_DisableD1DebugInStopMode(void)
-{
-  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD1);
-}
-
-/**
-  * @brief  Enable D1 Domain/CDomain debug during STANDBY mode
-  * @rmtoll DBGMCU_CR    DBGSTBY_D1/DBGSLEEP_CD     LL_DBGMCU_EnableD1DebugInStandbyMode
-  * @retval None
-  */
-__STATIC_INLINE void LL_DBGMCU_EnableD1DebugInStandbyMode(void)
-{
-  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD1);
-}
-
-/**
-  * @brief  Disable D1 Domain/CDomain debug during STANDBY mode
-  * @rmtoll DBGMCU_CR    DBGSTBY_D1/DBGSLEEP_CD     LL_DBGMCU_DisableD1DebugInStandbyMode
-  * @retval None
-  */
-__STATIC_INLINE void LL_DBGMCU_DisableD1DebugInStandbyMode(void)
-{
-  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD1);
-}
-
-#if defined (DUAL_CORE)
-/**
-  * @brief  Enable D2 Domain debug during SLEEP mode
-  * @rmtoll DBGMCU_CR    DBGSLEEP_D2     LL_DBGMCU_EnableD2DebugInSleepMode
-  * @retval None
-  */
-__STATIC_INLINE void LL_DBGMCU_EnableD2DebugInSleepMode(void)
-{
-  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD2);
-}
-
-/**
-  * @brief  Disable D2 Domain debug during SLEEP mode
-  * @rmtoll DBGMCU_CR    DBGSLEEP_D2     LL_DBGMCU_DisableD2DebugInSleepMode
-  * @retval None
-  */
-__STATIC_INLINE void LL_DBGMCU_DisableD2DebugInSleepMode(void)
-{
-  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD2);
-}
-
-/**
-  * @brief  Enable D2 Domain debug during STOP mode
-  * @rmtoll DBGMCU_CR    DBGSTOP_D2     LL_DBGMCU_EnableD2DebugInStopMode
-  * @retval None
-  */
-__STATIC_INLINE void LL_DBGMCU_EnableD2DebugInStopMode(void)
-{
-  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD2);
-}
-
-/**
-  * @brief  Disable D2 Domain debug during STOP mode
-  * @rmtoll DBGMCU_CR    DBGSTOP_D2     LL_DBGMCU_DisableD2DebugInStopMode
-  * @retval None
-  */
-__STATIC_INLINE void LL_DBGMCU_DisableD2DebugInStopMode(void)
-{
-  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD2);
-}
-
-/**
-  * @brief  Enable D2 Domain debug during STANDBY mode
-  * @rmtoll DBGMCU_CR    DBGSTBY_D2     LL_DBGMCU_EnableD2DebugInStandbyMode
-  * @retval None
-  */
-__STATIC_INLINE void LL_DBGMCU_EnableD2DebugInStandbyMode(void)
-{
-  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD2);
-}
-
-/**
-  * @brief  Disable D2 Domain debug during STANDBY mode
-  * @rmtoll DBGMCU_CR    DBGSTBY_D2     LL_DBGMCU_DisableD2DebugInStandbyMode
-  * @retval None
-  */
-__STATIC_INLINE void LL_DBGMCU_DisableD2DebugInStandbyMode(void)
-{
-  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD2);
-}
-#endif /* DUAL_CORE */
-
-
-#if defined(DBGMCU_CR_DBG_STOPD3)
-/**
-  * @brief  Enable D3 Domain/SRDomain debug during STOP mode
-  * @rmtoll DBGMCU_CR    DBGSTOP_D3/DBGSTOP_SRD    LL_DBGMCU_EnableD3DebugInStopMode
-  * @retval None
-  */
-__STATIC_INLINE void LL_DBGMCU_EnableD3DebugInStopMode(void)
-{
-  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD3);
-}
-
-/**
-  * @brief  Disable D3 Domain/SRDomain debug during STOP mode
-  * @rmtoll DBGMCU_CR    DBGSTOP_D3/DBGSTOP_SRD     LL_DBGMCU_DisableD3DebugInStopMode
-  * @retval None
-  */
-__STATIC_INLINE void LL_DBGMCU_DisableD3DebugInStopMode(void)
-{
-  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD3);
-}
-#endif /*DBGMCU_CR_DBG_STOPD3*/
-
-#if defined(DBGMCU_CR_DBG_STANDBYD3)
-/**
-  * @brief  Enable D3 Domain/SRDomain debug during STANDBY mode
-  * @rmtoll DBGMCU_CR    DBGSTBY_D3/DBGSTBY_SRD     LL_DBGMCU_EnableD3DebugInStandbyMode
-  * @retval None
-  */
-__STATIC_INLINE void LL_DBGMCU_EnableD3DebugInStandbyMode(void)
-{
-  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD3);
-}
-
-/**
-  * @brief  Disable D3 Domain/SRDomain debug during STANDBY mode
-  * @rmtoll DBGMCU_CR    DBGSTBY_D3/DBGSTBY_SRD     LL_DBGMCU_DisableD3DebugInStandbyMode
-  * @retval None
-  */
-__STATIC_INLINE void LL_DBGMCU_DisableD3DebugInStandbyMode(void)
-{
-  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD3);
-}
-#endif /*DBGMCU_CR_DBG_STANDBYD3*/
-
-/**
-  * @brief  Enable the trace port clock
-  * @rmtoll DBGMCU_CR    TRACECKEN     LL_DBGMCU_EnableTracePortClock
-  * @retval None
-  */
-__STATIC_INLINE void LL_DBGMCU_EnableTracePortClock(void)
-{
-  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TRACECKEN);
-}
-
-/**
-  * @brief  Disable the trace port clock
-  * @rmtoll DBGMCU_CR    TRACECKEN     LL_DBGMCU_DisableTracePortClock
-  * @retval None
-  */
-__STATIC_INLINE void LL_DBGMCU_DisableTracePortClock(void)
-{
-  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TRACECKEN);
-}
-
-/**
-  * @brief  Enable the Domain1/CDomain debug clock enable
-  * @rmtoll DBGMCU_CR    CKD1EN/CKCDEN     LL_DBGMCU_EnableD1DebugClock
-  * @retval None
-  */
-__STATIC_INLINE void LL_DBGMCU_EnableD1DebugClock(void)
-{
-  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CKD1EN);
-}
-
-/**
-  * @brief  Disable the Domain1/CDomain debug clock enable
-  * @rmtoll DBGMCU_CR    CKD1EN/CKCDEN     LL_DBGMCU_DisableD1DebugClock
-  * @retval None
-  */
-__STATIC_INLINE void LL_DBGMCU_DisableD1DebugClock(void)
-{
-  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CKD1EN);
-}
-
-/**
-  * @brief  Enable the Domain3/SRDomain debug clock enable
-  * @rmtoll DBGMCU_CR    CKD3EN/CKSRDEN     LL_DBGMCU_EnableD3DebugClock
-  * @retval None
-  */
-__STATIC_INLINE void LL_DBGMCU_EnableD3DebugClock(void)
-{
-  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CKD3EN);
-}
-
-/**
-  * @brief  Disable the Domain3/SRDomain debug clock enable
-  * @rmtoll DBGMCU_CR    CKD3EN/CKSRDEN    LL_DBGMCU_DisableD3DebugClock
-  * @retval None
-  */
-__STATIC_INLINE void LL_DBGMCU_DisableD3DebugClock(void)
-{
-  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CKD3EN);
-}
-
-#define LL_DBGMCU_TRGIO_INPUT_DIRECTION   0U
-#define LL_DBGMCU_TRGIO_OUTPUT_DIRECTION  DBGMCU_CR_DBG_TRGOEN
-/**
-  * @brief  Set the direction of the bi-directional trigger pin TRGIO
-  * @rmtoll DBGMCU_CR    TRGOEN    LL_DBGMCU_SetExternalTriggerPinDirection\n
-  * @param  PinDirection This parameter can be one of the following values:
-  *         @arg @ref LL_DBGMCU_TRGIO_INPUT_DIRECTION
-  *         @arg @ref LL_DBGMCU_TRGIO_OUTPUT_DIRECTION
-  * @retval None
-  */
-__STATIC_INLINE void LL_DBGMCU_SetExternalTriggerPinDirection(uint32_t PinDirection)
-{
-  MODIFY_REG(DBGMCU->CR, DBGMCU_CR_DBG_TRGOEN, PinDirection);
-}
-
-/**
-  * @brief  Get the direction of the bi-directional trigger pin TRGIO
-  * @rmtoll DBGMCU_CR    TRGOEN    LL_DBGMCU_GetExternalTriggerPinDirection\n
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DBGMCU_TRGIO_INPUT_DIRECTION
-  *         @arg @ref LL_DBGMCU_TRGIO_OUTPUT_DIRECTION
-  */
-__STATIC_INLINE uint32_t LL_DBGMCU_GetExternalTriggerPinDirection(void)
-{
-  return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TRGOEN));
-}
-
-/**
-  * @brief  Freeze APB1 group1 peripherals
-  * @rmtoll DBGMCU_APB1LFZ1   TIM2      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         DBGMCU_APB1LFZ1   TIM3      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         DBGMCU_APB1LFZ1   TIM4      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         DBGMCU_APB1LFZ1   TIM5      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         DBGMCU_APB1LFZ1   TIM6      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         DBGMCU_APB1LFZ1   TIM7      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         DBGMCU_APB1LFZ1   TIM12     LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         DBGMCU_APB1LFZ1   TIM13     LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         DBGMCU_APB1LFZ1   TIM14     LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         DBGMCU_APB1LFZ1   LPTIM1    LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         DBGMCU_APB1LFZ1   I2C1      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         DBGMCU_APB1LFZ1   I2C2      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         DBGMCU_APB1LFZ1   I2C3      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         DBGMCU_APB1LFZ1   I2C5      LL_DBGMCU_APB1_GRP1_FreezePeriph\n (*)
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C5_STOP (*)
-  *
-  *         (*) value not defined in all devices
-  * @retval None
-  */
-__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
-{
-  SET_BIT(DBGMCU->APB1LFZ1, Periphs);
-}
-
-/**
-  * @brief  Unfreeze APB1 peripherals (group1 peripherals)
-  * @rmtoll DBGMCU_APB1LFZ1   TIM2      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         DBGMCU_APB1LFZ1   TIM3      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         DBGMCU_APB1LFZ1   TIM4      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         DBGMCU_APB1LFZ1   TIM5      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         DBGMCU_APB1LFZ1   TIM6      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         DBGMCU_APB1LFZ1   TIM7      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         DBGMCU_APB1LFZ1   TIM12     LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         DBGMCU_APB1LFZ1   TIM13     LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         DBGMCU_APB1LFZ1   TIM14     LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         DBGMCU_APB1LFZ1   LPTIM1    LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         DBGMCU_APB1LFZ1   I2C1      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         DBGMCU_APB1LFZ1   I2C2      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         DBGMCU_APB1LFZ1   I2C3      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         DBGMCU_APB1LFZ1   I2C5      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C5_STOP (*)
-  *
-  *         (*) value not defined in all devices
-  * @retval None
-  */
-__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
-{
-  CLEAR_BIT(DBGMCU->APB1LFZ1, Periphs);
-}
-
-#ifdef DBGMCU_APB1HFZ1_DBG_FDCAN
-/**
-  * @brief  Freeze APB1 group2 peripherals
-  * @rmtoll DBGMCU_APB1HFZ1   FDCAN   LL_DBGMCU_APB1_GRP2_FreezePeriph\n
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_DBGMCU_APB1_GRP2_FDCAN_STOP
-  * @retval None
-  */
-__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)
-{
-  SET_BIT(DBGMCU->APB1HFZ1, Periphs);
-}
-
-/**
-  * @brief  Unfreeze APB1 group2 peripherals
-  * @rmtoll DBGMCU_APB1HFZ1   FDCAN   LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_DBGMCU_APB1_GRP2_FDCAN_STOP
-  * @retval None
-  */
-__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)
-{
-  CLEAR_BIT(DBGMCU->APB1HFZ1, Periphs);
-}
-#endif /*DBGMCU_APB1HFZ1_DBG_FDCAN*/
-
-#if defined(TIM23) || defined(TIM24)
-/**
-  * @brief  Freeze APB1 group2 peripherals
-  * @rmtoll DBGMCU_APB1HFZ1   TIM23   LL_DBGMCU_APB1_GRP2_FreezePeriph\n
-  *         DBGMCU_APB1HFZ1   TIM24   LL_DBGMCU_APB1_GRP2_FreezePeriph\n
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_DBGMCU_APB1_GRP2_TIM23_STOP
-  *         @arg @ref LL_DBGMCU_APB1_GRP2_TIM24_STOP
-  * @retval None
-  */
-__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)
-{
-  SET_BIT(DBGMCU->APB1HFZ1, Periphs);
-}
-
-/**
-  * @brief  Unfreeze APB1 group2 peripherals
-  * @rmtoll DBGMCU_APB1HFZ1   TIM23   LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n
-            DBGMCU_APB1HFZ1   TIM24   LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_DBGMCU_APB1_GRP2_TIM23_STOP
-  *         @arg @ref LL_DBGMCU_APB1_GRP2_TIM24_STOP
-  * @retval None
-  */
-__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)
-{
-  CLEAR_BIT(DBGMCU->APB1HFZ1, Periphs);
-}
-#endif /* TIM23 || TIM24 */
-
-/**
-  * @brief  Freeze APB2 peripherals
-  * @rmtoll DBGMCU_APB2FZ1    TIM1     LL_DBGMCU_APB2_GRP1_FreezePeriph\n
-  *         DBGMCU_APB2FZ1    TIM8     LL_DBGMCU_APB2_GRP1_FreezePeriph\n
-  *         DBGMCU_APB2FZ1    TIM15    LL_DBGMCU_APB2_GRP1_FreezePeriph\n
-  *         DBGMCU_APB2FZ1    TIM16    LL_DBGMCU_APB2_GRP1_FreezePeriph\n
-  *         DBGMCU_APB2FZ1    TIM17    LL_DBGMCU_APB2_GRP1_FreezePeriph
-  *         DBGMCU_APB2FZ1    HRTIM    LL_DBGMCU_APB2_GRP1_FreezePeriph
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
-  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP
-  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
-  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
-  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
-  *         @arg @ref LL_DBGMCU_APB2_GRP1_HRTIM_STOP (*)
-  *
-  *         (*) value not defined in all devices
-  * @retval None
-  */
-__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
-{
-  SET_BIT(DBGMCU->APB2FZ1, Periphs);
-}
-
-/**
-  * @brief  Unfreeze APB2 peripherals
-  * @rmtoll DBGMCU_APB2FZ1    TIM1     LL_DBGMCU_APB2_GRP1_FreezePeriph\n
-  *         DBGMCU_APB2FZ1    TIM8     LL_DBGMCU_APB2_GRP1_FreezePeriph\n
-  *         DBGMCU_APB2FZ1    TIM15    LL_DBGMCU_APB2_GRP1_FreezePeriph\n
-  *         DBGMCU_APB2FZ1    TIM16    LL_DBGMCU_APB2_GRP1_FreezePeriph\n
-  *         DBGMCU_APB2FZ1    TIM17    LL_DBGMCU_APB2_GRP1_FreezePeriph
-  *         DBGMCU_APB2FZ1    HRTIM    LL_DBGMCU_APB2_GRP1_FreezePeriph
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
-  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP
-  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
-  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
-  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
-  *         @arg @ref LL_DBGMCU_APB2_GRP1_HRTIM_STOP (*)
-  *
-  *         (*) value not defined in all devices
-  * @retval None
-  */
-__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
-{
-  CLEAR_BIT(DBGMCU->APB2FZ1, Periphs);
-}
-
-/**
-  * @brief  Freeze APB3 peripherals
-  * @rmtoll DBGMCU_APB3FZ1    WWDG1     LL_DBGMCU_APB3_GRP1_FreezePeriph\n
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_DBGMCU_APB3_GRP1_WWDG1_STOP
-  * @retval None
-  */
-__STATIC_INLINE void LL_DBGMCU_APB3_GRP1_FreezePeriph(uint32_t Periphs)
-{
-  SET_BIT(DBGMCU->APB3FZ1, Periphs);
-}
-
-/**
-  * @brief  Unfreeze APB3 peripherals
-  * @rmtoll DBGMCU_APB3FZ1    WWDG1     LL_DBGMCU_APB3_GRP1_UnFreezePeriph\n
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_DBGMCU_APB3_GRP1_WWDG1_STOP
-  * @retval None
-  */
-__STATIC_INLINE void LL_DBGMCU_APB3_GRP1_UnFreezePeriph(uint32_t Periphs)
-{
-  CLEAR_BIT(DBGMCU->APB3FZ1, Periphs);
-}
-
-/**
-  * @brief  Freeze APB4 peripherals
-  * @rmtoll DBGMCU_APB4FZ1    I2C4      LL_DBGMCU_APB4_GRP1_FreezePeriph\n
-  * @rmtoll DBGMCU_APB4FZ1    LPTIM2    LL_DBGMCU_APB4_GRP1_FreezePeriph\n
-  * @rmtoll DBGMCU_APB4FZ1    LPTIM3    LL_DBGMCU_APB4_GRP1_FreezePeriph\n
-  * @rmtoll DBGMCU_APB4FZ1    LPTIM4    LL_DBGMCU_APB4_GRP1_FreezePeriph\n
-  * @rmtoll DBGMCU_APB4FZ1    LPTIM5    LL_DBGMCU_APB4_GRP1_FreezePeriph\n
-  * @rmtoll DBGMCU_APB4FZ1    RTC       LL_DBGMCU_APB4_GRP1_FreezePeriph\n
-  * @rmtoll DBGMCU_APB4FZ1    WDGLSD1   LL_DBGMCU_APB4_GRP1_FreezePeriph\n
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_DBGMCU_APB4_GRP1_I2C4_STOP
-  *         @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM2_STOP
-  *         @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM3_STOP
-  *         @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM4_STOP (*)
-  *         @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM5_STOP (*)
-  *         @arg @ref LL_DBGMCU_APB4_GRP1_RTC_STOP
-  *         @arg @ref LL_DBGMCU_APB4_GRP1_IWDG1_STOP
-  *
-  *         (*) value not defined in all devices
-  * @retval None
-  */
-__STATIC_INLINE void LL_DBGMCU_APB4_GRP1_FreezePeriph(uint32_t Periphs)
-{
-  SET_BIT(DBGMCU->APB4FZ1, Periphs);
-}
-
-/**
-  * @brief  Unfreeze APB4 peripherals
-  * @rmtoll DBGMCU_APB4FZ1    I2C4      LL_DBGMCU_APB4_GRP1_FreezePeriph\n
-  * @rmtoll DBGMCU_APB4FZ1    LPTIM2    LL_DBGMCU_APB4_GRP1_FreezePeriph\n
-  * @rmtoll DBGMCU_APB4FZ1    LPTIM3    LL_DBGMCU_APB4_GRP1_FreezePeriph\n
-  * @rmtoll DBGMCU_APB4FZ1    LPTIM4    LL_DBGMCU_APB4_GRP1_FreezePeriph\n
-  * @rmtoll DBGMCU_APB4FZ1    LPTIM5    LL_DBGMCU_APB4_GRP1_FreezePeriph\n
-  * @rmtoll DBGMCU_APB4FZ1    RTC       LL_DBGMCU_APB4_GRP1_FreezePeriph\n
-  * @rmtoll DBGMCU_APB4FZ1    WDGLSD1   LL_DBGMCU_APB4_GRP1_FreezePeriph\n
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_DBGMCU_APB4_GRP1_I2C4_STOP
-  *         @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM2_STOP
-  *         @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM3_STOP
-  *         @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM4_STOP (*)
-  *         @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM5_STOP (*)
-  *         @arg @ref LL_DBGMCU_APB4_GRP1_RTC_STOP
-  *         @arg @ref LL_DBGMCU_APB4_GRP1_IWDG1_STOP
-  *
-  *         (*) value not defined in all devices
-  * @retval None
-  */
-__STATIC_INLINE void LL_DBGMCU_APB4_GRP1_UnFreezePeriph(uint32_t Periphs)
-{
-  CLEAR_BIT(DBGMCU->APB4FZ1, Periphs);
-}
-/**
-  * @}
-  */
-
-/** @defgroup SYSTEM_LL_EF_FLASH FLASH
-  * @{
-  */
-
-/**
-  * @brief  Set FLASH Latency
-  * @rmtoll FLASH_ACR    LATENCY       LL_FLASH_SetLatency
-  * @param  Latency This parameter can be one of the following values:
-  *         @arg @ref LL_FLASH_LATENCY_0
-  *         @arg @ref LL_FLASH_LATENCY_1
-  *         @arg @ref LL_FLASH_LATENCY_2
-  *         @arg @ref LL_FLASH_LATENCY_3
-  *         @arg @ref LL_FLASH_LATENCY_4
-  *         @arg @ref LL_FLASH_LATENCY_5
-  *         @arg @ref LL_FLASH_LATENCY_6
-  *         @arg @ref LL_FLASH_LATENCY_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
-{
-  MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
-}
-
-/**
-  * @brief  Get FLASH Latency
-  * @rmtoll FLASH_ACR    LATENCY       LL_FLASH_GetLatency
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_FLASH_LATENCY_0
-  *         @arg @ref LL_FLASH_LATENCY_1
-  *         @arg @ref LL_FLASH_LATENCY_2
-  *         @arg @ref LL_FLASH_LATENCY_3
-  *         @arg @ref LL_FLASH_LATENCY_4
-  *         @arg @ref LL_FLASH_LATENCY_5
-  *         @arg @ref LL_FLASH_LATENCY_6
-  *         @arg @ref LL_FLASH_LATENCY_7
-  */
-__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
-{
-  return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
-}
-
-/**
-  * @}
-  */
-
-#if defined(DUAL_CORE)
-/** @defgroup SYSTEM_LL_EF_ART ART
-  * @{
-  */
-
-/**
-  * @brief  Enable the Cortex-M4 ART cache.
-  * @rmtoll ART_CTR    EN   LL_ART_Enable
-  * @retval None
-  */
-__STATIC_INLINE void LL_ART_Enable(void)
-{
- SET_BIT(ART->CTR, ART_CTR_EN);
-}
-
-/**
-  * @brief  Disable the Cortex-M4 ART cache.
-  * @rmtoll ART_CTR    EN   LL_ART_Disable
-  * @retval None
-  */
-__STATIC_INLINE void LL_ART_Disable(void)
-{
- CLEAR_BIT(ART->CTR, ART_CTR_EN);
-}
-
-/**
-  * @brief  Check if the Cortex-M4 ART cache is enabled
-  * @rmtoll ART_CTR   EN    LL_ART_IsEnabled
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_ART_IsEnabled(void)
-{
-  return ((READ_BIT(ART->CTR, ART_CTR_EN) == ART_CTR_EN) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Set the Cortex-M4 ART cache Base Address.
-  * @rmtoll ART_CTR    PCACHEADDR   LL_ART_SetBaseAddress
-  * @param  BaseAddress Specifies the Base address of 1 Mbyte address page (cacheable page)
-            from which the ART accelerator loads code to the cache.
-  * @retval None
-  */
-__STATIC_INLINE void LL_ART_SetBaseAddress(uint32_t BaseAddress)
-{
- MODIFY_REG(ART->CTR, ART_CTR_PCACHEADDR, (((BaseAddress) >> 12U) & 0x000FFF00UL));
-}
-
-/**
-  * @brief  Get the Cortex-M4 ART cache Base Address.
-  * @rmtoll ART_CTR    PCACHEADDR   LL_ART_GetBaseAddress
-  * @retval the Base address of 1 Mbyte address page (cacheable page)
-            from which the ART accelerator loads code to the cache
-  */
-__STATIC_INLINE uint32_t LL_ART_GetBaseAddress(void)
-{
-  return (uint32_t)(READ_BIT(ART->CTR, ART_CTR_PCACHEADDR) << 12U);
-}
-#endif /* DUAL_CORE */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32H7xx_LL_SYSTEM_H */
-
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_ll_system.h
+  * @author  MCD Application Team
+  * @brief   Header file of SYSTEM LL module.
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    The LL SYSTEM driver contains a set of generic APIs that can be
+    used by user:
+      (+) Some of the FLASH features need to be handled in the SYSTEM file.
+      (+) Access to DBGCMU registers
+      (+) Access to SYSCFG registers
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32H7xx_LL_SYSTEM_H
+#define __STM32H7xx_LL_SYSTEM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx.h"
+
+/** @addtogroup STM32H7xx_LL_Driver
+  * @{
+  */
+
+#if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU)
+
+/** @defgroup SYSTEM_LL SYSTEM
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
+  * @{
+  */
+/** @defgroup SYSTEM_LL_EC_FLASH_BANK1_SECTORS SYSCFG Flash Bank1 sectors bits status
+  * @{
+  */
+#define LL_SYSCFG_FLASH_B1_SECTOR0_STATUS_BIT   0x10000U
+#define LL_SYSCFG_FLASH_B1_SECTOR1_STATUS_BIT   0x20000U
+#define LL_SYSCFG_FLASH_B1_SECTOR2_STATUS_BIT   0x40000U
+#define LL_SYSCFG_FLASH_B1_SECTOR3_STATUS_BIT   0x80000U
+#define LL_SYSCFG_FLASH_B1_SECTOR4_STATUS_BIT   0x100000U
+#define LL_SYSCFG_FLASH_B1_SECTOR5_STATUS_BIT   0x200000U
+#define LL_SYSCFG_FLASH_B1_SECTOR6_STATUS_BIT   0x400000U
+#define LL_SYSCFG_FLASH_B1_SECTOR7_STATUS_BIT   0x800000U
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_FLASH_BANK2_SECTORS SYSCFG Flash Bank2 sectors bits status
+  * @{
+  */
+#define LL_SYSCFG_FLASH_B2_SECTOR0_STATUS_BIT   0x10000U
+#define LL_SYSCFG_FLASH_B2_SECTOR1_STATUS_BIT   0x20000U
+#define LL_SYSCFG_FLASH_B2_SECTOR2_STATUS_BIT   0x40000U
+#define LL_SYSCFG_FLASH_B2_SECTOR3_STATUS_BIT   0x80000U
+#define LL_SYSCFG_FLASH_B2_SECTOR4_STATUS_BIT   0x100000U
+#define LL_SYSCFG_FLASH_B2_SECTOR5_STATUS_BIT   0x200000U
+#define LL_SYSCFG_FLASH_B2_SECTOR6_STATUS_BIT   0x400000U
+#define LL_SYSCFG_FLASH_B2_SECTOR7_STATUS_BIT   0x800000U
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
+  * @{
+  */
+
+/** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
+  * @{
+  */
+#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1        SYSCFG_PMCR_I2C1_FMP       /*!< Enable Fast Mode Plus for I2C1      */
+#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2        SYSCFG_PMCR_I2C2_FMP       /*!< Enable Fast Mode Plus for I2C2      */
+#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3        SYSCFG_PMCR_I2C3_FMP       /*!< Enable Fast Mode Plus for I2C3      */
+#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C4        SYSCFG_PMCR_I2C4_FMP       /*!< Enable Fast Mode Plus for I2C4      */
+#if defined(I2C5)
+#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C5        SYSCFG_PMCR_I2C5_FMP       /*!< Enable Fast Mode Plus for I2C5      */
+#endif /*I2C5*/
+#define LL_SYSCFG_I2C_FASTMODEPLUS_PB6         SYSCFG_PMCR_I2C_PB6_FMP    /*!< Enable Fast Mode Plus on PB6        */
+#define LL_SYSCFG_I2C_FASTMODEPLUS_PB7         SYSCFG_PMCR_I2C_PB7_FMP    /*!< Enable Fast Mode Plus on PB7        */
+#define LL_SYSCFG_I2C_FASTMODEPLUS_PB8         SYSCFG_PMCR_I2C_PB8_FMP    /*!< Enable Fast Mode Plus on PB8        */
+#define LL_SYSCFG_I2C_FASTMODEPLUS_PB9         SYSCFG_PMCR_I2C_PB9_FMP    /*!< Enable Fast Mode Plus on PB9        */
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_ANALOG_SWITCH Analog Switch control
+* @{
+*/
+#if defined(SYSCFG_PMCR_BOOSTEN)
+#define LL_SYSCFG_ANALOG_SWITCH_BOOSTEN           SYSCFG_PMCR_BOOSTEN               /*!< I/O analog switch voltage booster enable */
+#endif /*SYSCFG_PMCR_BOOSTEN*/
+#define LL_SYSCFG_ANALOG_SWITCH_PA0               SYSCFG_PMCR_PA0SO                 /*!< PA0 Switch Open */
+#define LL_SYSCFG_ANALOG_SWITCH_PA1               SYSCFG_PMCR_PA1SO                 /*!< PA1 Switch Open */
+#define LL_SYSCFG_ANALOG_SWITCH_PC2               SYSCFG_PMCR_PC2SO                 /*!< PC2 Switch Open */
+#define LL_SYSCFG_ANALOG_SWITCH_PC3               SYSCFG_PMCR_PC3SO                 /*!< PC3 Switch Open */
+/**
+  * @}
+  */
+
+#if defined(SYSCFG_PMCR_EPIS_SEL)
+/** @defgroup SYSTEM_LL_EC_EPIS Ethernet PHY Interface Selection
+* @{
+*/
+#define LL_SYSCFG_ETH_MII               0x00000000U                           /*!< ETH Media MII interface */
+#define LL_SYSCFG_ETH_RMII              SYSCFG_PMCR_EPIS_SEL_2                /*!< ETH Media RMII interface */
+/**
+  * @}
+  */
+#endif /* SYSCFG_PMCR_EPIS_SEL */
+
+/** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT
+  * @{
+  */
+#define LL_SYSCFG_EXTI_PORTA               0U               /*!< EXTI PORT A                        */
+#define LL_SYSCFG_EXTI_PORTB               1U               /*!< EXTI PORT B                        */
+#define LL_SYSCFG_EXTI_PORTC               2U               /*!< EXTI PORT C                        */
+#define LL_SYSCFG_EXTI_PORTD               3U               /*!< EXTI PORT D                        */
+#define LL_SYSCFG_EXTI_PORTE               4U               /*!< EXTI PORT E                        */
+#define LL_SYSCFG_EXTI_PORTF               5U               /*!< EXTI PORT F                        */
+#define LL_SYSCFG_EXTI_PORTG               6U               /*!< EXTI PORT G                        */
+#define LL_SYSCFG_EXTI_PORTH               7U               /*!< EXTI PORT H                        */
+#if defined(GPIOI)
+#define LL_SYSCFG_EXTI_PORTI               8U               /*!< EXTI PORT I                        */
+#endif /*GPIOI*/
+#define LL_SYSCFG_EXTI_PORTJ               9U               /*!< EXTI PORT J                        */
+#define LL_SYSCFG_EXTI_PORTK               10U              /*!< EXTI PORT k                        */
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE
+  * @{
+  */
+#define LL_SYSCFG_EXTI_LINE0               ((0x000FUL << 16U) | 0U)  /*!< EXTI_POSITION_0  | EXTICR[0] */
+#define LL_SYSCFG_EXTI_LINE1               ((0x00F0UL << 16U) | 0U)  /*!< EXTI_POSITION_4  | EXTICR[0] */
+#define LL_SYSCFG_EXTI_LINE2               ((0x0F00UL << 16U) | 0U)  /*!< EXTI_POSITION_8  | EXTICR[0] */
+#define LL_SYSCFG_EXTI_LINE3               ((0xF000UL << 16U) | 0U)  /*!< EXTI_POSITION_12 | EXTICR[0] */
+#define LL_SYSCFG_EXTI_LINE4               ((0x000FUL << 16U) | 1U)  /*!< EXTI_POSITION_0  | EXTICR[1] */
+#define LL_SYSCFG_EXTI_LINE5               ((0x00F0UL << 16U) | 1U)  /*!< EXTI_POSITION_4  | EXTICR[1] */
+#define LL_SYSCFG_EXTI_LINE6               ((0x0F00UL << 16U) | 1U)  /*!< EXTI_POSITION_8  | EXTICR[1] */
+#define LL_SYSCFG_EXTI_LINE7               ((0xF000UL << 16U) | 1U)  /*!< EXTI_POSITION_12 | EXTICR[1] */
+#define LL_SYSCFG_EXTI_LINE8               ((0x000FUL << 16U) | 2U)  /*!< EXTI_POSITION_0  | EXTICR[2] */
+#define LL_SYSCFG_EXTI_LINE9               ((0x00F0UL << 16U) | 2U)  /*!< EXTI_POSITION_4  | EXTICR[2] */
+#define LL_SYSCFG_EXTI_LINE10              ((0x0F00UL << 16U) | 2U)  /*!< EXTI_POSITION_8  | EXTICR[2] */
+#define LL_SYSCFG_EXTI_LINE11              ((0xF000UL << 16U) | 2U)  /*!< EXTI_POSITION_12 | EXTICR[2] */
+#define LL_SYSCFG_EXTI_LINE12              ((0x000FUL << 16U) | 3U)  /*!< EXTI_POSITION_0  | EXTICR[3] */
+#define LL_SYSCFG_EXTI_LINE13              ((0x00F0UL << 16U) | 3U)  /*!< EXTI_POSITION_4  | EXTICR[3] */
+#define LL_SYSCFG_EXTI_LINE14              ((0x0F00UL << 16U) | 3U)  /*!< EXTI_POSITION_8  | EXTICR[3] */
+#define LL_SYSCFG_EXTI_LINE15              ((0xF000UL << 16U) | 3U)  /*!< EXTI_POSITION_12 | EXTICR[3] */
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
+  * @{
+  */
+#define LL_SYSCFG_TIMBREAK_AXISRAM_DBL_ECC SYSCFG_CFGR_AXISRAML /*!< Enables and locks the AXIRAM double ECC error signal
+                                                                     with Break Input of TIM1/8/15/16/17 and HRTIM        */
+
+#define LL_SYSCFG_TIMBREAK_ITCM_DBL_ECC    SYSCFG_CFGR_ITCML    /*!< Enables and locks the ITCM double ECC error signal
+                                                                     with Break Input of TIM1/8/15/16/17 and HRTIM        */
+
+#define LL_SYSCFG_TIMBREAK_DTCM_DBL_ECC    SYSCFG_CFGR_DTCML    /*!< Enables and locks the DTCM double ECC error signal
+                                                                     with Break Input of TIM1/8/15/16/17 and HRTIM        */
+
+#define LL_SYSCFG_TIMBREAK_SRAM1_DBL_ECC   SYSCFG_CFGR_SRAM1L   /*!< Enables and locks the SRAM1 double ECC error signal
+                                                                     with Break Input of TIM1/8/15/16/17 and HRTIM        */
+
+#define LL_SYSCFG_TIMBREAK_SRAM2_DBL_ECC   SYSCFG_CFGR_SRAM2L   /*!< Enables and locks the SRAM2 double ECC error signal
+                                                                     with Break Input of TIM1/8/15/16/17 and HRTIM        */
+
+#if defined(SYSCFG_CFGR_SRAM3L)
+#define LL_SYSCFG_TIMBREAK_SRAM3_DBL_ECC   SYSCFG_CFGR_SRAM3L   /*!< Enables and locks the SRAM3 double ECC error signal
+                                                                     with Break Input of TIM1/8/15/16/17 and HRTIM        */
+#endif /*SYSCFG_CFGR_SRAM3L*/
+
+#define LL_SYSCFG_TIMBREAK_SRAM4_DBL_ECC   SYSCFG_CFGR_SRAM4L   /*!< Enables and locks the SRAM4 double ECC error signal
+                                                                     with Break Input of TIM1/8/15/16/17 and HRTIM        */
+
+#define LL_SYSCFG_TIMBREAK_BKRAM_DBL_ECC   SYSCFG_CFGR_BKRAML   /*!< Enables and locks the BKRAM double ECC error signal
+                                                                     with Break Input of TIM1/8/15/16/17 and HRTIM        */
+
+#define LL_SYSCFG_TIMBREAK_CM7_LOCKUP      SYSCFG_CFGR_CM7L     /*!< Enables and locks the Cortex-M7 LOCKUP signal
+                                                                     with Break Input of TIM1/8/15/16/17 and HRTIM        */
+
+#define LL_SYSCFG_TIMBREAK_FLASH_DBL_ECC   SYSCFG_CFGR_FLASHL   /*!< Enables and locks the FLASH double ECC error signal
+                                                                     with Break Input of TIM1/8/15/16/17 and HRTIM        */
+
+#define LL_SYSCFG_TIMBREAK_PVD             SYSCFG_CFGR_PVDL     /*!< Enables and locks the PVD connection
+                                                                     with TIM1/8/15/16/17 and HRTIM Break Input
+                                                                     and also the PVDE and PLS bits of the Power Control Interface */
+#if defined(DUAL_CORE)
+#define LL_SYSCFG_TIMBREAK_CM4_LOCKUP      SYSCFG_CFGR_CM4L     /*!< Enables and locks the Cortex-M4 LOCKUP signal
+                                                                     with Break Input of TIM1/8/15/16/17 and HRTIM        */
+#endif /* DUAL_CORE */
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_CS SYSCFG I/O compensation cell Code selection
+  * @{
+  */
+#define LL_SYSCFG_CELL_CODE               0U
+#define LL_SYSCFG_REGISTER_CODE           SYSCFG_CCCSR_CS
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_IWDG1_CONTROL_MODES SYSCFG IWDG1 control modes
+  * @{
+  */
+#define LL_SYSCFG_IWDG1_SW_CONTROL_MODE   0U
+#define LL_SYSCFG_IWDG1_HW_CONTROL_MODE   SYSCFG_UR11_IWDG1M
+/**
+  * @}
+  */
+
+#if defined (DUAL_CORE)
+/** @defgroup SYSTEM_LL_IWDG2_CONTROL_MODES SYSCFG IWDG2 control modes
+  * @{
+  */
+#define LL_SYSCFG_IWDG2_SW_CONTROL_MODE   0U
+#define LL_SYSCFG_IWDG2_HW_CONTROL_MODE   SYSCFG_UR12_IWDG2M
+/**
+  * @}
+  */
+#endif /* DUAL_CORE */
+
+/** @defgroup SYSTEM_LL_DTCM_RAM_SIZE SYSCFG DTCM RAM size configuration
+  * @{
+  */
+#define LL_SYSCFG_DTCM_RAM_SIZE_2KB     0U
+#define LL_SYSCFG_DTCM_RAM_SIZE_4KB     1U
+#define LL_SYSCFG_DTCM_RAM_SIZE_8KB     2U
+#define LL_SYSCFG_DTCM_RAM_SIZE_16KB    3U
+/**
+  * @}
+  */
+#ifdef SYSCFG_UR17_TCM_AXI_CFG
+/** @defgroup SYSTEM_LL_PACKAGE SYSCFG device package
+  * @{
+  */
+#define LL_SYSCFG_ITCM_AXI_64KB_320KB     0U
+#define LL_SYSCFG_ITCM_AXI_128KB_256KB    1U
+#define LL_SYSCFG_ITCM_AXI_192KB_192KB    2U
+#define LL_SYSCFG_ITCM_AXI_256KB_128KB    3U
+/**
+  * @}
+  */
+#endif /* #ifdef SYSCFG_UR17_TCM_AXI_CFG */
+#if defined(SYSCFG_PKGR_PKG)
+/** @defgroup SYSTEM_LL_PACKAGE SYSCFG device package
+  * @{
+  */
+#if (STM32H7_DEV_ID == 0x450UL)
+#define LL_SYSCFG_LQFP100_PACKAGE             0U
+#define LL_SYSCFG_TQFP144_PACKAGE             2U
+#define LL_SYSCFG_TQFP176_UFBGA176_PACKAGE    5U
+#define LL_SYSCFG_LQFP208_TFBGA240_PACKAGE    8U
+#elif (STM32H7_DEV_ID == 0x483UL)
+#define LL_SYSCFG_VFQFPN68_INDUS_PACKAGE       0U
+#define LL_SYSCFG_TFBGA100_LQFP100_PACKAGE    1U
+#define LL_SYSCFG_LQFP100_INDUS_PACKAGE        2U
+#define LL_SYSCFG_TFBGA100_INDUS_PACKAGE       3U
+#define LL_SYSCFG_WLCSP115_INDUS_PACKAGE       4U
+#define LL_SYSCFG_LQFP144_PACKAGE             5U
+#define LL_SYSCFG_UFBGA144_PACKAGE            6U
+#define LL_SYSCFG_LQFP144_INDUS_PACKAGE        7U
+#define LL_SYSCFG_UFBGA169_INDUS_PACKAGE       8U
+#define LL_SYSCFG_UFBGA176PLUS25_INDUS_PACKAGE 9U
+#define LL_SYSCFG_LQFP176_INDUS_PACKAGE        10U
+#endif /* STM32H7_DEV_ID == 0x450UL */
+/**
+  * @}
+  */
+#endif /* SYSCFG_PKGR_PKG */
+  
+/** @defgroup SYSTEM_LL_SYSCFG_BOR SYSCFG Brownout Reset Threshold Level
+  * @{
+  */
+#define LL_SYSCFG_BOR_OFF_RESET_LEVEL      0x00000000U
+#define LL_SYSCFG_BOR_LOW_RESET_LEVEL      SYSCFG_UR2_BORH_0
+#define LL_SYSCFG_BOR_MEDIUM_RESET_LEVEL   SYSCFG_UR2_BORH_1
+#define LL_SYSCFG_BOR_HIGH_RESET_LEVEL     SYSCFG_UR2_BORH
+
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
+  * @{
+  */
+#define LL_DBGMCU_TRACE_NONE               0x00000000U                                     /*!< TRACE pins not assigned (default state) */
+#define LL_DBGMCU_TRACE_ASYNCH             DBGMCU_CR_TRACE_IOEN                            /*!< TRACE pin assignment for Asynchronous Mode */
+#define LL_DBGMCU_TRACE_SYNCH_SIZE1        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */
+#define LL_DBGMCU_TRACE_SYNCH_SIZE2        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */
+#define LL_DBGMCU_TRACE_SYNCH_SIZE4        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)   /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
+  * @{
+  */
+#define LL_DBGMCU_APB1_GRP1_TIM2_STOP      DBGMCU_APB1LFZ1_DBG_TIM2     /*!< TIM2 counter stopped when core is halted */
+#define LL_DBGMCU_APB1_GRP1_TIM3_STOP      DBGMCU_APB1LFZ1_DBG_TIM3     /*!< TIM3 counter stopped when core is halted */
+#define LL_DBGMCU_APB1_GRP1_TIM4_STOP      DBGMCU_APB1LFZ1_DBG_TIM4     /*!< TIM4 counter stopped when core is halted */
+#define LL_DBGMCU_APB1_GRP1_TIM5_STOP      DBGMCU_APB1LFZ1_DBG_TIM5     /*!< TIM5 counter stopped when core is halted */
+#define LL_DBGMCU_APB1_GRP1_TIM6_STOP      DBGMCU_APB1LFZ1_DBG_TIM6     /*!< TIM6 counter stopped when core is halted */
+#define LL_DBGMCU_APB1_GRP1_TIM7_STOP      DBGMCU_APB1LFZ1_DBG_TIM7     /*!< TIM7 counter stopped when core is halted */
+#define LL_DBGMCU_APB1_GRP1_TIM12_STOP     DBGMCU_APB1LFZ1_DBG_TIM12    /*!< TIM12 counter stopped when core is halted */
+#define LL_DBGMCU_APB1_GRP1_TIM13_STOP     DBGMCU_APB1LFZ1_DBG_TIM13    /*!< TIM13 counter stopped when core is halted */
+#define LL_DBGMCU_APB1_GRP1_TIM14_STOP     DBGMCU_APB1LFZ1_DBG_TIM14    /*!< TIM14 counter stopped when core is halted */
+#define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP    DBGMCU_APB1LFZ1_DBG_LPTIM1   /*!< LPTIM1 counter stopped when core is halted */
+#define LL_DBGMCU_APB1_GRP1_I2C1_STOP      DBGMCU_APB1LFZ1_DBG_I2C1     /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
+#define LL_DBGMCU_APB1_GRP1_I2C2_STOP      DBGMCU_APB1LFZ1_DBG_I2C2     /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
+#define LL_DBGMCU_APB1_GRP1_I2C3_STOP      DBGMCU_APB1LFZ1_DBG_I2C3     /*!< I2C3 SMBUS timeout mode stopped when Core is halted */
+#if defined(I2C5)
+#define LL_DBGMCU_APB1_GRP1_I2C5_STOP      DBGMCU_APB1LFZ1_DBG_I2C5     /*!< I2C5 SMBUS timeout mode stopped when Core is halted */
+#endif /*I2C5*/
+/**
+  * @}
+  */
+
+
+/** @defgroup SYSTEM_LL_EC_APB1_GRP2_STOP_IP DBGMCU APB1 GRP2 STOP IP
+  * @{
+  */
+#if defined(DBGMCU_APB1HFZ1_DBG_FDCAN)
+#define LL_DBGMCU_APB1_GRP2_FDCAN_STOP    DBGMCU_APB1HFZ1_DBG_FDCAN    /*!< FDCAN is frozen while the core is in debug mode */
+#endif /*DBGMCU_APB1HFZ1_DBG_FDCAN*/
+#if defined(TIM23)
+#define LL_DBGMCU_APB1_GRP2_TIM23_STOP    DBGMCU_APB1HFZ1_DBG_TIM23    /*!< TIM23 is frozen while the core is in debug mode */
+#endif /*TIM23*/
+#if defined(TIM24)
+#define LL_DBGMCU_APB1_GRP2_TIM24_STOP    DBGMCU_APB1HFZ1_DBG_TIM24    /*!< TIM24 is frozen while the core is in debug mode */
+#endif /*TIM24*/
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
+  * @{
+  */
+#define LL_DBGMCU_APB2_GRP1_TIM1_STOP      DBGMCU_APB2FZ1_DBG_TIM1    /*!< TIM1 counter stopped when core is halted */
+#define LL_DBGMCU_APB2_GRP1_TIM8_STOP      DBGMCU_APB2FZ1_DBG_TIM8    /*!< TIM8 counter stopped when core is halted */
+#define LL_DBGMCU_APB2_GRP1_TIM15_STOP     DBGMCU_APB2FZ1_DBG_TIM15   /*!< TIM15 counter stopped when core is halted */
+#define LL_DBGMCU_APB2_GRP1_TIM16_STOP     DBGMCU_APB2FZ1_DBG_TIM16   /*!< TIM16 counter stopped when core is halted */
+#define LL_DBGMCU_APB2_GRP1_TIM17_STOP     DBGMCU_APB2FZ1_DBG_TIM17   /*!< TIM17 counter stopped when core is halted */
+#if defined(HRTIM1)
+#define LL_DBGMCU_APB2_GRP1_HRTIM_STOP     DBGMCU_APB2FZ1_DBG_HRTIM   /*!< HRTIM counter stopped when core is halted */
+#endif /*HRTIM1*/
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_APB3_GRP1_STOP_IP DBGMCU APB3 GRP1 STOP IP
+  * @{
+  */
+#define LL_DBGMCU_APB3_GRP1_WWDG1_STOP      DBGMCU_APB3FZ1_DBG_WWDG1   /*!< WWDG1 is frozen while the core is in debug mode */
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_APB4_GRP1_STOP_IP DBGMCU APB4 GRP1 STOP IP
+  * @{
+  */
+#define LL_DBGMCU_APB4_GRP1_I2C4_STOP       DBGMCU_APB4FZ1_DBG_I2C4     /*!< I2C4 is frozen while the core is in debug mode */
+#define LL_DBGMCU_APB4_GRP1_LPTIM2_STOP     DBGMCU_APB4FZ1_DBG_LPTIM2   /*!< LPTIM2 is frozen while the core is in debug mode */
+#define LL_DBGMCU_APB4_GRP1_LPTIM3_STOP     DBGMCU_APB4FZ1_DBG_LPTIM3   /*!< LPTIM3 is frozen while the core is in debug mode */
+#define LL_DBGMCU_APB4_GRP1_LPTIM4_STOP     DBGMCU_APB4FZ1_DBG_LPTIM4   /*!< LPTIM4 is frozen while the core is in debug mode */
+#define LL_DBGMCU_APB4_GRP1_LPTIM5_STOP     DBGMCU_APB4FZ1_DBG_LPTIM5   /*!< LPTIM5 is frozen while the core is in debug mode */
+#define LL_DBGMCU_APB4_GRP1_RTC_STOP        DBGMCU_APB4FZ1_DBG_RTC      /*!< RTC is frozen while the core is in debug mode */
+#define LL_DBGMCU_APB4_GRP1_IWDG1_STOP      DBGMCU_APB4FZ1_DBG_IWDG1    /*!< IWDG1 is frozen while the core is in debug mode */
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
+  * @{
+  */
+#define LL_FLASH_LATENCY_0                 FLASH_ACR_LATENCY_0WS   /*!< FLASH Zero wait state */
+#define LL_FLASH_LATENCY_1                 FLASH_ACR_LATENCY_1WS   /*!< FLASH One wait state */
+#define LL_FLASH_LATENCY_2                 FLASH_ACR_LATENCY_2WS   /*!< FLASH Two wait states */
+#define LL_FLASH_LATENCY_3                 FLASH_ACR_LATENCY_3WS   /*!< FLASH Three wait states */
+#define LL_FLASH_LATENCY_4                 FLASH_ACR_LATENCY_4WS   /*!< FLASH Four wait states */
+#define LL_FLASH_LATENCY_5                 FLASH_ACR_LATENCY_5WS   /*!< FLASH five wait state */
+#define LL_FLASH_LATENCY_6                 FLASH_ACR_LATENCY_6WS   /*!< FLASH six wait state */
+#define LL_FLASH_LATENCY_7                 FLASH_ACR_LATENCY_7WS   /*!< FLASH seven wait states */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
+  * @{
+  */
+
+/** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
+  * @{
+  */
+
+#if defined(SYSCFG_PMCR_EPIS_SEL)
+/**
+  * @brief  Select Ethernet PHY interface
+  * @rmtoll PMCR    EPIS_SEL    LL_SYSCFG_SetPHYInterface
+  * @param  Interface This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_ETH_MII
+  *         @arg @ref LL_SYSCFG_ETH_RMII
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_SetPHYInterface(uint32_t Interface)
+{
+  MODIFY_REG(SYSCFG->PMCR, SYSCFG_PMCR_EPIS_SEL, Interface);
+}
+
+/**
+  * @brief  Get Ethernet PHY interface
+  * @rmtoll PMCR    EPIS_SEL    LL_SYSCFG_GetPHYInterface
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSCFG_ETH_MII
+  *         @arg @ref LL_SYSCFG_ETH_RMII
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetPHYInterface(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->PMCR, SYSCFG_PMCR_EPIS_SEL));
+}
+
+#endif /* SYSCFG_PMCR_EPIS_SEL */
+/**
+  * @brief  Open an Analog Switch
+  * @rmtoll PMCR    PA0SO   LL_SYSCFG_OpenAnalogSwitch
+  * @rmtoll PMCR    PA1SO   LL_SYSCFG_OpenAnalogSwitch
+  * @rmtoll PMCR    PC2SO   LL_SYSCFG_OpenAnalogSwitch
+  * @rmtoll PMCR    PC3SO   LL_SYSCFG_OpenAnalogSwitch
+  * @param  AnalogSwitch This parameter can be one of the following values:
+  *         @arg LL_SYSCFG_ANALOG_SWITCH_PA0 : PA0 analog switch
+  *         @arg LL_SYSCFG_ANALOG_SWITCH_PA1:  PA1 analog switch
+  *         @arg LL_SYSCFG_ANALOG_SWITCH_PC2 : PC2 analog switch
+  *         @arg LL_SYSCFG_ANALOG_SWITCH_PC3:  PC3 analog switch
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_OpenAnalogSwitch(uint32_t AnalogSwitch)
+{
+  SET_BIT(SYSCFG->PMCR, AnalogSwitch);
+}
+
+/**
+  * @brief  Close an Analog Switch
+  * @rmtoll PMCR    PA0SO   LL_SYSCFG_CloseAnalogSwitch
+  * @rmtoll PMCR    PA1SO   LL_SYSCFG_CloseAnalogSwitch
+  * @rmtoll PMCR    PC2SO   LL_SYSCFG_CloseAnalogSwitch
+  * @rmtoll PMCR    PC3SO   LL_SYSCFG_CloseAnalogSwitch
+  * @param  AnalogSwitch This parameter can be one of the following values:
+  *         @arg LL_SYSCFG_ANALOG_SWITCH_PA0 : PA0 analog switch
+  *         @arg LL_SYSCFG_ANALOG_SWITCH_PA1:  PA1 analog switch
+  *         @arg LL_SYSCFG_ANALOG_SWITCH_PC2 : PC2 analog switch
+  *         @arg LL_SYSCFG_ANALOG_SWITCH_PC3:  PC3 analog switch
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_CloseAnalogSwitch(uint32_t AnalogSwitch)
+{
+  CLEAR_BIT(SYSCFG->PMCR, AnalogSwitch);
+}
+#ifdef SYSCFG_PMCR_BOOSTEN
+/**
+  * @brief  Enable the Analog booster to reduce the total harmonic distortion
+  *         of the analog switch when the supply voltage is lower than 2.7 V
+  * @rmtoll PMCR    BOOSTEN   LL_SYSCFG_EnableAnalogBooster
+  * @note   Activating the booster allows to guaranty the analog switch AC performance
+  *         when the supply voltage is below 2.7 V: in this case, the analog switch
+  *         performance is the same on the full voltage range
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_EnableAnalogBooster(void)
+{
+ SET_BIT(SYSCFG->PMCR, SYSCFG_PMCR_BOOSTEN) ;
+}
+
+/**
+  * @brief  Disable the Analog booster
+  * @rmtoll PMCR    BOOSTEN   LL_SYSCFG_DisableAnalogBooster
+  * @note   Activating the booster allows to guaranty the analog switch AC performance
+  *         when the supply voltage is below 2.7 V: in this case, the analog switch
+  *         performance is the same on the full voltage range
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DisableAnalogBooster(void)
+{
+ CLEAR_BIT(SYSCFG->PMCR, SYSCFG_PMCR_BOOSTEN) ;
+}
+#endif /*SYSCFG_PMCR_BOOSTEN*/
+/**
+  * @brief  Enable the I2C fast mode plus driving capability.
+  * @rmtoll SYSCFG_PMCR   I2C_PBx_FMP   LL_SYSCFG_EnableFastModePlus\n
+  *         SYSCFG_PMCR   I2Cx_FMP      LL_SYSCFG_EnableFastModePlus
+  * @param  ConfigFastModePlus This parameter can be a combination of the following values:
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4(*)
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C5(*)
+  *
+  *         (*) value not defined in all devices
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
+{
+  SET_BIT(SYSCFG->PMCR, ConfigFastModePlus);
+}
+
+/**
+  * @brief  Disable the I2C fast mode plus driving capability.
+  * @rmtoll SYSCFG_PMCR    I2C_PBx_FMP   LL_SYSCFG_DisableFastModePlus\n
+  *         SYSCFG_PMCR    I2Cx_FMP      LL_SYSCFG_DisableFastModePlus
+  * @param  ConfigFastModePlus This parameter can be a combination of the following values:
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C5 (*)
+  *
+  *         (*) value not defined in all devices
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
+{
+  CLEAR_BIT(SYSCFG->PMCR, ConfigFastModePlus);
+}
+
+/**
+  * @brief  Configure source input for the EXTI external interrupt.
+  * @rmtoll SYSCFG_EXTICR1  EXTIx         LL_SYSCFG_SetEXTISource\n
+  *         SYSCFG_EXTICR2 EXTIx         LL_SYSCFG_SetEXTISource\n
+  *         SYSCFG_EXTICR3 EXTIx         LL_SYSCFG_SetEXTISource\n
+  *         SYSCFG_EXTICR4 EXTIx         LL_SYSCFG_SetEXTISource
+  * @param  Port This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_EXTI_PORTA
+  *         @arg @ref LL_SYSCFG_EXTI_PORTB
+  *         @arg @ref LL_SYSCFG_EXTI_PORTC
+  *         @arg @ref LL_SYSCFG_EXTI_PORTD
+  *         @arg @ref LL_SYSCFG_EXTI_PORTE
+  *         @arg @ref LL_SYSCFG_EXTI_PORTF
+  *         @arg @ref LL_SYSCFG_EXTI_PORTG
+  *         @arg @ref LL_SYSCFG_EXTI_PORTH
+  *         @arg @ref LL_SYSCFG_EXTI_PORTI (*)
+  *         @arg @ref LL_SYSCFG_EXTI_PORTJ
+  *         @arg @ref LL_SYSCFG_EXTI_PORTK
+  *
+  *         (*) value not defined in all devices
+  * @param  Line This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_EXTI_LINE0
+  *         @arg @ref LL_SYSCFG_EXTI_LINE1
+  *         @arg @ref LL_SYSCFG_EXTI_LINE2
+  *         @arg @ref LL_SYSCFG_EXTI_LINE3
+  *         @arg @ref LL_SYSCFG_EXTI_LINE4
+  *         @arg @ref LL_SYSCFG_EXTI_LINE5
+  *         @arg @ref LL_SYSCFG_EXTI_LINE6
+  *         @arg @ref LL_SYSCFG_EXTI_LINE7
+  *         @arg @ref LL_SYSCFG_EXTI_LINE8
+  *         @arg @ref LL_SYSCFG_EXTI_LINE9
+  *         @arg @ref LL_SYSCFG_EXTI_LINE10
+  *         @arg @ref LL_SYSCFG_EXTI_LINE11
+  *         @arg @ref LL_SYSCFG_EXTI_LINE12
+  *         @arg @ref LL_SYSCFG_EXTI_LINE13
+  *         @arg @ref LL_SYSCFG_EXTI_LINE14
+  *         @arg @ref LL_SYSCFG_EXTI_LINE15
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
+{
+  MODIFY_REG(SYSCFG->EXTICR[Line & 0x3U], (Line >> 16U), Port << ((POSITION_VAL(Line >> 16U)) & 31U));
+}
+
+/**
+  * @brief  Get the configured defined for specific EXTI Line
+  * @rmtoll SYSCFG_EXTICR1 EXTIx         LL_SYSCFG_GetEXTISource\n
+  *         SYSCFG_EXTICR2 EXTIx         LL_SYSCFG_GetEXTISource\n
+  *         SYSCFG_EXTICR3 EXTIx         LL_SYSCFG_GetEXTISource\n
+  *         SYSCFG_EXTICR4 EXTIx         LL_SYSCFG_GetEXTISource
+  * @param  Line This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_EXTI_LINE0
+  *         @arg @ref LL_SYSCFG_EXTI_LINE1
+  *         @arg @ref LL_SYSCFG_EXTI_LINE2
+  *         @arg @ref LL_SYSCFG_EXTI_LINE3
+  *         @arg @ref LL_SYSCFG_EXTI_LINE4
+  *         @arg @ref LL_SYSCFG_EXTI_LINE5
+  *         @arg @ref LL_SYSCFG_EXTI_LINE6
+  *         @arg @ref LL_SYSCFG_EXTI_LINE7
+  *         @arg @ref LL_SYSCFG_EXTI_LINE8
+  *         @arg @ref LL_SYSCFG_EXTI_LINE9
+  *         @arg @ref LL_SYSCFG_EXTI_LINE10
+  *         @arg @ref LL_SYSCFG_EXTI_LINE11
+  *         @arg @ref LL_SYSCFG_EXTI_LINE12
+  *         @arg @ref LL_SYSCFG_EXTI_LINE13
+  *         @arg @ref LL_SYSCFG_EXTI_LINE14
+  *         @arg @ref LL_SYSCFG_EXTI_LINE15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSCFG_EXTI_PORTA
+  *         @arg @ref LL_SYSCFG_EXTI_PORTB
+  *         @arg @ref LL_SYSCFG_EXTI_PORTC
+  *         @arg @ref LL_SYSCFG_EXTI_PORTD
+  *         @arg @ref LL_SYSCFG_EXTI_PORTE
+  *         @arg @ref LL_SYSCFG_EXTI_PORTF
+  *         @arg @ref LL_SYSCFG_EXTI_PORTG
+  *         @arg @ref LL_SYSCFG_EXTI_PORTH
+  *         @arg @ref LL_SYSCFG_EXTI_PORTI (*)
+  *         @arg @ref LL_SYSCFG_EXTI_PORTJ
+  *         @arg @ref LL_SYSCFG_EXTI_PORTK
+  *         (*) value not defined in all devices
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0x3U], (Line >> 16U)) >> (POSITION_VAL(Line >> 16U) & 31U));
+}
+
+/**
+  * @brief  Set connections to TIM1/8/15/16/17 and HRTIM Break inputs
+  * @note this feature is available on STM32H7 rev.B and above
+  * @rmtoll SYSCFG_CFGR AXISRAML       LL_SYSCFG_SetTIMBreakInputs\n
+  *         SYSCFG_CFGR ITCML          LL_SYSCFG_SetTIMBreakInputs\n
+  *         SYSCFG_CFGR DTCML          LL_SYSCFG_SetTIMBreakInputs\n
+  *         SYSCFG_CFGR SRAM1L         LL_SYSCFG_SetTIMBreakInputs\n
+  *         SYSCFG_CFGR SRAM2L         LL_SYSCFG_SetTIMBreakInputs\n
+  *         SYSCFG_CFGR SRAM3L         LL_SYSCFG_SetTIMBreakInputs\n
+  *         SYSCFG_CFGR SRAM4L         LL_SYSCFG_SetTIMBreakInputs\n
+  *         SYSCFG_CFGR BKRAML         LL_SYSCFG_SetTIMBreakInputs\n
+  *         SYSCFG_CFGR CM7L           LL_SYSCFG_SetTIMBreakInputs\n
+  *         SYSCFG_CFGR FLASHL         LL_SYSCFG_SetTIMBreakInputs\n
+  *         SYSCFG_CFGR PVDL           LL_SYSCFG_SetTIMBreakInputs\n
+  *         SYSCFG_CFGR_CM4L           LL_SYSCFG_SetTIMBreakInputs
+  * @param  Break This parameter can be a combination of the following values:
+  *         @arg @ref LL_SYSCFG_TIMBREAK_AXISRAM_DBL_ECC
+  *         @arg @ref LL_SYSCFG_TIMBREAK_ITCM_DBL_ECC
+  *         @arg @ref LL_SYSCFG_TIMBREAK_DTCM_DBL_ECC
+  *         @arg @ref LL_SYSCFG_TIMBREAK_SRAM1_DBL_ECC
+  *         @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_DBL_ECC
+  *         @arg @ref LL_SYSCFG_TIMBREAK_SRAM3_DBL_ECC (*)
+  *         @arg @ref LL_SYSCFG_TIMBREAK_SRAM4_DBL_ECC
+  *         @arg @ref LL_SYSCFG_TIMBREAK_BKRAM_DBL_ECC
+  *         @arg @ref LL_SYSCFG_TIMBREAK_CM7_LOCKUP
+  *         @arg @ref LL_SYSCFG_TIMBREAK_FLASH_DBL_ECC
+  *         @arg @ref LL_SYSCFG_TIMBREAK_PVD
+  *         @arg @ref LL_SYSCFG_TIMBREAK_CM4_LOCKUP (available for dual core lines only)
+  * @retval None
+  *         (*) value not defined in all devices
+  */
+__STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
+{
+#if defined(DUAL_CORE)
+  MODIFY_REG(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML  | SYSCFG_CFGR_DTCML  | SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | \
+                           SYSCFG_CFGR_SRAM3L   | SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L   | SYSCFG_CFGR_FLASHL | \
+                           SYSCFG_CFGR_PVDL     | SYSCFG_CFGR_CM4L, Break);
+#elif defined(SYSCFG_CFGR_AXISRAML) && defined(SYSCFG_CFGR_SRAM3L)
+  MODIFY_REG(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML  | SYSCFG_CFGR_DTCML  | SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | \
+                           SYSCFG_CFGR_SRAM3L   | SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L   | SYSCFG_CFGR_FLASHL | \
+                           SYSCFG_CFGR_PVDL, Break);
+#elif defined(SYSCFG_CFGR_AXISRAML)
+  MODIFY_REG(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML  | SYSCFG_CFGR_DTCML  | SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | \
+                           SYSCFG_CFGR_SRAM4L   | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L   | SYSCFG_CFGR_FLASHL | SYSCFG_CFGR_PVDL,\
+                           Break);
+#else
+  MODIFY_REG(SYSCFG->CFGR, SYSCFG_CFGR_ITCML  | SYSCFG_CFGR_DTCML  |\
+                           SYSCFG_CFGR_CM7L   | SYSCFG_CFGR_FLASHL | \
+                           SYSCFG_CFGR_PVDL, Break);
+#endif /* DUAL_CORE */
+}
+
+/**
+  * @brief  Get connections to TIM1/8/15/16/17 and HRTIM Break inputs
+  * @note this feature is available on STM32H7 rev.B and above
+  * @rmtoll SYSCFG_CFGR AXISRAML       LL_SYSCFG_GetTIMBreakInputs\n
+  *         SYSCFG_CFGR ITCML          LL_SYSCFG_GetTIMBreakInputs\n
+  *         SYSCFG_CFGR DTCML          LL_SYSCFG_GetTIMBreakInputs\n
+  *         SYSCFG_CFGR SRAM1L         LL_SYSCFG_GetTIMBreakInputs\n
+  *         SYSCFG_CFGR SRAM2L         LL_SYSCFG_GetTIMBreakInputs\n
+  *         SYSCFG_CFGR SRAM3L         LL_SYSCFG_GetTIMBreakInputs\n
+  *         SYSCFG_CFGR SRAM4L         LL_SYSCFG_GetTIMBreakInputs\n
+  *         SYSCFG_CFGR BKRAML         LL_SYSCFG_GetTIMBreakInputs\n
+  *         SYSCFG_CFGR CM7L           LL_SYSCFG_GetTIMBreakInputs\n
+  *         SYSCFG_CFGR FLASHL         LL_SYSCFG_GetTIMBreakInputs\n
+  *         SYSCFG_CFGR PVDL           LL_SYSCFG_GetTIMBreakInputs\n
+  *         SYSCFG_CFGR_CM4L           LL_SYSCFG_GetTIMBreakInputs
+  * @retval Returned value can be can be a combination of the following values:
+  *         @arg @ref LL_SYSCFG_TIMBREAK_AXISRAM_DBL_ECC
+  *         @arg @ref LL_SYSCFG_TIMBREAK_ITCM_DBL_ECC
+  *         @arg @ref LL_SYSCFG_TIMBREAK_DTCM_DBL_ECC
+  *         @arg @ref LL_SYSCFG_TIMBREAK_SRAM1_DBL_ECC
+  *         @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_DBL_ECC
+  *         @arg @ref LL_SYSCFG_TIMBREAK_SRAM3_DBL_ECC (*)
+  *         @arg @ref LL_SYSCFG_TIMBREAK_SRAM4_DBL_ECC
+  *         @arg @ref LL_SYSCFG_TIMBREAK_BKRAM_DBL_ECC
+  *         @arg @ref LL_SYSCFG_TIMBREAK_CM7_LOCKUP
+  *         @arg @ref LL_SYSCFG_TIMBREAK_FLASH_DBL_ECC
+  *         @arg @ref LL_SYSCFG_TIMBREAK_PVD
+  *         @arg @ref LL_SYSCFG_TIMBREAK_CM4_LOCKUP (available for dual core lines only)
+  *         (*) value not defined in all devices
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
+{
+#if defined(DUAL_CORE)
+  return (uint32_t)(READ_BIT(SYSCFG->CFGR,  SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML  | SYSCFG_CFGR_DTCML  | \
+                                            SYSCFG_CFGR_SRAM1L   | SYSCFG_CFGR_SRAM2L | SYSCFG_CFGR_SRAM3L | \
+                                            SYSCFG_CFGR_SRAM4L   | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L   | \
+                                            SYSCFG_CFGR_FLASHL   | SYSCFG_CFGR_PVDL   | SYSCFG_CFGR_CM4L));
+#elif defined (SYSCFG_CFGR_AXISRAML) && defined(SYSCFG_CFGR_SRAM3L)
+  return (uint32_t)(READ_BIT(SYSCFG->CFGR,  SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML  | SYSCFG_CFGR_DTCML  | \
+                                            SYSCFG_CFGR_SRAM1L   | SYSCFG_CFGR_SRAM2L | SYSCFG_CFGR_SRAM3L | \
+                                            SYSCFG_CFGR_SRAM4L   | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L   | \
+                                            SYSCFG_CFGR_FLASHL   | SYSCFG_CFGR_PVDL ));
+#elif defined (SYSCFG_CFGR_AXISRAML)
+  return (uint32_t)(READ_BIT(SYSCFG->CFGR,  SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML  | SYSCFG_CFGR_DTCML  | \
+                                            SYSCFG_CFGR_SRAM1L   | SYSCFG_CFGR_SRAM2L | \
+                                            SYSCFG_CFGR_SRAM4L   | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L   | \
+                                            SYSCFG_CFGR_FLASHL   | SYSCFG_CFGR_PVDL ));
+#else
+  return (uint32_t)(READ_BIT(SYSCFG->CFGR,  SYSCFG_CFGR_ITCML    | SYSCFG_CFGR_DTCML  | SYSCFG_CFGR_CM7L   | \
+                                            SYSCFG_CFGR_FLASHL   | SYSCFG_CFGR_PVDL ));
+#endif /* DUAL_CORE */
+}
+
+/**
+  * @brief  Enable the Compensation Cell
+  * @rmtoll CCCSR   EN    LL_SYSCFG_EnableCompensationCell
+  * @note   The I/O compensation cell can be used only when the device supply
+  *         voltage ranges from 1.62 to 2.0 V and from 2.7 to 3.6 V.
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_EnableCompensationCell(void)
+{
+  SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN);
+}
+
+/**
+  * @brief  Disable the Compensation Cell
+  * @rmtoll CCCSR   EN    LL_SYSCFG_DisableCompensationCell
+  * @note   The I/O compensation cell can be used only when the device supply
+  *         voltage ranges from 1.62 to 2.0 V and from 2.7 to 3.6 V.
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DisableCompensationCell(void)
+{
+  CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN);
+}
+
+/**
+  * @brief  Check if the Compensation Cell is enabled
+  * @rmtoll CCCSR   EN    LL_SYSCFG_IsEnabledCompensationCell
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledCompensationCell(void)
+{
+  return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN) == SYSCFG_CCCSR_EN) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Compensation Cell ready Flag
+  * @rmtoll CCCSR   READY   LL_SYSCFG_IsActiveFlag_CMPCR
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CMPCR(void)
+{
+  return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_READY) == (SYSCFG_CCCSR_READY)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the I/O speed optimization when the product voltage is low.
+  * @rmtoll CCCSR   HSLV    LL_SYSCFG_EnableIOSpeedOptimize
+  * @note   This bit is active only if IO_HSLV user option bit is set. It must be used only if the
+  *         product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
+  *         might be destructive.
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimization(void)
+{
+#if defined(SYSCFG_CCCSR_HSLV)
+  SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV);
+#else
+  SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV0);
+#endif   /* SYSCFG_CCCSR_HSLV */
+}
+
+#if defined(SYSCFG_CCCSR_HSLV1)
+/**
+  * @brief  Enable the I/O speed optimization when the product voltage is low.
+  * @rmtoll CCCSR   HSLV1    LL_SYSCFG_EnableIOSpeedOptimize
+  * @note   This bit is active only if IO_HSLV user option bit is set. It must be used only if the
+  *         product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
+  *         might be destructive.
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimization1(void)
+{
+  SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV1);
+}
+
+/**
+  * @brief  Enable the I/O speed optimization when the product voltage is low.
+  * @rmtoll CCCSR   HSLV2    LL_SYSCFG_EnableIOSpeedOptimize
+  * @note   This bit is active only if IO_HSLV user option bit is set. It must be used only if the
+  *         product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
+  *         might be destructive.
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimization2(void)
+{
+  SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV2);
+}
+
+/**
+  * @brief  Enable the I/O speed optimization when the product voltage is low.
+  * @rmtoll CCCSR   HSLV3    LL_SYSCFG_EnableIOSpeedOptimize
+  * @note   This bit is active only if IO_HSLV user option bit is set. It must be used only if the
+  *         product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
+  *         might be destructive.
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimization3(void)
+{
+  SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV3);
+}
+#endif /*SYSCFG_CCCSR_HSLV1*/
+
+
+/**
+  * @brief  To Disable optimize the I/O speed when the product voltage is low.
+  * @rmtoll CCCSR   HSLV    LL_SYSCFG_DisableIOSpeedOptimize
+  * @note   This bit is active only if IO_HSLV user option bit is set. It must be used only if the
+  *         product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
+  *         might be destructive.
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimization(void)
+{
+#if defined(SYSCFG_CCCSR_HSLV)
+  CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV);
+#else
+  CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV0);
+#endif   /* SYSCFG_CCCSR_HSLV */
+}
+
+#if defined(SYSCFG_CCCSR_HSLV1)
+/**
+  * @brief  To Disable optimize the I/O speed when the product voltage is low.
+  * @rmtoll CCCSR   HSLV1    LL_SYSCFG_DisableIOSpeedOptimize
+  * @note   This bit is active only if IO_HSLV user option bit is set. It must be used only if the
+  *         product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
+  *         might be destructive.
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimization1(void)
+{
+  CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV1);
+}
+
+/**
+  * @brief  To Disable optimize the I/O speed when the product voltage is low.
+  * @rmtoll CCCSR   HSLV2    LL_SYSCFG_DisableIOSpeedOptimize
+  * @note   This bit is active only if IO_HSLV user option bit is set. It must be used only if the
+  *         product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
+  *         might be destructive.
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimization2(void)
+{
+  CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV2);
+}
+
+/**
+  * @brief  To Disable optimize the I/O speed when the product voltage is low.
+  * @rmtoll CCCSR   HSLV3    LL_SYSCFG_DisableIOSpeedOptimize
+  * @note   This bit is active only if IO_HSLV user option bit is set. It must be used only if the
+  *         product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
+  *         might be destructive.
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimization3(void)
+{
+  CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV3);
+}
+#endif /*SYSCFG_CCCSR_HSLV1*/
+
+/**
+  * @brief  Check if the I/O speed optimization is enabled
+  * @rmtoll CCCSR   HSLV    LL_SYSCFG_IsEnabledIOSpeedOptimization
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimization(void)
+{
+#if defined(SYSCFG_CCCSR_HSLV)
+  return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV) == SYSCFG_CCCSR_HSLV) ? 1UL : 0UL);
+#else
+  return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV0) == SYSCFG_CCCSR_HSLV0) ? 1UL : 0UL);
+#endif /*SYSCFG_CCCSR_HSLV*/
+}
+
+#if defined(SYSCFG_CCCSR_HSLV1)
+/**
+  * @brief  Check if the I/O speed optimization is enabled
+  * @rmtoll CCCSR   HSLV1    LL_SYSCFG_IsEnabledIOSpeedOptimization
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimization1(void)
+{
+  return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV1) == SYSCFG_CCCSR_HSLV1) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the I/O speed optimization is enabled
+  * @rmtoll CCCSR   HSLV2    LL_SYSCFG_IsEnabledIOSpeedOptimization
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimization2(void)
+{
+  return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV2) == SYSCFG_CCCSR_HSLV2) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the I/O speed optimization is enabled
+  * @rmtoll CCCSR   HSLV3    LL_SYSCFG_IsEnabledIOSpeedOptimization
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimization3(void)
+{
+  return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV3) == SYSCFG_CCCSR_HSLV3) ? 1UL : 0UL);
+}
+#endif /*SYSCFG_CCCSR_HSLV1*/
+
+/**
+  * @brief  Set the code selection for the I/O Compensation cell
+  * @rmtoll CCCSR   CS    LL_SYSCFG_SetCellCompensationCode
+  * @param  CompCode: Selects the code to be applied for the I/O compensation cell
+  *   This parameter can be one of the following values:
+  *   @arg LL_SYSCFG_CELL_CODE : Select Code from the cell (available in the SYSCFG_CCVR)
+  *   @arg LL_SYSCFG_REGISTER_CODE: Select Code from the SYSCFG compensation cell code register (SYSCFG_CCCR)
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_SetCellCompensationCode(uint32_t CompCode)
+{
+  SET_BIT(SYSCFG->CCCSR, CompCode);
+}
+
+/**
+  * @brief  Get the code selected for the I/O Compensation cell
+  * @rmtoll CCCSR   CS    LL_SYSCFG_GetCellCompensationCode
+  * @retval Returned value can be one of the following values:
+  *   @arg LL_SYSCFG_CELL_CODE : Selected Code is from the cell (available in the SYSCFG_CCVR)
+  *   @arg LL_SYSCFG_REGISTER_CODE: Selected Code is from the SYSCFG compensation cell code register (SYSCFG_CCCR)
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetCellCompensationCode(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_CS));
+}
+
+#ifdef SYSCFG_CCCSR_CS_MMC
+
+/**
+  * @brief  Get the code selected for the I/O Compensation cell on the VDDMMC power rail
+  * @rmtoll CCCSR   CS    LL_SYSCFG_GetCellCompensationCode
+  * @retval Returned value can be one of the following values:
+  *   @arg LL_SYSCFG_CELL_CODE : Selected Code is from the cell (available in the SYSCFG_CCVR)
+  *   @arg LL_SYSCFG_REGISTER_CODE: Selected Code is from the SYSCFG compensation cell code register (SYSCFG_CCCR)
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_MMCGetCellCompensationCode(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_CS_MMC));
+}
+#endif /*SYSCFG_CCCSR_CS_MMC*/
+
+/**
+  * @brief  Get I/O compensation cell value for PMOS transistors
+  * @rmtoll CCVR    PCV   LL_SYSCFG_GetPMOSCompensationValue
+  * @retval Returned value is the I/O compensation cell value for PMOS transistors
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSCompensationValue(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_PCV));
+}
+
+/**
+  * @brief  Get I/O compensation cell value for NMOS transistors
+  * @rmtoll CCVR    NCV   LL_SYSCFG_GetNMOSCompensationValue
+  * @retval Returned value is the I/O compensation cell value for NMOS transistors
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSCompensationValue(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_NCV));
+}
+
+/**
+  * @brief  Set I/O compensation cell code for PMOS transistors
+  * @rmtoll CCCR    PCC   LL_SYSCFG_SetPMOSCompensationCode
+  * @param  PMOSCode PMOS compensation code
+  *         This code is applied to the I/O compensation cell when the CS bit of the
+  *         SYSCFG_CMPCR is set
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_SetPMOSCompensationCode(uint32_t PMOSCode)
+{
+  MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_PCC, PMOSCode);
+}
+
+/**
+  * @brief  Get I/O compensation cell code for PMOS transistors
+  * @rmtoll CCCR    PCC   LL_SYSCFG_GetPMOSCompensationCode
+  * @retval Returned value is the I/O compensation cell code for PMOS transistors
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSCompensationCode(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_PCC));
+}
+
+#ifdef SYSCFG_CCCR_PCC_MMC
+
+/**
+  * @brief  Set I/O compensation cell code for PMOS transistors corresponding to the VDDMMC power rail
+  * @rmtoll CCCR    PCC   LL_SYSCFG_SetPMOSCompensationCode
+  * @param  PMOSCode PMOS compensation code
+  *         This code is applied to the I/O compensation cell when the CS bit of the
+  *         SYSCFG_CMPCR is set
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_MMCSetPMOSCompensationCode(uint32_t PMOSCode)
+{
+  MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_PCC_MMC, PMOSCode);
+}
+
+/**
+  * @brief  Get I/O compensation cell code for PMOS transistors corresponding to the VDDMMC power rail
+  * @rmtoll CCCR    PCC   LL_SYSCFG_GetPMOSCompensationCode
+  * @retval Returned value is the I/O compensation cell code for PMOS transistors
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_MMCGetPMOSCompensationCode(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_PCC_MMC));
+}
+#endif /* SYSCFG_CCCR_PCC_MMC */
+
+/**
+  * @brief  Set I/O compensation cell code for NMOS transistors
+  * @rmtoll CCCR    NCC   LL_SYSCFG_SetNMOSCompensationCode
+  * @param  NMOSCode NMOS compensation code
+  *         This code is applied to the I/O compensation cell when the CS bit of the
+  *         SYSCFG_CMPCR is set
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_SetNMOSCompensationCode(uint32_t NMOSCode)
+{
+  MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC, NMOSCode);
+}
+
+/**
+  * @brief  Get I/O compensation cell code for NMOS transistors
+  * @rmtoll CCCR    NCC   LL_SYSCFG_GetNMOSCompensationCode
+  * @retval Returned value is the I/O compensation cell code for NMOS transistors
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSCompensationCode(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_NCC));
+}
+
+#ifdef SYSCFG_CCCR_NCC_MMC
+
+/**
+  * @brief  Set I/O compensation cell code for NMOS transistors on the VDDMMC power rail.
+  * @rmtoll CCCR    NCC   LL_SYSCFG_SetNMOSCompensationCode
+  * @param  NMOSCode: NMOS compensation code
+  *         This code is applied to the I/O compensation cell when the CS bit of the
+  *         SYSCFG_CMPCR is set
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_VDMMCSetNMOSCompensationCode(uint32_t NMOSCode)
+{
+  MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC_MMC, NMOSCode);
+}
+
+/**
+  * @brief  Get I/O compensation cell code for NMOS transistors on the VDDMMC power rail.
+  * @rmtoll CCCR    NCC   LL_SYSCFG_GetNMOSCompensationCode
+  * @retval Returned value is the I/O compensation cell code for NMOS transistors
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_VDMMCGetNMOSCompensationCode(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_NCC_MMC));
+}
+#endif /*SYSCFG_CCCR_NCC_MMC*/
+
+#ifdef SYSCFG_PKGR_PKG
+/**
+  * @brief  Get the device package
+  * @rmtoll PKGR    PKG   LL_SYSCFG_GetPackage
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSCFG_LQFP100_PACKAGE (*)
+  *         @arg @ref LL_SYSCFG_TQFP144_PACKAGE (*)
+  *         @arg @ref LL_SYSCFG_TQFP176_UFBGA176_PACKAGE (*)
+  *         @arg @ref LL_SYSCFG_LQFP208_TFBGA240_PACKAGE (*)
+  *         @arg @ref LL_SYSCFG_VFQFPN68_INDUS_PACKAGE (*)
+  *         @arg @ref LL_SYSCFG_TFBGA100_LQFP100_PACKAGE (*)
+  *         @arg @ref LL_SYSCFG_LQFP100_INDUS_PACKAGE (**)
+  *         @arg @ref LL_SYSCFG_TFBGA100_INDUS_PACKAGE (**)
+  *         @arg @ref LL_SYSCFG_WLCSP115_INDUS_PACKAGE (**)
+  *         @arg @ref LL_SYSCFG_LQFP144_PACKAGE (**)
+  *         @arg @ref LL_SYSCFG_UFBGA144_PACKAGE (**)
+  *         @arg @ref LL_SYSCFG_LQFP144_INDUS_PACKAGE (**)
+  *         @arg @ref LL_SYSCFG_UFBGA169_INDUS_PACKAGE (**)
+  *         @arg @ref LL_SYSCFG_UFBGA176PLUS25_INDUS_PACKAGE (**)
+  *         @arg @ref LL_SYSCFG_LQFP176_INDUS_PACKAGE (**)
+  *
+  * (*) : For stm32h74xxx and stm32h75xxx family lines.
+  * (**): For stm32h72xxx and stm32h73xxx family lines.
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetPackage(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->PKGR, SYSCFG_PKGR_PKG));
+}
+#endif /*SYSCFG_PKGR_PKG*/
+
+#ifdef SYSCFG_UR0_RDP
+/**
+  * @brief  Get the Flash memory protection level
+  * @rmtoll UR0   RDP   LL_SYSCFG_GetFLashProtectionLevel
+  * @retval Returned value can be one of the following values:
+  *         0xAA : RDP level 0
+  *         0xCC : RDP level 2
+  *         Any other value : RDP level 1
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetFLashProtectionLevel(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->UR0, SYSCFG_UR0_RDP));
+}
+#ifdef SYSCFG_UR0_BKS
+/**
+  * @brief  Indicate if the Flash memory bank addresses are inverted or not
+  * @rmtoll UR0   BKS   LL_SYSCFG_IsFLashBankAddressesSwaped
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsFLashBankAddressesSwaped(void)
+{
+  return ((READ_BIT(SYSCFG->UR0, SYSCFG_UR0_BKS) == 0U) ? 1UL : 0UL);
+}
+#endif /*SYSCFG_UR0_BKS*/
+
+/**
+  * @brief  Get the BOR Threshold Reset Level
+  * @rmtoll UR2   BORH    LL_SYSCFG_GetBrownoutResetLevel
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSCFG_BOR_HIGH_RESET_LEVEL
+  *         @arg @ref LL_SYSCFG_BOR_MEDIUM_RESET_LEVEL
+  *         @arg @ref LL_SYSCFG_BOR_LOW_RESET_LEVEL
+  *         @arg @ref LL_SYSCFG_BOR_OFF_RESET_LEVEL
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetBrownoutResetLevel(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->UR2, SYSCFG_UR2_BORH));
+}
+/**
+  * @brief  BootCM7 address 0 configuration
+  * @rmtoll UR2   BOOT_ADD0   LL_SYSCFG_SetCM7BootAddress0
+  * @param  BootAddress :Specifies the CM7 Boot Address to be loaded in Address0
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_SetCM7BootAddress0(uint16_t BootAddress)
+{
+  /* Configure CM7 BOOT ADD0 */
+#if defined(DUAL_CORE)
+  MODIFY_REG(SYSCFG->UR2, SYSCFG_UR2_BCM7_ADD0, ((uint32_t)BootAddress << SYSCFG_UR2_BCM7_ADD0_Pos));
+#else
+  MODIFY_REG(SYSCFG->UR2, SYSCFG_UR2_BOOT_ADD0, ((uint32_t)BootAddress << SYSCFG_UR2_BOOT_ADD0_Pos));
+#endif /*DUAL_CORE*/
+
+}
+
+/**
+  * @brief  Get BootCM7 address 0
+  * @rmtoll UR2   BOOT_ADD0   LL_SYSCFG_GetCM7BootAddress0
+  * @retval Returned the CM7 Boot Address0
+  */
+__STATIC_INLINE uint16_t LL_SYSCFG_GetCM7BootAddress0(void)
+{
+  /* Get CM7 BOOT ADD0 */
+#if defined(DUAL_CORE)
+  return (uint16_t)((uint32_t)READ_BIT(SYSCFG->UR2, SYSCFG_UR2_BCM7_ADD0) >> SYSCFG_UR2_BCM7_ADD0_Pos);
+#else
+  return (uint16_t)((uint32_t)READ_BIT(SYSCFG->UR2, SYSCFG_UR2_BOOT_ADD0) >> SYSCFG_UR2_BOOT_ADD0_Pos);
+#endif /*DUAL_CORE*/
+}
+
+/**
+  * @brief  BootCM7 address 1 configuration
+  * @rmtoll UR3   BOOT_ADD1   LL_SYSCFG_SetCM7BootAddress1
+  * @param  BootAddress :Specifies the CM7 Boot Address to be loaded in Address1
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_SetCM7BootAddress1(uint16_t BootAddress)
+{
+  /* Configure CM7 BOOT ADD1 */
+#if defined(DUAL_CORE)
+  MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BCM7_ADD1, BootAddress);
+#else
+  MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BOOT_ADD1, BootAddress);
+#endif /*DUAL_CORE*/
+}
+
+/**
+  * @brief  Get BootCM7 address 1
+  * @rmtoll UR3   BOOT_ADD1   LL_SYSCFG_GetCM7BootAddress1
+  * @retval Returned the CM7 Boot Address0
+  */
+__STATIC_INLINE uint16_t LL_SYSCFG_GetCM7BootAddress1(void)
+{
+  /* Get CM7 BOOT ADD0 */
+#if defined(DUAL_CORE)
+  return (uint16_t)(READ_BIT(SYSCFG->UR3, SYSCFG_UR3_BCM7_ADD1));
+#else
+  return (uint16_t)(READ_BIT(SYSCFG->UR3, SYSCFG_UR3_BOOT_ADD1));
+#endif /* DUAL_CORE */
+}
+
+#if defined(DUAL_CORE)
+/**
+  * @brief  BootCM4 address 0 configuration
+  * @rmtoll UR3   BCM4_ADD0   LL_SYSCFG_SetCM4BootAddress0
+  * @param  BootAddress :Specifies the CM4 Boot Address to be loaded in Address0
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_SetCM4BootAddress0(uint16_t BootAddress)
+{
+  /* Configure CM4 BOOT ADD0 */
+  MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BCM4_ADD0, ((uint32_t)BootAddress << SYSCFG_UR3_BCM4_ADD0_Pos));
+}
+
+/**
+  * @brief  Get BootCM4 address 0
+  * @rmtoll UR3   BCM4_ADD0   LL_SYSCFG_GetCM4BootAddress0
+  * @retval Returned the CM4 Boot Address0
+  */
+__STATIC_INLINE uint16_t LL_SYSCFG_GetCM4BootAddress0(void)
+{
+  /* Get CM4 BOOT ADD0 */
+  return (uint16_t)((uint32_t)READ_BIT(SYSCFG->UR3, SYSCFG_UR3_BCM4_ADD0) >> SYSCFG_UR3_BCM4_ADD0_Pos);
+}
+
+/**
+  * @brief  BootCM4 address 1 configuration
+  * @rmtoll UR4   BCM4_ADD1   LL_SYSCFG_SetCM4BootAddress1
+  * @param  BootAddress :Specifies the CM4 Boot Address to be loaded in Address1
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_SetCM4BootAddress1(uint16_t BootAddress)
+{
+  /* Configure CM4 BOOT ADD1 */
+  MODIFY_REG(SYSCFG->UR4, SYSCFG_UR4_BCM4_ADD1, BootAddress);
+}
+
+/**
+  * @brief  Get BootCM4 address 1
+  * @rmtoll UR4   BCM4_ADD1   LL_SYSCFG_GetCM4BootAddress1
+  * @retval Returned the CM4 Boot Address0
+  */
+__STATIC_INLINE uint16_t LL_SYSCFG_GetCM4BootAddress1(void)
+{
+  /* Get CM4 BOOT ADD0 */
+  return (uint16_t)(READ_BIT(SYSCFG->UR4, SYSCFG_UR4_BCM4_ADD1));
+}
+#endif /*DUAL_CORE*/
+
+/**
+  * @brief  Indicates if the flash protected area (Bank 1) is erased by a mass erase
+  * @rmtoll UR4   MEPAD_BANK1   LL_SYSCFG_IsFlashB1ProtectedAreaErasable
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1ProtectedAreaErasable(void)
+{
+  return ((READ_BIT(SYSCFG->UR4, SYSCFG_UR4_MEPAD_BANK1) == SYSCFG_UR4_MEPAD_BANK1) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates if the flash secured area (Bank 1) is erased by a mass erase
+  * @rmtoll UR5   MESAD_BANK1   LL_SYSCFG_IsFlashB1SecuredAreaErasable
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1SecuredAreaErasable(void)
+{
+  return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_MESAD_BANK1) == SYSCFG_UR5_MESAD_BANK1) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates if the sector 0 of the Flash memory bank 1 is write protected
+  * @rmtoll UR5   WRPN_BANK1    LL_SYSCFG_IsFlashB1Sector0WriteProtected
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector0WriteProtected(void)
+{
+  return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR0_STATUS_BIT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates if the sector 1 of the Flash memory bank 1 is write protected
+  * @rmtoll UR5   WRPN_BANK1    LL_SYSCFG_IsFlashB1Sector1WriteProtected
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector1WriteProtected(void)
+{
+  return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR1_STATUS_BIT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates if the sector 2 of the Flash memory bank 1 is write protected
+  * @rmtoll UR5   WRPN_BANK1    LL_SYSCFG_IsFlashB1Sector2WriteProtected
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector2WriteProtected(void)
+{
+  return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR2_STATUS_BIT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates if the sector 3 of the Flash memory bank 1 is write protected
+  * @rmtoll UR5   WRPN_BANK1    LL_SYSCFG_IsFlashB1Sector3WriteProtected
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector3WriteProtected(void)
+{
+  return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR3_STATUS_BIT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates if the sector 4 of the Flash memory bank 1 is write protected
+  * @rmtoll UR5   WRPN_BANK1    LL_SYSCFG_IsFlashB1Sector4WriteProtected
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector4WriteProtected(void)
+{
+  return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR4_STATUS_BIT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates if the sector 5 of the Flash memory bank 1 is write protected
+  * @rmtoll UR5   WRPN_BANK1    LL_SYSCFG_IsFlashB1Sector5WriteProtected
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector5WriteProtected(void)
+{
+  return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR5_STATUS_BIT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates if the sector 6 of the Flash memory bank 1 is write protected
+  * @rmtoll UR5   WRPN_BANK1    LL_SYSCFG_IsFlashB1Sector6WriteProtected
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector6WriteProtected(void)
+{
+  return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR6_STATUS_BIT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates if the sector 7 of the Flash memory bank 1 is write protected
+  * @rmtoll UR5   WRPN_BANK1    LL_SYSCFG_IsFlashB1Sector7WriteProtected
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector7WriteProtected(void)
+{
+  return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR7_STATUS_BIT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get the protected area start address for Flash bank 1
+  * @rmtoll UR6   PABEG_BANK1    LL_SYSCFG_GetFlashB1ProtectedAreaStartAddress
+  * @retval Returned the protected area start address for Flash bank 1
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB1ProtectedAreaStartAddress(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->UR6, SYSCFG_UR6_PABEG_BANK1));
+}
+
+/**
+  * @brief  Get the protected area end address for Flash bank 1
+  * @rmtoll UR6   PAEND_BANK1   LL_SYSCFG_GetFlashB1ProtectedAreaEndAddress
+  * @retval Returned the protected area end address for Flash bank 1
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB1ProtectedAreaEndAddress(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->UR6, SYSCFG_UR6_PAEND_BANK1));
+}
+
+/**
+  * @brief  Get the secured area start address for Flash bank 1
+  * @rmtoll UR7   SABEG_BANK1   LL_SYSCFG_GetFlashB1SecuredAreaStartAddress
+  * @retval Returned the secured area start address for Flash bank 1
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB1SecuredAreaStartAddress(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->UR7, SYSCFG_UR7_SABEG_BANK1));
+}
+
+/**
+  * @brief  Get the secured area end address for Flash bank 1
+  * @rmtoll UR7   SAEND_BANK1   LL_SYSCFG_GetFlashB1SecuredAreaEndAddress
+  * @retval Returned the secured area end address for Flash bank 1
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB1SecuredAreaEndAddress(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->UR7, SYSCFG_UR7_SAEND_BANK1));
+}
+
+#ifdef SYSCFG_UR8_MEPAD_BANK2
+/**
+  * @brief  Indicates if the flash protected area (Bank 2) is erased by a mass erase
+  * @rmtoll UR8   MEPAD_BANK2   LL_SYSCFG_IsFlashB2ProtectedAreaErasable
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2ProtectedAreaErasable(void)
+{
+  return ((READ_BIT(SYSCFG->UR8, SYSCFG_UR8_MEPAD_BANK2) == SYSCFG_UR8_MEPAD_BANK2) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates if the flash secured area (Bank 2) is erased by a mass erase
+  * @rmtoll UR8   MESAD_BANK2   LL_SYSCFG_IsFlashB2SecuredAreaErasable
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2SecuredAreaErasable(void)
+{
+  return ((READ_BIT(SYSCFG->UR8, SYSCFG_UR8_MESAD_BANK2) == SYSCFG_UR8_MESAD_BANK2) ? 1UL : 0UL);
+}
+#endif /*SYSCFG_UR8_MEPAD_BANK2*/
+
+#ifdef SYSCFG_UR9_WRPN_BANK2
+/**
+  * @brief  Indicates if the sector 0 of the Flash memory bank 2 is write protected
+  * @rmtoll UR9   WRPN_BANK2    LL_SYSCFG_IsFlashB2Sector0WriteProtected
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector0WriteProtected(void)
+{
+  return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR0_STATUS_BIT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates if the sector 1 of the Flash memory bank 2 is write protected
+  * @rmtoll UR9   WRPN_BANK2    LL_SYSCFG_IsFlashB2Sector1WriteProtected
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector1WriteProtected(void)
+{
+  return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR1_STATUS_BIT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates if the sector 2 of the Flash memory bank 2 is write protected
+  * @rmtoll UR9   WRPN_BANK2    LL_SYSCFG_IsFlashB2Sector2WriteProtected
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector2WriteProtected(void)
+{
+  return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR2_STATUS_BIT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates if the sector 3 of the Flash memory bank 2 is write protected
+  * @rmtoll UR9   WRPN_BANK2    LL_SYSCFG_IsFlashB2Sector3WriteProtected
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector3WriteProtected(void)
+{
+  return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR3_STATUS_BIT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates if the sector 4 of the Flash memory bank 2 is write protected
+  * @rmtoll UR9   WRPN_BANK2    LL_SYSCFG_IsFlashB2Sector4WriteProtected
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector4WriteProtected(void)
+{
+  return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR4_STATUS_BIT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates if the sector 5 of the Flash memory bank 2 is write protected
+  * @rmtoll UR9   WRPN_BANK2    LL_SYSCFG_IsFlashB2Sector5WriteProtected
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector5WriteProtected(void)
+{
+  return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR5_STATUS_BIT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates if the sector 6 of the Flash memory bank 2 is write protected
+  * @rmtoll UR9   WRPN_BANK2    LL_SYSCFG_IsFlashB2Sector6WriteProtected
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector6WriteProtected(void)
+{
+  return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR6_STATUS_BIT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates if the sector 7 of the Flash memory bank 2 is write protected
+  * @rmtoll UR9   WRPN_BANK2    LL_SYSCFG_IsFlashB2Sector7WriteProtected
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector7WriteProtected(void)
+{
+  return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR7_STATUS_BIT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get the protected area start address for Flash bank 2
+  * @rmtoll UR9   PABEG_BANK2   LL_SYSCFG_GetFlashB2ProtectedAreaStartAddress
+  * @retval Returned the protected area start address for Flash bank 2
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB2ProtectedAreaStartAddress(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->UR9, SYSCFG_UR9_PABEG_BANK2));
+}
+#endif /*SYSCFG_UR9_WRPN_BANK2*/
+
+#ifdef SYSCFG_UR10_PAEND_BANK2
+/**
+  * @brief  Get the protected area end address for Flash bank 2
+  * @rmtoll UR10    PAEND_BANK2   LL_SYSCFG_GetFlashB2ProtectedAreaEndAddress
+  * @retval Returned the protected area end address for Flash bank 2
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB2ProtectedAreaEndAddress(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->UR10, SYSCFG_UR10_PAEND_BANK2));
+}
+
+/**
+  * @brief  Get the secured area start address for Flash bank 2
+  * @rmtoll UR10    SABEG_BANK2   LL_SYSCFG_GetFlashB2SecuredAreaStartAddress
+  * @retval Returned the secured area start address for Flash bank 2
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB2SecuredAreaStartAddress(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->UR10, SYSCFG_UR10_SABEG_BANK2));
+}
+#endif /*SYSCFG_UR10_PAEND_BANK2*/
+
+#ifdef SYSCFG_UR11_SAEND_BANK2
+/**
+  * @brief  Get the secured area end address for Flash bank 2
+  * @rmtoll UR11    SAEND_BANK2   LL_SYSCFG_GetFlashB2SecuredAreaEndAddress
+  * @retval Returned the secured area end address for Flash bank 2
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB2SecuredAreaEndAddress(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->UR11, SYSCFG_UR11_SAEND_BANK2));
+}
+#endif /*SYSCFG_UR11_SAEND_BANK2*/
+
+/**
+  * @brief  Get the Independent Watchdog 1 control mode (Software or Hardware)
+  * @rmtoll UR11    IWDG1M    LL_SYSCFG_GetIWDG1ControlMode
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSCFG_IWDG1_SW_CONTROL_MODE
+  *         @arg @ref LL_SYSCFG_IWDG1_HW_CONTROL_MODE
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetIWDG1ControlMode(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->UR11, SYSCFG_UR11_IWDG1M));
+}
+
+#if defined (DUAL_CORE)
+/**
+  * @brief  Get the Independent Watchdog 2 control mode (Software or Hardware)
+  * @rmtoll UR12    IWDG2M    LL_SYSCFG_GetIWDG2ControlMode
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSCFG_IWDG2_SW_CONTROL_MODE
+  *         @arg @ref LL_SYSCFG_IWDG2_HW_CONTROL_MODE
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetIWDG2ControlMode(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->UR12, SYSCFG_UR12_IWDG2M));
+}
+#endif /* DUAL_CORE */
+
+/**
+  * @brief  Indicates the Secure mode status
+  * @rmtoll UR12    SECURE    LL_SYSCFG_IsSecureModeEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsSecureModeEnabled(void)
+{
+  return ((READ_BIT(SYSCFG->UR12, SYSCFG_UR12_SECURE) == SYSCFG_UR12_SECURE) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates if a reset is generated when D1 domain enters DStandby mode
+  * @rmtoll UR13    D1SBRST   LL_SYSCFG_IsD1StandbyGenerateReset
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsD1StandbyGenerateReset(void)
+{
+  return ((READ_BIT(SYSCFG->UR13, SYSCFG_UR13_D1SBRST) == 0U) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get the secured DTCM RAM size
+  * @rmtoll UR13    SDRS    LL_SYSCFG_GetSecuredDTCMSize
+  * @retval Returned value can be one of the following values:
+  *           @arg @ref LL_SYSCFG_DTCM_RAM_SIZE_2KB
+  *           @arg @ref LL_SYSCFG_DTCM_RAM_SIZE_4KB
+  *           @arg @ref LL_SYSCFG_DTCM_RAM_SIZE_8KB
+  *           @arg @ref LL_SYSCFG_DTCM_RAM_SIZE_16KB
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetSecuredDTCMSize(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->UR13, SYSCFG_UR13_SDRS));
+}
+
+/**
+  * @brief  Indicates if a reset is generated when D1 domain enters DStop mode
+  * @rmtoll UR14    D1STPRST    LL_SYSCFG_IsD1StopGenerateReset
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsD1StopGenerateReset(void)
+{
+  return ((READ_BIT(SYSCFG->UR14, SYSCFG_UR14_D1STPRST) == 0U) ? 1UL : 0UL);
+}
+
+#if defined (DUAL_CORE)
+/**
+  * @brief  Indicates if a reset is generated when D2 domain enters DStandby mode
+  * @rmtoll UR14    D2SBRST   LL_SYSCFG_IsD2StandbyGenerateReset
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsD2StandbyGenerateReset(void)
+{
+  return ((READ_BIT(SYSCFG->UR14, SYSCFG_UR14_D2SBRST) == 0U) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates if a reset is generated when D2 domain enters DStop mode
+  * @rmtoll UR15    D2STPRST    LL_SYSCFG_IsD2StopGenerateReset
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsD2StopGenerateReset(void)
+{
+  return ((READ_BIT(SYSCFG->UR15, SYSCFG_UR15_D2STPRST) == 0U) ? 1UL : 0UL);
+}
+#endif /* DUAL_CORE */
+
+/**
+  * @brief  Indicates if the independent watchdog is frozen in Standby mode
+  * @rmtoll UR15    FZIWDGSTB   LL_SYSCFG_IsIWDGFrozenInStandbyMode
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsIWDGFrozenInStandbyMode(void)
+{
+  return ((READ_BIT(SYSCFG->UR15, SYSCFG_UR15_FZIWDGSTB) == 0U) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates if the independent watchdog is frozen in Stop mode
+  * @rmtoll UR16    FZIWDGSTP   LL_SYSCFG_IsIWDGFrozenInStopMode
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsIWDGFrozenInStopMode(void)
+{
+  return ((READ_BIT(SYSCFG->UR16, SYSCFG_UR16_FZIWDGSTP) == 0U) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates if the device private key is programmed
+  * @rmtoll UR16    PKP   LL_SYSCFG_IsPrivateKeyProgrammed
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsPrivateKeyProgrammed(void)
+{
+  return ((READ_BIT(SYSCFG->UR16, SYSCFG_UR16_PKP) == SYSCFG_UR16_PKP) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates if the Product is working on the full voltage range or not
+  * @rmtoll UR17    IOHSLV    LL_SYSCFG_IsActiveFlag_IOHSLV
+  * @note   When the IOHSLV option bit is set the Product is working below 2.7 V.
+  *         When the IOHSLV option bit is reset the Product is working on the
+  *         full voltage range.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_IOHSLV(void)
+{
+  return ((READ_BIT(SYSCFG->UR17, SYSCFG_UR17_IOHSLV) == SYSCFG_UR17_IOHSLV) ? 1UL : 0UL);
+}
+
+#ifdef SYSCFG_UR17_TCM_AXI_CFG
+/**
+  * @brief  Get the size of ITCM-RAM and AXI-SRAM
+  * @rmtoll UR17    TCM_AXI_CFG    LL_SYSCFG_Get_ITCM_AXI_RAM_Size
+  * @retval Returned value can be one of the following values:
+  *           @arg @ref LL_SYSCFG_ITCM_AXI_64KB_320KB
+  *           @arg @ref LL_SYSCFG_ITCM_AXI_128KB_256KB
+  *           @arg @ref LL_SYSCFG_ITCM_AXI_192KB_192KB
+  *           @arg @ref LL_SYSCFG_ITCM_AXI_256KB_128KB
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_Get_ITCM_AXI_RAM_Size(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->UR17, SYSCFG_UR17_TCM_AXI_CFG));
+}
+#endif /*SYSCFG_UR17_TCM_AXI_CFG*/
+
+#ifdef SYSCFG_UR18_CPU_FREQ_BOOST
+/**
+  * @brief  Indicates if the CPU maximum frequency boost is enabled
+  * @rmtoll UR18    CPU_FREQ_BOOST   LL_SYSCFG_IsCpuFreqBoostEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsCpuFreqBoostEnabled(void)
+{
+  return ((READ_BIT(SYSCFG->UR18, SYSCFG_UR18_CPU_FREQ_BOOST) == SYSCFG_UR18_CPU_FREQ_BOOST) ? 1UL : 0UL);
+}
+#endif /*SYSCFG_UR18_CPU_FREQ_BOOST*/
+
+#endif /*SYSCFG_UR0_RDP*/
+
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
+  * @{
+  */
+
+/**
+  * @brief  Return the device identifier
+  * @rmtoll DBGMCU_IDCODE DEV_ID        LL_DBGMCU_GetDeviceID
+  * @retval Values between Min_Data=0x00 and Max_Data=0xFFF
+  */
+__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
+{
+  return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
+}
+
+/**
+  * @brief  Return the device revision identifier
+  * @note This field indicates the revision of the device.
+          For example, it is read as RevA -> 0x1000, Cat 2 revZ -> 0x1001
+  * @rmtoll DBGMCU_IDCODE REV_ID        LL_DBGMCU_GetRevisionID
+  * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
+  */
+__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
+{
+  return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
+}
+
+/**
+  * @brief  Enable D1 Domain/CDomain debug during SLEEP mode
+  * @rmtoll DBGMCU_CR    DBGSLEEP_D1/DBGSLEEP_CD     LL_DBGMCU_EnableD1DebugInSleepMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_EnableD1DebugInSleepMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1);
+}
+
+/**
+  * @brief  Disable D1 Domain/CDomain debug during SLEEP mode
+  * @rmtoll DBGMCU_CR    DBGSLEEP_D1/DBGSLEEP_CD     LL_DBGMCU_DisableD1DebugInSleepMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_DisableD1DebugInSleepMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1);
+}
+
+/**
+  * @brief  Enable D1 Domain/CDomain debug during STOP mode
+  * @rmtoll DBGMCU_CR    DBGSTOP_D1/DBGSLEEP_CD     LL_DBGMCU_EnableD1DebugInStopMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_EnableD1DebugInStopMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD1);
+}
+
+/**
+  * @brief  Disable D1 Domain/CDomain debug during STOP mode
+  * @rmtoll DBGMCU_CR    DBGSTOP_D1/DBGSLEEP_CD     LL_DBGMCU_DisableD1DebugInStopMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_DisableD1DebugInStopMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD1);
+}
+
+/**
+  * @brief  Enable D1 Domain/CDomain debug during STANDBY mode
+  * @rmtoll DBGMCU_CR    DBGSTBY_D1/DBGSLEEP_CD     LL_DBGMCU_EnableD1DebugInStandbyMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_EnableD1DebugInStandbyMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD1);
+}
+
+/**
+  * @brief  Disable D1 Domain/CDomain debug during STANDBY mode
+  * @rmtoll DBGMCU_CR    DBGSTBY_D1/DBGSLEEP_CD     LL_DBGMCU_DisableD1DebugInStandbyMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_DisableD1DebugInStandbyMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD1);
+}
+
+#if defined (DUAL_CORE)
+/**
+  * @brief  Enable D2 Domain debug during SLEEP mode
+  * @rmtoll DBGMCU_CR    DBGSLEEP_D2     LL_DBGMCU_EnableD2DebugInSleepMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_EnableD2DebugInSleepMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD2);
+}
+
+/**
+  * @brief  Disable D2 Domain debug during SLEEP mode
+  * @rmtoll DBGMCU_CR    DBGSLEEP_D2     LL_DBGMCU_DisableD2DebugInSleepMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_DisableD2DebugInSleepMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD2);
+}
+
+/**
+  * @brief  Enable D2 Domain debug during STOP mode
+  * @rmtoll DBGMCU_CR    DBGSTOP_D2     LL_DBGMCU_EnableD2DebugInStopMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_EnableD2DebugInStopMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD2);
+}
+
+/**
+  * @brief  Disable D2 Domain debug during STOP mode
+  * @rmtoll DBGMCU_CR    DBGSTOP_D2     LL_DBGMCU_DisableD2DebugInStopMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_DisableD2DebugInStopMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD2);
+}
+
+/**
+  * @brief  Enable D2 Domain debug during STANDBY mode
+  * @rmtoll DBGMCU_CR    DBGSTBY_D2     LL_DBGMCU_EnableD2DebugInStandbyMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_EnableD2DebugInStandbyMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD2);
+}
+
+/**
+  * @brief  Disable D2 Domain debug during STANDBY mode
+  * @rmtoll DBGMCU_CR    DBGSTBY_D2     LL_DBGMCU_DisableD2DebugInStandbyMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_DisableD2DebugInStandbyMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD2);
+}
+#endif /* DUAL_CORE */
+
+
+#if defined(DBGMCU_CR_DBG_STOPD3)
+/**
+  * @brief  Enable D3 Domain/SRDomain debug during STOP mode
+  * @rmtoll DBGMCU_CR    DBGSTOP_D3/DBGSTOP_SRD    LL_DBGMCU_EnableD3DebugInStopMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_EnableD3DebugInStopMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD3);
+}
+
+/**
+  * @brief  Disable D3 Domain/SRDomain debug during STOP mode
+  * @rmtoll DBGMCU_CR    DBGSTOP_D3/DBGSTOP_SRD     LL_DBGMCU_DisableD3DebugInStopMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_DisableD3DebugInStopMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD3);
+}
+#endif /*DBGMCU_CR_DBG_STOPD3*/
+
+#if defined(DBGMCU_CR_DBG_STANDBYD3)
+/**
+  * @brief  Enable D3 Domain/SRDomain debug during STANDBY mode
+  * @rmtoll DBGMCU_CR    DBGSTBY_D3/DBGSTBY_SRD     LL_DBGMCU_EnableD3DebugInStandbyMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_EnableD3DebugInStandbyMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD3);
+}
+
+/**
+  * @brief  Disable D3 Domain/SRDomain debug during STANDBY mode
+  * @rmtoll DBGMCU_CR    DBGSTBY_D3/DBGSTBY_SRD     LL_DBGMCU_DisableD3DebugInStandbyMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_DisableD3DebugInStandbyMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD3);
+}
+#endif /*DBGMCU_CR_DBG_STANDBYD3*/
+
+/**
+  * @brief  Enable the trace port clock
+  * @rmtoll DBGMCU_CR    TRACECKEN     LL_DBGMCU_EnableTracePortClock
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_EnableTracePortClock(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TRACECKEN);
+}
+
+/**
+  * @brief  Disable the trace port clock
+  * @rmtoll DBGMCU_CR    TRACECKEN     LL_DBGMCU_DisableTracePortClock
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_DisableTracePortClock(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TRACECKEN);
+}
+
+/**
+  * @brief  Enable the Domain1/CDomain debug clock enable
+  * @rmtoll DBGMCU_CR    CKD1EN/CKCDEN     LL_DBGMCU_EnableD1DebugClock
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_EnableD1DebugClock(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CKD1EN);
+}
+
+/**
+  * @brief  Disable the Domain1/CDomain debug clock enable
+  * @rmtoll DBGMCU_CR    CKD1EN/CKCDEN     LL_DBGMCU_DisableD1DebugClock
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_DisableD1DebugClock(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CKD1EN);
+}
+
+/**
+  * @brief  Enable the Domain3/SRDomain debug clock enable
+  * @rmtoll DBGMCU_CR    CKD3EN/CKSRDEN     LL_DBGMCU_EnableD3DebugClock
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_EnableD3DebugClock(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CKD3EN);
+}
+
+/**
+  * @brief  Disable the Domain3/SRDomain debug clock enable
+  * @rmtoll DBGMCU_CR    CKD3EN/CKSRDEN    LL_DBGMCU_DisableD3DebugClock
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_DisableD3DebugClock(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CKD3EN);
+}
+
+#define LL_DBGMCU_TRGIO_INPUT_DIRECTION   0U
+#define LL_DBGMCU_TRGIO_OUTPUT_DIRECTION  DBGMCU_CR_DBG_TRGOEN
+/**
+  * @brief  Set the direction of the bi-directional trigger pin TRGIO
+  * @rmtoll DBGMCU_CR    TRGOEN    LL_DBGMCU_SetExternalTriggerPinDirection\n
+  * @param  PinDirection This parameter can be one of the following values:
+  *         @arg @ref LL_DBGMCU_TRGIO_INPUT_DIRECTION
+  *         @arg @ref LL_DBGMCU_TRGIO_OUTPUT_DIRECTION
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_SetExternalTriggerPinDirection(uint32_t PinDirection)
+{
+  MODIFY_REG(DBGMCU->CR, DBGMCU_CR_DBG_TRGOEN, PinDirection);
+}
+
+/**
+  * @brief  Get the direction of the bi-directional trigger pin TRGIO
+  * @rmtoll DBGMCU_CR    TRGOEN    LL_DBGMCU_GetExternalTriggerPinDirection\n
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DBGMCU_TRGIO_INPUT_DIRECTION
+  *         @arg @ref LL_DBGMCU_TRGIO_OUTPUT_DIRECTION
+  */
+__STATIC_INLINE uint32_t LL_DBGMCU_GetExternalTriggerPinDirection(void)
+{
+  return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TRGOEN));
+}
+
+/**
+  * @brief  Freeze APB1 group1 peripherals
+  * @rmtoll DBGMCU_APB1LFZ1   TIM2      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1LFZ1   TIM3      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1LFZ1   TIM4      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1LFZ1   TIM5      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1LFZ1   TIM6      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1LFZ1   TIM7      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1LFZ1   TIM12     LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1LFZ1   TIM13     LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1LFZ1   TIM14     LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1LFZ1   LPTIM1    LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1LFZ1   I2C1      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1LFZ1   I2C2      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1LFZ1   I2C3      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1LFZ1   I2C5      LL_DBGMCU_APB1_GRP1_FreezePeriph\n (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C5_STOP (*)
+  *
+  *         (*) value not defined in all devices
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
+{
+  SET_BIT(DBGMCU->APB1LFZ1, Periphs);
+}
+
+/**
+  * @brief  Unfreeze APB1 peripherals (group1 peripherals)
+  * @rmtoll DBGMCU_APB1LFZ1   TIM2      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1LFZ1   TIM3      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1LFZ1   TIM4      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1LFZ1   TIM5      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1LFZ1   TIM6      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1LFZ1   TIM7      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1LFZ1   TIM12     LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1LFZ1   TIM13     LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1LFZ1   TIM14     LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1LFZ1   LPTIM1    LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1LFZ1   I2C1      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1LFZ1   I2C2      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1LFZ1   I2C3      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1LFZ1   I2C5      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C5_STOP (*)
+  *
+  *         (*) value not defined in all devices
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
+{
+  CLEAR_BIT(DBGMCU->APB1LFZ1, Periphs);
+}
+
+#ifdef DBGMCU_APB1HFZ1_DBG_FDCAN
+/**
+  * @brief  Freeze APB1 group2 peripherals
+  * @rmtoll DBGMCU_APB1HFZ1   FDCAN   LL_DBGMCU_APB1_GRP2_FreezePeriph\n
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBGMCU_APB1_GRP2_FDCAN_STOP
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)
+{
+  SET_BIT(DBGMCU->APB1HFZ1, Periphs);
+}
+
+/**
+  * @brief  Unfreeze APB1 group2 peripherals
+  * @rmtoll DBGMCU_APB1HFZ1   FDCAN   LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBGMCU_APB1_GRP2_FDCAN_STOP
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)
+{
+  CLEAR_BIT(DBGMCU->APB1HFZ1, Periphs);
+}
+#endif /*DBGMCU_APB1HFZ1_DBG_FDCAN*/
+
+#if defined(TIM23) || defined(TIM24)
+/**
+  * @brief  Freeze APB1 group2 peripherals
+  * @rmtoll DBGMCU_APB1HFZ1   TIM23   LL_DBGMCU_APB1_GRP2_FreezePeriph\n
+  *         DBGMCU_APB1HFZ1   TIM24   LL_DBGMCU_APB1_GRP2_FreezePeriph\n
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBGMCU_APB1_GRP2_TIM23_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP2_TIM24_STOP
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)
+{
+  SET_BIT(DBGMCU->APB1HFZ1, Periphs);
+}
+
+/**
+  * @brief  Unfreeze APB1 group2 peripherals
+  * @rmtoll DBGMCU_APB1HFZ1   TIM23   LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n
+            DBGMCU_APB1HFZ1   TIM24   LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBGMCU_APB1_GRP2_TIM23_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP2_TIM24_STOP
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)
+{
+  CLEAR_BIT(DBGMCU->APB1HFZ1, Periphs);
+}
+#endif /* TIM23 || TIM24 */
+
+/**
+  * @brief  Freeze APB2 peripherals
+  * @rmtoll DBGMCU_APB2FZ1    TIM1     LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+  *         DBGMCU_APB2FZ1    TIM8     LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+  *         DBGMCU_APB2FZ1    TIM15    LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+  *         DBGMCU_APB2FZ1    TIM16    LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+  *         DBGMCU_APB2FZ1    TIM17    LL_DBGMCU_APB2_GRP1_FreezePeriph
+  *         DBGMCU_APB2FZ1    HRTIM    LL_DBGMCU_APB2_GRP1_FreezePeriph
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_HRTIM_STOP (*)
+  *
+  *         (*) value not defined in all devices
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
+{
+  SET_BIT(DBGMCU->APB2FZ1, Periphs);
+}
+
+/**
+  * @brief  Unfreeze APB2 peripherals
+  * @rmtoll DBGMCU_APB2FZ1    TIM1     LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+  *         DBGMCU_APB2FZ1    TIM8     LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+  *         DBGMCU_APB2FZ1    TIM15    LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+  *         DBGMCU_APB2FZ1    TIM16    LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+  *         DBGMCU_APB2FZ1    TIM17    LL_DBGMCU_APB2_GRP1_FreezePeriph
+  *         DBGMCU_APB2FZ1    HRTIM    LL_DBGMCU_APB2_GRP1_FreezePeriph
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_HRTIM_STOP (*)
+  *
+  *         (*) value not defined in all devices
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
+{
+  CLEAR_BIT(DBGMCU->APB2FZ1, Periphs);
+}
+
+/**
+  * @brief  Freeze APB3 peripherals
+  * @rmtoll DBGMCU_APB3FZ1    WWDG1     LL_DBGMCU_APB3_GRP1_FreezePeriph\n
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBGMCU_APB3_GRP1_WWDG1_STOP
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_APB3_GRP1_FreezePeriph(uint32_t Periphs)
+{
+  SET_BIT(DBGMCU->APB3FZ1, Periphs);
+}
+
+/**
+  * @brief  Unfreeze APB3 peripherals
+  * @rmtoll DBGMCU_APB3FZ1    WWDG1     LL_DBGMCU_APB3_GRP1_UnFreezePeriph\n
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBGMCU_APB3_GRP1_WWDG1_STOP
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_APB3_GRP1_UnFreezePeriph(uint32_t Periphs)
+{
+  CLEAR_BIT(DBGMCU->APB3FZ1, Periphs);
+}
+
+/**
+  * @brief  Freeze APB4 peripherals
+  * @rmtoll DBGMCU_APB4FZ1    I2C4      LL_DBGMCU_APB4_GRP1_FreezePeriph\n
+  * @rmtoll DBGMCU_APB4FZ1    LPTIM2    LL_DBGMCU_APB4_GRP1_FreezePeriph\n
+  * @rmtoll DBGMCU_APB4FZ1    LPTIM3    LL_DBGMCU_APB4_GRP1_FreezePeriph\n
+  * @rmtoll DBGMCU_APB4FZ1    LPTIM4    LL_DBGMCU_APB4_GRP1_FreezePeriph\n
+  * @rmtoll DBGMCU_APB4FZ1    LPTIM5    LL_DBGMCU_APB4_GRP1_FreezePeriph\n
+  * @rmtoll DBGMCU_APB4FZ1    RTC       LL_DBGMCU_APB4_GRP1_FreezePeriph\n
+  * @rmtoll DBGMCU_APB4FZ1    WDGLSD1   LL_DBGMCU_APB4_GRP1_FreezePeriph\n
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBGMCU_APB4_GRP1_I2C4_STOP
+  *         @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM2_STOP
+  *         @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM3_STOP
+  *         @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM4_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM5_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB4_GRP1_RTC_STOP
+  *         @arg @ref LL_DBGMCU_APB4_GRP1_IWDG1_STOP
+  *
+  *         (*) value not defined in all devices
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_APB4_GRP1_FreezePeriph(uint32_t Periphs)
+{
+  SET_BIT(DBGMCU->APB4FZ1, Periphs);
+}
+
+/**
+  * @brief  Unfreeze APB4 peripherals
+  * @rmtoll DBGMCU_APB4FZ1    I2C4      LL_DBGMCU_APB4_GRP1_FreezePeriph\n
+  * @rmtoll DBGMCU_APB4FZ1    LPTIM2    LL_DBGMCU_APB4_GRP1_FreezePeriph\n
+  * @rmtoll DBGMCU_APB4FZ1    LPTIM3    LL_DBGMCU_APB4_GRP1_FreezePeriph\n
+  * @rmtoll DBGMCU_APB4FZ1    LPTIM4    LL_DBGMCU_APB4_GRP1_FreezePeriph\n
+  * @rmtoll DBGMCU_APB4FZ1    LPTIM5    LL_DBGMCU_APB4_GRP1_FreezePeriph\n
+  * @rmtoll DBGMCU_APB4FZ1    RTC       LL_DBGMCU_APB4_GRP1_FreezePeriph\n
+  * @rmtoll DBGMCU_APB4FZ1    WDGLSD1   LL_DBGMCU_APB4_GRP1_FreezePeriph\n
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBGMCU_APB4_GRP1_I2C4_STOP
+  *         @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM2_STOP
+  *         @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM3_STOP
+  *         @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM4_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM5_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB4_GRP1_RTC_STOP
+  *         @arg @ref LL_DBGMCU_APB4_GRP1_IWDG1_STOP
+  *
+  *         (*) value not defined in all devices
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_APB4_GRP1_UnFreezePeriph(uint32_t Periphs)
+{
+  CLEAR_BIT(DBGMCU->APB4FZ1, Periphs);
+}
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EF_FLASH FLASH
+  * @{
+  */
+
+/**
+  * @brief  Set FLASH Latency
+  * @rmtoll FLASH_ACR    LATENCY       LL_FLASH_SetLatency
+  * @param  Latency This parameter can be one of the following values:
+  *         @arg @ref LL_FLASH_LATENCY_0
+  *         @arg @ref LL_FLASH_LATENCY_1
+  *         @arg @ref LL_FLASH_LATENCY_2
+  *         @arg @ref LL_FLASH_LATENCY_3
+  *         @arg @ref LL_FLASH_LATENCY_4
+  *         @arg @ref LL_FLASH_LATENCY_5
+  *         @arg @ref LL_FLASH_LATENCY_6
+  *         @arg @ref LL_FLASH_LATENCY_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
+{
+  MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
+}
+
+/**
+  * @brief  Get FLASH Latency
+  * @rmtoll FLASH_ACR    LATENCY       LL_FLASH_GetLatency
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_FLASH_LATENCY_0
+  *         @arg @ref LL_FLASH_LATENCY_1
+  *         @arg @ref LL_FLASH_LATENCY_2
+  *         @arg @ref LL_FLASH_LATENCY_3
+  *         @arg @ref LL_FLASH_LATENCY_4
+  *         @arg @ref LL_FLASH_LATENCY_5
+  *         @arg @ref LL_FLASH_LATENCY_6
+  *         @arg @ref LL_FLASH_LATENCY_7
+  */
+__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
+{
+  return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
+}
+
+/**
+  * @}
+  */
+
+#if defined(DUAL_CORE)
+/** @defgroup SYSTEM_LL_EF_ART ART
+  * @{
+  */
+
+/**
+  * @brief  Enable the Cortex-M4 ART cache.
+  * @rmtoll ART_CTR    EN   LL_ART_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_ART_Enable(void)
+{
+ SET_BIT(ART->CTR, ART_CTR_EN);
+}
+
+/**
+  * @brief  Disable the Cortex-M4 ART cache.
+  * @rmtoll ART_CTR    EN   LL_ART_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_ART_Disable(void)
+{
+ CLEAR_BIT(ART->CTR, ART_CTR_EN);
+}
+
+/**
+  * @brief  Check if the Cortex-M4 ART cache is enabled
+  * @rmtoll ART_CTR   EN    LL_ART_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ART_IsEnabled(void)
+{
+  return ((READ_BIT(ART->CTR, ART_CTR_EN) == ART_CTR_EN) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the Cortex-M4 ART cache Base Address.
+  * @rmtoll ART_CTR    PCACHEADDR   LL_ART_SetBaseAddress
+  * @param  BaseAddress Specifies the Base address of 1 Mbyte address page (cacheable page)
+            from which the ART accelerator loads code to the cache.
+  * @retval None
+  */
+__STATIC_INLINE void LL_ART_SetBaseAddress(uint32_t BaseAddress)
+{
+ MODIFY_REG(ART->CTR, ART_CTR_PCACHEADDR, (((BaseAddress) >> 12U) & 0x000FFF00UL));
+}
+
+/**
+  * @brief  Get the Cortex-M4 ART cache Base Address.
+  * @rmtoll ART_CTR    PCACHEADDR   LL_ART_GetBaseAddress
+  * @retval the Base address of 1 Mbyte address page (cacheable page)
+            from which the ART accelerator loads code to the cache
+  */
+__STATIC_INLINE uint32_t LL_ART_GetBaseAddress(void)
+{
+  return (uint32_t)(READ_BIT(ART->CTR, ART_CTR_PCACHEADDR) << 12U);
+}
+#endif /* DUAL_CORE */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32H7xx_LL_SYSTEM_H */
+
diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_tim.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_tim.h
index dfb4ac48..b340a43f 100644
--- a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_tim.h
+++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_tim.h
@@ -1,5213 +1,5213 @@
-/**
-  ******************************************************************************
-  * @file    stm32h7xx_ll_tim.h
-  * @author  MCD Application Team
-  * @brief   Header file of TIM LL module.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_LL_TIM_H
-#define __STM32H7xx_LL_TIM_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx.h"
-
-/** @addtogroup STM32H7xx_LL_Driver
-  * @{
-  */
-
-#if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM23) || defined (TIM24)
-
-/** @defgroup TIM_LL TIM
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup TIM_LL_Private_Variables TIM Private Variables
-  * @{
-  */
-static const uint8_t OFFSET_TAB_CCMRx[] =
-{
-  0x00U,   /* 0: TIMx_CH1  */
-  0x00U,   /* 1: TIMx_CH1N */
-  0x00U,   /* 2: TIMx_CH2  */
-  0x00U,   /* 3: TIMx_CH2N */
-  0x04U,   /* 4: TIMx_CH3  */
-  0x04U,   /* 5: TIMx_CH3N */
-  0x04U,   /* 6: TIMx_CH4  */
-  0x3CU,   /* 7: TIMx_CH5  */
-  0x3CU    /* 8: TIMx_CH6  */
-};
-
-static const uint8_t SHIFT_TAB_OCxx[] =
-{
-  0U,            /* 0: OC1M, OC1FE, OC1PE */
-  0U,            /* 1: - NA */
-  8U,            /* 2: OC2M, OC2FE, OC2PE */
-  0U,            /* 3: - NA */
-  0U,            /* 4: OC3M, OC3FE, OC3PE */
-  0U,            /* 5: - NA */
-  8U,            /* 6: OC4M, OC4FE, OC4PE */
-  0U,            /* 7: OC5M, OC5FE, OC5PE */
-  8U             /* 8: OC6M, OC6FE, OC6PE */
-};
-
-static const uint8_t SHIFT_TAB_ICxx[] =
-{
-  0U,            /* 0: CC1S, IC1PSC, IC1F */
-  0U,            /* 1: - NA */
-  8U,            /* 2: CC2S, IC2PSC, IC2F */
-  0U,            /* 3: - NA */
-  0U,            /* 4: CC3S, IC3PSC, IC3F */
-  0U,            /* 5: - NA */
-  8U,            /* 6: CC4S, IC4PSC, IC4F */
-  0U,            /* 7: - NA */
-  0U             /* 8: - NA */
-};
-
-static const uint8_t SHIFT_TAB_CCxP[] =
-{
-  0U,            /* 0: CC1P */
-  2U,            /* 1: CC1NP */
-  4U,            /* 2: CC2P */
-  6U,            /* 3: CC2NP */
-  8U,            /* 4: CC3P */
-  10U,           /* 5: CC3NP */
-  12U,           /* 6: CC4P */
-  16U,           /* 7: CC5P */
-  20U            /* 8: CC6P */
-};
-
-static const uint8_t SHIFT_TAB_OISx[] =
-{
-  0U,            /* 0: OIS1 */
-  1U,            /* 1: OIS1N */
-  2U,            /* 2: OIS2 */
-  3U,            /* 3: OIS2N */
-  4U,            /* 4: OIS3 */
-  5U,            /* 5: OIS3N */
-  6U,            /* 6: OIS4 */
-  8U,            /* 7: OIS5 */
-  10U            /* 8: OIS6 */
-};
-/**
-  * @}
-  */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup TIM_LL_Private_Constants TIM Private Constants
-  * @{
-  */
-
-#if   defined(TIM_BREAK_INPUT_SUPPORT)
-/* Defines used for the bit position in the register and perform offsets */
-#define TIM_POSITION_BRK_SOURCE            (POSITION_VAL(Source) & 0x1FUL)
-
-/* Generic bit definitions for TIMx_AF1 register */
-#define TIMx_AF1_BKINP     TIM1_AF1_BKINP     /*!< BRK BKIN input polarity */
-#define TIMx_AF1_ETRSEL    TIM1_AF1_ETRSEL    /*!< TIMx ETR source selection */
-#endif /* TIM_BREAK_INPUT_SUPPORT */
-
-
-/* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
-#define DT_DELAY_1 ((uint8_t)0x7F)
-#define DT_DELAY_2 ((uint8_t)0x3F)
-#define DT_DELAY_3 ((uint8_t)0x1F)
-#define DT_DELAY_4 ((uint8_t)0x1F)
-
-/* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
-#define DT_RANGE_1 ((uint8_t)0x00)
-#define DT_RANGE_2 ((uint8_t)0x80)
-#define DT_RANGE_3 ((uint8_t)0xC0)
-#define DT_RANGE_4 ((uint8_t)0xE0)
-
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup TIM_LL_Private_Macros TIM Private Macros
-  * @{
-  */
-/** @brief  Convert channel id into channel index.
-  * @param  __CHANNEL__ This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH1N
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH2N
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH3N
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  *         @arg @ref LL_TIM_CHANNEL_CH5
-  *         @arg @ref LL_TIM_CHANNEL_CH6
-  * @retval none
-  */
-#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
-  (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
-   ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
-   ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
-   ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
-   ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
-   ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
-   ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
-   ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U)
-
-/** @brief  Calculate the deadtime sampling period(in ps).
-  * @param  __TIMCLK__ timer input clock frequency (in Hz).
-  * @param  __CKD__ This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
-  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
-  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
-  * @retval none
-  */
-#define TIM_CALC_DTS(__TIMCLK__, __CKD__)                                                        \
-  (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__))         : \
-   ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
-   ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
-/**
-  * @}
-  */
-
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
-  * @{
-  */
-
-/**
-  * @brief  TIM Time Base configuration structure definition.
-  */
-typedef struct
-{
-  uint16_t Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
-                                   This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
-
-                                   This feature can be modified afterwards using unitary function
-                                   @ref LL_TIM_SetPrescaler().*/
-
-  uint32_t CounterMode;       /*!< Specifies the counter mode.
-                                   This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
-
-                                   This feature can be modified afterwards using unitary function
-                                   @ref LL_TIM_SetCounterMode().*/
-
-  uint32_t Autoreload;        /*!< Specifies the auto reload value to be loaded into the active
-                                   Auto-Reload Register at the next update event.
-                                   This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
-                                   Some timer instances may support 32 bits counters. In that case this parameter must
-                                   be a number between 0x0000 and 0xFFFFFFFF.
-
-                                   This feature can be modified afterwards using unitary function
-                                   @ref LL_TIM_SetAutoReload().*/
-
-  uint32_t ClockDivision;     /*!< Specifies the clock division.
-                                   This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
-
-                                   This feature can be modified afterwards using unitary function
-                                   @ref LL_TIM_SetClockDivision().*/
-
-  uint32_t RepetitionCounter;  /*!< Specifies the repetition counter value. Each time the RCR downcounter
-                                   reaches zero, an update event is generated and counting restarts
-                                   from the RCR value (N).
-                                   This means in PWM mode that (N+1) corresponds to:
-                                      - the number of PWM periods in edge-aligned mode
-                                      - the number of half PWM period in center-aligned mode
-                                   GP timers: this parameter must be a number between Min_Data = 0x00 and
-                                   Max_Data = 0xFF.
-                                   Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
-                                   Max_Data = 0xFFFF.
-
-                                   This feature can be modified afterwards using unitary function
-                                   @ref LL_TIM_SetRepetitionCounter().*/
-} LL_TIM_InitTypeDef;
-
-/**
-  * @brief  TIM Output Compare configuration structure definition.
-  */
-typedef struct
-{
-  uint32_t OCMode;        /*!< Specifies the output mode.
-                               This parameter can be a value of @ref TIM_LL_EC_OCMODE.
-
-                               This feature can be modified afterwards using unitary function
-                               @ref LL_TIM_OC_SetMode().*/
-
-  uint32_t OCState;       /*!< Specifies the TIM Output Compare state.
-                               This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
-
-                               This feature can be modified afterwards using unitary functions
-                               @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
-
-  uint32_t OCNState;      /*!< Specifies the TIM complementary Output Compare state.
-                               This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
-
-                               This feature can be modified afterwards using unitary functions
-                               @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
-
-  uint32_t CompareValue;  /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
-                               This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
-
-                               This feature can be modified afterwards using unitary function
-                               LL_TIM_OC_SetCompareCHx (x=1..6).*/
-
-  uint32_t OCPolarity;    /*!< Specifies the output polarity.
-                               This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
-
-                               This feature can be modified afterwards using unitary function
-                               @ref LL_TIM_OC_SetPolarity().*/
-
-  uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
-                               This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
-
-                               This feature can be modified afterwards using unitary function
-                               @ref LL_TIM_OC_SetPolarity().*/
-
-
-  uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
-                               This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
-
-                               This feature can be modified afterwards using unitary function
-                               @ref LL_TIM_OC_SetIdleState().*/
-
-  uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
-                               This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
-
-                               This feature can be modified afterwards using unitary function
-                               @ref LL_TIM_OC_SetIdleState().*/
-} LL_TIM_OC_InitTypeDef;
-
-/**
-  * @brief  TIM Input Capture configuration structure definition.
-  */
-
-typedef struct
-{
-
-  uint32_t ICPolarity;    /*!< Specifies the active edge of the input signal.
-                               This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
-
-                               This feature can be modified afterwards using unitary function
-                               @ref LL_TIM_IC_SetPolarity().*/
-
-  uint32_t ICActiveInput; /*!< Specifies the input.
-                               This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
-
-                               This feature can be modified afterwards using unitary function
-                               @ref LL_TIM_IC_SetActiveInput().*/
-
-  uint32_t ICPrescaler;   /*!< Specifies the Input Capture Prescaler.
-                               This parameter can be a value of @ref TIM_LL_EC_ICPSC.
-
-                               This feature can be modified afterwards using unitary function
-                               @ref LL_TIM_IC_SetPrescaler().*/
-
-  uint32_t ICFilter;      /*!< Specifies the input capture filter.
-                               This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
-
-                               This feature can be modified afterwards using unitary function
-                               @ref LL_TIM_IC_SetFilter().*/
-} LL_TIM_IC_InitTypeDef;
-
-
-/**
-  * @brief  TIM Encoder interface configuration structure definition.
-  */
-typedef struct
-{
-  uint32_t EncoderMode;     /*!< Specifies the encoder resolution (x2 or x4).
-                                 This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
-
-                                 This feature can be modified afterwards using unitary function
-                                 @ref LL_TIM_SetEncoderMode().*/
-
-  uint32_t IC1Polarity;     /*!< Specifies the active edge of TI1 input.
-                                 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
-
-                                 This feature can be modified afterwards using unitary function
-                                 @ref LL_TIM_IC_SetPolarity().*/
-
-  uint32_t IC1ActiveInput;  /*!< Specifies the TI1 input source
-                                 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
-
-                                 This feature can be modified afterwards using unitary function
-                                 @ref LL_TIM_IC_SetActiveInput().*/
-
-  uint32_t IC1Prescaler;    /*!< Specifies the TI1 input prescaler value.
-                                 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
-
-                                 This feature can be modified afterwards using unitary function
-                                 @ref LL_TIM_IC_SetPrescaler().*/
-
-  uint32_t IC1Filter;       /*!< Specifies the TI1 input filter.
-                                 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
-
-                                 This feature can be modified afterwards using unitary function
-                                 @ref LL_TIM_IC_SetFilter().*/
-
-  uint32_t IC2Polarity;      /*!< Specifies the active edge of TI2 input.
-                                 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
-
-                                 This feature can be modified afterwards using unitary function
-                                 @ref LL_TIM_IC_SetPolarity().*/
-
-  uint32_t IC2ActiveInput;  /*!< Specifies the TI2 input source
-                                 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
-
-                                 This feature can be modified afterwards using unitary function
-                                 @ref LL_TIM_IC_SetActiveInput().*/
-
-  uint32_t IC2Prescaler;    /*!< Specifies the TI2 input prescaler value.
-                                 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
-
-                                 This feature can be modified afterwards using unitary function
-                                 @ref LL_TIM_IC_SetPrescaler().*/
-
-  uint32_t IC2Filter;       /*!< Specifies the TI2 input filter.
-                                 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
-
-                                 This feature can be modified afterwards using unitary function
-                                 @ref LL_TIM_IC_SetFilter().*/
-
-} LL_TIM_ENCODER_InitTypeDef;
-
-/**
-  * @brief  TIM Hall sensor interface configuration structure definition.
-  */
-typedef struct
-{
-
-  uint32_t IC1Polarity;        /*!< Specifies the active edge of TI1 input.
-                                    This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
-
-                                    This feature can be modified afterwards using unitary function
-                                    @ref LL_TIM_IC_SetPolarity().*/
-
-  uint32_t IC1Prescaler;       /*!< Specifies the TI1 input prescaler value.
-                                    Prescaler must be set to get a maximum counter period longer than the
-                                    time interval between 2 consecutive changes on the Hall inputs.
-                                    This parameter can be a value of @ref TIM_LL_EC_ICPSC.
-
-                                    This feature can be modified afterwards using unitary function
-                                    @ref LL_TIM_IC_SetPrescaler().*/
-
-  uint32_t IC1Filter;          /*!< Specifies the TI1 input filter.
-                                    This parameter can be a value of
-                                    @ref TIM_LL_EC_IC_FILTER.
-
-                                    This feature can be modified afterwards using unitary function
-                                    @ref LL_TIM_IC_SetFilter().*/
-
-  uint32_t CommutationDelay;   /*!< Specifies the compare value to be loaded into the Capture Compare Register.
-                                    A positive pulse (TRGO event) is generated with a programmable delay every time
-                                    a change occurs on the Hall inputs.
-                                    This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
-
-                                    This feature can be modified afterwards using unitary function
-                                    @ref LL_TIM_OC_SetCompareCH2().*/
-} LL_TIM_HALLSENSOR_InitTypeDef;
-
-/**
-  * @brief  BDTR (Break and Dead Time) structure definition
-  */
-typedef struct
-{
-  uint32_t OSSRState;            /*!< Specifies the Off-State selection used in Run mode.
-                                      This parameter can be a value of @ref TIM_LL_EC_OSSR
-
-                                      This feature can be modified afterwards using unitary function
-                                      @ref LL_TIM_SetOffStates()
-
-                                      @note This bit-field cannot be modified as long as LOCK level 2 has been
-                                       programmed. */
-
-  uint32_t OSSIState;            /*!< Specifies the Off-State used in Idle state.
-                                      This parameter can be a value of @ref TIM_LL_EC_OSSI
-
-                                      This feature can be modified afterwards using unitary function
-                                      @ref LL_TIM_SetOffStates()
-
-                                      @note This bit-field cannot be modified as long as LOCK level 2 has been
-                                      programmed. */
-
-  uint32_t LockLevel;            /*!< Specifies the LOCK level parameters.
-                                      This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
-
-                                      @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR
-                                      register has been written, their content is frozen until the next reset.*/
-
-  uint8_t DeadTime;              /*!< Specifies the delay time between the switching-off and the
-                                      switching-on of the outputs.
-                                      This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
-
-                                      This feature can be modified afterwards using unitary function
-                                      @ref LL_TIM_OC_SetDeadTime()
-
-                                      @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been
-                                       programmed. */
-
-  uint16_t BreakState;           /*!< Specifies whether the TIM Break input is enabled or not.
-                                      This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
-
-                                      This feature can be modified afterwards using unitary functions
-                                      @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
-
-                                      @note This bit-field can not be modified as long as LOCK level 1 has been
-                                      programmed. */
-
-  uint32_t BreakPolarity;        /*!< Specifies the TIM Break Input pin polarity.
-                                      This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
-
-                                      This feature can be modified afterwards using unitary function
-                                      @ref LL_TIM_ConfigBRK()
-
-                                      @note This bit-field can not be modified as long as LOCK level 1 has been
-                                      programmed. */
-
-  uint32_t BreakFilter;          /*!< Specifies the TIM Break Filter.
-                                      This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER
-
-                                      This feature can be modified afterwards using unitary function
-                                      @ref LL_TIM_ConfigBRK()
-
-                                      @note This bit-field can not be modified as long as LOCK level 1 has been
-                                      programmed. */
-
-#if defined(TIM_BDTR_BKBID)
-  uint32_t BreakAFMode;           /*!< Specifies the alternate function mode of the break input.
-                                      This parameter can be a value of @ref TIM_LL_EC_BREAK_AFMODE
-
-                                      This feature can be modified afterwards using unitary functions
-                                      @ref LL_TIM_ConfigBRK()
-
-                                      @note Bidirectional break input is only supported by advanced timers instances.
-
-                                      @note This bit-field can not be modified as long as LOCK level 1 has been
-                                      programmed. */
-
-#endif /*TIM_BDTR_BKBID */
-  uint32_t Break2State;          /*!< Specifies whether the TIM Break2 input is enabled or not.
-                                      This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE
-
-                                      This feature can be modified afterwards using unitary functions
-                                      @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
-
-                                      @note This bit-field can not be modified as long as LOCK level 1 has been
-                                      programmed. */
-
-  uint32_t Break2Polarity;        /*!< Specifies the TIM Break2 Input pin polarity.
-                                      This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY
-
-                                      This feature can be modified afterwards using unitary function
-                                      @ref LL_TIM_ConfigBRK2()
-
-                                      @note This bit-field can not be modified as long as LOCK level 1 has been
-                                      programmed. */
-
-  uint32_t Break2Filter;          /*!< Specifies the TIM Break2 Filter.
-                                      This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER
-
-                                      This feature can be modified afterwards using unitary function
-                                      @ref LL_TIM_ConfigBRK2()
-
-                                      @note This bit-field can not be modified as long as LOCK level 1 has been
-                                      programmed. */
-
-#if defined(TIM_BDTR_BKBID)
-  uint32_t Break2AFMode;          /*!< Specifies the alternate function mode of the break2 input.
-                                      This parameter can be a value of @ref TIM_LL_EC_BREAK2_AFMODE
-
-                                      This feature can be modified afterwards using unitary functions
-                                      @ref LL_TIM_ConfigBRK2()
-
-                                      @note Bidirectional break input is only supported by advanced timers instances.
-
-                                      @note This bit-field can not be modified as long as LOCK level 1 has been
-                                      programmed. */
-
-#endif /*TIM_BDTR_BKBID */
-  uint32_t AutomaticOutput;      /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
-                                      This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
-
-                                      This feature can be modified afterwards using unitary functions
-                                      @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
-
-                                      @note This bit-field can not be modified as long as LOCK level 1 has been
-                                      programmed. */
-} LL_TIM_BDTR_InitTypeDef;
-
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
-  * @{
-  */
-
-/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
-  * @brief    Flags defines which can be used with LL_TIM_ReadReg function.
-  * @{
-  */
-#define LL_TIM_SR_UIF                          TIM_SR_UIF           /*!< Update interrupt flag */
-#define LL_TIM_SR_CC1IF                        TIM_SR_CC1IF         /*!< Capture/compare 1 interrupt flag */
-#define LL_TIM_SR_CC2IF                        TIM_SR_CC2IF         /*!< Capture/compare 2 interrupt flag */
-#define LL_TIM_SR_CC3IF                        TIM_SR_CC3IF         /*!< Capture/compare 3 interrupt flag */
-#define LL_TIM_SR_CC4IF                        TIM_SR_CC4IF         /*!< Capture/compare 4 interrupt flag */
-#define LL_TIM_SR_CC5IF                        TIM_SR_CC5IF         /*!< Capture/compare 5 interrupt flag */
-#define LL_TIM_SR_CC6IF                        TIM_SR_CC6IF         /*!< Capture/compare 6 interrupt flag */
-#define LL_TIM_SR_COMIF                        TIM_SR_COMIF         /*!< COM interrupt flag */
-#define LL_TIM_SR_TIF                          TIM_SR_TIF           /*!< Trigger interrupt flag */
-#define LL_TIM_SR_BIF                          TIM_SR_BIF           /*!< Break interrupt flag */
-#define LL_TIM_SR_B2IF                         TIM_SR_B2IF          /*!< Second break interrupt flag */
-#define LL_TIM_SR_CC1OF                        TIM_SR_CC1OF         /*!< Capture/Compare 1 overcapture flag */
-#define LL_TIM_SR_CC2OF                        TIM_SR_CC2OF         /*!< Capture/Compare 2 overcapture flag */
-#define LL_TIM_SR_CC3OF                        TIM_SR_CC3OF         /*!< Capture/Compare 3 overcapture flag */
-#define LL_TIM_SR_CC4OF                        TIM_SR_CC4OF         /*!< Capture/Compare 4 overcapture flag */
-#define LL_TIM_SR_SBIF                         TIM_SR_SBIF          /*!< System Break interrupt flag  */
-/**
-  * @}
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
-  * @{
-  */
-#define LL_TIM_BREAK_DISABLE            0x00000000U             /*!< Break function disabled */
-#define LL_TIM_BREAK_ENABLE             TIM_BDTR_BKE            /*!< Break function enabled */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable
-  * @{
-  */
-#define LL_TIM_BREAK2_DISABLE            0x00000000U              /*!< Break2 function disabled */
-#define LL_TIM_BREAK2_ENABLE             TIM_BDTR_BK2E            /*!< Break2 function enabled */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
-  * @{
-  */
-#define LL_TIM_AUTOMATICOUTPUT_DISABLE         0x00000000U             /*!< MOE can be set only by software */
-#define LL_TIM_AUTOMATICOUTPUT_ENABLE          TIM_BDTR_AOE            /*!< MOE can be set by software or automatically at the next update event */
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/** @defgroup TIM_LL_EC_IT IT Defines
-  * @brief    IT defines which can be used with LL_TIM_ReadReg and  LL_TIM_WriteReg functions.
-  * @{
-  */
-#define LL_TIM_DIER_UIE                        TIM_DIER_UIE         /*!< Update interrupt enable */
-#define LL_TIM_DIER_CC1IE                      TIM_DIER_CC1IE       /*!< Capture/compare 1 interrupt enable */
-#define LL_TIM_DIER_CC2IE                      TIM_DIER_CC2IE       /*!< Capture/compare 2 interrupt enable */
-#define LL_TIM_DIER_CC3IE                      TIM_DIER_CC3IE       /*!< Capture/compare 3 interrupt enable */
-#define LL_TIM_DIER_CC4IE                      TIM_DIER_CC4IE       /*!< Capture/compare 4 interrupt enable */
-#define LL_TIM_DIER_COMIE                      TIM_DIER_COMIE       /*!< COM interrupt enable */
-#define LL_TIM_DIER_TIE                        TIM_DIER_TIE         /*!< Trigger interrupt enable */
-#define LL_TIM_DIER_BIE                        TIM_DIER_BIE         /*!< Break interrupt enable */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
-  * @{
-  */
-#define LL_TIM_UPDATESOURCE_REGULAR            0x00000000U          /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
-#define LL_TIM_UPDATESOURCE_COUNTER            TIM_CR1_URS          /*!< Only counter overflow/underflow generates an update request */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
-  * @{
-  */
-#define LL_TIM_ONEPULSEMODE_SINGLE             TIM_CR1_OPM          /*!< Counter stops counting at the next update event */
-#define LL_TIM_ONEPULSEMODE_REPETITIVE         0x00000000U          /*!< Counter is not stopped at update event */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
-  * @{
-  */
-#define LL_TIM_COUNTERMODE_UP                  0x00000000U          /*!<Counter used as upcounter */
-#define LL_TIM_COUNTERMODE_DOWN                TIM_CR1_DIR          /*!< Counter used as downcounter */
-#define LL_TIM_COUNTERMODE_CENTER_DOWN         TIM_CR1_CMS_0        /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting down. */
-#define LL_TIM_COUNTERMODE_CENTER_UP           TIM_CR1_CMS_1        /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting up */
-#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN      TIM_CR1_CMS          /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting up or down. */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
-  * @{
-  */
-#define LL_TIM_CLOCKDIVISION_DIV1              0x00000000U          /*!< tDTS=tCK_INT */
-#define LL_TIM_CLOCKDIVISION_DIV2              TIM_CR1_CKD_0        /*!< tDTS=2*tCK_INT */
-#define LL_TIM_CLOCKDIVISION_DIV4              TIM_CR1_CKD_1        /*!< tDTS=4*tCK_INT */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
-  * @{
-  */
-#define LL_TIM_COUNTERDIRECTION_UP             0x00000000U          /*!< Timer counter counts up */
-#define LL_TIM_COUNTERDIRECTION_DOWN           TIM_CR1_DIR          /*!< Timer counter counts down */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare  Update Source
-  * @{
-  */
-#define LL_TIM_CCUPDATESOURCE_COMG_ONLY        0x00000000U          /*!< Capture/compare control bits are updated by setting the COMG bit only */
-#define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI    TIM_CR2_CCUS         /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
-  * @{
-  */
-#define LL_TIM_CCDMAREQUEST_CC                 0x00000000U          /*!< CCx DMA request sent when CCx event occurs */
-#define LL_TIM_CCDMAREQUEST_UPDATE             TIM_CR2_CCDS         /*!< CCx DMA requests sent when update event occurs */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
-  * @{
-  */
-#define LL_TIM_LOCKLEVEL_OFF                   0x00000000U          /*!< LOCK OFF - No bit is write protected */
-#define LL_TIM_LOCKLEVEL_1                     TIM_BDTR_LOCK_0      /*!< LOCK Level 1 */
-#define LL_TIM_LOCKLEVEL_2                     TIM_BDTR_LOCK_1      /*!< LOCK Level 2 */
-#define LL_TIM_LOCKLEVEL_3                     TIM_BDTR_LOCK        /*!< LOCK Level 3 */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_CHANNEL Channel
-  * @{
-  */
-#define LL_TIM_CHANNEL_CH1                     TIM_CCER_CC1E     /*!< Timer input/output channel 1 */
-#define LL_TIM_CHANNEL_CH1N                    TIM_CCER_CC1NE    /*!< Timer complementary output channel 1 */
-#define LL_TIM_CHANNEL_CH2                     TIM_CCER_CC2E     /*!< Timer input/output channel 2 */
-#define LL_TIM_CHANNEL_CH2N                    TIM_CCER_CC2NE    /*!< Timer complementary output channel 2 */
-#define LL_TIM_CHANNEL_CH3                     TIM_CCER_CC3E     /*!< Timer input/output channel 3 */
-#define LL_TIM_CHANNEL_CH3N                    TIM_CCER_CC3NE    /*!< Timer complementary output channel 3 */
-#define LL_TIM_CHANNEL_CH4                     TIM_CCER_CC4E     /*!< Timer input/output channel 4 */
-#define LL_TIM_CHANNEL_CH5                     TIM_CCER_CC5E     /*!< Timer output channel 5 */
-#define LL_TIM_CHANNEL_CH6                     TIM_CCER_CC6E     /*!< Timer output channel 6 */
-/**
-  * @}
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
-  * @{
-  */
-#define LL_TIM_OCSTATE_DISABLE                 0x00000000U             /*!< OCx is not active */
-#define LL_TIM_OCSTATE_ENABLE                  TIM_CCER_CC1E           /*!< OCx signal is output on the corresponding output pin */
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
-  * @{
-  */
-#define LL_TIM_OCMODE_FROZEN                   0x00000000U                                              /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
-#define LL_TIM_OCMODE_ACTIVE                   TIM_CCMR1_OC1M_0                                         /*!<OCyREF is forced high on compare match*/
-#define LL_TIM_OCMODE_INACTIVE                 TIM_CCMR1_OC1M_1                                         /*!<OCyREF is forced low on compare match*/
-#define LL_TIM_OCMODE_TOGGLE                   (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)                    /*!<OCyREF toggles on compare match*/
-#define LL_TIM_OCMODE_FORCED_INACTIVE          TIM_CCMR1_OC1M_2                                         /*!<OCyREF is forced low*/
-#define LL_TIM_OCMODE_FORCED_ACTIVE            (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)                    /*!<OCyREF is forced high*/
-#define LL_TIM_OCMODE_PWM1                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)                    /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive.  In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
-#define LL_TIM_OCMODE_PWM2                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active.  In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
-#define LL_TIM_OCMODE_RETRIG_OPM1              TIM_CCMR1_OC1M_3                                         /*!<Retrigerrable OPM mode 1*/
-#define LL_TIM_OCMODE_RETRIG_OPM2              (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)                    /*!<Retrigerrable OPM mode 2*/
-#define LL_TIM_OCMODE_COMBINED_PWM1            (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)                    /*!<Combined PWM mode 1*/
-#define LL_TIM_OCMODE_COMBINED_PWM2            (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 2*/
-#define LL_TIM_OCMODE_ASSYMETRIC_PWM1          (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/
-#define LL_TIM_OCMODE_ASSYMETRIC_PWM2          (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M)                      /*!<Asymmetric PWM mode 2*/
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
-  * @{
-  */
-#define LL_TIM_OCPOLARITY_HIGH                 0x00000000U                 /*!< OCxactive high*/
-#define LL_TIM_OCPOLARITY_LOW                  TIM_CCER_CC1P               /*!< OCxactive low*/
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
-  * @{
-  */
-#define LL_TIM_OCIDLESTATE_LOW                 0x00000000U             /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
-#define LL_TIM_OCIDLESTATE_HIGH                TIM_CR2_OIS1            /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5
-  * @{
-  */
-#define LL_TIM_GROUPCH5_NONE                   0x00000000U           /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
-#define LL_TIM_GROUPCH5_OC1REFC                TIM_CCR5_GC5C1        /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */
-#define LL_TIM_GROUPCH5_OC2REFC                TIM_CCR5_GC5C2        /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */
-#define LL_TIM_GROUPCH5_OC3REFC                TIM_CCR5_GC5C3        /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
-  * @{
-  */
-#define LL_TIM_ACTIVEINPUT_DIRECTTI            (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
-#define LL_TIM_ACTIVEINPUT_INDIRECTTI          (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
-#define LL_TIM_ACTIVEINPUT_TRC                 (TIM_CCMR1_CC1S << 16U)   /*!< ICx is mapped on TRC */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
-  * @{
-  */
-#define LL_TIM_ICPSC_DIV1                      0x00000000U                    /*!< No prescaler, capture is done each time an edge is detected on the capture input */
-#define LL_TIM_ICPSC_DIV2                      (TIM_CCMR1_IC1PSC_0 << 16U)    /*!< Capture is done once every 2 events */
-#define LL_TIM_ICPSC_DIV4                      (TIM_CCMR1_IC1PSC_1 << 16U)    /*!< Capture is done once every 4 events */
-#define LL_TIM_ICPSC_DIV8                      (TIM_CCMR1_IC1PSC << 16U)      /*!< Capture is done once every 8 events */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
-  * @{
-  */
-#define LL_TIM_IC_FILTER_FDIV1                 0x00000000U                                                        /*!< No filter, sampling is done at fDTS */
-#define LL_TIM_IC_FILTER_FDIV1_N2              (TIM_CCMR1_IC1F_0 << 16U)                                          /*!< fSAMPLING=fCK_INT, N=2 */
-#define LL_TIM_IC_FILTER_FDIV1_N4              (TIM_CCMR1_IC1F_1 << 16U)                                          /*!< fSAMPLING=fCK_INT, N=4 */
-#define LL_TIM_IC_FILTER_FDIV1_N8              ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fCK_INT, N=8 */
-#define LL_TIM_IC_FILTER_FDIV2_N6              (TIM_CCMR1_IC1F_2 << 16U)                                          /*!< fSAMPLING=fDTS/2, N=6 */
-#define LL_TIM_IC_FILTER_FDIV2_N8              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fDTS/2, N=8 */
-#define LL_TIM_IC_FILTER_FDIV4_N6              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)                     /*!< fSAMPLING=fDTS/4, N=6 */
-#define LL_TIM_IC_FILTER_FDIV4_N8              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/4, N=8 */
-#define LL_TIM_IC_FILTER_FDIV8_N6              (TIM_CCMR1_IC1F_3 << 16U)                                          /*!< fSAMPLING=fDTS/8, N=6 */
-#define LL_TIM_IC_FILTER_FDIV8_N8              ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fDTS/8, N=8 */
-#define LL_TIM_IC_FILTER_FDIV16_N5             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U)                     /*!< fSAMPLING=fDTS/16, N=5 */
-#define LL_TIM_IC_FILTER_FDIV16_N6             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/16, N=6 */
-#define LL_TIM_IC_FILTER_FDIV16_N8             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U)                     /*!< fSAMPLING=fDTS/16, N=8 */
-#define LL_TIM_IC_FILTER_FDIV32_N5             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/32, N=5 */
-#define LL_TIM_IC_FILTER_FDIV32_N6             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)  /*!< fSAMPLING=fDTS/32, N=6 */
-#define LL_TIM_IC_FILTER_FDIV32_N8             (TIM_CCMR1_IC1F << 16U)                                            /*!< fSAMPLING=fDTS/32, N=8 */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
-  * @{
-  */
-#define LL_TIM_IC_POLARITY_RISING              0x00000000U                      /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
-#define LL_TIM_IC_POLARITY_FALLING             TIM_CCER_CC1P                    /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
-#define LL_TIM_IC_POLARITY_BOTHEDGE            (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
-  * @{
-  */
-#define LL_TIM_CLOCKSOURCE_INTERNAL            0x00000000U                                          /*!< The timer is clocked by the internal clock provided from the RCC */
-#define LL_TIM_CLOCKSOURCE_EXT_MODE1           (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)   /*!< Counter counts at each rising or falling edge on a selected input*/
-#define LL_TIM_CLOCKSOURCE_EXT_MODE2           TIM_SMCR_ECE                                         /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
-  * @{
-  */
-#define LL_TIM_ENCODERMODE_X2_TI1                     TIM_SMCR_SMS_0                                                     /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
-#define LL_TIM_ENCODERMODE_X2_TI2                     TIM_SMCR_SMS_1                                                     /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
-#define LL_TIM_ENCODERMODE_X4_TI12                   (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)                                   /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_TRGO Trigger Output
-  * @{
-  */
-#define LL_TIM_TRGO_RESET                      0x00000000U                                     /*!< UG bit from the TIMx_EGR register is used as trigger output */
-#define LL_TIM_TRGO_ENABLE                     TIM_CR2_MMS_0                                   /*!< Counter Enable signal (CNT_EN) is used as trigger output */
-#define LL_TIM_TRGO_UPDATE                     TIM_CR2_MMS_1                                   /*!< Update event is used as trigger output */
-#define LL_TIM_TRGO_CC1IF                      (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)                 /*!< CC1 capture or a compare match is used as trigger output */
-#define LL_TIM_TRGO_OC1REF                     TIM_CR2_MMS_2                                   /*!< OC1REF signal is used as trigger output */
-#define LL_TIM_TRGO_OC2REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)                 /*!< OC2REF signal is used as trigger output */
-#define LL_TIM_TRGO_OC3REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)                 /*!< OC3REF signal is used as trigger output */
-#define LL_TIM_TRGO_OC4REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2
-  * @{
-  */
-#define LL_TIM_TRGO2_RESET                     0x00000000U                                                         /*!< UG bit from the TIMx_EGR register is used as trigger output 2 */
-#define LL_TIM_TRGO2_ENABLE                    TIM_CR2_MMS2_0                                                      /*!< Counter Enable signal (CNT_EN) is used as trigger output 2 */
-#define LL_TIM_TRGO2_UPDATE                    TIM_CR2_MMS2_1                                                      /*!< Update event is used as trigger output 2 */
-#define LL_TIM_TRGO2_CC1F                      (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                                   /*!< CC1 capture or a compare match is used as trigger output 2 */
-#define LL_TIM_TRGO2_OC1                       TIM_CR2_MMS2_2                                                      /*!< OC1REF signal is used as trigger output 2 */
-#define LL_TIM_TRGO2_OC2                       (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)                                   /*!< OC2REF signal is used as trigger output 2 */
-#define LL_TIM_TRGO2_OC3                       (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)                                   /*!< OC3REF signal is used as trigger output 2 */
-#define LL_TIM_TRGO2_OC4                       (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                  /*!< OC4REF signal is used as trigger output 2 */
-#define LL_TIM_TRGO2_OC5                       TIM_CR2_MMS2_3                                                      /*!< OC5REF signal is used as trigger output 2 */
-#define LL_TIM_TRGO2_OC6                       (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)                                   /*!< OC6REF signal is used as trigger output 2 */
-#define LL_TIM_TRGO2_OC4_RISINGFALLING         (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)                                   /*!< OC4REF rising or falling edges are used as trigger output 2 */
-#define LL_TIM_TRGO2_OC6_RISINGFALLING         (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                  /*!< OC6REF rising or falling edges are used as trigger output 2 */
-#define LL_TIM_TRGO2_OC4_RISING_OC6_RISING     (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)                                   /*!< OC4REF or OC6REF rising edges are used as trigger output 2 */
-#define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING    (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)                  /*!< OC4REF rising or OC6REF falling edges are used as trigger output 2 */
-#define LL_TIM_TRGO2_OC5_RISING_OC6_RISING     (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)                   /*!< OC5REF or OC6REF rising edges are used as trigger output 2 */
-#define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING    (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF rising or OC6REF falling edges are used as trigger output 2 */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
-  * @{
-  */
-#define LL_TIM_SLAVEMODE_DISABLED              0x00000000U                         /*!< Slave mode disabled */
-#define LL_TIM_SLAVEMODE_RESET                 TIM_SMCR_SMS_2                      /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
-#define LL_TIM_SLAVEMODE_GATED                 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)   /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
-#define LL_TIM_SLAVEMODE_TRIGGER               (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)   /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
-#define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3                      /*!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI)  reinitializes the counter, generates an update of the registers and starts the counter */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_TS Trigger Selection
-  * @{
-  */
-#define LL_TIM_TS_ITR0                         0x00000000U                                                     /*!< Internal Trigger 0 (ITR0) is used as trigger input */
-#define LL_TIM_TS_ITR1                         TIM_SMCR_TS_0                                                   /*!< Internal Trigger 1 (ITR1) is used as trigger input */
-#define LL_TIM_TS_ITR2                         TIM_SMCR_TS_1                                                   /*!< Internal Trigger 2 (ITR2) is used as trigger input */
-#define LL_TIM_TS_ITR3                         (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)                                 /*!< Internal Trigger 3 (ITR3) is used as trigger input */
-#define LL_TIM_TS_ITR4                         (TIM_SMCR_TS_3)                                                 /*!< Internal Trigger 4 (ITR4) is used as trigger input */
-#define LL_TIM_TS_ITR5                         (TIM_SMCR_TS_0 | TIM_SMCR_TS_3)                                 /*!< Internal Trigger 5 (ITR5) is used as trigger input */
-#define LL_TIM_TS_ITR6                         (TIM_SMCR_TS_1 | TIM_SMCR_TS_3)                                 /*!< Internal Trigger 6 (ITR6) is used as trigger input */
-#define LL_TIM_TS_ITR7                         (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_3)                 /*!< Internal Trigger 7 (ITR7) is used as trigger input */
-#define LL_TIM_TS_ITR8                         (TIM_SMCR_TS_2 | TIM_SMCR_TS_3)                                 /*!< Internal Trigger 8 (ITR8) is used as trigger input */
-#define LL_TIM_TS_ITR9                         (TIM_SMCR_TS_0 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)                 /*!< Internal Trigger 9 (ITR9) is used as trigger input */
-#define LL_TIM_TS_ITR10                        (TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)                 /*!< Internal Trigger 10 (ITR10) is used as trigger input */
-#define LL_TIM_TS_ITR11                        (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 11 (ITR11) is used as trigger input */
-#define LL_TIM_TS_ITR12                        (TIM_SMCR_TS_4)                                                 /*!< Internal Trigger 12 (ITR12) is used as trigger input */
-#define LL_TIM_TS_ITR13                        (TIM_SMCR_TS_0 | TIM_SMCR_TS_4)                                 /*!< Internal Trigger 13 (ITR13) is used as trigger input */
-#define LL_TIM_TS_TI1F_ED                      TIM_SMCR_TS_2                                                   /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
-#define LL_TIM_TS_TI1FP1                       (TIM_SMCR_TS_2 | TIM_SMCR_TS_0)                                 /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
-#define LL_TIM_TS_TI2FP2                       (TIM_SMCR_TS_2 | TIM_SMCR_TS_1)                                 /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
-#define LL_TIM_TS_ETRF                         (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0)                 /*!< Filtered external Trigger (ETRF) is used as trigger input */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
-  * @{
-  */
-#define LL_TIM_ETR_POLARITY_NONINVERTED        0x00000000U             /*!< ETR is non-inverted, active at high level or rising edge */
-#define LL_TIM_ETR_POLARITY_INVERTED           TIM_SMCR_ETP            /*!< ETR is inverted, active at low level or falling edge */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
-  * @{
-  */
-#define LL_TIM_ETR_PRESCALER_DIV1              0x00000000U             /*!< ETR prescaler OFF */
-#define LL_TIM_ETR_PRESCALER_DIV2              TIM_SMCR_ETPS_0         /*!< ETR frequency is divided by 2 */
-#define LL_TIM_ETR_PRESCALER_DIV4              TIM_SMCR_ETPS_1         /*!< ETR frequency is divided by 4 */
-#define LL_TIM_ETR_PRESCALER_DIV8              TIM_SMCR_ETPS           /*!< ETR frequency is divided by 8 */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
-  * @{
-  */
-#define LL_TIM_ETR_FILTER_FDIV1                0x00000000U                                          /*!< No filter, sampling is done at fDTS */
-#define LL_TIM_ETR_FILTER_FDIV1_N2             TIM_SMCR_ETF_0                                       /*!< fSAMPLING=fCK_INT, N=2 */
-#define LL_TIM_ETR_FILTER_FDIV1_N4             TIM_SMCR_ETF_1                                       /*!< fSAMPLING=fCK_INT, N=4 */
-#define LL_TIM_ETR_FILTER_FDIV1_N8             (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fCK_INT, N=8 */
-#define LL_TIM_ETR_FILTER_FDIV2_N6             TIM_SMCR_ETF_2                                       /*!< fSAMPLING=fDTS/2, N=6 */
-#define LL_TIM_ETR_FILTER_FDIV2_N8             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fDTS/2, N=8 */
-#define LL_TIM_ETR_FILTER_FDIV4_N6             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)                    /*!< fSAMPLING=fDTS/4, N=6 */
-#define LL_TIM_ETR_FILTER_FDIV4_N8             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/4, N=8 */
-#define LL_TIM_ETR_FILTER_FDIV8_N6             TIM_SMCR_ETF_3                                       /*!< fSAMPLING=fDTS/8, N=8 */
-#define LL_TIM_ETR_FILTER_FDIV8_N8             (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fDTS/16, N=5 */
-#define LL_TIM_ETR_FILTER_FDIV16_N5            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1)                    /*!< fSAMPLING=fDTS/16, N=6 */
-#define LL_TIM_ETR_FILTER_FDIV16_N6            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/16, N=8 */
-#define LL_TIM_ETR_FILTER_FDIV16_N8            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2)                    /*!< fSAMPLING=fDTS/16, N=5 */
-#define LL_TIM_ETR_FILTER_FDIV32_N5            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/32, N=5 */
-#define LL_TIM_ETR_FILTER_FDIV32_N6            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)   /*!< fSAMPLING=fDTS/32, N=6 */
-#define LL_TIM_ETR_FILTER_FDIV32_N8            TIM_SMCR_ETF                                         /*!< fSAMPLING=fDTS/32, N=8 */
-/**
-  * @}
-  */
-
-#define LL_TIM_TIM1_ETRSOURCE_GPIO        0x00000000U                                                 /* !< TIM1_ETR is connected to GPIO */
-#define LL_TIM_TIM1_ETRSOURCE_COMP1       TIM1_AF1_ETRSEL_0                                           /* !< TIM1_ETR is connected to COMP1 OUT */
-#define LL_TIM_TIM1_ETRSOURCE_COMP2       TIM1_AF1_ETRSEL_1                                           /* !< TIM1_ETR is connected to COMP2 OUT */
-#define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1   (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)                     /* !< TIM1_ETR is connected to ADC1 AWD1 */
-#define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2   (TIM1_AF1_ETRSEL_2)                                         /* !< TIM1_ETR is connected to ADC1 AWD2 */
-#define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3   (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)                     /* !< TIM1_ETR is connected to ADC1 AWD3 */
-#define LL_TIM_TIM1_ETRSOURCE_ADC3_AWD1   (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1)                     /* !< TIM1_ETR is connected to ADC3 AWD1 */
-#define LL_TIM_TIM1_ETRSOURCE_ADC3_AWD2   (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC3 AWD2 */
-#define LL_TIM_TIM1_ETRSOURCE_ADC3_AWD3   TIM1_AF1_ETRSEL_3                                           /* !< TIM1_ETR is connected to ADC3 AWD3 */
-
-#define LL_TIM_TIM8_ETRSOURCE_GPIO        0x00000000U                                                 /* !< TIM8_ETR is connected to GPIO */
-#define LL_TIM_TIM8_ETRSOURCE_COMP1       TIM8_AF1_ETRSEL_0                                           /* !< TIM8_ETR is connected to COMP1 OUT */
-#define LL_TIM_TIM8_ETRSOURCE_COMP2       TIM8_AF1_ETRSEL_1                                           /* !< TIM8_ETR is connected to COMP2 OUT */
-#define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1   (TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0)                     /* !< TIM8_ETR is connected to ADC2 AWD1 */
-#define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2   (TIM8_AF1_ETRSEL_2)                                         /* !< TIM8_ETR is connected to ADC2 AWD2 */
-#define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3   (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0)                     /* !< TIM8_ETR is connected to ADC2 AWD3 */
-#define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD1   (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1)                     /* !< TIM8_ETR is connected to ADC3 AWD1 */
-#define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD2   (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC3 AWD2 */
-#define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD3   TIM8_AF1_ETRSEL_3                                           /* !< TIM8_ETR is connected to ADC3 AWD3 */
-
-#define LL_TIM_TIM2_ETRSOURCE_GPIO        0x00000000U                                                 /* !< TIM2_ETR is connected to GPIO */
-#define LL_TIM_TIM2_ETRSOURCE_COMP1       (TIM2_AF1_ETRSEL_0)                                         /* !< TIM2_ETR is connected to COMP1 OUT */
-#define LL_TIM_TIM2_ETRSOURCE_COMP2       (TIM2_AF1_ETRSEL_1)                                         /* !< TIM2_ETR is connected to COMP2 OUT */
-#define LL_TIM_TIM2_ETRSOURCE_RCC_LSE     (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0)                     /* !< TIM2_ETR is connected to RCC LSE */
-#define LL_TIM_TIM2_ETRSOURCE_SAI1_FSA    TIM2_AF1_ETRSEL_2                                           /* !< TIM2_ETR is connected to SAI1 FS_A */
-#define LL_TIM_TIM2_ETRSOURCE_SAI1_FSB    (TIM2_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0)                     /* !< TIM2_ETR is connected to SAI1 FS_B */
-
-#define LL_TIM_TIM3_ETRSOURCE_GPIO        0x00000000U                                                 /* !< TIM3_ETR is connected to GPIO */
-#define LL_TIM_TIM3_ETRSOURCE_COMP1       TIM3_AF1_ETRSEL_0                                           /* !< TIM3_ETR is connected to COMP1 OUT */
-
-#define LL_TIM_TIM5_ETRSOURCE_GPIO        0x00000000U                                                 /* !< TIM5_ETR is connected to GPIO */
-#define LL_TIM_TIM5_ETRSOURCE_SAI2_FSA    TIM5_AF1_ETRSEL_0                                           /* !< TIM5_ETR is connected to SAI2 FS_A */
-#define LL_TIM_TIM5_ETRSOURCE_SAI2_FSB    TIM5_AF1_ETRSEL_1                                           /* !< TIM5_ETR is connected to SAI2 FS_B */
-#define LL_TIM_TIM5_ETRSOURCE_SAI4_FSA    TIM5_AF1_ETRSEL_0                                           /* !< TIM5_ETR is connected to SAI4 FS_A */
-#define LL_TIM_TIM5_ETRSOURCE_SAI4_FSB    TIM5_AF1_ETRSEL_1                                           /* !< TIM5_ETR is connected to SAI4 FS_B */
-
-#define LL_TIM_TIM23_ETRSOURCE_GPIO       0x00000000U                                                 /* !< TIM23_ETR is connected to GPIO */
-#define LL_TIM_TIM23_ETRSOURCE_COMP1      (TIM2_AF1_ETRSEL_0)                                         /* !< TIM23_ETR is connected to COMP1 OUT */
-#define LL_TIM_TIM23_ETRSOURCE_COMP2      (TIM2_AF1_ETRSEL_1)                                         /* !< TIM23_ETR is connected to COMP2 OUT */
-
-#define LL_TIM_TIM24_ETRSOURCE_GPIO        0x00000000U                                                /* !< TIM24_ETR is connected to GPIO */
-#define LL_TIM_TIM24_ETRSOURCE_SAI4_FSA    TIM5_AF1_ETRSEL_0                                          /* !< TIM24_ETR is connected to SAI4 FS_A */
-#define LL_TIM_TIM24_ETRSOURCE_SAI4_FSB    TIM5_AF1_ETRSEL_1                                          /* !< TIM24_ETR is connected to SAI4 FS_B */
-#define LL_TIM_TIM24_ETRSOURCE_SAI1_FSA    (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0)                    /* !< TIM24_ETR is connected to SAI1 FS_A */
-#define LL_TIM_TIM24_ETRSOURCE_SAI1_FSB    TIM2_AF1_ETRSEL_2                                          /* !< TIM24_ETR is connected to SAI1 FS_B */
-
-/** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
-  * @{
-  */
-#define LL_TIM_BREAK_POLARITY_LOW              0x00000000U               /*!< Break input BRK is active low */
-#define LL_TIM_BREAK_POLARITY_HIGH             TIM_BDTR_BKP              /*!< Break input BRK is active high */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_BREAK_FILTER break filter
-  * @{
-  */
-#define LL_TIM_BREAK_FILTER_FDIV1              0x00000000U   /*!< No filter, BRK acts asynchronously */
-#define LL_TIM_BREAK_FILTER_FDIV1_N2           0x00010000U   /*!< fSAMPLING=fCK_INT, N=2 */
-#define LL_TIM_BREAK_FILTER_FDIV1_N4           0x00020000U   /*!< fSAMPLING=fCK_INT, N=4 */
-#define LL_TIM_BREAK_FILTER_FDIV1_N8           0x00030000U   /*!< fSAMPLING=fCK_INT, N=8 */
-#define LL_TIM_BREAK_FILTER_FDIV2_N6           0x00040000U   /*!< fSAMPLING=fDTS/2, N=6 */
-#define LL_TIM_BREAK_FILTER_FDIV2_N8           0x00050000U   /*!< fSAMPLING=fDTS/2, N=8 */
-#define LL_TIM_BREAK_FILTER_FDIV4_N6           0x00060000U   /*!< fSAMPLING=fDTS/4, N=6 */
-#define LL_TIM_BREAK_FILTER_FDIV4_N8           0x00070000U   /*!< fSAMPLING=fDTS/4, N=8 */
-#define LL_TIM_BREAK_FILTER_FDIV8_N6           0x00080000U   /*!< fSAMPLING=fDTS/8, N=6 */
-#define LL_TIM_BREAK_FILTER_FDIV8_N8           0x00090000U   /*!< fSAMPLING=fDTS/8, N=8 */
-#define LL_TIM_BREAK_FILTER_FDIV16_N5          0x000A0000U   /*!< fSAMPLING=fDTS/16, N=5 */
-#define LL_TIM_BREAK_FILTER_FDIV16_N6          0x000B0000U   /*!< fSAMPLING=fDTS/16, N=6 */
-#define LL_TIM_BREAK_FILTER_FDIV16_N8          0x000C0000U   /*!< fSAMPLING=fDTS/16, N=8 */
-#define LL_TIM_BREAK_FILTER_FDIV32_N5          0x000D0000U   /*!< fSAMPLING=fDTS/32, N=5 */
-#define LL_TIM_BREAK_FILTER_FDIV32_N6          0x000E0000U   /*!< fSAMPLING=fDTS/32, N=6 */
-#define LL_TIM_BREAK_FILTER_FDIV32_N8          0x000F0000U   /*!< fSAMPLING=fDTS/32, N=8 */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY
-  * @{
-  */
-#define LL_TIM_BREAK2_POLARITY_LOW             0x00000000U             /*!< Break input BRK2 is active low */
-#define LL_TIM_BREAK2_POLARITY_HIGH            TIM_BDTR_BK2P           /*!< Break input BRK2 is active high */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER
-  * @{
-  */
-#define LL_TIM_BREAK2_FILTER_FDIV1             0x00000000U   /*!< No filter, BRK acts asynchronously */
-#define LL_TIM_BREAK2_FILTER_FDIV1_N2          0x00100000U   /*!< fSAMPLING=fCK_INT, N=2 */
-#define LL_TIM_BREAK2_FILTER_FDIV1_N4          0x00200000U   /*!< fSAMPLING=fCK_INT, N=4 */
-#define LL_TIM_BREAK2_FILTER_FDIV1_N8          0x00300000U   /*!< fSAMPLING=fCK_INT, N=8 */
-#define LL_TIM_BREAK2_FILTER_FDIV2_N6          0x00400000U   /*!< fSAMPLING=fDTS/2, N=6 */
-#define LL_TIM_BREAK2_FILTER_FDIV2_N8          0x00500000U   /*!< fSAMPLING=fDTS/2, N=8 */
-#define LL_TIM_BREAK2_FILTER_FDIV4_N6          0x00600000U   /*!< fSAMPLING=fDTS/4, N=6 */
-#define LL_TIM_BREAK2_FILTER_FDIV4_N8          0x00700000U   /*!< fSAMPLING=fDTS/4, N=8 */
-#define LL_TIM_BREAK2_FILTER_FDIV8_N6          0x00800000U   /*!< fSAMPLING=fDTS/8, N=6 */
-#define LL_TIM_BREAK2_FILTER_FDIV8_N8          0x00900000U   /*!< fSAMPLING=fDTS/8, N=8 */
-#define LL_TIM_BREAK2_FILTER_FDIV16_N5         0x00A00000U   /*!< fSAMPLING=fDTS/16, N=5 */
-#define LL_TIM_BREAK2_FILTER_FDIV16_N6         0x00B00000U   /*!< fSAMPLING=fDTS/16, N=6 */
-#define LL_TIM_BREAK2_FILTER_FDIV16_N8         0x00C00000U   /*!< fSAMPLING=fDTS/16, N=8 */
-#define LL_TIM_BREAK2_FILTER_FDIV32_N5         0x00D00000U   /*!< fSAMPLING=fDTS/32, N=5 */
-#define LL_TIM_BREAK2_FILTER_FDIV32_N6         0x00E00000U   /*!< fSAMPLING=fDTS/32, N=6 */
-#define LL_TIM_BREAK2_FILTER_FDIV32_N8         0x00F00000U   /*!< fSAMPLING=fDTS/32, N=8 */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_OSSI OSSI
-  * @{
-  */
-#define LL_TIM_OSSI_DISABLE                    0x00000000U             /*!< When inactive, OCx/OCxN outputs are disabled */
-#define LL_TIM_OSSI_ENABLE                     TIM_BDTR_OSSI           /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_OSSR OSSR
-  * @{
-  */
-#define LL_TIM_OSSR_DISABLE                    0x00000000U             /*!< When inactive, OCx/OCxN outputs are disabled */
-#define LL_TIM_OSSR_ENABLE                     TIM_BDTR_OSSR           /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */
-/**
-  * @}
-  */
-
-#if   defined(TIM_BREAK_INPUT_SUPPORT)
-/** @defgroup TIM_LL_EC_BREAK_INPUT BREAK INPUT
-  * @{
-  */
-#define LL_TIM_BREAK_INPUT_BKIN                0x00000000U  /*!< TIMx_BKIN input */
-#define LL_TIM_BREAK_INPUT_BKIN2               0x00000004U  /*!< TIMx_BKIN2 input */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_BKIN_SOURCE BKIN SOURCE
-  * @{
-  */
-#define LL_TIM_BKIN_SOURCE_BKIN                TIM1_AF1_BKINE      /*!< BKIN input from AF controller */
-#define LL_TIM_BKIN_SOURCE_BKCOMP1             TIM1_AF1_BKCMP1E    /*!< internal signal: COMP1 output */
-#define LL_TIM_BKIN_SOURCE_BKCOMP2             TIM1_AF1_BKCMP2E    /*!< internal signal: COMP2 output */
-#define LL_TIM_BKIN_SOURCE_DF1BK               TIM1_AF1_BKDF1BK0E  /*!< internal signal: DFSDM1 break output */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_BKIN_POLARITY BKIN POLARITY
-  * @{
-  */
-#define LL_TIM_BKIN_POLARITY_LOW               TIM1_AF1_BKINP           /*!< BRK BKIN input is active low */
-#define LL_TIM_BKIN_POLARITY_HIGH              0x00000000U              /*!< BRK BKIN input is active high */
-/**
-  * @}
-  */
-#endif /* TIM_BREAK_INPUT_SUPPORT */
-
-#if defined(TIM_BDTR_BKBID)
-/** @defgroup TIM_LL_EC_BREAK_AFMODE BREAK AF MODE
-  * @{
-  */
-#define LL_TIM_BREAK_AFMODE_INPUT              0x00000000U              /*!< Break input BRK in input mode */
-#define LL_TIM_BREAK_AFMODE_BIDIRECTIONAL      TIM_BDTR_BKBID           /*!< Break input BRK in bidirectional mode */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_BREAK2_AFMODE BREAK2 AF MODE
-  * @{
-  */
-#define LL_TIM_BREAK2_AFMODE_INPUT             0x00000000U             /*!< Break2 input BRK2 in input mode */
-#define LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL     TIM_BDTR_BK2BID         /*!< Break2 input BRK2 in bidirectional mode */
-/**
-  * @}
-  */
-
-#endif /*TIM_BDTR_BKBID */
-/** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
-  * @{
-  */
-#define LL_TIM_DMABURST_BASEADDR_CR1           0x00000000U                                                      /*!< TIMx_CR1 register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CR2           TIM_DCR_DBA_0                                                    /*!< TIMx_CR2 register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_SMCR          TIM_DCR_DBA_1                                                    /*!< TIMx_SMCR register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_DIER          (TIM_DCR_DBA_1 |  TIM_DCR_DBA_0)                                 /*!< TIMx_DIER register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_SR            TIM_DCR_DBA_2                                                    /*!< TIMx_SR register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_EGR           (TIM_DCR_DBA_2 | TIM_DCR_DBA_0)                                  /*!< TIMx_EGR register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CCMR1         (TIM_DCR_DBA_2 | TIM_DCR_DBA_1)                                  /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CCMR2         (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)                  /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CCER          TIM_DCR_DBA_3                                                    /*!< TIMx_CCER register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CNT           (TIM_DCR_DBA_3 | TIM_DCR_DBA_0)                                  /*!< TIMx_CNT register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_PSC           (TIM_DCR_DBA_3 | TIM_DCR_DBA_1)                                  /*!< TIMx_PSC register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_ARR           (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)                  /*!< TIMx_ARR register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_RCR           (TIM_DCR_DBA_3 | TIM_DCR_DBA_2)                                  /*!< TIMx_RCR register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CCR1          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)                  /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CCR2          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)                  /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CCR3          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)  /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CCR4          TIM_DCR_DBA_4                                                    /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_BDTR          (TIM_DCR_DBA_4 | TIM_DCR_DBA_0)                                  /*!< TIMx_BDTR register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CCMR3         (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)                  /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CCR5          (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)                  /*!< TIMx_CCR5 register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CCR6          (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)  /*!< TIMx_CCR6 register is the DMA base address for DMA burst */
-#if defined(TIM1_AF1_BKINE)&&defined(TIM1_AF2_BKINE)
-#define LL_TIM_DMABURST_BASEADDR_AF1           (TIM_DCR_DBA_4 | TIM_DCR_DBA_3)                                  /*!< TIMx_AF1 register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_AF2           (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_0)                  /*!< TIMx_AF2 register is the DMA base address for DMA burst */
-#endif /* TIM1_AF1_BKINE && TIM1_AF2_BKINE */
-#define LL_TIM_DMABURST_BASEADDR_TISEL         (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_1)                  /*!< TIMx_TISEL register is the DMA base address for DMA burst */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
-  * @{
-  */
-#define LL_TIM_DMABURST_LENGTH_1TRANSFER       0x00000000U                                                     /*!< Transfer is done to 1 register starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_2TRANSFERS      TIM_DCR_DBL_0                                                   /*!< Transfer is done to 2 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_3TRANSFERS      TIM_DCR_DBL_1                                                   /*!< Transfer is done to 3 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_4TRANSFERS      (TIM_DCR_DBL_1 |  TIM_DCR_DBL_0)                                /*!< Transfer is done to 4 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_5TRANSFERS      TIM_DCR_DBL_2                                                   /*!< Transfer is done to 5 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_6TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_0)                                 /*!< Transfer is done to 6 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_7TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_1)                                 /*!< Transfer is done to 7 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_8TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 1 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_9TRANSFERS      TIM_DCR_DBL_3                                                   /*!< Transfer is done to 9 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_10TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_0)                                 /*!< Transfer is done to 10 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_11TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_1)                                 /*!< Transfer is done to 11 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_12TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 12 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_13TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2)                                 /*!< Transfer is done to 13 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_14TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 14 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_15TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1)                 /*!< Transfer is done to 15 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_16TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_17TRANSFERS     TIM_DCR_DBL_4                                                   /*!< Transfer is done to 17 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_18TRANSFERS     (TIM_DCR_DBL_4 |  TIM_DCR_DBL_0)                                /*!< Transfer is done to 18 registers starting from the DMA burst base address */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_TIM1_TI1_RMP  TIM1 Timer Input Ch1 Remap
-  * @{
-  */
-#define LL_TIM_TIM1_TI1_RMP_GPIO                          0x00000000U                               /* !< TIM1 input 1 is connected to GPIO */
-#define LL_TIM_TIM1_TI1_RMP_COMP1                         TIM_TISEL_TI1SEL_0                        /* !< TIM1 input 1 is connected to COMP1 OUT */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_TIM8_TI1_RMP  TIM8 Timer Input Ch1 Remap
-  * @{
-  */
-#define LL_TIM_TIM8_TI1_RMP_GPIO                          0x00000000U                               /* !< TIM8 input 1 is connected to GPIO */
-#define LL_TIM_TIM8_TI1_RMP_COMP2                         TIM_TISEL_TI1SEL_0                        /* !< TIM8 input 1 is connected to COMP2 OUT */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_TIM2_TI4_RMP  TIM2 Timer Input Ch4 Remap
-  * @{
-  */
-#define LL_TIM_TIM2_TI4_RMP_GPIO                          0x00000000U                               /* !< TIM2 input 4 is connected to GPIO */
-#define LL_TIM_TIM2_TI4_RMP_COMP1                         TIM_TISEL_TI4SEL_0                        /* !< TIM2 input 4 is connected to COMP1 OUT */
-#define LL_TIM_TIM2_TI4_RMP_COMP2                         TIM_TISEL_TI4SEL_1                        /* !< TIM2 input 4 is connected to COMP2 OUT */
-#define LL_TIM_TIM2_TI4_RMP_COMP1_COMP2                   (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM2 input 4 is connected to COMP2 OUT OR COMP2 OUT */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_TIM3_TI1_RMP  TIM3 Timer Input Ch1 Remap
-  * @{
-  */
-#define LL_TIM_TIM3_TI1_RMP_GPIO                          0x00000000U                               /* !< TIM3 input 1 is connected to GPIO */
-#define LL_TIM_TIM3_TI1_RMP_COMP1                         TIM_TISEL_TI1SEL_0                        /* !< TIM3 input 1 is connected to COMP1 OUT */
-#define LL_TIM_TIM3_TI1_RMP_COMP2                         TIM_TISEL_TI1SEL_1                        /* !< TIM3 input 1 is connected to COMP2 OUT */
-#define LL_TIM_TIM3_TI1_RMP_COMP1_COMP2                   (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM3 input 1 is connected to COMP1 OUT or COMP2 OUT */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_TIM5_TI1_RMP  TIM5 Timer Input Ch1 Remap
-  * @{
-  */
-#define LL_TIM_TIM5_TI1_RMP_GPIO                          0x00000000U                               /* !< TIM5 input 1 is connected to GPIO */
-#define LL_TIM_TIM5_TI1_RMP_CAN_TMP                       TIM_TISEL_TI1SEL_0                        /* !< TIM5 input 1 is connected to CAN TMP */
-#define LL_TIM_TIM5_TI1_RMP_CAN_RTP                       TIM_TISEL_TI1SEL_1                        /* !< TIM5 input 1 is connected to CAN RTP */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_TIM12_TI1_RMP  TIM12 Timer Input Ch1 Remap
-  * @{
-  */
-#define LL_TIM_TIM12_TI1_RMP_GPIO                         0x00000000U                               /* !< TIM12 input 1 is connected to GPIO */
-#define LL_TIM_TIM12_TI1_RMP_SPDIF_FS                     TIM_TISEL_TI1SEL_0                        /* !< TIM12 input 1 is connected to SPDIF FS */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_TIM15_TI1_RMP  TIM15 Timer Input Ch1 Remap
-  * @{
-  */
-#define LL_TIM_TIM15_TI1_RMP_GPIO                         0x00000000U                               /* !< TIM15 input 1 is connected to GPIO */
-#define LL_TIM_TIM15_TI1_RMP_TIM2_CH1                     TIM_TISEL_TI1SEL_0                        /* !< TIM15 input 1 is connected to TIM2 CH1 */
-#define LL_TIM_TIM15_TI1_RMP_TIM3_CH1                     TIM_TISEL_TI1SEL_1                        /* !< TIM15 input 1 is connected to TIM3 CH1 */
-#define LL_TIM_TIM15_TI1_RMP_TIM4_CH1                     (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM15 input 1 is connected to TIM4 CH1 */
-#define LL_TIM_TIM15_TI1_RMP_RCC_LSE                      (TIM_TISEL_TI1SEL_2)                      /* !< TIM15 input 1 is connected to RCC LSE  */
-#define LL_TIM_TIM15_TI1_RMP_RCC_CSI                      (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /* !< TIM15 input 1 is connected to RCC CSI  */
-#define LL_TIM_TIM15_TI1_RMP_RCC_MCO2                     (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /* !< TIM15 input 1 is connected to RCC MCO2 */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_TIM15_TI2_RMP  TIM15 Timer Input Ch2 Remap
-  * @{
-  */
-#define LL_TIM_TIM15_TI2_RMP_GPIO                         0x00000000U                               /* !< TIM15 input 2 is connected to GPIO */
-#define LL_TIM_TIM15_TI2_RMP_TIM2_CH2                     (TIM_TISEL_TI2SEL_0)                      /* !< TIM15 input 2 is connected to TIM2 CH2 */
-#define LL_TIM_TIM15_TI2_RMP_TIM3_CH2                     (TIM_TISEL_TI2SEL_1)                      /* !< TIM15 input 2 is connected to TIM3 CH2 */
-#define LL_TIM_TIM15_TI2_RMP_TIM4_CH2                     (TIM_TISEL_TI2SEL_0 | TIM_TISEL_TI2SEL_1) /* !< TIM15 input 2 is connected to TIM4 CH2 */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_TIM16_TI1_RMP  TIM16 Timer Input Ch1 Remap
-  * @{
-  */
-#define LL_TIM_TIM16_TI1_RMP_GPIO                         0x00000000U                               /* !< TIM16 input 1 is connected to GPIO */
-#define LL_TIM_TIM16_TI1_RMP_RCC_LSI                      TIM_TISEL_TI1SEL_0                        /* !< TIM16 input 1 is connected to RCC LSI */
-#define LL_TIM_TIM16_TI1_RMP_RCC_LSE                      TIM_TISEL_TI1SEL_1                        /* !< TIM16 input 1 is connected to RCC LSE */
-#define LL_TIM_TIM16_TI1_RMP_WKUP_IT                      (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM16 input 1 is connected to WKUP_IT */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_TIM17_TI1_RMP  TIM17 Timer Input Ch1 Remap
-  * @{
-  */
-#define LL_TIM_TIM17_TI1_RMP_GPIO                         0x00000000U                               /* !< TIM17 input 1 is connected to GPIO */
-#define LL_TIM_TIM17_TI1_RMP_SPDIF_FS                     TIM_TISEL_TI1SEL_0                        /* !< TIM17 input 1 is connected to SPDIF FS */
-#define LL_TIM_TIM17_TI1_RMP_RCC_HSE1MHZ                  TIM_TISEL_TI1SEL_1                        /* !< TIM17 input 1 is connected to RCC HSE 1Mhz */
-#define LL_TIM_TIM17_TI1_RMP_RCC_MCO1                     (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM17 input 1 is connected to RCC MCO1 */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_TIM23_TI4_RMP  TIM23 Timer Input Ch4 Remap
-  * @{
-  */
-#define LL_TIM_TIM23_TI4_RMP_GPIO                         0x00000000U                               /* !< TIM23 input 4 is connected to GPIO */
-#define LL_TIM_TIM23_TI4_RMP_COMP1                        TIM_TISEL_TI4SEL_0                        /* !< TIM23 input 4 is connected to COMP1 OUT */
-#define LL_TIM_TIM23_TI4_RMP_COMP2                        TIM_TISEL_TI4SEL_1                        /* !< TIM23 input 4 is connected to COMP2 OUT */
-#define LL_TIM_TIM23_TI4_RMP_COMP1_COMP2                  (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM23 input 4 is connected to COMP1 OUT or COMP2 OUT */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_TIM24_TI1_RMP  TIM24 Timer Input Ch1 Remap
-  * @{
-  */
-#define LL_TIM_TIM24_TI1_RMP_GPIO                         0x00000000U                               /* !< TIM24 input 1 is connected to GPIO */
-#define LL_TIM_TIM24_TI1_RMP_CAN_TMP                      TIM_TISEL_TI1SEL_0                        /* !< TIM24 input 1 is connected to CAN TMP  */
-#define LL_TIM_TIM24_TI1_RMP_CAN_RTP                      TIM_TISEL_TI1SEL_1                        /* !< TIM24 input 1 is connected to CAN RTP  */
-#define LL_TIM_TIM24_TI1_RMP_CAN_SOC                      (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM24 input 1 is connected to CAN SOC */
-
-#if defined(TIM_BREAK_INPUT_SUPPORT)
-/** Legacy definitions for compatibility purpose
-@cond 0
-  */
-#define LL_TIM_BKIN_SOURCE_DFBK  LL_TIM_BKIN_SOURCE_DF1BK
-/**
-@endcond
-  */
-#endif /* TIM_BREAK_INPUT_SUPPORT */
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
-  * @{
-  */
-
-/** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
-  * @{
-  */
-/**
-  * @brief  Write a value in TIM register.
-  * @param  __INSTANCE__ TIM Instance
-  * @param  __REG__ Register to be written
-  * @param  __VALUE__ Value to be written in the register
-  * @retval None
-  */
-#define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
-
-/**
-  * @brief  Read a value in TIM register.
-  * @param  __INSTANCE__ TIM Instance
-  * @param  __REG__ Register to be read
-  * @retval Register value
-  */
-#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
-  * @{
-  */
-
-/**
-  * @brief  HELPER macro retrieving the UIFCPY flag from the counter value.
-  * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
-  * @note  Relevant only if UIF flag remapping has been enabled  (UIF status bit is copied
-  *        to TIMx_CNT register bit 31)
-  * @param  __CNT__ Counter value
-  * @retval UIF status bit
-  */
-#define __LL_TIM_GETFLAG_UIFCPY(__CNT__)  \
-  (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
-
-/**
-  * @brief  HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
-  * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
-  * @param  __TIMCLK__ timer input clock frequency (in Hz)
-  * @param  __CKD__ This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
-  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
-  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
-  * @param  __DT__ deadtime duration (in ns)
-  * @retval DTG[0:7]
-  */
-#define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__)  \
-  ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))    ?  \
-    (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__)))  & DT_DELAY_1) :      \
-    (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))  ?  \
-    (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__),   \
-                                                 (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
-    (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))  ?  \
-    (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__),  \
-                                                 (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
-    (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ?  \
-    (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__),  \
-                                                 (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
-    0U)
-
-/**
-  * @brief  HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
-  * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
-  * @param  __TIMCLK__ timer input clock frequency (in Hz)
-  * @param  __CNTCLK__ counter clock frequency (in Hz)
-  * @retval Prescaler value  (between Min_Data=0 and Max_Data=65535)
-  */
-#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__)   \
-  (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U)
-
-/**
-  * @brief  HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
-  * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
-  * @param  __TIMCLK__ timer input clock frequency (in Hz)
-  * @param  __PSC__ prescaler
-  * @param  __FREQ__ output signal frequency (in Hz)
-  * @retval  Auto-reload value  (between Min_Data=0 and Max_Data=65535)
-  */
-#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
-  ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
-
-/**
-  * @brief  HELPER macro calculating the compare value required to achieve the required timer output compare
-  *         active/inactive delay.
-  * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
-  * @param  __TIMCLK__ timer input clock frequency (in Hz)
-  * @param  __PSC__ prescaler
-  * @param  __DELAY__ timer output compare active/inactive delay (in us)
-  * @retval Compare value  (between Min_Data=0 and Max_Data=65535)
-  */
-#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__)  \
-  ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
-              / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
-
-/**
-  * @brief  HELPER macro calculating the auto-reload value to achieve the required pulse duration
-  *         (when the timer operates in one pulse mode).
-  * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
-  * @param  __TIMCLK__ timer input clock frequency (in Hz)
-  * @param  __PSC__ prescaler
-  * @param  __DELAY__ timer output compare active/inactive delay (in us)
-  * @param  __PULSE__ pulse duration (in us)
-  * @retval Auto-reload value  (between Min_Data=0 and Max_Data=65535)
-  */
-#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__)  \
-  ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
-              + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
-
-/**
-  * @brief  HELPER macro retrieving the ratio of the input capture prescaler
-  * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
-  * @param  __ICPSC__ This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_ICPSC_DIV1
-  *         @arg @ref LL_TIM_ICPSC_DIV2
-  *         @arg @ref LL_TIM_ICPSC_DIV4
-  *         @arg @ref LL_TIM_ICPSC_DIV8
-  * @retval Input capture prescaler ratio (1, 2, 4 or 8)
-  */
-#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__)  \
-  ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
-
-
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
-  * @{
-  */
-
-/** @defgroup TIM_LL_EF_Time_Base Time Base configuration
-  * @{
-  */
-/**
-  * @brief  Enable timer counter.
-  * @rmtoll CR1          CEN           LL_TIM_EnableCounter
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->CR1, TIM_CR1_CEN);
-}
-
-/**
-  * @brief  Disable timer counter.
-  * @rmtoll CR1          CEN           LL_TIM_DisableCounter
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
-}
-
-/**
-  * @brief  Indicates whether the timer counter is enabled.
-  * @rmtoll CR1          CEN           LL_TIM_IsEnabledCounter
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable update event generation.
-  * @rmtoll CR1          UDIS          LL_TIM_EnableUpdateEvent
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
-}
-
-/**
-  * @brief  Disable update event generation.
-  * @rmtoll CR1          UDIS          LL_TIM_DisableUpdateEvent
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
-}
-
-/**
-  * @brief  Indicates whether update event generation is enabled.
-  * @rmtoll CR1          UDIS          LL_TIM_IsEnabledUpdateEvent
-  * @param  TIMx Timer instance
-  * @retval Inverted state of bit (0 or 1).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Set update event source
-  * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
-  *       generate an update interrupt or DMA request if enabled:
-  *        - Counter overflow/underflow
-  *        - Setting the UG bit
-  *        - Update generation through the slave mode controller
-  * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
-  *       overflow/underflow generates an update interrupt or DMA request if enabled.
-  * @rmtoll CR1          URS           LL_TIM_SetUpdateSource
-  * @param  TIMx Timer instance
-  * @param  UpdateSource This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_UPDATESOURCE_REGULAR
-  *         @arg @ref LL_TIM_UPDATESOURCE_COUNTER
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
-{
-  MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
-}
-
-/**
-  * @brief  Get actual event update source
-  * @rmtoll CR1          URS           LL_TIM_GetUpdateSource
-  * @param  TIMx Timer instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_TIM_UPDATESOURCE_REGULAR
-  *         @arg @ref LL_TIM_UPDATESOURCE_COUNTER
-  */
-__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
-}
-
-/**
-  * @brief  Set one pulse mode (one shot v.s. repetitive).
-  * @rmtoll CR1          OPM           LL_TIM_SetOnePulseMode
-  * @param  TIMx Timer instance
-  * @param  OnePulseMode This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
-  *         @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
-{
-  MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
-}
-
-/**
-  * @brief  Get actual one pulse mode.
-  * @rmtoll CR1          OPM           LL_TIM_GetOnePulseMode
-  * @param  TIMx Timer instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
-  *         @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
-  */
-__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
-}
-
-/**
-  * @brief  Set the timer counter counting mode.
-  * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
-  *       check whether or not the counter mode selection feature is supported
-  *       by a timer instance.
-  * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
-  *       requires a timer reset to avoid unexpected direction
-  *       due to DIR bit readonly in center aligned mode.
-  * @rmtoll CR1          DIR           LL_TIM_SetCounterMode\n
-  *         CR1          CMS           LL_TIM_SetCounterMode
-  * @param  TIMx Timer instance
-  * @param  CounterMode This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_COUNTERMODE_UP
-  *         @arg @ref LL_TIM_COUNTERMODE_DOWN
-  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
-  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
-  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
-{
-  MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
-}
-
-/**
-  * @brief  Get actual counter mode.
-  * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
-  *       check whether or not the counter mode selection feature is supported
-  *       by a timer instance.
-  * @rmtoll CR1          DIR           LL_TIM_GetCounterMode\n
-  *         CR1          CMS           LL_TIM_GetCounterMode
-  * @param  TIMx Timer instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_TIM_COUNTERMODE_UP
-  *         @arg @ref LL_TIM_COUNTERMODE_DOWN
-  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
-  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
-  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
-  */
-__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
-{
-  uint32_t counter_mode;
-
-  counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS));
-
-  if (counter_mode == 0U)
-  {
-    counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
-  }
-
-  return counter_mode;
-}
-
-/**
-  * @brief  Enable auto-reload (ARR) preload.
-  * @rmtoll CR1          ARPE          LL_TIM_EnableARRPreload
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
-}
-
-/**
-  * @brief  Disable auto-reload (ARR) preload.
-  * @rmtoll CR1          ARPE          LL_TIM_DisableARRPreload
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
-}
-
-/**
-  * @brief  Indicates whether auto-reload (ARR) preload is enabled.
-  * @rmtoll CR1          ARPE          LL_TIM_IsEnabledARRPreload
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Set the division ratio between the timer clock  and the sampling clock used by the dead-time generators
-  *         (when supported) and the digital filters.
-  * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
-  *       whether or not the clock division feature is supported by the timer
-  *       instance.
-  * @rmtoll CR1          CKD           LL_TIM_SetClockDivision
-  * @param  TIMx Timer instance
-  * @param  ClockDivision This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
-  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
-  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
-{
-  MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
-}
-
-/**
-  * @brief  Get the actual division ratio between the timer clock  and the sampling clock used by the dead-time
-  *         generators (when supported) and the digital filters.
-  * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
-  *       whether or not the clock division feature is supported by the timer
-  *       instance.
-  * @rmtoll CR1          CKD           LL_TIM_GetClockDivision
-  * @param  TIMx Timer instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
-  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
-  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
-  */
-__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
-}
-
-/**
-  * @brief  Set the counter value.
-  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports a 32 bits counter.
-  * @rmtoll CNT          CNT           LL_TIM_SetCounter
-  * @param  TIMx Timer instance
-  * @param  Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
-{
-  WRITE_REG(TIMx->CNT, Counter);
-}
-
-/**
-  * @brief  Get the counter value.
-  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports a 32 bits counter.
-  * @rmtoll CNT          CNT           LL_TIM_GetCounter
-  * @param  TIMx Timer instance
-  * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
-  */
-__STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_REG(TIMx->CNT));
-}
-
-/**
-  * @brief  Get the current direction of the counter
-  * @rmtoll CR1          DIR           LL_TIM_GetDirection
-  * @param  TIMx Timer instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_TIM_COUNTERDIRECTION_UP
-  *         @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
-  */
-__STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
-}
-
-/**
-  * @brief  Set the prescaler value.
-  * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
-  * @note The prescaler can be changed on the fly as this control register is buffered. The new
-  *       prescaler ratio is taken into account at the next update event.
-  * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
-  * @rmtoll PSC          PSC           LL_TIM_SetPrescaler
-  * @param  TIMx Timer instance
-  * @param  Prescaler between Min_Data=0 and Max_Data=65535
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
-{
-  WRITE_REG(TIMx->PSC, Prescaler);
-}
-
-/**
-  * @brief  Get the prescaler value.
-  * @rmtoll PSC          PSC           LL_TIM_GetPrescaler
-  * @param  TIMx Timer instance
-  * @retval  Prescaler value between Min_Data=0 and Max_Data=65535
-  */
-__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_REG(TIMx->PSC));
-}
-
-/**
-  * @brief  Set the auto-reload value.
-  * @note The counter is blocked while the auto-reload value is null.
-  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports a 32 bits counter.
-  * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
-  * @rmtoll ARR          ARR           LL_TIM_SetAutoReload
-  * @param  TIMx Timer instance
-  * @param  AutoReload between Min_Data=0 and Max_Data=65535
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
-{
-  WRITE_REG(TIMx->ARR, AutoReload);
-}
-
-/**
-  * @brief  Get the auto-reload value.
-  * @rmtoll ARR          ARR           LL_TIM_GetAutoReload
-  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports a 32 bits counter.
-  * @param  TIMx Timer instance
-  * @retval Auto-reload value
-  */
-__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_REG(TIMx->ARR));
-}
-
-/**
-  * @brief  Set the repetition counter value.
-  * @note For advanced timer instances RepetitionCounter can be up to 65535.
-  * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports a repetition counter.
-  * @rmtoll RCR          REP           LL_TIM_SetRepetitionCounter
-  * @param  TIMx Timer instance
-  * @param  RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer.
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
-{
-  WRITE_REG(TIMx->RCR, RepetitionCounter);
-}
-
-/**
-  * @brief  Get the repetition counter value.
-  * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports a repetition counter.
-  * @rmtoll RCR          REP           LL_TIM_GetRepetitionCounter
-  * @param  TIMx Timer instance
-  * @retval Repetition counter value
-  */
-__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_REG(TIMx->RCR));
-}
-
-/**
-  * @brief  Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
-  * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read
-  *       in an atomic way.
-  * @rmtoll CR1          UIFREMAP      LL_TIM_EnableUIFRemap
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
-}
-
-/**
-  * @brief  Disable update interrupt flag (UIF) remapping.
-  * @rmtoll CR1          UIFREMAP      LL_TIM_DisableUIFRemap
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
-}
-
-/**
-  * @brief  Indicate whether update interrupt flag (UIF) copy is set.
-  * @param  Counter Counter value
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(uint32_t Counter)
-{
-  return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
-  * @{
-  */
-/**
-  * @brief  Enable  the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
-  * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
-  *       they are updated only when a commutation event (COM) occurs.
-  * @note Only on channels that have a complementary output.
-  * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance is able to generate a commutation event.
-  * @rmtoll CR2          CCPC          LL_TIM_CC_EnablePreload
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
-}
-
-/**
-  * @brief  Disable  the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
-  * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance is able to generate a commutation event.
-  * @rmtoll CR2          CCPC          LL_TIM_CC_DisablePreload
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
-}
-
-/**
-  * @brief  Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
-  * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance is able to generate a commutation event.
-  * @rmtoll CR2          CCUS          LL_TIM_CC_SetUpdate
-  * @param  TIMx Timer instance
-  * @param  CCUpdateSource This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
-  *         @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
-{
-  MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
-}
-
-/**
-  * @brief  Set the trigger of the capture/compare DMA request.
-  * @rmtoll CR2          CCDS          LL_TIM_CC_SetDMAReqTrigger
-  * @param  TIMx Timer instance
-  * @param  DMAReqTrigger This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CCDMAREQUEST_CC
-  *         @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
-{
-  MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
-}
-
-/**
-  * @brief  Get actual trigger of the capture/compare DMA request.
-  * @rmtoll CR2          CCDS          LL_TIM_CC_GetDMAReqTrigger
-  * @param  TIMx Timer instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_TIM_CCDMAREQUEST_CC
-  *         @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
-  */
-__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
-}
-
-/**
-  * @brief  Set the lock level to freeze the
-  *         configuration of several capture/compare parameters.
-  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
-  *       the lock mechanism is supported by a timer instance.
-  * @rmtoll BDTR         LOCK          LL_TIM_CC_SetLockLevel
-  * @param  TIMx Timer instance
-  * @param  LockLevel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_LOCKLEVEL_OFF
-  *         @arg @ref LL_TIM_LOCKLEVEL_1
-  *         @arg @ref LL_TIM_LOCKLEVEL_2
-  *         @arg @ref LL_TIM_LOCKLEVEL_3
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
-{
-  MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
-}
-
-/**
-  * @brief  Enable capture/compare channels.
-  * @rmtoll CCER         CC1E          LL_TIM_CC_EnableChannel\n
-  *         CCER         CC1NE         LL_TIM_CC_EnableChannel\n
-  *         CCER         CC2E          LL_TIM_CC_EnableChannel\n
-  *         CCER         CC2NE         LL_TIM_CC_EnableChannel\n
-  *         CCER         CC3E          LL_TIM_CC_EnableChannel\n
-  *         CCER         CC3NE         LL_TIM_CC_EnableChannel\n
-  *         CCER         CC4E          LL_TIM_CC_EnableChannel\n
-  *         CCER         CC5E          LL_TIM_CC_EnableChannel\n
-  *         CCER         CC6E          LL_TIM_CC_EnableChannel
-  * @param  TIMx Timer instance
-  * @param  Channels This parameter can be a combination of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH1N
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH2N
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH3N
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  *         @arg @ref LL_TIM_CHANNEL_CH5
-  *         @arg @ref LL_TIM_CHANNEL_CH6
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
-{
-  SET_BIT(TIMx->CCER, Channels);
-}
-
-/**
-  * @brief  Disable capture/compare channels.
-  * @rmtoll CCER         CC1E          LL_TIM_CC_DisableChannel\n
-  *         CCER         CC1NE         LL_TIM_CC_DisableChannel\n
-  *         CCER         CC2E          LL_TIM_CC_DisableChannel\n
-  *         CCER         CC2NE         LL_TIM_CC_DisableChannel\n
-  *         CCER         CC3E          LL_TIM_CC_DisableChannel\n
-  *         CCER         CC3NE         LL_TIM_CC_DisableChannel\n
-  *         CCER         CC4E          LL_TIM_CC_DisableChannel\n
-  *         CCER         CC5E          LL_TIM_CC_DisableChannel\n
-  *         CCER         CC6E          LL_TIM_CC_DisableChannel
-  * @param  TIMx Timer instance
-  * @param  Channels This parameter can be a combination of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH1N
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH2N
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH3N
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  *         @arg @ref LL_TIM_CHANNEL_CH5
-  *         @arg @ref LL_TIM_CHANNEL_CH6
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
-{
-  CLEAR_BIT(TIMx->CCER, Channels);
-}
-
-/**
-  * @brief  Indicate whether channel(s) is(are) enabled.
-  * @rmtoll CCER         CC1E          LL_TIM_CC_IsEnabledChannel\n
-  *         CCER         CC1NE         LL_TIM_CC_IsEnabledChannel\n
-  *         CCER         CC2E          LL_TIM_CC_IsEnabledChannel\n
-  *         CCER         CC2NE         LL_TIM_CC_IsEnabledChannel\n
-  *         CCER         CC3E          LL_TIM_CC_IsEnabledChannel\n
-  *         CCER         CC3NE         LL_TIM_CC_IsEnabledChannel\n
-  *         CCER         CC4E          LL_TIM_CC_IsEnabledChannel\n
-  *         CCER         CC5E          LL_TIM_CC_IsEnabledChannel\n
-  *         CCER         CC6E          LL_TIM_CC_IsEnabledChannel
-  * @param  TIMx Timer instance
-  * @param  Channels This parameter can be a combination of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH1N
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH2N
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH3N
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  *         @arg @ref LL_TIM_CHANNEL_CH5
-  *         @arg @ref LL_TIM_CHANNEL_CH6
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
-{
-  return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
-  * @{
-  */
-/**
-  * @brief  Configure an output channel.
-  * @rmtoll CCMR1        CC1S          LL_TIM_OC_ConfigOutput\n
-  *         CCMR1        CC2S          LL_TIM_OC_ConfigOutput\n
-  *         CCMR2        CC3S          LL_TIM_OC_ConfigOutput\n
-  *         CCMR2        CC4S          LL_TIM_OC_ConfigOutput\n
-  *         CCMR3        CC5S          LL_TIM_OC_ConfigOutput\n
-  *         CCMR3        CC6S          LL_TIM_OC_ConfigOutput\n
-  *         CCER         CC1P          LL_TIM_OC_ConfigOutput\n
-  *         CCER         CC2P          LL_TIM_OC_ConfigOutput\n
-  *         CCER         CC3P          LL_TIM_OC_ConfigOutput\n
-  *         CCER         CC4P          LL_TIM_OC_ConfigOutput\n
-  *         CCER         CC5P          LL_TIM_OC_ConfigOutput\n
-  *         CCER         CC6P          LL_TIM_OC_ConfigOutput\n
-  *         CR2          OIS1          LL_TIM_OC_ConfigOutput\n
-  *         CR2          OIS2          LL_TIM_OC_ConfigOutput\n
-  *         CR2          OIS3          LL_TIM_OC_ConfigOutput\n
-  *         CR2          OIS4          LL_TIM_OC_ConfigOutput\n
-  *         CR2          OIS5          LL_TIM_OC_ConfigOutput\n
-  *         CR2          OIS6          LL_TIM_OC_ConfigOutput
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  *         @arg @ref LL_TIM_CHANNEL_CH5
-  *         @arg @ref LL_TIM_CHANNEL_CH6
-  * @param  Configuration This parameter must be a combination of all the following values:
-  *         @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
-  *         @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
-  MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
-             (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
-  MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
-             (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
-}
-
-/**
-  * @brief  Define the behavior of the output reference signal OCxREF from which
-  *         OCx and OCxN (when relevant) are derived.
-  * @rmtoll CCMR1        OC1M          LL_TIM_OC_SetMode\n
-  *         CCMR1        OC2M          LL_TIM_OC_SetMode\n
-  *         CCMR2        OC3M          LL_TIM_OC_SetMode\n
-  *         CCMR2        OC4M          LL_TIM_OC_SetMode\n
-  *         CCMR3        OC5M          LL_TIM_OC_SetMode\n
-  *         CCMR3        OC6M          LL_TIM_OC_SetMode
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  *         @arg @ref LL_TIM_CHANNEL_CH5
-  *         @arg @ref LL_TIM_CHANNEL_CH6
-  * @param  Mode This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_OCMODE_FROZEN
-  *         @arg @ref LL_TIM_OCMODE_ACTIVE
-  *         @arg @ref LL_TIM_OCMODE_INACTIVE
-  *         @arg @ref LL_TIM_OCMODE_TOGGLE
-  *         @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
-  *         @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
-  *         @arg @ref LL_TIM_OCMODE_PWM1
-  *         @arg @ref LL_TIM_OCMODE_PWM2
-  *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
-  *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
-  *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
-  *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
-  *         @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
-  *         @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M  | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
-}
-
-/**
-  * @brief  Get the output compare mode of an output channel.
-  * @rmtoll CCMR1        OC1M          LL_TIM_OC_GetMode\n
-  *         CCMR1        OC2M          LL_TIM_OC_GetMode\n
-  *         CCMR2        OC3M          LL_TIM_OC_GetMode\n
-  *         CCMR2        OC4M          LL_TIM_OC_GetMode\n
-  *         CCMR3        OC5M          LL_TIM_OC_GetMode\n
-  *         CCMR3        OC6M          LL_TIM_OC_GetMode
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  *         @arg @ref LL_TIM_CHANNEL_CH5
-  *         @arg @ref LL_TIM_CHANNEL_CH6
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_TIM_OCMODE_FROZEN
-  *         @arg @ref LL_TIM_OCMODE_ACTIVE
-  *         @arg @ref LL_TIM_OCMODE_INACTIVE
-  *         @arg @ref LL_TIM_OCMODE_TOGGLE
-  *         @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
-  *         @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
-  *         @arg @ref LL_TIM_OCMODE_PWM1
-  *         @arg @ref LL_TIM_OCMODE_PWM2
-  *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
-  *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
-  *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
-  *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
-  *         @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
-  *         @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
-  */
-__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
-}
-
-/**
-  * @brief  Set the polarity of an output channel.
-  * @rmtoll CCER         CC1P          LL_TIM_OC_SetPolarity\n
-  *         CCER         CC1NP         LL_TIM_OC_SetPolarity\n
-  *         CCER         CC2P          LL_TIM_OC_SetPolarity\n
-  *         CCER         CC2NP         LL_TIM_OC_SetPolarity\n
-  *         CCER         CC3P          LL_TIM_OC_SetPolarity\n
-  *         CCER         CC3NP         LL_TIM_OC_SetPolarity\n
-  *         CCER         CC4P          LL_TIM_OC_SetPolarity\n
-  *         CCER         CC5P          LL_TIM_OC_SetPolarity\n
-  *         CCER         CC6P          LL_TIM_OC_SetPolarity
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH1N
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH2N
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH3N
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  *         @arg @ref LL_TIM_CHANNEL_CH5
-  *         @arg @ref LL_TIM_CHANNEL_CH6
-  * @param  Polarity This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_OCPOLARITY_HIGH
-  *         @arg @ref LL_TIM_OCPOLARITY_LOW
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),  Polarity << SHIFT_TAB_CCxP[iChannel]);
-}
-
-/**
-  * @brief  Get the polarity of an output channel.
-  * @rmtoll CCER         CC1P          LL_TIM_OC_GetPolarity\n
-  *         CCER         CC1NP         LL_TIM_OC_GetPolarity\n
-  *         CCER         CC2P          LL_TIM_OC_GetPolarity\n
-  *         CCER         CC2NP         LL_TIM_OC_GetPolarity\n
-  *         CCER         CC3P          LL_TIM_OC_GetPolarity\n
-  *         CCER         CC3NP         LL_TIM_OC_GetPolarity\n
-  *         CCER         CC4P          LL_TIM_OC_GetPolarity\n
-  *         CCER         CC5P          LL_TIM_OC_GetPolarity\n
-  *         CCER         CC6P          LL_TIM_OC_GetPolarity
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH1N
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH2N
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH3N
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  *         @arg @ref LL_TIM_CHANNEL_CH5
-  *         @arg @ref LL_TIM_CHANNEL_CH6
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_TIM_OCPOLARITY_HIGH
-  *         @arg @ref LL_TIM_OCPOLARITY_LOW
-  */
-__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
-}
-
-/**
-  * @brief  Set the IDLE state of an output channel
-  * @note This function is significant only for the timer instances
-  *       supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
-  *       can be used to check whether or not a timer instance provides
-  *       a break input.
-  * @rmtoll CR2         OIS1          LL_TIM_OC_SetIdleState\n
-  *         CR2         OIS2N         LL_TIM_OC_SetIdleState\n
-  *         CR2         OIS2          LL_TIM_OC_SetIdleState\n
-  *         CR2         OIS2N         LL_TIM_OC_SetIdleState\n
-  *         CR2         OIS3          LL_TIM_OC_SetIdleState\n
-  *         CR2         OIS3N         LL_TIM_OC_SetIdleState\n
-  *         CR2         OIS4          LL_TIM_OC_SetIdleState\n
-  *         CR2         OIS5          LL_TIM_OC_SetIdleState\n
-  *         CR2         OIS6          LL_TIM_OC_SetIdleState
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH1N
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH2N
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH3N
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  *         @arg @ref LL_TIM_CHANNEL_CH5
-  *         @arg @ref LL_TIM_CHANNEL_CH6
-  * @param  IdleState This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_OCIDLESTATE_LOW
-  *         @arg @ref LL_TIM_OCIDLESTATE_HIGH
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),  IdleState << SHIFT_TAB_OISx[iChannel]);
-}
-
-/**
-  * @brief  Get the IDLE state of an output channel
-  * @rmtoll CR2         OIS1          LL_TIM_OC_GetIdleState\n
-  *         CR2         OIS2N         LL_TIM_OC_GetIdleState\n
-  *         CR2         OIS2          LL_TIM_OC_GetIdleState\n
-  *         CR2         OIS2N         LL_TIM_OC_GetIdleState\n
-  *         CR2         OIS3          LL_TIM_OC_GetIdleState\n
-  *         CR2         OIS3N         LL_TIM_OC_GetIdleState\n
-  *         CR2         OIS4          LL_TIM_OC_GetIdleState\n
-  *         CR2         OIS5          LL_TIM_OC_GetIdleState\n
-  *         CR2         OIS6          LL_TIM_OC_GetIdleState
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH1N
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH2N
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH3N
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  *         @arg @ref LL_TIM_CHANNEL_CH5
-  *         @arg @ref LL_TIM_CHANNEL_CH6
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_TIM_OCIDLESTATE_LOW
-  *         @arg @ref LL_TIM_OCIDLESTATE_HIGH
-  */
-__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
-}
-
-/**
-  * @brief  Enable fast mode for the output channel.
-  * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
-  * @rmtoll CCMR1        OC1FE          LL_TIM_OC_EnableFast\n
-  *         CCMR1        OC2FE          LL_TIM_OC_EnableFast\n
-  *         CCMR2        OC3FE          LL_TIM_OC_EnableFast\n
-  *         CCMR2        OC4FE          LL_TIM_OC_EnableFast\n
-  *         CCMR3        OC5FE          LL_TIM_OC_EnableFast\n
-  *         CCMR3        OC6FE          LL_TIM_OC_EnableFast
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  *         @arg @ref LL_TIM_CHANNEL_CH5
-  *         @arg @ref LL_TIM_CHANNEL_CH6
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
-
-}
-
-/**
-  * @brief  Disable fast mode for the output channel.
-  * @rmtoll CCMR1        OC1FE          LL_TIM_OC_DisableFast\n
-  *         CCMR1        OC2FE          LL_TIM_OC_DisableFast\n
-  *         CCMR2        OC3FE          LL_TIM_OC_DisableFast\n
-  *         CCMR2        OC4FE          LL_TIM_OC_DisableFast\n
-  *         CCMR3        OC5FE          LL_TIM_OC_DisableFast\n
-  *         CCMR3        OC6FE          LL_TIM_OC_DisableFast
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  *         @arg @ref LL_TIM_CHANNEL_CH5
-  *         @arg @ref LL_TIM_CHANNEL_CH6
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
-
-}
-
-/**
-  * @brief  Indicates whether fast mode is enabled for the output channel.
-  * @rmtoll CCMR1        OC1FE          LL_TIM_OC_IsEnabledFast\n
-  *         CCMR1        OC2FE          LL_TIM_OC_IsEnabledFast\n
-  *         CCMR2        OC3FE          LL_TIM_OC_IsEnabledFast\n
-  *         CCMR2        OC4FE          LL_TIM_OC_IsEnabledFast\n
-  *         CCMR3        OC5FE          LL_TIM_OC_IsEnabledFast\n
-  *         CCMR3        OC6FE          LL_TIM_OC_IsEnabledFast
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  *         @arg @ref LL_TIM_CHANNEL_CH5
-  *         @arg @ref LL_TIM_CHANNEL_CH6
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
-  return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable compare register (TIMx_CCRx) preload for the output channel.
-  * @rmtoll CCMR1        OC1PE          LL_TIM_OC_EnablePreload\n
-  *         CCMR1        OC2PE          LL_TIM_OC_EnablePreload\n
-  *         CCMR2        OC3PE          LL_TIM_OC_EnablePreload\n
-  *         CCMR2        OC4PE          LL_TIM_OC_EnablePreload\n
-  *         CCMR3        OC5PE          LL_TIM_OC_EnablePreload\n
-  *         CCMR3        OC6PE          LL_TIM_OC_EnablePreload
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  *         @arg @ref LL_TIM_CHANNEL_CH5
-  *         @arg @ref LL_TIM_CHANNEL_CH6
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
-}
-
-/**
-  * @brief  Disable compare register (TIMx_CCRx) preload for the output channel.
-  * @rmtoll CCMR1        OC1PE          LL_TIM_OC_DisablePreload\n
-  *         CCMR1        OC2PE          LL_TIM_OC_DisablePreload\n
-  *         CCMR2        OC3PE          LL_TIM_OC_DisablePreload\n
-  *         CCMR2        OC4PE          LL_TIM_OC_DisablePreload\n
-  *         CCMR3        OC5PE          LL_TIM_OC_DisablePreload\n
-  *         CCMR3        OC6PE          LL_TIM_OC_DisablePreload
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  *         @arg @ref LL_TIM_CHANNEL_CH5
-  *         @arg @ref LL_TIM_CHANNEL_CH6
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
-}
-
-/**
-  * @brief  Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
-  * @rmtoll CCMR1        OC1PE          LL_TIM_OC_IsEnabledPreload\n
-  *         CCMR1        OC2PE          LL_TIM_OC_IsEnabledPreload\n
-  *         CCMR2        OC3PE          LL_TIM_OC_IsEnabledPreload\n
-  *         CCMR2        OC4PE          LL_TIM_OC_IsEnabledPreload\n
-  *         CCMR3        OC5PE          LL_TIM_OC_IsEnabledPreload\n
-  *         CCMR3        OC6PE          LL_TIM_OC_IsEnabledPreload
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  *         @arg @ref LL_TIM_CHANNEL_CH5
-  *         @arg @ref LL_TIM_CHANNEL_CH6
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
-  return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable clearing the output channel on an external event.
-  * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
-  * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
-  *       or not a timer instance can clear the OCxREF signal on an external event.
-  * @rmtoll CCMR1        OC1CE          LL_TIM_OC_EnableClear\n
-  *         CCMR1        OC2CE          LL_TIM_OC_EnableClear\n
-  *         CCMR2        OC3CE          LL_TIM_OC_EnableClear\n
-  *         CCMR2        OC4CE          LL_TIM_OC_EnableClear\n
-  *         CCMR3        OC5CE          LL_TIM_OC_EnableClear\n
-  *         CCMR3        OC6CE          LL_TIM_OC_EnableClear
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  *         @arg @ref LL_TIM_CHANNEL_CH5
-  *         @arg @ref LL_TIM_CHANNEL_CH6
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
-}
-
-/**
-  * @brief  Disable clearing the output channel on an external event.
-  * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
-  *       or not a timer instance can clear the OCxREF signal on an external event.
-  * @rmtoll CCMR1        OC1CE          LL_TIM_OC_DisableClear\n
-  *         CCMR1        OC2CE          LL_TIM_OC_DisableClear\n
-  *         CCMR2        OC3CE          LL_TIM_OC_DisableClear\n
-  *         CCMR2        OC4CE          LL_TIM_OC_DisableClear\n
-  *         CCMR3        OC5CE          LL_TIM_OC_DisableClear\n
-  *         CCMR3        OC6CE          LL_TIM_OC_DisableClear
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  *         @arg @ref LL_TIM_CHANNEL_CH5
-  *         @arg @ref LL_TIM_CHANNEL_CH6
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
-}
-
-/**
-  * @brief  Indicates clearing the output channel on an external event is enabled for the output channel.
-  * @note This function enables clearing the output channel on an external event.
-  * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
-  * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
-  *       or not a timer instance can clear the OCxREF signal on an external event.
-  * @rmtoll CCMR1        OC1CE          LL_TIM_OC_IsEnabledClear\n
-  *         CCMR1        OC2CE          LL_TIM_OC_IsEnabledClear\n
-  *         CCMR2        OC3CE          LL_TIM_OC_IsEnabledClear\n
-  *         CCMR2        OC4CE          LL_TIM_OC_IsEnabledClear\n
-  *         CCMR3        OC5CE          LL_TIM_OC_IsEnabledClear\n
-  *         CCMR3        OC6CE          LL_TIM_OC_IsEnabledClear
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  *         @arg @ref LL_TIM_CHANNEL_CH5
-  *         @arg @ref LL_TIM_CHANNEL_CH6
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
-  return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of
-  *         the Ocx and OCxN signals).
-  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
-  *       dead-time insertion feature is supported by a timer instance.
-  * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
-  * @rmtoll BDTR         DTG           LL_TIM_OC_SetDeadTime
-  * @param  TIMx Timer instance
-  * @param  DeadTime between Min_Data=0 and Max_Data=255
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
-{
-  MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
-}
-
-/**
-  * @brief  Set compare value for output channel 1 (TIMx_CCR1).
-  * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
-  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports a 32 bits counter.
-  * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
-  *       output channel 1 is supported by a timer instance.
-  * @rmtoll CCR1         CCR1          LL_TIM_OC_SetCompareCH1
-  * @param  TIMx Timer instance
-  * @param  CompareValue between Min_Data=0 and Max_Data=65535
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
-{
-  WRITE_REG(TIMx->CCR1, CompareValue);
-}
-
-/**
-  * @brief  Set compare value for output channel 2 (TIMx_CCR2).
-  * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
-  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports a 32 bits counter.
-  * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
-  *       output channel 2 is supported by a timer instance.
-  * @rmtoll CCR2         CCR2          LL_TIM_OC_SetCompareCH2
-  * @param  TIMx Timer instance
-  * @param  CompareValue between Min_Data=0 and Max_Data=65535
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
-{
-  WRITE_REG(TIMx->CCR2, CompareValue);
-}
-
-/**
-  * @brief  Set compare value for output channel 3 (TIMx_CCR3).
-  * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
-  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports a 32 bits counter.
-  * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
-  *       output channel is supported by a timer instance.
-  * @rmtoll CCR3         CCR3          LL_TIM_OC_SetCompareCH3
-  * @param  TIMx Timer instance
-  * @param  CompareValue between Min_Data=0 and Max_Data=65535
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
-{
-  WRITE_REG(TIMx->CCR3, CompareValue);
-}
-
-/**
-  * @brief  Set compare value for output channel 4 (TIMx_CCR4).
-  * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
-  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports a 32 bits counter.
-  * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
-  *       output channel 4 is supported by a timer instance.
-  * @rmtoll CCR4         CCR4          LL_TIM_OC_SetCompareCH4
-  * @param  TIMx Timer instance
-  * @param  CompareValue between Min_Data=0 and Max_Data=65535
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
-{
-  WRITE_REG(TIMx->CCR4, CompareValue);
-}
-
-/**
-  * @brief  Set compare value for output channel 5 (TIMx_CCR5).
-  * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
-  *       output channel 5 is supported by a timer instance.
-  * @rmtoll CCR5         CCR5          LL_TIM_OC_SetCompareCH5
-  * @param  TIMx Timer instance
-  * @param  CompareValue between Min_Data=0 and Max_Data=65535
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue)
-{
-  MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue);
-}
-
-/**
-  * @brief  Set compare value for output channel 6 (TIMx_CCR6).
-  * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
-  *       output channel 6 is supported by a timer instance.
-  * @rmtoll CCR6         CCR6          LL_TIM_OC_SetCompareCH6
-  * @param  TIMx Timer instance
-  * @param  CompareValue between Min_Data=0 and Max_Data=65535
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue)
-{
-  WRITE_REG(TIMx->CCR6, CompareValue);
-}
-
-/**
-  * @brief  Get compare value (TIMx_CCR1) set for  output channel 1.
-  * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
-  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports a 32 bits counter.
-  * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
-  *       output channel 1 is supported by a timer instance.
-  * @rmtoll CCR1         CCR1          LL_TIM_OC_GetCompareCH1
-  * @param  TIMx Timer instance
-  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
-  */
-__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_REG(TIMx->CCR1));
-}
-
-/**
-  * @brief  Get compare value (TIMx_CCR2) set for  output channel 2.
-  * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
-  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports a 32 bits counter.
-  * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
-  *       output channel 2 is supported by a timer instance.
-  * @rmtoll CCR2         CCR2          LL_TIM_OC_GetCompareCH2
-  * @param  TIMx Timer instance
-  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
-  */
-__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_REG(TIMx->CCR2));
-}
-
-/**
-  * @brief  Get compare value (TIMx_CCR3) set for  output channel 3.
-  * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
-  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports a 32 bits counter.
-  * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
-  *       output channel 3 is supported by a timer instance.
-  * @rmtoll CCR3         CCR3          LL_TIM_OC_GetCompareCH3
-  * @param  TIMx Timer instance
-  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
-  */
-__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_REG(TIMx->CCR3));
-}
-
-/**
-  * @brief  Get compare value (TIMx_CCR4) set for  output channel 4.
-  * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
-  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports a 32 bits counter.
-  * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
-  *       output channel 4 is supported by a timer instance.
-  * @rmtoll CCR4         CCR4          LL_TIM_OC_GetCompareCH4
-  * @param  TIMx Timer instance
-  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
-  */
-__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_REG(TIMx->CCR4));
-}
-
-/**
-  * @brief  Get compare value (TIMx_CCR5) set for  output channel 5.
-  * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
-  *       output channel 5 is supported by a timer instance.
-  * @rmtoll CCR5         CCR5          LL_TIM_OC_GetCompareCH5
-  * @param  TIMx Timer instance
-  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
-  */
-__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5));
-}
-
-/**
-  * @brief  Get compare value (TIMx_CCR6) set for  output channel 6.
-  * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
-  *       output channel 6 is supported by a timer instance.
-  * @rmtoll CCR6         CCR6          LL_TIM_OC_GetCompareCH6
-  * @param  TIMx Timer instance
-  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
-  */
-__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_REG(TIMx->CCR6));
-}
-
-/**
-  * @brief  Select on which reference signal the OC5REF is combined to.
-  * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports the combined 3-phase PWM mode.
-  * @rmtoll CCR5         GC5C3          LL_TIM_SetCH5CombinedChannels\n
-  *         CCR5         GC5C2          LL_TIM_SetCH5CombinedChannels\n
-  *         CCR5         GC5C1          LL_TIM_SetCH5CombinedChannels
-  * @param  TIMx Timer instance
-  * @param  GroupCH5 This parameter can be a combination of the following values:
-  *         @arg @ref LL_TIM_GROUPCH5_NONE
-  *         @arg @ref LL_TIM_GROUPCH5_OC1REFC
-  *         @arg @ref LL_TIM_GROUPCH5_OC2REFC
-  *         @arg @ref LL_TIM_GROUPCH5_OC3REFC
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5)
-{
-  MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
-  * @{
-  */
-/**
-  * @brief  Configure input channel.
-  * @rmtoll CCMR1        CC1S          LL_TIM_IC_Config\n
-  *         CCMR1        IC1PSC        LL_TIM_IC_Config\n
-  *         CCMR1        IC1F          LL_TIM_IC_Config\n
-  *         CCMR1        CC2S          LL_TIM_IC_Config\n
-  *         CCMR1        IC2PSC        LL_TIM_IC_Config\n
-  *         CCMR1        IC2F          LL_TIM_IC_Config\n
-  *         CCMR2        CC3S          LL_TIM_IC_Config\n
-  *         CCMR2        IC3PSC        LL_TIM_IC_Config\n
-  *         CCMR2        IC3F          LL_TIM_IC_Config\n
-  *         CCMR2        CC4S          LL_TIM_IC_Config\n
-  *         CCMR2        IC4PSC        LL_TIM_IC_Config\n
-  *         CCMR2        IC4F          LL_TIM_IC_Config\n
-  *         CCER         CC1P          LL_TIM_IC_Config\n
-  *         CCER         CC1NP         LL_TIM_IC_Config\n
-  *         CCER         CC2P          LL_TIM_IC_Config\n
-  *         CCER         CC2NP         LL_TIM_IC_Config\n
-  *         CCER         CC3P          LL_TIM_IC_Config\n
-  *         CCER         CC3NP         LL_TIM_IC_Config\n
-  *         CCER         CC4P          LL_TIM_IC_Config\n
-  *         CCER         CC4NP         LL_TIM_IC_Config
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @param  Configuration This parameter must be a combination of all the following values:
-  *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
-  *         @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
-  *         @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
-             ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S))                \
-             << SHIFT_TAB_ICxx[iChannel]);
-  MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
-             (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
-}
-
-/**
-  * @brief  Set the active input.
-  * @rmtoll CCMR1        CC1S          LL_TIM_IC_SetActiveInput\n
-  *         CCMR1        CC2S          LL_TIM_IC_SetActiveInput\n
-  *         CCMR2        CC3S          LL_TIM_IC_SetActiveInput\n
-  *         CCMR2        CC4S          LL_TIM_IC_SetActiveInput
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @param  ICActiveInput This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
-  *         @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
-  *         @arg @ref LL_TIM_ACTIVEINPUT_TRC
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
-}
-
-/**
-  * @brief  Get the current active input.
-  * @rmtoll CCMR1        CC1S          LL_TIM_IC_GetActiveInput\n
-  *         CCMR1        CC2S          LL_TIM_IC_GetActiveInput\n
-  *         CCMR2        CC3S          LL_TIM_IC_GetActiveInput\n
-  *         CCMR2        CC4S          LL_TIM_IC_GetActiveInput
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
-  *         @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
-  *         @arg @ref LL_TIM_ACTIVEINPUT_TRC
-  */
-__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
-}
-
-/**
-  * @brief  Set the prescaler of input channel.
-  * @rmtoll CCMR1        IC1PSC        LL_TIM_IC_SetPrescaler\n
-  *         CCMR1        IC2PSC        LL_TIM_IC_SetPrescaler\n
-  *         CCMR2        IC3PSC        LL_TIM_IC_SetPrescaler\n
-  *         CCMR2        IC4PSC        LL_TIM_IC_SetPrescaler
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @param  ICPrescaler This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_ICPSC_DIV1
-  *         @arg @ref LL_TIM_ICPSC_DIV2
-  *         @arg @ref LL_TIM_ICPSC_DIV4
-  *         @arg @ref LL_TIM_ICPSC_DIV8
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
-}
-
-/**
-  * @brief  Get the current prescaler value acting on an  input channel.
-  * @rmtoll CCMR1        IC1PSC        LL_TIM_IC_GetPrescaler\n
-  *         CCMR1        IC2PSC        LL_TIM_IC_GetPrescaler\n
-  *         CCMR2        IC3PSC        LL_TIM_IC_GetPrescaler\n
-  *         CCMR2        IC4PSC        LL_TIM_IC_GetPrescaler
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_TIM_ICPSC_DIV1
-  *         @arg @ref LL_TIM_ICPSC_DIV2
-  *         @arg @ref LL_TIM_ICPSC_DIV4
-  *         @arg @ref LL_TIM_ICPSC_DIV8
-  */
-__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
-}
-
-/**
-  * @brief  Set the input filter duration.
-  * @rmtoll CCMR1        IC1F          LL_TIM_IC_SetFilter\n
-  *         CCMR1        IC2F          LL_TIM_IC_SetFilter\n
-  *         CCMR2        IC3F          LL_TIM_IC_SetFilter\n
-  *         CCMR2        IC4F          LL_TIM_IC_SetFilter
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @param  ICFilter This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV1
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
-}
-
-/**
-  * @brief  Get the input filter duration.
-  * @rmtoll CCMR1        IC1F          LL_TIM_IC_GetFilter\n
-  *         CCMR1        IC2F          LL_TIM_IC_GetFilter\n
-  *         CCMR2        IC3F          LL_TIM_IC_GetFilter\n
-  *         CCMR2        IC4F          LL_TIM_IC_GetFilter
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV1
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
-  */
-__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
-}
-
-/**
-  * @brief  Set the input channel polarity.
-  * @rmtoll CCER         CC1P          LL_TIM_IC_SetPolarity\n
-  *         CCER         CC1NP         LL_TIM_IC_SetPolarity\n
-  *         CCER         CC2P          LL_TIM_IC_SetPolarity\n
-  *         CCER         CC2NP         LL_TIM_IC_SetPolarity\n
-  *         CCER         CC3P          LL_TIM_IC_SetPolarity\n
-  *         CCER         CC3NP         LL_TIM_IC_SetPolarity\n
-  *         CCER         CC4P          LL_TIM_IC_SetPolarity\n
-  *         CCER         CC4NP         LL_TIM_IC_SetPolarity
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @param  ICPolarity This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_IC_POLARITY_RISING
-  *         @arg @ref LL_TIM_IC_POLARITY_FALLING
-  *         @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
-             ICPolarity << SHIFT_TAB_CCxP[iChannel]);
-}
-
-/**
-  * @brief  Get the current input channel polarity.
-  * @rmtoll CCER         CC1P          LL_TIM_IC_GetPolarity\n
-  *         CCER         CC1NP         LL_TIM_IC_GetPolarity\n
-  *         CCER         CC2P          LL_TIM_IC_GetPolarity\n
-  *         CCER         CC2NP         LL_TIM_IC_GetPolarity\n
-  *         CCER         CC3P          LL_TIM_IC_GetPolarity\n
-  *         CCER         CC3NP         LL_TIM_IC_GetPolarity\n
-  *         CCER         CC4P          LL_TIM_IC_GetPolarity\n
-  *         CCER         CC4NP         LL_TIM_IC_GetPolarity
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_TIM_IC_POLARITY_RISING
-  *         @arg @ref LL_TIM_IC_POLARITY_FALLING
-  *         @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
-  */
-__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
-          SHIFT_TAB_CCxP[iChannel]);
-}
-
-/**
-  * @brief  Connect the TIMx_CH1, CH2 and CH3 pins  to the TI1 input (XOR combination).
-  * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance provides an XOR input.
-  * @rmtoll CR2          TI1S          LL_TIM_IC_EnableXORCombination
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
-}
-
-/**
-  * @brief  Disconnect the TIMx_CH1, CH2 and CH3 pins  from the TI1 input.
-  * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance provides an XOR input.
-  * @rmtoll CR2          TI1S          LL_TIM_IC_DisableXORCombination
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
-}
-
-/**
-  * @brief  Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
-  * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
-  * a timer instance provides an XOR input.
-  * @rmtoll CR2          TI1S          LL_TIM_IC_IsEnabledXORCombination
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get captured value for input channel 1.
-  * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
-  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports a 32 bits counter.
-  * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
-  *       input channel 1 is supported by a timer instance.
-  * @rmtoll CCR1         CCR1          LL_TIM_IC_GetCaptureCH1
-  * @param  TIMx Timer instance
-  * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
-  */
-__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_REG(TIMx->CCR1));
-}
-
-/**
-  * @brief  Get captured value for input channel 2.
-  * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
-  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports a 32 bits counter.
-  * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
-  *       input channel 2 is supported by a timer instance.
-  * @rmtoll CCR2         CCR2          LL_TIM_IC_GetCaptureCH2
-  * @param  TIMx Timer instance
-  * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
-  */
-__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_REG(TIMx->CCR2));
-}
-
-/**
-  * @brief  Get captured value for input channel 3.
-  * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
-  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports a 32 bits counter.
-  * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
-  *       input channel 3 is supported by a timer instance.
-  * @rmtoll CCR3         CCR3          LL_TIM_IC_GetCaptureCH3
-  * @param  TIMx Timer instance
-  * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
-  */
-__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_REG(TIMx->CCR3));
-}
-
-/**
-  * @brief  Get captured value for input channel 4.
-  * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
-  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports a 32 bits counter.
-  * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
-  *       input channel 4 is supported by a timer instance.
-  * @rmtoll CCR4         CCR4          LL_TIM_IC_GetCaptureCH4
-  * @param  TIMx Timer instance
-  * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
-  */
-__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_REG(TIMx->CCR4));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
-  * @{
-  */
-/**
-  * @brief  Enable external clock mode 2.
-  * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
-  * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports external clock mode2.
-  * @rmtoll SMCR         ECE           LL_TIM_EnableExternalClock
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
-}
-
-/**
-  * @brief  Disable external clock mode 2.
-  * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports external clock mode2.
-  * @rmtoll SMCR         ECE           LL_TIM_DisableExternalClock
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
-}
-
-/**
-  * @brief  Indicate whether external clock mode 2 is enabled.
-  * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports external clock mode2.
-  * @rmtoll SMCR         ECE           LL_TIM_IsEnabledExternalClock
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Set the clock source of the counter clock.
-  * @note when selected clock source is external clock mode 1, the timer input
-  *       the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
-  *       function. This timer input must be configured by calling
-  *       the @ref LL_TIM_IC_Config() function.
-  * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports external clock mode1.
-  * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports external clock mode2.
-  * @rmtoll SMCR         SMS           LL_TIM_SetClockSource\n
-  *         SMCR         ECE           LL_TIM_SetClockSource
-  * @param  TIMx Timer instance
-  * @param  ClockSource This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
-  *         @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
-  *         @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
-{
-  MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
-}
-
-/**
-  * @brief  Set the encoder interface mode.
-  * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports the encoder mode.
-  * @rmtoll SMCR         SMS           LL_TIM_SetEncoderMode
-  * @param  TIMx Timer instance
-  * @param  EncoderMode This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_ENCODERMODE_X2_TI1
-  *         @arg @ref LL_TIM_ENCODERMODE_X2_TI2
-  *         @arg @ref LL_TIM_ENCODERMODE_X4_TI12
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
-{
-  MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
-  * @{
-  */
-/**
-  * @brief  Set the trigger output (TRGO) used for timer synchronization .
-  * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance can operate as a master timer.
-  * @rmtoll CR2          MMS           LL_TIM_SetTriggerOutput
-  * @param  TIMx Timer instance
-  * @param  TimerSynchronization This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_TRGO_RESET
-  *         @arg @ref LL_TIM_TRGO_ENABLE
-  *         @arg @ref LL_TIM_TRGO_UPDATE
-  *         @arg @ref LL_TIM_TRGO_CC1IF
-  *         @arg @ref LL_TIM_TRGO_OC1REF
-  *         @arg @ref LL_TIM_TRGO_OC2REF
-  *         @arg @ref LL_TIM_TRGO_OC3REF
-  *         @arg @ref LL_TIM_TRGO_OC4REF
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
-{
-  MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
-}
-
-/**
-  * @brief  Set the trigger output 2 (TRGO2) used for ADC synchronization .
-  * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance can be used for ADC synchronization.
-  * @rmtoll CR2          MMS2          LL_TIM_SetTriggerOutput2
-  * @param  TIMx Timer Instance
-  * @param  ADCSynchronization This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_TRGO2_RESET
-  *         @arg @ref LL_TIM_TRGO2_ENABLE
-  *         @arg @ref LL_TIM_TRGO2_UPDATE
-  *         @arg @ref LL_TIM_TRGO2_CC1F
-  *         @arg @ref LL_TIM_TRGO2_OC1
-  *         @arg @ref LL_TIM_TRGO2_OC2
-  *         @arg @ref LL_TIM_TRGO2_OC3
-  *         @arg @ref LL_TIM_TRGO2_OC4
-  *         @arg @ref LL_TIM_TRGO2_OC5
-  *         @arg @ref LL_TIM_TRGO2_OC6
-  *         @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING
-  *         @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING
-  *         @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING
-  *         @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
-  *         @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING
-  *         @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
-{
-  MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization);
-}
-
-/**
-  * @brief  Set the synchronization mode of a slave timer.
-  * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance can operate as a slave timer.
-  * @rmtoll SMCR         SMS           LL_TIM_SetSlaveMode
-  * @param  TIMx Timer instance
-  * @param  SlaveMode This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_SLAVEMODE_DISABLED
-  *         @arg @ref LL_TIM_SLAVEMODE_RESET
-  *         @arg @ref LL_TIM_SLAVEMODE_GATED
-  *         @arg @ref LL_TIM_SLAVEMODE_TRIGGER
-  *         @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
-{
-  MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
-}
-
-/**
-  * @brief  Set the selects the trigger input to be used to synchronize the counter.
-  * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance can operate as a slave timer.
-  * @rmtoll SMCR         TS            LL_TIM_SetTriggerInput
-  * @param  TIMx Timer instance
-  * @param  TriggerInput This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_TS_ITR0
-  *         @arg @ref LL_TIM_TS_ITR1
-  *         @arg @ref LL_TIM_TS_ITR2
-  *         @arg @ref LL_TIM_TS_ITR3
-  *         @arg @ref LL_TIM_TS_ITR4
-  *         @arg @ref LL_TIM_TS_ITR5
-  *         @arg @ref LL_TIM_TS_ITR6
-  *         @arg @ref LL_TIM_TS_ITR7
-  *         @arg @ref LL_TIM_TS_ITR8 (*)
-  *         @arg @ref LL_TIM_TS_ITR9 (*)
-  *         @arg @ref LL_TIM_TS_ITR10 (*)
-  *         @arg @ref LL_TIM_TS_ITR11 (*)
-  *         @arg @ref LL_TIM_TS_ITR12 (*)
-  *         @arg @ref LL_TIM_TS_ITR13 (*)
-  *         @arg @ref LL_TIM_TS_TI1F_ED
-  *         @arg @ref LL_TIM_TS_TI1FP1
-  *         @arg @ref LL_TIM_TS_TI2FP2
-  *         @arg @ref LL_TIM_TS_ETRF
-  *
-  *      (*)  Value not defined in all devices.
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
-{
-  MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
-}
-
-/**
-  * @brief  Enable the Master/Slave mode.
-  * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance can operate as a slave timer.
-  * @rmtoll SMCR         MSM           LL_TIM_EnableMasterSlaveMode
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
-}
-
-/**
-  * @brief  Disable the Master/Slave mode.
-  * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance can operate as a slave timer.
-  * @rmtoll SMCR         MSM           LL_TIM_DisableMasterSlaveMode
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
-}
-
-/**
-  * @brief Indicates whether the Master/Slave mode is enabled.
-  * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
-  * a timer instance can operate as a slave timer.
-  * @rmtoll SMCR         MSM           LL_TIM_IsEnabledMasterSlaveMode
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Configure the external trigger (ETR) input.
-  * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance provides an external trigger input.
-  * @rmtoll SMCR         ETP           LL_TIM_ConfigETR\n
-  *         SMCR         ETPS          LL_TIM_ConfigETR\n
-  *         SMCR         ETF           LL_TIM_ConfigETR
-  * @param  TIMx Timer instance
-  * @param  ETRPolarity This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
-  *         @arg @ref LL_TIM_ETR_POLARITY_INVERTED
-  * @param  ETRPrescaler This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_ETR_PRESCALER_DIV1
-  *         @arg @ref LL_TIM_ETR_PRESCALER_DIV2
-  *         @arg @ref LL_TIM_ETR_PRESCALER_DIV4
-  *         @arg @ref LL_TIM_ETR_PRESCALER_DIV8
-  * @param  ETRFilter This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV1
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
-                                      uint32_t ETRFilter)
-{
-  MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
-}
-
-/**
-  * @brief  Select the external trigger (ETR) input source.
-  * @note Macro IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or
-  *       not a timer instance supports ETR source selection.
-  * @rmtoll AF1          ETRSEL        LL_TIM_SetETRSource
-  * @param  TIMx Timer instance
-  * @param  ETRSource This parameter can be one of the following values:
-  *      For TIM1, the parameter is one of the following values:
-  *         @arg LL_TIM_TIM1_ETRSOURCE_GPIO:               TIM1_ETR is connected to GPIO
-  *         @arg LL_TIM_TIM1_ETRSOURCE_COMP1:              TIM1_ETR is connected to COMP1 output
-  *         @arg LL_TIM_TIM1_ETRSOURCE_COMP2:              TIM1_ETR is connected to COMP2 output
-  *         @arg LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1:          TIM1_ETR is connected to ADC1 AWD1
-  *         @arg LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2:          TIM1_ETR is connected to ADC1 AWD2
-  *         @arg LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3:          TIM1_ETR is connected to ADC1 AWD3
-  *         @arg LL_TIM_TIM1_ETRSOURCE_ADC3_AWD1:          TIM1_ETR is connected to ADC3 AWD1
-  *         @arg LL_TIM_TIM1_ETRSOURCE_ADC3_AWD2:          TIM1_ETR is connected to ADC3 AWD2
-  *         @arg LL_TIM_TIM1_ETRSOURCE_ADC3_AWD3:          TIM1_ETR is connected to ADC3 AWD3
-  *
-  *      For TIM2, the parameter is one of the following values:
-  *         @arg LL_TIM_TIM2_ETRSOURCE_GPIO:               TIM2_ETR is connected to GPIO
-  *         @arg LL_TIM_TIM2_ETRSOURCE_COMP1:              TIM2_ETR is connected to COMP1 output
-  *         @arg LL_TIM_TIM2_ETRSOURCE_COMP2:              TIM2_ETR is connected to COMP2 output
-  *         @arg LL_TIM_TIM2_ETRSOURCE_LSE:                TIM2_ETR is connected to LSE
-  *         @arg LL_TIM_TIM2_ETRSOURCE_SAI1_FSA:           TIM2_ETR is connected to SAI1 FS_A
-  *         @arg LL_TIM_TIM2_ETRSOURCE_SAI1_FSB:           TIM2_ETR is connected to SAI1 FS_B
-  *
-  *      For TIM3, the parameter is one of the following values:
-  *         @arg LL_TIM_TIM3_ETRSOURCE_GPIO:               TIM3_ETR is connected to GPIO
-  *         @arg LL_TIM_TIM3_ETRSOURCE_COMP1:              TIM3_ETR is connected to COMP1 output
-  *
-  *      For TIM5, the parameter is one of the following values:
-  *         @arg LL_TIM_TIM5_ETRSOURCE_GPIO:               TIM5_ETR is connected to GPIO
-  *         @arg LL_TIM_TIM5_ETRSOURCE_SAI2_FSA:           TIM5_ETR is connected to SAI2 FS_A (*)
-  *         @arg LL_TIM_TIM5_ETRSOURCE_SAI2_FSB:           TIM5_ETR is connected to SAI2 FS_B (*)
-  *         @arg LL_TIM_TIM5_ETRSOURCE_SAI4_FSA:           TIM5_ETR is connected to SAI2 FS_A (*)
-  *         @arg LL_TIM_TIM5_ETRSOURCE_SAI4_FSB:           TIM5_ETR is connected to SAI2 FS_B (*)
-  *
-  *      For TIM8, the parameter is one of the following values:
-  *         @arg LL_TIM_TIM8_ETRSOURCE_GPIO:               TIM8_ETR is connected to GPIO
-  *         @arg LL_TIM_TIM8_ETRSOURCE_COMP1:              TIM8_ETR is connected to COMP1 output
-  *         @arg LL_TIM_TIM8_ETRSOURCE_COMP2:              TIM8_ETR is connected to COMP2 output
-  *         @arg LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1:          TIM8_ETR is connected to ADC2 AWD1
-  *         @arg LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2:          TIM8_ETR is connected to ADC2 AWD2
-  *         @arg LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3:          TIM8_ETR is connected to ADC2 AWD3
-  *         @arg LL_TIM_TIM8_ETRSOURCE_ADC3_AWD1:          TIM8_ETR is connected to ADC3 AWD1
-  *         @arg LL_TIM_TIM8_ETRSOURCE_ADC3_AWD2:          TIM8_ETR is connected to ADC3 AWD2
-  *         @arg LL_TIM_TIM8_ETRSOURCE_ADC3_AWD3:          TIM8_ETR is connected to ADC3 AWD3
-  *
-  *      For TIM23, the parameter is one of the following values: (*)
-  *         @arg LL_TIM_TIM23_ETRSOURCE_GPIO               TIM23_ETR is connected to GPIO
-  *         @arg LL_TIM_TIM23_ETRSOURCE_COMP1              TIM23_ETR is connected to COMP1 output
-  *         @arg LL_TIM_TIM23_ETRSOURCE_COMP2              TIM23_ETR is connected to COMP2 output
-  *
-  *      For TIM24, the parameter is one of the following values: (*)
-  *        @arg LL_TIM_TIM24_ETRSOURCE_GPIO                TIM24_ETR is connected to GPIO
-  *        @arg LL_TIM_TIM24_ETRSOURCE_SAI4_FSA            TIM24_ETR is connected to SAI4 FS_A
-  *        @arg LL_TIM_TIM24_ETRSOURCE_SAI4_FSB            TIM24_ETR is connected to SAI4 FS_B
-  *        @arg LL_TIM_TIM24_ETRSOURCE_SAI1_FSA            TIM24_ETR is connected to SAI1 FS_A
-  *        @arg LL_TIM_TIM24_ETRSOURCE_SAI1_FSB            TIM24_ETR is connected to SAI1 FS_B
-  *
-  *      (*)  Value not defined in all devices.
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource)
-{
-  MODIFY_REG(TIMx->AF1, TIMx_AF1_ETRSEL, ETRSource);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EF_Break_Function Break function configuration
-  * @{
-  */
-/**
-  * @brief  Enable the break function.
-  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance provides a break input.
-  * @rmtoll BDTR         BKE           LL_TIM_EnableBRK
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
-}
-
-/**
-  * @brief  Disable the break function.
-  * @rmtoll BDTR         BKE           LL_TIM_DisableBRK
-  * @param  TIMx Timer instance
-  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance provides a break input.
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
-}
-
-#if defined(TIM_BDTR_BKBID)
-/**
-  * @brief  Configure the break input.
-  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance provides a break input.
-  * @note Bidirectional mode is only supported by advanced timer instances.
-  *       Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance is an advanced-control timer.
-  * @note In bidirectional mode (BKBID bit set), the Break input is configured both
-  *        in input mode and in open drain output mode. Any active Break event will
-  *        assert a low logic level on the Break input to indicate an internal break
-  *        event to external devices.
-  * @note When bidirectional mode isn't supported, BreakAFMode must be set to
-  *       LL_TIM_BREAK_AFMODE_INPUT.
-  * @rmtoll BDTR         BKP           LL_TIM_ConfigBRK\n
-  *         BDTR         BKF           LL_TIM_ConfigBRK\n
-  *         BDTR         BKBID         LL_TIM_ConfigBRK
-  * @param  TIMx Timer instance
-  * @param  BreakPolarity This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_BREAK_POLARITY_LOW
-  *         @arg @ref LL_TIM_BREAK_POLARITY_HIGH
-  * @param  BreakFilter This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
-  * @param  BreakAFMode This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_BREAK_AFMODE_INPUT
-  *         @arg @ref LL_TIM_BREAK_AFMODE_BIDIRECTIONAL
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter,
-                                      uint32_t BreakAFMode)
-{
-  MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF | TIM_BDTR_BKBID, BreakPolarity | BreakFilter | BreakAFMode);
-}
-
-#else
-/**
-  * @brief  Configure the break input.
-  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance provides a break input.
-  * @rmtoll BDTR         BKP           LL_TIM_ConfigBRK\n
-  *         BDTR         BKF           LL_TIM_ConfigBRK
-  * @param  TIMx Timer instance
-  * @param  BreakPolarity This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_BREAK_POLARITY_LOW
-  *         @arg @ref LL_TIM_BREAK_POLARITY_HIGH
-  * @param  BreakFilter This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity,
-                                      uint32_t BreakFilter)
-{
-  MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF, BreakPolarity | BreakFilter);
-}
-
-#endif /* TIM_BDTR_BKBID */
-#if defined(TIM_BDTR_BKBID)
-/**
-  * @brief  Disarm the break input (when it operates in bidirectional mode).
-  * @note  The break input can be disarmed only when it is configured in
-  *        bidirectional mode and when when MOE is reset.
-  * @note  Purpose is to be able to have the input voltage back to high-state,
-  *        whatever the time constant on the output .
-  * @rmtoll BDTR         BKDSRM        LL_TIM_DisarmBRK
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisarmBRK(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
-}
-
-/**
-  * @brief  Re-arm the break input (when it operates in bidirectional mode).
-  * @note  The Break input is automatically armed as soon as MOE bit is set.
-  * @rmtoll BDTR         BKDSRM        LL_TIM_ReArmBRK
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ReArmBRK(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
-}
-
-#endif /*TIM_BDTR_BKBID */
-/**
-  * @brief  Enable the break 2 function.
-  * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance provides a second break input.
-  * @rmtoll BDTR         BK2E          LL_TIM_EnableBRK2
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
-}
-
-/**
-  * @brief  Disable the break  2 function.
-  * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance provides a second break input.
-  * @rmtoll BDTR         BK2E          LL_TIM_DisableBRK2
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
-}
-
-#if defined(TIM_BDTR_BKBID)
-/**
-  * @brief  Configure the break 2 input.
-  * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance provides a second break input.
-  * @note Bidirectional mode is only supported by advanced timer instances.
-  *       Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance is an advanced-control timer.
-  * @note In bidirectional mode (BK2BID bit set), the Break 2 input is configured both
-  *        in input mode and in open drain output mode. Any active Break event will
-  *        assert a low logic level on the Break 2 input to indicate an internal break
-  *        event to external devices.
-  * @note When bidirectional mode isn't supported, Break2AFMode must be set to
-  *       LL_TIM_BREAK2_AFMODE_INPUT.
-  * @rmtoll BDTR         BK2P          LL_TIM_ConfigBRK2\n
-  *         BDTR         BK2F          LL_TIM_ConfigBRK2\n
-  *         BDTR         BK2BID        LL_TIM_ConfigBRK2
-  * @param  TIMx Timer instance
-  * @param  Break2Polarity This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_BREAK2_POLARITY_LOW
-  *         @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
-  * @param  Break2Filter This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
-  * @param  Break2AFMode This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_BREAK2_AFMODE_INPUT
-  *         @arg @ref LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter,
-                                       uint32_t Break2AFMode)
-{
-  MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F | TIM_BDTR_BK2BID, Break2Polarity | Break2Filter | Break2AFMode);
-}
-
-#else
-/**
-  * @brief  Configure the break 2 input.
-  * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance provides a second break input.
-  * @rmtoll BDTR         BK2P          LL_TIM_ConfigBRK2\n
-  *         BDTR         BK2F          LL_TIM_ConfigBRK2
-  * @param  TIMx Timer instance
-  * @param  Break2Polarity This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_BREAK2_POLARITY_LOW
-  *         @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
-  * @param  Break2Filter This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter)
-{
-  MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F, Break2Polarity | Break2Filter);
-}
-
-#endif /*TIM_BDTR_BKBID */
-#if defined(TIM_BDTR_BKBID)
-/**
-  * @brief  Disarm the break 2 input (when it operates in bidirectional mode).
-  * @note  The break 2 input can be disarmed only when it is configured in
-  *        bidirectional mode and when when MOE is reset.
-  * @note  Purpose is to be able to have the input voltage back to high-state,
-  *        whatever the time constant on the output.
-  * @rmtoll BDTR         BK2DSRM       LL_TIM_DisarmBRK2
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisarmBRK2(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM);
-}
-
-/**
-  * @brief  Re-arm the break 2 input (when it operates in bidirectional mode).
-  * @note  The Break 2 input is automatically armed as soon as MOE bit is set.
-  * @rmtoll BDTR         BK2DSRM       LL_TIM_ReArmBRK2
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ReArmBRK2(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM);
-}
-
-#endif /*TIM_BDTR_BKBID */
-/**
-  * @brief  Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
-  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance provides a break input.
-  * @rmtoll BDTR         OSSI          LL_TIM_SetOffStates\n
-  *         BDTR         OSSR          LL_TIM_SetOffStates
-  * @param  TIMx Timer instance
-  * @param  OffStateIdle This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_OSSI_DISABLE
-  *         @arg @ref LL_TIM_OSSI_ENABLE
-  * @param  OffStateRun This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_OSSR_DISABLE
-  *         @arg @ref LL_TIM_OSSR_ENABLE
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
-{
-  MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
-}
-
-/**
-  * @brief  Enable automatic output (MOE can be set by software or automatically when a break input is active).
-  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance provides a break input.
-  * @rmtoll BDTR         AOE           LL_TIM_EnableAutomaticOutput
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
-}
-
-/**
-  * @brief  Disable automatic output (MOE can be set only by software).
-  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance provides a break input.
-  * @rmtoll BDTR         AOE           LL_TIM_DisableAutomaticOutput
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
-}
-
-/**
-  * @brief  Indicate whether automatic output is enabled.
-  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance provides a break input.
-  * @rmtoll BDTR         AOE           LL_TIM_IsEnabledAutomaticOutput
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable the outputs (set the MOE bit in TIMx_BDTR register).
-  * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
-  *       software and is reset in case of break or break2 event
-  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance provides a break input.
-  * @rmtoll BDTR         MOE           LL_TIM_EnableAllOutputs
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
-}
-
-/**
-  * @brief  Disable the outputs (reset the MOE bit in TIMx_BDTR register).
-  * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
-  *       software and is reset in case of break or break2 event.
-  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance provides a break input.
-  * @rmtoll BDTR         MOE           LL_TIM_DisableAllOutputs
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
-}
-
-/**
-  * @brief  Indicates whether outputs are enabled.
-  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance provides a break input.
-  * @rmtoll BDTR         MOE           LL_TIM_IsEnabledAllOutputs
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
-}
-
-#if defined(TIM_BREAK_INPUT_SUPPORT)
-/**
-  * @brief  Enable the signals connected to the designated timer break input.
-  * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
-  *       or not a timer instance allows for break input selection.
-  * @rmtoll AF1          BKINE         LL_TIM_EnableBreakInputSource\n
-  *         AF1          BKCMP1E       LL_TIM_EnableBreakInputSource\n
-  *         AF1          BKCMP2E       LL_TIM_EnableBreakInputSource\n
-  *         AF1          BKDF1BK0E     LL_TIM_EnableBreakInputSource\n
-  *         AF2          BK2INE        LL_TIM_EnableBreakInputSource\n
-  *         AF2          BK2CMP1E      LL_TIM_EnableBreakInputSource\n
-  *         AF2          BK2CMP2E      LL_TIM_EnableBreakInputSource\n
-  *         AF2          BK2DF1BK1E    LL_TIM_EnableBreakInputSource
-  * @param  TIMx Timer instance
-  * @param  BreakInput This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_BREAK_INPUT_BKIN
-  *         @arg @ref LL_TIM_BREAK_INPUT_BKIN2
-  * @param  Source This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_BKIN_SOURCE_BKIN
-  *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
-  *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
-  *         @arg @ref LL_TIM_BKIN_SOURCE_DF1BK
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
-{
-  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
-  SET_BIT(*pReg, Source);
-}
-
-/**
-  * @brief  Disable the signals connected to the designated timer break input.
-  * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
-  *       or not a timer instance allows for break input selection.
-  * @rmtoll AF1          BKINE         LL_TIM_DisableBreakInputSource\n
-  *         AF1          BKCMP1E       LL_TIM_DisableBreakInputSource\n
-  *         AF1          BKCMP2E       LL_TIM_DisableBreakInputSource\n
-  *         AF1          BKDF1BK0E     LL_TIM_DisableBreakInputSource\n
-  *         AF2          BK2INE        LL_TIM_DisableBreakInputSource\n
-  *         AF2          BK2CMP1E      LL_TIM_DisableBreakInputSource\n
-  *         AF2          BK2CMP2E      LL_TIM_DisableBreakInputSource\n
-  *         AF2          BK2DF1BK1E    LL_TIM_DisableBreakInputSource
-  * @param  TIMx Timer instance
-  * @param  BreakInput This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_BREAK_INPUT_BKIN
-  *         @arg @ref LL_TIM_BREAK_INPUT_BKIN2
-  * @param  Source This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_BKIN_SOURCE_BKIN
-  *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
-  *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
-  *         @arg @ref LL_TIM_BKIN_SOURCE_DF1BK
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
-{
-  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
-  CLEAR_BIT(*pReg, Source);
-}
-
-/**
-  * @brief  Set the polarity of the break signal for the timer break input.
-  * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
-  *       or not a timer instance allows for break input selection.
-  * @rmtoll AF1          BKINP         LL_TIM_SetBreakInputSourcePolarity\n
-  *         AF1          BKCMP1P       LL_TIM_SetBreakInputSourcePolarity\n
-  *         AF1          BKCMP2P       LL_TIM_SetBreakInputSourcePolarity\n
-  *         AF2          BK2INP        LL_TIM_SetBreakInputSourcePolarity\n
-  *         AF2          BK2CMP1P      LL_TIM_SetBreakInputSourcePolarity\n
-  *         AF2          BK2CMP2P      LL_TIM_SetBreakInputSourcePolarity
-  * @param  TIMx Timer instance
-  * @param  BreakInput This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_BREAK_INPUT_BKIN
-  *         @arg @ref LL_TIM_BREAK_INPUT_BKIN2
-  * @param  Source This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_BKIN_SOURCE_BKIN
-  *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
-  *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
-  * @param  Polarity This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_BKIN_POLARITY_LOW
-  *         @arg @ref LL_TIM_BKIN_POLARITY_HIGH
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source,
-                                                        uint32_t Polarity)
-{
-  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
-  MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE));
-}
-#endif /* TIM_BREAK_INPUT_SUPPORT */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
-  * @{
-  */
-/**
-  * @brief  Configures the timer DMA burst feature.
-  * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
-  *       not a timer instance supports the DMA burst mode.
-  * @rmtoll DCR          DBL           LL_TIM_ConfigDMABurst\n
-  *         DCR          DBA           LL_TIM_ConfigDMABurst
-  * @param  TIMx Timer instance
-  * @param  DMABurstBaseAddress This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_SR
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_AF1
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_AF2
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_TISEL
-  *
-  * @param  DMABurstLength This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
-{
-  MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
-  * @{
-  */
-/**
-  * @brief  Remap TIM inputs (input channel, internal/external triggers).
-  * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
-  *       a some timer inputs can be remapped.
-  *         TIM1: one of the following values:
-  *            @arg LL_TIM_TIM1_TI1_RMP_GPIO:                TIM1 TI1 is connected to GPIO
-  *            @arg LL_TIM_TIM1_TI1_RMP_COMP1:               TIM1 TI1 is connected to COMP1 output
-  *
-  *         TIM2: one of the following values:
-  *            @arg LL_TIM_TIM2_TI4_RMP_GPIO:                TIM2 TI4 is connected to GPIO
-  *            @arg LL_TIM_TIM2_TI4_RMP_COMP1:               TIM2 TI4 is connected to COMP1 output
-  *            @arg LL_TIM_TIM2_TI4_RMP_COMP2:               TIM2 TI4 is connected to COMP2 output
-  *            @arg LL_TIM_TIM2_TI4_RMP_COMP1_COMP2:         TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output
-  *
-  *         TIM3: one of the following values:
-  *            @arg LL_TIM_TIM3_TI1_RMP_GPIO:                TIM3 TI1 is connected to GPIO
-  *            @arg LL_TIM_TIM3_TI1_RMP_COMP1:               TIM3 TI1 is connected to COMP1 output
-  *            @arg LL_TIM_TIM3_TI1_RMP_COMP2:               TIM3 TI1 is connected to COMP2 output
-  *            @arg LL_TIM_TIM3_TI1_RMP_COMP1_COMP2:         TIM3 TI1 is connected to logical OR between COMP1 and COMP2 output
-  *
-  *         TIM5: one of the following values:
-  *            @arg LL_TIM_TIM5_TI1_RMP_GPIO:                TIM5 TI1 is connected to GPIO
-  *            @arg LL_TIM_TIM5_TI1_RMP_CAN_TMP:             TIM5 TI1 is connected to CAN TMP
-  *            @arg LL_TIM_TIM5_TI1_RMP_CAN_RTP:             TIM5 TI1 is connected to CAN RTP
-  *
-  *         TIM8: one of the following values:
-  *            @arg LL_TIM_TIM8_TI1_RMP_GPIO:               TIM8 TI1 is connected to GPIO
-  *            @arg LL_TIM_TIM8_TI1_RMP_COMP2:              TIM8 TI1 is connected to COMP2 output
-  *
-  *         TIM12: one of the following values: (*)
-  *            @arg LL_TIM_TIM12_TI1_RMP_GPIO:              TIM12 TI1 is connected to GPIO
-  *            @arg LL_TIM_TIM12_TI1_RMP_SPDIF_FS:          TIM12 TI1 is connected to SPDIF FS
-  *
-  *         TIM15: one of the following values:
-  *            @arg LL_TIM_TIM15_TI1_RMP_GPIO:              TIM15 TI1 is connected to GPIO
-  *            @arg LL_TIM_TIM15_TI1_RMP_TIM2:              TIM15 TI1 is connected to TIM2 CH1
-  *            @arg LL_TIM_TIM15_TI1_RMP_TIM3:              TIM15 TI1 is connected to TIM3 CH1
-  *            @arg LL_TIM_TIM15_TI1_RMP_TIM4:              TIM15 TI1 is connected to TIM4 CH1
-  *            @arg LL_TIM_TIM15_TI1_RMP_LSE:               TIM15 TI1 is connected to LSE
-  *            @arg LL_TIM_TIM15_TI1_RMP_CSI:               TIM15 TI1 is connected to CSI
-  *            @arg LL_TIM_TIM15_TI1_RMP_MCO2:              TIM15 TI1 is connected to MCO2
-  *            @arg LL_TIM_TIM15_TI2_RMP_GPIO:              TIM15 TI2 is connected to GPIO
-  *            @arg LL_TIM_TIM15_TI2_RMP_TIM2:              TIM15 TI2 is connected to TIM2 CH2
-  *            @arg LL_TIM_TIM15_TI2_RMP_TIM3:              TIM15 TI2 is connected to TIM3 CH2
-  *            @arg LL_TIM_TIM15_TI2_RMP_TIM4:              TIM15 TI2 is connected to TIM4 CH2
-  *
-  *         TIM16: one of the following values:
-  *            @arg LL_TIM_TIM16_TI1_RMP_GPIO:              TIM16 TI1 is connected to GPIO
-  *            @arg LL_TIM_TIM16_TI1_RMP_LSI:               TIM16 TI1 is connected to LSI
-  *            @arg LL_TIM_TIM16_TI1_RMP_LSE:               TIM16 TI1 is connected to LSE
-  *            @arg LL_TIM_TIM16_TI1_RMP_RTC:               TIM16 TI1 is connected to RTC wakeup interrupt
-  *
-  *         TIM17: one of the following values:
-  *            @arg LL_TIM_TIM17_TI1_RMP_GPIO:              TIM17 TI1 is connected to GPIO
-  *            @arg LL_TIM_TIM17_TI1_RMP_SPDIF_FS:          TIM17 TI1 is connected to SPDIF FS (*)
-  *            @arg LL_TIM_TIM17_TI1_RMP_HSE_1MHZ:          TIM17 TI1 is connected to HSE 1MHz
-  *            @arg LL_TIM_TIM17_TI1_RMP_MCO1:              TIM17 TI1 is connected to MCO1
-  *
-  *         TIM23: one of the following values: (*)
-  *            @arg LL_TIM_TIM23_TI4_RMP_GPIO               TIM23_TI4 is connected to GPIO
-  *            @arg LL_TIM_TIM23_TI4_RMP_COMP1              TIM23_TI4 is connected to COMP1 output
-  *            @arg LL_TIM_TIM23_TI4_RMP_COMP2              TIM23_TI4 is connected to COMP2 output
-  *            @arg LL_TIM_TIM23_TI4_RMP_COMP1_COMP2        TIM23_TI4 is connected to COMP2 output
-  *
-  *         TIM24: one of the following values: (*)
-  *            @arg LL_TIM_TIM24_TI1_RMP_GPIO               TIM24_TI1 is connected to GPIO
-  *            @arg LL_TIM_TIM24_TI1_RMP_CAN_TMP            TIM24_TI1 is connected to CAN_TMP
-  *            @arg LL_TIM_TIM24_TI1_RMP_CAN_RTP            TIM24_TI1 is connected to CAN_RTP
-  *            @arg LL_TIM_TIM24_TI1_RMP_CAN_SOC            TIM24_TI1 is connected to CAN_SOC
-  *
-  *         (*)  Value not defined in all devices. \n
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
-{
-  MODIFY_REG(TIMx->TISEL, (TIM_TISEL_TI1SEL | TIM_TISEL_TI2SEL | TIM_TISEL_TI3SEL | TIM_TISEL_TI4SEL), Remap);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
-  * @{
-  */
-/**
-  * @brief  Clear the update interrupt flag (UIF).
-  * @rmtoll SR           UIF           LL_TIM_ClearFlag_UPDATE
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
-{
-  WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
-}
-
-/**
-  * @brief  Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
-  * @rmtoll SR           UIF           LL_TIM_IsActiveFlag_UPDATE
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear the Capture/Compare 1 interrupt flag (CC1F).
-  * @rmtoll SR           CC1IF         LL_TIM_ClearFlag_CC1
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
-{
-  WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
-}
-
-/**
-  * @brief  Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
-  * @rmtoll SR           CC1IF         LL_TIM_IsActiveFlag_CC1
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear the Capture/Compare 2 interrupt flag (CC2F).
-  * @rmtoll SR           CC2IF         LL_TIM_ClearFlag_CC2
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
-{
-  WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
-}
-
-/**
-  * @brief  Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
-  * @rmtoll SR           CC2IF         LL_TIM_IsActiveFlag_CC2
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear the Capture/Compare 3 interrupt flag (CC3F).
-  * @rmtoll SR           CC3IF         LL_TIM_ClearFlag_CC3
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
-{
-  WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
-}
-
-/**
-  * @brief  Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
-  * @rmtoll SR           CC3IF         LL_TIM_IsActiveFlag_CC3
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear the Capture/Compare 4 interrupt flag (CC4F).
-  * @rmtoll SR           CC4IF         LL_TIM_ClearFlag_CC4
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
-{
-  WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
-}
-
-/**
-  * @brief  Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
-  * @rmtoll SR           CC4IF         LL_TIM_IsActiveFlag_CC4
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear the Capture/Compare 5 interrupt flag (CC5F).
-  * @rmtoll SR           CC5IF         LL_TIM_ClearFlag_CC5
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx)
-{
-  WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF));
-}
-
-/**
-  * @brief  Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
-  * @rmtoll SR           CC5IF         LL_TIM_IsActiveFlag_CC5
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear the Capture/Compare 6 interrupt flag (CC6F).
-  * @rmtoll SR           CC6IF         LL_TIM_ClearFlag_CC6
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx)
-{
-  WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF));
-}
-
-/**
-  * @brief  Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
-  * @rmtoll SR           CC6IF         LL_TIM_IsActiveFlag_CC6
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear the commutation interrupt flag (COMIF).
-  * @rmtoll SR           COMIF         LL_TIM_ClearFlag_COM
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
-{
-  WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
-}
-
-/**
-  * @brief  Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
-  * @rmtoll SR           COMIF         LL_TIM_IsActiveFlag_COM
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear the trigger interrupt flag (TIF).
-  * @rmtoll SR           TIF           LL_TIM_ClearFlag_TRIG
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
-{
-  WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
-}
-
-/**
-  * @brief  Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
-  * @rmtoll SR           TIF           LL_TIM_IsActiveFlag_TRIG
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear the break interrupt flag (BIF).
-  * @rmtoll SR           BIF           LL_TIM_ClearFlag_BRK
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
-{
-  WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
-}
-
-/**
-  * @brief  Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
-  * @rmtoll SR           BIF           LL_TIM_IsActiveFlag_BRK
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear the break 2 interrupt flag (B2IF).
-  * @rmtoll SR           B2IF          LL_TIM_ClearFlag_BRK2
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx)
-{
-  WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF));
-}
-
-/**
-  * @brief  Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
-  * @rmtoll SR           B2IF          LL_TIM_IsActiveFlag_BRK2
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
-  * @rmtoll SR           CC1OF         LL_TIM_ClearFlag_CC1OVR
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
-{
-  WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
-}
-
-/**
-  * @brief  Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set
-  *         (Capture/Compare 1 interrupt is pending).
-  * @rmtoll SR           CC1OF         LL_TIM_IsActiveFlag_CC1OVR
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
-  * @rmtoll SR           CC2OF         LL_TIM_ClearFlag_CC2OVR
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
-{
-  WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
-}
-
-/**
-  * @brief  Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set
-  *         (Capture/Compare 2 over-capture interrupt is pending).
-  * @rmtoll SR           CC2OF         LL_TIM_IsActiveFlag_CC2OVR
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
-  * @rmtoll SR           CC3OF         LL_TIM_ClearFlag_CC3OVR
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
-{
-  WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
-}
-
-/**
-  * @brief  Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set
-  *         (Capture/Compare 3 over-capture interrupt is pending).
-  * @rmtoll SR           CC3OF         LL_TIM_IsActiveFlag_CC3OVR
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
-  * @rmtoll SR           CC4OF         LL_TIM_ClearFlag_CC4OVR
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
-{
-  WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
-}
-
-/**
-  * @brief  Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set
-  *         (Capture/Compare 4 over-capture interrupt is pending).
-  * @rmtoll SR           CC4OF         LL_TIM_IsActiveFlag_CC4OVR
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear the system break interrupt flag (SBIF).
-  * @rmtoll SR           SBIF          LL_TIM_ClearFlag_SYSBRK
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx)
-{
-  WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF));
-}
-
-/**
-  * @brief  Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).
-  * @rmtoll SR           SBIF          LL_TIM_IsActiveFlag_SYSBRK
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EF_IT_Management IT-Management
-  * @{
-  */
-/**
-  * @brief  Enable update interrupt (UIE).
-  * @rmtoll DIER         UIE           LL_TIM_EnableIT_UPDATE
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->DIER, TIM_DIER_UIE);
-}
-
-/**
-  * @brief  Disable update interrupt (UIE).
-  * @rmtoll DIER         UIE           LL_TIM_DisableIT_UPDATE
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
-}
-
-/**
-  * @brief  Indicates whether the update interrupt (UIE) is enabled.
-  * @rmtoll DIER         UIE           LL_TIM_IsEnabledIT_UPDATE
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable capture/compare 1 interrupt (CC1IE).
-  * @rmtoll DIER         CC1IE         LL_TIM_EnableIT_CC1
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
-}
-
-/**
-  * @brief  Disable capture/compare 1  interrupt (CC1IE).
-  * @rmtoll DIER         CC1IE         LL_TIM_DisableIT_CC1
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
-}
-
-/**
-  * @brief  Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
-  * @rmtoll DIER         CC1IE         LL_TIM_IsEnabledIT_CC1
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable capture/compare 2 interrupt (CC2IE).
-  * @rmtoll DIER         CC2IE         LL_TIM_EnableIT_CC2
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
-}
-
-/**
-  * @brief  Disable capture/compare 2  interrupt (CC2IE).
-  * @rmtoll DIER         CC2IE         LL_TIM_DisableIT_CC2
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
-}
-
-/**
-  * @brief  Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
-  * @rmtoll DIER         CC2IE         LL_TIM_IsEnabledIT_CC2
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable capture/compare 3 interrupt (CC3IE).
-  * @rmtoll DIER         CC3IE         LL_TIM_EnableIT_CC3
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
-}
-
-/**
-  * @brief  Disable capture/compare 3  interrupt (CC3IE).
-  * @rmtoll DIER         CC3IE         LL_TIM_DisableIT_CC3
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
-}
-
-/**
-  * @brief  Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
-  * @rmtoll DIER         CC3IE         LL_TIM_IsEnabledIT_CC3
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable capture/compare 4 interrupt (CC4IE).
-  * @rmtoll DIER         CC4IE         LL_TIM_EnableIT_CC4
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
-}
-
-/**
-  * @brief  Disable capture/compare 4  interrupt (CC4IE).
-  * @rmtoll DIER         CC4IE         LL_TIM_DisableIT_CC4
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
-}
-
-/**
-  * @brief  Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
-  * @rmtoll DIER         CC4IE         LL_TIM_IsEnabledIT_CC4
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable commutation interrupt (COMIE).
-  * @rmtoll DIER         COMIE         LL_TIM_EnableIT_COM
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
-}
-
-/**
-  * @brief  Disable commutation interrupt (COMIE).
-  * @rmtoll DIER         COMIE         LL_TIM_DisableIT_COM
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
-}
-
-/**
-  * @brief  Indicates whether the commutation interrupt (COMIE) is enabled.
-  * @rmtoll DIER         COMIE         LL_TIM_IsEnabledIT_COM
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable trigger interrupt (TIE).
-  * @rmtoll DIER         TIE           LL_TIM_EnableIT_TRIG
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->DIER, TIM_DIER_TIE);
-}
-
-/**
-  * @brief  Disable trigger interrupt (TIE).
-  * @rmtoll DIER         TIE           LL_TIM_DisableIT_TRIG
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
-}
-
-/**
-  * @brief  Indicates whether the trigger interrupt (TIE) is enabled.
-  * @rmtoll DIER         TIE           LL_TIM_IsEnabledIT_TRIG
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable break interrupt (BIE).
-  * @rmtoll DIER         BIE           LL_TIM_EnableIT_BRK
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->DIER, TIM_DIER_BIE);
-}
-
-/**
-  * @brief  Disable break interrupt (BIE).
-  * @rmtoll DIER         BIE           LL_TIM_DisableIT_BRK
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
-}
-
-/**
-  * @brief  Indicates whether the break interrupt (BIE) is enabled.
-  * @rmtoll DIER         BIE           LL_TIM_IsEnabledIT_BRK
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EF_DMA_Management DMA Management
-  * @{
-  */
-/**
-  * @brief  Enable update DMA request (UDE).
-  * @rmtoll DIER         UDE           LL_TIM_EnableDMAReq_UPDATE
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->DIER, TIM_DIER_UDE);
-}
-
-/**
-  * @brief  Disable update DMA request (UDE).
-  * @rmtoll DIER         UDE           LL_TIM_DisableDMAReq_UPDATE
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
-}
-
-/**
-  * @brief  Indicates whether the update DMA request  (UDE) is enabled.
-  * @rmtoll DIER         UDE           LL_TIM_IsEnabledDMAReq_UPDATE
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable capture/compare 1 DMA request (CC1DE).
-  * @rmtoll DIER         CC1DE         LL_TIM_EnableDMAReq_CC1
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
-}
-
-/**
-  * @brief  Disable capture/compare 1  DMA request (CC1DE).
-  * @rmtoll DIER         CC1DE         LL_TIM_DisableDMAReq_CC1
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
-}
-
-/**
-  * @brief  Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
-  * @rmtoll DIER         CC1DE         LL_TIM_IsEnabledDMAReq_CC1
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable capture/compare 2 DMA request (CC2DE).
-  * @rmtoll DIER         CC2DE         LL_TIM_EnableDMAReq_CC2
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
-}
-
-/**
-  * @brief  Disable capture/compare 2  DMA request (CC2DE).
-  * @rmtoll DIER         CC2DE         LL_TIM_DisableDMAReq_CC2
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
-}
-
-/**
-  * @brief  Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
-  * @rmtoll DIER         CC2DE         LL_TIM_IsEnabledDMAReq_CC2
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable capture/compare 3 DMA request (CC3DE).
-  * @rmtoll DIER         CC3DE         LL_TIM_EnableDMAReq_CC3
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
-}
-
-/**
-  * @brief  Disable capture/compare 3  DMA request (CC3DE).
-  * @rmtoll DIER         CC3DE         LL_TIM_DisableDMAReq_CC3
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
-}
-
-/**
-  * @brief  Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
-  * @rmtoll DIER         CC3DE         LL_TIM_IsEnabledDMAReq_CC3
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable capture/compare 4 DMA request (CC4DE).
-  * @rmtoll DIER         CC4DE         LL_TIM_EnableDMAReq_CC4
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
-}
-
-/**
-  * @brief  Disable capture/compare 4  DMA request (CC4DE).
-  * @rmtoll DIER         CC4DE         LL_TIM_DisableDMAReq_CC4
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
-}
-
-/**
-  * @brief  Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
-  * @rmtoll DIER         CC4DE         LL_TIM_IsEnabledDMAReq_CC4
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable commutation DMA request (COMDE).
-  * @rmtoll DIER         COMDE         LL_TIM_EnableDMAReq_COM
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
-}
-
-/**
-  * @brief  Disable commutation DMA request (COMDE).
-  * @rmtoll DIER         COMDE         LL_TIM_DisableDMAReq_COM
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
-}
-
-/**
-  * @brief  Indicates whether the commutation DMA request (COMDE) is enabled.
-  * @rmtoll DIER         COMDE         LL_TIM_IsEnabledDMAReq_COM
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable trigger interrupt (TDE).
-  * @rmtoll DIER         TDE           LL_TIM_EnableDMAReq_TRIG
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->DIER, TIM_DIER_TDE);
-}
-
-/**
-  * @brief  Disable trigger interrupt (TDE).
-  * @rmtoll DIER         TDE           LL_TIM_DisableDMAReq_TRIG
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
-}
-
-/**
-  * @brief  Indicates whether the trigger interrupt (TDE) is enabled.
-  * @rmtoll DIER         TDE           LL_TIM_IsEnabledDMAReq_TRIG
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
-  * @{
-  */
-/**
-  * @brief  Generate an update event.
-  * @rmtoll EGR          UG            LL_TIM_GenerateEvent_UPDATE
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->EGR, TIM_EGR_UG);
-}
-
-/**
-  * @brief  Generate Capture/Compare 1 event.
-  * @rmtoll EGR          CC1G          LL_TIM_GenerateEvent_CC1
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
-}
-
-/**
-  * @brief  Generate Capture/Compare 2 event.
-  * @rmtoll EGR          CC2G          LL_TIM_GenerateEvent_CC2
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
-}
-
-/**
-  * @brief  Generate Capture/Compare 3 event.
-  * @rmtoll EGR          CC3G          LL_TIM_GenerateEvent_CC3
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
-}
-
-/**
-  * @brief  Generate Capture/Compare 4 event.
-  * @rmtoll EGR          CC4G          LL_TIM_GenerateEvent_CC4
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
-}
-
-/**
-  * @brief  Generate commutation event.
-  * @rmtoll EGR          COMG          LL_TIM_GenerateEvent_COM
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->EGR, TIM_EGR_COMG);
-}
-
-/**
-  * @brief  Generate trigger event.
-  * @rmtoll EGR          TG            LL_TIM_GenerateEvent_TRIG
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->EGR, TIM_EGR_TG);
-}
-
-/**
-  * @brief  Generate break event.
-  * @rmtoll EGR          BG            LL_TIM_GenerateEvent_BRK
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->EGR, TIM_EGR_BG);
-}
-
-/**
-  * @brief  Generate break 2 event.
-  * @rmtoll EGR          B2G           LL_TIM_GenerateEvent_BRK2
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->EGR, TIM_EGR_B2G);
-}
-
-/**
-  * @}
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
-  * @{
-  */
-
-ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
-void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
-ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct);
-void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
-ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
-void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
-ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
-void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
-ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
-void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
-ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
-void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
-ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM12 || TIM13 ||TIM14 || TIM15 || TIM16 || TIM17  || TIM23  || TIM24 */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32H7xx_LL_TIM_H */
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_ll_tim.h
+  * @author  MCD Application Team
+  * @brief   Header file of TIM LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32H7xx_LL_TIM_H
+#define __STM32H7xx_LL_TIM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx.h"
+
+/** @addtogroup STM32H7xx_LL_Driver
+  * @{
+  */
+
+#if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM23) || defined (TIM24)
+
+/** @defgroup TIM_LL TIM
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup TIM_LL_Private_Variables TIM Private Variables
+  * @{
+  */
+static const uint8_t OFFSET_TAB_CCMRx[] =
+{
+  0x00U,   /* 0: TIMx_CH1  */
+  0x00U,   /* 1: TIMx_CH1N */
+  0x00U,   /* 2: TIMx_CH2  */
+  0x00U,   /* 3: TIMx_CH2N */
+  0x04U,   /* 4: TIMx_CH3  */
+  0x04U,   /* 5: TIMx_CH3N */
+  0x04U,   /* 6: TIMx_CH4  */
+  0x3CU,   /* 7: TIMx_CH5  */
+  0x3CU    /* 8: TIMx_CH6  */
+};
+
+static const uint8_t SHIFT_TAB_OCxx[] =
+{
+  0U,            /* 0: OC1M, OC1FE, OC1PE */
+  0U,            /* 1: - NA */
+  8U,            /* 2: OC2M, OC2FE, OC2PE */
+  0U,            /* 3: - NA */
+  0U,            /* 4: OC3M, OC3FE, OC3PE */
+  0U,            /* 5: - NA */
+  8U,            /* 6: OC4M, OC4FE, OC4PE */
+  0U,            /* 7: OC5M, OC5FE, OC5PE */
+  8U             /* 8: OC6M, OC6FE, OC6PE */
+};
+
+static const uint8_t SHIFT_TAB_ICxx[] =
+{
+  0U,            /* 0: CC1S, IC1PSC, IC1F */
+  0U,            /* 1: - NA */
+  8U,            /* 2: CC2S, IC2PSC, IC2F */
+  0U,            /* 3: - NA */
+  0U,            /* 4: CC3S, IC3PSC, IC3F */
+  0U,            /* 5: - NA */
+  8U,            /* 6: CC4S, IC4PSC, IC4F */
+  0U,            /* 7: - NA */
+  0U             /* 8: - NA */
+};
+
+static const uint8_t SHIFT_TAB_CCxP[] =
+{
+  0U,            /* 0: CC1P */
+  2U,            /* 1: CC1NP */
+  4U,            /* 2: CC2P */
+  6U,            /* 3: CC2NP */
+  8U,            /* 4: CC3P */
+  10U,           /* 5: CC3NP */
+  12U,           /* 6: CC4P */
+  16U,           /* 7: CC5P */
+  20U            /* 8: CC6P */
+};
+
+static const uint8_t SHIFT_TAB_OISx[] =
+{
+  0U,            /* 0: OIS1 */
+  1U,            /* 1: OIS1N */
+  2U,            /* 2: OIS2 */
+  3U,            /* 3: OIS2N */
+  4U,            /* 4: OIS3 */
+  5U,            /* 5: OIS3N */
+  6U,            /* 6: OIS4 */
+  8U,            /* 7: OIS5 */
+  10U            /* 8: OIS6 */
+};
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup TIM_LL_Private_Constants TIM Private Constants
+  * @{
+  */
+
+#if   defined(TIM_BREAK_INPUT_SUPPORT)
+/* Defines used for the bit position in the register and perform offsets */
+#define TIM_POSITION_BRK_SOURCE            (POSITION_VAL(Source) & 0x1FUL)
+
+/* Generic bit definitions for TIMx_AF1 register */
+#define TIMx_AF1_BKINP     TIM1_AF1_BKINP     /*!< BRK BKIN input polarity */
+#define TIMx_AF1_ETRSEL    TIM1_AF1_ETRSEL    /*!< TIMx ETR source selection */
+#endif /* TIM_BREAK_INPUT_SUPPORT */
+
+
+/* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
+#define DT_DELAY_1 ((uint8_t)0x7F)
+#define DT_DELAY_2 ((uint8_t)0x3F)
+#define DT_DELAY_3 ((uint8_t)0x1F)
+#define DT_DELAY_4 ((uint8_t)0x1F)
+
+/* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
+#define DT_RANGE_1 ((uint8_t)0x00)
+#define DT_RANGE_2 ((uint8_t)0x80)
+#define DT_RANGE_3 ((uint8_t)0xC0)
+#define DT_RANGE_4 ((uint8_t)0xE0)
+
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup TIM_LL_Private_Macros TIM Private Macros
+  * @{
+  */
+/** @brief  Convert channel id into channel index.
+  * @param  __CHANNEL__ This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH1N
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH2N
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH3N
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval none
+  */
+#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
+  (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
+   ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
+   ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
+   ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
+   ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
+   ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
+   ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
+   ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U)
+
+/** @brief  Calculate the deadtime sampling period(in ps).
+  * @param  __TIMCLK__ timer input clock frequency (in Hz).
+  * @param  __CKD__ This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+  * @retval none
+  */
+#define TIM_CALC_DTS(__TIMCLK__, __CKD__)                                                        \
+  (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__))         : \
+   ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
+   ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
+/**
+  * @}
+  */
+
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
+  * @{
+  */
+
+/**
+  * @brief  TIM Time Base configuration structure definition.
+  */
+typedef struct
+{
+  uint16_t Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
+                                   This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
+
+                                   This feature can be modified afterwards using unitary function
+                                   @ref LL_TIM_SetPrescaler().*/
+
+  uint32_t CounterMode;       /*!< Specifies the counter mode.
+                                   This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
+
+                                   This feature can be modified afterwards using unitary function
+                                   @ref LL_TIM_SetCounterMode().*/
+
+  uint32_t Autoreload;        /*!< Specifies the auto reload value to be loaded into the active
+                                   Auto-Reload Register at the next update event.
+                                   This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
+                                   Some timer instances may support 32 bits counters. In that case this parameter must
+                                   be a number between 0x0000 and 0xFFFFFFFF.
+
+                                   This feature can be modified afterwards using unitary function
+                                   @ref LL_TIM_SetAutoReload().*/
+
+  uint32_t ClockDivision;     /*!< Specifies the clock division.
+                                   This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
+
+                                   This feature can be modified afterwards using unitary function
+                                   @ref LL_TIM_SetClockDivision().*/
+
+  uint32_t RepetitionCounter;  /*!< Specifies the repetition counter value. Each time the RCR downcounter
+                                   reaches zero, an update event is generated and counting restarts
+                                   from the RCR value (N).
+                                   This means in PWM mode that (N+1) corresponds to:
+                                      - the number of PWM periods in edge-aligned mode
+                                      - the number of half PWM period in center-aligned mode
+                                   GP timers: this parameter must be a number between Min_Data = 0x00 and
+                                   Max_Data = 0xFF.
+                                   Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
+                                   Max_Data = 0xFFFF.
+
+                                   This feature can be modified afterwards using unitary function
+                                   @ref LL_TIM_SetRepetitionCounter().*/
+} LL_TIM_InitTypeDef;
+
+/**
+  * @brief  TIM Output Compare configuration structure definition.
+  */
+typedef struct
+{
+  uint32_t OCMode;        /*!< Specifies the output mode.
+                               This parameter can be a value of @ref TIM_LL_EC_OCMODE.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_OC_SetMode().*/
+
+  uint32_t OCState;       /*!< Specifies the TIM Output Compare state.
+                               This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
+
+                               This feature can be modified afterwards using unitary functions
+                               @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
+
+  uint32_t OCNState;      /*!< Specifies the TIM complementary Output Compare state.
+                               This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
+
+                               This feature can be modified afterwards using unitary functions
+                               @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
+
+  uint32_t CompareValue;  /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
+                               This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
+
+                               This feature can be modified afterwards using unitary function
+                               LL_TIM_OC_SetCompareCHx (x=1..6).*/
+
+  uint32_t OCPolarity;    /*!< Specifies the output polarity.
+                               This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_OC_SetPolarity().*/
+
+  uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
+                               This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_OC_SetPolarity().*/
+
+
+  uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
+                               This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_OC_SetIdleState().*/
+
+  uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
+                               This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_OC_SetIdleState().*/
+} LL_TIM_OC_InitTypeDef;
+
+/**
+  * @brief  TIM Input Capture configuration structure definition.
+  */
+
+typedef struct
+{
+
+  uint32_t ICPolarity;    /*!< Specifies the active edge of the input signal.
+                               This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_IC_SetPolarity().*/
+
+  uint32_t ICActiveInput; /*!< Specifies the input.
+                               This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_IC_SetActiveInput().*/
+
+  uint32_t ICPrescaler;   /*!< Specifies the Input Capture Prescaler.
+                               This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_IC_SetPrescaler().*/
+
+  uint32_t ICFilter;      /*!< Specifies the input capture filter.
+                               This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_IC_SetFilter().*/
+} LL_TIM_IC_InitTypeDef;
+
+
+/**
+  * @brief  TIM Encoder interface configuration structure definition.
+  */
+typedef struct
+{
+  uint32_t EncoderMode;     /*!< Specifies the encoder resolution (x2 or x4).
+                                 This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_SetEncoderMode().*/
+
+  uint32_t IC1Polarity;     /*!< Specifies the active edge of TI1 input.
+                                 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetPolarity().*/
+
+  uint32_t IC1ActiveInput;  /*!< Specifies the TI1 input source
+                                 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetActiveInput().*/
+
+  uint32_t IC1Prescaler;    /*!< Specifies the TI1 input prescaler value.
+                                 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetPrescaler().*/
+
+  uint32_t IC1Filter;       /*!< Specifies the TI1 input filter.
+                                 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetFilter().*/
+
+  uint32_t IC2Polarity;      /*!< Specifies the active edge of TI2 input.
+                                 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetPolarity().*/
+
+  uint32_t IC2ActiveInput;  /*!< Specifies the TI2 input source
+                                 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetActiveInput().*/
+
+  uint32_t IC2Prescaler;    /*!< Specifies the TI2 input prescaler value.
+                                 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetPrescaler().*/
+
+  uint32_t IC2Filter;       /*!< Specifies the TI2 input filter.
+                                 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetFilter().*/
+
+} LL_TIM_ENCODER_InitTypeDef;
+
+/**
+  * @brief  TIM Hall sensor interface configuration structure definition.
+  */
+typedef struct
+{
+
+  uint32_t IC1Polarity;        /*!< Specifies the active edge of TI1 input.
+                                    This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+
+                                    This feature can be modified afterwards using unitary function
+                                    @ref LL_TIM_IC_SetPolarity().*/
+
+  uint32_t IC1Prescaler;       /*!< Specifies the TI1 input prescaler value.
+                                    Prescaler must be set to get a maximum counter period longer than the
+                                    time interval between 2 consecutive changes on the Hall inputs.
+                                    This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+
+                                    This feature can be modified afterwards using unitary function
+                                    @ref LL_TIM_IC_SetPrescaler().*/
+
+  uint32_t IC1Filter;          /*!< Specifies the TI1 input filter.
+                                    This parameter can be a value of
+                                    @ref TIM_LL_EC_IC_FILTER.
+
+                                    This feature can be modified afterwards using unitary function
+                                    @ref LL_TIM_IC_SetFilter().*/
+
+  uint32_t CommutationDelay;   /*!< Specifies the compare value to be loaded into the Capture Compare Register.
+                                    A positive pulse (TRGO event) is generated with a programmable delay every time
+                                    a change occurs on the Hall inputs.
+                                    This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
+
+                                    This feature can be modified afterwards using unitary function
+                                    @ref LL_TIM_OC_SetCompareCH2().*/
+} LL_TIM_HALLSENSOR_InitTypeDef;
+
+/**
+  * @brief  BDTR (Break and Dead Time) structure definition
+  */
+typedef struct
+{
+  uint32_t OSSRState;            /*!< Specifies the Off-State selection used in Run mode.
+                                      This parameter can be a value of @ref TIM_LL_EC_OSSR
+
+                                      This feature can be modified afterwards using unitary function
+                                      @ref LL_TIM_SetOffStates()
+
+                                      @note This bit-field cannot be modified as long as LOCK level 2 has been
+                                       programmed. */
+
+  uint32_t OSSIState;            /*!< Specifies the Off-State used in Idle state.
+                                      This parameter can be a value of @ref TIM_LL_EC_OSSI
+
+                                      This feature can be modified afterwards using unitary function
+                                      @ref LL_TIM_SetOffStates()
+
+                                      @note This bit-field cannot be modified as long as LOCK level 2 has been
+                                      programmed. */
+
+  uint32_t LockLevel;            /*!< Specifies the LOCK level parameters.
+                                      This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
+
+                                      @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR
+                                      register has been written, their content is frozen until the next reset.*/
+
+  uint8_t DeadTime;              /*!< Specifies the delay time between the switching-off and the
+                                      switching-on of the outputs.
+                                      This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
+
+                                      This feature can be modified afterwards using unitary function
+                                      @ref LL_TIM_OC_SetDeadTime()
+
+                                      @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been
+                                       programmed. */
+
+  uint16_t BreakState;           /*!< Specifies whether the TIM Break input is enabled or not.
+                                      This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
+
+                                      This feature can be modified afterwards using unitary functions
+                                      @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
+
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been
+                                      programmed. */
+
+  uint32_t BreakPolarity;        /*!< Specifies the TIM Break Input pin polarity.
+                                      This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
+
+                                      This feature can be modified afterwards using unitary function
+                                      @ref LL_TIM_ConfigBRK()
+
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been
+                                      programmed. */
+
+  uint32_t BreakFilter;          /*!< Specifies the TIM Break Filter.
+                                      This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER
+
+                                      This feature can be modified afterwards using unitary function
+                                      @ref LL_TIM_ConfigBRK()
+
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been
+                                      programmed. */
+
+#if defined(TIM_BDTR_BKBID)
+  uint32_t BreakAFMode;           /*!< Specifies the alternate function mode of the break input.
+                                      This parameter can be a value of @ref TIM_LL_EC_BREAK_AFMODE
+
+                                      This feature can be modified afterwards using unitary functions
+                                      @ref LL_TIM_ConfigBRK()
+
+                                      @note Bidirectional break input is only supported by advanced timers instances.
+
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been
+                                      programmed. */
+
+#endif /*TIM_BDTR_BKBID */
+  uint32_t Break2State;          /*!< Specifies whether the TIM Break2 input is enabled or not.
+                                      This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE
+
+                                      This feature can be modified afterwards using unitary functions
+                                      @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
+
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been
+                                      programmed. */
+
+  uint32_t Break2Polarity;        /*!< Specifies the TIM Break2 Input pin polarity.
+                                      This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY
+
+                                      This feature can be modified afterwards using unitary function
+                                      @ref LL_TIM_ConfigBRK2()
+
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been
+                                      programmed. */
+
+  uint32_t Break2Filter;          /*!< Specifies the TIM Break2 Filter.
+                                      This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER
+
+                                      This feature can be modified afterwards using unitary function
+                                      @ref LL_TIM_ConfigBRK2()
+
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been
+                                      programmed. */
+
+#if defined(TIM_BDTR_BKBID)
+  uint32_t Break2AFMode;          /*!< Specifies the alternate function mode of the break2 input.
+                                      This parameter can be a value of @ref TIM_LL_EC_BREAK2_AFMODE
+
+                                      This feature can be modified afterwards using unitary functions
+                                      @ref LL_TIM_ConfigBRK2()
+
+                                      @note Bidirectional break input is only supported by advanced timers instances.
+
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been
+                                      programmed. */
+
+#endif /*TIM_BDTR_BKBID */
+  uint32_t AutomaticOutput;      /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
+                                      This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
+
+                                      This feature can be modified afterwards using unitary functions
+                                      @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
+
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been
+                                      programmed. */
+} LL_TIM_BDTR_InitTypeDef;
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
+  * @{
+  */
+
+/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_TIM_ReadReg function.
+  * @{
+  */
+#define LL_TIM_SR_UIF                          TIM_SR_UIF           /*!< Update interrupt flag */
+#define LL_TIM_SR_CC1IF                        TIM_SR_CC1IF         /*!< Capture/compare 1 interrupt flag */
+#define LL_TIM_SR_CC2IF                        TIM_SR_CC2IF         /*!< Capture/compare 2 interrupt flag */
+#define LL_TIM_SR_CC3IF                        TIM_SR_CC3IF         /*!< Capture/compare 3 interrupt flag */
+#define LL_TIM_SR_CC4IF                        TIM_SR_CC4IF         /*!< Capture/compare 4 interrupt flag */
+#define LL_TIM_SR_CC5IF                        TIM_SR_CC5IF         /*!< Capture/compare 5 interrupt flag */
+#define LL_TIM_SR_CC6IF                        TIM_SR_CC6IF         /*!< Capture/compare 6 interrupt flag */
+#define LL_TIM_SR_COMIF                        TIM_SR_COMIF         /*!< COM interrupt flag */
+#define LL_TIM_SR_TIF                          TIM_SR_TIF           /*!< Trigger interrupt flag */
+#define LL_TIM_SR_BIF                          TIM_SR_BIF           /*!< Break interrupt flag */
+#define LL_TIM_SR_B2IF                         TIM_SR_B2IF          /*!< Second break interrupt flag */
+#define LL_TIM_SR_CC1OF                        TIM_SR_CC1OF         /*!< Capture/Compare 1 overcapture flag */
+#define LL_TIM_SR_CC2OF                        TIM_SR_CC2OF         /*!< Capture/Compare 2 overcapture flag */
+#define LL_TIM_SR_CC3OF                        TIM_SR_CC3OF         /*!< Capture/Compare 3 overcapture flag */
+#define LL_TIM_SR_CC4OF                        TIM_SR_CC4OF         /*!< Capture/Compare 4 overcapture flag */
+#define LL_TIM_SR_SBIF                         TIM_SR_SBIF          /*!< System Break interrupt flag  */
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
+  * @{
+  */
+#define LL_TIM_BREAK_DISABLE            0x00000000U             /*!< Break function disabled */
+#define LL_TIM_BREAK_ENABLE             TIM_BDTR_BKE            /*!< Break function enabled */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable
+  * @{
+  */
+#define LL_TIM_BREAK2_DISABLE            0x00000000U              /*!< Break2 function disabled */
+#define LL_TIM_BREAK2_ENABLE             TIM_BDTR_BK2E            /*!< Break2 function enabled */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
+  * @{
+  */
+#define LL_TIM_AUTOMATICOUTPUT_DISABLE         0x00000000U             /*!< MOE can be set only by software */
+#define LL_TIM_AUTOMATICOUTPUT_ENABLE          TIM_BDTR_AOE            /*!< MOE can be set by software or automatically at the next update event */
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/** @defgroup TIM_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_TIM_ReadReg and  LL_TIM_WriteReg functions.
+  * @{
+  */
+#define LL_TIM_DIER_UIE                        TIM_DIER_UIE         /*!< Update interrupt enable */
+#define LL_TIM_DIER_CC1IE                      TIM_DIER_CC1IE       /*!< Capture/compare 1 interrupt enable */
+#define LL_TIM_DIER_CC2IE                      TIM_DIER_CC2IE       /*!< Capture/compare 2 interrupt enable */
+#define LL_TIM_DIER_CC3IE                      TIM_DIER_CC3IE       /*!< Capture/compare 3 interrupt enable */
+#define LL_TIM_DIER_CC4IE                      TIM_DIER_CC4IE       /*!< Capture/compare 4 interrupt enable */
+#define LL_TIM_DIER_COMIE                      TIM_DIER_COMIE       /*!< COM interrupt enable */
+#define LL_TIM_DIER_TIE                        TIM_DIER_TIE         /*!< Trigger interrupt enable */
+#define LL_TIM_DIER_BIE                        TIM_DIER_BIE         /*!< Break interrupt enable */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
+  * @{
+  */
+#define LL_TIM_UPDATESOURCE_REGULAR            0x00000000U          /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
+#define LL_TIM_UPDATESOURCE_COUNTER            TIM_CR1_URS          /*!< Only counter overflow/underflow generates an update request */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
+  * @{
+  */
+#define LL_TIM_ONEPULSEMODE_SINGLE             TIM_CR1_OPM          /*!< Counter stops counting at the next update event */
+#define LL_TIM_ONEPULSEMODE_REPETITIVE         0x00000000U          /*!< Counter is not stopped at update event */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
+  * @{
+  */
+#define LL_TIM_COUNTERMODE_UP                  0x00000000U          /*!<Counter used as upcounter */
+#define LL_TIM_COUNTERMODE_DOWN                TIM_CR1_DIR          /*!< Counter used as downcounter */
+#define LL_TIM_COUNTERMODE_CENTER_DOWN         TIM_CR1_CMS_0        /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting down. */
+#define LL_TIM_COUNTERMODE_CENTER_UP           TIM_CR1_CMS_1        /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting up */
+#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN      TIM_CR1_CMS          /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting up or down. */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
+  * @{
+  */
+#define LL_TIM_CLOCKDIVISION_DIV1              0x00000000U          /*!< tDTS=tCK_INT */
+#define LL_TIM_CLOCKDIVISION_DIV2              TIM_CR1_CKD_0        /*!< tDTS=2*tCK_INT */
+#define LL_TIM_CLOCKDIVISION_DIV4              TIM_CR1_CKD_1        /*!< tDTS=4*tCK_INT */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
+  * @{
+  */
+#define LL_TIM_COUNTERDIRECTION_UP             0x00000000U          /*!< Timer counter counts up */
+#define LL_TIM_COUNTERDIRECTION_DOWN           TIM_CR1_DIR          /*!< Timer counter counts down */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare  Update Source
+  * @{
+  */
+#define LL_TIM_CCUPDATESOURCE_COMG_ONLY        0x00000000U          /*!< Capture/compare control bits are updated by setting the COMG bit only */
+#define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI    TIM_CR2_CCUS         /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
+  * @{
+  */
+#define LL_TIM_CCDMAREQUEST_CC                 0x00000000U          /*!< CCx DMA request sent when CCx event occurs */
+#define LL_TIM_CCDMAREQUEST_UPDATE             TIM_CR2_CCDS         /*!< CCx DMA requests sent when update event occurs */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
+  * @{
+  */
+#define LL_TIM_LOCKLEVEL_OFF                   0x00000000U          /*!< LOCK OFF - No bit is write protected */
+#define LL_TIM_LOCKLEVEL_1                     TIM_BDTR_LOCK_0      /*!< LOCK Level 1 */
+#define LL_TIM_LOCKLEVEL_2                     TIM_BDTR_LOCK_1      /*!< LOCK Level 2 */
+#define LL_TIM_LOCKLEVEL_3                     TIM_BDTR_LOCK        /*!< LOCK Level 3 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_CHANNEL Channel
+  * @{
+  */
+#define LL_TIM_CHANNEL_CH1                     TIM_CCER_CC1E     /*!< Timer input/output channel 1 */
+#define LL_TIM_CHANNEL_CH1N                    TIM_CCER_CC1NE    /*!< Timer complementary output channel 1 */
+#define LL_TIM_CHANNEL_CH2                     TIM_CCER_CC2E     /*!< Timer input/output channel 2 */
+#define LL_TIM_CHANNEL_CH2N                    TIM_CCER_CC2NE    /*!< Timer complementary output channel 2 */
+#define LL_TIM_CHANNEL_CH3                     TIM_CCER_CC3E     /*!< Timer input/output channel 3 */
+#define LL_TIM_CHANNEL_CH3N                    TIM_CCER_CC3NE    /*!< Timer complementary output channel 3 */
+#define LL_TIM_CHANNEL_CH4                     TIM_CCER_CC4E     /*!< Timer input/output channel 4 */
+#define LL_TIM_CHANNEL_CH5                     TIM_CCER_CC5E     /*!< Timer output channel 5 */
+#define LL_TIM_CHANNEL_CH6                     TIM_CCER_CC6E     /*!< Timer output channel 6 */
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
+  * @{
+  */
+#define LL_TIM_OCSTATE_DISABLE                 0x00000000U             /*!< OCx is not active */
+#define LL_TIM_OCSTATE_ENABLE                  TIM_CCER_CC1E           /*!< OCx signal is output on the corresponding output pin */
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
+  * @{
+  */
+#define LL_TIM_OCMODE_FROZEN                   0x00000000U                                              /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
+#define LL_TIM_OCMODE_ACTIVE                   TIM_CCMR1_OC1M_0                                         /*!<OCyREF is forced high on compare match*/
+#define LL_TIM_OCMODE_INACTIVE                 TIM_CCMR1_OC1M_1                                         /*!<OCyREF is forced low on compare match*/
+#define LL_TIM_OCMODE_TOGGLE                   (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)                    /*!<OCyREF toggles on compare match*/
+#define LL_TIM_OCMODE_FORCED_INACTIVE          TIM_CCMR1_OC1M_2                                         /*!<OCyREF is forced low*/
+#define LL_TIM_OCMODE_FORCED_ACTIVE            (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)                    /*!<OCyREF is forced high*/
+#define LL_TIM_OCMODE_PWM1                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)                    /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive.  In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
+#define LL_TIM_OCMODE_PWM2                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active.  In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
+#define LL_TIM_OCMODE_RETRIG_OPM1              TIM_CCMR1_OC1M_3                                         /*!<Retrigerrable OPM mode 1*/
+#define LL_TIM_OCMODE_RETRIG_OPM2              (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)                    /*!<Retrigerrable OPM mode 2*/
+#define LL_TIM_OCMODE_COMBINED_PWM1            (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)                    /*!<Combined PWM mode 1*/
+#define LL_TIM_OCMODE_COMBINED_PWM2            (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 2*/
+#define LL_TIM_OCMODE_ASSYMETRIC_PWM1          (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/
+#define LL_TIM_OCMODE_ASSYMETRIC_PWM2          (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M)                      /*!<Asymmetric PWM mode 2*/
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
+  * @{
+  */
+#define LL_TIM_OCPOLARITY_HIGH                 0x00000000U                 /*!< OCxactive high*/
+#define LL_TIM_OCPOLARITY_LOW                  TIM_CCER_CC1P               /*!< OCxactive low*/
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
+  * @{
+  */
+#define LL_TIM_OCIDLESTATE_LOW                 0x00000000U             /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
+#define LL_TIM_OCIDLESTATE_HIGH                TIM_CR2_OIS1            /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5
+  * @{
+  */
+#define LL_TIM_GROUPCH5_NONE                   0x00000000U           /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
+#define LL_TIM_GROUPCH5_OC1REFC                TIM_CCR5_GC5C1        /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */
+#define LL_TIM_GROUPCH5_OC2REFC                TIM_CCR5_GC5C2        /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */
+#define LL_TIM_GROUPCH5_OC3REFC                TIM_CCR5_GC5C3        /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
+  * @{
+  */
+#define LL_TIM_ACTIVEINPUT_DIRECTTI            (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
+#define LL_TIM_ACTIVEINPUT_INDIRECTTI          (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
+#define LL_TIM_ACTIVEINPUT_TRC                 (TIM_CCMR1_CC1S << 16U)   /*!< ICx is mapped on TRC */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
+  * @{
+  */
+#define LL_TIM_ICPSC_DIV1                      0x00000000U                    /*!< No prescaler, capture is done each time an edge is detected on the capture input */
+#define LL_TIM_ICPSC_DIV2                      (TIM_CCMR1_IC1PSC_0 << 16U)    /*!< Capture is done once every 2 events */
+#define LL_TIM_ICPSC_DIV4                      (TIM_CCMR1_IC1PSC_1 << 16U)    /*!< Capture is done once every 4 events */
+#define LL_TIM_ICPSC_DIV8                      (TIM_CCMR1_IC1PSC << 16U)      /*!< Capture is done once every 8 events */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
+  * @{
+  */
+#define LL_TIM_IC_FILTER_FDIV1                 0x00000000U                                                        /*!< No filter, sampling is done at fDTS */
+#define LL_TIM_IC_FILTER_FDIV1_N2              (TIM_CCMR1_IC1F_0 << 16U)                                          /*!< fSAMPLING=fCK_INT, N=2 */
+#define LL_TIM_IC_FILTER_FDIV1_N4              (TIM_CCMR1_IC1F_1 << 16U)                                          /*!< fSAMPLING=fCK_INT, N=4 */
+#define LL_TIM_IC_FILTER_FDIV1_N8              ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fCK_INT, N=8 */
+#define LL_TIM_IC_FILTER_FDIV2_N6              (TIM_CCMR1_IC1F_2 << 16U)                                          /*!< fSAMPLING=fDTS/2, N=6 */
+#define LL_TIM_IC_FILTER_FDIV2_N8              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fDTS/2, N=8 */
+#define LL_TIM_IC_FILTER_FDIV4_N6              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)                     /*!< fSAMPLING=fDTS/4, N=6 */
+#define LL_TIM_IC_FILTER_FDIV4_N8              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/4, N=8 */
+#define LL_TIM_IC_FILTER_FDIV8_N6              (TIM_CCMR1_IC1F_3 << 16U)                                          /*!< fSAMPLING=fDTS/8, N=6 */
+#define LL_TIM_IC_FILTER_FDIV8_N8              ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fDTS/8, N=8 */
+#define LL_TIM_IC_FILTER_FDIV16_N5             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U)                     /*!< fSAMPLING=fDTS/16, N=5 */
+#define LL_TIM_IC_FILTER_FDIV16_N6             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/16, N=6 */
+#define LL_TIM_IC_FILTER_FDIV16_N8             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U)                     /*!< fSAMPLING=fDTS/16, N=8 */
+#define LL_TIM_IC_FILTER_FDIV32_N5             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/32, N=5 */
+#define LL_TIM_IC_FILTER_FDIV32_N6             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)  /*!< fSAMPLING=fDTS/32, N=6 */
+#define LL_TIM_IC_FILTER_FDIV32_N8             (TIM_CCMR1_IC1F << 16U)                                            /*!< fSAMPLING=fDTS/32, N=8 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
+  * @{
+  */
+#define LL_TIM_IC_POLARITY_RISING              0x00000000U                      /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
+#define LL_TIM_IC_POLARITY_FALLING             TIM_CCER_CC1P                    /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
+#define LL_TIM_IC_POLARITY_BOTHEDGE            (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
+  * @{
+  */
+#define LL_TIM_CLOCKSOURCE_INTERNAL            0x00000000U                                          /*!< The timer is clocked by the internal clock provided from the RCC */
+#define LL_TIM_CLOCKSOURCE_EXT_MODE1           (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)   /*!< Counter counts at each rising or falling edge on a selected input*/
+#define LL_TIM_CLOCKSOURCE_EXT_MODE2           TIM_SMCR_ECE                                         /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
+  * @{
+  */
+#define LL_TIM_ENCODERMODE_X2_TI1                     TIM_SMCR_SMS_0                                                     /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
+#define LL_TIM_ENCODERMODE_X2_TI2                     TIM_SMCR_SMS_1                                                     /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
+#define LL_TIM_ENCODERMODE_X4_TI12                   (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)                                   /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TRGO Trigger Output
+  * @{
+  */
+#define LL_TIM_TRGO_RESET                      0x00000000U                                     /*!< UG bit from the TIMx_EGR register is used as trigger output */
+#define LL_TIM_TRGO_ENABLE                     TIM_CR2_MMS_0                                   /*!< Counter Enable signal (CNT_EN) is used as trigger output */
+#define LL_TIM_TRGO_UPDATE                     TIM_CR2_MMS_1                                   /*!< Update event is used as trigger output */
+#define LL_TIM_TRGO_CC1IF                      (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)                 /*!< CC1 capture or a compare match is used as trigger output */
+#define LL_TIM_TRGO_OC1REF                     TIM_CR2_MMS_2                                   /*!< OC1REF signal is used as trigger output */
+#define LL_TIM_TRGO_OC2REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)                 /*!< OC2REF signal is used as trigger output */
+#define LL_TIM_TRGO_OC3REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)                 /*!< OC3REF signal is used as trigger output */
+#define LL_TIM_TRGO_OC4REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2
+  * @{
+  */
+#define LL_TIM_TRGO2_RESET                     0x00000000U                                                         /*!< UG bit from the TIMx_EGR register is used as trigger output 2 */
+#define LL_TIM_TRGO2_ENABLE                    TIM_CR2_MMS2_0                                                      /*!< Counter Enable signal (CNT_EN) is used as trigger output 2 */
+#define LL_TIM_TRGO2_UPDATE                    TIM_CR2_MMS2_1                                                      /*!< Update event is used as trigger output 2 */
+#define LL_TIM_TRGO2_CC1F                      (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                                   /*!< CC1 capture or a compare match is used as trigger output 2 */
+#define LL_TIM_TRGO2_OC1                       TIM_CR2_MMS2_2                                                      /*!< OC1REF signal is used as trigger output 2 */
+#define LL_TIM_TRGO2_OC2                       (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)                                   /*!< OC2REF signal is used as trigger output 2 */
+#define LL_TIM_TRGO2_OC3                       (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)                                   /*!< OC3REF signal is used as trigger output 2 */
+#define LL_TIM_TRGO2_OC4                       (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                  /*!< OC4REF signal is used as trigger output 2 */
+#define LL_TIM_TRGO2_OC5                       TIM_CR2_MMS2_3                                                      /*!< OC5REF signal is used as trigger output 2 */
+#define LL_TIM_TRGO2_OC6                       (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)                                   /*!< OC6REF signal is used as trigger output 2 */
+#define LL_TIM_TRGO2_OC4_RISINGFALLING         (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)                                   /*!< OC4REF rising or falling edges are used as trigger output 2 */
+#define LL_TIM_TRGO2_OC6_RISINGFALLING         (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                  /*!< OC6REF rising or falling edges are used as trigger output 2 */
+#define LL_TIM_TRGO2_OC4_RISING_OC6_RISING     (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)                                   /*!< OC4REF or OC6REF rising edges are used as trigger output 2 */
+#define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING    (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)                  /*!< OC4REF rising or OC6REF falling edges are used as trigger output 2 */
+#define LL_TIM_TRGO2_OC5_RISING_OC6_RISING     (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)                   /*!< OC5REF or OC6REF rising edges are used as trigger output 2 */
+#define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING    (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF rising or OC6REF falling edges are used as trigger output 2 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
+  * @{
+  */
+#define LL_TIM_SLAVEMODE_DISABLED              0x00000000U                         /*!< Slave mode disabled */
+#define LL_TIM_SLAVEMODE_RESET                 TIM_SMCR_SMS_2                      /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
+#define LL_TIM_SLAVEMODE_GATED                 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)   /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
+#define LL_TIM_SLAVEMODE_TRIGGER               (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)   /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
+#define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3                      /*!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI)  reinitializes the counter, generates an update of the registers and starts the counter */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TS Trigger Selection
+  * @{
+  */
+#define LL_TIM_TS_ITR0                         0x00000000U                                                     /*!< Internal Trigger 0 (ITR0) is used as trigger input */
+#define LL_TIM_TS_ITR1                         TIM_SMCR_TS_0                                                   /*!< Internal Trigger 1 (ITR1) is used as trigger input */
+#define LL_TIM_TS_ITR2                         TIM_SMCR_TS_1                                                   /*!< Internal Trigger 2 (ITR2) is used as trigger input */
+#define LL_TIM_TS_ITR3                         (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)                                 /*!< Internal Trigger 3 (ITR3) is used as trigger input */
+#define LL_TIM_TS_ITR4                         (TIM_SMCR_TS_3)                                                 /*!< Internal Trigger 4 (ITR4) is used as trigger input */
+#define LL_TIM_TS_ITR5                         (TIM_SMCR_TS_0 | TIM_SMCR_TS_3)                                 /*!< Internal Trigger 5 (ITR5) is used as trigger input */
+#define LL_TIM_TS_ITR6                         (TIM_SMCR_TS_1 | TIM_SMCR_TS_3)                                 /*!< Internal Trigger 6 (ITR6) is used as trigger input */
+#define LL_TIM_TS_ITR7                         (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_3)                 /*!< Internal Trigger 7 (ITR7) is used as trigger input */
+#define LL_TIM_TS_ITR8                         (TIM_SMCR_TS_2 | TIM_SMCR_TS_3)                                 /*!< Internal Trigger 8 (ITR8) is used as trigger input */
+#define LL_TIM_TS_ITR9                         (TIM_SMCR_TS_0 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)                 /*!< Internal Trigger 9 (ITR9) is used as trigger input */
+#define LL_TIM_TS_ITR10                        (TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)                 /*!< Internal Trigger 10 (ITR10) is used as trigger input */
+#define LL_TIM_TS_ITR11                        (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 11 (ITR11) is used as trigger input */
+#define LL_TIM_TS_ITR12                        (TIM_SMCR_TS_4)                                                 /*!< Internal Trigger 12 (ITR12) is used as trigger input */
+#define LL_TIM_TS_ITR13                        (TIM_SMCR_TS_0 | TIM_SMCR_TS_4)                                 /*!< Internal Trigger 13 (ITR13) is used as trigger input */
+#define LL_TIM_TS_TI1F_ED                      TIM_SMCR_TS_2                                                   /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
+#define LL_TIM_TS_TI1FP1                       (TIM_SMCR_TS_2 | TIM_SMCR_TS_0)                                 /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
+#define LL_TIM_TS_TI2FP2                       (TIM_SMCR_TS_2 | TIM_SMCR_TS_1)                                 /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
+#define LL_TIM_TS_ETRF                         (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0)                 /*!< Filtered external Trigger (ETRF) is used as trigger input */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
+  * @{
+  */
+#define LL_TIM_ETR_POLARITY_NONINVERTED        0x00000000U             /*!< ETR is non-inverted, active at high level or rising edge */
+#define LL_TIM_ETR_POLARITY_INVERTED           TIM_SMCR_ETP            /*!< ETR is inverted, active at low level or falling edge */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
+  * @{
+  */
+#define LL_TIM_ETR_PRESCALER_DIV1              0x00000000U             /*!< ETR prescaler OFF */
+#define LL_TIM_ETR_PRESCALER_DIV2              TIM_SMCR_ETPS_0         /*!< ETR frequency is divided by 2 */
+#define LL_TIM_ETR_PRESCALER_DIV4              TIM_SMCR_ETPS_1         /*!< ETR frequency is divided by 4 */
+#define LL_TIM_ETR_PRESCALER_DIV8              TIM_SMCR_ETPS           /*!< ETR frequency is divided by 8 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
+  * @{
+  */
+#define LL_TIM_ETR_FILTER_FDIV1                0x00000000U                                          /*!< No filter, sampling is done at fDTS */
+#define LL_TIM_ETR_FILTER_FDIV1_N2             TIM_SMCR_ETF_0                                       /*!< fSAMPLING=fCK_INT, N=2 */
+#define LL_TIM_ETR_FILTER_FDIV1_N4             TIM_SMCR_ETF_1                                       /*!< fSAMPLING=fCK_INT, N=4 */
+#define LL_TIM_ETR_FILTER_FDIV1_N8             (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fCK_INT, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV2_N6             TIM_SMCR_ETF_2                                       /*!< fSAMPLING=fDTS/2, N=6 */
+#define LL_TIM_ETR_FILTER_FDIV2_N8             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fDTS/2, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV4_N6             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)                    /*!< fSAMPLING=fDTS/4, N=6 */
+#define LL_TIM_ETR_FILTER_FDIV4_N8             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/4, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV8_N6             TIM_SMCR_ETF_3                                       /*!< fSAMPLING=fDTS/8, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV8_N8             (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fDTS/16, N=5 */
+#define LL_TIM_ETR_FILTER_FDIV16_N5            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1)                    /*!< fSAMPLING=fDTS/16, N=6 */
+#define LL_TIM_ETR_FILTER_FDIV16_N6            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/16, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV16_N8            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2)                    /*!< fSAMPLING=fDTS/16, N=5 */
+#define LL_TIM_ETR_FILTER_FDIV32_N5            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/32, N=5 */
+#define LL_TIM_ETR_FILTER_FDIV32_N6            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)   /*!< fSAMPLING=fDTS/32, N=6 */
+#define LL_TIM_ETR_FILTER_FDIV32_N8            TIM_SMCR_ETF                                         /*!< fSAMPLING=fDTS/32, N=8 */
+/**
+  * @}
+  */
+
+#define LL_TIM_TIM1_ETRSOURCE_GPIO        0x00000000U                                                 /* !< TIM1_ETR is connected to GPIO */
+#define LL_TIM_TIM1_ETRSOURCE_COMP1       TIM1_AF1_ETRSEL_0                                           /* !< TIM1_ETR is connected to COMP1 OUT */
+#define LL_TIM_TIM1_ETRSOURCE_COMP2       TIM1_AF1_ETRSEL_1                                           /* !< TIM1_ETR is connected to COMP2 OUT */
+#define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1   (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)                     /* !< TIM1_ETR is connected to ADC1 AWD1 */
+#define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2   (TIM1_AF1_ETRSEL_2)                                         /* !< TIM1_ETR is connected to ADC1 AWD2 */
+#define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3   (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)                     /* !< TIM1_ETR is connected to ADC1 AWD3 */
+#define LL_TIM_TIM1_ETRSOURCE_ADC3_AWD1   (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1)                     /* !< TIM1_ETR is connected to ADC3 AWD1 */
+#define LL_TIM_TIM1_ETRSOURCE_ADC3_AWD2   (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC3 AWD2 */
+#define LL_TIM_TIM1_ETRSOURCE_ADC3_AWD3   TIM1_AF1_ETRSEL_3                                           /* !< TIM1_ETR is connected to ADC3 AWD3 */
+
+#define LL_TIM_TIM8_ETRSOURCE_GPIO        0x00000000U                                                 /* !< TIM8_ETR is connected to GPIO */
+#define LL_TIM_TIM8_ETRSOURCE_COMP1       TIM8_AF1_ETRSEL_0                                           /* !< TIM8_ETR is connected to COMP1 OUT */
+#define LL_TIM_TIM8_ETRSOURCE_COMP2       TIM8_AF1_ETRSEL_1                                           /* !< TIM8_ETR is connected to COMP2 OUT */
+#define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1   (TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0)                     /* !< TIM8_ETR is connected to ADC2 AWD1 */
+#define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2   (TIM8_AF1_ETRSEL_2)                                         /* !< TIM8_ETR is connected to ADC2 AWD2 */
+#define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3   (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0)                     /* !< TIM8_ETR is connected to ADC2 AWD3 */
+#define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD1   (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1)                     /* !< TIM8_ETR is connected to ADC3 AWD1 */
+#define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD2   (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC3 AWD2 */
+#define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD3   TIM8_AF1_ETRSEL_3                                           /* !< TIM8_ETR is connected to ADC3 AWD3 */
+
+#define LL_TIM_TIM2_ETRSOURCE_GPIO        0x00000000U                                                 /* !< TIM2_ETR is connected to GPIO */
+#define LL_TIM_TIM2_ETRSOURCE_COMP1       (TIM2_AF1_ETRSEL_0)                                         /* !< TIM2_ETR is connected to COMP1 OUT */
+#define LL_TIM_TIM2_ETRSOURCE_COMP2       (TIM2_AF1_ETRSEL_1)                                         /* !< TIM2_ETR is connected to COMP2 OUT */
+#define LL_TIM_TIM2_ETRSOURCE_RCC_LSE     (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0)                     /* !< TIM2_ETR is connected to RCC LSE */
+#define LL_TIM_TIM2_ETRSOURCE_SAI1_FSA    TIM2_AF1_ETRSEL_2                                           /* !< TIM2_ETR is connected to SAI1 FS_A */
+#define LL_TIM_TIM2_ETRSOURCE_SAI1_FSB    (TIM2_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0)                     /* !< TIM2_ETR is connected to SAI1 FS_B */
+
+#define LL_TIM_TIM3_ETRSOURCE_GPIO        0x00000000U                                                 /* !< TIM3_ETR is connected to GPIO */
+#define LL_TIM_TIM3_ETRSOURCE_COMP1       TIM3_AF1_ETRSEL_0                                           /* !< TIM3_ETR is connected to COMP1 OUT */
+
+#define LL_TIM_TIM5_ETRSOURCE_GPIO        0x00000000U                                                 /* !< TIM5_ETR is connected to GPIO */
+#define LL_TIM_TIM5_ETRSOURCE_SAI2_FSA    TIM5_AF1_ETRSEL_0                                           /* !< TIM5_ETR is connected to SAI2 FS_A */
+#define LL_TIM_TIM5_ETRSOURCE_SAI2_FSB    TIM5_AF1_ETRSEL_1                                           /* !< TIM5_ETR is connected to SAI2 FS_B */
+#define LL_TIM_TIM5_ETRSOURCE_SAI4_FSA    TIM5_AF1_ETRSEL_0                                           /* !< TIM5_ETR is connected to SAI4 FS_A */
+#define LL_TIM_TIM5_ETRSOURCE_SAI4_FSB    TIM5_AF1_ETRSEL_1                                           /* !< TIM5_ETR is connected to SAI4 FS_B */
+
+#define LL_TIM_TIM23_ETRSOURCE_GPIO       0x00000000U                                                 /* !< TIM23_ETR is connected to GPIO */
+#define LL_TIM_TIM23_ETRSOURCE_COMP1      (TIM2_AF1_ETRSEL_0)                                         /* !< TIM23_ETR is connected to COMP1 OUT */
+#define LL_TIM_TIM23_ETRSOURCE_COMP2      (TIM2_AF1_ETRSEL_1)                                         /* !< TIM23_ETR is connected to COMP2 OUT */
+
+#define LL_TIM_TIM24_ETRSOURCE_GPIO        0x00000000U                                                /* !< TIM24_ETR is connected to GPIO */
+#define LL_TIM_TIM24_ETRSOURCE_SAI4_FSA    TIM5_AF1_ETRSEL_0                                          /* !< TIM24_ETR is connected to SAI4 FS_A */
+#define LL_TIM_TIM24_ETRSOURCE_SAI4_FSB    TIM5_AF1_ETRSEL_1                                          /* !< TIM24_ETR is connected to SAI4 FS_B */
+#define LL_TIM_TIM24_ETRSOURCE_SAI1_FSA    (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0)                    /* !< TIM24_ETR is connected to SAI1 FS_A */
+#define LL_TIM_TIM24_ETRSOURCE_SAI1_FSB    TIM2_AF1_ETRSEL_2                                          /* !< TIM24_ETR is connected to SAI1 FS_B */
+
+/** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
+  * @{
+  */
+#define LL_TIM_BREAK_POLARITY_LOW              0x00000000U               /*!< Break input BRK is active low */
+#define LL_TIM_BREAK_POLARITY_HIGH             TIM_BDTR_BKP              /*!< Break input BRK is active high */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_BREAK_FILTER break filter
+  * @{
+  */
+#define LL_TIM_BREAK_FILTER_FDIV1              0x00000000U   /*!< No filter, BRK acts asynchronously */
+#define LL_TIM_BREAK_FILTER_FDIV1_N2           0x00010000U   /*!< fSAMPLING=fCK_INT, N=2 */
+#define LL_TIM_BREAK_FILTER_FDIV1_N4           0x00020000U   /*!< fSAMPLING=fCK_INT, N=4 */
+#define LL_TIM_BREAK_FILTER_FDIV1_N8           0x00030000U   /*!< fSAMPLING=fCK_INT, N=8 */
+#define LL_TIM_BREAK_FILTER_FDIV2_N6           0x00040000U   /*!< fSAMPLING=fDTS/2, N=6 */
+#define LL_TIM_BREAK_FILTER_FDIV2_N8           0x00050000U   /*!< fSAMPLING=fDTS/2, N=8 */
+#define LL_TIM_BREAK_FILTER_FDIV4_N6           0x00060000U   /*!< fSAMPLING=fDTS/4, N=6 */
+#define LL_TIM_BREAK_FILTER_FDIV4_N8           0x00070000U   /*!< fSAMPLING=fDTS/4, N=8 */
+#define LL_TIM_BREAK_FILTER_FDIV8_N6           0x00080000U   /*!< fSAMPLING=fDTS/8, N=6 */
+#define LL_TIM_BREAK_FILTER_FDIV8_N8           0x00090000U   /*!< fSAMPLING=fDTS/8, N=8 */
+#define LL_TIM_BREAK_FILTER_FDIV16_N5          0x000A0000U   /*!< fSAMPLING=fDTS/16, N=5 */
+#define LL_TIM_BREAK_FILTER_FDIV16_N6          0x000B0000U   /*!< fSAMPLING=fDTS/16, N=6 */
+#define LL_TIM_BREAK_FILTER_FDIV16_N8          0x000C0000U   /*!< fSAMPLING=fDTS/16, N=8 */
+#define LL_TIM_BREAK_FILTER_FDIV32_N5          0x000D0000U   /*!< fSAMPLING=fDTS/32, N=5 */
+#define LL_TIM_BREAK_FILTER_FDIV32_N6          0x000E0000U   /*!< fSAMPLING=fDTS/32, N=6 */
+#define LL_TIM_BREAK_FILTER_FDIV32_N8          0x000F0000U   /*!< fSAMPLING=fDTS/32, N=8 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY
+  * @{
+  */
+#define LL_TIM_BREAK2_POLARITY_LOW             0x00000000U             /*!< Break input BRK2 is active low */
+#define LL_TIM_BREAK2_POLARITY_HIGH            TIM_BDTR_BK2P           /*!< Break input BRK2 is active high */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER
+  * @{
+  */
+#define LL_TIM_BREAK2_FILTER_FDIV1             0x00000000U   /*!< No filter, BRK acts asynchronously */
+#define LL_TIM_BREAK2_FILTER_FDIV1_N2          0x00100000U   /*!< fSAMPLING=fCK_INT, N=2 */
+#define LL_TIM_BREAK2_FILTER_FDIV1_N4          0x00200000U   /*!< fSAMPLING=fCK_INT, N=4 */
+#define LL_TIM_BREAK2_FILTER_FDIV1_N8          0x00300000U   /*!< fSAMPLING=fCK_INT, N=8 */
+#define LL_TIM_BREAK2_FILTER_FDIV2_N6          0x00400000U   /*!< fSAMPLING=fDTS/2, N=6 */
+#define LL_TIM_BREAK2_FILTER_FDIV2_N8          0x00500000U   /*!< fSAMPLING=fDTS/2, N=8 */
+#define LL_TIM_BREAK2_FILTER_FDIV4_N6          0x00600000U   /*!< fSAMPLING=fDTS/4, N=6 */
+#define LL_TIM_BREAK2_FILTER_FDIV4_N8          0x00700000U   /*!< fSAMPLING=fDTS/4, N=8 */
+#define LL_TIM_BREAK2_FILTER_FDIV8_N6          0x00800000U   /*!< fSAMPLING=fDTS/8, N=6 */
+#define LL_TIM_BREAK2_FILTER_FDIV8_N8          0x00900000U   /*!< fSAMPLING=fDTS/8, N=8 */
+#define LL_TIM_BREAK2_FILTER_FDIV16_N5         0x00A00000U   /*!< fSAMPLING=fDTS/16, N=5 */
+#define LL_TIM_BREAK2_FILTER_FDIV16_N6         0x00B00000U   /*!< fSAMPLING=fDTS/16, N=6 */
+#define LL_TIM_BREAK2_FILTER_FDIV16_N8         0x00C00000U   /*!< fSAMPLING=fDTS/16, N=8 */
+#define LL_TIM_BREAK2_FILTER_FDIV32_N5         0x00D00000U   /*!< fSAMPLING=fDTS/32, N=5 */
+#define LL_TIM_BREAK2_FILTER_FDIV32_N6         0x00E00000U   /*!< fSAMPLING=fDTS/32, N=6 */
+#define LL_TIM_BREAK2_FILTER_FDIV32_N8         0x00F00000U   /*!< fSAMPLING=fDTS/32, N=8 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_OSSI OSSI
+  * @{
+  */
+#define LL_TIM_OSSI_DISABLE                    0x00000000U             /*!< When inactive, OCx/OCxN outputs are disabled */
+#define LL_TIM_OSSI_ENABLE                     TIM_BDTR_OSSI           /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_OSSR OSSR
+  * @{
+  */
+#define LL_TIM_OSSR_DISABLE                    0x00000000U             /*!< When inactive, OCx/OCxN outputs are disabled */
+#define LL_TIM_OSSR_ENABLE                     TIM_BDTR_OSSR           /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */
+/**
+  * @}
+  */
+
+#if   defined(TIM_BREAK_INPUT_SUPPORT)
+/** @defgroup TIM_LL_EC_BREAK_INPUT BREAK INPUT
+  * @{
+  */
+#define LL_TIM_BREAK_INPUT_BKIN                0x00000000U  /*!< TIMx_BKIN input */
+#define LL_TIM_BREAK_INPUT_BKIN2               0x00000004U  /*!< TIMx_BKIN2 input */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_BKIN_SOURCE BKIN SOURCE
+  * @{
+  */
+#define LL_TIM_BKIN_SOURCE_BKIN                TIM1_AF1_BKINE      /*!< BKIN input from AF controller */
+#define LL_TIM_BKIN_SOURCE_BKCOMP1             TIM1_AF1_BKCMP1E    /*!< internal signal: COMP1 output */
+#define LL_TIM_BKIN_SOURCE_BKCOMP2             TIM1_AF1_BKCMP2E    /*!< internal signal: COMP2 output */
+#define LL_TIM_BKIN_SOURCE_DF1BK               TIM1_AF1_BKDF1BK0E  /*!< internal signal: DFSDM1 break output */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_BKIN_POLARITY BKIN POLARITY
+  * @{
+  */
+#define LL_TIM_BKIN_POLARITY_LOW               TIM1_AF1_BKINP           /*!< BRK BKIN input is active low */
+#define LL_TIM_BKIN_POLARITY_HIGH              0x00000000U              /*!< BRK BKIN input is active high */
+/**
+  * @}
+  */
+#endif /* TIM_BREAK_INPUT_SUPPORT */
+
+#if defined(TIM_BDTR_BKBID)
+/** @defgroup TIM_LL_EC_BREAK_AFMODE BREAK AF MODE
+  * @{
+  */
+#define LL_TIM_BREAK_AFMODE_INPUT              0x00000000U              /*!< Break input BRK in input mode */
+#define LL_TIM_BREAK_AFMODE_BIDIRECTIONAL      TIM_BDTR_BKBID           /*!< Break input BRK in bidirectional mode */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_BREAK2_AFMODE BREAK2 AF MODE
+  * @{
+  */
+#define LL_TIM_BREAK2_AFMODE_INPUT             0x00000000U             /*!< Break2 input BRK2 in input mode */
+#define LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL     TIM_BDTR_BK2BID         /*!< Break2 input BRK2 in bidirectional mode */
+/**
+  * @}
+  */
+
+#endif /*TIM_BDTR_BKBID */
+/** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
+  * @{
+  */
+#define LL_TIM_DMABURST_BASEADDR_CR1           0x00000000U                                                      /*!< TIMx_CR1 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CR2           TIM_DCR_DBA_0                                                    /*!< TIMx_CR2 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_SMCR          TIM_DCR_DBA_1                                                    /*!< TIMx_SMCR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_DIER          (TIM_DCR_DBA_1 |  TIM_DCR_DBA_0)                                 /*!< TIMx_DIER register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_SR            TIM_DCR_DBA_2                                                    /*!< TIMx_SR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_EGR           (TIM_DCR_DBA_2 | TIM_DCR_DBA_0)                                  /*!< TIMx_EGR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCMR1         (TIM_DCR_DBA_2 | TIM_DCR_DBA_1)                                  /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCMR2         (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)                  /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCER          TIM_DCR_DBA_3                                                    /*!< TIMx_CCER register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CNT           (TIM_DCR_DBA_3 | TIM_DCR_DBA_0)                                  /*!< TIMx_CNT register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_PSC           (TIM_DCR_DBA_3 | TIM_DCR_DBA_1)                                  /*!< TIMx_PSC register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_ARR           (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)                  /*!< TIMx_ARR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_RCR           (TIM_DCR_DBA_3 | TIM_DCR_DBA_2)                                  /*!< TIMx_RCR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR1          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)                  /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR2          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)                  /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR3          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)  /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR4          TIM_DCR_DBA_4                                                    /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_BDTR          (TIM_DCR_DBA_4 | TIM_DCR_DBA_0)                                  /*!< TIMx_BDTR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCMR3         (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)                  /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR5          (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)                  /*!< TIMx_CCR5 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR6          (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)  /*!< TIMx_CCR6 register is the DMA base address for DMA burst */
+#if defined(TIM1_AF1_BKINE)&&defined(TIM1_AF2_BKINE)
+#define LL_TIM_DMABURST_BASEADDR_AF1           (TIM_DCR_DBA_4 | TIM_DCR_DBA_3)                                  /*!< TIMx_AF1 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_AF2           (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_0)                  /*!< TIMx_AF2 register is the DMA base address for DMA burst */
+#endif /* TIM1_AF1_BKINE && TIM1_AF2_BKINE */
+#define LL_TIM_DMABURST_BASEADDR_TISEL         (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_1)                  /*!< TIMx_TISEL register is the DMA base address for DMA burst */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
+  * @{
+  */
+#define LL_TIM_DMABURST_LENGTH_1TRANSFER       0x00000000U                                                     /*!< Transfer is done to 1 register starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_2TRANSFERS      TIM_DCR_DBL_0                                                   /*!< Transfer is done to 2 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_3TRANSFERS      TIM_DCR_DBL_1                                                   /*!< Transfer is done to 3 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_4TRANSFERS      (TIM_DCR_DBL_1 |  TIM_DCR_DBL_0)                                /*!< Transfer is done to 4 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_5TRANSFERS      TIM_DCR_DBL_2                                                   /*!< Transfer is done to 5 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_6TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_0)                                 /*!< Transfer is done to 6 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_7TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_1)                                 /*!< Transfer is done to 7 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_8TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 1 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_9TRANSFERS      TIM_DCR_DBL_3                                                   /*!< Transfer is done to 9 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_10TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_0)                                 /*!< Transfer is done to 10 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_11TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_1)                                 /*!< Transfer is done to 11 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_12TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 12 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_13TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2)                                 /*!< Transfer is done to 13 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_14TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 14 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_15TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1)                 /*!< Transfer is done to 15 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_16TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_17TRANSFERS     TIM_DCR_DBL_4                                                   /*!< Transfer is done to 17 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_18TRANSFERS     (TIM_DCR_DBL_4 |  TIM_DCR_DBL_0)                                /*!< Transfer is done to 18 registers starting from the DMA burst base address */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM1_TI1_RMP  TIM1 Timer Input Ch1 Remap
+  * @{
+  */
+#define LL_TIM_TIM1_TI1_RMP_GPIO                          0x00000000U                               /* !< TIM1 input 1 is connected to GPIO */
+#define LL_TIM_TIM1_TI1_RMP_COMP1                         TIM_TISEL_TI1SEL_0                        /* !< TIM1 input 1 is connected to COMP1 OUT */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM8_TI1_RMP  TIM8 Timer Input Ch1 Remap
+  * @{
+  */
+#define LL_TIM_TIM8_TI1_RMP_GPIO                          0x00000000U                               /* !< TIM8 input 1 is connected to GPIO */
+#define LL_TIM_TIM8_TI1_RMP_COMP2                         TIM_TISEL_TI1SEL_0                        /* !< TIM8 input 1 is connected to COMP2 OUT */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM2_TI4_RMP  TIM2 Timer Input Ch4 Remap
+  * @{
+  */
+#define LL_TIM_TIM2_TI4_RMP_GPIO                          0x00000000U                               /* !< TIM2 input 4 is connected to GPIO */
+#define LL_TIM_TIM2_TI4_RMP_COMP1                         TIM_TISEL_TI4SEL_0                        /* !< TIM2 input 4 is connected to COMP1 OUT */
+#define LL_TIM_TIM2_TI4_RMP_COMP2                         TIM_TISEL_TI4SEL_1                        /* !< TIM2 input 4 is connected to COMP2 OUT */
+#define LL_TIM_TIM2_TI4_RMP_COMP1_COMP2                   (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM2 input 4 is connected to COMP2 OUT OR COMP2 OUT */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM3_TI1_RMP  TIM3 Timer Input Ch1 Remap
+  * @{
+  */
+#define LL_TIM_TIM3_TI1_RMP_GPIO                          0x00000000U                               /* !< TIM3 input 1 is connected to GPIO */
+#define LL_TIM_TIM3_TI1_RMP_COMP1                         TIM_TISEL_TI1SEL_0                        /* !< TIM3 input 1 is connected to COMP1 OUT */
+#define LL_TIM_TIM3_TI1_RMP_COMP2                         TIM_TISEL_TI1SEL_1                        /* !< TIM3 input 1 is connected to COMP2 OUT */
+#define LL_TIM_TIM3_TI1_RMP_COMP1_COMP2                   (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM3 input 1 is connected to COMP1 OUT or COMP2 OUT */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM5_TI1_RMP  TIM5 Timer Input Ch1 Remap
+  * @{
+  */
+#define LL_TIM_TIM5_TI1_RMP_GPIO                          0x00000000U                               /* !< TIM5 input 1 is connected to GPIO */
+#define LL_TIM_TIM5_TI1_RMP_CAN_TMP                       TIM_TISEL_TI1SEL_0                        /* !< TIM5 input 1 is connected to CAN TMP */
+#define LL_TIM_TIM5_TI1_RMP_CAN_RTP                       TIM_TISEL_TI1SEL_1                        /* !< TIM5 input 1 is connected to CAN RTP */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM12_TI1_RMP  TIM12 Timer Input Ch1 Remap
+  * @{
+  */
+#define LL_TIM_TIM12_TI1_RMP_GPIO                         0x00000000U                               /* !< TIM12 input 1 is connected to GPIO */
+#define LL_TIM_TIM12_TI1_RMP_SPDIF_FS                     TIM_TISEL_TI1SEL_0                        /* !< TIM12 input 1 is connected to SPDIF FS */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM15_TI1_RMP  TIM15 Timer Input Ch1 Remap
+  * @{
+  */
+#define LL_TIM_TIM15_TI1_RMP_GPIO                         0x00000000U                               /* !< TIM15 input 1 is connected to GPIO */
+#define LL_TIM_TIM15_TI1_RMP_TIM2_CH1                     TIM_TISEL_TI1SEL_0                        /* !< TIM15 input 1 is connected to TIM2 CH1 */
+#define LL_TIM_TIM15_TI1_RMP_TIM3_CH1                     TIM_TISEL_TI1SEL_1                        /* !< TIM15 input 1 is connected to TIM3 CH1 */
+#define LL_TIM_TIM15_TI1_RMP_TIM4_CH1                     (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM15 input 1 is connected to TIM4 CH1 */
+#define LL_TIM_TIM15_TI1_RMP_RCC_LSE                      (TIM_TISEL_TI1SEL_2)                      /* !< TIM15 input 1 is connected to RCC LSE  */
+#define LL_TIM_TIM15_TI1_RMP_RCC_CSI                      (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /* !< TIM15 input 1 is connected to RCC CSI  */
+#define LL_TIM_TIM15_TI1_RMP_RCC_MCO2                     (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /* !< TIM15 input 1 is connected to RCC MCO2 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM15_TI2_RMP  TIM15 Timer Input Ch2 Remap
+  * @{
+  */
+#define LL_TIM_TIM15_TI2_RMP_GPIO                         0x00000000U                               /* !< TIM15 input 2 is connected to GPIO */
+#define LL_TIM_TIM15_TI2_RMP_TIM2_CH2                     (TIM_TISEL_TI2SEL_0)                      /* !< TIM15 input 2 is connected to TIM2 CH2 */
+#define LL_TIM_TIM15_TI2_RMP_TIM3_CH2                     (TIM_TISEL_TI2SEL_1)                      /* !< TIM15 input 2 is connected to TIM3 CH2 */
+#define LL_TIM_TIM15_TI2_RMP_TIM4_CH2                     (TIM_TISEL_TI2SEL_0 | TIM_TISEL_TI2SEL_1) /* !< TIM15 input 2 is connected to TIM4 CH2 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM16_TI1_RMP  TIM16 Timer Input Ch1 Remap
+  * @{
+  */
+#define LL_TIM_TIM16_TI1_RMP_GPIO                         0x00000000U                               /* !< TIM16 input 1 is connected to GPIO */
+#define LL_TIM_TIM16_TI1_RMP_RCC_LSI                      TIM_TISEL_TI1SEL_0                        /* !< TIM16 input 1 is connected to RCC LSI */
+#define LL_TIM_TIM16_TI1_RMP_RCC_LSE                      TIM_TISEL_TI1SEL_1                        /* !< TIM16 input 1 is connected to RCC LSE */
+#define LL_TIM_TIM16_TI1_RMP_WKUP_IT                      (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM16 input 1 is connected to WKUP_IT */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM17_TI1_RMP  TIM17 Timer Input Ch1 Remap
+  * @{
+  */
+#define LL_TIM_TIM17_TI1_RMP_GPIO                         0x00000000U                               /* !< TIM17 input 1 is connected to GPIO */
+#define LL_TIM_TIM17_TI1_RMP_SPDIF_FS                     TIM_TISEL_TI1SEL_0                        /* !< TIM17 input 1 is connected to SPDIF FS */
+#define LL_TIM_TIM17_TI1_RMP_RCC_HSE1MHZ                  TIM_TISEL_TI1SEL_1                        /* !< TIM17 input 1 is connected to RCC HSE 1Mhz */
+#define LL_TIM_TIM17_TI1_RMP_RCC_MCO1                     (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM17 input 1 is connected to RCC MCO1 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM23_TI4_RMP  TIM23 Timer Input Ch4 Remap
+  * @{
+  */
+#define LL_TIM_TIM23_TI4_RMP_GPIO                         0x00000000U                               /* !< TIM23 input 4 is connected to GPIO */
+#define LL_TIM_TIM23_TI4_RMP_COMP1                        TIM_TISEL_TI4SEL_0                        /* !< TIM23 input 4 is connected to COMP1 OUT */
+#define LL_TIM_TIM23_TI4_RMP_COMP2                        TIM_TISEL_TI4SEL_1                        /* !< TIM23 input 4 is connected to COMP2 OUT */
+#define LL_TIM_TIM23_TI4_RMP_COMP1_COMP2                  (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM23 input 4 is connected to COMP1 OUT or COMP2 OUT */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM24_TI1_RMP  TIM24 Timer Input Ch1 Remap
+  * @{
+  */
+#define LL_TIM_TIM24_TI1_RMP_GPIO                         0x00000000U                               /* !< TIM24 input 1 is connected to GPIO */
+#define LL_TIM_TIM24_TI1_RMP_CAN_TMP                      TIM_TISEL_TI1SEL_0                        /* !< TIM24 input 1 is connected to CAN TMP  */
+#define LL_TIM_TIM24_TI1_RMP_CAN_RTP                      TIM_TISEL_TI1SEL_1                        /* !< TIM24 input 1 is connected to CAN RTP  */
+#define LL_TIM_TIM24_TI1_RMP_CAN_SOC                      (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM24 input 1 is connected to CAN SOC */
+
+#if defined(TIM_BREAK_INPUT_SUPPORT)
+/** Legacy definitions for compatibility purpose
+@cond 0
+  */
+#define LL_TIM_BKIN_SOURCE_DFBK  LL_TIM_BKIN_SOURCE_DF1BK
+/**
+@endcond
+  */
+#endif /* TIM_BREAK_INPUT_SUPPORT */
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
+  * @{
+  */
+
+/** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+/**
+  * @brief  Write a value in TIM register.
+  * @param  __INSTANCE__ TIM Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in TIM register.
+  * @param  __INSTANCE__ TIM Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
+  * @{
+  */
+
+/**
+  * @brief  HELPER macro retrieving the UIFCPY flag from the counter value.
+  * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
+  * @note  Relevant only if UIF flag remapping has been enabled  (UIF status bit is copied
+  *        to TIMx_CNT register bit 31)
+  * @param  __CNT__ Counter value
+  * @retval UIF status bit
+  */
+#define __LL_TIM_GETFLAG_UIFCPY(__CNT__)  \
+  (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
+
+/**
+  * @brief  HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
+  * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __CKD__ This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+  * @param  __DT__ deadtime duration (in ns)
+  * @retval DTG[0:7]
+  */
+#define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__)  \
+  ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))    ?  \
+    (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__)))  & DT_DELAY_1) :      \
+    (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))  ?  \
+    (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__),   \
+                                                 (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
+    (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))  ?  \
+    (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__),  \
+                                                 (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
+    (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ?  \
+    (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__),  \
+                                                 (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
+    0U)
+
+/**
+  * @brief  HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
+  * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __CNTCLK__ counter clock frequency (in Hz)
+  * @retval Prescaler value  (between Min_Data=0 and Max_Data=65535)
+  */
+#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__)   \
+  (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U)
+
+/**
+  * @brief  HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
+  * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __PSC__ prescaler
+  * @param  __FREQ__ output signal frequency (in Hz)
+  * @retval  Auto-reload value  (between Min_Data=0 and Max_Data=65535)
+  */
+#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
+  ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
+
+/**
+  * @brief  HELPER macro calculating the compare value required to achieve the required timer output compare
+  *         active/inactive delay.
+  * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __PSC__ prescaler
+  * @param  __DELAY__ timer output compare active/inactive delay (in us)
+  * @retval Compare value  (between Min_Data=0 and Max_Data=65535)
+  */
+#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__)  \
+  ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
+              / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
+
+/**
+  * @brief  HELPER macro calculating the auto-reload value to achieve the required pulse duration
+  *         (when the timer operates in one pulse mode).
+  * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __PSC__ prescaler
+  * @param  __DELAY__ timer output compare active/inactive delay (in us)
+  * @param  __PULSE__ pulse duration (in us)
+  * @retval Auto-reload value  (between Min_Data=0 and Max_Data=65535)
+  */
+#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__)  \
+  ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
+              + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
+
+/**
+  * @brief  HELPER macro retrieving the ratio of the input capture prescaler
+  * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
+  * @param  __ICPSC__ This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ICPSC_DIV1
+  *         @arg @ref LL_TIM_ICPSC_DIV2
+  *         @arg @ref LL_TIM_ICPSC_DIV4
+  *         @arg @ref LL_TIM_ICPSC_DIV8
+  * @retval Input capture prescaler ratio (1, 2, 4 or 8)
+  */
+#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__)  \
+  ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
+
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
+  * @{
+  */
+
+/** @defgroup TIM_LL_EF_Time_Base Time Base configuration
+  * @{
+  */
+/**
+  * @brief  Enable timer counter.
+  * @rmtoll CR1          CEN           LL_TIM_EnableCounter
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->CR1, TIM_CR1_CEN);
+}
+
+/**
+  * @brief  Disable timer counter.
+  * @rmtoll CR1          CEN           LL_TIM_DisableCounter
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
+}
+
+/**
+  * @brief  Indicates whether the timer counter is enabled.
+  * @rmtoll CR1          CEN           LL_TIM_IsEnabledCounter
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable update event generation.
+  * @rmtoll CR1          UDIS          LL_TIM_EnableUpdateEvent
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
+}
+
+/**
+  * @brief  Disable update event generation.
+  * @rmtoll CR1          UDIS          LL_TIM_DisableUpdateEvent
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
+}
+
+/**
+  * @brief  Indicates whether update event generation is enabled.
+  * @rmtoll CR1          UDIS          LL_TIM_IsEnabledUpdateEvent
+  * @param  TIMx Timer instance
+  * @retval Inverted state of bit (0 or 1).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set update event source
+  * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
+  *       generate an update interrupt or DMA request if enabled:
+  *        - Counter overflow/underflow
+  *        - Setting the UG bit
+  *        - Update generation through the slave mode controller
+  * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
+  *       overflow/underflow generates an update interrupt or DMA request if enabled.
+  * @rmtoll CR1          URS           LL_TIM_SetUpdateSource
+  * @param  TIMx Timer instance
+  * @param  UpdateSource This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_UPDATESOURCE_REGULAR
+  *         @arg @ref LL_TIM_UPDATESOURCE_COUNTER
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
+{
+  MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
+}
+
+/**
+  * @brief  Get actual event update source
+  * @rmtoll CR1          URS           LL_TIM_GetUpdateSource
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_UPDATESOURCE_REGULAR
+  *         @arg @ref LL_TIM_UPDATESOURCE_COUNTER
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
+}
+
+/**
+  * @brief  Set one pulse mode (one shot v.s. repetitive).
+  * @rmtoll CR1          OPM           LL_TIM_SetOnePulseMode
+  * @param  TIMx Timer instance
+  * @param  OnePulseMode This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
+  *         @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
+{
+  MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
+}
+
+/**
+  * @brief  Get actual one pulse mode.
+  * @rmtoll CR1          OPM           LL_TIM_GetOnePulseMode
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
+  *         @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
+}
+
+/**
+  * @brief  Set the timer counter counting mode.
+  * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
+  *       check whether or not the counter mode selection feature is supported
+  *       by a timer instance.
+  * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+  *       requires a timer reset to avoid unexpected direction
+  *       due to DIR bit readonly in center aligned mode.
+  * @rmtoll CR1          DIR           LL_TIM_SetCounterMode\n
+  *         CR1          CMS           LL_TIM_SetCounterMode
+  * @param  TIMx Timer instance
+  * @param  CounterMode This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_COUNTERMODE_UP
+  *         @arg @ref LL_TIM_COUNTERMODE_DOWN
+  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
+  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
+  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
+{
+  MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
+}
+
+/**
+  * @brief  Get actual counter mode.
+  * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
+  *       check whether or not the counter mode selection feature is supported
+  *       by a timer instance.
+  * @rmtoll CR1          DIR           LL_TIM_GetCounterMode\n
+  *         CR1          CMS           LL_TIM_GetCounterMode
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_COUNTERMODE_UP
+  *         @arg @ref LL_TIM_COUNTERMODE_DOWN
+  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
+  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
+  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
+{
+  uint32_t counter_mode;
+
+  counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS));
+
+  if (counter_mode == 0U)
+  {
+    counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
+  }
+
+  return counter_mode;
+}
+
+/**
+  * @brief  Enable auto-reload (ARR) preload.
+  * @rmtoll CR1          ARPE          LL_TIM_EnableARRPreload
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
+}
+
+/**
+  * @brief  Disable auto-reload (ARR) preload.
+  * @rmtoll CR1          ARPE          LL_TIM_DisableARRPreload
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
+}
+
+/**
+  * @brief  Indicates whether auto-reload (ARR) preload is enabled.
+  * @rmtoll CR1          ARPE          LL_TIM_IsEnabledARRPreload
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the division ratio between the timer clock  and the sampling clock used by the dead-time generators
+  *         (when supported) and the digital filters.
+  * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
+  *       whether or not the clock division feature is supported by the timer
+  *       instance.
+  * @rmtoll CR1          CKD           LL_TIM_SetClockDivision
+  * @param  TIMx Timer instance
+  * @param  ClockDivision This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
+{
+  MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
+}
+
+/**
+  * @brief  Get the actual division ratio between the timer clock  and the sampling clock used by the dead-time
+  *         generators (when supported) and the digital filters.
+  * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
+  *       whether or not the clock division feature is supported by the timer
+  *       instance.
+  * @rmtoll CR1          CKD           LL_TIM_GetClockDivision
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
+}
+
+/**
+  * @brief  Set the counter value.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @rmtoll CNT          CNT           LL_TIM_SetCounter
+  * @param  TIMx Timer instance
+  * @param  Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
+{
+  WRITE_REG(TIMx->CNT, Counter);
+}
+
+/**
+  * @brief  Get the counter value.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @rmtoll CNT          CNT           LL_TIM_GetCounter
+  * @param  TIMx Timer instance
+  * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CNT));
+}
+
+/**
+  * @brief  Get the current direction of the counter
+  * @rmtoll CR1          DIR           LL_TIM_GetDirection
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_COUNTERDIRECTION_UP
+  *         @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
+}
+
+/**
+  * @brief  Set the prescaler value.
+  * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
+  * @note The prescaler can be changed on the fly as this control register is buffered. The new
+  *       prescaler ratio is taken into account at the next update event.
+  * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
+  * @rmtoll PSC          PSC           LL_TIM_SetPrescaler
+  * @param  TIMx Timer instance
+  * @param  Prescaler between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
+{
+  WRITE_REG(TIMx->PSC, Prescaler);
+}
+
+/**
+  * @brief  Get the prescaler value.
+  * @rmtoll PSC          PSC           LL_TIM_GetPrescaler
+  * @param  TIMx Timer instance
+  * @retval  Prescaler value between Min_Data=0 and Max_Data=65535
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->PSC));
+}
+
+/**
+  * @brief  Set the auto-reload value.
+  * @note The counter is blocked while the auto-reload value is null.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
+  * @rmtoll ARR          ARR           LL_TIM_SetAutoReload
+  * @param  TIMx Timer instance
+  * @param  AutoReload between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
+{
+  WRITE_REG(TIMx->ARR, AutoReload);
+}
+
+/**
+  * @brief  Get the auto-reload value.
+  * @rmtoll ARR          ARR           LL_TIM_GetAutoReload
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @param  TIMx Timer instance
+  * @retval Auto-reload value
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->ARR));
+}
+
+/**
+  * @brief  Set the repetition counter value.
+  * @note For advanced timer instances RepetitionCounter can be up to 65535.
+  * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a repetition counter.
+  * @rmtoll RCR          REP           LL_TIM_SetRepetitionCounter
+  * @param  TIMx Timer instance
+  * @param  RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer.
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
+{
+  WRITE_REG(TIMx->RCR, RepetitionCounter);
+}
+
+/**
+  * @brief  Get the repetition counter value.
+  * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a repetition counter.
+  * @rmtoll RCR          REP           LL_TIM_GetRepetitionCounter
+  * @param  TIMx Timer instance
+  * @retval Repetition counter value
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->RCR));
+}
+
+/**
+  * @brief  Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
+  * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read
+  *       in an atomic way.
+  * @rmtoll CR1          UIFREMAP      LL_TIM_EnableUIFRemap
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
+}
+
+/**
+  * @brief  Disable update interrupt flag (UIF) remapping.
+  * @rmtoll CR1          UIFREMAP      LL_TIM_DisableUIFRemap
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
+}
+
+/**
+  * @brief  Indicate whether update interrupt flag (UIF) copy is set.
+  * @param  Counter Counter value
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(uint32_t Counter)
+{
+  return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
+  * @{
+  */
+/**
+  * @brief  Enable  the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
+  * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
+  *       they are updated only when a commutation event (COM) occurs.
+  * @note Only on channels that have a complementary output.
+  * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance is able to generate a commutation event.
+  * @rmtoll CR2          CCPC          LL_TIM_CC_EnablePreload
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
+}
+
+/**
+  * @brief  Disable  the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
+  * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance is able to generate a commutation event.
+  * @rmtoll CR2          CCPC          LL_TIM_CC_DisablePreload
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
+}
+
+/**
+  * @brief  Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
+  * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance is able to generate a commutation event.
+  * @rmtoll CR2          CCUS          LL_TIM_CC_SetUpdate
+  * @param  TIMx Timer instance
+  * @param  CCUpdateSource This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
+  *         @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
+{
+  MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
+}
+
+/**
+  * @brief  Set the trigger of the capture/compare DMA request.
+  * @rmtoll CR2          CCDS          LL_TIM_CC_SetDMAReqTrigger
+  * @param  TIMx Timer instance
+  * @param  DMAReqTrigger This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CCDMAREQUEST_CC
+  *         @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
+{
+  MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
+}
+
+/**
+  * @brief  Get actual trigger of the capture/compare DMA request.
+  * @rmtoll CR2          CCDS          LL_TIM_CC_GetDMAReqTrigger
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_CCDMAREQUEST_CC
+  *         @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
+  */
+__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
+}
+
+/**
+  * @brief  Set the lock level to freeze the
+  *         configuration of several capture/compare parameters.
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       the lock mechanism is supported by a timer instance.
+  * @rmtoll BDTR         LOCK          LL_TIM_CC_SetLockLevel
+  * @param  TIMx Timer instance
+  * @param  LockLevel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_LOCKLEVEL_OFF
+  *         @arg @ref LL_TIM_LOCKLEVEL_1
+  *         @arg @ref LL_TIM_LOCKLEVEL_2
+  *         @arg @ref LL_TIM_LOCKLEVEL_3
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
+{
+  MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
+}
+
+/**
+  * @brief  Enable capture/compare channels.
+  * @rmtoll CCER         CC1E          LL_TIM_CC_EnableChannel\n
+  *         CCER         CC1NE         LL_TIM_CC_EnableChannel\n
+  *         CCER         CC2E          LL_TIM_CC_EnableChannel\n
+  *         CCER         CC2NE         LL_TIM_CC_EnableChannel\n
+  *         CCER         CC3E          LL_TIM_CC_EnableChannel\n
+  *         CCER         CC3NE         LL_TIM_CC_EnableChannel\n
+  *         CCER         CC4E          LL_TIM_CC_EnableChannel\n
+  *         CCER         CC5E          LL_TIM_CC_EnableChannel\n
+  *         CCER         CC6E          LL_TIM_CC_EnableChannel
+  * @param  TIMx Timer instance
+  * @param  Channels This parameter can be a combination of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH1N
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH2N
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH3N
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
+{
+  SET_BIT(TIMx->CCER, Channels);
+}
+
+/**
+  * @brief  Disable capture/compare channels.
+  * @rmtoll CCER         CC1E          LL_TIM_CC_DisableChannel\n
+  *         CCER         CC1NE         LL_TIM_CC_DisableChannel\n
+  *         CCER         CC2E          LL_TIM_CC_DisableChannel\n
+  *         CCER         CC2NE         LL_TIM_CC_DisableChannel\n
+  *         CCER         CC3E          LL_TIM_CC_DisableChannel\n
+  *         CCER         CC3NE         LL_TIM_CC_DisableChannel\n
+  *         CCER         CC4E          LL_TIM_CC_DisableChannel\n
+  *         CCER         CC5E          LL_TIM_CC_DisableChannel\n
+  *         CCER         CC6E          LL_TIM_CC_DisableChannel
+  * @param  TIMx Timer instance
+  * @param  Channels This parameter can be a combination of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH1N
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH2N
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH3N
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
+{
+  CLEAR_BIT(TIMx->CCER, Channels);
+}
+
+/**
+  * @brief  Indicate whether channel(s) is(are) enabled.
+  * @rmtoll CCER         CC1E          LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC1NE         LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC2E          LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC2NE         LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC3E          LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC3NE         LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC4E          LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC5E          LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC6E          LL_TIM_CC_IsEnabledChannel
+  * @param  TIMx Timer instance
+  * @param  Channels This parameter can be a combination of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH1N
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH2N
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH3N
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
+{
+  return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
+  * @{
+  */
+/**
+  * @brief  Configure an output channel.
+  * @rmtoll CCMR1        CC1S          LL_TIM_OC_ConfigOutput\n
+  *         CCMR1        CC2S          LL_TIM_OC_ConfigOutput\n
+  *         CCMR2        CC3S          LL_TIM_OC_ConfigOutput\n
+  *         CCMR2        CC4S          LL_TIM_OC_ConfigOutput\n
+  *         CCMR3        CC5S          LL_TIM_OC_ConfigOutput\n
+  *         CCMR3        CC6S          LL_TIM_OC_ConfigOutput\n
+  *         CCER         CC1P          LL_TIM_OC_ConfigOutput\n
+  *         CCER         CC2P          LL_TIM_OC_ConfigOutput\n
+  *         CCER         CC3P          LL_TIM_OC_ConfigOutput\n
+  *         CCER         CC4P          LL_TIM_OC_ConfigOutput\n
+  *         CCER         CC5P          LL_TIM_OC_ConfigOutput\n
+  *         CCER         CC6P          LL_TIM_OC_ConfigOutput\n
+  *         CR2          OIS1          LL_TIM_OC_ConfigOutput\n
+  *         CR2          OIS2          LL_TIM_OC_ConfigOutput\n
+  *         CR2          OIS3          LL_TIM_OC_ConfigOutput\n
+  *         CR2          OIS4          LL_TIM_OC_ConfigOutput\n
+  *         CR2          OIS5          LL_TIM_OC_ConfigOutput\n
+  *         CR2          OIS6          LL_TIM_OC_ConfigOutput
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @param  Configuration This parameter must be a combination of all the following values:
+  *         @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
+  *         @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
+  MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
+             (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
+  MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
+             (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
+}
+
+/**
+  * @brief  Define the behavior of the output reference signal OCxREF from which
+  *         OCx and OCxN (when relevant) are derived.
+  * @rmtoll CCMR1        OC1M          LL_TIM_OC_SetMode\n
+  *         CCMR1        OC2M          LL_TIM_OC_SetMode\n
+  *         CCMR2        OC3M          LL_TIM_OC_SetMode\n
+  *         CCMR2        OC4M          LL_TIM_OC_SetMode\n
+  *         CCMR3        OC5M          LL_TIM_OC_SetMode\n
+  *         CCMR3        OC6M          LL_TIM_OC_SetMode
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @param  Mode This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_OCMODE_FROZEN
+  *         @arg @ref LL_TIM_OCMODE_ACTIVE
+  *         @arg @ref LL_TIM_OCMODE_INACTIVE
+  *         @arg @ref LL_TIM_OCMODE_TOGGLE
+  *         @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
+  *         @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
+  *         @arg @ref LL_TIM_OCMODE_PWM1
+  *         @arg @ref LL_TIM_OCMODE_PWM2
+  *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
+  *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
+  *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
+  *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
+  *         @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
+  *         @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M  | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
+}
+
+/**
+  * @brief  Get the output compare mode of an output channel.
+  * @rmtoll CCMR1        OC1M          LL_TIM_OC_GetMode\n
+  *         CCMR1        OC2M          LL_TIM_OC_GetMode\n
+  *         CCMR2        OC3M          LL_TIM_OC_GetMode\n
+  *         CCMR2        OC4M          LL_TIM_OC_GetMode\n
+  *         CCMR3        OC5M          LL_TIM_OC_GetMode\n
+  *         CCMR3        OC6M          LL_TIM_OC_GetMode
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_OCMODE_FROZEN
+  *         @arg @ref LL_TIM_OCMODE_ACTIVE
+  *         @arg @ref LL_TIM_OCMODE_INACTIVE
+  *         @arg @ref LL_TIM_OCMODE_TOGGLE
+  *         @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
+  *         @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
+  *         @arg @ref LL_TIM_OCMODE_PWM1
+  *         @arg @ref LL_TIM_OCMODE_PWM2
+  *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
+  *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
+  *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
+  *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
+  *         @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
+  *         @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
+}
+
+/**
+  * @brief  Set the polarity of an output channel.
+  * @rmtoll CCER         CC1P          LL_TIM_OC_SetPolarity\n
+  *         CCER         CC1NP         LL_TIM_OC_SetPolarity\n
+  *         CCER         CC2P          LL_TIM_OC_SetPolarity\n
+  *         CCER         CC2NP         LL_TIM_OC_SetPolarity\n
+  *         CCER         CC3P          LL_TIM_OC_SetPolarity\n
+  *         CCER         CC3NP         LL_TIM_OC_SetPolarity\n
+  *         CCER         CC4P          LL_TIM_OC_SetPolarity\n
+  *         CCER         CC5P          LL_TIM_OC_SetPolarity\n
+  *         CCER         CC6P          LL_TIM_OC_SetPolarity
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH1N
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH2N
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH3N
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_OCPOLARITY_HIGH
+  *         @arg @ref LL_TIM_OCPOLARITY_LOW
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),  Polarity << SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+  * @brief  Get the polarity of an output channel.
+  * @rmtoll CCER         CC1P          LL_TIM_OC_GetPolarity\n
+  *         CCER         CC1NP         LL_TIM_OC_GetPolarity\n
+  *         CCER         CC2P          LL_TIM_OC_GetPolarity\n
+  *         CCER         CC2NP         LL_TIM_OC_GetPolarity\n
+  *         CCER         CC3P          LL_TIM_OC_GetPolarity\n
+  *         CCER         CC3NP         LL_TIM_OC_GetPolarity\n
+  *         CCER         CC4P          LL_TIM_OC_GetPolarity\n
+  *         CCER         CC5P          LL_TIM_OC_GetPolarity\n
+  *         CCER         CC6P          LL_TIM_OC_GetPolarity
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH1N
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH2N
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH3N
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_OCPOLARITY_HIGH
+  *         @arg @ref LL_TIM_OCPOLARITY_LOW
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+  * @brief  Set the IDLE state of an output channel
+  * @note This function is significant only for the timer instances
+  *       supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
+  *       can be used to check whether or not a timer instance provides
+  *       a break input.
+  * @rmtoll CR2         OIS1          LL_TIM_OC_SetIdleState\n
+  *         CR2         OIS2N         LL_TIM_OC_SetIdleState\n
+  *         CR2         OIS2          LL_TIM_OC_SetIdleState\n
+  *         CR2         OIS2N         LL_TIM_OC_SetIdleState\n
+  *         CR2         OIS3          LL_TIM_OC_SetIdleState\n
+  *         CR2         OIS3N         LL_TIM_OC_SetIdleState\n
+  *         CR2         OIS4          LL_TIM_OC_SetIdleState\n
+  *         CR2         OIS5          LL_TIM_OC_SetIdleState\n
+  *         CR2         OIS6          LL_TIM_OC_SetIdleState
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH1N
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH2N
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH3N
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @param  IdleState This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_OCIDLESTATE_LOW
+  *         @arg @ref LL_TIM_OCIDLESTATE_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),  IdleState << SHIFT_TAB_OISx[iChannel]);
+}
+
+/**
+  * @brief  Get the IDLE state of an output channel
+  * @rmtoll CR2         OIS1          LL_TIM_OC_GetIdleState\n
+  *         CR2         OIS2N         LL_TIM_OC_GetIdleState\n
+  *         CR2         OIS2          LL_TIM_OC_GetIdleState\n
+  *         CR2         OIS2N         LL_TIM_OC_GetIdleState\n
+  *         CR2         OIS3          LL_TIM_OC_GetIdleState\n
+  *         CR2         OIS3N         LL_TIM_OC_GetIdleState\n
+  *         CR2         OIS4          LL_TIM_OC_GetIdleState\n
+  *         CR2         OIS5          LL_TIM_OC_GetIdleState\n
+  *         CR2         OIS6          LL_TIM_OC_GetIdleState
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH1N
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH2N
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH3N
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_OCIDLESTATE_LOW
+  *         @arg @ref LL_TIM_OCIDLESTATE_HIGH
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
+}
+
+/**
+  * @brief  Enable fast mode for the output channel.
+  * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
+  * @rmtoll CCMR1        OC1FE          LL_TIM_OC_EnableFast\n
+  *         CCMR1        OC2FE          LL_TIM_OC_EnableFast\n
+  *         CCMR2        OC3FE          LL_TIM_OC_EnableFast\n
+  *         CCMR2        OC4FE          LL_TIM_OC_EnableFast\n
+  *         CCMR3        OC5FE          LL_TIM_OC_EnableFast\n
+  *         CCMR3        OC6FE          LL_TIM_OC_EnableFast
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
+
+}
+
+/**
+  * @brief  Disable fast mode for the output channel.
+  * @rmtoll CCMR1        OC1FE          LL_TIM_OC_DisableFast\n
+  *         CCMR1        OC2FE          LL_TIM_OC_DisableFast\n
+  *         CCMR2        OC3FE          LL_TIM_OC_DisableFast\n
+  *         CCMR2        OC4FE          LL_TIM_OC_DisableFast\n
+  *         CCMR3        OC5FE          LL_TIM_OC_DisableFast\n
+  *         CCMR3        OC6FE          LL_TIM_OC_DisableFast
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
+
+}
+
+/**
+  * @brief  Indicates whether fast mode is enabled for the output channel.
+  * @rmtoll CCMR1        OC1FE          LL_TIM_OC_IsEnabledFast\n
+  *         CCMR1        OC2FE          LL_TIM_OC_IsEnabledFast\n
+  *         CCMR2        OC3FE          LL_TIM_OC_IsEnabledFast\n
+  *         CCMR2        OC4FE          LL_TIM_OC_IsEnabledFast\n
+  *         CCMR3        OC5FE          LL_TIM_OC_IsEnabledFast\n
+  *         CCMR3        OC6FE          LL_TIM_OC_IsEnabledFast
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
+  return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable compare register (TIMx_CCRx) preload for the output channel.
+  * @rmtoll CCMR1        OC1PE          LL_TIM_OC_EnablePreload\n
+  *         CCMR1        OC2PE          LL_TIM_OC_EnablePreload\n
+  *         CCMR2        OC3PE          LL_TIM_OC_EnablePreload\n
+  *         CCMR2        OC4PE          LL_TIM_OC_EnablePreload\n
+  *         CCMR3        OC5PE          LL_TIM_OC_EnablePreload\n
+  *         CCMR3        OC6PE          LL_TIM_OC_EnablePreload
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
+}
+
+/**
+  * @brief  Disable compare register (TIMx_CCRx) preload for the output channel.
+  * @rmtoll CCMR1        OC1PE          LL_TIM_OC_DisablePreload\n
+  *         CCMR1        OC2PE          LL_TIM_OC_DisablePreload\n
+  *         CCMR2        OC3PE          LL_TIM_OC_DisablePreload\n
+  *         CCMR2        OC4PE          LL_TIM_OC_DisablePreload\n
+  *         CCMR3        OC5PE          LL_TIM_OC_DisablePreload\n
+  *         CCMR3        OC6PE          LL_TIM_OC_DisablePreload
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
+}
+
+/**
+  * @brief  Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
+  * @rmtoll CCMR1        OC1PE          LL_TIM_OC_IsEnabledPreload\n
+  *         CCMR1        OC2PE          LL_TIM_OC_IsEnabledPreload\n
+  *         CCMR2        OC3PE          LL_TIM_OC_IsEnabledPreload\n
+  *         CCMR2        OC4PE          LL_TIM_OC_IsEnabledPreload\n
+  *         CCMR3        OC5PE          LL_TIM_OC_IsEnabledPreload\n
+  *         CCMR3        OC6PE          LL_TIM_OC_IsEnabledPreload
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
+  return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable clearing the output channel on an external event.
+  * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
+  * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+  *       or not a timer instance can clear the OCxREF signal on an external event.
+  * @rmtoll CCMR1        OC1CE          LL_TIM_OC_EnableClear\n
+  *         CCMR1        OC2CE          LL_TIM_OC_EnableClear\n
+  *         CCMR2        OC3CE          LL_TIM_OC_EnableClear\n
+  *         CCMR2        OC4CE          LL_TIM_OC_EnableClear\n
+  *         CCMR3        OC5CE          LL_TIM_OC_EnableClear\n
+  *         CCMR3        OC6CE          LL_TIM_OC_EnableClear
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
+}
+
+/**
+  * @brief  Disable clearing the output channel on an external event.
+  * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+  *       or not a timer instance can clear the OCxREF signal on an external event.
+  * @rmtoll CCMR1        OC1CE          LL_TIM_OC_DisableClear\n
+  *         CCMR1        OC2CE          LL_TIM_OC_DisableClear\n
+  *         CCMR2        OC3CE          LL_TIM_OC_DisableClear\n
+  *         CCMR2        OC4CE          LL_TIM_OC_DisableClear\n
+  *         CCMR3        OC5CE          LL_TIM_OC_DisableClear\n
+  *         CCMR3        OC6CE          LL_TIM_OC_DisableClear
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
+}
+
+/**
+  * @brief  Indicates clearing the output channel on an external event is enabled for the output channel.
+  * @note This function enables clearing the output channel on an external event.
+  * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
+  * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+  *       or not a timer instance can clear the OCxREF signal on an external event.
+  * @rmtoll CCMR1        OC1CE          LL_TIM_OC_IsEnabledClear\n
+  *         CCMR1        OC2CE          LL_TIM_OC_IsEnabledClear\n
+  *         CCMR2        OC3CE          LL_TIM_OC_IsEnabledClear\n
+  *         CCMR2        OC4CE          LL_TIM_OC_IsEnabledClear\n
+  *         CCMR3        OC5CE          LL_TIM_OC_IsEnabledClear\n
+  *         CCMR3        OC6CE          LL_TIM_OC_IsEnabledClear
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
+  return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of
+  *         the Ocx and OCxN signals).
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       dead-time insertion feature is supported by a timer instance.
+  * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
+  * @rmtoll BDTR         DTG           LL_TIM_OC_SetDeadTime
+  * @param  TIMx Timer instance
+  * @param  DeadTime between Min_Data=0 and Max_Data=255
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
+{
+  MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
+}
+
+/**
+  * @brief  Set compare value for output channel 1 (TIMx_CCR1).
+  * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 1 is supported by a timer instance.
+  * @rmtoll CCR1         CCR1          LL_TIM_OC_SetCompareCH1
+  * @param  TIMx Timer instance
+  * @param  CompareValue between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+  WRITE_REG(TIMx->CCR1, CompareValue);
+}
+
+/**
+  * @brief  Set compare value for output channel 2 (TIMx_CCR2).
+  * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 2 is supported by a timer instance.
+  * @rmtoll CCR2         CCR2          LL_TIM_OC_SetCompareCH2
+  * @param  TIMx Timer instance
+  * @param  CompareValue between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+  WRITE_REG(TIMx->CCR2, CompareValue);
+}
+
+/**
+  * @brief  Set compare value for output channel 3 (TIMx_CCR3).
+  * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel is supported by a timer instance.
+  * @rmtoll CCR3         CCR3          LL_TIM_OC_SetCompareCH3
+  * @param  TIMx Timer instance
+  * @param  CompareValue between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+  WRITE_REG(TIMx->CCR3, CompareValue);
+}
+
+/**
+  * @brief  Set compare value for output channel 4 (TIMx_CCR4).
+  * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 4 is supported by a timer instance.
+  * @rmtoll CCR4         CCR4          LL_TIM_OC_SetCompareCH4
+  * @param  TIMx Timer instance
+  * @param  CompareValue between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+  WRITE_REG(TIMx->CCR4, CompareValue);
+}
+
+/**
+  * @brief  Set compare value for output channel 5 (TIMx_CCR5).
+  * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 5 is supported by a timer instance.
+  * @rmtoll CCR5         CCR5          LL_TIM_OC_SetCompareCH5
+  * @param  TIMx Timer instance
+  * @param  CompareValue between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+  MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue);
+}
+
+/**
+  * @brief  Set compare value for output channel 6 (TIMx_CCR6).
+  * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 6 is supported by a timer instance.
+  * @rmtoll CCR6         CCR6          LL_TIM_OC_SetCompareCH6
+  * @param  TIMx Timer instance
+  * @param  CompareValue between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+  WRITE_REG(TIMx->CCR6, CompareValue);
+}
+
+/**
+  * @brief  Get compare value (TIMx_CCR1) set for  output channel 1.
+  * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 1 is supported by a timer instance.
+  * @rmtoll CCR1         CCR1          LL_TIM_OC_GetCompareCH1
+  * @param  TIMx Timer instance
+  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR1));
+}
+
+/**
+  * @brief  Get compare value (TIMx_CCR2) set for  output channel 2.
+  * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 2 is supported by a timer instance.
+  * @rmtoll CCR2         CCR2          LL_TIM_OC_GetCompareCH2
+  * @param  TIMx Timer instance
+  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR2));
+}
+
+/**
+  * @brief  Get compare value (TIMx_CCR3) set for  output channel 3.
+  * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 3 is supported by a timer instance.
+  * @rmtoll CCR3         CCR3          LL_TIM_OC_GetCompareCH3
+  * @param  TIMx Timer instance
+  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR3));
+}
+
+/**
+  * @brief  Get compare value (TIMx_CCR4) set for  output channel 4.
+  * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 4 is supported by a timer instance.
+  * @rmtoll CCR4         CCR4          LL_TIM_OC_GetCompareCH4
+  * @param  TIMx Timer instance
+  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR4));
+}
+
+/**
+  * @brief  Get compare value (TIMx_CCR5) set for  output channel 5.
+  * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 5 is supported by a timer instance.
+  * @rmtoll CCR5         CCR5          LL_TIM_OC_GetCompareCH5
+  * @param  TIMx Timer instance
+  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5));
+}
+
+/**
+  * @brief  Get compare value (TIMx_CCR6) set for  output channel 6.
+  * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 6 is supported by a timer instance.
+  * @rmtoll CCR6         CCR6          LL_TIM_OC_GetCompareCH6
+  * @param  TIMx Timer instance
+  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR6));
+}
+
+/**
+  * @brief  Select on which reference signal the OC5REF is combined to.
+  * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports the combined 3-phase PWM mode.
+  * @rmtoll CCR5         GC5C3          LL_TIM_SetCH5CombinedChannels\n
+  *         CCR5         GC5C2          LL_TIM_SetCH5CombinedChannels\n
+  *         CCR5         GC5C1          LL_TIM_SetCH5CombinedChannels
+  * @param  TIMx Timer instance
+  * @param  GroupCH5 This parameter can be a combination of the following values:
+  *         @arg @ref LL_TIM_GROUPCH5_NONE
+  *         @arg @ref LL_TIM_GROUPCH5_OC1REFC
+  *         @arg @ref LL_TIM_GROUPCH5_OC2REFC
+  *         @arg @ref LL_TIM_GROUPCH5_OC3REFC
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5)
+{
+  MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
+  * @{
+  */
+/**
+  * @brief  Configure input channel.
+  * @rmtoll CCMR1        CC1S          LL_TIM_IC_Config\n
+  *         CCMR1        IC1PSC        LL_TIM_IC_Config\n
+  *         CCMR1        IC1F          LL_TIM_IC_Config\n
+  *         CCMR1        CC2S          LL_TIM_IC_Config\n
+  *         CCMR1        IC2PSC        LL_TIM_IC_Config\n
+  *         CCMR1        IC2F          LL_TIM_IC_Config\n
+  *         CCMR2        CC3S          LL_TIM_IC_Config\n
+  *         CCMR2        IC3PSC        LL_TIM_IC_Config\n
+  *         CCMR2        IC3F          LL_TIM_IC_Config\n
+  *         CCMR2        CC4S          LL_TIM_IC_Config\n
+  *         CCMR2        IC4PSC        LL_TIM_IC_Config\n
+  *         CCMR2        IC4F          LL_TIM_IC_Config\n
+  *         CCER         CC1P          LL_TIM_IC_Config\n
+  *         CCER         CC1NP         LL_TIM_IC_Config\n
+  *         CCER         CC2P          LL_TIM_IC_Config\n
+  *         CCER         CC2NP         LL_TIM_IC_Config\n
+  *         CCER         CC3P          LL_TIM_IC_Config\n
+  *         CCER         CC3NP         LL_TIM_IC_Config\n
+  *         CCER         CC4P          LL_TIM_IC_Config\n
+  *         CCER         CC4NP         LL_TIM_IC_Config
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @param  Configuration This parameter must be a combination of all the following values:
+  *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
+  *         @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
+  *         @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
+             ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S))                \
+             << SHIFT_TAB_ICxx[iChannel]);
+  MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
+             (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+  * @brief  Set the active input.
+  * @rmtoll CCMR1        CC1S          LL_TIM_IC_SetActiveInput\n
+  *         CCMR1        CC2S          LL_TIM_IC_SetActiveInput\n
+  *         CCMR2        CC3S          LL_TIM_IC_SetActiveInput\n
+  *         CCMR2        CC4S          LL_TIM_IC_SetActiveInput
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @param  ICActiveInput This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
+  *         @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
+  *         @arg @ref LL_TIM_ACTIVEINPUT_TRC
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
+}
+
+/**
+  * @brief  Get the current active input.
+  * @rmtoll CCMR1        CC1S          LL_TIM_IC_GetActiveInput\n
+  *         CCMR1        CC2S          LL_TIM_IC_GetActiveInput\n
+  *         CCMR2        CC3S          LL_TIM_IC_GetActiveInput\n
+  *         CCMR2        CC4S          LL_TIM_IC_GetActiveInput
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
+  *         @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
+  *         @arg @ref LL_TIM_ACTIVEINPUT_TRC
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
+}
+
+/**
+  * @brief  Set the prescaler of input channel.
+  * @rmtoll CCMR1        IC1PSC        LL_TIM_IC_SetPrescaler\n
+  *         CCMR1        IC2PSC        LL_TIM_IC_SetPrescaler\n
+  *         CCMR2        IC3PSC        LL_TIM_IC_SetPrescaler\n
+  *         CCMR2        IC4PSC        LL_TIM_IC_SetPrescaler
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @param  ICPrescaler This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ICPSC_DIV1
+  *         @arg @ref LL_TIM_ICPSC_DIV2
+  *         @arg @ref LL_TIM_ICPSC_DIV4
+  *         @arg @ref LL_TIM_ICPSC_DIV8
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
+}
+
+/**
+  * @brief  Get the current prescaler value acting on an  input channel.
+  * @rmtoll CCMR1        IC1PSC        LL_TIM_IC_GetPrescaler\n
+  *         CCMR1        IC2PSC        LL_TIM_IC_GetPrescaler\n
+  *         CCMR2        IC3PSC        LL_TIM_IC_GetPrescaler\n
+  *         CCMR2        IC4PSC        LL_TIM_IC_GetPrescaler
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_ICPSC_DIV1
+  *         @arg @ref LL_TIM_ICPSC_DIV2
+  *         @arg @ref LL_TIM_ICPSC_DIV4
+  *         @arg @ref LL_TIM_ICPSC_DIV8
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
+}
+
+/**
+  * @brief  Set the input filter duration.
+  * @rmtoll CCMR1        IC1F          LL_TIM_IC_SetFilter\n
+  *         CCMR1        IC2F          LL_TIM_IC_SetFilter\n
+  *         CCMR2        IC3F          LL_TIM_IC_SetFilter\n
+  *         CCMR2        IC4F          LL_TIM_IC_SetFilter
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @param  ICFilter This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
+}
+
+/**
+  * @brief  Get the input filter duration.
+  * @rmtoll CCMR1        IC1F          LL_TIM_IC_GetFilter\n
+  *         CCMR1        IC2F          LL_TIM_IC_GetFilter\n
+  *         CCMR2        IC3F          LL_TIM_IC_GetFilter\n
+  *         CCMR2        IC4F          LL_TIM_IC_GetFilter
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
+}
+
+/**
+  * @brief  Set the input channel polarity.
+  * @rmtoll CCER         CC1P          LL_TIM_IC_SetPolarity\n
+  *         CCER         CC1NP         LL_TIM_IC_SetPolarity\n
+  *         CCER         CC2P          LL_TIM_IC_SetPolarity\n
+  *         CCER         CC2NP         LL_TIM_IC_SetPolarity\n
+  *         CCER         CC3P          LL_TIM_IC_SetPolarity\n
+  *         CCER         CC3NP         LL_TIM_IC_SetPolarity\n
+  *         CCER         CC4P          LL_TIM_IC_SetPolarity\n
+  *         CCER         CC4NP         LL_TIM_IC_SetPolarity
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @param  ICPolarity This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_IC_POLARITY_RISING
+  *         @arg @ref LL_TIM_IC_POLARITY_FALLING
+  *         @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
+             ICPolarity << SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+  * @brief  Get the current input channel polarity.
+  * @rmtoll CCER         CC1P          LL_TIM_IC_GetPolarity\n
+  *         CCER         CC1NP         LL_TIM_IC_GetPolarity\n
+  *         CCER         CC2P          LL_TIM_IC_GetPolarity\n
+  *         CCER         CC2NP         LL_TIM_IC_GetPolarity\n
+  *         CCER         CC3P          LL_TIM_IC_GetPolarity\n
+  *         CCER         CC3NP         LL_TIM_IC_GetPolarity\n
+  *         CCER         CC4P          LL_TIM_IC_GetPolarity\n
+  *         CCER         CC4NP         LL_TIM_IC_GetPolarity
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_IC_POLARITY_RISING
+  *         @arg @ref LL_TIM_IC_POLARITY_FALLING
+  *         @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
+          SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+  * @brief  Connect the TIMx_CH1, CH2 and CH3 pins  to the TI1 input (XOR combination).
+  * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides an XOR input.
+  * @rmtoll CR2          TI1S          LL_TIM_IC_EnableXORCombination
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
+}
+
+/**
+  * @brief  Disconnect the TIMx_CH1, CH2 and CH3 pins  from the TI1 input.
+  * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides an XOR input.
+  * @rmtoll CR2          TI1S          LL_TIM_IC_DisableXORCombination
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
+}
+
+/**
+  * @brief  Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
+  * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+  * a timer instance provides an XOR input.
+  * @rmtoll CR2          TI1S          LL_TIM_IC_IsEnabledXORCombination
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get captured value for input channel 1.
+  * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+  *       input channel 1 is supported by a timer instance.
+  * @rmtoll CCR1         CCR1          LL_TIM_IC_GetCaptureCH1
+  * @param  TIMx Timer instance
+  * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR1));
+}
+
+/**
+  * @brief  Get captured value for input channel 2.
+  * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+  *       input channel 2 is supported by a timer instance.
+  * @rmtoll CCR2         CCR2          LL_TIM_IC_GetCaptureCH2
+  * @param  TIMx Timer instance
+  * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR2));
+}
+
+/**
+  * @brief  Get captured value for input channel 3.
+  * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+  *       input channel 3 is supported by a timer instance.
+  * @rmtoll CCR3         CCR3          LL_TIM_IC_GetCaptureCH3
+  * @param  TIMx Timer instance
+  * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR3));
+}
+
+/**
+  * @brief  Get captured value for input channel 4.
+  * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+  *       input channel 4 is supported by a timer instance.
+  * @rmtoll CCR4         CCR4          LL_TIM_IC_GetCaptureCH4
+  * @param  TIMx Timer instance
+  * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR4));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
+  * @{
+  */
+/**
+  * @brief  Enable external clock mode 2.
+  * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
+  * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports external clock mode2.
+  * @rmtoll SMCR         ECE           LL_TIM_EnableExternalClock
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
+}
+
+/**
+  * @brief  Disable external clock mode 2.
+  * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports external clock mode2.
+  * @rmtoll SMCR         ECE           LL_TIM_DisableExternalClock
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
+}
+
+/**
+  * @brief  Indicate whether external clock mode 2 is enabled.
+  * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports external clock mode2.
+  * @rmtoll SMCR         ECE           LL_TIM_IsEnabledExternalClock
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the clock source of the counter clock.
+  * @note when selected clock source is external clock mode 1, the timer input
+  *       the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
+  *       function. This timer input must be configured by calling
+  *       the @ref LL_TIM_IC_Config() function.
+  * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports external clock mode1.
+  * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports external clock mode2.
+  * @rmtoll SMCR         SMS           LL_TIM_SetClockSource\n
+  *         SMCR         ECE           LL_TIM_SetClockSource
+  * @param  TIMx Timer instance
+  * @param  ClockSource This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
+  *         @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
+  *         @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
+{
+  MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
+}
+
+/**
+  * @brief  Set the encoder interface mode.
+  * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports the encoder mode.
+  * @rmtoll SMCR         SMS           LL_TIM_SetEncoderMode
+  * @param  TIMx Timer instance
+  * @param  EncoderMode This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ENCODERMODE_X2_TI1
+  *         @arg @ref LL_TIM_ENCODERMODE_X2_TI2
+  *         @arg @ref LL_TIM_ENCODERMODE_X4_TI12
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
+{
+  MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
+  * @{
+  */
+/**
+  * @brief  Set the trigger output (TRGO) used for timer synchronization .
+  * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance can operate as a master timer.
+  * @rmtoll CR2          MMS           LL_TIM_SetTriggerOutput
+  * @param  TIMx Timer instance
+  * @param  TimerSynchronization This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_TRGO_RESET
+  *         @arg @ref LL_TIM_TRGO_ENABLE
+  *         @arg @ref LL_TIM_TRGO_UPDATE
+  *         @arg @ref LL_TIM_TRGO_CC1IF
+  *         @arg @ref LL_TIM_TRGO_OC1REF
+  *         @arg @ref LL_TIM_TRGO_OC2REF
+  *         @arg @ref LL_TIM_TRGO_OC3REF
+  *         @arg @ref LL_TIM_TRGO_OC4REF
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
+{
+  MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
+}
+
+/**
+  * @brief  Set the trigger output 2 (TRGO2) used for ADC synchronization .
+  * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance can be used for ADC synchronization.
+  * @rmtoll CR2          MMS2          LL_TIM_SetTriggerOutput2
+  * @param  TIMx Timer Instance
+  * @param  ADCSynchronization This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_TRGO2_RESET
+  *         @arg @ref LL_TIM_TRGO2_ENABLE
+  *         @arg @ref LL_TIM_TRGO2_UPDATE
+  *         @arg @ref LL_TIM_TRGO2_CC1F
+  *         @arg @ref LL_TIM_TRGO2_OC1
+  *         @arg @ref LL_TIM_TRGO2_OC2
+  *         @arg @ref LL_TIM_TRGO2_OC3
+  *         @arg @ref LL_TIM_TRGO2_OC4
+  *         @arg @ref LL_TIM_TRGO2_OC5
+  *         @arg @ref LL_TIM_TRGO2_OC6
+  *         @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING
+  *         @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING
+  *         @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING
+  *         @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
+  *         @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING
+  *         @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
+{
+  MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization);
+}
+
+/**
+  * @brief  Set the synchronization mode of a slave timer.
+  * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance can operate as a slave timer.
+  * @rmtoll SMCR         SMS           LL_TIM_SetSlaveMode
+  * @param  TIMx Timer instance
+  * @param  SlaveMode This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_SLAVEMODE_DISABLED
+  *         @arg @ref LL_TIM_SLAVEMODE_RESET
+  *         @arg @ref LL_TIM_SLAVEMODE_GATED
+  *         @arg @ref LL_TIM_SLAVEMODE_TRIGGER
+  *         @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
+{
+  MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
+}
+
+/**
+  * @brief  Set the selects the trigger input to be used to synchronize the counter.
+  * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance can operate as a slave timer.
+  * @rmtoll SMCR         TS            LL_TIM_SetTriggerInput
+  * @param  TIMx Timer instance
+  * @param  TriggerInput This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_TS_ITR0
+  *         @arg @ref LL_TIM_TS_ITR1
+  *         @arg @ref LL_TIM_TS_ITR2
+  *         @arg @ref LL_TIM_TS_ITR3
+  *         @arg @ref LL_TIM_TS_ITR4
+  *         @arg @ref LL_TIM_TS_ITR5
+  *         @arg @ref LL_TIM_TS_ITR6
+  *         @arg @ref LL_TIM_TS_ITR7
+  *         @arg @ref LL_TIM_TS_ITR8 (*)
+  *         @arg @ref LL_TIM_TS_ITR9 (*)
+  *         @arg @ref LL_TIM_TS_ITR10 (*)
+  *         @arg @ref LL_TIM_TS_ITR11 (*)
+  *         @arg @ref LL_TIM_TS_ITR12 (*)
+  *         @arg @ref LL_TIM_TS_ITR13 (*)
+  *         @arg @ref LL_TIM_TS_TI1F_ED
+  *         @arg @ref LL_TIM_TS_TI1FP1
+  *         @arg @ref LL_TIM_TS_TI2FP2
+  *         @arg @ref LL_TIM_TS_ETRF
+  *
+  *      (*)  Value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
+{
+  MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
+}
+
+/**
+  * @brief  Enable the Master/Slave mode.
+  * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance can operate as a slave timer.
+  * @rmtoll SMCR         MSM           LL_TIM_EnableMasterSlaveMode
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
+}
+
+/**
+  * @brief  Disable the Master/Slave mode.
+  * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance can operate as a slave timer.
+  * @rmtoll SMCR         MSM           LL_TIM_DisableMasterSlaveMode
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
+}
+
+/**
+  * @brief Indicates whether the Master/Slave mode is enabled.
+  * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+  * a timer instance can operate as a slave timer.
+  * @rmtoll SMCR         MSM           LL_TIM_IsEnabledMasterSlaveMode
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Configure the external trigger (ETR) input.
+  * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides an external trigger input.
+  * @rmtoll SMCR         ETP           LL_TIM_ConfigETR\n
+  *         SMCR         ETPS          LL_TIM_ConfigETR\n
+  *         SMCR         ETF           LL_TIM_ConfigETR
+  * @param  TIMx Timer instance
+  * @param  ETRPolarity This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
+  *         @arg @ref LL_TIM_ETR_POLARITY_INVERTED
+  * @param  ETRPrescaler This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ETR_PRESCALER_DIV1
+  *         @arg @ref LL_TIM_ETR_PRESCALER_DIV2
+  *         @arg @ref LL_TIM_ETR_PRESCALER_DIV4
+  *         @arg @ref LL_TIM_ETR_PRESCALER_DIV8
+  * @param  ETRFilter This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV1
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
+                                      uint32_t ETRFilter)
+{
+  MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
+}
+
+/**
+  * @brief  Select the external trigger (ETR) input source.
+  * @note Macro IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or
+  *       not a timer instance supports ETR source selection.
+  * @rmtoll AF1          ETRSEL        LL_TIM_SetETRSource
+  * @param  TIMx Timer instance
+  * @param  ETRSource This parameter can be one of the following values:
+  *      For TIM1, the parameter is one of the following values:
+  *         @arg LL_TIM_TIM1_ETRSOURCE_GPIO:               TIM1_ETR is connected to GPIO
+  *         @arg LL_TIM_TIM1_ETRSOURCE_COMP1:              TIM1_ETR is connected to COMP1 output
+  *         @arg LL_TIM_TIM1_ETRSOURCE_COMP2:              TIM1_ETR is connected to COMP2 output
+  *         @arg LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1:          TIM1_ETR is connected to ADC1 AWD1
+  *         @arg LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2:          TIM1_ETR is connected to ADC1 AWD2
+  *         @arg LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3:          TIM1_ETR is connected to ADC1 AWD3
+  *         @arg LL_TIM_TIM1_ETRSOURCE_ADC3_AWD1:          TIM1_ETR is connected to ADC3 AWD1
+  *         @arg LL_TIM_TIM1_ETRSOURCE_ADC3_AWD2:          TIM1_ETR is connected to ADC3 AWD2
+  *         @arg LL_TIM_TIM1_ETRSOURCE_ADC3_AWD3:          TIM1_ETR is connected to ADC3 AWD3
+  *
+  *      For TIM2, the parameter is one of the following values:
+  *         @arg LL_TIM_TIM2_ETRSOURCE_GPIO:               TIM2_ETR is connected to GPIO
+  *         @arg LL_TIM_TIM2_ETRSOURCE_COMP1:              TIM2_ETR is connected to COMP1 output
+  *         @arg LL_TIM_TIM2_ETRSOURCE_COMP2:              TIM2_ETR is connected to COMP2 output
+  *         @arg LL_TIM_TIM2_ETRSOURCE_LSE:                TIM2_ETR is connected to LSE
+  *         @arg LL_TIM_TIM2_ETRSOURCE_SAI1_FSA:           TIM2_ETR is connected to SAI1 FS_A
+  *         @arg LL_TIM_TIM2_ETRSOURCE_SAI1_FSB:           TIM2_ETR is connected to SAI1 FS_B
+  *
+  *      For TIM3, the parameter is one of the following values:
+  *         @arg LL_TIM_TIM3_ETRSOURCE_GPIO:               TIM3_ETR is connected to GPIO
+  *         @arg LL_TIM_TIM3_ETRSOURCE_COMP1:              TIM3_ETR is connected to COMP1 output
+  *
+  *      For TIM5, the parameter is one of the following values:
+  *         @arg LL_TIM_TIM5_ETRSOURCE_GPIO:               TIM5_ETR is connected to GPIO
+  *         @arg LL_TIM_TIM5_ETRSOURCE_SAI2_FSA:           TIM5_ETR is connected to SAI2 FS_A (*)
+  *         @arg LL_TIM_TIM5_ETRSOURCE_SAI2_FSB:           TIM5_ETR is connected to SAI2 FS_B (*)
+  *         @arg LL_TIM_TIM5_ETRSOURCE_SAI4_FSA:           TIM5_ETR is connected to SAI2 FS_A (*)
+  *         @arg LL_TIM_TIM5_ETRSOURCE_SAI4_FSB:           TIM5_ETR is connected to SAI2 FS_B (*)
+  *
+  *      For TIM8, the parameter is one of the following values:
+  *         @arg LL_TIM_TIM8_ETRSOURCE_GPIO:               TIM8_ETR is connected to GPIO
+  *         @arg LL_TIM_TIM8_ETRSOURCE_COMP1:              TIM8_ETR is connected to COMP1 output
+  *         @arg LL_TIM_TIM8_ETRSOURCE_COMP2:              TIM8_ETR is connected to COMP2 output
+  *         @arg LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1:          TIM8_ETR is connected to ADC2 AWD1
+  *         @arg LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2:          TIM8_ETR is connected to ADC2 AWD2
+  *         @arg LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3:          TIM8_ETR is connected to ADC2 AWD3
+  *         @arg LL_TIM_TIM8_ETRSOURCE_ADC3_AWD1:          TIM8_ETR is connected to ADC3 AWD1
+  *         @arg LL_TIM_TIM8_ETRSOURCE_ADC3_AWD2:          TIM8_ETR is connected to ADC3 AWD2
+  *         @arg LL_TIM_TIM8_ETRSOURCE_ADC3_AWD3:          TIM8_ETR is connected to ADC3 AWD3
+  *
+  *      For TIM23, the parameter is one of the following values: (*)
+  *         @arg LL_TIM_TIM23_ETRSOURCE_GPIO               TIM23_ETR is connected to GPIO
+  *         @arg LL_TIM_TIM23_ETRSOURCE_COMP1              TIM23_ETR is connected to COMP1 output
+  *         @arg LL_TIM_TIM23_ETRSOURCE_COMP2              TIM23_ETR is connected to COMP2 output
+  *
+  *      For TIM24, the parameter is one of the following values: (*)
+  *        @arg LL_TIM_TIM24_ETRSOURCE_GPIO                TIM24_ETR is connected to GPIO
+  *        @arg LL_TIM_TIM24_ETRSOURCE_SAI4_FSA            TIM24_ETR is connected to SAI4 FS_A
+  *        @arg LL_TIM_TIM24_ETRSOURCE_SAI4_FSB            TIM24_ETR is connected to SAI4 FS_B
+  *        @arg LL_TIM_TIM24_ETRSOURCE_SAI1_FSA            TIM24_ETR is connected to SAI1 FS_A
+  *        @arg LL_TIM_TIM24_ETRSOURCE_SAI1_FSB            TIM24_ETR is connected to SAI1 FS_B
+  *
+  *      (*)  Value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource)
+{
+  MODIFY_REG(TIMx->AF1, TIMx_AF1_ETRSEL, ETRSource);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Break_Function Break function configuration
+  * @{
+  */
+/**
+  * @brief  Enable the break function.
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         BKE           LL_TIM_EnableBRK
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
+}
+
+/**
+  * @brief  Disable the break function.
+  * @rmtoll BDTR         BKE           LL_TIM_DisableBRK
+  * @param  TIMx Timer instance
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
+}
+
+#if defined(TIM_BDTR_BKBID)
+/**
+  * @brief  Configure the break input.
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @note Bidirectional mode is only supported by advanced timer instances.
+  *       Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance is an advanced-control timer.
+  * @note In bidirectional mode (BKBID bit set), the Break input is configured both
+  *        in input mode and in open drain output mode. Any active Break event will
+  *        assert a low logic level on the Break input to indicate an internal break
+  *        event to external devices.
+  * @note When bidirectional mode isn't supported, BreakAFMode must be set to
+  *       LL_TIM_BREAK_AFMODE_INPUT.
+  * @rmtoll BDTR         BKP           LL_TIM_ConfigBRK\n
+  *         BDTR         BKF           LL_TIM_ConfigBRK\n
+  *         BDTR         BKBID         LL_TIM_ConfigBRK
+  * @param  TIMx Timer instance
+  * @param  BreakPolarity This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BREAK_POLARITY_LOW
+  *         @arg @ref LL_TIM_BREAK_POLARITY_HIGH
+  * @param  BreakFilter This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
+  * @param  BreakAFMode This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BREAK_AFMODE_INPUT
+  *         @arg @ref LL_TIM_BREAK_AFMODE_BIDIRECTIONAL
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter,
+                                      uint32_t BreakAFMode)
+{
+  MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF | TIM_BDTR_BKBID, BreakPolarity | BreakFilter | BreakAFMode);
+}
+
+#else
+/**
+  * @brief  Configure the break input.
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         BKP           LL_TIM_ConfigBRK\n
+  *         BDTR         BKF           LL_TIM_ConfigBRK
+  * @param  TIMx Timer instance
+  * @param  BreakPolarity This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BREAK_POLARITY_LOW
+  *         @arg @ref LL_TIM_BREAK_POLARITY_HIGH
+  * @param  BreakFilter This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity,
+                                      uint32_t BreakFilter)
+{
+  MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF, BreakPolarity | BreakFilter);
+}
+
+#endif /* TIM_BDTR_BKBID */
+#if defined(TIM_BDTR_BKBID)
+/**
+  * @brief  Disarm the break input (when it operates in bidirectional mode).
+  * @note  The break input can be disarmed only when it is configured in
+  *        bidirectional mode and when when MOE is reset.
+  * @note  Purpose is to be able to have the input voltage back to high-state,
+  *        whatever the time constant on the output .
+  * @rmtoll BDTR         BKDSRM        LL_TIM_DisarmBRK
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisarmBRK(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
+}
+
+/**
+  * @brief  Re-arm the break input (when it operates in bidirectional mode).
+  * @note  The Break input is automatically armed as soon as MOE bit is set.
+  * @rmtoll BDTR         BKDSRM        LL_TIM_ReArmBRK
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ReArmBRK(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
+}
+
+#endif /*TIM_BDTR_BKBID */
+/**
+  * @brief  Enable the break 2 function.
+  * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a second break input.
+  * @rmtoll BDTR         BK2E          LL_TIM_EnableBRK2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
+}
+
+/**
+  * @brief  Disable the break  2 function.
+  * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a second break input.
+  * @rmtoll BDTR         BK2E          LL_TIM_DisableBRK2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
+}
+
+#if defined(TIM_BDTR_BKBID)
+/**
+  * @brief  Configure the break 2 input.
+  * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a second break input.
+  * @note Bidirectional mode is only supported by advanced timer instances.
+  *       Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance is an advanced-control timer.
+  * @note In bidirectional mode (BK2BID bit set), the Break 2 input is configured both
+  *        in input mode and in open drain output mode. Any active Break event will
+  *        assert a low logic level on the Break 2 input to indicate an internal break
+  *        event to external devices.
+  * @note When bidirectional mode isn't supported, Break2AFMode must be set to
+  *       LL_TIM_BREAK2_AFMODE_INPUT.
+  * @rmtoll BDTR         BK2P          LL_TIM_ConfigBRK2\n
+  *         BDTR         BK2F          LL_TIM_ConfigBRK2\n
+  *         BDTR         BK2BID        LL_TIM_ConfigBRK2
+  * @param  TIMx Timer instance
+  * @param  Break2Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BREAK2_POLARITY_LOW
+  *         @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
+  * @param  Break2Filter This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
+  * @param  Break2AFMode This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BREAK2_AFMODE_INPUT
+  *         @arg @ref LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter,
+                                       uint32_t Break2AFMode)
+{
+  MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F | TIM_BDTR_BK2BID, Break2Polarity | Break2Filter | Break2AFMode);
+}
+
+#else
+/**
+  * @brief  Configure the break 2 input.
+  * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a second break input.
+  * @rmtoll BDTR         BK2P          LL_TIM_ConfigBRK2\n
+  *         BDTR         BK2F          LL_TIM_ConfigBRK2
+  * @param  TIMx Timer instance
+  * @param  Break2Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BREAK2_POLARITY_LOW
+  *         @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
+  * @param  Break2Filter This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter)
+{
+  MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F, Break2Polarity | Break2Filter);
+}
+
+#endif /*TIM_BDTR_BKBID */
+#if defined(TIM_BDTR_BKBID)
+/**
+  * @brief  Disarm the break 2 input (when it operates in bidirectional mode).
+  * @note  The break 2 input can be disarmed only when it is configured in
+  *        bidirectional mode and when when MOE is reset.
+  * @note  Purpose is to be able to have the input voltage back to high-state,
+  *        whatever the time constant on the output.
+  * @rmtoll BDTR         BK2DSRM       LL_TIM_DisarmBRK2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisarmBRK2(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM);
+}
+
+/**
+  * @brief  Re-arm the break 2 input (when it operates in bidirectional mode).
+  * @note  The Break 2 input is automatically armed as soon as MOE bit is set.
+  * @rmtoll BDTR         BK2DSRM       LL_TIM_ReArmBRK2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ReArmBRK2(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM);
+}
+
+#endif /*TIM_BDTR_BKBID */
+/**
+  * @brief  Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         OSSI          LL_TIM_SetOffStates\n
+  *         BDTR         OSSR          LL_TIM_SetOffStates
+  * @param  TIMx Timer instance
+  * @param  OffStateIdle This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_OSSI_DISABLE
+  *         @arg @ref LL_TIM_OSSI_ENABLE
+  * @param  OffStateRun This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_OSSR_DISABLE
+  *         @arg @ref LL_TIM_OSSR_ENABLE
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
+{
+  MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
+}
+
+/**
+  * @brief  Enable automatic output (MOE can be set by software or automatically when a break input is active).
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         AOE           LL_TIM_EnableAutomaticOutput
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
+}
+
+/**
+  * @brief  Disable automatic output (MOE can be set only by software).
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         AOE           LL_TIM_DisableAutomaticOutput
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
+}
+
+/**
+  * @brief  Indicate whether automatic output is enabled.
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         AOE           LL_TIM_IsEnabledAutomaticOutput
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the outputs (set the MOE bit in TIMx_BDTR register).
+  * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
+  *       software and is reset in case of break or break2 event
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         MOE           LL_TIM_EnableAllOutputs
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
+}
+
+/**
+  * @brief  Disable the outputs (reset the MOE bit in TIMx_BDTR register).
+  * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
+  *       software and is reset in case of break or break2 event.
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         MOE           LL_TIM_DisableAllOutputs
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
+}
+
+/**
+  * @brief  Indicates whether outputs are enabled.
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         MOE           LL_TIM_IsEnabledAllOutputs
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
+}
+
+#if defined(TIM_BREAK_INPUT_SUPPORT)
+/**
+  * @brief  Enable the signals connected to the designated timer break input.
+  * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
+  *       or not a timer instance allows for break input selection.
+  * @rmtoll AF1          BKINE         LL_TIM_EnableBreakInputSource\n
+  *         AF1          BKCMP1E       LL_TIM_EnableBreakInputSource\n
+  *         AF1          BKCMP2E       LL_TIM_EnableBreakInputSource\n
+  *         AF1          BKDF1BK0E     LL_TIM_EnableBreakInputSource\n
+  *         AF2          BK2INE        LL_TIM_EnableBreakInputSource\n
+  *         AF2          BK2CMP1E      LL_TIM_EnableBreakInputSource\n
+  *         AF2          BK2CMP2E      LL_TIM_EnableBreakInputSource\n
+  *         AF2          BK2DF1BK1E    LL_TIM_EnableBreakInputSource
+  * @param  TIMx Timer instance
+  * @param  BreakInput This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BREAK_INPUT_BKIN
+  *         @arg @ref LL_TIM_BREAK_INPUT_BKIN2
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BKIN_SOURCE_BKIN
+  *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
+  *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
+  *         @arg @ref LL_TIM_BKIN_SOURCE_DF1BK
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
+{
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
+  SET_BIT(*pReg, Source);
+}
+
+/**
+  * @brief  Disable the signals connected to the designated timer break input.
+  * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
+  *       or not a timer instance allows for break input selection.
+  * @rmtoll AF1          BKINE         LL_TIM_DisableBreakInputSource\n
+  *         AF1          BKCMP1E       LL_TIM_DisableBreakInputSource\n
+  *         AF1          BKCMP2E       LL_TIM_DisableBreakInputSource\n
+  *         AF1          BKDF1BK0E     LL_TIM_DisableBreakInputSource\n
+  *         AF2          BK2INE        LL_TIM_DisableBreakInputSource\n
+  *         AF2          BK2CMP1E      LL_TIM_DisableBreakInputSource\n
+  *         AF2          BK2CMP2E      LL_TIM_DisableBreakInputSource\n
+  *         AF2          BK2DF1BK1E    LL_TIM_DisableBreakInputSource
+  * @param  TIMx Timer instance
+  * @param  BreakInput This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BREAK_INPUT_BKIN
+  *         @arg @ref LL_TIM_BREAK_INPUT_BKIN2
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BKIN_SOURCE_BKIN
+  *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
+  *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
+  *         @arg @ref LL_TIM_BKIN_SOURCE_DF1BK
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
+{
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
+  CLEAR_BIT(*pReg, Source);
+}
+
+/**
+  * @brief  Set the polarity of the break signal for the timer break input.
+  * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
+  *       or not a timer instance allows for break input selection.
+  * @rmtoll AF1          BKINP         LL_TIM_SetBreakInputSourcePolarity\n
+  *         AF1          BKCMP1P       LL_TIM_SetBreakInputSourcePolarity\n
+  *         AF1          BKCMP2P       LL_TIM_SetBreakInputSourcePolarity\n
+  *         AF2          BK2INP        LL_TIM_SetBreakInputSourcePolarity\n
+  *         AF2          BK2CMP1P      LL_TIM_SetBreakInputSourcePolarity\n
+  *         AF2          BK2CMP2P      LL_TIM_SetBreakInputSourcePolarity
+  * @param  TIMx Timer instance
+  * @param  BreakInput This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BREAK_INPUT_BKIN
+  *         @arg @ref LL_TIM_BREAK_INPUT_BKIN2
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BKIN_SOURCE_BKIN
+  *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
+  *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BKIN_POLARITY_LOW
+  *         @arg @ref LL_TIM_BKIN_POLARITY_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source,
+                                                        uint32_t Polarity)
+{
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
+  MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE));
+}
+#endif /* TIM_BREAK_INPUT_SUPPORT */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
+  * @{
+  */
+/**
+  * @brief  Configures the timer DMA burst feature.
+  * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
+  *       not a timer instance supports the DMA burst mode.
+  * @rmtoll DCR          DBL           LL_TIM_ConfigDMABurst\n
+  *         DCR          DBA           LL_TIM_ConfigDMABurst
+  * @param  TIMx Timer instance
+  * @param  DMABurstBaseAddress This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_SR
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_AF1
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_AF2
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_TISEL
+  *
+  * @param  DMABurstLength This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
+{
+  MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
+  * @{
+  */
+/**
+  * @brief  Remap TIM inputs (input channel, internal/external triggers).
+  * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
+  *       a some timer inputs can be remapped.
+  *         TIM1: one of the following values:
+  *            @arg LL_TIM_TIM1_TI1_RMP_GPIO:                TIM1 TI1 is connected to GPIO
+  *            @arg LL_TIM_TIM1_TI1_RMP_COMP1:               TIM1 TI1 is connected to COMP1 output
+  *
+  *         TIM2: one of the following values:
+  *            @arg LL_TIM_TIM2_TI4_RMP_GPIO:                TIM2 TI4 is connected to GPIO
+  *            @arg LL_TIM_TIM2_TI4_RMP_COMP1:               TIM2 TI4 is connected to COMP1 output
+  *            @arg LL_TIM_TIM2_TI4_RMP_COMP2:               TIM2 TI4 is connected to COMP2 output
+  *            @arg LL_TIM_TIM2_TI4_RMP_COMP1_COMP2:         TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output
+  *
+  *         TIM3: one of the following values:
+  *            @arg LL_TIM_TIM3_TI1_RMP_GPIO:                TIM3 TI1 is connected to GPIO
+  *            @arg LL_TIM_TIM3_TI1_RMP_COMP1:               TIM3 TI1 is connected to COMP1 output
+  *            @arg LL_TIM_TIM3_TI1_RMP_COMP2:               TIM3 TI1 is connected to COMP2 output
+  *            @arg LL_TIM_TIM3_TI1_RMP_COMP1_COMP2:         TIM3 TI1 is connected to logical OR between COMP1 and COMP2 output
+  *
+  *         TIM5: one of the following values:
+  *            @arg LL_TIM_TIM5_TI1_RMP_GPIO:                TIM5 TI1 is connected to GPIO
+  *            @arg LL_TIM_TIM5_TI1_RMP_CAN_TMP:             TIM5 TI1 is connected to CAN TMP
+  *            @arg LL_TIM_TIM5_TI1_RMP_CAN_RTP:             TIM5 TI1 is connected to CAN RTP
+  *
+  *         TIM8: one of the following values:
+  *            @arg LL_TIM_TIM8_TI1_RMP_GPIO:               TIM8 TI1 is connected to GPIO
+  *            @arg LL_TIM_TIM8_TI1_RMP_COMP2:              TIM8 TI1 is connected to COMP2 output
+  *
+  *         TIM12: one of the following values: (*)
+  *            @arg LL_TIM_TIM12_TI1_RMP_GPIO:              TIM12 TI1 is connected to GPIO
+  *            @arg LL_TIM_TIM12_TI1_RMP_SPDIF_FS:          TIM12 TI1 is connected to SPDIF FS
+  *
+  *         TIM15: one of the following values:
+  *            @arg LL_TIM_TIM15_TI1_RMP_GPIO:              TIM15 TI1 is connected to GPIO
+  *            @arg LL_TIM_TIM15_TI1_RMP_TIM2:              TIM15 TI1 is connected to TIM2 CH1
+  *            @arg LL_TIM_TIM15_TI1_RMP_TIM3:              TIM15 TI1 is connected to TIM3 CH1
+  *            @arg LL_TIM_TIM15_TI1_RMP_TIM4:              TIM15 TI1 is connected to TIM4 CH1
+  *            @arg LL_TIM_TIM15_TI1_RMP_LSE:               TIM15 TI1 is connected to LSE
+  *            @arg LL_TIM_TIM15_TI1_RMP_CSI:               TIM15 TI1 is connected to CSI
+  *            @arg LL_TIM_TIM15_TI1_RMP_MCO2:              TIM15 TI1 is connected to MCO2
+  *            @arg LL_TIM_TIM15_TI2_RMP_GPIO:              TIM15 TI2 is connected to GPIO
+  *            @arg LL_TIM_TIM15_TI2_RMP_TIM2:              TIM15 TI2 is connected to TIM2 CH2
+  *            @arg LL_TIM_TIM15_TI2_RMP_TIM3:              TIM15 TI2 is connected to TIM3 CH2
+  *            @arg LL_TIM_TIM15_TI2_RMP_TIM4:              TIM15 TI2 is connected to TIM4 CH2
+  *
+  *         TIM16: one of the following values:
+  *            @arg LL_TIM_TIM16_TI1_RMP_GPIO:              TIM16 TI1 is connected to GPIO
+  *            @arg LL_TIM_TIM16_TI1_RMP_LSI:               TIM16 TI1 is connected to LSI
+  *            @arg LL_TIM_TIM16_TI1_RMP_LSE:               TIM16 TI1 is connected to LSE
+  *            @arg LL_TIM_TIM16_TI1_RMP_RTC:               TIM16 TI1 is connected to RTC wakeup interrupt
+  *
+  *         TIM17: one of the following values:
+  *            @arg LL_TIM_TIM17_TI1_RMP_GPIO:              TIM17 TI1 is connected to GPIO
+  *            @arg LL_TIM_TIM17_TI1_RMP_SPDIF_FS:          TIM17 TI1 is connected to SPDIF FS (*)
+  *            @arg LL_TIM_TIM17_TI1_RMP_HSE_1MHZ:          TIM17 TI1 is connected to HSE 1MHz
+  *            @arg LL_TIM_TIM17_TI1_RMP_MCO1:              TIM17 TI1 is connected to MCO1
+  *
+  *         TIM23: one of the following values: (*)
+  *            @arg LL_TIM_TIM23_TI4_RMP_GPIO               TIM23_TI4 is connected to GPIO
+  *            @arg LL_TIM_TIM23_TI4_RMP_COMP1              TIM23_TI4 is connected to COMP1 output
+  *            @arg LL_TIM_TIM23_TI4_RMP_COMP2              TIM23_TI4 is connected to COMP2 output
+  *            @arg LL_TIM_TIM23_TI4_RMP_COMP1_COMP2        TIM23_TI4 is connected to COMP2 output
+  *
+  *         TIM24: one of the following values: (*)
+  *            @arg LL_TIM_TIM24_TI1_RMP_GPIO               TIM24_TI1 is connected to GPIO
+  *            @arg LL_TIM_TIM24_TI1_RMP_CAN_TMP            TIM24_TI1 is connected to CAN_TMP
+  *            @arg LL_TIM_TIM24_TI1_RMP_CAN_RTP            TIM24_TI1 is connected to CAN_RTP
+  *            @arg LL_TIM_TIM24_TI1_RMP_CAN_SOC            TIM24_TI1 is connected to CAN_SOC
+  *
+  *         (*)  Value not defined in all devices. \n
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
+{
+  MODIFY_REG(TIMx->TISEL, (TIM_TISEL_TI1SEL | TIM_TISEL_TI2SEL | TIM_TISEL_TI3SEL | TIM_TISEL_TI4SEL), Remap);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
+  * @{
+  */
+/**
+  * @brief  Clear the update interrupt flag (UIF).
+  * @rmtoll SR           UIF           LL_TIM_ClearFlag_UPDATE
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
+}
+
+/**
+  * @brief  Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
+  * @rmtoll SR           UIF           LL_TIM_IsActiveFlag_UPDATE
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 1 interrupt flag (CC1F).
+  * @rmtoll SR           CC1IF         LL_TIM_ClearFlag_CC1
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
+  * @rmtoll SR           CC1IF         LL_TIM_IsActiveFlag_CC1
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 2 interrupt flag (CC2F).
+  * @rmtoll SR           CC2IF         LL_TIM_ClearFlag_CC2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
+  * @rmtoll SR           CC2IF         LL_TIM_IsActiveFlag_CC2
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 3 interrupt flag (CC3F).
+  * @rmtoll SR           CC3IF         LL_TIM_ClearFlag_CC3
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
+  * @rmtoll SR           CC3IF         LL_TIM_IsActiveFlag_CC3
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 4 interrupt flag (CC4F).
+  * @rmtoll SR           CC4IF         LL_TIM_ClearFlag_CC4
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
+  * @rmtoll SR           CC4IF         LL_TIM_IsActiveFlag_CC4
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 5 interrupt flag (CC5F).
+  * @rmtoll SR           CC5IF         LL_TIM_ClearFlag_CC5
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
+  * @rmtoll SR           CC5IF         LL_TIM_IsActiveFlag_CC5
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 6 interrupt flag (CC6F).
+  * @rmtoll SR           CC6IF         LL_TIM_ClearFlag_CC6
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
+  * @rmtoll SR           CC6IF         LL_TIM_IsActiveFlag_CC6
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the commutation interrupt flag (COMIF).
+  * @rmtoll SR           COMIF         LL_TIM_ClearFlag_COM
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
+}
+
+/**
+  * @brief  Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
+  * @rmtoll SR           COMIF         LL_TIM_IsActiveFlag_COM
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the trigger interrupt flag (TIF).
+  * @rmtoll SR           TIF           LL_TIM_ClearFlag_TRIG
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
+}
+
+/**
+  * @brief  Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
+  * @rmtoll SR           TIF           LL_TIM_IsActiveFlag_TRIG
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the break interrupt flag (BIF).
+  * @rmtoll SR           BIF           LL_TIM_ClearFlag_BRK
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
+}
+
+/**
+  * @brief  Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
+  * @rmtoll SR           BIF           LL_TIM_IsActiveFlag_BRK
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the break 2 interrupt flag (B2IF).
+  * @rmtoll SR           B2IF          LL_TIM_ClearFlag_BRK2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF));
+}
+
+/**
+  * @brief  Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
+  * @rmtoll SR           B2IF          LL_TIM_IsActiveFlag_BRK2
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
+  * @rmtoll SR           CC1OF         LL_TIM_ClearFlag_CC1OVR
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set
+  *         (Capture/Compare 1 interrupt is pending).
+  * @rmtoll SR           CC1OF         LL_TIM_IsActiveFlag_CC1OVR
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
+  * @rmtoll SR           CC2OF         LL_TIM_ClearFlag_CC2OVR
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set
+  *         (Capture/Compare 2 over-capture interrupt is pending).
+  * @rmtoll SR           CC2OF         LL_TIM_IsActiveFlag_CC2OVR
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
+  * @rmtoll SR           CC3OF         LL_TIM_ClearFlag_CC3OVR
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set
+  *         (Capture/Compare 3 over-capture interrupt is pending).
+  * @rmtoll SR           CC3OF         LL_TIM_IsActiveFlag_CC3OVR
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
+  * @rmtoll SR           CC4OF         LL_TIM_ClearFlag_CC4OVR
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set
+  *         (Capture/Compare 4 over-capture interrupt is pending).
+  * @rmtoll SR           CC4OF         LL_TIM_IsActiveFlag_CC4OVR
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the system break interrupt flag (SBIF).
+  * @rmtoll SR           SBIF          LL_TIM_ClearFlag_SYSBRK
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF));
+}
+
+/**
+  * @brief  Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).
+  * @rmtoll SR           SBIF          LL_TIM_IsActiveFlag_SYSBRK
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_IT_Management IT-Management
+  * @{
+  */
+/**
+  * @brief  Enable update interrupt (UIE).
+  * @rmtoll DIER         UIE           LL_TIM_EnableIT_UPDATE
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_UIE);
+}
+
+/**
+  * @brief  Disable update interrupt (UIE).
+  * @rmtoll DIER         UIE           LL_TIM_DisableIT_UPDATE
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
+}
+
+/**
+  * @brief  Indicates whether the update interrupt (UIE) is enabled.
+  * @rmtoll DIER         UIE           LL_TIM_IsEnabledIT_UPDATE
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable capture/compare 1 interrupt (CC1IE).
+  * @rmtoll DIER         CC1IE         LL_TIM_EnableIT_CC1
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
+}
+
+/**
+  * @brief  Disable capture/compare 1  interrupt (CC1IE).
+  * @rmtoll DIER         CC1IE         LL_TIM_DisableIT_CC1
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
+  * @rmtoll DIER         CC1IE         LL_TIM_IsEnabledIT_CC1
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable capture/compare 2 interrupt (CC2IE).
+  * @rmtoll DIER         CC2IE         LL_TIM_EnableIT_CC2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
+}
+
+/**
+  * @brief  Disable capture/compare 2  interrupt (CC2IE).
+  * @rmtoll DIER         CC2IE         LL_TIM_DisableIT_CC2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
+  * @rmtoll DIER         CC2IE         LL_TIM_IsEnabledIT_CC2
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable capture/compare 3 interrupt (CC3IE).
+  * @rmtoll DIER         CC3IE         LL_TIM_EnableIT_CC3
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
+}
+
+/**
+  * @brief  Disable capture/compare 3  interrupt (CC3IE).
+  * @rmtoll DIER         CC3IE         LL_TIM_DisableIT_CC3
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
+  * @rmtoll DIER         CC3IE         LL_TIM_IsEnabledIT_CC3
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable capture/compare 4 interrupt (CC4IE).
+  * @rmtoll DIER         CC4IE         LL_TIM_EnableIT_CC4
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
+}
+
+/**
+  * @brief  Disable capture/compare 4  interrupt (CC4IE).
+  * @rmtoll DIER         CC4IE         LL_TIM_DisableIT_CC4
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
+  * @rmtoll DIER         CC4IE         LL_TIM_IsEnabledIT_CC4
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable commutation interrupt (COMIE).
+  * @rmtoll DIER         COMIE         LL_TIM_EnableIT_COM
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
+}
+
+/**
+  * @brief  Disable commutation interrupt (COMIE).
+  * @rmtoll DIER         COMIE         LL_TIM_DisableIT_COM
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
+}
+
+/**
+  * @brief  Indicates whether the commutation interrupt (COMIE) is enabled.
+  * @rmtoll DIER         COMIE         LL_TIM_IsEnabledIT_COM
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable trigger interrupt (TIE).
+  * @rmtoll DIER         TIE           LL_TIM_EnableIT_TRIG
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_TIE);
+}
+
+/**
+  * @brief  Disable trigger interrupt (TIE).
+  * @rmtoll DIER         TIE           LL_TIM_DisableIT_TRIG
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
+}
+
+/**
+  * @brief  Indicates whether the trigger interrupt (TIE) is enabled.
+  * @rmtoll DIER         TIE           LL_TIM_IsEnabledIT_TRIG
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable break interrupt (BIE).
+  * @rmtoll DIER         BIE           LL_TIM_EnableIT_BRK
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_BIE);
+}
+
+/**
+  * @brief  Disable break interrupt (BIE).
+  * @rmtoll DIER         BIE           LL_TIM_DisableIT_BRK
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
+}
+
+/**
+  * @brief  Indicates whether the break interrupt (BIE) is enabled.
+  * @rmtoll DIER         BIE           LL_TIM_IsEnabledIT_BRK
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_DMA_Management DMA Management
+  * @{
+  */
+/**
+  * @brief  Enable update DMA request (UDE).
+  * @rmtoll DIER         UDE           LL_TIM_EnableDMAReq_UPDATE
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_UDE);
+}
+
+/**
+  * @brief  Disable update DMA request (UDE).
+  * @rmtoll DIER         UDE           LL_TIM_DisableDMAReq_UPDATE
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
+}
+
+/**
+  * @brief  Indicates whether the update DMA request  (UDE) is enabled.
+  * @rmtoll DIER         UDE           LL_TIM_IsEnabledDMAReq_UPDATE
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable capture/compare 1 DMA request (CC1DE).
+  * @rmtoll DIER         CC1DE         LL_TIM_EnableDMAReq_CC1
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
+}
+
+/**
+  * @brief  Disable capture/compare 1  DMA request (CC1DE).
+  * @rmtoll DIER         CC1DE         LL_TIM_DisableDMAReq_CC1
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
+  * @rmtoll DIER         CC1DE         LL_TIM_IsEnabledDMAReq_CC1
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable capture/compare 2 DMA request (CC2DE).
+  * @rmtoll DIER         CC2DE         LL_TIM_EnableDMAReq_CC2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
+}
+
+/**
+  * @brief  Disable capture/compare 2  DMA request (CC2DE).
+  * @rmtoll DIER         CC2DE         LL_TIM_DisableDMAReq_CC2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
+  * @rmtoll DIER         CC2DE         LL_TIM_IsEnabledDMAReq_CC2
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable capture/compare 3 DMA request (CC3DE).
+  * @rmtoll DIER         CC3DE         LL_TIM_EnableDMAReq_CC3
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
+}
+
+/**
+  * @brief  Disable capture/compare 3  DMA request (CC3DE).
+  * @rmtoll DIER         CC3DE         LL_TIM_DisableDMAReq_CC3
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
+  * @rmtoll DIER         CC3DE         LL_TIM_IsEnabledDMAReq_CC3
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable capture/compare 4 DMA request (CC4DE).
+  * @rmtoll DIER         CC4DE         LL_TIM_EnableDMAReq_CC4
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
+}
+
+/**
+  * @brief  Disable capture/compare 4  DMA request (CC4DE).
+  * @rmtoll DIER         CC4DE         LL_TIM_DisableDMAReq_CC4
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
+  * @rmtoll DIER         CC4DE         LL_TIM_IsEnabledDMAReq_CC4
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable commutation DMA request (COMDE).
+  * @rmtoll DIER         COMDE         LL_TIM_EnableDMAReq_COM
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
+}
+
+/**
+  * @brief  Disable commutation DMA request (COMDE).
+  * @rmtoll DIER         COMDE         LL_TIM_DisableDMAReq_COM
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
+}
+
+/**
+  * @brief  Indicates whether the commutation DMA request (COMDE) is enabled.
+  * @rmtoll DIER         COMDE         LL_TIM_IsEnabledDMAReq_COM
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable trigger interrupt (TDE).
+  * @rmtoll DIER         TDE           LL_TIM_EnableDMAReq_TRIG
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_TDE);
+}
+
+/**
+  * @brief  Disable trigger interrupt (TDE).
+  * @rmtoll DIER         TDE           LL_TIM_DisableDMAReq_TRIG
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
+}
+
+/**
+  * @brief  Indicates whether the trigger interrupt (TDE) is enabled.
+  * @rmtoll DIER         TDE           LL_TIM_IsEnabledDMAReq_TRIG
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
+  * @{
+  */
+/**
+  * @brief  Generate an update event.
+  * @rmtoll EGR          UG            LL_TIM_GenerateEvent_UPDATE
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_UG);
+}
+
+/**
+  * @brief  Generate Capture/Compare 1 event.
+  * @rmtoll EGR          CC1G          LL_TIM_GenerateEvent_CC1
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
+}
+
+/**
+  * @brief  Generate Capture/Compare 2 event.
+  * @rmtoll EGR          CC2G          LL_TIM_GenerateEvent_CC2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
+}
+
+/**
+  * @brief  Generate Capture/Compare 3 event.
+  * @rmtoll EGR          CC3G          LL_TIM_GenerateEvent_CC3
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
+}
+
+/**
+  * @brief  Generate Capture/Compare 4 event.
+  * @rmtoll EGR          CC4G          LL_TIM_GenerateEvent_CC4
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
+}
+
+/**
+  * @brief  Generate commutation event.
+  * @rmtoll EGR          COMG          LL_TIM_GenerateEvent_COM
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_COMG);
+}
+
+/**
+  * @brief  Generate trigger event.
+  * @rmtoll EGR          TG            LL_TIM_GenerateEvent_TRIG
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_TG);
+}
+
+/**
+  * @brief  Generate break event.
+  * @rmtoll EGR          BG            LL_TIM_GenerateEvent_BRK
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_BG);
+}
+
+/**
+  * @brief  Generate break 2 event.
+  * @rmtoll EGR          B2G           LL_TIM_GenerateEvent_BRK2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_B2G);
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
+  * @{
+  */
+
+ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
+void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
+ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct);
+void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
+ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
+void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
+ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
+void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
+ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
+void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
+ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
+void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
+ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM12 || TIM13 ||TIM14 || TIM15 || TIM16 || TIM17  || TIM23  || TIM24 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32H7xx_LL_TIM_H */
diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usart.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usart.h
index 5ff3e38e..0e7bff81 100644
--- a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usart.h
+++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usart.h
@@ -1,4401 +1,4401 @@
-/**
-  ******************************************************************************
-  * @file    stm32h7xx_ll_usart.h
-  * @author  MCD Application Team
-  * @brief   Header file of USART LL module.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32H7xx_LL_USART_H
-#define STM32H7xx_LL_USART_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx.h"
-
-/** @addtogroup STM32H7xx_LL_Driver
-  * @{
-  */
-
-#if defined (USART1) || defined (USART2) || defined (USART3) || defined (USART6) || defined (UART4) || defined (UART5) || defined (UART7) || defined (UART8) || defined (UART9) || defined (USART10)
-
-/** @defgroup USART_LL USART
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup USART_LL_Private_Variables USART Private Variables
-  * @{
-  */
-/* Array used to get the USART prescaler division decimal values versus @ref USART_LL_EC_PRESCALER values */
-static const uint32_t USART_PRESCALER_TAB[] =
-{
-  1UL,
-  2UL,
-  4UL,
-  6UL,
-  8UL,
-  10UL,
-  12UL,
-  16UL,
-  32UL,
-  64UL,
-  128UL,
-  256UL
-};
-/**
-  * @}
-  */
-
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup USART_LL_Private_Macros USART Private Macros
-  * @{
-  */
-/**
-  * @}
-  */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup USART_LL_ES_INIT USART Exported Init structures
-  * @{
-  */
-
-/**
-  * @brief LL USART Init Structure definition
-  */
-typedef struct
-{
-  uint32_t PrescalerValue;            /*!< Specifies the Prescaler to compute the communication baud rate.
-                                           This parameter can be a value of @ref USART_LL_EC_PRESCALER.
-
-                                           This feature can be modified afterwards using unitary
-                                           function @ref LL_USART_SetPrescaler().*/
-
-  uint32_t BaudRate;                  /*!< This field defines expected Usart communication baud rate.
-
-                                           This feature can be modified afterwards using unitary
-                                           function @ref LL_USART_SetBaudRate().*/
-
-  uint32_t DataWidth;                 /*!< Specifies the number of data bits transmitted or received in a frame.
-                                           This parameter can be a value of @ref USART_LL_EC_DATAWIDTH.
-
-                                           This feature can be modified afterwards using unitary
-                                           function @ref LL_USART_SetDataWidth().*/
-
-  uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
-                                           This parameter can be a value of @ref USART_LL_EC_STOPBITS.
-
-                                           This feature can be modified afterwards using unitary
-                                           function @ref LL_USART_SetStopBitsLength().*/
-
-  uint32_t Parity;                    /*!< Specifies the parity mode.
-                                           This parameter can be a value of @ref USART_LL_EC_PARITY.
-
-                                           This feature can be modified afterwards using unitary
-                                           function @ref LL_USART_SetParity().*/
-
-  uint32_t TransferDirection;         /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
-                                           This parameter can be a value of @ref USART_LL_EC_DIRECTION.
-
-                                           This feature can be modified afterwards using unitary
-                                           function @ref LL_USART_SetTransferDirection().*/
-
-  uint32_t HardwareFlowControl;       /*!< Specifies whether the hardware flow control mode is enabled or disabled.
-                                           This parameter can be a value of @ref USART_LL_EC_HWCONTROL.
-
-                                           This feature can be modified afterwards using unitary
-                                           function @ref LL_USART_SetHWFlowCtrl().*/
-
-  uint32_t OverSampling;              /*!< Specifies whether USART oversampling mode is 16 or 8.
-                                           This parameter can be a value of @ref USART_LL_EC_OVERSAMPLING.
-
-                                           This feature can be modified afterwards using unitary
-                                           function @ref LL_USART_SetOverSampling().*/
-
-} LL_USART_InitTypeDef;
-
-/**
-  * @brief LL USART Clock Init Structure definition
-  */
-typedef struct
-{
-  uint32_t ClockOutput;               /*!< Specifies whether the USART clock is enabled or disabled.
-                                           This parameter can be a value of @ref USART_LL_EC_CLOCK.
-
-                                           USART HW configuration can be modified afterwards using unitary functions
-                                           @ref LL_USART_EnableSCLKOutput() or @ref LL_USART_DisableSCLKOutput().
-                                           For more details, refer to description of this function. */
-
-  uint32_t ClockPolarity;             /*!< Specifies the steady state of the serial clock.
-                                           This parameter can be a value of @ref USART_LL_EC_POLARITY.
-
-                                           USART HW configuration can be modified afterwards using unitary
-                                           functions @ref LL_USART_SetClockPolarity().
-                                           For more details, refer to description of this function. */
-
-  uint32_t ClockPhase;                /*!< Specifies the clock transition on which the bit capture is made.
-                                           This parameter can be a value of @ref USART_LL_EC_PHASE.
-
-                                           USART HW configuration can be modified afterwards using unitary
-                                           functions @ref LL_USART_SetClockPhase().
-                                           For more details, refer to description of this function. */
-
-  uint32_t LastBitClockPulse;         /*!< Specifies whether the clock pulse corresponding to the last transmitted
-                                           data bit (MSB) has to be output on the SCLK pin in synchronous mode.
-                                           This parameter can be a value of @ref USART_LL_EC_LASTCLKPULSE.
-
-                                           USART HW configuration can be modified afterwards using unitary
-                                           functions @ref LL_USART_SetLastClkPulseOutput().
-                                           For more details, refer to description of this function. */
-
-} LL_USART_ClockInitTypeDef;
-
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup USART_LL_Exported_Constants USART Exported Constants
-  * @{
-  */
-
-/** @defgroup USART_LL_EC_CLEAR_FLAG Clear Flags Defines
-  * @brief    Flags defines which can be used with LL_USART_WriteReg function
-  * @{
-  */
-#define LL_USART_ICR_PECF                       USART_ICR_PECF                /*!< Parity error clear flag */
-#define LL_USART_ICR_FECF                       USART_ICR_FECF                /*!< Framing error clear flag */
-#define LL_USART_ICR_NECF                       USART_ICR_NECF                /*!< Noise error detected clear flag */
-#define LL_USART_ICR_ORECF                      USART_ICR_ORECF               /*!< Overrun error clear flag */
-#define LL_USART_ICR_IDLECF                     USART_ICR_IDLECF              /*!< Idle line detected clear flag */
-#define LL_USART_ICR_TXFECF                     USART_ICR_TXFECF              /*!< TX FIFO Empty clear flag */
-#define LL_USART_ICR_TCCF                       USART_ICR_TCCF                /*!< Transmission complete clear flag */
-#define LL_USART_ICR_TCBGTCF                    USART_ICR_TCBGTCF             /*!< Transmission completed before guard time clear flag */
-#define LL_USART_ICR_LBDCF                      USART_ICR_LBDCF               /*!< LIN break detection clear flag */
-#define LL_USART_ICR_CTSCF                      USART_ICR_CTSCF               /*!< CTS clear flag */
-#define LL_USART_ICR_RTOCF                      USART_ICR_RTOCF               /*!< Receiver timeout clear flag */
-#define LL_USART_ICR_EOBCF                      USART_ICR_EOBCF               /*!< End of block clear flag */
-#define LL_USART_ICR_UDRCF                      USART_ICR_UDRCF               /*!< SPI Slave Underrun clear flag */
-#define LL_USART_ICR_CMCF                       USART_ICR_CMCF                /*!< Character match clear flag */
-#define LL_USART_ICR_WUCF                       USART_ICR_WUCF                /*!< Wakeup from Stop mode clear flag */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_GET_FLAG Get Flags Defines
-  * @brief    Flags defines which can be used with LL_USART_ReadReg function
-  * @{
-  */
-#define LL_USART_ISR_PE                         USART_ISR_PE                  /*!< Parity error flag */
-#define LL_USART_ISR_FE                         USART_ISR_FE                  /*!< Framing error flag */
-#define LL_USART_ISR_NE                         USART_ISR_NE                  /*!< Noise detected flag */
-#define LL_USART_ISR_ORE                        USART_ISR_ORE                 /*!< Overrun error flag */
-#define LL_USART_ISR_IDLE                       USART_ISR_IDLE                /*!< Idle line detected flag */
-#define LL_USART_ISR_RXNE_RXFNE                 USART_ISR_RXNE_RXFNE          /*!< Read data register or RX FIFO not empty flag */
-#define LL_USART_ISR_TC                         USART_ISR_TC                  /*!< Transmission complete flag */
-#define LL_USART_ISR_TXE_TXFNF                  USART_ISR_TXE_TXFNF           /*!< Transmit data register empty or TX FIFO Not Full flag*/
-#define LL_USART_ISR_LBDF                       USART_ISR_LBDF                /*!< LIN break detection flag */
-#define LL_USART_ISR_CTSIF                      USART_ISR_CTSIF               /*!< CTS interrupt flag */
-#define LL_USART_ISR_CTS                        USART_ISR_CTS                 /*!< CTS flag */
-#define LL_USART_ISR_RTOF                       USART_ISR_RTOF                /*!< Receiver timeout flag */
-#define LL_USART_ISR_EOBF                       USART_ISR_EOBF                /*!< End of block flag */
-#define LL_USART_ISR_UDR                        USART_ISR_UDR                 /*!< SPI Slave underrun error flag */
-#define LL_USART_ISR_ABRE                       USART_ISR_ABRE                /*!< Auto baud rate error flag */
-#define LL_USART_ISR_ABRF                       USART_ISR_ABRF                /*!< Auto baud rate flag */
-#define LL_USART_ISR_BUSY                       USART_ISR_BUSY                /*!< Busy flag */
-#define LL_USART_ISR_CMF                        USART_ISR_CMF                 /*!< Character match flag */
-#define LL_USART_ISR_SBKF                       USART_ISR_SBKF                /*!< Send break flag */
-#define LL_USART_ISR_RWU                        USART_ISR_RWU                 /*!< Receiver wakeup from Mute mode flag */
-#define LL_USART_ISR_WUF                        USART_ISR_WUF                 /*!< Wakeup from Stop mode flag */
-#define LL_USART_ISR_TEACK                      USART_ISR_TEACK               /*!< Transmit enable acknowledge flag */
-#define LL_USART_ISR_REACK                      USART_ISR_REACK               /*!< Receive enable acknowledge flag */
-#define LL_USART_ISR_TXFE                       USART_ISR_TXFE                /*!< TX FIFO empty flag */
-#define LL_USART_ISR_RXFF                       USART_ISR_RXFF                /*!< RX FIFO full flag */
-#define LL_USART_ISR_TCBGT                      USART_ISR_TCBGT               /*!< Transmission complete before guard time completion flag */
-#define LL_USART_ISR_RXFT                       USART_ISR_RXFT                /*!< RX FIFO threshold flag */
-#define LL_USART_ISR_TXFT                       USART_ISR_TXFT                /*!< TX FIFO threshold flag */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_IT IT Defines
-  * @brief    IT defines which can be used with LL_USART_ReadReg and  LL_USART_WriteReg functions
-  * @{
-  */
-#define LL_USART_CR1_IDLEIE                     USART_CR1_IDLEIE              /*!< IDLE interrupt enable */
-#define LL_USART_CR1_RXNEIE_RXFNEIE             USART_CR1_RXNEIE_RXFNEIE      /*!< Read data register and RXFIFO not empty interrupt enable */
-#define LL_USART_CR1_TCIE                       USART_CR1_TCIE                /*!< Transmission complete interrupt enable */
-#define LL_USART_CR1_TXEIE_TXFNFIE              USART_CR1_TXEIE_TXFNFIE       /*!< Transmit data register empty and TX FIFO not full interrupt enable */
-#define LL_USART_CR1_PEIE                       USART_CR1_PEIE                /*!< Parity error */
-#define LL_USART_CR1_CMIE                       USART_CR1_CMIE                /*!< Character match interrupt enable */
-#define LL_USART_CR1_RTOIE                      USART_CR1_RTOIE               /*!< Receiver timeout interrupt enable */
-#define LL_USART_CR1_EOBIE                      USART_CR1_EOBIE               /*!< End of Block interrupt enable */
-#define LL_USART_CR1_TXFEIE                     USART_CR1_TXFEIE              /*!< TX FIFO empty interrupt enable */
-#define LL_USART_CR1_RXFFIE                     USART_CR1_RXFFIE              /*!< RX FIFO full interrupt enable */
-#define LL_USART_CR2_LBDIE                      USART_CR2_LBDIE               /*!< LIN break detection interrupt enable */
-#define LL_USART_CR3_EIE                        USART_CR3_EIE                 /*!< Error interrupt enable */
-#define LL_USART_CR3_CTSIE                      USART_CR3_CTSIE               /*!< CTS interrupt enable */
-#define LL_USART_CR3_WUFIE                      USART_CR3_WUFIE               /*!< Wakeup from Stop mode interrupt enable */
-#define LL_USART_CR3_TXFTIE                     USART_CR3_TXFTIE              /*!< TX FIFO threshold interrupt enable */
-#define LL_USART_CR3_TCBGTIE                    USART_CR3_TCBGTIE             /*!< Transmission complete before guard time interrupt enable */
-#define LL_USART_CR3_RXFTIE                     USART_CR3_RXFTIE              /*!< RX FIFO threshold interrupt enable */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_FIFOTHRESHOLD FIFO Threshold
-  * @{
-  */
-#define LL_USART_FIFOTHRESHOLD_1_8              0x00000000U /*!< FIFO reaches 1/8 of its depth */
-#define LL_USART_FIFOTHRESHOLD_1_4              0x00000001U /*!< FIFO reaches 1/4 of its depth */
-#define LL_USART_FIFOTHRESHOLD_1_2              0x00000002U /*!< FIFO reaches 1/2 of its depth */
-#define LL_USART_FIFOTHRESHOLD_3_4              0x00000003U /*!< FIFO reaches 3/4 of its depth */
-#define LL_USART_FIFOTHRESHOLD_7_8              0x00000004U /*!< FIFO reaches 7/8 of its depth */
-#define LL_USART_FIFOTHRESHOLD_8_8              0x00000005U /*!< FIFO becomes empty for TX and full for RX */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_DIRECTION Communication Direction
-  * @{
-  */
-#define LL_USART_DIRECTION_NONE                 0x00000000U                        /*!< Transmitter and Receiver are disabled */
-#define LL_USART_DIRECTION_RX                   USART_CR1_RE                       /*!< Transmitter is disabled and Receiver is enabled */
-#define LL_USART_DIRECTION_TX                   USART_CR1_TE                       /*!< Transmitter is enabled and Receiver is disabled */
-#define LL_USART_DIRECTION_TX_RX                (USART_CR1_TE |USART_CR1_RE)       /*!< Transmitter and Receiver are enabled */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_PARITY Parity Control
-  * @{
-  */
-#define LL_USART_PARITY_NONE                    0x00000000U                          /*!< Parity control disabled */
-#define LL_USART_PARITY_EVEN                    USART_CR1_PCE                        /*!< Parity control enabled and Even Parity is selected */
-#define LL_USART_PARITY_ODD                     (USART_CR1_PCE | USART_CR1_PS)       /*!< Parity control enabled and Odd Parity is selected */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_WAKEUP Wakeup
-  * @{
-  */
-#define LL_USART_WAKEUP_IDLELINE                0x00000000U           /*!<  USART wake up from Mute mode on Idle Line */
-#define LL_USART_WAKEUP_ADDRESSMARK             USART_CR1_WAKE        /*!<  USART wake up from Mute mode on Address Mark */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_DATAWIDTH Datawidth
-  * @{
-  */
-#define LL_USART_DATAWIDTH_7B                   USART_CR1_M1            /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */
-#define LL_USART_DATAWIDTH_8B                   0x00000000U             /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
-#define LL_USART_DATAWIDTH_9B                   USART_CR1_M0            /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_OVERSAMPLING Oversampling
-  * @{
-  */
-#define LL_USART_OVERSAMPLING_16                0x00000000U            /*!< Oversampling by 16 */
-#define LL_USART_OVERSAMPLING_8                 USART_CR1_OVER8        /*!< Oversampling by 8 */
-/**
-  * @}
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup USART_LL_EC_CLOCK Clock Signal
-  * @{
-  */
-
-#define LL_USART_CLOCK_DISABLE                  0x00000000U            /*!< Clock signal not provided */
-#define LL_USART_CLOCK_ENABLE                   USART_CR2_CLKEN        /*!< Clock signal provided */
-/**
-  * @}
-  */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse
-  * @{
-  */
-#define LL_USART_LASTCLKPULSE_NO_OUTPUT         0x00000000U           /*!< The clock pulse of the last data bit is not output to the SCLK pin */
-#define LL_USART_LASTCLKPULSE_OUTPUT            USART_CR2_LBCL        /*!< The clock pulse of the last data bit is output to the SCLK pin */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_PHASE Clock Phase
-  * @{
-  */
-#define LL_USART_PHASE_1EDGE                    0x00000000U           /*!< The first clock transition is the first data capture edge */
-#define LL_USART_PHASE_2EDGE                    USART_CR2_CPHA        /*!< The second clock transition is the first data capture edge */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_POLARITY Clock Polarity
-  * @{
-  */
-#define LL_USART_POLARITY_LOW                   0x00000000U           /*!< Steady low value on SCLK pin outside transmission window*/
-#define LL_USART_POLARITY_HIGH                  USART_CR2_CPOL        /*!< Steady high value on SCLK pin outside transmission window */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_PRESCALER Clock Source Prescaler
-  * @{
-  */
-#define LL_USART_PRESCALER_DIV1                 0x00000000U                                                                   /*!< Input clock not divided   */
-#define LL_USART_PRESCALER_DIV2                 (USART_PRESC_PRESCALER_0)                                                     /*!< Input clock divided by 2  */
-#define LL_USART_PRESCALER_DIV4                 (USART_PRESC_PRESCALER_1)                                                     /*!< Input clock divided by 4  */
-#define LL_USART_PRESCALER_DIV6                 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)                           /*!< Input clock divided by 6  */
-#define LL_USART_PRESCALER_DIV8                 (USART_PRESC_PRESCALER_2)                                                     /*!< Input clock divided by 8  */
-#define LL_USART_PRESCALER_DIV10                (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0)                           /*!< Input clock divided by 10 */
-#define LL_USART_PRESCALER_DIV12                (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1)                           /*!< Input clock divided by 12 */
-#define LL_USART_PRESCALER_DIV16                (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 16 */
-#define LL_USART_PRESCALER_DIV32                (USART_PRESC_PRESCALER_3)                                                     /*!< Input clock divided by 32 */
-#define LL_USART_PRESCALER_DIV64                (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0)                           /*!< Input clock divided by 64 */
-#define LL_USART_PRESCALER_DIV128               (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1)                           /*!< Input clock divided by 128 */
-#define LL_USART_PRESCALER_DIV256               (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 256 */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_STOPBITS Stop Bits
-  * @{
-  */
-#define LL_USART_STOPBITS_0_5                   USART_CR2_STOP_0                           /*!< 0.5 stop bit */
-#define LL_USART_STOPBITS_1                     0x00000000U                                /*!< 1 stop bit */
-#define LL_USART_STOPBITS_1_5                   (USART_CR2_STOP_0 | USART_CR2_STOP_1)      /*!< 1.5 stop bits */
-#define LL_USART_STOPBITS_2                     USART_CR2_STOP_1                           /*!< 2 stop bits */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_TXRX TX RX Pins Swap
-  * @{
-  */
-#define LL_USART_TXRX_STANDARD                  0x00000000U           /*!< TX/RX pins are used as defined in standard pinout */
-#define LL_USART_TXRX_SWAPPED                   (USART_CR2_SWAP)      /*!< TX and RX pins functions are swapped.             */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion
-  * @{
-  */
-#define LL_USART_RXPIN_LEVEL_STANDARD           0x00000000U           /*!< RX pin signal works using the standard logic levels */
-#define LL_USART_RXPIN_LEVEL_INVERTED           (USART_CR2_RXINV)     /*!< RX pin signal values are inverted.                  */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion
-  * @{
-  */
-#define LL_USART_TXPIN_LEVEL_STANDARD           0x00000000U           /*!< TX pin signal works using the standard logic levels */
-#define LL_USART_TXPIN_LEVEL_INVERTED           (USART_CR2_TXINV)     /*!< TX pin signal values are inverted.                  */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_BINARY_LOGIC Binary Data Inversion
-  * @{
-  */
-#define LL_USART_BINARY_LOGIC_POSITIVE          0x00000000U           /*!< Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) */
-#define LL_USART_BINARY_LOGIC_NEGATIVE          USART_CR2_DATAINV     /*!< Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_BITORDER Bit Order
-  * @{
-  */
-#define LL_USART_BITORDER_LSBFIRST              0x00000000U           /*!< data is transmitted/received with data bit 0 first, following the start bit */
-#define LL_USART_BITORDER_MSBFIRST              USART_CR2_MSBFIRST    /*!< data is transmitted/received with the MSB first, following the start bit */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_AUTOBAUD_DETECT_ON Autobaud Detection
-  * @{
-  */
-#define LL_USART_AUTOBAUD_DETECT_ON_STARTBIT    0x00000000U                                 /*!< Measurement of the start bit is used to detect the baud rate */
-#define LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE USART_CR2_ABRMODE_0                         /*!< Falling edge to falling edge measurement. Received frame must start with a single bit = 1 -> Frame = Start10xxxxxx */
-#define LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME    USART_CR2_ABRMODE_1                         /*!< 0x7F frame detection */
-#define LL_USART_AUTOBAUD_DETECT_ON_55_FRAME    (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0) /*!< 0x55 frame detection */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_ADDRESS_DETECT Address Length Detection
-  * @{
-  */
-#define LL_USART_ADDRESS_DETECT_4B              0x00000000U           /*!< 4-bit address detection method selected */
-#define LL_USART_ADDRESS_DETECT_7B              USART_CR2_ADDM7       /*!< 7-bit address detection (in 8-bit data mode) method selected */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_HWCONTROL Hardware Control
-  * @{
-  */
-#define LL_USART_HWCONTROL_NONE                 0x00000000U                          /*!< CTS and RTS hardware flow control disabled */
-#define LL_USART_HWCONTROL_RTS                  USART_CR3_RTSE                       /*!< RTS output enabled, data is only requested when there is space in the receive buffer */
-#define LL_USART_HWCONTROL_CTS                  USART_CR3_CTSE                       /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */
-#define LL_USART_HWCONTROL_RTS_CTS              (USART_CR3_RTSE | USART_CR3_CTSE)    /*!< CTS and RTS hardware flow control enabled */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_WAKEUP_ON Wakeup Activation
-  * @{
-  */
-#define LL_USART_WAKEUP_ON_ADDRESS              0x00000000U                             /*!< Wake up active on address match */
-#define LL_USART_WAKEUP_ON_STARTBIT             USART_CR3_WUS_1                         /*!< Wake up active on Start bit detection */
-#define LL_USART_WAKEUP_ON_RXNE                 (USART_CR3_WUS_0 | USART_CR3_WUS_1)     /*!< Wake up active on RXNE */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_IRDA_POWER IrDA Power
-  * @{
-  */
-#define LL_USART_IRDA_POWER_NORMAL              0x00000000U           /*!< IrDA normal power mode */
-#define LL_USART_IRDA_POWER_LOW                 USART_CR3_IRLP        /*!< IrDA low power mode */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length
-  * @{
-  */
-#define LL_USART_LINBREAK_DETECT_10B            0x00000000U           /*!< 10-bit break detection method selected */
-#define LL_USART_LINBREAK_DETECT_11B            USART_CR2_LBDL        /*!< 11-bit break detection method selected */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_DE_POLARITY Driver Enable Polarity
-  * @{
-  */
-#define LL_USART_DE_POLARITY_HIGH               0x00000000U           /*!< DE signal is active high */
-#define LL_USART_DE_POLARITY_LOW                USART_CR3_DEP         /*!< DE signal is active low */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_DMA_REG_DATA DMA Register Data
-  * @{
-  */
-#define LL_USART_DMA_REG_DATA_TRANSMIT          0x00000000U          /*!< Get address of data register used for transmission */
-#define LL_USART_DMA_REG_DATA_RECEIVE           0x00000001U          /*!< Get address of data register used for reception */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup USART_LL_Exported_Macros USART Exported Macros
-  * @{
-  */
-
-/** @defgroup USART_LL_EM_WRITE_READ Common Write and read registers Macros
-  * @{
-  */
-
-/**
-  * @brief  Write a value in USART register
-  * @param  __INSTANCE__ USART Instance
-  * @param  __REG__ Register to be written
-  * @param  __VALUE__ Value to be written in the register
-  * @retval None
-  */
-#define LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
-  * @brief  Read a value in USART register
-  * @param  __INSTANCE__ USART Instance
-  * @param  __REG__ Register to be read
-  * @retval Register value
-  */
-#define LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
-  * @{
-  */
-
-/**
-  * @brief  Compute USARTDIV value according to Peripheral Clock and
-  *         expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned)
-  * @param  __PERIPHCLK__ Peripheral Clock frequency used for USART instance
-  * @param  __PRESCALER__ This parameter can be one of the following values:
-  *         @arg @ref LL_USART_PRESCALER_DIV1
-  *         @arg @ref LL_USART_PRESCALER_DIV2
-  *         @arg @ref LL_USART_PRESCALER_DIV4
-  *         @arg @ref LL_USART_PRESCALER_DIV6
-  *         @arg @ref LL_USART_PRESCALER_DIV8
-  *         @arg @ref LL_USART_PRESCALER_DIV10
-  *         @arg @ref LL_USART_PRESCALER_DIV12
-  *         @arg @ref LL_USART_PRESCALER_DIV16
-  *         @arg @ref LL_USART_PRESCALER_DIV32
-  *         @arg @ref LL_USART_PRESCALER_DIV64
-  *         @arg @ref LL_USART_PRESCALER_DIV128
-  *         @arg @ref LL_USART_PRESCALER_DIV256
-  * @param  __BAUDRATE__ Baud rate value to achieve
-  * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case
-  */
-#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) \
-  (((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))*2U)\
-    + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
-
-/**
-  * @brief  Compute USARTDIV value according to Peripheral Clock and
-  *         expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned)
-  * @param  __PERIPHCLK__ Peripheral Clock frequency used for USART instance
-  * @param  __PRESCALER__ This parameter can be one of the following values:
-  *         @arg @ref LL_USART_PRESCALER_DIV1
-  *         @arg @ref LL_USART_PRESCALER_DIV2
-  *         @arg @ref LL_USART_PRESCALER_DIV4
-  *         @arg @ref LL_USART_PRESCALER_DIV6
-  *         @arg @ref LL_USART_PRESCALER_DIV8
-  *         @arg @ref LL_USART_PRESCALER_DIV10
-  *         @arg @ref LL_USART_PRESCALER_DIV12
-  *         @arg @ref LL_USART_PRESCALER_DIV16
-  *         @arg @ref LL_USART_PRESCALER_DIV32
-  *         @arg @ref LL_USART_PRESCALER_DIV64
-  *         @arg @ref LL_USART_PRESCALER_DIV128
-  *         @arg @ref LL_USART_PRESCALER_DIV256
-  * @param  __BAUDRATE__ Baud rate value to achieve
-  * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case
-  */
-#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) \
-  ((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))\
-    + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup USART_LL_Exported_Functions USART Exported Functions
-  * @{
-  */
-
-/** @defgroup USART_LL_EF_Configuration Configuration functions
-  * @{
-  */
-
-/**
-  * @brief  USART Enable
-  * @rmtoll CR1          UE            LL_USART_Enable
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_Enable(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR1, USART_CR1_UE);
-}
-
-/**
-  * @brief  USART Disable (all USART prescalers and outputs are disabled)
-  * @note   When USART is disabled, USART prescalers and outputs are stopped immediately,
-  *         and current operations are discarded. The configuration of the USART is kept, but all the status
-  *         flags, in the USARTx_ISR are set to their default values.
-  * @rmtoll CR1          UE            LL_USART_Disable
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR1, USART_CR1_UE);
-}
-
-/**
-  * @brief  Indicate if USART is enabled
-  * @rmtoll CR1          UE            LL_USART_IsEnabled
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabled(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  FIFO Mode Enable
-  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
-  *         FIFO mode feature is supported by the USARTx instance.
-  * @rmtoll CR1          FIFOEN        LL_USART_EnableFIFO
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableFIFO(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR1, USART_CR1_FIFOEN);
-}
-
-/**
-  * @brief  FIFO Mode Disable
-  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
-  *         FIFO mode feature is supported by the USARTx instance.
-  * @rmtoll CR1          FIFOEN        LL_USART_DisableFIFO
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableFIFO(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR1, USART_CR1_FIFOEN);
-}
-
-/**
-  * @brief  Indicate if FIFO Mode is enabled
-  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
-  *         FIFO mode feature is supported by the USARTx instance.
-  * @rmtoll CR1          FIFOEN        LL_USART_IsEnabledFIFO
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledFIFO(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Configure TX FIFO Threshold
-  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
-  *         FIFO mode feature is supported by the USARTx instance.
-  * @rmtoll CR3          TXFTCFG       LL_USART_SetTXFIFOThreshold
-  * @param  USARTx USART Instance
-  * @param  Threshold This parameter can be one of the following values:
-  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
-  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
-  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
-  *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
-  *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
-  *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetTXFIFOThreshold(USART_TypeDef *USARTx, uint32_t Threshold)
-{
-  ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos);
-}
-
-/**
-  * @brief  Return TX FIFO Threshold Configuration
-  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
-  *         FIFO mode feature is supported by the USARTx instance.
-  * @rmtoll CR3          TXFTCFG       LL_USART_GetTXFIFOThreshold
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
-  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
-  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
-  *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
-  *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
-  *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
-  */
-__STATIC_INLINE uint32_t LL_USART_GetTXFIFOThreshold(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
-}
-
-/**
-  * @brief  Configure RX FIFO Threshold
-  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
-  *         FIFO mode feature is supported by the USARTx instance.
-  * @rmtoll CR3          RXFTCFG       LL_USART_SetRXFIFOThreshold
-  * @param  USARTx USART Instance
-  * @param  Threshold This parameter can be one of the following values:
-  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
-  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
-  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
-  *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
-  *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
-  *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetRXFIFOThreshold(USART_TypeDef *USARTx, uint32_t Threshold)
-{
-  ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos);
-}
-
-/**
-  * @brief  Return RX FIFO Threshold Configuration
-  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
-  *         FIFO mode feature is supported by the USARTx instance.
-  * @rmtoll CR3          RXFTCFG       LL_USART_GetRXFIFOThreshold
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
-  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
-  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
-  *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
-  *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
-  *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
-  */
-__STATIC_INLINE uint32_t LL_USART_GetRXFIFOThreshold(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
-}
-
-/**
-  * @brief  Configure TX and RX FIFOs Threshold
-  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
-  *         FIFO mode feature is supported by the USARTx instance.
-  * @rmtoll CR3          TXFTCFG       LL_USART_ConfigFIFOsThreshold\n
-  *         CR3          RXFTCFG       LL_USART_ConfigFIFOsThreshold
-  * @param  USARTx USART Instance
-  * @param  TXThreshold This parameter can be one of the following values:
-  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
-  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
-  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
-  *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
-  *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
-  *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
-  * @param  RXThreshold This parameter can be one of the following values:
-  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
-  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
-  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
-  *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
-  *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
-  *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ConfigFIFOsThreshold(USART_TypeDef *USARTx, uint32_t TXThreshold, uint32_t RXThreshold)
-{
-  ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) |
-                    (RXThreshold << USART_CR3_RXFTCFG_Pos));
-}
-
-/**
-  * @brief  USART enabled in STOP Mode.
-  * @note   When this function is enabled, USART is able to wake up the MCU from Stop mode, provided that
-  *         USART clock selection is HSI or LSE in RCC.
-  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
-  *         Wake-up from Stop mode feature is supported by the USARTx instance.
-  * @rmtoll CR1          UESM          LL_USART_EnableInStopMode
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableInStopMode(USART_TypeDef *USARTx)
-{
-  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_UESM);
-}
-
-/**
-  * @brief  USART disabled in STOP Mode.
-  * @note   When this function is disabled, USART is not able to wake up the MCU from Stop mode
-  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
-  *         Wake-up from Stop mode feature is supported by the USARTx instance.
-  * @rmtoll CR1          UESM          LL_USART_DisableInStopMode
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx)
-{
-  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_UESM);
-}
-
-/**
-  * @brief  Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not)
-  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
-  *         Wake-up from Stop mode feature is supported by the USARTx instance.
-  * @rmtoll CR1          UESM          LL_USART_IsEnabledInStopMode
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Receiver Enable (Receiver is enabled and begins searching for a start bit)
-  * @rmtoll CR1          RE            LL_USART_EnableDirectionRx
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx)
-{
-  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RE);
-}
-
-/**
-  * @brief  Receiver Disable
-  * @rmtoll CR1          RE            LL_USART_DisableDirectionRx
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx)
-{
-  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RE);
-}
-
-/**
-  * @brief  Transmitter Enable
-  * @rmtoll CR1          TE            LL_USART_EnableDirectionTx
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx)
-{
-  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TE);
-}
-
-/**
-  * @brief  Transmitter Disable
-  * @rmtoll CR1          TE            LL_USART_DisableDirectionTx
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx)
-{
-  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TE);
-}
-
-/**
-  * @brief  Configure simultaneously enabled/disabled states
-  *         of Transmitter and Receiver
-  * @rmtoll CR1          RE            LL_USART_SetTransferDirection\n
-  *         CR1          TE            LL_USART_SetTransferDirection
-  * @param  USARTx USART Instance
-  * @param  TransferDirection This parameter can be one of the following values:
-  *         @arg @ref LL_USART_DIRECTION_NONE
-  *         @arg @ref LL_USART_DIRECTION_RX
-  *         @arg @ref LL_USART_DIRECTION_TX
-  *         @arg @ref LL_USART_DIRECTION_TX_RX
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirection)
-{
-  ATOMIC_MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
-}
-
-/**
-  * @brief  Return enabled/disabled states of Transmitter and Receiver
-  * @rmtoll CR1          RE            LL_USART_GetTransferDirection\n
-  *         CR1          TE            LL_USART_GetTransferDirection
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_DIRECTION_NONE
-  *         @arg @ref LL_USART_DIRECTION_RX
-  *         @arg @ref LL_USART_DIRECTION_TX
-  *         @arg @ref LL_USART_DIRECTION_TX_RX
-  */
-__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE));
-}
-
-/**
-  * @brief  Configure Parity (enabled/disabled and parity mode if enabled).
-  * @note   This function selects if hardware parity control (generation and detection) is enabled or disabled.
-  *         When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position
-  *         (9th or 8th bit depending on data width) and parity is checked on the received data.
-  * @rmtoll CR1          PS            LL_USART_SetParity\n
-  *         CR1          PCE           LL_USART_SetParity
-  * @param  USARTx USART Instance
-  * @param  Parity This parameter can be one of the following values:
-  *         @arg @ref LL_USART_PARITY_NONE
-  *         @arg @ref LL_USART_PARITY_EVEN
-  *         @arg @ref LL_USART_PARITY_ODD
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity)
-{
-  MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);
-}
-
-/**
-  * @brief  Return Parity configuration (enabled/disabled and parity mode if enabled)
-  * @rmtoll CR1          PS            LL_USART_GetParity\n
-  *         CR1          PCE           LL_USART_GetParity
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_PARITY_NONE
-  *         @arg @ref LL_USART_PARITY_EVEN
-  *         @arg @ref LL_USART_PARITY_ODD
-  */
-__STATIC_INLINE uint32_t LL_USART_GetParity(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
-}
-
-/**
-  * @brief  Set Receiver Wake Up method from Mute mode.
-  * @rmtoll CR1          WAKE          LL_USART_SetWakeUpMethod
-  * @param  USARTx USART Instance
-  * @param  Method This parameter can be one of the following values:
-  *         @arg @ref LL_USART_WAKEUP_IDLELINE
-  *         @arg @ref LL_USART_WAKEUP_ADDRESSMARK
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Method)
-{
-  MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method);
-}
-
-/**
-  * @brief  Return Receiver Wake Up method from Mute mode
-  * @rmtoll CR1          WAKE          LL_USART_GetWakeUpMethod
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_WAKEUP_IDLELINE
-  *         @arg @ref LL_USART_WAKEUP_ADDRESSMARK
-  */
-__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE));
-}
-
-/**
-  * @brief  Set Word length (i.e. nb of data bits, excluding start and stop bits)
-  * @rmtoll CR1          M0            LL_USART_SetDataWidth\n
-  *         CR1          M1            LL_USART_SetDataWidth
-  * @param  USARTx USART Instance
-  * @param  DataWidth This parameter can be one of the following values:
-  *         @arg @ref LL_USART_DATAWIDTH_7B
-  *         @arg @ref LL_USART_DATAWIDTH_8B
-  *         @arg @ref LL_USART_DATAWIDTH_9B
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataWidth)
-{
-  MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth);
-}
-
-/**
-  * @brief  Return Word length (i.e. nb of data bits, excluding start and stop bits)
-  * @rmtoll CR1          M0            LL_USART_GetDataWidth\n
-  *         CR1          M1            LL_USART_GetDataWidth
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_DATAWIDTH_7B
-  *         @arg @ref LL_USART_DATAWIDTH_8B
-  *         @arg @ref LL_USART_DATAWIDTH_9B
-  */
-__STATIC_INLINE uint32_t LL_USART_GetDataWidth(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M));
-}
-
-/**
-  * @brief  Allow switch between Mute Mode and Active mode
-  * @rmtoll CR1          MME           LL_USART_EnableMuteMode
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableMuteMode(USART_TypeDef *USARTx)
-{
-  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_MME);
-}
-
-/**
-  * @brief  Prevent Mute Mode use. Set Receiver in active mode permanently.
-  * @rmtoll CR1          MME           LL_USART_DisableMuteMode
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableMuteMode(USART_TypeDef *USARTx)
-{
-  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_MME);
-}
-
-/**
-  * @brief  Indicate if switch between Mute Mode and Active mode is allowed
-  * @rmtoll CR1          MME           LL_USART_IsEnabledMuteMode
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Set Oversampling to 8-bit or 16-bit mode
-  * @rmtoll CR1          OVER8         LL_USART_SetOverSampling
-  * @param  USARTx USART Instance
-  * @param  OverSampling This parameter can be one of the following values:
-  *         @arg @ref LL_USART_OVERSAMPLING_16
-  *         @arg @ref LL_USART_OVERSAMPLING_8
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t OverSampling)
-{
-  MODIFY_REG(USARTx->CR1, USART_CR1_OVER8, OverSampling);
-}
-
-/**
-  * @brief  Return Oversampling mode
-  * @rmtoll CR1          OVER8         LL_USART_GetOverSampling
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_OVERSAMPLING_16
-  *         @arg @ref LL_USART_OVERSAMPLING_8
-  */
-__STATIC_INLINE uint32_t LL_USART_GetOverSampling(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8));
-}
-
-/**
-  * @brief  Configure if Clock pulse of the last data bit is output to the SCLK pin or not
-  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
-  *         Synchronous mode is supported by the USARTx instance.
-  * @rmtoll CR2          LBCL          LL_USART_SetLastClkPulseOutput
-  * @param  USARTx USART Instance
-  * @param  LastBitClockPulse This parameter can be one of the following values:
-  *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
-  *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint32_t LastBitClockPulse)
-{
-  MODIFY_REG(USARTx->CR2, USART_CR2_LBCL, LastBitClockPulse);
-}
-
-/**
-  * @brief  Retrieve Clock pulse of the last data bit output configuration
-  *         (Last bit Clock pulse output to the SCLK pin or not)
-  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
-  *         Synchronous mode is supported by the USARTx instance.
-  * @rmtoll CR2          LBCL          LL_USART_GetLastClkPulseOutput
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
-  *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
-  */
-__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL));
-}
-
-/**
-  * @brief  Select the phase of the clock output on the SCLK pin in synchronous mode
-  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
-  *         Synchronous mode is supported by the USARTx instance.
-  * @rmtoll CR2          CPHA          LL_USART_SetClockPhase
-  * @param  USARTx USART Instance
-  * @param  ClockPhase This parameter can be one of the following values:
-  *         @arg @ref LL_USART_PHASE_1EDGE
-  *         @arg @ref LL_USART_PHASE_2EDGE
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t ClockPhase)
-{
-  MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase);
-}
-
-/**
-  * @brief  Return phase of the clock output on the SCLK pin in synchronous mode
-  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
-  *         Synchronous mode is supported by the USARTx instance.
-  * @rmtoll CR2          CPHA          LL_USART_GetClockPhase
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_PHASE_1EDGE
-  *         @arg @ref LL_USART_PHASE_2EDGE
-  */
-__STATIC_INLINE uint32_t LL_USART_GetClockPhase(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA));
-}
-
-/**
-  * @brief  Select the polarity of the clock output on the SCLK pin in synchronous mode
-  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
-  *         Synchronous mode is supported by the USARTx instance.
-  * @rmtoll CR2          CPOL          LL_USART_SetClockPolarity
-  * @param  USARTx USART Instance
-  * @param  ClockPolarity This parameter can be one of the following values:
-  *         @arg @ref LL_USART_POLARITY_LOW
-  *         @arg @ref LL_USART_POLARITY_HIGH
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t ClockPolarity)
-{
-  MODIFY_REG(USARTx->CR2, USART_CR2_CPOL, ClockPolarity);
-}
-
-/**
-  * @brief  Return polarity of the clock output on the SCLK pin in synchronous mode
-  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
-  *         Synchronous mode is supported by the USARTx instance.
-  * @rmtoll CR2          CPOL          LL_USART_GetClockPolarity
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_POLARITY_LOW
-  *         @arg @ref LL_USART_POLARITY_HIGH
-  */
-__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL));
-}
-
-/**
-  * @brief  Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse)
-  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
-  *         Synchronous mode is supported by the USARTx instance.
-  * @note   Call of this function is equivalent to following function call sequence :
-  *         - Clock Phase configuration using @ref LL_USART_SetClockPhase() function
-  *         - Clock Polarity configuration using @ref LL_USART_SetClockPolarity() function
-  *         - Output of Last bit Clock pulse configuration using @ref LL_USART_SetLastClkPulseOutput() function
-  * @rmtoll CR2          CPHA          LL_USART_ConfigClock\n
-  *         CR2          CPOL          LL_USART_ConfigClock\n
-  *         CR2          LBCL          LL_USART_ConfigClock
-  * @param  USARTx USART Instance
-  * @param  Phase This parameter can be one of the following values:
-  *         @arg @ref LL_USART_PHASE_1EDGE
-  *         @arg @ref LL_USART_PHASE_2EDGE
-  * @param  Polarity This parameter can be one of the following values:
-  *         @arg @ref LL_USART_POLARITY_LOW
-  *         @arg @ref LL_USART_POLARITY_HIGH
-  * @param  LBCPOutput This parameter can be one of the following values:
-  *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
-  *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput)
-{
-  MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, Phase | Polarity | LBCPOutput);
-}
-
-/**
-  * @brief  Configure Clock source prescaler for baudrate generator and oversampling
-  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
-  *         FIFO mode feature is supported by the USARTx instance.
-  * @rmtoll PRESC        PRESCALER     LL_USART_SetPrescaler
-  * @param  USARTx USART Instance
-  * @param  PrescalerValue This parameter can be one of the following values:
-  *         @arg @ref LL_USART_PRESCALER_DIV1
-  *         @arg @ref LL_USART_PRESCALER_DIV2
-  *         @arg @ref LL_USART_PRESCALER_DIV4
-  *         @arg @ref LL_USART_PRESCALER_DIV6
-  *         @arg @ref LL_USART_PRESCALER_DIV8
-  *         @arg @ref LL_USART_PRESCALER_DIV10
-  *         @arg @ref LL_USART_PRESCALER_DIV12
-  *         @arg @ref LL_USART_PRESCALER_DIV16
-  *         @arg @ref LL_USART_PRESCALER_DIV32
-  *         @arg @ref LL_USART_PRESCALER_DIV64
-  *         @arg @ref LL_USART_PRESCALER_DIV128
-  *         @arg @ref LL_USART_PRESCALER_DIV256
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
-{
-  MODIFY_REG(USARTx->PRESC, USART_PRESC_PRESCALER, (uint16_t)PrescalerValue);
-}
-
-/**
-  * @brief  Retrieve the Clock source prescaler for baudrate generator and oversampling
-  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
-  *         FIFO mode feature is supported by the USARTx instance.
-  * @rmtoll PRESC        PRESCALER     LL_USART_GetPrescaler
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_PRESCALER_DIV1
-  *         @arg @ref LL_USART_PRESCALER_DIV2
-  *         @arg @ref LL_USART_PRESCALER_DIV4
-  *         @arg @ref LL_USART_PRESCALER_DIV6
-  *         @arg @ref LL_USART_PRESCALER_DIV8
-  *         @arg @ref LL_USART_PRESCALER_DIV10
-  *         @arg @ref LL_USART_PRESCALER_DIV12
-  *         @arg @ref LL_USART_PRESCALER_DIV16
-  *         @arg @ref LL_USART_PRESCALER_DIV32
-  *         @arg @ref LL_USART_PRESCALER_DIV64
-  *         @arg @ref LL_USART_PRESCALER_DIV128
-  *         @arg @ref LL_USART_PRESCALER_DIV256
-  */
-__STATIC_INLINE uint32_t LL_USART_GetPrescaler(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->PRESC, USART_PRESC_PRESCALER));
-}
-
-/**
-  * @brief  Enable Clock output on SCLK pin
-  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
-  *         Synchronous mode is supported by the USARTx instance.
-  * @rmtoll CR2          CLKEN         LL_USART_EnableSCLKOutput
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
-}
-
-/**
-  * @brief  Disable Clock output on SCLK pin
-  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
-  *         Synchronous mode is supported by the USARTx instance.
-  * @rmtoll CR2          CLKEN         LL_USART_DisableSCLKOutput
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN);
-}
-
-/**
-  * @brief  Indicate if Clock output on SCLK pin is enabled
-  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
-  *         Synchronous mode is supported by the USARTx instance.
-  * @rmtoll CR2          CLKEN         LL_USART_IsEnabledSCLKOutput
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Set the length of the stop bits
-  * @rmtoll CR2          STOP          LL_USART_SetStopBitsLength
-  * @param  USARTx USART Instance
-  * @param  StopBits This parameter can be one of the following values:
-  *         @arg @ref LL_USART_STOPBITS_0_5
-  *         @arg @ref LL_USART_STOPBITS_1
-  *         @arg @ref LL_USART_STOPBITS_1_5
-  *         @arg @ref LL_USART_STOPBITS_2
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t StopBits)
-{
-  MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
-}
-
-/**
-  * @brief  Retrieve the length of the stop bits
-  * @rmtoll CR2          STOP          LL_USART_GetStopBitsLength
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_STOPBITS_0_5
-  *         @arg @ref LL_USART_STOPBITS_1
-  *         @arg @ref LL_USART_STOPBITS_1_5
-  *         @arg @ref LL_USART_STOPBITS_2
-  */
-__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP));
-}
-
-/**
-  * @brief  Configure Character frame format (Datawidth, Parity control, Stop Bits)
-  * @note   Call of this function is equivalent to following function call sequence :
-  *         - Data Width configuration using @ref LL_USART_SetDataWidth() function
-  *         - Parity Control and mode configuration using @ref LL_USART_SetParity() function
-  *         - Stop bits configuration using @ref LL_USART_SetStopBitsLength() function
-  * @rmtoll CR1          PS            LL_USART_ConfigCharacter\n
-  *         CR1          PCE           LL_USART_ConfigCharacter\n
-  *         CR1          M0            LL_USART_ConfigCharacter\n
-  *         CR1          M1            LL_USART_ConfigCharacter\n
-  *         CR2          STOP          LL_USART_ConfigCharacter
-  * @param  USARTx USART Instance
-  * @param  DataWidth This parameter can be one of the following values:
-  *         @arg @ref LL_USART_DATAWIDTH_7B
-  *         @arg @ref LL_USART_DATAWIDTH_8B
-  *         @arg @ref LL_USART_DATAWIDTH_9B
-  * @param  Parity This parameter can be one of the following values:
-  *         @arg @ref LL_USART_PARITY_NONE
-  *         @arg @ref LL_USART_PARITY_EVEN
-  *         @arg @ref LL_USART_PARITY_ODD
-  * @param  StopBits This parameter can be one of the following values:
-  *         @arg @ref LL_USART_STOPBITS_0_5
-  *         @arg @ref LL_USART_STOPBITS_1
-  *         @arg @ref LL_USART_STOPBITS_1_5
-  *         @arg @ref LL_USART_STOPBITS_2
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ConfigCharacter(USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity,
-                                              uint32_t StopBits)
-{
-  MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);
-  MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
-}
-
-/**
-  * @brief  Configure TX/RX pins swapping setting.
-  * @rmtoll CR2          SWAP          LL_USART_SetTXRXSwap
-  * @param  USARTx USART Instance
-  * @param  SwapConfig This parameter can be one of the following values:
-  *         @arg @ref LL_USART_TXRX_STANDARD
-  *         @arg @ref LL_USART_TXRX_SWAPPED
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetTXRXSwap(USART_TypeDef *USARTx, uint32_t SwapConfig)
-{
-  MODIFY_REG(USARTx->CR2, USART_CR2_SWAP, SwapConfig);
-}
-
-/**
-  * @brief  Retrieve TX/RX pins swapping configuration.
-  * @rmtoll CR2          SWAP          LL_USART_GetTXRXSwap
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_TXRX_STANDARD
-  *         @arg @ref LL_USART_TXRX_SWAPPED
-  */
-__STATIC_INLINE uint32_t LL_USART_GetTXRXSwap(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_SWAP));
-}
-
-/**
-  * @brief  Configure RX pin active level logic
-  * @rmtoll CR2          RXINV         LL_USART_SetRXPinLevel
-  * @param  USARTx USART Instance
-  * @param  PinInvMethod This parameter can be one of the following values:
-  *         @arg @ref LL_USART_RXPIN_LEVEL_STANDARD
-  *         @arg @ref LL_USART_RXPIN_LEVEL_INVERTED
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetRXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod)
-{
-  MODIFY_REG(USARTx->CR2, USART_CR2_RXINV, PinInvMethod);
-}
-
-/**
-  * @brief  Retrieve RX pin active level logic configuration
-  * @rmtoll CR2          RXINV         LL_USART_GetRXPinLevel
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_RXPIN_LEVEL_STANDARD
-  *         @arg @ref LL_USART_RXPIN_LEVEL_INVERTED
-  */
-__STATIC_INLINE uint32_t LL_USART_GetRXPinLevel(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_RXINV));
-}
-
-/**
-  * @brief  Configure TX pin active level logic
-  * @rmtoll CR2          TXINV         LL_USART_SetTXPinLevel
-  * @param  USARTx USART Instance
-  * @param  PinInvMethod This parameter can be one of the following values:
-  *         @arg @ref LL_USART_TXPIN_LEVEL_STANDARD
-  *         @arg @ref LL_USART_TXPIN_LEVEL_INVERTED
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetTXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod)
-{
-  MODIFY_REG(USARTx->CR2, USART_CR2_TXINV, PinInvMethod);
-}
-
-/**
-  * @brief  Retrieve TX pin active level logic configuration
-  * @rmtoll CR2          TXINV         LL_USART_GetTXPinLevel
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_TXPIN_LEVEL_STANDARD
-  *         @arg @ref LL_USART_TXPIN_LEVEL_INVERTED
-  */
-__STATIC_INLINE uint32_t LL_USART_GetTXPinLevel(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_TXINV));
-}
-
-/**
-  * @brief  Configure Binary data logic.
-  * @note   Allow to define how Logical data from the data register are send/received :
-  *         either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)
-  * @rmtoll CR2          DATAINV       LL_USART_SetBinaryDataLogic
-  * @param  USARTx USART Instance
-  * @param  DataLogic This parameter can be one of the following values:
-  *         @arg @ref LL_USART_BINARY_LOGIC_POSITIVE
-  *         @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetBinaryDataLogic(USART_TypeDef *USARTx, uint32_t DataLogic)
-{
-  MODIFY_REG(USARTx->CR2, USART_CR2_DATAINV, DataLogic);
-}
-
-/**
-  * @brief  Retrieve Binary data configuration
-  * @rmtoll CR2          DATAINV       LL_USART_GetBinaryDataLogic
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_BINARY_LOGIC_POSITIVE
-  *         @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE
-  */
-__STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_DATAINV));
-}
-
-/**
-  * @brief  Configure transfer bit order (either Less or Most Significant Bit First)
-  * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.
-  *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.
-  * @rmtoll CR2          MSBFIRST      LL_USART_SetTransferBitOrder
-  * @param  USARTx USART Instance
-  * @param  BitOrder This parameter can be one of the following values:
-  *         @arg @ref LL_USART_BITORDER_LSBFIRST
-  *         @arg @ref LL_USART_BITORDER_MSBFIRST
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetTransferBitOrder(USART_TypeDef *USARTx, uint32_t BitOrder)
-{
-  MODIFY_REG(USARTx->CR2, USART_CR2_MSBFIRST, BitOrder);
-}
-
-/**
-  * @brief  Return transfer bit order (either Less or Most Significant Bit First)
-  * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.
-  *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.
-  * @rmtoll CR2          MSBFIRST      LL_USART_GetTransferBitOrder
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_BITORDER_LSBFIRST
-  *         @arg @ref LL_USART_BITORDER_MSBFIRST
-  */
-__STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_MSBFIRST));
-}
-
-/**
-  * @brief  Enable Auto Baud-Rate Detection
-  * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
-  *         Auto Baud Rate detection feature is supported by the USARTx instance.
-  * @rmtoll CR2          ABREN         LL_USART_EnableAutoBaudRate
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableAutoBaudRate(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR2, USART_CR2_ABREN);
-}
-
-/**
-  * @brief  Disable Auto Baud-Rate Detection
-  * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
-  *         Auto Baud Rate detection feature is supported by the USARTx instance.
-  * @rmtoll CR2          ABREN         LL_USART_DisableAutoBaudRate
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableAutoBaudRate(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR2, USART_CR2_ABREN);
-}
-
-/**
-  * @brief  Indicate if Auto Baud-Rate Detection mechanism is enabled
-  * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
-  *         Auto Baud Rate detection feature is supported by the USARTx instance.
-  * @rmtoll CR2          ABREN         LL_USART_IsEnabledAutoBaud
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR2, USART_CR2_ABREN) == (USART_CR2_ABREN)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Set Auto Baud-Rate mode bits
-  * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
-  *         Auto Baud Rate detection feature is supported by the USARTx instance.
-  * @rmtoll CR2          ABRMODE       LL_USART_SetAutoBaudRateMode
-  * @param  USARTx USART Instance
-  * @param  AutoBaudRateMode This parameter can be one of the following values:
-  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
-  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
-  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
-  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetAutoBaudRateMode(USART_TypeDef *USARTx, uint32_t AutoBaudRateMode)
-{
-  MODIFY_REG(USARTx->CR2, USART_CR2_ABRMODE, AutoBaudRateMode);
-}
-
-/**
-  * @brief  Return Auto Baud-Rate mode
-  * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
-  *         Auto Baud Rate detection feature is supported by the USARTx instance.
-  * @rmtoll CR2          ABRMODE       LL_USART_GetAutoBaudRateMode
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
-  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
-  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
-  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
-  */
-__STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ABRMODE));
-}
-
-/**
-  * @brief  Enable Receiver Timeout
-  * @rmtoll CR2          RTOEN         LL_USART_EnableRxTimeout
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableRxTimeout(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR2, USART_CR2_RTOEN);
-}
-
-/**
-  * @brief  Disable Receiver Timeout
-  * @rmtoll CR2          RTOEN         LL_USART_DisableRxTimeout
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableRxTimeout(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR2, USART_CR2_RTOEN);
-}
-
-/**
-  * @brief  Indicate if Receiver Timeout feature is enabled
-  * @rmtoll CR2          RTOEN         LL_USART_IsEnabledRxTimeout
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR2, USART_CR2_RTOEN) == (USART_CR2_RTOEN)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Set Address of the USART node.
-  * @note   This is used in multiprocessor communication during Mute mode or Stop mode,
-  *         for wake up with address mark detection.
-  * @note   4bits address node is used when 4-bit Address Detection is selected in ADDM7.
-  *         (b7-b4 should be set to 0)
-  *         8bits address node is used when 7-bit Address Detection is selected in ADDM7.
-  *         (This is used in multiprocessor communication during Mute mode or Stop mode,
-  *         for wake up with 7-bit address mark detection.
-  *         The MSB of the character sent by the transmitter should be equal to 1.
-  *         It may also be used for character detection during normal reception,
-  *         Mute mode inactive (for example, end of block detection in ModBus protocol).
-  *         In this case, the whole received character (8-bit) is compared to the ADD[7:0]
-  *         value and CMF flag is set on match)
-  * @rmtoll CR2          ADD           LL_USART_ConfigNodeAddress\n
-  *         CR2          ADDM7         LL_USART_ConfigNodeAddress
-  * @param  USARTx USART Instance
-  * @param  AddressLen This parameter can be one of the following values:
-  *         @arg @ref LL_USART_ADDRESS_DETECT_4B
-  *         @arg @ref LL_USART_ADDRESS_DETECT_7B
-  * @param  NodeAddress 4 or 7 bit Address of the USART node.
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ConfigNodeAddress(USART_TypeDef *USARTx, uint32_t AddressLen, uint32_t NodeAddress)
-{
-  MODIFY_REG(USARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7,
-             (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos)));
-}
-
-/**
-  * @brief  Return 8 bit Address of the USART node as set in ADD field of CR2.
-  * @note   If 4-bit Address Detection is selected in ADDM7,
-  *         only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)
-  *         If 7-bit Address Detection is selected in ADDM7,
-  *         only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)
-  * @rmtoll CR2          ADD           LL_USART_GetNodeAddress
-  * @param  USARTx USART Instance
-  * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255)
-  */
-__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos);
-}
-
-/**
-  * @brief  Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
-  * @rmtoll CR2          ADDM7         LL_USART_GetNodeAddressLen
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_ADDRESS_DETECT_4B
-  *         @arg @ref LL_USART_ADDRESS_DETECT_7B
-  */
-__STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADDM7));
-}
-
-/**
-  * @brief  Enable RTS HW Flow Control
-  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
-  *         Hardware Flow control feature is supported by the USARTx instance.
-  * @rmtoll CR3          RTSE          LL_USART_EnableRTSHWFlowCtrl
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR3, USART_CR3_RTSE);
-}
-
-/**
-  * @brief  Disable RTS HW Flow Control
-  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
-  *         Hardware Flow control feature is supported by the USARTx instance.
-  * @rmtoll CR3          RTSE          LL_USART_DisableRTSHWFlowCtrl
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR3, USART_CR3_RTSE);
-}
-
-/**
-  * @brief  Enable CTS HW Flow Control
-  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
-  *         Hardware Flow control feature is supported by the USARTx instance.
-  * @rmtoll CR3          CTSE          LL_USART_EnableCTSHWFlowCtrl
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR3, USART_CR3_CTSE);
-}
-
-/**
-  * @brief  Disable CTS HW Flow Control
-  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
-  *         Hardware Flow control feature is supported by the USARTx instance.
-  * @rmtoll CR3          CTSE          LL_USART_DisableCTSHWFlowCtrl
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR3, USART_CR3_CTSE);
-}
-
-/**
-  * @brief  Configure HW Flow Control mode (both CTS and RTS)
-  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
-  *         Hardware Flow control feature is supported by the USARTx instance.
-  * @rmtoll CR3          RTSE          LL_USART_SetHWFlowCtrl\n
-  *         CR3          CTSE          LL_USART_SetHWFlowCtrl
-  * @param  USARTx USART Instance
-  * @param  HardwareFlowControl This parameter can be one of the following values:
-  *         @arg @ref LL_USART_HWCONTROL_NONE
-  *         @arg @ref LL_USART_HWCONTROL_RTS
-  *         @arg @ref LL_USART_HWCONTROL_CTS
-  *         @arg @ref LL_USART_HWCONTROL_RTS_CTS
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t HardwareFlowControl)
-{
-  MODIFY_REG(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);
-}
-
-/**
-  * @brief  Return HW Flow Control configuration (both CTS and RTS)
-  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
-  *         Hardware Flow control feature is supported by the USARTx instance.
-  * @rmtoll CR3          RTSE          LL_USART_GetHWFlowCtrl\n
-  *         CR3          CTSE          LL_USART_GetHWFlowCtrl
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_HWCONTROL_NONE
-  *         @arg @ref LL_USART_HWCONTROL_RTS
-  *         @arg @ref LL_USART_HWCONTROL_CTS
-  *         @arg @ref LL_USART_HWCONTROL_RTS_CTS
-  */
-__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
-}
-
-/**
-  * @brief  Enable One bit sampling method
-  * @rmtoll CR3          ONEBIT        LL_USART_EnableOneBitSamp
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableOneBitSamp(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR3, USART_CR3_ONEBIT);
-}
-
-/**
-  * @brief  Disable One bit sampling method
-  * @rmtoll CR3          ONEBIT        LL_USART_DisableOneBitSamp
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR3, USART_CR3_ONEBIT);
-}
-
-/**
-  * @brief  Indicate if One bit sampling method is enabled
-  * @rmtoll CR3          ONEBIT        LL_USART_IsEnabledOneBitSamp
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable Overrun detection
-  * @rmtoll CR3          OVRDIS        LL_USART_EnableOverrunDetect
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableOverrunDetect(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR3, USART_CR3_OVRDIS);
-}
-
-/**
-  * @brief  Disable Overrun detection
-  * @rmtoll CR3          OVRDIS        LL_USART_DisableOverrunDetect
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableOverrunDetect(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR3, USART_CR3_OVRDIS);
-}
-
-/**
-  * @brief  Indicate if Overrun detection is enabled
-  * @rmtoll CR3          OVRDIS        LL_USART_IsEnabledOverrunDetect
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
-  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
-  *         Wake-up from Stop mode feature is supported by the USARTx instance.
-  * @rmtoll CR3          WUS           LL_USART_SetWKUPType
-  * @param  USARTx USART Instance
-  * @param  Type This parameter can be one of the following values:
-  *         @arg @ref LL_USART_WAKEUP_ON_ADDRESS
-  *         @arg @ref LL_USART_WAKEUP_ON_STARTBIT
-  *         @arg @ref LL_USART_WAKEUP_ON_RXNE
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetWKUPType(USART_TypeDef *USARTx, uint32_t Type)
-{
-  MODIFY_REG(USARTx->CR3, USART_CR3_WUS, Type);
-}
-
-/**
-  * @brief  Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
-  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
-  *         Wake-up from Stop mode feature is supported by the USARTx instance.
-  * @rmtoll CR3          WUS           LL_USART_GetWKUPType
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_WAKEUP_ON_ADDRESS
-  *         @arg @ref LL_USART_WAKEUP_ON_STARTBIT
-  *         @arg @ref LL_USART_WAKEUP_ON_RXNE
-  */
-__STATIC_INLINE uint32_t LL_USART_GetWKUPType(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_WUS));
-}
-
-/**
-  * @brief  Configure USART BRR register for achieving expected Baud Rate value.
-  * @note   Compute and set USARTDIV value in BRR Register (full BRR content)
-  *         according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values
-  * @note   Peripheral clock and Baud rate values provided as function parameters should be valid
-  *         (Baud rate value != 0)
-  * @note   In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d.
-  * @rmtoll BRR          BRR           LL_USART_SetBaudRate
-  * @param  USARTx USART Instance
-  * @param  PeriphClk Peripheral Clock
-  * @param  PrescalerValue This parameter can be one of the following values:
-  *         @arg @ref LL_USART_PRESCALER_DIV1
-  *         @arg @ref LL_USART_PRESCALER_DIV2
-  *         @arg @ref LL_USART_PRESCALER_DIV4
-  *         @arg @ref LL_USART_PRESCALER_DIV6
-  *         @arg @ref LL_USART_PRESCALER_DIV8
-  *         @arg @ref LL_USART_PRESCALER_DIV10
-  *         @arg @ref LL_USART_PRESCALER_DIV12
-  *         @arg @ref LL_USART_PRESCALER_DIV16
-  *         @arg @ref LL_USART_PRESCALER_DIV32
-  *         @arg @ref LL_USART_PRESCALER_DIV64
-  *         @arg @ref LL_USART_PRESCALER_DIV128
-  *         @arg @ref LL_USART_PRESCALER_DIV256
-  * @param  OverSampling This parameter can be one of the following values:
-  *         @arg @ref LL_USART_OVERSAMPLING_16
-  *         @arg @ref LL_USART_OVERSAMPLING_8
-  * @param  BaudRate Baud Rate
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
-                                          uint32_t OverSampling,
-                                          uint32_t BaudRate)
-{
-  uint32_t usartdiv;
-  uint32_t brrtemp;
-
-  if (PrescalerValue > LL_USART_PRESCALER_DIV256)
-  {
-    /* Do not overstep the size of USART_PRESCALER_TAB */
-  }
-  else if (BaudRate == 0U)
-  {
-    /* Can Not divide per 0 */
-  }
-  else if (OverSampling == LL_USART_OVERSAMPLING_8)
-  {
-    usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, (uint8_t)PrescalerValue, BaudRate));
-    brrtemp = usartdiv & 0xFFF0U;
-    brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
-    USARTx->BRR = brrtemp;
-  }
-  else
-  {
-    USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, (uint8_t)PrescalerValue, BaudRate));
-  }
-}
-
-/**
-  * @brief  Return current Baud Rate value, according to USARTDIV present in BRR register
-  *         (full BRR content), and to used Peripheral Clock and Oversampling mode values
-  * @note   In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
-  * @note   In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d.
-  * @rmtoll BRR          BRR           LL_USART_GetBaudRate
-  * @param  USARTx USART Instance
-  * @param  PeriphClk Peripheral Clock
-  * @param  PrescalerValue This parameter can be one of the following values:
-  *         @arg @ref LL_USART_PRESCALER_DIV1
-  *         @arg @ref LL_USART_PRESCALER_DIV2
-  *         @arg @ref LL_USART_PRESCALER_DIV4
-  *         @arg @ref LL_USART_PRESCALER_DIV6
-  *         @arg @ref LL_USART_PRESCALER_DIV8
-  *         @arg @ref LL_USART_PRESCALER_DIV10
-  *         @arg @ref LL_USART_PRESCALER_DIV12
-  *         @arg @ref LL_USART_PRESCALER_DIV16
-  *         @arg @ref LL_USART_PRESCALER_DIV32
-  *         @arg @ref LL_USART_PRESCALER_DIV64
-  *         @arg @ref LL_USART_PRESCALER_DIV128
-  *         @arg @ref LL_USART_PRESCALER_DIV256
-  * @param  OverSampling This parameter can be one of the following values:
-  *         @arg @ref LL_USART_OVERSAMPLING_16
-  *         @arg @ref LL_USART_OVERSAMPLING_8
-  * @retval Baud Rate
-  */
-__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
-                                              uint32_t OverSampling)
-{
-  uint32_t usartdiv;
-  uint32_t brrresult = 0x0U;
-  uint32_t periphclkpresc = (uint32_t)(PeriphClk / (USART_PRESCALER_TAB[(uint8_t)PrescalerValue]));
-
-  usartdiv = USARTx->BRR;
-
-  if (usartdiv == 0U)
-  {
-    /* Do not perform a division by 0 */
-  }
-  else if (OverSampling == LL_USART_OVERSAMPLING_8)
-  {
-    usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ;
-    if (usartdiv != 0U)
-    {
-      brrresult = (periphclkpresc * 2U) / usartdiv;
-    }
-  }
-  else
-  {
-    if ((usartdiv & 0xFFFFU) != 0U)
-    {
-      brrresult = periphclkpresc / usartdiv;
-    }
-  }
-  return (brrresult);
-}
-
-/**
-  * @brief  Set Receiver Time Out Value (expressed in nb of bits duration)
-  * @rmtoll RTOR         RTO           LL_USART_SetRxTimeout
-  * @param  USARTx USART Instance
-  * @param  Timeout Value between Min_Data=0x00 and Max_Data=0x00FFFFFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetRxTimeout(USART_TypeDef *USARTx, uint32_t Timeout)
-{
-  MODIFY_REG(USARTx->RTOR, USART_RTOR_RTO, Timeout);
-}
-
-/**
-  * @brief  Get Receiver Time Out Value (expressed in nb of bits duration)
-  * @rmtoll RTOR         RTO           LL_USART_GetRxTimeout
-  * @param  USARTx USART Instance
-  * @retval Value between Min_Data=0x00 and Max_Data=0x00FFFFFF
-  */
-__STATIC_INLINE uint32_t LL_USART_GetRxTimeout(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_RTO));
-}
-
-/**
-  * @brief  Set Block Length value in reception
-  * @rmtoll RTOR         BLEN          LL_USART_SetBlockLength
-  * @param  USARTx USART Instance
-  * @param  BlockLength Value between Min_Data=0x00 and Max_Data=0xFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetBlockLength(USART_TypeDef *USARTx, uint32_t BlockLength)
-{
-  MODIFY_REG(USARTx->RTOR, USART_RTOR_BLEN, BlockLength << USART_RTOR_BLEN_Pos);
-}
-
-/**
-  * @brief  Get Block Length value in reception
-  * @rmtoll RTOR         BLEN          LL_USART_GetBlockLength
-  * @param  USARTx USART Instance
-  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
-  */
-__STATIC_INLINE uint32_t LL_USART_GetBlockLength(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_BLEN) >> USART_RTOR_BLEN_Pos);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EF_Configuration_IRDA Configuration functions related to Irda feature
-  * @{
-  */
-
-/**
-  * @brief  Enable IrDA mode
-  * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
-  *         IrDA feature is supported by the USARTx instance.
-  * @rmtoll CR3          IREN          LL_USART_EnableIrda
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR3, USART_CR3_IREN);
-}
-
-/**
-  * @brief  Disable IrDA mode
-  * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
-  *         IrDA feature is supported by the USARTx instance.
-  * @rmtoll CR3          IREN          LL_USART_DisableIrda
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR3, USART_CR3_IREN);
-}
-
-/**
-  * @brief  Indicate if IrDA mode is enabled
-  * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
-  *         IrDA feature is supported by the USARTx instance.
-  * @rmtoll CR3          IREN          LL_USART_IsEnabledIrda
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Configure IrDA Power Mode (Normal or Low Power)
-  * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
-  *         IrDA feature is supported by the USARTx instance.
-  * @rmtoll CR3          IRLP          LL_USART_SetIrdaPowerMode
-  * @param  USARTx USART Instance
-  * @param  PowerMode This parameter can be one of the following values:
-  *         @arg @ref LL_USART_IRDA_POWER_NORMAL
-  *         @arg @ref LL_USART_IRDA_POWER_LOW
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t PowerMode)
-{
-  MODIFY_REG(USARTx->CR3, USART_CR3_IRLP, PowerMode);
-}
-
-/**
-  * @brief  Retrieve IrDA Power Mode configuration (Normal or Low Power)
-  * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
-  *         IrDA feature is supported by the USARTx instance.
-  * @rmtoll CR3          IRLP          LL_USART_GetIrdaPowerMode
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_IRDA_POWER_NORMAL
-  *         @arg @ref LL_USART_PHASE_2EDGE
-  */
-__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP));
-}
-
-/**
-  * @brief  Set Irda prescaler value, used for dividing the USART clock source
-  *         to achieve the Irda Low Power frequency (8 bits value)
-  * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
-  *         IrDA feature is supported by the USARTx instance.
-  * @rmtoll GTPR         PSC           LL_USART_SetIrdaPrescaler
-  * @param  USARTx USART Instance
-  * @param  PrescalerValue Value between Min_Data=0x00 and Max_Data=0xFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
-{
-  MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue);
-}
-
-/**
-  * @brief  Return Irda prescaler value, used for dividing the USART clock source
-  *         to achieve the Irda Low Power frequency (8 bits value)
-  * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
-  *         IrDA feature is supported by the USARTx instance.
-  * @rmtoll GTPR         PSC           LL_USART_GetIrdaPrescaler
-  * @param  USARTx USART Instance
-  * @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF)
-  */
-__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EF_Configuration_Smartcard Configuration functions related to Smartcard feature
-  * @{
-  */
-
-/**
-  * @brief  Enable Smartcard NACK transmission
-  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll CR3          NACK          LL_USART_EnableSmartcardNACK
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR3, USART_CR3_NACK);
-}
-
-/**
-  * @brief  Disable Smartcard NACK transmission
-  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll CR3          NACK          LL_USART_DisableSmartcardNACK
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR3, USART_CR3_NACK);
-}
-
-/**
-  * @brief  Indicate if Smartcard NACK transmission is enabled
-  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll CR3          NACK          LL_USART_IsEnabledSmartcardNACK
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable Smartcard mode
-  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll CR3          SCEN          LL_USART_EnableSmartcard
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR3, USART_CR3_SCEN);
-}
-
-/**
-  * @brief  Disable Smartcard mode
-  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll CR3          SCEN          LL_USART_DisableSmartcard
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR3, USART_CR3_SCEN);
-}
-
-/**
-  * @brief  Indicate if Smartcard mode is enabled
-  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll CR3          SCEN          LL_USART_IsEnabledSmartcard
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
-  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @note   This bit-field specifies the number of retries in transmit and receive, in Smartcard mode.
-  *         In transmission mode, it specifies the number of automatic retransmission retries, before
-  *         generating a transmission error (FE bit set).
-  *         In reception mode, it specifies the number or erroneous reception trials, before generating a
-  *         reception error (RXNE and PE bits set)
-  * @rmtoll CR3          SCARCNT       LL_USART_SetSmartcardAutoRetryCount
-  * @param  USARTx USART Instance
-  * @param  AutoRetryCount Value between Min_Data=0 and Max_Data=7
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount(USART_TypeDef *USARTx, uint32_t AutoRetryCount)
-{
-  MODIFY_REG(USARTx->CR3, USART_CR3_SCARCNT, AutoRetryCount << USART_CR3_SCARCNT_Pos);
-}
-
-/**
-  * @brief  Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
-  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll CR3          SCARCNT       LL_USART_GetSmartcardAutoRetryCount
-  * @param  USARTx USART Instance
-  * @retval Smartcard Auto-Retry Count value (Value between Min_Data=0 and Max_Data=7)
-  */
-__STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_SCARCNT) >> USART_CR3_SCARCNT_Pos);
-}
-
-/**
-  * @brief  Set Smartcard prescaler value, used for dividing the USART clock
-  *         source to provide the SMARTCARD Clock (5 bits value)
-  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll GTPR         PSC           LL_USART_SetSmartcardPrescaler
-  * @param  USARTx USART Instance
-  * @param  PrescalerValue Value between Min_Data=0 and Max_Data=31
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
-{
-  MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue);
-}
-
-/**
-  * @brief  Return Smartcard prescaler value, used for dividing the USART clock
-  *         source to provide the SMARTCARD Clock (5 bits value)
-  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll GTPR         PSC           LL_USART_GetSmartcardPrescaler
-  * @param  USARTx USART Instance
-  * @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31)
-  */
-__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
-}
-
-/**
-  * @brief  Set Smartcard Guard time value, expressed in nb of baud clocks periods
-  *         (GT[7:0] bits : Guard time value)
-  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll GTPR         GT            LL_USART_SetSmartcardGuardTime
-  * @param  USARTx USART Instance
-  * @param  GuardTime Value between Min_Data=0x00 and Max_Data=0xFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime)
-{
-  MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, (uint16_t)(GuardTime << USART_GTPR_GT_Pos));
-}
-
-/**
-  * @brief  Return Smartcard Guard time value, expressed in nb of baud clocks periods
-  *         (GT[7:0] bits : Guard time value)
-  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll GTPR         GT            LL_USART_GetSmartcardGuardTime
-  * @param  USARTx USART Instance
-  * @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF)
-  */
-__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_GTPR_GT_Pos);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature
-  * @{
-  */
-
-/**
-  * @brief  Enable Single Wire Half-Duplex mode
-  * @note   Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
-  *         Half-Duplex mode is supported by the USARTx instance.
-  * @rmtoll CR3          HDSEL         LL_USART_EnableHalfDuplex
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
-}
-
-/**
-  * @brief  Disable Single Wire Half-Duplex mode
-  * @note   Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
-  *         Half-Duplex mode is supported by the USARTx instance.
-  * @rmtoll CR3          HDSEL         LL_USART_DisableHalfDuplex
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL);
-}
-
-/**
-  * @brief  Indicate if Single Wire Half-Duplex mode is enabled
-  * @note   Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
-  *         Half-Duplex mode is supported by the USARTx instance.
-  * @rmtoll CR3          HDSEL         LL_USART_IsEnabledHalfDuplex
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EF_Configuration_SPI_SLAVE Configuration functions related to SPI Slave feature
-  * @{
-  */
-/**
-  * @brief  Enable SPI Synchronous Slave mode
-  * @note   Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
-  *         SPI Slave mode feature is supported by the USARTx instance.
-  * @rmtoll CR2          SLVEN         LL_USART_EnableSPISlave
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableSPISlave(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR2, USART_CR2_SLVEN);
-}
-
-/**
-  * @brief  Disable SPI Synchronous Slave mode
-  * @note   Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
-  *         SPI Slave mode feature is supported by the USARTx instance.
-  * @rmtoll CR2          SLVEN         LL_USART_DisableSPISlave
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableSPISlave(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR2, USART_CR2_SLVEN);
-}
-
-/**
-  * @brief  Indicate if  SPI Synchronous Slave mode is enabled
-  * @note   Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
-  *         SPI Slave mode feature is supported by the USARTx instance.
-  * @rmtoll CR2          SLVEN         LL_USART_IsEnabledSPISlave
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlave(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR2, USART_CR2_SLVEN) == (USART_CR2_SLVEN)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable SPI Slave Selection using NSS input pin
-  * @note   Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
-  *         SPI Slave mode feature is supported by the USARTx instance.
-  * @note   SPI Slave Selection depends on NSS input pin
-  *         (The slave is selected when NSS is low and deselected when NSS is high).
-  * @rmtoll CR2          DIS_NSS       LL_USART_EnableSPISlaveSelect
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableSPISlaveSelect(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR2, USART_CR2_DIS_NSS);
-}
-
-/**
-  * @brief  Disable SPI Slave Selection using NSS input pin
-  * @note   Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
-  *         SPI Slave mode feature is supported by the USARTx instance.
-  * @note   SPI Slave will be always selected and NSS input pin will be ignored.
-  * @rmtoll CR2          DIS_NSS       LL_USART_DisableSPISlaveSelect
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableSPISlaveSelect(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR2, USART_CR2_DIS_NSS);
-}
-
-/**
-  * @brief  Indicate if  SPI Slave Selection depends on NSS input pin
-  * @note   Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
-  *         SPI Slave mode feature is supported by the USARTx instance.
-  * @rmtoll CR2          DIS_NSS       LL_USART_IsEnabledSPISlaveSelect
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlaveSelect(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR2, USART_CR2_DIS_NSS) != (USART_CR2_DIS_NSS)) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EF_Configuration_LIN Configuration functions related to LIN feature
-  * @{
-  */
-
-/**
-  * @brief  Set LIN Break Detection Length
-  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
-  *         LIN feature is supported by the USARTx instance.
-  * @rmtoll CR2          LBDL          LL_USART_SetLINBrkDetectionLen
-  * @param  USARTx USART Instance
-  * @param  LINBDLength This parameter can be one of the following values:
-  *         @arg @ref LL_USART_LINBREAK_DETECT_10B
-  *         @arg @ref LL_USART_LINBREAK_DETECT_11B
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint32_t LINBDLength)
-{
-  MODIFY_REG(USARTx->CR2, USART_CR2_LBDL, LINBDLength);
-}
-
-/**
-  * @brief  Return LIN Break Detection Length
-  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
-  *         LIN feature is supported by the USARTx instance.
-  * @rmtoll CR2          LBDL          LL_USART_GetLINBrkDetectionLen
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_LINBREAK_DETECT_10B
-  *         @arg @ref LL_USART_LINBREAK_DETECT_11B
-  */
-__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL));
-}
-
-/**
-  * @brief  Enable LIN mode
-  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
-  *         LIN feature is supported by the USARTx instance.
-  * @rmtoll CR2          LINEN         LL_USART_EnableLIN
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR2, USART_CR2_LINEN);
-}
-
-/**
-  * @brief  Disable LIN mode
-  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
-  *         LIN feature is supported by the USARTx instance.
-  * @rmtoll CR2          LINEN         LL_USART_DisableLIN
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR2, USART_CR2_LINEN);
-}
-
-/**
-  * @brief  Indicate if LIN mode is enabled
-  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
-  *         LIN feature is supported by the USARTx instance.
-  * @rmtoll CR2          LINEN         LL_USART_IsEnabledLIN
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN)) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature
-  * @{
-  */
-
-/**
-  * @brief  Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
-  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
-  *         Driver Enable feature is supported by the USARTx instance.
-  * @rmtoll CR1          DEDT          LL_USART_SetDEDeassertionTime
-  * @param  USARTx USART Instance
-  * @param  Time Value between Min_Data=0 and Max_Data=31
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetDEDeassertionTime(USART_TypeDef *USARTx, uint32_t Time)
-{
-  MODIFY_REG(USARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos);
-}
-
-/**
-  * @brief  Return DEDT (Driver Enable De-Assertion Time)
-  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
-  *         Driver Enable feature is supported by the USARTx instance.
-  * @rmtoll CR1          DEDT          LL_USART_GetDEDeassertionTime
-  * @param  USARTx USART Instance
-  * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31
-  */
-__STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos);
-}
-
-/**
-  * @brief  Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
-  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
-  *         Driver Enable feature is supported by the USARTx instance.
-  * @rmtoll CR1          DEAT          LL_USART_SetDEAssertionTime
-  * @param  USARTx USART Instance
-  * @param  Time Value between Min_Data=0 and Max_Data=31
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetDEAssertionTime(USART_TypeDef *USARTx, uint32_t Time)
-{
-  MODIFY_REG(USARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos);
-}
-
-/**
-  * @brief  Return DEAT (Driver Enable Assertion Time)
-  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
-  *         Driver Enable feature is supported by the USARTx instance.
-  * @rmtoll CR1          DEAT          LL_USART_GetDEAssertionTime
-  * @param  USARTx USART Instance
-  * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31
-  */
-__STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos);
-}
-
-/**
-  * @brief  Enable Driver Enable (DE) Mode
-  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
-  *         Driver Enable feature is supported by the USARTx instance.
-  * @rmtoll CR3          DEM           LL_USART_EnableDEMode
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableDEMode(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR3, USART_CR3_DEM);
-}
-
-/**
-  * @brief  Disable Driver Enable (DE) Mode
-  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
-  *         Driver Enable feature is supported by the USARTx instance.
-  * @rmtoll CR3          DEM           LL_USART_DisableDEMode
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableDEMode(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR3, USART_CR3_DEM);
-}
-
-/**
-  * @brief  Indicate if Driver Enable (DE) Mode is enabled
-  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
-  *         Driver Enable feature is supported by the USARTx instance.
-  * @rmtoll CR3          DEM           LL_USART_IsEnabledDEMode
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Select Driver Enable Polarity
-  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
-  *         Driver Enable feature is supported by the USARTx instance.
-  * @rmtoll CR3          DEP           LL_USART_SetDESignalPolarity
-  * @param  USARTx USART Instance
-  * @param  Polarity This parameter can be one of the following values:
-  *         @arg @ref LL_USART_DE_POLARITY_HIGH
-  *         @arg @ref LL_USART_DE_POLARITY_LOW
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetDESignalPolarity(USART_TypeDef *USARTx, uint32_t Polarity)
-{
-  MODIFY_REG(USARTx->CR3, USART_CR3_DEP, Polarity);
-}
-
-/**
-  * @brief  Return Driver Enable Polarity
-  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
-  *         Driver Enable feature is supported by the USARTx instance.
-  * @rmtoll CR3          DEP           LL_USART_GetDESignalPolarity
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_DE_POLARITY_HIGH
-  *         @arg @ref LL_USART_DE_POLARITY_LOW
-  */
-__STATIC_INLINE uint32_t LL_USART_GetDESignalPolarity(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_DEP));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EF_AdvancedConfiguration Advanced Configurations services
-  * @{
-  */
-
-/**
-  * @brief  Perform basic configuration of USART for enabling use in Asynchronous Mode (UART)
-  * @note   In UART mode, the following bits must be kept cleared:
-  *           - LINEN bit in the USART_CR2 register,
-  *           - CLKEN bit in the USART_CR2 register,
-  *           - SCEN bit in the USART_CR3 register,
-  *           - IREN bit in the USART_CR3 register,
-  *           - HDSEL bit in the USART_CR3 register.
-  * @note   Call of this function is equivalent to following function call sequence :
-  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
-  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
-  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
-  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
-  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
-  * @note   Other remaining configurations items related to Asynchronous Mode
-  *         (as Baud Rate, Word length, Parity, ...) should be set using
-  *         dedicated functions
-  * @rmtoll CR2          LINEN         LL_USART_ConfigAsyncMode\n
-  *         CR2          CLKEN         LL_USART_ConfigAsyncMode\n
-  *         CR3          SCEN          LL_USART_ConfigAsyncMode\n
-  *         CR3          IREN          LL_USART_ConfigAsyncMode\n
-  *         CR3          HDSEL         LL_USART_ConfigAsyncMode
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx)
-{
-  /* In Asynchronous mode, the following bits must be kept cleared:
-  - LINEN, CLKEN bits in the USART_CR2 register,
-  - SCEN, IREN and HDSEL bits in the USART_CR3 register.
-  */
-  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
-  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
-}
-
-/**
-  * @brief  Perform basic configuration of USART for enabling use in Synchronous Mode
-  * @note   In Synchronous mode, the following bits must be kept cleared:
-  *           - LINEN bit in the USART_CR2 register,
-  *           - SCEN bit in the USART_CR3 register,
-  *           - IREN bit in the USART_CR3 register,
-  *           - HDSEL bit in the USART_CR3 register.
-  *         This function also sets the USART in Synchronous mode.
-  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
-  *         Synchronous mode is supported by the USARTx instance.
-  * @note   Call of this function is equivalent to following function call sequence :
-  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
-  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
-  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
-  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
-  *         - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
-  * @note   Other remaining configurations items related to Synchronous Mode
-  *         (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be set using
-  *         dedicated functions
-  * @rmtoll CR2          LINEN         LL_USART_ConfigSyncMode\n
-  *         CR2          CLKEN         LL_USART_ConfigSyncMode\n
-  *         CR3          SCEN          LL_USART_ConfigSyncMode\n
-  *         CR3          IREN          LL_USART_ConfigSyncMode\n
-  *         CR3          HDSEL         LL_USART_ConfigSyncMode
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx)
-{
-  /* In Synchronous mode, the following bits must be kept cleared:
-  - LINEN bit in the USART_CR2 register,
-  - SCEN, IREN and HDSEL bits in the USART_CR3 register.
-  */
-  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
-  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
-  /* set the UART/USART in Synchronous mode */
-  SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
-}
-
-/**
-  * @brief  Perform basic configuration of USART for enabling use in LIN Mode
-  * @note   In LIN mode, the following bits must be kept cleared:
-  *           - STOP and CLKEN bits in the USART_CR2 register,
-  *           - SCEN bit in the USART_CR3 register,
-  *           - IREN bit in the USART_CR3 register,
-  *           - HDSEL bit in the USART_CR3 register.
-  *         This function also set the UART/USART in LIN mode.
-  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
-  *         LIN feature is supported by the USARTx instance.
-  * @note   Call of this function is equivalent to following function call sequence :
-  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
-  *         - Clear STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
-  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
-  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
-  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
-  *         - Set LINEN in CR2 using @ref LL_USART_EnableLIN() function
-  * @note   Other remaining configurations items related to LIN Mode
-  *         (as Baud Rate, Word length, LIN Break Detection Length, ...) should be set using
-  *         dedicated functions
-  * @rmtoll CR2          CLKEN         LL_USART_ConfigLINMode\n
-  *         CR2          STOP          LL_USART_ConfigLINMode\n
-  *         CR2          LINEN         LL_USART_ConfigLINMode\n
-  *         CR3          IREN          LL_USART_ConfigLINMode\n
-  *         CR3          SCEN          LL_USART_ConfigLINMode\n
-  *         CR3          HDSEL         LL_USART_ConfigLINMode
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx)
-{
-  /* In LIN mode, the following bits must be kept cleared:
-  - STOP and CLKEN bits in the USART_CR2 register,
-  - IREN, SCEN and HDSEL bits in the USART_CR3 register.
-  */
-  CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP));
-  CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL));
-  /* Set the UART/USART in LIN mode */
-  SET_BIT(USARTx->CR2, USART_CR2_LINEN);
-}
-
-/**
-  * @brief  Perform basic configuration of USART for enabling use in Half Duplex Mode
-  * @note   In Half Duplex mode, the following bits must be kept cleared:
-  *           - LINEN bit in the USART_CR2 register,
-  *           - CLKEN bit in the USART_CR2 register,
-  *           - SCEN bit in the USART_CR3 register,
-  *           - IREN bit in the USART_CR3 register,
-  *         This function also sets the UART/USART in Half Duplex mode.
-  * @note   Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
-  *         Half-Duplex mode is supported by the USARTx instance.
-  * @note   Call of this function is equivalent to following function call sequence :
-  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
-  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
-  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
-  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
-  *         - Set HDSEL in CR3 using @ref LL_USART_EnableHalfDuplex() function
-  * @note   Other remaining configurations items related to Half Duplex Mode
-  *         (as Baud Rate, Word length, Parity, ...) should be set using
-  *         dedicated functions
-  * @rmtoll CR2          LINEN         LL_USART_ConfigHalfDuplexMode\n
-  *         CR2          CLKEN         LL_USART_ConfigHalfDuplexMode\n
-  *         CR3          HDSEL         LL_USART_ConfigHalfDuplexMode\n
-  *         CR3          SCEN          LL_USART_ConfigHalfDuplexMode\n
-  *         CR3          IREN          LL_USART_ConfigHalfDuplexMode
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx)
-{
-  /* In Half Duplex mode, the following bits must be kept cleared:
-  - LINEN and CLKEN bits in the USART_CR2 register,
-  - SCEN and IREN bits in the USART_CR3 register.
-  */
-  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
-  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN));
-  /* set the UART/USART in Half Duplex mode */
-  SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
-}
-
-/**
-  * @brief  Perform basic configuration of USART for enabling use in Smartcard Mode
-  * @note   In Smartcard mode, the following bits must be kept cleared:
-  *           - LINEN bit in the USART_CR2 register,
-  *           - IREN bit in the USART_CR3 register,
-  *           - HDSEL bit in the USART_CR3 register.
-  *         This function also configures Stop bits to 1.5 bits and
-  *         sets the USART in Smartcard mode (SCEN bit).
-  *         Clock Output is also enabled (CLKEN).
-  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @note   Call of this function is equivalent to following function call sequence :
-  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
-  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
-  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
-  *         - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
-  *         - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
-  *         - Set SCEN in CR3 using @ref LL_USART_EnableSmartcard() function
-  * @note   Other remaining configurations items related to Smartcard Mode
-  *         (as Baud Rate, Word length, Parity, ...) should be set using
-  *         dedicated functions
-  * @rmtoll CR2          LINEN         LL_USART_ConfigSmartcardMode\n
-  *         CR2          STOP          LL_USART_ConfigSmartcardMode\n
-  *         CR2          CLKEN         LL_USART_ConfigSmartcardMode\n
-  *         CR3          HDSEL         LL_USART_ConfigSmartcardMode\n
-  *         CR3          SCEN          LL_USART_ConfigSmartcardMode
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx)
-{
-  /* In Smartcard mode, the following bits must be kept cleared:
-  - LINEN bit in the USART_CR2 register,
-  - IREN and HDSEL bits in the USART_CR3 register.
-  */
-  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
-  CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL));
-  /* Configure Stop bits to 1.5 bits */
-  /* Synchronous mode is activated by default */
-  SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN));
-  /* set the UART/USART in Smartcard mode */
-  SET_BIT(USARTx->CR3, USART_CR3_SCEN);
-}
-
-/**
-  * @brief  Perform basic configuration of USART for enabling use in Irda Mode
-  * @note   In IRDA mode, the following bits must be kept cleared:
-  *           - LINEN bit in the USART_CR2 register,
-  *           - STOP and CLKEN bits in the USART_CR2 register,
-  *           - SCEN bit in the USART_CR3 register,
-  *           - HDSEL bit in the USART_CR3 register.
-  *         This function also sets the UART/USART in IRDA mode (IREN bit).
-  * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
-  *         IrDA feature is supported by the USARTx instance.
-  * @note   Call of this function is equivalent to following function call sequence :
-  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
-  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
-  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
-  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
-  *         - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
-  *         - Set IREN in CR3 using @ref LL_USART_EnableIrda() function
-  * @note   Other remaining configurations items related to Irda Mode
-  *         (as Baud Rate, Word length, Power mode, ...) should be set using
-  *         dedicated functions
-  * @rmtoll CR2          LINEN         LL_USART_ConfigIrdaMode\n
-  *         CR2          CLKEN         LL_USART_ConfigIrdaMode\n
-  *         CR2          STOP          LL_USART_ConfigIrdaMode\n
-  *         CR3          SCEN          LL_USART_ConfigIrdaMode\n
-  *         CR3          HDSEL         LL_USART_ConfigIrdaMode\n
-  *         CR3          IREN          LL_USART_ConfigIrdaMode
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx)
-{
-  /* In IRDA mode, the following bits must be kept cleared:
-  - LINEN, STOP and CLKEN bits in the USART_CR2 register,
-  - SCEN and HDSEL bits in the USART_CR3 register.
-  */
-  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP));
-  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
-  /* set the UART/USART in IRDA mode */
-  SET_BIT(USARTx->CR3, USART_CR3_IREN);
-}
-
-/**
-  * @brief  Perform basic configuration of USART for enabling use in Multi processor Mode
-  *         (several USARTs connected in a network, one of the USARTs can be the master,
-  *         its TX output connected to the RX inputs of the other slaves USARTs).
-  * @note   In MultiProcessor mode, the following bits must be kept cleared:
-  *           - LINEN bit in the USART_CR2 register,
-  *           - CLKEN bit in the USART_CR2 register,
-  *           - SCEN bit in the USART_CR3 register,
-  *           - IREN bit in the USART_CR3 register,
-  *           - HDSEL bit in the USART_CR3 register.
-  * @note   Call of this function is equivalent to following function call sequence :
-  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
-  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
-  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
-  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
-  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
-  * @note   Other remaining configurations items related to Multi processor Mode
-  *         (as Baud Rate, Wake Up Method, Node address, ...) should be set using
-  *         dedicated functions
-  * @rmtoll CR2          LINEN         LL_USART_ConfigMultiProcessMode\n
-  *         CR2          CLKEN         LL_USART_ConfigMultiProcessMode\n
-  *         CR3          SCEN          LL_USART_ConfigMultiProcessMode\n
-  *         CR3          HDSEL         LL_USART_ConfigMultiProcessMode\n
-  *         CR3          IREN          LL_USART_ConfigMultiProcessMode
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx)
-{
-  /* In Multi Processor mode, the following bits must be kept cleared:
-  - LINEN and CLKEN bits in the USART_CR2 register,
-  - IREN, SCEN and HDSEL bits in the USART_CR3 register.
-  */
-  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
-  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EF_FLAG_Management FLAG_Management
-  * @{
-  */
-
-/**
-  * @brief  Check if the USART Parity Error Flag is set or not
-  * @rmtoll ISR          PE            LL_USART_IsActiveFlag_PE
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART Framing Error Flag is set or not
-  * @rmtoll ISR          FE            LL_USART_IsActiveFlag_FE
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART Noise error detected Flag is set or not
-  * @rmtoll ISR          NE            LL_USART_IsActiveFlag_NE
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART OverRun Error Flag is set or not
-  * @rmtoll ISR          ORE           LL_USART_IsActiveFlag_ORE
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART IDLE line detected Flag is set or not
-  * @rmtoll ISR          IDLE          LL_USART_IsActiveFlag_IDLE
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL);
-}
-
-/* Legacy define */
-#define LL_USART_IsActiveFlag_RXNE  LL_USART_IsActiveFlag_RXNE_RXFNE
-
-/**
-  * @brief  Check if the USART Read Data Register or USART RX FIFO Not Empty Flag is set or not
-  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
-  *         FIFO mode feature is supported by the USARTx instance.
-  * @rmtoll ISR          RXNE_RXFNE    LL_USART_IsActiveFlag_RXNE_RXFNE
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE_RXFNE(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART Transmission Complete Flag is set or not
-  * @rmtoll ISR          TC            LL_USART_IsActiveFlag_TC
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL);
-}
-
-/* Legacy define */
-#define LL_USART_IsActiveFlag_TXE  LL_USART_IsActiveFlag_TXE_TXFNF
-
-/**
-  * @brief  Check if the USART Transmit Data Register Empty or USART TX FIFO Not Full Flag is set or not
-  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
-  *         FIFO mode feature is supported by the USARTx instance.
-  * @rmtoll ISR          TXE_TXFNF     LL_USART_IsActiveFlag_TXE_TXFNF
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE_TXFNF(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART LIN Break Detection Flag is set or not
-  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
-  *         LIN feature is supported by the USARTx instance.
-  * @rmtoll ISR          LBDF          LL_USART_IsActiveFlag_LBD
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_LBDF) == (USART_ISR_LBDF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART CTS interrupt Flag is set or not
-  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
-  *         Hardware Flow control feature is supported by the USARTx instance.
-  * @rmtoll ISR          CTSIF         LL_USART_IsActiveFlag_nCTS
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART CTS Flag is set or not
-  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
-  *         Hardware Flow control feature is supported by the USARTx instance.
-  * @rmtoll ISR          CTS           LL_USART_IsActiveFlag_CTS
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART Receiver Time Out Flag is set or not
-  * @rmtoll ISR          RTOF          LL_USART_IsActiveFlag_RTO
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_RTOF) == (USART_ISR_RTOF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART End Of Block Flag is set or not
-  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll ISR          EOBF          LL_USART_IsActiveFlag_EOB
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_EOBF) == (USART_ISR_EOBF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the SPI Slave Underrun error flag is set or not
-  * @note   Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
-  *         SPI Slave mode feature is supported by the USARTx instance.
-  * @rmtoll ISR          UDR           LL_USART_IsActiveFlag_UDR
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_UDR(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_UDR) == (USART_ISR_UDR)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART Auto-Baud Rate Error Flag is set or not
-  * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
-  *         Auto Baud Rate detection feature is supported by the USARTx instance.
-  * @rmtoll ISR          ABRE          LL_USART_IsActiveFlag_ABRE
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_ABRE) == (USART_ISR_ABRE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART Auto-Baud Rate Flag is set or not
-  * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
-  *         Auto Baud Rate detection feature is supported by the USARTx instance.
-  * @rmtoll ISR          ABRF          LL_USART_IsActiveFlag_ABR
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_ABRF) == (USART_ISR_ABRF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART Busy Flag is set or not
-  * @rmtoll ISR          BUSY          LL_USART_IsActiveFlag_BUSY
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART Character Match Flag is set or not
-  * @rmtoll ISR          CMF           LL_USART_IsActiveFlag_CM
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART Send Break Flag is set or not
-  * @rmtoll ISR          SBKF          LL_USART_IsActiveFlag_SBK
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART Receive Wake Up from mute mode Flag is set or not
-  * @rmtoll ISR          RWU           LL_USART_IsActiveFlag_RWU
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART Wake Up from stop mode Flag is set or not
-  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
-  *         Wake-up from Stop mode feature is supported by the USARTx instance.
-  * @rmtoll ISR          WUF           LL_USART_IsActiveFlag_WKUP
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART Transmit Enable Acknowledge Flag is set or not
-  * @rmtoll ISR          TEACK         LL_USART_IsActiveFlag_TEACK
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART Receive Enable Acknowledge Flag is set or not
-  * @rmtoll ISR          REACK         LL_USART_IsActiveFlag_REACK
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART TX FIFO Empty Flag is set or not
-  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
-  *         FIFO mode feature is supported by the USARTx instance.
-  * @rmtoll ISR          TXFE          LL_USART_IsActiveFlag_TXFE
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFE(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART RX FIFO Full Flag is set or not
-  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
-  *         FIFO mode feature is supported by the USARTx instance.
-  * @rmtoll ISR          RXFF          LL_USART_IsActiveFlag_RXFF
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFF(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the Smartcard Transmission Complete Before Guard Time Flag is set or not
-  * @rmtoll ISR          TCBGT         LL_USART_IsActiveFlag_TCBGT
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_TCBGT) == (USART_ISR_TCBGT)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART TX FIFO Threshold Flag is set or not
-  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
-  *         FIFO mode feature is supported by the USARTx instance.
-  * @rmtoll ISR          TXFT          LL_USART_IsActiveFlag_TXFT
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFT(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART RX FIFO Threshold Flag is set or not
-  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
-  *         FIFO mode feature is supported by the USARTx instance.
-  * @rmtoll ISR          RXFT          LL_USART_IsActiveFlag_RXFT
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFT(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear Parity Error Flag
-  * @rmtoll ICR          PECF          LL_USART_ClearFlag_PE
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ClearFlag_PE(USART_TypeDef *USARTx)
-{
-  WRITE_REG(USARTx->ICR, USART_ICR_PECF);
-}
-
-/**
-  * @brief  Clear Framing Error Flag
-  * @rmtoll ICR          FECF          LL_USART_ClearFlag_FE
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx)
-{
-  WRITE_REG(USARTx->ICR, USART_ICR_FECF);
-}
-
-/**
-  * @brief  Clear Noise Error detected Flag
-  * @rmtoll ICR          NECF          LL_USART_ClearFlag_NE
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx)
-{
-  WRITE_REG(USARTx->ICR, USART_ICR_NECF);
-}
-
-/**
-  * @brief  Clear OverRun Error Flag
-  * @rmtoll ICR          ORECF         LL_USART_ClearFlag_ORE
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx)
-{
-  WRITE_REG(USARTx->ICR, USART_ICR_ORECF);
-}
-
-/**
-  * @brief  Clear IDLE line detected Flag
-  * @rmtoll ICR          IDLECF        LL_USART_ClearFlag_IDLE
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx)
-{
-  WRITE_REG(USARTx->ICR, USART_ICR_IDLECF);
-}
-
-/**
-  * @brief  Clear TX FIFO Empty Flag
-  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
-  *         FIFO mode feature is supported by the USARTx instance.
-  * @rmtoll ICR          TXFECF        LL_USART_ClearFlag_TXFE
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ClearFlag_TXFE(USART_TypeDef *USARTx)
-{
-  WRITE_REG(USARTx->ICR, USART_ICR_TXFECF);
-}
-
-/**
-  * @brief  Clear Transmission Complete Flag
-  * @rmtoll ICR          TCCF          LL_USART_ClearFlag_TC
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx)
-{
-  WRITE_REG(USARTx->ICR, USART_ICR_TCCF);
-}
-
-/**
-  * @brief  Clear Smartcard Transmission Complete Before Guard Time Flag
-  * @rmtoll ICR          TCBGTCF       LL_USART_ClearFlag_TCBGT
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ClearFlag_TCBGT(USART_TypeDef *USARTx)
-{
-  WRITE_REG(USARTx->ICR, USART_ICR_TCBGTCF);
-}
-
-/**
-  * @brief  Clear LIN Break Detection Flag
-  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
-  *         LIN feature is supported by the USARTx instance.
-  * @rmtoll ICR          LBDCF         LL_USART_ClearFlag_LBD
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx)
-{
-  WRITE_REG(USARTx->ICR, USART_ICR_LBDCF);
-}
-
-/**
-  * @brief  Clear CTS Interrupt Flag
-  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
-  *         Hardware Flow control feature is supported by the USARTx instance.
-  * @rmtoll ICR          CTSCF         LL_USART_ClearFlag_nCTS
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx)
-{
-  WRITE_REG(USARTx->ICR, USART_ICR_CTSCF);
-}
-
-/**
-  * @brief  Clear Receiver Time Out Flag
-  * @rmtoll ICR          RTOCF         LL_USART_ClearFlag_RTO
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ClearFlag_RTO(USART_TypeDef *USARTx)
-{
-  WRITE_REG(USARTx->ICR, USART_ICR_RTOCF);
-}
-
-/**
-  * @brief  Clear End Of Block Flag
-  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll ICR          EOBCF         LL_USART_ClearFlag_EOB
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ClearFlag_EOB(USART_TypeDef *USARTx)
-{
-  WRITE_REG(USARTx->ICR, USART_ICR_EOBCF);
-}
-
-/**
-  * @brief  Clear SPI Slave Underrun Flag
-  * @note   Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
-  *         SPI Slave mode feature is supported by the USARTx instance.
-  * @rmtoll ICR          UDRCF         LL_USART_ClearFlag_UDR
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ClearFlag_UDR(USART_TypeDef *USARTx)
-{
-  WRITE_REG(USARTx->ICR, USART_ICR_UDRCF);
-}
-
-/**
-  * @brief  Clear Character Match Flag
-  * @rmtoll ICR          CMCF          LL_USART_ClearFlag_CM
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ClearFlag_CM(USART_TypeDef *USARTx)
-{
-  WRITE_REG(USARTx->ICR, USART_ICR_CMCF);
-}
-
-/**
-  * @brief  Clear Wake Up from stop mode Flag
-  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
-  *         Wake-up from Stop mode feature is supported by the USARTx instance.
-  * @rmtoll ICR          WUCF          LL_USART_ClearFlag_WKUP
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ClearFlag_WKUP(USART_TypeDef *USARTx)
-{
-  WRITE_REG(USARTx->ICR, USART_ICR_WUCF);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EF_IT_Management IT_Management
-  * @{
-  */
-
-/**
-  * @brief  Enable IDLE Interrupt
-  * @rmtoll CR1          IDLEIE        LL_USART_EnableIT_IDLE
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx)
-{
-  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_IDLEIE);
-}
-
-/* Legacy define */
-#define LL_USART_EnableIT_RXNE  LL_USART_EnableIT_RXNE_RXFNE
-
-/**
-  * @brief  Enable RX Not Empty and RX FIFO Not Empty Interrupt
-  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
-  *         FIFO mode feature is supported by the USARTx instance.
-  * @rmtoll CR1        RXNEIE_RXFNEIE  LL_USART_EnableIT_RXNE_RXFNE
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableIT_RXNE_RXFNE(USART_TypeDef *USARTx)
-{
-  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
-}
-
-/**
-  * @brief  Enable Transmission Complete Interrupt
-  * @rmtoll CR1          TCIE          LL_USART_EnableIT_TC
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx)
-{
-  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TCIE);
-}
-
-/* Legacy define */
-#define LL_USART_EnableIT_TXE  LL_USART_EnableIT_TXE_TXFNF
-
-/**
-  * @brief  Enable TX Empty and TX FIFO Not Full Interrupt
-  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
-  *         FIFO mode feature is supported by the USARTx instance.
-  * @rmtoll CR1         TXEIE_TXFNFIE  LL_USART_EnableIT_TXE_TXFNF
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableIT_TXE_TXFNF(USART_TypeDef *USARTx)
-{
-  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
-}
-
-/**
-  * @brief  Enable Parity Error Interrupt
-  * @rmtoll CR1          PEIE          LL_USART_EnableIT_PE
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx)
-{
-  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_PEIE);
-}
-
-/**
-  * @brief  Enable Character Match Interrupt
-  * @rmtoll CR1          CMIE          LL_USART_EnableIT_CM
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableIT_CM(USART_TypeDef *USARTx)
-{
-  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_CMIE);
-}
-
-/**
-  * @brief  Enable Receiver Timeout Interrupt
-  * @rmtoll CR1          RTOIE         LL_USART_EnableIT_RTO
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableIT_RTO(USART_TypeDef *USARTx)
-{
-  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RTOIE);
-}
-
-/**
-  * @brief  Enable End Of Block Interrupt
-  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll CR1          EOBIE         LL_USART_EnableIT_EOB
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableIT_EOB(USART_TypeDef *USARTx)
-{
-  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_EOBIE);
-}
-
-/**
-  * @brief  Enable TX FIFO Empty Interrupt
-  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
-  *         FIFO mode feature is supported by the USARTx instance.
-  * @rmtoll CR1          TXFEIE        LL_USART_EnableIT_TXFE
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableIT_TXFE(USART_TypeDef *USARTx)
-{
-  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXFEIE);
-}
-
-/**
-  * @brief  Enable RX FIFO Full Interrupt
-  * @rmtoll CR1          RXFFIE        LL_USART_EnableIT_RXFF
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableIT_RXFF(USART_TypeDef *USARTx)
-{
-  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXFFIE);
-}
-
-/**
-  * @brief  Enable LIN Break Detection Interrupt
-  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
-  *         LIN feature is supported by the USARTx instance.
-  * @rmtoll CR2          LBDIE         LL_USART_EnableIT_LBD
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR2, USART_CR2_LBDIE);
-}
-
-/**
-  * @brief  Enable Error Interrupt
-  * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
-  *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register).
-  *           0: Interrupt is inhibited
-  *           1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.
-  * @rmtoll CR3          EIE           LL_USART_EnableIT_ERROR
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx)
-{
-  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_EIE);
-}
-
-/**
-  * @brief  Enable CTS Interrupt
-  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
-  *         Hardware Flow control feature is supported by the USARTx instance.
-  * @rmtoll CR3          CTSIE         LL_USART_EnableIT_CTS
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx)
-{
-  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_CTSIE);
-}
-
-/**
-  * @brief  Enable Wake Up from Stop Mode Interrupt
-  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
-  *         Wake-up from Stop mode feature is supported by the USARTx instance.
-  * @rmtoll CR3          WUFIE         LL_USART_EnableIT_WKUP
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableIT_WKUP(USART_TypeDef *USARTx)
-{
-  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_WUFIE);
-}
-
-/**
-  * @brief  Enable TX FIFO Threshold Interrupt
-  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
-  *         FIFO mode feature is supported by the USARTx instance.
-  * @rmtoll CR3          TXFTIE        LL_USART_EnableIT_TXFT
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableIT_TXFT(USART_TypeDef *USARTx)
-{
-  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_TXFTIE);
-}
-
-/**
-  * @brief  Enable Smartcard Transmission Complete Before Guard Time Interrupt
-  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll CR3          TCBGTIE       LL_USART_EnableIT_TCBGT
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableIT_TCBGT(USART_TypeDef *USARTx)
-{
-  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_TCBGTIE);
-}
-
-/**
-  * @brief  Enable RX FIFO Threshold Interrupt
-  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
-  *         FIFO mode feature is supported by the USARTx instance.
-  * @rmtoll CR3          RXFTIE        LL_USART_EnableIT_RXFT
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableIT_RXFT(USART_TypeDef *USARTx)
-{
-  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_RXFTIE);
-}
-
-/**
-  * @brief  Disable IDLE Interrupt
-  * @rmtoll CR1          IDLEIE        LL_USART_DisableIT_IDLE
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx)
-{
-  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE);
-}
-
-/* Legacy define */
-#define LL_USART_DisableIT_RXNE  LL_USART_DisableIT_RXNE_RXFNE
-
-/**
-  * @brief  Disable RX Not Empty and RX FIFO Not Empty Interrupt
-  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
-  *         FIFO mode feature is supported by the USARTx instance.
-  * @rmtoll CR1        RXNEIE_RXFNEIE  LL_USART_DisableIT_RXNE_RXFNE
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableIT_RXNE_RXFNE(USART_TypeDef *USARTx)
-{
-  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
-}
-
-/**
-  * @brief  Disable Transmission Complete Interrupt
-  * @rmtoll CR1          TCIE          LL_USART_DisableIT_TC
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx)
-{
-  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE);
-}
-
-/* Legacy define */
-#define LL_USART_DisableIT_TXE  LL_USART_DisableIT_TXE_TXFNF
-
-/**
-  * @brief  Disable TX Empty and TX FIFO Not Full Interrupt
-  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
-  *         FIFO mode feature is supported by the USARTx instance.
-  * @rmtoll CR1        TXEIE_TXFNFIE  LL_USART_DisableIT_TXE_TXFNF
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableIT_TXE_TXFNF(USART_TypeDef *USARTx)
-{
-  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
-}
-
-/**
-  * @brief  Disable Parity Error Interrupt
-  * @rmtoll CR1          PEIE          LL_USART_DisableIT_PE
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx)
-{
-  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE);
-}
-
-/**
-  * @brief  Disable Character Match Interrupt
-  * @rmtoll CR1          CMIE          LL_USART_DisableIT_CM
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableIT_CM(USART_TypeDef *USARTx)
-{
-  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_CMIE);
-}
-
-/**
-  * @brief  Disable Receiver Timeout Interrupt
-  * @rmtoll CR1          RTOIE         LL_USART_DisableIT_RTO
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableIT_RTO(USART_TypeDef *USARTx)
-{
-  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RTOIE);
-}
-
-/**
-  * @brief  Disable End Of Block Interrupt
-  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll CR1          EOBIE         LL_USART_DisableIT_EOB
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableIT_EOB(USART_TypeDef *USARTx)
-{
-  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_EOBIE);
-}
-
-/**
-  * @brief  Disable TX FIFO Empty Interrupt
-  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
-  *         FIFO mode feature is supported by the USARTx instance.
-  * @rmtoll CR1          TXFEIE        LL_USART_DisableIT_TXFE
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableIT_TXFE(USART_TypeDef *USARTx)
-{
-  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXFEIE);
-}
-
-/**
-  * @brief  Disable RX FIFO Full Interrupt
-  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
-  *         FIFO mode feature is supported by the USARTx instance.
-  * @rmtoll CR1          RXFFIE        LL_USART_DisableIT_RXFF
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableIT_RXFF(USART_TypeDef *USARTx)
-{
-  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXFFIE);
-}
-
-/**
-  * @brief  Disable LIN Break Detection Interrupt
-  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
-  *         LIN feature is supported by the USARTx instance.
-  * @rmtoll CR2          LBDIE         LL_USART_DisableIT_LBD
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR2, USART_CR2_LBDIE);
-}
-
-/**
-  * @brief  Disable Error Interrupt
-  * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
-  *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register).
-  *           0: Interrupt is inhibited
-  *           1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.
-  * @rmtoll CR3          EIE           LL_USART_DisableIT_ERROR
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx)
-{
-  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_EIE);
-}
-
-/**
-  * @brief  Disable CTS Interrupt
-  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
-  *         Hardware Flow control feature is supported by the USARTx instance.
-  * @rmtoll CR3          CTSIE         LL_USART_DisableIT_CTS
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx)
-{
-  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE);
-}
-
-/**
-  * @brief  Disable Wake Up from Stop Mode Interrupt
-  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
-  *         Wake-up from Stop mode feature is supported by the USARTx instance.
-  * @rmtoll CR3          WUFIE         LL_USART_DisableIT_WKUP
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableIT_WKUP(USART_TypeDef *USARTx)
-{
-  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_WUFIE);
-}
-
-/**
-  * @brief  Disable TX FIFO Threshold Interrupt
-  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
-  *         FIFO mode feature is supported by the USARTx instance.
-  * @rmtoll CR3          TXFTIE        LL_USART_DisableIT_TXFT
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableIT_TXFT(USART_TypeDef *USARTx)
-{
-  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_TXFTIE);
-}
-
-/**
-  * @brief  Disable Smartcard Transmission Complete Before Guard Time Interrupt
-  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll CR3          TCBGTIE       LL_USART_DisableIT_TCBGT
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableIT_TCBGT(USART_TypeDef *USARTx)
-{
-  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_TCBGTIE);
-}
-
-/**
-  * @brief  Disable RX FIFO Threshold Interrupt
-  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
-  *         FIFO mode feature is supported by the USARTx instance.
-  * @rmtoll CR3          RXFTIE        LL_USART_DisableIT_RXFT
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableIT_RXFT(USART_TypeDef *USARTx)
-{
-  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_RXFTIE);
-}
-
-/**
-  * @brief  Check if the USART IDLE Interrupt  source is enabled or disabled.
-  * @rmtoll CR1          IDLEIE        LL_USART_IsEnabledIT_IDLE
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL);
-}
-
-/* Legacy define */
-#define LL_USART_IsEnabledIT_RXNE  LL_USART_IsEnabledIT_RXNE_RXFNE
-
-/**
-  * @brief  Check if the USART RX Not Empty and USART RX FIFO Not Empty Interrupt is enabled or disabled.
-  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
-  *         FIFO mode feature is supported by the USARTx instance.
-  * @rmtoll CR1        RXNEIE_RXFNEIE  LL_USART_IsEnabledIT_RXNE_RXFNE
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE_RXFNE(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART Transmission Complete Interrupt is enabled or disabled.
-  * @rmtoll CR1          TCIE          LL_USART_IsEnabledIT_TC
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL);
-}
-
-/* Legacy define */
-#define LL_USART_IsEnabledIT_TXE  LL_USART_IsEnabledIT_TXE_TXFNF
-
-/**
-  * @brief  Check if the USART TX Empty and USART TX FIFO Not Full Interrupt is enabled or disabled
-  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
-  *         FIFO mode feature is supported by the USARTx instance.
-  * @rmtoll CR1         TXEIE_TXFNFIE  LL_USART_IsEnabledIT_TXE_TXFNF
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE_TXFNF(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART Parity Error Interrupt is enabled or disabled.
-  * @rmtoll CR1          PEIE          LL_USART_IsEnabledIT_PE
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART Character Match Interrupt is enabled or disabled.
-  * @rmtoll CR1          CMIE          LL_USART_IsEnabledIT_CM
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART Receiver Timeout Interrupt is enabled or disabled.
-  * @rmtoll CR1          RTOIE         LL_USART_IsEnabledIT_RTO
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR1, USART_CR1_RTOIE) == (USART_CR1_RTOIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART End Of Block Interrupt is enabled or disabled.
-  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll CR1          EOBIE         LL_USART_IsEnabledIT_EOB
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR1, USART_CR1_EOBIE) == (USART_CR1_EOBIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART TX FIFO Empty Interrupt is enabled or disabled
-  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
-  *         FIFO mode feature is supported by the USARTx instance.
-  * @rmtoll CR1          TXFEIE        LL_USART_IsEnabledIT_TXFE
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFE(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART RX FIFO Full Interrupt is enabled or disabled
-  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
-  *         FIFO mode feature is supported by the USARTx instance.
-  * @rmtoll CR1          RXFFIE        LL_USART_IsEnabledIT_RXFF
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFF(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART LIN Break Detection Interrupt is enabled or disabled.
-  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
-  *         LIN feature is supported by the USARTx instance.
-  * @rmtoll CR2          LBDIE         LL_USART_IsEnabledIT_LBD
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART Error Interrupt is enabled or disabled.
-  * @rmtoll CR3          EIE           LL_USART_IsEnabledIT_ERROR
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART CTS Interrupt is enabled or disabled.
-  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
-  *         Hardware Flow control feature is supported by the USARTx instance.
-  * @rmtoll CR3          CTSIE         LL_USART_IsEnabledIT_CTS
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART Wake Up from Stop Mode Interrupt is enabled or disabled.
-  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
-  *         Wake-up from Stop mode feature is supported by the USARTx instance.
-  * @rmtoll CR3          WUFIE         LL_USART_IsEnabledIT_WKUP
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if USART TX FIFO Threshold Interrupt is enabled or disabled
-  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
-  *         FIFO mode feature is supported by the USARTx instance.
-  * @rmtoll CR3          TXFTIE        LL_USART_IsEnabledIT_TXFT
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFT(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the Smartcard Transmission Complete Before Guard Time Interrupt is enabled or disabled.
-  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll CR3          TCBGTIE       LL_USART_IsEnabledIT_TCBGT
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR3, USART_CR3_TCBGTIE) == (USART_CR3_TCBGTIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if USART RX FIFO Threshold Interrupt is enabled or disabled
-  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
-  *         FIFO mode feature is supported by the USARTx instance.
-  * @rmtoll CR3          RXFTIE        LL_USART_IsEnabledIT_RXFT
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFT(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EF_DMA_Management DMA_Management
-  * @{
-  */
-
-/**
-  * @brief  Enable DMA Mode for reception
-  * @rmtoll CR3          DMAR          LL_USART_EnableDMAReq_RX
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx)
-{
-  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAR);
-}
-
-/**
-  * @brief  Disable DMA Mode for reception
-  * @rmtoll CR3          DMAR          LL_USART_DisableDMAReq_RX
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx)
-{
-  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR);
-}
-
-/**
-  * @brief  Check if DMA Mode is enabled for reception
-  * @rmtoll CR3          DMAR          LL_USART_IsEnabledDMAReq_RX
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable DMA Mode for transmission
-  * @rmtoll CR3          DMAT          LL_USART_EnableDMAReq_TX
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx)
-{
-  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAT);
-}
-
-/**
-  * @brief  Disable DMA Mode for transmission
-  * @rmtoll CR3          DMAT          LL_USART_DisableDMAReq_TX
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx)
-{
-  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT);
-}
-
-/**
-  * @brief  Check if DMA Mode is enabled for transmission
-  * @rmtoll CR3          DMAT          LL_USART_IsEnabledDMAReq_TX
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable DMA Disabling on Reception Error
-  * @rmtoll CR3          DDRE          LL_USART_EnableDMADeactOnRxErr
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableDMADeactOnRxErr(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR3, USART_CR3_DDRE);
-}
-
-/**
-  * @brief  Disable DMA Disabling on Reception Error
-  * @rmtoll CR3          DDRE          LL_USART_DisableDMADeactOnRxErr
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableDMADeactOnRxErr(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR3, USART_CR3_DDRE);
-}
-
-/**
-  * @brief  Indicate if DMA Disabling on Reception Error is disabled
-  * @rmtoll CR3          DDRE          LL_USART_IsEnabledDMADeactOnRxErr
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get the data register address used for DMA transfer
-  * @rmtoll RDR          RDR           LL_USART_DMA_GetRegAddr\n
-  * @rmtoll TDR          TDR           LL_USART_DMA_GetRegAddr
-  * @param  USARTx USART Instance
-  * @param  Direction This parameter can be one of the following values:
-  *         @arg @ref LL_USART_DMA_REG_DATA_TRANSMIT
-  *         @arg @ref LL_USART_DMA_REG_DATA_RECEIVE
-  * @retval Address of data register
-  */
-__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx, uint32_t Direction)
-{
-  uint32_t data_reg_addr;
-
-  if (Direction == LL_USART_DMA_REG_DATA_TRANSMIT)
-  {
-    /* return address of TDR register */
-    data_reg_addr = (uint32_t) &(USARTx->TDR);
-  }
-  else
-  {
-    /* return address of RDR register */
-    data_reg_addr = (uint32_t) &(USARTx->RDR);
-  }
-
-  return data_reg_addr;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EF_Data_Management Data_Management
-  * @{
-  */
-
-/**
-  * @brief  Read Receiver Data register (Receive Data value, 8 bits)
-  * @rmtoll RDR          RDR           LL_USART_ReceiveData8
-  * @param  USARTx USART Instance
-  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
-  */
-__STATIC_INLINE uint8_t LL_USART_ReceiveData8(USART_TypeDef *USARTx)
-{
-  return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR) & 0xFFU);
-}
-
-/**
-  * @brief  Read Receiver Data register (Receive Data value, 9 bits)
-  * @rmtoll RDR          RDR           LL_USART_ReceiveData9
-  * @param  USARTx USART Instance
-  * @retval Value between Min_Data=0x00 and Max_Data=0x1FF
-  */
-__STATIC_INLINE uint16_t LL_USART_ReceiveData9(USART_TypeDef *USARTx)
-{
-  return (uint16_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR));
-}
-
-/**
-  * @brief  Write in Transmitter Data Register (Transmit Data value, 8 bits)
-  * @rmtoll TDR          TDR           LL_USART_TransmitData8
-  * @param  USARTx USART Instance
-  * @param  Value between Min_Data=0x00 and Max_Data=0xFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_TransmitData8(USART_TypeDef *USARTx, uint8_t Value)
-{
-  USARTx->TDR = Value;
-}
-
-/**
-  * @brief  Write in Transmitter Data Register (Transmit Data value, 9 bits)
-  * @rmtoll TDR          TDR           LL_USART_TransmitData9
-  * @param  USARTx USART Instance
-  * @param  Value between Min_Data=0x00 and Max_Data=0x1FF
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Value)
-{
-  USARTx->TDR = (uint16_t)(Value & 0x1FFUL);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EF_Execution Execution
-  * @{
-  */
-
-/**
-  * @brief  Request an Automatic Baud Rate measurement on next received data frame
-  * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
-  *         Auto Baud Rate detection feature is supported by the USARTx instance.
-  * @rmtoll RQR          ABRRQ         LL_USART_RequestAutoBaudRate
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_RequestAutoBaudRate(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_ABRRQ);
-}
-
-/**
-  * @brief  Request Break sending
-  * @rmtoll RQR          SBKRQ         LL_USART_RequestBreakSending
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_RequestBreakSending(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_SBKRQ);
-}
-
-/**
-  * @brief  Put USART in mute mode and set the RWU flag
-  * @rmtoll RQR          MMRQ          LL_USART_RequestEnterMuteMode
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_RequestEnterMuteMode(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_MMRQ);
-}
-
-/**
-  * @brief  Request a Receive Data and FIFO flush
-  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
-  *         FIFO mode feature is supported by the USARTx instance.
-  * @note   Allows to discard the received data without reading them, and avoid an overrun
-  *         condition.
-  * @rmtoll RQR          RXFRQ         LL_USART_RequestRxDataFlush
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_RequestRxDataFlush(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_RXFRQ);
-}
-
-/**
-  * @brief  Request a Transmit data and FIFO flush
-  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
-  *         FIFO mode feature is supported by the USARTx instance.
-  * @rmtoll RQR          TXFRQ         LL_USART_RequestTxDataFlush
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_RequestTxDataFlush(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_TXFRQ);
-}
-
-/**
-  * @}
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup USART_LL_EF_Init Initialization and de-initialization functions
-  * @{
-  */
-ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx);
-ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct);
-void        LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct);
-ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
-void        LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* USART1 || USART2 || USART3 || USART6 || UART4 || UART5 || UART7 || UART8 || UART9 || USART10 */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32H7xx_LL_USART_H */
-
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_ll_usart.h
+  * @author  MCD Application Team
+  * @brief   Header file of USART LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_LL_USART_H
+#define STM32H7xx_LL_USART_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx.h"
+
+/** @addtogroup STM32H7xx_LL_Driver
+  * @{
+  */
+
+#if defined (USART1) || defined (USART2) || defined (USART3) || defined (USART6) || defined (UART4) || defined (UART5) || defined (UART7) || defined (UART8) || defined (UART9) || defined (USART10)
+
+/** @defgroup USART_LL USART
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup USART_LL_Private_Variables USART Private Variables
+  * @{
+  */
+/* Array used to get the USART prescaler division decimal values versus @ref USART_LL_EC_PRESCALER values */
+static const uint32_t USART_PRESCALER_TAB[] =
+{
+  1UL,
+  2UL,
+  4UL,
+  6UL,
+  8UL,
+  10UL,
+  12UL,
+  16UL,
+  32UL,
+  64UL,
+  128UL,
+  256UL
+};
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_Private_Macros USART Private Macros
+  * @{
+  */
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_ES_INIT USART Exported Init structures
+  * @{
+  */
+
+/**
+  * @brief LL USART Init Structure definition
+  */
+typedef struct
+{
+  uint32_t PrescalerValue;            /*!< Specifies the Prescaler to compute the communication baud rate.
+                                           This parameter can be a value of @ref USART_LL_EC_PRESCALER.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_USART_SetPrescaler().*/
+
+  uint32_t BaudRate;                  /*!< This field defines expected Usart communication baud rate.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_USART_SetBaudRate().*/
+
+  uint32_t DataWidth;                 /*!< Specifies the number of data bits transmitted or received in a frame.
+                                           This parameter can be a value of @ref USART_LL_EC_DATAWIDTH.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_USART_SetDataWidth().*/
+
+  uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
+                                           This parameter can be a value of @ref USART_LL_EC_STOPBITS.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_USART_SetStopBitsLength().*/
+
+  uint32_t Parity;                    /*!< Specifies the parity mode.
+                                           This parameter can be a value of @ref USART_LL_EC_PARITY.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_USART_SetParity().*/
+
+  uint32_t TransferDirection;         /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
+                                           This parameter can be a value of @ref USART_LL_EC_DIRECTION.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_USART_SetTransferDirection().*/
+
+  uint32_t HardwareFlowControl;       /*!< Specifies whether the hardware flow control mode is enabled or disabled.
+                                           This parameter can be a value of @ref USART_LL_EC_HWCONTROL.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_USART_SetHWFlowCtrl().*/
+
+  uint32_t OverSampling;              /*!< Specifies whether USART oversampling mode is 16 or 8.
+                                           This parameter can be a value of @ref USART_LL_EC_OVERSAMPLING.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_USART_SetOverSampling().*/
+
+} LL_USART_InitTypeDef;
+
+/**
+  * @brief LL USART Clock Init Structure definition
+  */
+typedef struct
+{
+  uint32_t ClockOutput;               /*!< Specifies whether the USART clock is enabled or disabled.
+                                           This parameter can be a value of @ref USART_LL_EC_CLOCK.
+
+                                           USART HW configuration can be modified afterwards using unitary functions
+                                           @ref LL_USART_EnableSCLKOutput() or @ref LL_USART_DisableSCLKOutput().
+                                           For more details, refer to description of this function. */
+
+  uint32_t ClockPolarity;             /*!< Specifies the steady state of the serial clock.
+                                           This parameter can be a value of @ref USART_LL_EC_POLARITY.
+
+                                           USART HW configuration can be modified afterwards using unitary
+                                           functions @ref LL_USART_SetClockPolarity().
+                                           For more details, refer to description of this function. */
+
+  uint32_t ClockPhase;                /*!< Specifies the clock transition on which the bit capture is made.
+                                           This parameter can be a value of @ref USART_LL_EC_PHASE.
+
+                                           USART HW configuration can be modified afterwards using unitary
+                                           functions @ref LL_USART_SetClockPhase().
+                                           For more details, refer to description of this function. */
+
+  uint32_t LastBitClockPulse;         /*!< Specifies whether the clock pulse corresponding to the last transmitted
+                                           data bit (MSB) has to be output on the SCLK pin in synchronous mode.
+                                           This parameter can be a value of @ref USART_LL_EC_LASTCLKPULSE.
+
+                                           USART HW configuration can be modified afterwards using unitary
+                                           functions @ref LL_USART_SetLastClkPulseOutput().
+                                           For more details, refer to description of this function. */
+
+} LL_USART_ClockInitTypeDef;
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup USART_LL_Exported_Constants USART Exported Constants
+  * @{
+  */
+
+/** @defgroup USART_LL_EC_CLEAR_FLAG Clear Flags Defines
+  * @brief    Flags defines which can be used with LL_USART_WriteReg function
+  * @{
+  */
+#define LL_USART_ICR_PECF                       USART_ICR_PECF                /*!< Parity error clear flag */
+#define LL_USART_ICR_FECF                       USART_ICR_FECF                /*!< Framing error clear flag */
+#define LL_USART_ICR_NECF                       USART_ICR_NECF                /*!< Noise error detected clear flag */
+#define LL_USART_ICR_ORECF                      USART_ICR_ORECF               /*!< Overrun error clear flag */
+#define LL_USART_ICR_IDLECF                     USART_ICR_IDLECF              /*!< Idle line detected clear flag */
+#define LL_USART_ICR_TXFECF                     USART_ICR_TXFECF              /*!< TX FIFO Empty clear flag */
+#define LL_USART_ICR_TCCF                       USART_ICR_TCCF                /*!< Transmission complete clear flag */
+#define LL_USART_ICR_TCBGTCF                    USART_ICR_TCBGTCF             /*!< Transmission completed before guard time clear flag */
+#define LL_USART_ICR_LBDCF                      USART_ICR_LBDCF               /*!< LIN break detection clear flag */
+#define LL_USART_ICR_CTSCF                      USART_ICR_CTSCF               /*!< CTS clear flag */
+#define LL_USART_ICR_RTOCF                      USART_ICR_RTOCF               /*!< Receiver timeout clear flag */
+#define LL_USART_ICR_EOBCF                      USART_ICR_EOBCF               /*!< End of block clear flag */
+#define LL_USART_ICR_UDRCF                      USART_ICR_UDRCF               /*!< SPI Slave Underrun clear flag */
+#define LL_USART_ICR_CMCF                       USART_ICR_CMCF                /*!< Character match clear flag */
+#define LL_USART_ICR_WUCF                       USART_ICR_WUCF                /*!< Wakeup from Stop mode clear flag */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_USART_ReadReg function
+  * @{
+  */
+#define LL_USART_ISR_PE                         USART_ISR_PE                  /*!< Parity error flag */
+#define LL_USART_ISR_FE                         USART_ISR_FE                  /*!< Framing error flag */
+#define LL_USART_ISR_NE                         USART_ISR_NE                  /*!< Noise detected flag */
+#define LL_USART_ISR_ORE                        USART_ISR_ORE                 /*!< Overrun error flag */
+#define LL_USART_ISR_IDLE                       USART_ISR_IDLE                /*!< Idle line detected flag */
+#define LL_USART_ISR_RXNE_RXFNE                 USART_ISR_RXNE_RXFNE          /*!< Read data register or RX FIFO not empty flag */
+#define LL_USART_ISR_TC                         USART_ISR_TC                  /*!< Transmission complete flag */
+#define LL_USART_ISR_TXE_TXFNF                  USART_ISR_TXE_TXFNF           /*!< Transmit data register empty or TX FIFO Not Full flag*/
+#define LL_USART_ISR_LBDF                       USART_ISR_LBDF                /*!< LIN break detection flag */
+#define LL_USART_ISR_CTSIF                      USART_ISR_CTSIF               /*!< CTS interrupt flag */
+#define LL_USART_ISR_CTS                        USART_ISR_CTS                 /*!< CTS flag */
+#define LL_USART_ISR_RTOF                       USART_ISR_RTOF                /*!< Receiver timeout flag */
+#define LL_USART_ISR_EOBF                       USART_ISR_EOBF                /*!< End of block flag */
+#define LL_USART_ISR_UDR                        USART_ISR_UDR                 /*!< SPI Slave underrun error flag */
+#define LL_USART_ISR_ABRE                       USART_ISR_ABRE                /*!< Auto baud rate error flag */
+#define LL_USART_ISR_ABRF                       USART_ISR_ABRF                /*!< Auto baud rate flag */
+#define LL_USART_ISR_BUSY                       USART_ISR_BUSY                /*!< Busy flag */
+#define LL_USART_ISR_CMF                        USART_ISR_CMF                 /*!< Character match flag */
+#define LL_USART_ISR_SBKF                       USART_ISR_SBKF                /*!< Send break flag */
+#define LL_USART_ISR_RWU                        USART_ISR_RWU                 /*!< Receiver wakeup from Mute mode flag */
+#define LL_USART_ISR_WUF                        USART_ISR_WUF                 /*!< Wakeup from Stop mode flag */
+#define LL_USART_ISR_TEACK                      USART_ISR_TEACK               /*!< Transmit enable acknowledge flag */
+#define LL_USART_ISR_REACK                      USART_ISR_REACK               /*!< Receive enable acknowledge flag */
+#define LL_USART_ISR_TXFE                       USART_ISR_TXFE                /*!< TX FIFO empty flag */
+#define LL_USART_ISR_RXFF                       USART_ISR_RXFF                /*!< RX FIFO full flag */
+#define LL_USART_ISR_TCBGT                      USART_ISR_TCBGT               /*!< Transmission complete before guard time completion flag */
+#define LL_USART_ISR_RXFT                       USART_ISR_RXFT                /*!< RX FIFO threshold flag */
+#define LL_USART_ISR_TXFT                       USART_ISR_TXFT                /*!< TX FIFO threshold flag */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_USART_ReadReg and  LL_USART_WriteReg functions
+  * @{
+  */
+#define LL_USART_CR1_IDLEIE                     USART_CR1_IDLEIE              /*!< IDLE interrupt enable */
+#define LL_USART_CR1_RXNEIE_RXFNEIE             USART_CR1_RXNEIE_RXFNEIE      /*!< Read data register and RXFIFO not empty interrupt enable */
+#define LL_USART_CR1_TCIE                       USART_CR1_TCIE                /*!< Transmission complete interrupt enable */
+#define LL_USART_CR1_TXEIE_TXFNFIE              USART_CR1_TXEIE_TXFNFIE       /*!< Transmit data register empty and TX FIFO not full interrupt enable */
+#define LL_USART_CR1_PEIE                       USART_CR1_PEIE                /*!< Parity error */
+#define LL_USART_CR1_CMIE                       USART_CR1_CMIE                /*!< Character match interrupt enable */
+#define LL_USART_CR1_RTOIE                      USART_CR1_RTOIE               /*!< Receiver timeout interrupt enable */
+#define LL_USART_CR1_EOBIE                      USART_CR1_EOBIE               /*!< End of Block interrupt enable */
+#define LL_USART_CR1_TXFEIE                     USART_CR1_TXFEIE              /*!< TX FIFO empty interrupt enable */
+#define LL_USART_CR1_RXFFIE                     USART_CR1_RXFFIE              /*!< RX FIFO full interrupt enable */
+#define LL_USART_CR2_LBDIE                      USART_CR2_LBDIE               /*!< LIN break detection interrupt enable */
+#define LL_USART_CR3_EIE                        USART_CR3_EIE                 /*!< Error interrupt enable */
+#define LL_USART_CR3_CTSIE                      USART_CR3_CTSIE               /*!< CTS interrupt enable */
+#define LL_USART_CR3_WUFIE                      USART_CR3_WUFIE               /*!< Wakeup from Stop mode interrupt enable */
+#define LL_USART_CR3_TXFTIE                     USART_CR3_TXFTIE              /*!< TX FIFO threshold interrupt enable */
+#define LL_USART_CR3_TCBGTIE                    USART_CR3_TCBGTIE             /*!< Transmission complete before guard time interrupt enable */
+#define LL_USART_CR3_RXFTIE                     USART_CR3_RXFTIE              /*!< RX FIFO threshold interrupt enable */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_FIFOTHRESHOLD FIFO Threshold
+  * @{
+  */
+#define LL_USART_FIFOTHRESHOLD_1_8              0x00000000U /*!< FIFO reaches 1/8 of its depth */
+#define LL_USART_FIFOTHRESHOLD_1_4              0x00000001U /*!< FIFO reaches 1/4 of its depth */
+#define LL_USART_FIFOTHRESHOLD_1_2              0x00000002U /*!< FIFO reaches 1/2 of its depth */
+#define LL_USART_FIFOTHRESHOLD_3_4              0x00000003U /*!< FIFO reaches 3/4 of its depth */
+#define LL_USART_FIFOTHRESHOLD_7_8              0x00000004U /*!< FIFO reaches 7/8 of its depth */
+#define LL_USART_FIFOTHRESHOLD_8_8              0x00000005U /*!< FIFO becomes empty for TX and full for RX */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_DIRECTION Communication Direction
+  * @{
+  */
+#define LL_USART_DIRECTION_NONE                 0x00000000U                        /*!< Transmitter and Receiver are disabled */
+#define LL_USART_DIRECTION_RX                   USART_CR1_RE                       /*!< Transmitter is disabled and Receiver is enabled */
+#define LL_USART_DIRECTION_TX                   USART_CR1_TE                       /*!< Transmitter is enabled and Receiver is disabled */
+#define LL_USART_DIRECTION_TX_RX                (USART_CR1_TE |USART_CR1_RE)       /*!< Transmitter and Receiver are enabled */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_PARITY Parity Control
+  * @{
+  */
+#define LL_USART_PARITY_NONE                    0x00000000U                          /*!< Parity control disabled */
+#define LL_USART_PARITY_EVEN                    USART_CR1_PCE                        /*!< Parity control enabled and Even Parity is selected */
+#define LL_USART_PARITY_ODD                     (USART_CR1_PCE | USART_CR1_PS)       /*!< Parity control enabled and Odd Parity is selected */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_WAKEUP Wakeup
+  * @{
+  */
+#define LL_USART_WAKEUP_IDLELINE                0x00000000U           /*!<  USART wake up from Mute mode on Idle Line */
+#define LL_USART_WAKEUP_ADDRESSMARK             USART_CR1_WAKE        /*!<  USART wake up from Mute mode on Address Mark */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_DATAWIDTH Datawidth
+  * @{
+  */
+#define LL_USART_DATAWIDTH_7B                   USART_CR1_M1            /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */
+#define LL_USART_DATAWIDTH_8B                   0x00000000U             /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
+#define LL_USART_DATAWIDTH_9B                   USART_CR1_M0            /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_OVERSAMPLING Oversampling
+  * @{
+  */
+#define LL_USART_OVERSAMPLING_16                0x00000000U            /*!< Oversampling by 16 */
+#define LL_USART_OVERSAMPLING_8                 USART_CR1_OVER8        /*!< Oversampling by 8 */
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_EC_CLOCK Clock Signal
+  * @{
+  */
+
+#define LL_USART_CLOCK_DISABLE                  0x00000000U            /*!< Clock signal not provided */
+#define LL_USART_CLOCK_ENABLE                   USART_CR2_CLKEN        /*!< Clock signal provided */
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse
+  * @{
+  */
+#define LL_USART_LASTCLKPULSE_NO_OUTPUT         0x00000000U           /*!< The clock pulse of the last data bit is not output to the SCLK pin */
+#define LL_USART_LASTCLKPULSE_OUTPUT            USART_CR2_LBCL        /*!< The clock pulse of the last data bit is output to the SCLK pin */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_PHASE Clock Phase
+  * @{
+  */
+#define LL_USART_PHASE_1EDGE                    0x00000000U           /*!< The first clock transition is the first data capture edge */
+#define LL_USART_PHASE_2EDGE                    USART_CR2_CPHA        /*!< The second clock transition is the first data capture edge */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_POLARITY Clock Polarity
+  * @{
+  */
+#define LL_USART_POLARITY_LOW                   0x00000000U           /*!< Steady low value on SCLK pin outside transmission window*/
+#define LL_USART_POLARITY_HIGH                  USART_CR2_CPOL        /*!< Steady high value on SCLK pin outside transmission window */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_PRESCALER Clock Source Prescaler
+  * @{
+  */
+#define LL_USART_PRESCALER_DIV1                 0x00000000U                                                                   /*!< Input clock not divided   */
+#define LL_USART_PRESCALER_DIV2                 (USART_PRESC_PRESCALER_0)                                                     /*!< Input clock divided by 2  */
+#define LL_USART_PRESCALER_DIV4                 (USART_PRESC_PRESCALER_1)                                                     /*!< Input clock divided by 4  */
+#define LL_USART_PRESCALER_DIV6                 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)                           /*!< Input clock divided by 6  */
+#define LL_USART_PRESCALER_DIV8                 (USART_PRESC_PRESCALER_2)                                                     /*!< Input clock divided by 8  */
+#define LL_USART_PRESCALER_DIV10                (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0)                           /*!< Input clock divided by 10 */
+#define LL_USART_PRESCALER_DIV12                (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1)                           /*!< Input clock divided by 12 */
+#define LL_USART_PRESCALER_DIV16                (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 16 */
+#define LL_USART_PRESCALER_DIV32                (USART_PRESC_PRESCALER_3)                                                     /*!< Input clock divided by 32 */
+#define LL_USART_PRESCALER_DIV64                (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0)                           /*!< Input clock divided by 64 */
+#define LL_USART_PRESCALER_DIV128               (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1)                           /*!< Input clock divided by 128 */
+#define LL_USART_PRESCALER_DIV256               (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 256 */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_STOPBITS Stop Bits
+  * @{
+  */
+#define LL_USART_STOPBITS_0_5                   USART_CR2_STOP_0                           /*!< 0.5 stop bit */
+#define LL_USART_STOPBITS_1                     0x00000000U                                /*!< 1 stop bit */
+#define LL_USART_STOPBITS_1_5                   (USART_CR2_STOP_0 | USART_CR2_STOP_1)      /*!< 1.5 stop bits */
+#define LL_USART_STOPBITS_2                     USART_CR2_STOP_1                           /*!< 2 stop bits */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_TXRX TX RX Pins Swap
+  * @{
+  */
+#define LL_USART_TXRX_STANDARD                  0x00000000U           /*!< TX/RX pins are used as defined in standard pinout */
+#define LL_USART_TXRX_SWAPPED                   (USART_CR2_SWAP)      /*!< TX and RX pins functions are swapped.             */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion
+  * @{
+  */
+#define LL_USART_RXPIN_LEVEL_STANDARD           0x00000000U           /*!< RX pin signal works using the standard logic levels */
+#define LL_USART_RXPIN_LEVEL_INVERTED           (USART_CR2_RXINV)     /*!< RX pin signal values are inverted.                  */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion
+  * @{
+  */
+#define LL_USART_TXPIN_LEVEL_STANDARD           0x00000000U           /*!< TX pin signal works using the standard logic levels */
+#define LL_USART_TXPIN_LEVEL_INVERTED           (USART_CR2_TXINV)     /*!< TX pin signal values are inverted.                  */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_BINARY_LOGIC Binary Data Inversion
+  * @{
+  */
+#define LL_USART_BINARY_LOGIC_POSITIVE          0x00000000U           /*!< Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) */
+#define LL_USART_BINARY_LOGIC_NEGATIVE          USART_CR2_DATAINV     /*!< Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_BITORDER Bit Order
+  * @{
+  */
+#define LL_USART_BITORDER_LSBFIRST              0x00000000U           /*!< data is transmitted/received with data bit 0 first, following the start bit */
+#define LL_USART_BITORDER_MSBFIRST              USART_CR2_MSBFIRST    /*!< data is transmitted/received with the MSB first, following the start bit */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_AUTOBAUD_DETECT_ON Autobaud Detection
+  * @{
+  */
+#define LL_USART_AUTOBAUD_DETECT_ON_STARTBIT    0x00000000U                                 /*!< Measurement of the start bit is used to detect the baud rate */
+#define LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE USART_CR2_ABRMODE_0                         /*!< Falling edge to falling edge measurement. Received frame must start with a single bit = 1 -> Frame = Start10xxxxxx */
+#define LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME    USART_CR2_ABRMODE_1                         /*!< 0x7F frame detection */
+#define LL_USART_AUTOBAUD_DETECT_ON_55_FRAME    (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0) /*!< 0x55 frame detection */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_ADDRESS_DETECT Address Length Detection
+  * @{
+  */
+#define LL_USART_ADDRESS_DETECT_4B              0x00000000U           /*!< 4-bit address detection method selected */
+#define LL_USART_ADDRESS_DETECT_7B              USART_CR2_ADDM7       /*!< 7-bit address detection (in 8-bit data mode) method selected */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_HWCONTROL Hardware Control
+  * @{
+  */
+#define LL_USART_HWCONTROL_NONE                 0x00000000U                          /*!< CTS and RTS hardware flow control disabled */
+#define LL_USART_HWCONTROL_RTS                  USART_CR3_RTSE                       /*!< RTS output enabled, data is only requested when there is space in the receive buffer */
+#define LL_USART_HWCONTROL_CTS                  USART_CR3_CTSE                       /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */
+#define LL_USART_HWCONTROL_RTS_CTS              (USART_CR3_RTSE | USART_CR3_CTSE)    /*!< CTS and RTS hardware flow control enabled */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_WAKEUP_ON Wakeup Activation
+  * @{
+  */
+#define LL_USART_WAKEUP_ON_ADDRESS              0x00000000U                             /*!< Wake up active on address match */
+#define LL_USART_WAKEUP_ON_STARTBIT             USART_CR3_WUS_1                         /*!< Wake up active on Start bit detection */
+#define LL_USART_WAKEUP_ON_RXNE                 (USART_CR3_WUS_0 | USART_CR3_WUS_1)     /*!< Wake up active on RXNE */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_IRDA_POWER IrDA Power
+  * @{
+  */
+#define LL_USART_IRDA_POWER_NORMAL              0x00000000U           /*!< IrDA normal power mode */
+#define LL_USART_IRDA_POWER_LOW                 USART_CR3_IRLP        /*!< IrDA low power mode */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length
+  * @{
+  */
+#define LL_USART_LINBREAK_DETECT_10B            0x00000000U           /*!< 10-bit break detection method selected */
+#define LL_USART_LINBREAK_DETECT_11B            USART_CR2_LBDL        /*!< 11-bit break detection method selected */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_DE_POLARITY Driver Enable Polarity
+  * @{
+  */
+#define LL_USART_DE_POLARITY_HIGH               0x00000000U           /*!< DE signal is active high */
+#define LL_USART_DE_POLARITY_LOW                USART_CR3_DEP         /*!< DE signal is active low */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_DMA_REG_DATA DMA Register Data
+  * @{
+  */
+#define LL_USART_DMA_REG_DATA_TRANSMIT          0x00000000U          /*!< Get address of data register used for transmission */
+#define LL_USART_DMA_REG_DATA_RECEIVE           0x00000001U          /*!< Get address of data register used for reception */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup USART_LL_Exported_Macros USART Exported Macros
+  * @{
+  */
+
+/** @defgroup USART_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in USART register
+  * @param  __INSTANCE__ USART Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in USART register
+  * @param  __INSTANCE__ USART Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
+  * @{
+  */
+
+/**
+  * @brief  Compute USARTDIV value according to Peripheral Clock and
+  *         expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned)
+  * @param  __PERIPHCLK__ Peripheral Clock frequency used for USART instance
+  * @param  __PRESCALER__ This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PRESCALER_DIV1
+  *         @arg @ref LL_USART_PRESCALER_DIV2
+  *         @arg @ref LL_USART_PRESCALER_DIV4
+  *         @arg @ref LL_USART_PRESCALER_DIV6
+  *         @arg @ref LL_USART_PRESCALER_DIV8
+  *         @arg @ref LL_USART_PRESCALER_DIV10
+  *         @arg @ref LL_USART_PRESCALER_DIV12
+  *         @arg @ref LL_USART_PRESCALER_DIV16
+  *         @arg @ref LL_USART_PRESCALER_DIV32
+  *         @arg @ref LL_USART_PRESCALER_DIV64
+  *         @arg @ref LL_USART_PRESCALER_DIV128
+  *         @arg @ref LL_USART_PRESCALER_DIV256
+  * @param  __BAUDRATE__ Baud rate value to achieve
+  * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case
+  */
+#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) \
+  (((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))*2U)\
+    + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
+
+/**
+  * @brief  Compute USARTDIV value according to Peripheral Clock and
+  *         expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned)
+  * @param  __PERIPHCLK__ Peripheral Clock frequency used for USART instance
+  * @param  __PRESCALER__ This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PRESCALER_DIV1
+  *         @arg @ref LL_USART_PRESCALER_DIV2
+  *         @arg @ref LL_USART_PRESCALER_DIV4
+  *         @arg @ref LL_USART_PRESCALER_DIV6
+  *         @arg @ref LL_USART_PRESCALER_DIV8
+  *         @arg @ref LL_USART_PRESCALER_DIV10
+  *         @arg @ref LL_USART_PRESCALER_DIV12
+  *         @arg @ref LL_USART_PRESCALER_DIV16
+  *         @arg @ref LL_USART_PRESCALER_DIV32
+  *         @arg @ref LL_USART_PRESCALER_DIV64
+  *         @arg @ref LL_USART_PRESCALER_DIV128
+  *         @arg @ref LL_USART_PRESCALER_DIV256
+  * @param  __BAUDRATE__ Baud rate value to achieve
+  * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case
+  */
+#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) \
+  ((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))\
+    + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup USART_LL_Exported_Functions USART Exported Functions
+  * @{
+  */
+
+/** @defgroup USART_LL_EF_Configuration Configuration functions
+  * @{
+  */
+
+/**
+  * @brief  USART Enable
+  * @rmtoll CR1          UE            LL_USART_Enable
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_Enable(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR1, USART_CR1_UE);
+}
+
+/**
+  * @brief  USART Disable (all USART prescalers and outputs are disabled)
+  * @note   When USART is disabled, USART prescalers and outputs are stopped immediately,
+  *         and current operations are discarded. The configuration of the USART is kept, but all the status
+  *         flags, in the USARTx_ISR are set to their default values.
+  * @rmtoll CR1          UE            LL_USART_Disable
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR1, USART_CR1_UE);
+}
+
+/**
+  * @brief  Indicate if USART is enabled
+  * @rmtoll CR1          UE            LL_USART_IsEnabled
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabled(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  FIFO Mode Enable
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          FIFOEN        LL_USART_EnableFIFO
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableFIFO(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR1, USART_CR1_FIFOEN);
+}
+
+/**
+  * @brief  FIFO Mode Disable
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          FIFOEN        LL_USART_DisableFIFO
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableFIFO(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR1, USART_CR1_FIFOEN);
+}
+
+/**
+  * @brief  Indicate if FIFO Mode is enabled
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          FIFOEN        LL_USART_IsEnabledFIFO
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledFIFO(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Configure TX FIFO Threshold
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          TXFTCFG       LL_USART_SetTXFIFOThreshold
+  * @param  USARTx USART Instance
+  * @param  Threshold This parameter can be one of the following values:
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetTXFIFOThreshold(USART_TypeDef *USARTx, uint32_t Threshold)
+{
+  ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos);
+}
+
+/**
+  * @brief  Return TX FIFO Threshold Configuration
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          TXFTCFG       LL_USART_GetTXFIFOThreshold
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
+  */
+__STATIC_INLINE uint32_t LL_USART_GetTXFIFOThreshold(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
+}
+
+/**
+  * @brief  Configure RX FIFO Threshold
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          RXFTCFG       LL_USART_SetRXFIFOThreshold
+  * @param  USARTx USART Instance
+  * @param  Threshold This parameter can be one of the following values:
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetRXFIFOThreshold(USART_TypeDef *USARTx, uint32_t Threshold)
+{
+  ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos);
+}
+
+/**
+  * @brief  Return RX FIFO Threshold Configuration
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          RXFTCFG       LL_USART_GetRXFIFOThreshold
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
+  */
+__STATIC_INLINE uint32_t LL_USART_GetRXFIFOThreshold(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
+}
+
+/**
+  * @brief  Configure TX and RX FIFOs Threshold
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          TXFTCFG       LL_USART_ConfigFIFOsThreshold\n
+  *         CR3          RXFTCFG       LL_USART_ConfigFIFOsThreshold
+  * @param  USARTx USART Instance
+  * @param  TXThreshold This parameter can be one of the following values:
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
+  * @param  RXThreshold This parameter can be one of the following values:
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigFIFOsThreshold(USART_TypeDef *USARTx, uint32_t TXThreshold, uint32_t RXThreshold)
+{
+  ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) |
+                    (RXThreshold << USART_CR3_RXFTCFG_Pos));
+}
+
+/**
+  * @brief  USART enabled in STOP Mode.
+  * @note   When this function is enabled, USART is able to wake up the MCU from Stop mode, provided that
+  *         USART clock selection is HSI or LSE in RCC.
+  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          UESM          LL_USART_EnableInStopMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableInStopMode(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_UESM);
+}
+
+/**
+  * @brief  USART disabled in STOP Mode.
+  * @note   When this function is disabled, USART is not able to wake up the MCU from Stop mode
+  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          UESM          LL_USART_DisableInStopMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_UESM);
+}
+
+/**
+  * @brief  Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not)
+  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          UESM          LL_USART_IsEnabledInStopMode
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Receiver Enable (Receiver is enabled and begins searching for a start bit)
+  * @rmtoll CR1          RE            LL_USART_EnableDirectionRx
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RE);
+}
+
+/**
+  * @brief  Receiver Disable
+  * @rmtoll CR1          RE            LL_USART_DisableDirectionRx
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RE);
+}
+
+/**
+  * @brief  Transmitter Enable
+  * @rmtoll CR1          TE            LL_USART_EnableDirectionTx
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TE);
+}
+
+/**
+  * @brief  Transmitter Disable
+  * @rmtoll CR1          TE            LL_USART_DisableDirectionTx
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TE);
+}
+
+/**
+  * @brief  Configure simultaneously enabled/disabled states
+  *         of Transmitter and Receiver
+  * @rmtoll CR1          RE            LL_USART_SetTransferDirection\n
+  *         CR1          TE            LL_USART_SetTransferDirection
+  * @param  USARTx USART Instance
+  * @param  TransferDirection This parameter can be one of the following values:
+  *         @arg @ref LL_USART_DIRECTION_NONE
+  *         @arg @ref LL_USART_DIRECTION_RX
+  *         @arg @ref LL_USART_DIRECTION_TX
+  *         @arg @ref LL_USART_DIRECTION_TX_RX
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirection)
+{
+  ATOMIC_MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
+}
+
+/**
+  * @brief  Return enabled/disabled states of Transmitter and Receiver
+  * @rmtoll CR1          RE            LL_USART_GetTransferDirection\n
+  *         CR1          TE            LL_USART_GetTransferDirection
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_DIRECTION_NONE
+  *         @arg @ref LL_USART_DIRECTION_RX
+  *         @arg @ref LL_USART_DIRECTION_TX
+  *         @arg @ref LL_USART_DIRECTION_TX_RX
+  */
+__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE));
+}
+
+/**
+  * @brief  Configure Parity (enabled/disabled and parity mode if enabled).
+  * @note   This function selects if hardware parity control (generation and detection) is enabled or disabled.
+  *         When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position
+  *         (9th or 8th bit depending on data width) and parity is checked on the received data.
+  * @rmtoll CR1          PS            LL_USART_SetParity\n
+  *         CR1          PCE           LL_USART_SetParity
+  * @param  USARTx USART Instance
+  * @param  Parity This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PARITY_NONE
+  *         @arg @ref LL_USART_PARITY_EVEN
+  *         @arg @ref LL_USART_PARITY_ODD
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);
+}
+
+/**
+  * @brief  Return Parity configuration (enabled/disabled and parity mode if enabled)
+  * @rmtoll CR1          PS            LL_USART_GetParity\n
+  *         CR1          PCE           LL_USART_GetParity
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_PARITY_NONE
+  *         @arg @ref LL_USART_PARITY_EVEN
+  *         @arg @ref LL_USART_PARITY_ODD
+  */
+__STATIC_INLINE uint32_t LL_USART_GetParity(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
+}
+
+/**
+  * @brief  Set Receiver Wake Up method from Mute mode.
+  * @rmtoll CR1          WAKE          LL_USART_SetWakeUpMethod
+  * @param  USARTx USART Instance
+  * @param  Method This parameter can be one of the following values:
+  *         @arg @ref LL_USART_WAKEUP_IDLELINE
+  *         @arg @ref LL_USART_WAKEUP_ADDRESSMARK
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Method)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method);
+}
+
+/**
+  * @brief  Return Receiver Wake Up method from Mute mode
+  * @rmtoll CR1          WAKE          LL_USART_GetWakeUpMethod
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_WAKEUP_IDLELINE
+  *         @arg @ref LL_USART_WAKEUP_ADDRESSMARK
+  */
+__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE));
+}
+
+/**
+  * @brief  Set Word length (i.e. nb of data bits, excluding start and stop bits)
+  * @rmtoll CR1          M0            LL_USART_SetDataWidth\n
+  *         CR1          M1            LL_USART_SetDataWidth
+  * @param  USARTx USART Instance
+  * @param  DataWidth This parameter can be one of the following values:
+  *         @arg @ref LL_USART_DATAWIDTH_7B
+  *         @arg @ref LL_USART_DATAWIDTH_8B
+  *         @arg @ref LL_USART_DATAWIDTH_9B
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataWidth)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth);
+}
+
+/**
+  * @brief  Return Word length (i.e. nb of data bits, excluding start and stop bits)
+  * @rmtoll CR1          M0            LL_USART_GetDataWidth\n
+  *         CR1          M1            LL_USART_GetDataWidth
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_DATAWIDTH_7B
+  *         @arg @ref LL_USART_DATAWIDTH_8B
+  *         @arg @ref LL_USART_DATAWIDTH_9B
+  */
+__STATIC_INLINE uint32_t LL_USART_GetDataWidth(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M));
+}
+
+/**
+  * @brief  Allow switch between Mute Mode and Active mode
+  * @rmtoll CR1          MME           LL_USART_EnableMuteMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableMuteMode(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_MME);
+}
+
+/**
+  * @brief  Prevent Mute Mode use. Set Receiver in active mode permanently.
+  * @rmtoll CR1          MME           LL_USART_DisableMuteMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableMuteMode(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_MME);
+}
+
+/**
+  * @brief  Indicate if switch between Mute Mode and Active mode is allowed
+  * @rmtoll CR1          MME           LL_USART_IsEnabledMuteMode
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set Oversampling to 8-bit or 16-bit mode
+  * @rmtoll CR1          OVER8         LL_USART_SetOverSampling
+  * @param  USARTx USART Instance
+  * @param  OverSampling This parameter can be one of the following values:
+  *         @arg @ref LL_USART_OVERSAMPLING_16
+  *         @arg @ref LL_USART_OVERSAMPLING_8
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t OverSampling)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_OVER8, OverSampling);
+}
+
+/**
+  * @brief  Return Oversampling mode
+  * @rmtoll CR1          OVER8         LL_USART_GetOverSampling
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_OVERSAMPLING_16
+  *         @arg @ref LL_USART_OVERSAMPLING_8
+  */
+__STATIC_INLINE uint32_t LL_USART_GetOverSampling(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8));
+}
+
+/**
+  * @brief  Configure if Clock pulse of the last data bit is output to the SCLK pin or not
+  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          LBCL          LL_USART_SetLastClkPulseOutput
+  * @param  USARTx USART Instance
+  * @param  LastBitClockPulse This parameter can be one of the following values:
+  *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
+  *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint32_t LastBitClockPulse)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_LBCL, LastBitClockPulse);
+}
+
+/**
+  * @brief  Retrieve Clock pulse of the last data bit output configuration
+  *         (Last bit Clock pulse output to the SCLK pin or not)
+  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          LBCL          LL_USART_GetLastClkPulseOutput
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
+  *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
+  */
+__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL));
+}
+
+/**
+  * @brief  Select the phase of the clock output on the SCLK pin in synchronous mode
+  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CPHA          LL_USART_SetClockPhase
+  * @param  USARTx USART Instance
+  * @param  ClockPhase This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PHASE_1EDGE
+  *         @arg @ref LL_USART_PHASE_2EDGE
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t ClockPhase)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase);
+}
+
+/**
+  * @brief  Return phase of the clock output on the SCLK pin in synchronous mode
+  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CPHA          LL_USART_GetClockPhase
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_PHASE_1EDGE
+  *         @arg @ref LL_USART_PHASE_2EDGE
+  */
+__STATIC_INLINE uint32_t LL_USART_GetClockPhase(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA));
+}
+
+/**
+  * @brief  Select the polarity of the clock output on the SCLK pin in synchronous mode
+  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CPOL          LL_USART_SetClockPolarity
+  * @param  USARTx USART Instance
+  * @param  ClockPolarity This parameter can be one of the following values:
+  *         @arg @ref LL_USART_POLARITY_LOW
+  *         @arg @ref LL_USART_POLARITY_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t ClockPolarity)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_CPOL, ClockPolarity);
+}
+
+/**
+  * @brief  Return polarity of the clock output on the SCLK pin in synchronous mode
+  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CPOL          LL_USART_GetClockPolarity
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_POLARITY_LOW
+  *         @arg @ref LL_USART_POLARITY_HIGH
+  */
+__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL));
+}
+
+/**
+  * @brief  Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse)
+  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clock Phase configuration using @ref LL_USART_SetClockPhase() function
+  *         - Clock Polarity configuration using @ref LL_USART_SetClockPolarity() function
+  *         - Output of Last bit Clock pulse configuration using @ref LL_USART_SetLastClkPulseOutput() function
+  * @rmtoll CR2          CPHA          LL_USART_ConfigClock\n
+  *         CR2          CPOL          LL_USART_ConfigClock\n
+  *         CR2          LBCL          LL_USART_ConfigClock
+  * @param  USARTx USART Instance
+  * @param  Phase This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PHASE_1EDGE
+  *         @arg @ref LL_USART_PHASE_2EDGE
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_USART_POLARITY_LOW
+  *         @arg @ref LL_USART_POLARITY_HIGH
+  * @param  LBCPOutput This parameter can be one of the following values:
+  *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
+  *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, Phase | Polarity | LBCPOutput);
+}
+
+/**
+  * @brief  Configure Clock source prescaler for baudrate generator and oversampling
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll PRESC        PRESCALER     LL_USART_SetPrescaler
+  * @param  USARTx USART Instance
+  * @param  PrescalerValue This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PRESCALER_DIV1
+  *         @arg @ref LL_USART_PRESCALER_DIV2
+  *         @arg @ref LL_USART_PRESCALER_DIV4
+  *         @arg @ref LL_USART_PRESCALER_DIV6
+  *         @arg @ref LL_USART_PRESCALER_DIV8
+  *         @arg @ref LL_USART_PRESCALER_DIV10
+  *         @arg @ref LL_USART_PRESCALER_DIV12
+  *         @arg @ref LL_USART_PRESCALER_DIV16
+  *         @arg @ref LL_USART_PRESCALER_DIV32
+  *         @arg @ref LL_USART_PRESCALER_DIV64
+  *         @arg @ref LL_USART_PRESCALER_DIV128
+  *         @arg @ref LL_USART_PRESCALER_DIV256
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
+{
+  MODIFY_REG(USARTx->PRESC, USART_PRESC_PRESCALER, (uint16_t)PrescalerValue);
+}
+
+/**
+  * @brief  Retrieve the Clock source prescaler for baudrate generator and oversampling
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll PRESC        PRESCALER     LL_USART_GetPrescaler
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_PRESCALER_DIV1
+  *         @arg @ref LL_USART_PRESCALER_DIV2
+  *         @arg @ref LL_USART_PRESCALER_DIV4
+  *         @arg @ref LL_USART_PRESCALER_DIV6
+  *         @arg @ref LL_USART_PRESCALER_DIV8
+  *         @arg @ref LL_USART_PRESCALER_DIV10
+  *         @arg @ref LL_USART_PRESCALER_DIV12
+  *         @arg @ref LL_USART_PRESCALER_DIV16
+  *         @arg @ref LL_USART_PRESCALER_DIV32
+  *         @arg @ref LL_USART_PRESCALER_DIV64
+  *         @arg @ref LL_USART_PRESCALER_DIV128
+  *         @arg @ref LL_USART_PRESCALER_DIV256
+  */
+__STATIC_INLINE uint32_t LL_USART_GetPrescaler(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->PRESC, USART_PRESC_PRESCALER));
+}
+
+/**
+  * @brief  Enable Clock output on SCLK pin
+  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CLKEN         LL_USART_EnableSCLKOutput
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
+}
+
+/**
+  * @brief  Disable Clock output on SCLK pin
+  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CLKEN         LL_USART_DisableSCLKOutput
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN);
+}
+
+/**
+  * @brief  Indicate if Clock output on SCLK pin is enabled
+  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CLKEN         LL_USART_IsEnabledSCLKOutput
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the length of the stop bits
+  * @rmtoll CR2          STOP          LL_USART_SetStopBitsLength
+  * @param  USARTx USART Instance
+  * @param  StopBits This parameter can be one of the following values:
+  *         @arg @ref LL_USART_STOPBITS_0_5
+  *         @arg @ref LL_USART_STOPBITS_1
+  *         @arg @ref LL_USART_STOPBITS_1_5
+  *         @arg @ref LL_USART_STOPBITS_2
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t StopBits)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
+}
+
+/**
+  * @brief  Retrieve the length of the stop bits
+  * @rmtoll CR2          STOP          LL_USART_GetStopBitsLength
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_STOPBITS_0_5
+  *         @arg @ref LL_USART_STOPBITS_1
+  *         @arg @ref LL_USART_STOPBITS_1_5
+  *         @arg @ref LL_USART_STOPBITS_2
+  */
+__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP));
+}
+
+/**
+  * @brief  Configure Character frame format (Datawidth, Parity control, Stop Bits)
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Data Width configuration using @ref LL_USART_SetDataWidth() function
+  *         - Parity Control and mode configuration using @ref LL_USART_SetParity() function
+  *         - Stop bits configuration using @ref LL_USART_SetStopBitsLength() function
+  * @rmtoll CR1          PS            LL_USART_ConfigCharacter\n
+  *         CR1          PCE           LL_USART_ConfigCharacter\n
+  *         CR1          M0            LL_USART_ConfigCharacter\n
+  *         CR1          M1            LL_USART_ConfigCharacter\n
+  *         CR2          STOP          LL_USART_ConfigCharacter
+  * @param  USARTx USART Instance
+  * @param  DataWidth This parameter can be one of the following values:
+  *         @arg @ref LL_USART_DATAWIDTH_7B
+  *         @arg @ref LL_USART_DATAWIDTH_8B
+  *         @arg @ref LL_USART_DATAWIDTH_9B
+  * @param  Parity This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PARITY_NONE
+  *         @arg @ref LL_USART_PARITY_EVEN
+  *         @arg @ref LL_USART_PARITY_ODD
+  * @param  StopBits This parameter can be one of the following values:
+  *         @arg @ref LL_USART_STOPBITS_0_5
+  *         @arg @ref LL_USART_STOPBITS_1
+  *         @arg @ref LL_USART_STOPBITS_1_5
+  *         @arg @ref LL_USART_STOPBITS_2
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigCharacter(USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity,
+                                              uint32_t StopBits)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);
+  MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
+}
+
+/**
+  * @brief  Configure TX/RX pins swapping setting.
+  * @rmtoll CR2          SWAP          LL_USART_SetTXRXSwap
+  * @param  USARTx USART Instance
+  * @param  SwapConfig This parameter can be one of the following values:
+  *         @arg @ref LL_USART_TXRX_STANDARD
+  *         @arg @ref LL_USART_TXRX_SWAPPED
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetTXRXSwap(USART_TypeDef *USARTx, uint32_t SwapConfig)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_SWAP, SwapConfig);
+}
+
+/**
+  * @brief  Retrieve TX/RX pins swapping configuration.
+  * @rmtoll CR2          SWAP          LL_USART_GetTXRXSwap
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_TXRX_STANDARD
+  *         @arg @ref LL_USART_TXRX_SWAPPED
+  */
+__STATIC_INLINE uint32_t LL_USART_GetTXRXSwap(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_SWAP));
+}
+
+/**
+  * @brief  Configure RX pin active level logic
+  * @rmtoll CR2          RXINV         LL_USART_SetRXPinLevel
+  * @param  USARTx USART Instance
+  * @param  PinInvMethod This parameter can be one of the following values:
+  *         @arg @ref LL_USART_RXPIN_LEVEL_STANDARD
+  *         @arg @ref LL_USART_RXPIN_LEVEL_INVERTED
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetRXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_RXINV, PinInvMethod);
+}
+
+/**
+  * @brief  Retrieve RX pin active level logic configuration
+  * @rmtoll CR2          RXINV         LL_USART_GetRXPinLevel
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_RXPIN_LEVEL_STANDARD
+  *         @arg @ref LL_USART_RXPIN_LEVEL_INVERTED
+  */
+__STATIC_INLINE uint32_t LL_USART_GetRXPinLevel(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_RXINV));
+}
+
+/**
+  * @brief  Configure TX pin active level logic
+  * @rmtoll CR2          TXINV         LL_USART_SetTXPinLevel
+  * @param  USARTx USART Instance
+  * @param  PinInvMethod This parameter can be one of the following values:
+  *         @arg @ref LL_USART_TXPIN_LEVEL_STANDARD
+  *         @arg @ref LL_USART_TXPIN_LEVEL_INVERTED
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetTXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_TXINV, PinInvMethod);
+}
+
+/**
+  * @brief  Retrieve TX pin active level logic configuration
+  * @rmtoll CR2          TXINV         LL_USART_GetTXPinLevel
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_TXPIN_LEVEL_STANDARD
+  *         @arg @ref LL_USART_TXPIN_LEVEL_INVERTED
+  */
+__STATIC_INLINE uint32_t LL_USART_GetTXPinLevel(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_TXINV));
+}
+
+/**
+  * @brief  Configure Binary data logic.
+  * @note   Allow to define how Logical data from the data register are send/received :
+  *         either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)
+  * @rmtoll CR2          DATAINV       LL_USART_SetBinaryDataLogic
+  * @param  USARTx USART Instance
+  * @param  DataLogic This parameter can be one of the following values:
+  *         @arg @ref LL_USART_BINARY_LOGIC_POSITIVE
+  *         @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetBinaryDataLogic(USART_TypeDef *USARTx, uint32_t DataLogic)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_DATAINV, DataLogic);
+}
+
+/**
+  * @brief  Retrieve Binary data configuration
+  * @rmtoll CR2          DATAINV       LL_USART_GetBinaryDataLogic
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_BINARY_LOGIC_POSITIVE
+  *         @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE
+  */
+__STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_DATAINV));
+}
+
+/**
+  * @brief  Configure transfer bit order (either Less or Most Significant Bit First)
+  * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.
+  *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.
+  * @rmtoll CR2          MSBFIRST      LL_USART_SetTransferBitOrder
+  * @param  USARTx USART Instance
+  * @param  BitOrder This parameter can be one of the following values:
+  *         @arg @ref LL_USART_BITORDER_LSBFIRST
+  *         @arg @ref LL_USART_BITORDER_MSBFIRST
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetTransferBitOrder(USART_TypeDef *USARTx, uint32_t BitOrder)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_MSBFIRST, BitOrder);
+}
+
+/**
+  * @brief  Return transfer bit order (either Less or Most Significant Bit First)
+  * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.
+  *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.
+  * @rmtoll CR2          MSBFIRST      LL_USART_GetTransferBitOrder
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_BITORDER_LSBFIRST
+  *         @arg @ref LL_USART_BITORDER_MSBFIRST
+  */
+__STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_MSBFIRST));
+}
+
+/**
+  * @brief  Enable Auto Baud-Rate Detection
+  * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll CR2          ABREN         LL_USART_EnableAutoBaudRate
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableAutoBaudRate(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR2, USART_CR2_ABREN);
+}
+
+/**
+  * @brief  Disable Auto Baud-Rate Detection
+  * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll CR2          ABREN         LL_USART_DisableAutoBaudRate
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableAutoBaudRate(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR2, USART_CR2_ABREN);
+}
+
+/**
+  * @brief  Indicate if Auto Baud-Rate Detection mechanism is enabled
+  * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll CR2          ABREN         LL_USART_IsEnabledAutoBaud
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR2, USART_CR2_ABREN) == (USART_CR2_ABREN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set Auto Baud-Rate mode bits
+  * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll CR2          ABRMODE       LL_USART_SetAutoBaudRateMode
+  * @param  USARTx USART Instance
+  * @param  AutoBaudRateMode This parameter can be one of the following values:
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetAutoBaudRateMode(USART_TypeDef *USARTx, uint32_t AutoBaudRateMode)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_ABRMODE, AutoBaudRateMode);
+}
+
+/**
+  * @brief  Return Auto Baud-Rate mode
+  * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll CR2          ABRMODE       LL_USART_GetAutoBaudRateMode
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
+  */
+__STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ABRMODE));
+}
+
+/**
+  * @brief  Enable Receiver Timeout
+  * @rmtoll CR2          RTOEN         LL_USART_EnableRxTimeout
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableRxTimeout(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR2, USART_CR2_RTOEN);
+}
+
+/**
+  * @brief  Disable Receiver Timeout
+  * @rmtoll CR2          RTOEN         LL_USART_DisableRxTimeout
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableRxTimeout(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR2, USART_CR2_RTOEN);
+}
+
+/**
+  * @brief  Indicate if Receiver Timeout feature is enabled
+  * @rmtoll CR2          RTOEN         LL_USART_IsEnabledRxTimeout
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR2, USART_CR2_RTOEN) == (USART_CR2_RTOEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set Address of the USART node.
+  * @note   This is used in multiprocessor communication during Mute mode or Stop mode,
+  *         for wake up with address mark detection.
+  * @note   4bits address node is used when 4-bit Address Detection is selected in ADDM7.
+  *         (b7-b4 should be set to 0)
+  *         8bits address node is used when 7-bit Address Detection is selected in ADDM7.
+  *         (This is used in multiprocessor communication during Mute mode or Stop mode,
+  *         for wake up with 7-bit address mark detection.
+  *         The MSB of the character sent by the transmitter should be equal to 1.
+  *         It may also be used for character detection during normal reception,
+  *         Mute mode inactive (for example, end of block detection in ModBus protocol).
+  *         In this case, the whole received character (8-bit) is compared to the ADD[7:0]
+  *         value and CMF flag is set on match)
+  * @rmtoll CR2          ADD           LL_USART_ConfigNodeAddress\n
+  *         CR2          ADDM7         LL_USART_ConfigNodeAddress
+  * @param  USARTx USART Instance
+  * @param  AddressLen This parameter can be one of the following values:
+  *         @arg @ref LL_USART_ADDRESS_DETECT_4B
+  *         @arg @ref LL_USART_ADDRESS_DETECT_7B
+  * @param  NodeAddress 4 or 7 bit Address of the USART node.
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigNodeAddress(USART_TypeDef *USARTx, uint32_t AddressLen, uint32_t NodeAddress)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7,
+             (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos)));
+}
+
+/**
+  * @brief  Return 8 bit Address of the USART node as set in ADD field of CR2.
+  * @note   If 4-bit Address Detection is selected in ADDM7,
+  *         only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)
+  *         If 7-bit Address Detection is selected in ADDM7,
+  *         only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)
+  * @rmtoll CR2          ADD           LL_USART_GetNodeAddress
+  * @param  USARTx USART Instance
+  * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255)
+  */
+__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos);
+}
+
+/**
+  * @brief  Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
+  * @rmtoll CR2          ADDM7         LL_USART_GetNodeAddressLen
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_ADDRESS_DETECT_4B
+  *         @arg @ref LL_USART_ADDRESS_DETECT_7B
+  */
+__STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADDM7));
+}
+
+/**
+  * @brief  Enable RTS HW Flow Control
+  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          RTSE          LL_USART_EnableRTSHWFlowCtrl
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_RTSE);
+}
+
+/**
+  * @brief  Disable RTS HW Flow Control
+  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          RTSE          LL_USART_DisableRTSHWFlowCtrl
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_RTSE);
+}
+
+/**
+  * @brief  Enable CTS HW Flow Control
+  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          CTSE          LL_USART_EnableCTSHWFlowCtrl
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_CTSE);
+}
+
+/**
+  * @brief  Disable CTS HW Flow Control
+  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          CTSE          LL_USART_DisableCTSHWFlowCtrl
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_CTSE);
+}
+
+/**
+  * @brief  Configure HW Flow Control mode (both CTS and RTS)
+  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          RTSE          LL_USART_SetHWFlowCtrl\n
+  *         CR3          CTSE          LL_USART_SetHWFlowCtrl
+  * @param  USARTx USART Instance
+  * @param  HardwareFlowControl This parameter can be one of the following values:
+  *         @arg @ref LL_USART_HWCONTROL_NONE
+  *         @arg @ref LL_USART_HWCONTROL_RTS
+  *         @arg @ref LL_USART_HWCONTROL_CTS
+  *         @arg @ref LL_USART_HWCONTROL_RTS_CTS
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t HardwareFlowControl)
+{
+  MODIFY_REG(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);
+}
+
+/**
+  * @brief  Return HW Flow Control configuration (both CTS and RTS)
+  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          RTSE          LL_USART_GetHWFlowCtrl\n
+  *         CR3          CTSE          LL_USART_GetHWFlowCtrl
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_HWCONTROL_NONE
+  *         @arg @ref LL_USART_HWCONTROL_RTS
+  *         @arg @ref LL_USART_HWCONTROL_CTS
+  *         @arg @ref LL_USART_HWCONTROL_RTS_CTS
+  */
+__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
+}
+
+/**
+  * @brief  Enable One bit sampling method
+  * @rmtoll CR3          ONEBIT        LL_USART_EnableOneBitSamp
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableOneBitSamp(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_ONEBIT);
+}
+
+/**
+  * @brief  Disable One bit sampling method
+  * @rmtoll CR3          ONEBIT        LL_USART_DisableOneBitSamp
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_ONEBIT);
+}
+
+/**
+  * @brief  Indicate if One bit sampling method is enabled
+  * @rmtoll CR3          ONEBIT        LL_USART_IsEnabledOneBitSamp
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Overrun detection
+  * @rmtoll CR3          OVRDIS        LL_USART_EnableOverrunDetect
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableOverrunDetect(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_OVRDIS);
+}
+
+/**
+  * @brief  Disable Overrun detection
+  * @rmtoll CR3          OVRDIS        LL_USART_DisableOverrunDetect
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableOverrunDetect(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_OVRDIS);
+}
+
+/**
+  * @brief  Indicate if Overrun detection is enabled
+  * @rmtoll CR3          OVRDIS        LL_USART_IsEnabledOverrunDetect
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
+  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          WUS           LL_USART_SetWKUPType
+  * @param  USARTx USART Instance
+  * @param  Type This parameter can be one of the following values:
+  *         @arg @ref LL_USART_WAKEUP_ON_ADDRESS
+  *         @arg @ref LL_USART_WAKEUP_ON_STARTBIT
+  *         @arg @ref LL_USART_WAKEUP_ON_RXNE
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetWKUPType(USART_TypeDef *USARTx, uint32_t Type)
+{
+  MODIFY_REG(USARTx->CR3, USART_CR3_WUS, Type);
+}
+
+/**
+  * @brief  Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
+  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          WUS           LL_USART_GetWKUPType
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_WAKEUP_ON_ADDRESS
+  *         @arg @ref LL_USART_WAKEUP_ON_STARTBIT
+  *         @arg @ref LL_USART_WAKEUP_ON_RXNE
+  */
+__STATIC_INLINE uint32_t LL_USART_GetWKUPType(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_WUS));
+}
+
+/**
+  * @brief  Configure USART BRR register for achieving expected Baud Rate value.
+  * @note   Compute and set USARTDIV value in BRR Register (full BRR content)
+  *         according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values
+  * @note   Peripheral clock and Baud rate values provided as function parameters should be valid
+  *         (Baud rate value != 0)
+  * @note   In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d.
+  * @rmtoll BRR          BRR           LL_USART_SetBaudRate
+  * @param  USARTx USART Instance
+  * @param  PeriphClk Peripheral Clock
+  * @param  PrescalerValue This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PRESCALER_DIV1
+  *         @arg @ref LL_USART_PRESCALER_DIV2
+  *         @arg @ref LL_USART_PRESCALER_DIV4
+  *         @arg @ref LL_USART_PRESCALER_DIV6
+  *         @arg @ref LL_USART_PRESCALER_DIV8
+  *         @arg @ref LL_USART_PRESCALER_DIV10
+  *         @arg @ref LL_USART_PRESCALER_DIV12
+  *         @arg @ref LL_USART_PRESCALER_DIV16
+  *         @arg @ref LL_USART_PRESCALER_DIV32
+  *         @arg @ref LL_USART_PRESCALER_DIV64
+  *         @arg @ref LL_USART_PRESCALER_DIV128
+  *         @arg @ref LL_USART_PRESCALER_DIV256
+  * @param  OverSampling This parameter can be one of the following values:
+  *         @arg @ref LL_USART_OVERSAMPLING_16
+  *         @arg @ref LL_USART_OVERSAMPLING_8
+  * @param  BaudRate Baud Rate
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
+                                          uint32_t OverSampling,
+                                          uint32_t BaudRate)
+{
+  uint32_t usartdiv;
+  uint32_t brrtemp;
+
+  if (PrescalerValue > LL_USART_PRESCALER_DIV256)
+  {
+    /* Do not overstep the size of USART_PRESCALER_TAB */
+  }
+  else if (BaudRate == 0U)
+  {
+    /* Can Not divide per 0 */
+  }
+  else if (OverSampling == LL_USART_OVERSAMPLING_8)
+  {
+    usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, (uint8_t)PrescalerValue, BaudRate));
+    brrtemp = usartdiv & 0xFFF0U;
+    brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
+    USARTx->BRR = brrtemp;
+  }
+  else
+  {
+    USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, (uint8_t)PrescalerValue, BaudRate));
+  }
+}
+
+/**
+  * @brief  Return current Baud Rate value, according to USARTDIV present in BRR register
+  *         (full BRR content), and to used Peripheral Clock and Oversampling mode values
+  * @note   In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
+  * @note   In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d.
+  * @rmtoll BRR          BRR           LL_USART_GetBaudRate
+  * @param  USARTx USART Instance
+  * @param  PeriphClk Peripheral Clock
+  * @param  PrescalerValue This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PRESCALER_DIV1
+  *         @arg @ref LL_USART_PRESCALER_DIV2
+  *         @arg @ref LL_USART_PRESCALER_DIV4
+  *         @arg @ref LL_USART_PRESCALER_DIV6
+  *         @arg @ref LL_USART_PRESCALER_DIV8
+  *         @arg @ref LL_USART_PRESCALER_DIV10
+  *         @arg @ref LL_USART_PRESCALER_DIV12
+  *         @arg @ref LL_USART_PRESCALER_DIV16
+  *         @arg @ref LL_USART_PRESCALER_DIV32
+  *         @arg @ref LL_USART_PRESCALER_DIV64
+  *         @arg @ref LL_USART_PRESCALER_DIV128
+  *         @arg @ref LL_USART_PRESCALER_DIV256
+  * @param  OverSampling This parameter can be one of the following values:
+  *         @arg @ref LL_USART_OVERSAMPLING_16
+  *         @arg @ref LL_USART_OVERSAMPLING_8
+  * @retval Baud Rate
+  */
+__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
+                                              uint32_t OverSampling)
+{
+  uint32_t usartdiv;
+  uint32_t brrresult = 0x0U;
+  uint32_t periphclkpresc = (uint32_t)(PeriphClk / (USART_PRESCALER_TAB[(uint8_t)PrescalerValue]));
+
+  usartdiv = USARTx->BRR;
+
+  if (usartdiv == 0U)
+  {
+    /* Do not perform a division by 0 */
+  }
+  else if (OverSampling == LL_USART_OVERSAMPLING_8)
+  {
+    usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ;
+    if (usartdiv != 0U)
+    {
+      brrresult = (periphclkpresc * 2U) / usartdiv;
+    }
+  }
+  else
+  {
+    if ((usartdiv & 0xFFFFU) != 0U)
+    {
+      brrresult = periphclkpresc / usartdiv;
+    }
+  }
+  return (brrresult);
+}
+
+/**
+  * @brief  Set Receiver Time Out Value (expressed in nb of bits duration)
+  * @rmtoll RTOR         RTO           LL_USART_SetRxTimeout
+  * @param  USARTx USART Instance
+  * @param  Timeout Value between Min_Data=0x00 and Max_Data=0x00FFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetRxTimeout(USART_TypeDef *USARTx, uint32_t Timeout)
+{
+  MODIFY_REG(USARTx->RTOR, USART_RTOR_RTO, Timeout);
+}
+
+/**
+  * @brief  Get Receiver Time Out Value (expressed in nb of bits duration)
+  * @rmtoll RTOR         RTO           LL_USART_GetRxTimeout
+  * @param  USARTx USART Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0x00FFFFFF
+  */
+__STATIC_INLINE uint32_t LL_USART_GetRxTimeout(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_RTO));
+}
+
+/**
+  * @brief  Set Block Length value in reception
+  * @rmtoll RTOR         BLEN          LL_USART_SetBlockLength
+  * @param  USARTx USART Instance
+  * @param  BlockLength Value between Min_Data=0x00 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetBlockLength(USART_TypeDef *USARTx, uint32_t BlockLength)
+{
+  MODIFY_REG(USARTx->RTOR, USART_RTOR_BLEN, BlockLength << USART_RTOR_BLEN_Pos);
+}
+
+/**
+  * @brief  Get Block Length value in reception
+  * @rmtoll RTOR         BLEN          LL_USART_GetBlockLength
+  * @param  USARTx USART Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint32_t LL_USART_GetBlockLength(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_BLEN) >> USART_RTOR_BLEN_Pos);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Configuration_IRDA Configuration functions related to Irda feature
+  * @{
+  */
+
+/**
+  * @brief  Enable IrDA mode
+  * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll CR3          IREN          LL_USART_EnableIrda
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_IREN);
+}
+
+/**
+  * @brief  Disable IrDA mode
+  * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll CR3          IREN          LL_USART_DisableIrda
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_IREN);
+}
+
+/**
+  * @brief  Indicate if IrDA mode is enabled
+  * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll CR3          IREN          LL_USART_IsEnabledIrda
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Configure IrDA Power Mode (Normal or Low Power)
+  * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll CR3          IRLP          LL_USART_SetIrdaPowerMode
+  * @param  USARTx USART Instance
+  * @param  PowerMode This parameter can be one of the following values:
+  *         @arg @ref LL_USART_IRDA_POWER_NORMAL
+  *         @arg @ref LL_USART_IRDA_POWER_LOW
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t PowerMode)
+{
+  MODIFY_REG(USARTx->CR3, USART_CR3_IRLP, PowerMode);
+}
+
+/**
+  * @brief  Retrieve IrDA Power Mode configuration (Normal or Low Power)
+  * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll CR3          IRLP          LL_USART_GetIrdaPowerMode
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_IRDA_POWER_NORMAL
+  *         @arg @ref LL_USART_PHASE_2EDGE
+  */
+__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP));
+}
+
+/**
+  * @brief  Set Irda prescaler value, used for dividing the USART clock source
+  *         to achieve the Irda Low Power frequency (8 bits value)
+  * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll GTPR         PSC           LL_USART_SetIrdaPrescaler
+  * @param  USARTx USART Instance
+  * @param  PrescalerValue Value between Min_Data=0x00 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
+{
+  MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue);
+}
+
+/**
+  * @brief  Return Irda prescaler value, used for dividing the USART clock source
+  *         to achieve the Irda Low Power frequency (8 bits value)
+  * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll GTPR         PSC           LL_USART_GetIrdaPrescaler
+  * @param  USARTx USART Instance
+  * @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF)
+  */
+__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Configuration_Smartcard Configuration functions related to Smartcard feature
+  * @{
+  */
+
+/**
+  * @brief  Enable Smartcard NACK transmission
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          NACK          LL_USART_EnableSmartcardNACK
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_NACK);
+}
+
+/**
+  * @brief  Disable Smartcard NACK transmission
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          NACK          LL_USART_DisableSmartcardNACK
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_NACK);
+}
+
+/**
+  * @brief  Indicate if Smartcard NACK transmission is enabled
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          NACK          LL_USART_IsEnabledSmartcardNACK
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Smartcard mode
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          SCEN          LL_USART_EnableSmartcard
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_SCEN);
+}
+
+/**
+  * @brief  Disable Smartcard mode
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          SCEN          LL_USART_DisableSmartcard
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_SCEN);
+}
+
+/**
+  * @brief  Indicate if Smartcard mode is enabled
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          SCEN          LL_USART_IsEnabledSmartcard
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @note   This bit-field specifies the number of retries in transmit and receive, in Smartcard mode.
+  *         In transmission mode, it specifies the number of automatic retransmission retries, before
+  *         generating a transmission error (FE bit set).
+  *         In reception mode, it specifies the number or erroneous reception trials, before generating a
+  *         reception error (RXNE and PE bits set)
+  * @rmtoll CR3          SCARCNT       LL_USART_SetSmartcardAutoRetryCount
+  * @param  USARTx USART Instance
+  * @param  AutoRetryCount Value between Min_Data=0 and Max_Data=7
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount(USART_TypeDef *USARTx, uint32_t AutoRetryCount)
+{
+  MODIFY_REG(USARTx->CR3, USART_CR3_SCARCNT, AutoRetryCount << USART_CR3_SCARCNT_Pos);
+}
+
+/**
+  * @brief  Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          SCARCNT       LL_USART_GetSmartcardAutoRetryCount
+  * @param  USARTx USART Instance
+  * @retval Smartcard Auto-Retry Count value (Value between Min_Data=0 and Max_Data=7)
+  */
+__STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_SCARCNT) >> USART_CR3_SCARCNT_Pos);
+}
+
+/**
+  * @brief  Set Smartcard prescaler value, used for dividing the USART clock
+  *         source to provide the SMARTCARD Clock (5 bits value)
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll GTPR         PSC           LL_USART_SetSmartcardPrescaler
+  * @param  USARTx USART Instance
+  * @param  PrescalerValue Value between Min_Data=0 and Max_Data=31
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
+{
+  MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue);
+}
+
+/**
+  * @brief  Return Smartcard prescaler value, used for dividing the USART clock
+  *         source to provide the SMARTCARD Clock (5 bits value)
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll GTPR         PSC           LL_USART_GetSmartcardPrescaler
+  * @param  USARTx USART Instance
+  * @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31)
+  */
+__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
+}
+
+/**
+  * @brief  Set Smartcard Guard time value, expressed in nb of baud clocks periods
+  *         (GT[7:0] bits : Guard time value)
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll GTPR         GT            LL_USART_SetSmartcardGuardTime
+  * @param  USARTx USART Instance
+  * @param  GuardTime Value between Min_Data=0x00 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime)
+{
+  MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, (uint16_t)(GuardTime << USART_GTPR_GT_Pos));
+}
+
+/**
+  * @brief  Return Smartcard Guard time value, expressed in nb of baud clocks periods
+  *         (GT[7:0] bits : Guard time value)
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll GTPR         GT            LL_USART_GetSmartcardGuardTime
+  * @param  USARTx USART Instance
+  * @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF)
+  */
+__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_GTPR_GT_Pos);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature
+  * @{
+  */
+
+/**
+  * @brief  Enable Single Wire Half-Duplex mode
+  * @note   Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+  *         Half-Duplex mode is supported by the USARTx instance.
+  * @rmtoll CR3          HDSEL         LL_USART_EnableHalfDuplex
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
+}
+
+/**
+  * @brief  Disable Single Wire Half-Duplex mode
+  * @note   Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+  *         Half-Duplex mode is supported by the USARTx instance.
+  * @rmtoll CR3          HDSEL         LL_USART_DisableHalfDuplex
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL);
+}
+
+/**
+  * @brief  Indicate if Single Wire Half-Duplex mode is enabled
+  * @note   Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+  *         Half-Duplex mode is supported by the USARTx instance.
+  * @rmtoll CR3          HDSEL         LL_USART_IsEnabledHalfDuplex
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Configuration_SPI_SLAVE Configuration functions related to SPI Slave feature
+  * @{
+  */
+/**
+  * @brief  Enable SPI Synchronous Slave mode
+  * @note   Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+  *         SPI Slave mode feature is supported by the USARTx instance.
+  * @rmtoll CR2          SLVEN         LL_USART_EnableSPISlave
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableSPISlave(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR2, USART_CR2_SLVEN);
+}
+
+/**
+  * @brief  Disable SPI Synchronous Slave mode
+  * @note   Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+  *         SPI Slave mode feature is supported by the USARTx instance.
+  * @rmtoll CR2          SLVEN         LL_USART_DisableSPISlave
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableSPISlave(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR2, USART_CR2_SLVEN);
+}
+
+/**
+  * @brief  Indicate if  SPI Synchronous Slave mode is enabled
+  * @note   Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+  *         SPI Slave mode feature is supported by the USARTx instance.
+  * @rmtoll CR2          SLVEN         LL_USART_IsEnabledSPISlave
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlave(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR2, USART_CR2_SLVEN) == (USART_CR2_SLVEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable SPI Slave Selection using NSS input pin
+  * @note   Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+  *         SPI Slave mode feature is supported by the USARTx instance.
+  * @note   SPI Slave Selection depends on NSS input pin
+  *         (The slave is selected when NSS is low and deselected when NSS is high).
+  * @rmtoll CR2          DIS_NSS       LL_USART_EnableSPISlaveSelect
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableSPISlaveSelect(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR2, USART_CR2_DIS_NSS);
+}
+
+/**
+  * @brief  Disable SPI Slave Selection using NSS input pin
+  * @note   Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+  *         SPI Slave mode feature is supported by the USARTx instance.
+  * @note   SPI Slave will be always selected and NSS input pin will be ignored.
+  * @rmtoll CR2          DIS_NSS       LL_USART_DisableSPISlaveSelect
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableSPISlaveSelect(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR2, USART_CR2_DIS_NSS);
+}
+
+/**
+  * @brief  Indicate if  SPI Slave Selection depends on NSS input pin
+  * @note   Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+  *         SPI Slave mode feature is supported by the USARTx instance.
+  * @rmtoll CR2          DIS_NSS       LL_USART_IsEnabledSPISlaveSelect
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlaveSelect(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR2, USART_CR2_DIS_NSS) != (USART_CR2_DIS_NSS)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Configuration_LIN Configuration functions related to LIN feature
+  * @{
+  */
+
+/**
+  * @brief  Set LIN Break Detection Length
+  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LBDL          LL_USART_SetLINBrkDetectionLen
+  * @param  USARTx USART Instance
+  * @param  LINBDLength This parameter can be one of the following values:
+  *         @arg @ref LL_USART_LINBREAK_DETECT_10B
+  *         @arg @ref LL_USART_LINBREAK_DETECT_11B
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint32_t LINBDLength)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_LBDL, LINBDLength);
+}
+
+/**
+  * @brief  Return LIN Break Detection Length
+  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LBDL          LL_USART_GetLINBrkDetectionLen
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_LINBREAK_DETECT_10B
+  *         @arg @ref LL_USART_LINBREAK_DETECT_11B
+  */
+__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL));
+}
+
+/**
+  * @brief  Enable LIN mode
+  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LINEN         LL_USART_EnableLIN
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR2, USART_CR2_LINEN);
+}
+
+/**
+  * @brief  Disable LIN mode
+  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LINEN         LL_USART_DisableLIN
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR2, USART_CR2_LINEN);
+}
+
+/**
+  * @brief  Indicate if LIN mode is enabled
+  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LINEN         LL_USART_IsEnabledLIN
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature
+  * @{
+  */
+
+/**
+  * @brief  Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
+  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR1          DEDT          LL_USART_SetDEDeassertionTime
+  * @param  USARTx USART Instance
+  * @param  Time Value between Min_Data=0 and Max_Data=31
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetDEDeassertionTime(USART_TypeDef *USARTx, uint32_t Time)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos);
+}
+
+/**
+  * @brief  Return DEDT (Driver Enable De-Assertion Time)
+  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR1          DEDT          LL_USART_GetDEDeassertionTime
+  * @param  USARTx USART Instance
+  * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31
+  */
+__STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos);
+}
+
+/**
+  * @brief  Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
+  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR1          DEAT          LL_USART_SetDEAssertionTime
+  * @param  USARTx USART Instance
+  * @param  Time Value between Min_Data=0 and Max_Data=31
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetDEAssertionTime(USART_TypeDef *USARTx, uint32_t Time)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos);
+}
+
+/**
+  * @brief  Return DEAT (Driver Enable Assertion Time)
+  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR1          DEAT          LL_USART_GetDEAssertionTime
+  * @param  USARTx USART Instance
+  * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31
+  */
+__STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos);
+}
+
+/**
+  * @brief  Enable Driver Enable (DE) Mode
+  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR3          DEM           LL_USART_EnableDEMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableDEMode(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_DEM);
+}
+
+/**
+  * @brief  Disable Driver Enable (DE) Mode
+  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR3          DEM           LL_USART_DisableDEMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableDEMode(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_DEM);
+}
+
+/**
+  * @brief  Indicate if Driver Enable (DE) Mode is enabled
+  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR3          DEM           LL_USART_IsEnabledDEMode
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Select Driver Enable Polarity
+  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR3          DEP           LL_USART_SetDESignalPolarity
+  * @param  USARTx USART Instance
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_USART_DE_POLARITY_HIGH
+  *         @arg @ref LL_USART_DE_POLARITY_LOW
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetDESignalPolarity(USART_TypeDef *USARTx, uint32_t Polarity)
+{
+  MODIFY_REG(USARTx->CR3, USART_CR3_DEP, Polarity);
+}
+
+/**
+  * @brief  Return Driver Enable Polarity
+  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR3          DEP           LL_USART_GetDESignalPolarity
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_DE_POLARITY_HIGH
+  *         @arg @ref LL_USART_DE_POLARITY_LOW
+  */
+__STATIC_INLINE uint32_t LL_USART_GetDESignalPolarity(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_DEP));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_AdvancedConfiguration Advanced Configurations services
+  * @{
+  */
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in Asynchronous Mode (UART)
+  * @note   In UART mode, the following bits must be kept cleared:
+  *           - LINEN bit in the USART_CR2 register,
+  *           - CLKEN bit in the USART_CR2 register,
+  *           - SCEN bit in the USART_CR3 register,
+  *           - IREN bit in the USART_CR3 register,
+  *           - HDSEL bit in the USART_CR3 register.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+  * @note   Other remaining configurations items related to Asynchronous Mode
+  *         (as Baud Rate, Word length, Parity, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          LINEN         LL_USART_ConfigAsyncMode\n
+  *         CR2          CLKEN         LL_USART_ConfigAsyncMode\n
+  *         CR3          SCEN          LL_USART_ConfigAsyncMode\n
+  *         CR3          IREN          LL_USART_ConfigAsyncMode\n
+  *         CR3          HDSEL         LL_USART_ConfigAsyncMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx)
+{
+  /* In Asynchronous mode, the following bits must be kept cleared:
+  - LINEN, CLKEN bits in the USART_CR2 register,
+  - SCEN, IREN and HDSEL bits in the USART_CR3 register.
+  */
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
+}
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in Synchronous Mode
+  * @note   In Synchronous mode, the following bits must be kept cleared:
+  *           - LINEN bit in the USART_CR2 register,
+  *           - SCEN bit in the USART_CR3 register,
+  *           - IREN bit in the USART_CR3 register,
+  *           - HDSEL bit in the USART_CR3 register.
+  *         This function also sets the USART in Synchronous mode.
+  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+  *         - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
+  * @note   Other remaining configurations items related to Synchronous Mode
+  *         (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          LINEN         LL_USART_ConfigSyncMode\n
+  *         CR2          CLKEN         LL_USART_ConfigSyncMode\n
+  *         CR3          SCEN          LL_USART_ConfigSyncMode\n
+  *         CR3          IREN          LL_USART_ConfigSyncMode\n
+  *         CR3          HDSEL         LL_USART_ConfigSyncMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx)
+{
+  /* In Synchronous mode, the following bits must be kept cleared:
+  - LINEN bit in the USART_CR2 register,
+  - SCEN, IREN and HDSEL bits in the USART_CR3 register.
+  */
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
+  /* set the UART/USART in Synchronous mode */
+  SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
+}
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in LIN Mode
+  * @note   In LIN mode, the following bits must be kept cleared:
+  *           - STOP and CLKEN bits in the USART_CR2 register,
+  *           - SCEN bit in the USART_CR3 register,
+  *           - IREN bit in the USART_CR3 register,
+  *           - HDSEL bit in the USART_CR3 register.
+  *         This function also set the UART/USART in LIN mode.
+  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+  *         - Clear STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+  *         - Set LINEN in CR2 using @ref LL_USART_EnableLIN() function
+  * @note   Other remaining configurations items related to LIN Mode
+  *         (as Baud Rate, Word length, LIN Break Detection Length, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          CLKEN         LL_USART_ConfigLINMode\n
+  *         CR2          STOP          LL_USART_ConfigLINMode\n
+  *         CR2          LINEN         LL_USART_ConfigLINMode\n
+  *         CR3          IREN          LL_USART_ConfigLINMode\n
+  *         CR3          SCEN          LL_USART_ConfigLINMode\n
+  *         CR3          HDSEL         LL_USART_ConfigLINMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx)
+{
+  /* In LIN mode, the following bits must be kept cleared:
+  - STOP and CLKEN bits in the USART_CR2 register,
+  - IREN, SCEN and HDSEL bits in the USART_CR3 register.
+  */
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL));
+  /* Set the UART/USART in LIN mode */
+  SET_BIT(USARTx->CR2, USART_CR2_LINEN);
+}
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in Half Duplex Mode
+  * @note   In Half Duplex mode, the following bits must be kept cleared:
+  *           - LINEN bit in the USART_CR2 register,
+  *           - CLKEN bit in the USART_CR2 register,
+  *           - SCEN bit in the USART_CR3 register,
+  *           - IREN bit in the USART_CR3 register,
+  *         This function also sets the UART/USART in Half Duplex mode.
+  * @note   Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+  *         Half-Duplex mode is supported by the USARTx instance.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+  *         - Set HDSEL in CR3 using @ref LL_USART_EnableHalfDuplex() function
+  * @note   Other remaining configurations items related to Half Duplex Mode
+  *         (as Baud Rate, Word length, Parity, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          LINEN         LL_USART_ConfigHalfDuplexMode\n
+  *         CR2          CLKEN         LL_USART_ConfigHalfDuplexMode\n
+  *         CR3          HDSEL         LL_USART_ConfigHalfDuplexMode\n
+  *         CR3          SCEN          LL_USART_ConfigHalfDuplexMode\n
+  *         CR3          IREN          LL_USART_ConfigHalfDuplexMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx)
+{
+  /* In Half Duplex mode, the following bits must be kept cleared:
+  - LINEN and CLKEN bits in the USART_CR2 register,
+  - SCEN and IREN bits in the USART_CR3 register.
+  */
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN));
+  /* set the UART/USART in Half Duplex mode */
+  SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
+}
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in Smartcard Mode
+  * @note   In Smartcard mode, the following bits must be kept cleared:
+  *           - LINEN bit in the USART_CR2 register,
+  *           - IREN bit in the USART_CR3 register,
+  *           - HDSEL bit in the USART_CR3 register.
+  *         This function also configures Stop bits to 1.5 bits and
+  *         sets the USART in Smartcard mode (SCEN bit).
+  *         Clock Output is also enabled (CLKEN).
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+  *         - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
+  *         - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
+  *         - Set SCEN in CR3 using @ref LL_USART_EnableSmartcard() function
+  * @note   Other remaining configurations items related to Smartcard Mode
+  *         (as Baud Rate, Word length, Parity, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          LINEN         LL_USART_ConfigSmartcardMode\n
+  *         CR2          STOP          LL_USART_ConfigSmartcardMode\n
+  *         CR2          CLKEN         LL_USART_ConfigSmartcardMode\n
+  *         CR3          HDSEL         LL_USART_ConfigSmartcardMode\n
+  *         CR3          SCEN          LL_USART_ConfigSmartcardMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx)
+{
+  /* In Smartcard mode, the following bits must be kept cleared:
+  - LINEN bit in the USART_CR2 register,
+  - IREN and HDSEL bits in the USART_CR3 register.
+  */
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL));
+  /* Configure Stop bits to 1.5 bits */
+  /* Synchronous mode is activated by default */
+  SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN));
+  /* set the UART/USART in Smartcard mode */
+  SET_BIT(USARTx->CR3, USART_CR3_SCEN);
+}
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in Irda Mode
+  * @note   In IRDA mode, the following bits must be kept cleared:
+  *           - LINEN bit in the USART_CR2 register,
+  *           - STOP and CLKEN bits in the USART_CR2 register,
+  *           - SCEN bit in the USART_CR3 register,
+  *           - HDSEL bit in the USART_CR3 register.
+  *         This function also sets the UART/USART in IRDA mode (IREN bit).
+  * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+  *         - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
+  *         - Set IREN in CR3 using @ref LL_USART_EnableIrda() function
+  * @note   Other remaining configurations items related to Irda Mode
+  *         (as Baud Rate, Word length, Power mode, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          LINEN         LL_USART_ConfigIrdaMode\n
+  *         CR2          CLKEN         LL_USART_ConfigIrdaMode\n
+  *         CR2          STOP          LL_USART_ConfigIrdaMode\n
+  *         CR3          SCEN          LL_USART_ConfigIrdaMode\n
+  *         CR3          HDSEL         LL_USART_ConfigIrdaMode\n
+  *         CR3          IREN          LL_USART_ConfigIrdaMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx)
+{
+  /* In IRDA mode, the following bits must be kept cleared:
+  - LINEN, STOP and CLKEN bits in the USART_CR2 register,
+  - SCEN and HDSEL bits in the USART_CR3 register.
+  */
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
+  /* set the UART/USART in IRDA mode */
+  SET_BIT(USARTx->CR3, USART_CR3_IREN);
+}
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in Multi processor Mode
+  *         (several USARTs connected in a network, one of the USARTs can be the master,
+  *         its TX output connected to the RX inputs of the other slaves USARTs).
+  * @note   In MultiProcessor mode, the following bits must be kept cleared:
+  *           - LINEN bit in the USART_CR2 register,
+  *           - CLKEN bit in the USART_CR2 register,
+  *           - SCEN bit in the USART_CR3 register,
+  *           - IREN bit in the USART_CR3 register,
+  *           - HDSEL bit in the USART_CR3 register.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+  * @note   Other remaining configurations items related to Multi processor Mode
+  *         (as Baud Rate, Wake Up Method, Node address, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          LINEN         LL_USART_ConfigMultiProcessMode\n
+  *         CR2          CLKEN         LL_USART_ConfigMultiProcessMode\n
+  *         CR3          SCEN          LL_USART_ConfigMultiProcessMode\n
+  *         CR3          HDSEL         LL_USART_ConfigMultiProcessMode\n
+  *         CR3          IREN          LL_USART_ConfigMultiProcessMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx)
+{
+  /* In Multi Processor mode, the following bits must be kept cleared:
+  - LINEN and CLKEN bits in the USART_CR2 register,
+  - IREN, SCEN and HDSEL bits in the USART_CR3 register.
+  */
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_FLAG_Management FLAG_Management
+  * @{
+  */
+
+/**
+  * @brief  Check if the USART Parity Error Flag is set or not
+  * @rmtoll ISR          PE            LL_USART_IsActiveFlag_PE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Framing Error Flag is set or not
+  * @rmtoll ISR          FE            LL_USART_IsActiveFlag_FE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Noise error detected Flag is set or not
+  * @rmtoll ISR          NE            LL_USART_IsActiveFlag_NE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART OverRun Error Flag is set or not
+  * @rmtoll ISR          ORE           LL_USART_IsActiveFlag_ORE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART IDLE line detected Flag is set or not
+  * @rmtoll ISR          IDLE          LL_USART_IsActiveFlag_IDLE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL);
+}
+
+/* Legacy define */
+#define LL_USART_IsActiveFlag_RXNE  LL_USART_IsActiveFlag_RXNE_RXFNE
+
+/**
+  * @brief  Check if the USART Read Data Register or USART RX FIFO Not Empty Flag is set or not
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll ISR          RXNE_RXFNE    LL_USART_IsActiveFlag_RXNE_RXFNE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE_RXFNE(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Transmission Complete Flag is set or not
+  * @rmtoll ISR          TC            LL_USART_IsActiveFlag_TC
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL);
+}
+
+/* Legacy define */
+#define LL_USART_IsActiveFlag_TXE  LL_USART_IsActiveFlag_TXE_TXFNF
+
+/**
+  * @brief  Check if the USART Transmit Data Register Empty or USART TX FIFO Not Full Flag is set or not
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll ISR          TXE_TXFNF     LL_USART_IsActiveFlag_TXE_TXFNF
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE_TXFNF(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART LIN Break Detection Flag is set or not
+  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll ISR          LBDF          LL_USART_IsActiveFlag_LBD
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_LBDF) == (USART_ISR_LBDF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART CTS interrupt Flag is set or not
+  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll ISR          CTSIF         LL_USART_IsActiveFlag_nCTS
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART CTS Flag is set or not
+  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll ISR          CTS           LL_USART_IsActiveFlag_CTS
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Receiver Time Out Flag is set or not
+  * @rmtoll ISR          RTOF          LL_USART_IsActiveFlag_RTO
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_RTOF) == (USART_ISR_RTOF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART End Of Block Flag is set or not
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll ISR          EOBF          LL_USART_IsActiveFlag_EOB
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_EOBF) == (USART_ISR_EOBF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the SPI Slave Underrun error flag is set or not
+  * @note   Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+  *         SPI Slave mode feature is supported by the USARTx instance.
+  * @rmtoll ISR          UDR           LL_USART_IsActiveFlag_UDR
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_UDR(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_UDR) == (USART_ISR_UDR)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Auto-Baud Rate Error Flag is set or not
+  * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll ISR          ABRE          LL_USART_IsActiveFlag_ABRE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_ABRE) == (USART_ISR_ABRE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Auto-Baud Rate Flag is set or not
+  * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll ISR          ABRF          LL_USART_IsActiveFlag_ABR
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_ABRF) == (USART_ISR_ABRF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Busy Flag is set or not
+  * @rmtoll ISR          BUSY          LL_USART_IsActiveFlag_BUSY
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Character Match Flag is set or not
+  * @rmtoll ISR          CMF           LL_USART_IsActiveFlag_CM
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Send Break Flag is set or not
+  * @rmtoll ISR          SBKF          LL_USART_IsActiveFlag_SBK
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Receive Wake Up from mute mode Flag is set or not
+  * @rmtoll ISR          RWU           LL_USART_IsActiveFlag_RWU
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Wake Up from stop mode Flag is set or not
+  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll ISR          WUF           LL_USART_IsActiveFlag_WKUP
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Transmit Enable Acknowledge Flag is set or not
+  * @rmtoll ISR          TEACK         LL_USART_IsActiveFlag_TEACK
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Receive Enable Acknowledge Flag is set or not
+  * @rmtoll ISR          REACK         LL_USART_IsActiveFlag_REACK
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART TX FIFO Empty Flag is set or not
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll ISR          TXFE          LL_USART_IsActiveFlag_TXFE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFE(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART RX FIFO Full Flag is set or not
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll ISR          RXFF          LL_USART_IsActiveFlag_RXFF
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFF(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the Smartcard Transmission Complete Before Guard Time Flag is set or not
+  * @rmtoll ISR          TCBGT         LL_USART_IsActiveFlag_TCBGT
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_TCBGT) == (USART_ISR_TCBGT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART TX FIFO Threshold Flag is set or not
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll ISR          TXFT          LL_USART_IsActiveFlag_TXFT
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFT(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART RX FIFO Threshold Flag is set or not
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll ISR          RXFT          LL_USART_IsActiveFlag_RXFT
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFT(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear Parity Error Flag
+  * @rmtoll ICR          PECF          LL_USART_ClearFlag_PE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_PE(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_PECF);
+}
+
+/**
+  * @brief  Clear Framing Error Flag
+  * @rmtoll ICR          FECF          LL_USART_ClearFlag_FE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_FECF);
+}
+
+/**
+  * @brief  Clear Noise Error detected Flag
+  * @rmtoll ICR          NECF          LL_USART_ClearFlag_NE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_NECF);
+}
+
+/**
+  * @brief  Clear OverRun Error Flag
+  * @rmtoll ICR          ORECF         LL_USART_ClearFlag_ORE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_ORECF);
+}
+
+/**
+  * @brief  Clear IDLE line detected Flag
+  * @rmtoll ICR          IDLECF        LL_USART_ClearFlag_IDLE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_IDLECF);
+}
+
+/**
+  * @brief  Clear TX FIFO Empty Flag
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll ICR          TXFECF        LL_USART_ClearFlag_TXFE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_TXFE(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_TXFECF);
+}
+
+/**
+  * @brief  Clear Transmission Complete Flag
+  * @rmtoll ICR          TCCF          LL_USART_ClearFlag_TC
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_TCCF);
+}
+
+/**
+  * @brief  Clear Smartcard Transmission Complete Before Guard Time Flag
+  * @rmtoll ICR          TCBGTCF       LL_USART_ClearFlag_TCBGT
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_TCBGT(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_TCBGTCF);
+}
+
+/**
+  * @brief  Clear LIN Break Detection Flag
+  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll ICR          LBDCF         LL_USART_ClearFlag_LBD
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_LBDCF);
+}
+
+/**
+  * @brief  Clear CTS Interrupt Flag
+  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll ICR          CTSCF         LL_USART_ClearFlag_nCTS
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_CTSCF);
+}
+
+/**
+  * @brief  Clear Receiver Time Out Flag
+  * @rmtoll ICR          RTOCF         LL_USART_ClearFlag_RTO
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_RTO(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_RTOCF);
+}
+
+/**
+  * @brief  Clear End Of Block Flag
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll ICR          EOBCF         LL_USART_ClearFlag_EOB
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_EOB(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_EOBCF);
+}
+
+/**
+  * @brief  Clear SPI Slave Underrun Flag
+  * @note   Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+  *         SPI Slave mode feature is supported by the USARTx instance.
+  * @rmtoll ICR          UDRCF         LL_USART_ClearFlag_UDR
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_UDR(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_UDRCF);
+}
+
+/**
+  * @brief  Clear Character Match Flag
+  * @rmtoll ICR          CMCF          LL_USART_ClearFlag_CM
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_CM(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_CMCF);
+}
+
+/**
+  * @brief  Clear Wake Up from stop mode Flag
+  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll ICR          WUCF          LL_USART_ClearFlag_WKUP
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_WKUP(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_WUCF);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_IT_Management IT_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable IDLE Interrupt
+  * @rmtoll CR1          IDLEIE        LL_USART_EnableIT_IDLE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_IDLEIE);
+}
+
+/* Legacy define */
+#define LL_USART_EnableIT_RXNE  LL_USART_EnableIT_RXNE_RXFNE
+
+/**
+  * @brief  Enable RX Not Empty and RX FIFO Not Empty Interrupt
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1        RXNEIE_RXFNEIE  LL_USART_EnableIT_RXNE_RXFNE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_RXNE_RXFNE(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
+}
+
+/**
+  * @brief  Enable Transmission Complete Interrupt
+  * @rmtoll CR1          TCIE          LL_USART_EnableIT_TC
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TCIE);
+}
+
+/* Legacy define */
+#define LL_USART_EnableIT_TXE  LL_USART_EnableIT_TXE_TXFNF
+
+/**
+  * @brief  Enable TX Empty and TX FIFO Not Full Interrupt
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1         TXEIE_TXFNFIE  LL_USART_EnableIT_TXE_TXFNF
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_TXE_TXFNF(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
+}
+
+/**
+  * @brief  Enable Parity Error Interrupt
+  * @rmtoll CR1          PEIE          LL_USART_EnableIT_PE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_PEIE);
+}
+
+/**
+  * @brief  Enable Character Match Interrupt
+  * @rmtoll CR1          CMIE          LL_USART_EnableIT_CM
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_CM(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_CMIE);
+}
+
+/**
+  * @brief  Enable Receiver Timeout Interrupt
+  * @rmtoll CR1          RTOIE         LL_USART_EnableIT_RTO
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_RTO(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RTOIE);
+}
+
+/**
+  * @brief  Enable End Of Block Interrupt
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR1          EOBIE         LL_USART_EnableIT_EOB
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_EOB(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_EOBIE);
+}
+
+/**
+  * @brief  Enable TX FIFO Empty Interrupt
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          TXFEIE        LL_USART_EnableIT_TXFE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_TXFE(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXFEIE);
+}
+
+/**
+  * @brief  Enable RX FIFO Full Interrupt
+  * @rmtoll CR1          RXFFIE        LL_USART_EnableIT_RXFF
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_RXFF(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXFFIE);
+}
+
+/**
+  * @brief  Enable LIN Break Detection Interrupt
+  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LBDIE         LL_USART_EnableIT_LBD
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR2, USART_CR2_LBDIE);
+}
+
+/**
+  * @brief  Enable Error Interrupt
+  * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
+  *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register).
+  *           0: Interrupt is inhibited
+  *           1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.
+  * @rmtoll CR3          EIE           LL_USART_EnableIT_ERROR
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_EIE);
+}
+
+/**
+  * @brief  Enable CTS Interrupt
+  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          CTSIE         LL_USART_EnableIT_CTS
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_CTSIE);
+}
+
+/**
+  * @brief  Enable Wake Up from Stop Mode Interrupt
+  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          WUFIE         LL_USART_EnableIT_WKUP
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_WKUP(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_WUFIE);
+}
+
+/**
+  * @brief  Enable TX FIFO Threshold Interrupt
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          TXFTIE        LL_USART_EnableIT_TXFT
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_TXFT(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_TXFTIE);
+}
+
+/**
+  * @brief  Enable Smartcard Transmission Complete Before Guard Time Interrupt
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          TCBGTIE       LL_USART_EnableIT_TCBGT
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_TCBGT(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_TCBGTIE);
+}
+
+/**
+  * @brief  Enable RX FIFO Threshold Interrupt
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          RXFTIE        LL_USART_EnableIT_RXFT
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_RXFT(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_RXFTIE);
+}
+
+/**
+  * @brief  Disable IDLE Interrupt
+  * @rmtoll CR1          IDLEIE        LL_USART_DisableIT_IDLE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE);
+}
+
+/* Legacy define */
+#define LL_USART_DisableIT_RXNE  LL_USART_DisableIT_RXNE_RXFNE
+
+/**
+  * @brief  Disable RX Not Empty and RX FIFO Not Empty Interrupt
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1        RXNEIE_RXFNEIE  LL_USART_DisableIT_RXNE_RXFNE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_RXNE_RXFNE(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
+}
+
+/**
+  * @brief  Disable Transmission Complete Interrupt
+  * @rmtoll CR1          TCIE          LL_USART_DisableIT_TC
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE);
+}
+
+/* Legacy define */
+#define LL_USART_DisableIT_TXE  LL_USART_DisableIT_TXE_TXFNF
+
+/**
+  * @brief  Disable TX Empty and TX FIFO Not Full Interrupt
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1        TXEIE_TXFNFIE  LL_USART_DisableIT_TXE_TXFNF
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_TXE_TXFNF(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
+}
+
+/**
+  * @brief  Disable Parity Error Interrupt
+  * @rmtoll CR1          PEIE          LL_USART_DisableIT_PE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE);
+}
+
+/**
+  * @brief  Disable Character Match Interrupt
+  * @rmtoll CR1          CMIE          LL_USART_DisableIT_CM
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_CM(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_CMIE);
+}
+
+/**
+  * @brief  Disable Receiver Timeout Interrupt
+  * @rmtoll CR1          RTOIE         LL_USART_DisableIT_RTO
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_RTO(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RTOIE);
+}
+
+/**
+  * @brief  Disable End Of Block Interrupt
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR1          EOBIE         LL_USART_DisableIT_EOB
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_EOB(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_EOBIE);
+}
+
+/**
+  * @brief  Disable TX FIFO Empty Interrupt
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          TXFEIE        LL_USART_DisableIT_TXFE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_TXFE(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXFEIE);
+}
+
+/**
+  * @brief  Disable RX FIFO Full Interrupt
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          RXFFIE        LL_USART_DisableIT_RXFF
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_RXFF(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXFFIE);
+}
+
+/**
+  * @brief  Disable LIN Break Detection Interrupt
+  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LBDIE         LL_USART_DisableIT_LBD
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR2, USART_CR2_LBDIE);
+}
+
+/**
+  * @brief  Disable Error Interrupt
+  * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
+  *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register).
+  *           0: Interrupt is inhibited
+  *           1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.
+  * @rmtoll CR3          EIE           LL_USART_DisableIT_ERROR
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_EIE);
+}
+
+/**
+  * @brief  Disable CTS Interrupt
+  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          CTSIE         LL_USART_DisableIT_CTS
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE);
+}
+
+/**
+  * @brief  Disable Wake Up from Stop Mode Interrupt
+  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          WUFIE         LL_USART_DisableIT_WKUP
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_WKUP(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_WUFIE);
+}
+
+/**
+  * @brief  Disable TX FIFO Threshold Interrupt
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          TXFTIE        LL_USART_DisableIT_TXFT
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_TXFT(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_TXFTIE);
+}
+
+/**
+  * @brief  Disable Smartcard Transmission Complete Before Guard Time Interrupt
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          TCBGTIE       LL_USART_DisableIT_TCBGT
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_TCBGT(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_TCBGTIE);
+}
+
+/**
+  * @brief  Disable RX FIFO Threshold Interrupt
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          RXFTIE        LL_USART_DisableIT_RXFT
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_RXFT(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_RXFTIE);
+}
+
+/**
+  * @brief  Check if the USART IDLE Interrupt  source is enabled or disabled.
+  * @rmtoll CR1          IDLEIE        LL_USART_IsEnabledIT_IDLE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL);
+}
+
+/* Legacy define */
+#define LL_USART_IsEnabledIT_RXNE  LL_USART_IsEnabledIT_RXNE_RXFNE
+
+/**
+  * @brief  Check if the USART RX Not Empty and USART RX FIFO Not Empty Interrupt is enabled or disabled.
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1        RXNEIE_RXFNEIE  LL_USART_IsEnabledIT_RXNE_RXFNE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE_RXFNE(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Transmission Complete Interrupt is enabled or disabled.
+  * @rmtoll CR1          TCIE          LL_USART_IsEnabledIT_TC
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL);
+}
+
+/* Legacy define */
+#define LL_USART_IsEnabledIT_TXE  LL_USART_IsEnabledIT_TXE_TXFNF
+
+/**
+  * @brief  Check if the USART TX Empty and USART TX FIFO Not Full Interrupt is enabled or disabled
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1         TXEIE_TXFNFIE  LL_USART_IsEnabledIT_TXE_TXFNF
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE_TXFNF(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Parity Error Interrupt is enabled or disabled.
+  * @rmtoll CR1          PEIE          LL_USART_IsEnabledIT_PE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Character Match Interrupt is enabled or disabled.
+  * @rmtoll CR1          CMIE          LL_USART_IsEnabledIT_CM
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Receiver Timeout Interrupt is enabled or disabled.
+  * @rmtoll CR1          RTOIE         LL_USART_IsEnabledIT_RTO
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_RTOIE) == (USART_CR1_RTOIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART End Of Block Interrupt is enabled or disabled.
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR1          EOBIE         LL_USART_IsEnabledIT_EOB
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_EOBIE) == (USART_CR1_EOBIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART TX FIFO Empty Interrupt is enabled or disabled
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          TXFEIE        LL_USART_IsEnabledIT_TXFE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFE(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART RX FIFO Full Interrupt is enabled or disabled
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          RXFFIE        LL_USART_IsEnabledIT_RXFF
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFF(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART LIN Break Detection Interrupt is enabled or disabled.
+  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LBDIE         LL_USART_IsEnabledIT_LBD
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Error Interrupt is enabled or disabled.
+  * @rmtoll CR3          EIE           LL_USART_IsEnabledIT_ERROR
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART CTS Interrupt is enabled or disabled.
+  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          CTSIE         LL_USART_IsEnabledIT_CTS
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Wake Up from Stop Mode Interrupt is enabled or disabled.
+  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          WUFIE         LL_USART_IsEnabledIT_WKUP
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if USART TX FIFO Threshold Interrupt is enabled or disabled
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          TXFTIE        LL_USART_IsEnabledIT_TXFT
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFT(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the Smartcard Transmission Complete Before Guard Time Interrupt is enabled or disabled.
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          TCBGTIE       LL_USART_IsEnabledIT_TCBGT
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_TCBGTIE) == (USART_CR3_TCBGTIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if USART RX FIFO Threshold Interrupt is enabled or disabled
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          RXFTIE        LL_USART_IsEnabledIT_RXFT
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFT(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_DMA_Management DMA_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable DMA Mode for reception
+  * @rmtoll CR3          DMAR          LL_USART_EnableDMAReq_RX
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAR);
+}
+
+/**
+  * @brief  Disable DMA Mode for reception
+  * @rmtoll CR3          DMAR          LL_USART_DisableDMAReq_RX
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR);
+}
+
+/**
+  * @brief  Check if DMA Mode is enabled for reception
+  * @rmtoll CR3          DMAR          LL_USART_IsEnabledDMAReq_RX
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable DMA Mode for transmission
+  * @rmtoll CR3          DMAT          LL_USART_EnableDMAReq_TX
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAT);
+}
+
+/**
+  * @brief  Disable DMA Mode for transmission
+  * @rmtoll CR3          DMAT          LL_USART_DisableDMAReq_TX
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT);
+}
+
+/**
+  * @brief  Check if DMA Mode is enabled for transmission
+  * @rmtoll CR3          DMAT          LL_USART_IsEnabledDMAReq_TX
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable DMA Disabling on Reception Error
+  * @rmtoll CR3          DDRE          LL_USART_EnableDMADeactOnRxErr
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableDMADeactOnRxErr(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_DDRE);
+}
+
+/**
+  * @brief  Disable DMA Disabling on Reception Error
+  * @rmtoll CR3          DDRE          LL_USART_DisableDMADeactOnRxErr
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableDMADeactOnRxErr(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_DDRE);
+}
+
+/**
+  * @brief  Indicate if DMA Disabling on Reception Error is disabled
+  * @rmtoll CR3          DDRE          LL_USART_IsEnabledDMADeactOnRxErr
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get the data register address used for DMA transfer
+  * @rmtoll RDR          RDR           LL_USART_DMA_GetRegAddr\n
+  * @rmtoll TDR          TDR           LL_USART_DMA_GetRegAddr
+  * @param  USARTx USART Instance
+  * @param  Direction This parameter can be one of the following values:
+  *         @arg @ref LL_USART_DMA_REG_DATA_TRANSMIT
+  *         @arg @ref LL_USART_DMA_REG_DATA_RECEIVE
+  * @retval Address of data register
+  */
+__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx, uint32_t Direction)
+{
+  uint32_t data_reg_addr;
+
+  if (Direction == LL_USART_DMA_REG_DATA_TRANSMIT)
+  {
+    /* return address of TDR register */
+    data_reg_addr = (uint32_t) &(USARTx->TDR);
+  }
+  else
+  {
+    /* return address of RDR register */
+    data_reg_addr = (uint32_t) &(USARTx->RDR);
+  }
+
+  return data_reg_addr;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Data_Management Data_Management
+  * @{
+  */
+
+/**
+  * @brief  Read Receiver Data register (Receive Data value, 8 bits)
+  * @rmtoll RDR          RDR           LL_USART_ReceiveData8
+  * @param  USARTx USART Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint8_t LL_USART_ReceiveData8(USART_TypeDef *USARTx)
+{
+  return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR) & 0xFFU);
+}
+
+/**
+  * @brief  Read Receiver Data register (Receive Data value, 9 bits)
+  * @rmtoll RDR          RDR           LL_USART_ReceiveData9
+  * @param  USARTx USART Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0x1FF
+  */
+__STATIC_INLINE uint16_t LL_USART_ReceiveData9(USART_TypeDef *USARTx)
+{
+  return (uint16_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR));
+}
+
+/**
+  * @brief  Write in Transmitter Data Register (Transmit Data value, 8 bits)
+  * @rmtoll TDR          TDR           LL_USART_TransmitData8
+  * @param  USARTx USART Instance
+  * @param  Value between Min_Data=0x00 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_TransmitData8(USART_TypeDef *USARTx, uint8_t Value)
+{
+  USARTx->TDR = Value;
+}
+
+/**
+  * @brief  Write in Transmitter Data Register (Transmit Data value, 9 bits)
+  * @rmtoll TDR          TDR           LL_USART_TransmitData9
+  * @param  USARTx USART Instance
+  * @param  Value between Min_Data=0x00 and Max_Data=0x1FF
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Value)
+{
+  USARTx->TDR = (uint16_t)(Value & 0x1FFUL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Execution Execution
+  * @{
+  */
+
+/**
+  * @brief  Request an Automatic Baud Rate measurement on next received data frame
+  * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll RQR          ABRRQ         LL_USART_RequestAutoBaudRate
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_RequestAutoBaudRate(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_ABRRQ);
+}
+
+/**
+  * @brief  Request Break sending
+  * @rmtoll RQR          SBKRQ         LL_USART_RequestBreakSending
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_RequestBreakSending(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_SBKRQ);
+}
+
+/**
+  * @brief  Put USART in mute mode and set the RWU flag
+  * @rmtoll RQR          MMRQ          LL_USART_RequestEnterMuteMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_RequestEnterMuteMode(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_MMRQ);
+}
+
+/**
+  * @brief  Request a Receive Data and FIFO flush
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @note   Allows to discard the received data without reading them, and avoid an overrun
+  *         condition.
+  * @rmtoll RQR          RXFRQ         LL_USART_RequestRxDataFlush
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_RequestRxDataFlush(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_RXFRQ);
+}
+
+/**
+  * @brief  Request a Transmit data and FIFO flush
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll RQR          TXFRQ         LL_USART_RequestTxDataFlush
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_RequestTxDataFlush(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_TXFRQ);
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx);
+ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct);
+void        LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct);
+ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
+void        LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* USART1 || USART2 || USART3 || USART6 || UART4 || UART5 || UART7 || UART8 || UART9 || USART10 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_LL_USART_H */
+
diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_utils.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_utils.h
index 635ea598..237fd632 100644
--- a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_utils.h
+++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_utils.h
@@ -1,401 +1,401 @@
-/**
-  ******************************************************************************
-  * @file    stm32h7xx_ll_utils.h
-  * @author  MCD Application Team
-  * @brief   Header file of UTILS LL module.
-  ******************************************************************************
-  * @attention
-  * Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file in
-  * the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  @verbatim
-  ==============================================================================
-                     ##### How to use this driver #####
-  ==============================================================================
-    [..]
-    The LL UTILS driver contains a set of generic APIs that can be
-    used by user:
-      (+) Device electronic signature
-      (+) Timing functions
-      (+) PLL configuration functions
-
-  @endverbatim
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32H7xx_LL_UTILS_H
-#define STM32H7xx_LL_UTILS_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx.h"
-#include "stm32h7xx_ll_system.h"
-#include "stm32h7xx_ll_bus.h"
-
-/** @addtogroup STM32H7xx_LL_Driver
-  * @{
-  */
-
-/** @defgroup UTILS_LL UTILS
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
-  * @{
-  */
-
-/* Max delay can be used in LL_mDelay */
-#define LL_MAX_DELAY                  0xFFFFFFFFU
-
-/**
- * @brief Unique device ID register base address
- */
-#define UID_BASE_ADDRESS              UID_BASE
-
-/**
- * @brief Flash size data register base address
- */
-#define FLASHSIZE_BASE_ADDRESS        FLASHSIZE_BASE
-
-/**
- * @brief Package data register base address
- */
-#define PACKAGE_BASE_ADDRESS          PACKAGE_BASE
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
-  * @{
-  */
-/**
-  * @}
-  */
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
-  * @{
-  */
-/**
-  * @brief  UTILS PLL structure definition
-  */
-typedef struct
-{
-  uint32_t PLLM;   /*!< Division factor for PLL VCO input clock.
-                        This parameter must be a number between Min_Data = 0 and Max_Data = 63
-
-                        This feature can be modified afterwards using unitary function
-                        @ref LL_RCC_PLL1_SetM(). */
-
-  uint32_t PLLN;   /*!< Multiplication factor for PLL VCO output clock.
-                        This parameter must be a number between Min_Data = 4 and Max_Data = 512
-
-                        This feature can be modified afterwards using unitary function
-                        @ref LL_RCC_PLL1_SetN(). */
-
-  uint32_t PLLP;   /*!< Division for the main system clock.
-                        This parameter must be a number between Min_Data = 2 and Max_Data = 128
-                          odd division factors are not allowed
-
-                        This feature can be modified afterwards using unitary function
-                        @ref LL_RCC_PLL1_SetP(). */
-
-  uint32_t FRACN;  /*!< Fractional part of the multiplication factor for PLL VCO.
-                        This parameter can be a value between 0 and 8191
-
-                        This feature can be modified afterwards using unitary function
-                        @ref LL_RCC_PLL1_SetFRACN(). */
-
-  uint32_t VCO_Input;  /*!< PLL clock Input range.
-                        This parameter can be a value of @ref RCC_LL_EC_PLLINPUTRANGE
-
-                        This feature can be modified afterwards using unitary function
-                        @ref LL_RCC_PLL1_SetVCOInputRange(). */
-
-  uint32_t VCO_Output;  /*!< PLL clock Output range.
-                        This parameter can be a value of @ref RCC_LL_EC_PLLVCORANGE
-
-                      This feature can be modified afterwards using unitary function
-                      @ref LL_RCC_PLL1_SetVCOOutputRange(). */
-
-} LL_UTILS_PLLInitTypeDef;
-
-/**
-  * @brief  UTILS System, AHB and APB buses clock configuration structure definition
-  */
-typedef struct
-{
-  uint32_t SYSCLKDivider;         /*!< The System clock (SYSCLK) divider. This clock is derived from the PLL output.
-                                     This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
-
-                                     This feature can be modified afterwards using unitary function
-                                     @ref LL_RCC_SetSysPrescaler(). */
-
-  uint32_t AHBCLKDivider;         /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
-                                       This parameter can be a value of @ref RCC_LL_EC_AHB_DIV
-
-                                       This feature can be modified afterwards using unitary function
-                                       @ref LL_RCC_SetAHBPrescaler(). */
-
-  uint32_t APB1CLKDivider;        /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
-                                       This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
-
-                                       This feature can be modified afterwards using unitary function
-                                       @ref LL_RCC_SetAPB1Prescaler(). */
-
-  uint32_t APB2CLKDivider;        /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
-                                       This parameter can be a value of @ref RCC_LL_EC_APB2_DIV
-
-                                       This feature can be modified afterwards using unitary function
-                                       @ref LL_RCC_SetAPB2Prescaler(). */
-
-  uint32_t APB3CLKDivider;        /*!< The APB2 clock (PCLK3) divider. This clock is derived from the AHB clock (HCLK).
-                                       This parameter can be a value of @ref RCC_LL_EC_APB3_DIV
-
-                                       This feature can be modified afterwards using unitary function
-                                       @ref LL_RCC_SetAPB3Prescaler(). */
-
-  uint32_t APB4CLKDivider;        /*!< The APB4 clock (PCLK4) divider. This clock is derived from the AHB clock (HCLK).
-                                       This parameter can be a value of @ref RCC_LL_EC_APB4_DIV
-
-                                       This feature can be modified afterwards using unitary function
-                                       @ref LL_RCC_SetAPB4Prescaler(). */
-
-} LL_UTILS_ClkInitTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
-  * @{
-  */
-
-/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
-  * @{
-  */
-#define LL_UTILS_HSEBYPASS_OFF        0x00000000U       /*!< HSE Bypass is not enabled                */
-#define LL_UTILS_HSEBYPASS_ON         0x00000001U       /*!< HSE Bypass is enabled                    */
-/**
-  * @}
-  */
-
-/** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE
-  * @{
-  */
-#if (STM32H7_DEV_ID == 0x450UL)
-#define LL_UTILS_PACKAGETYPE_LQFP100            LL_SYSCFG_LQFP100_PACKAGE          /*!< LQFP100 package type             */
-#define LL_UTILS_PACKAGETYPE_TQFP144            LL_SYSCFG_TQFP144_PACKAGE          /*!< TQFP144 package type             */
-#define LL_UTILS_PACKAGETYPE_TQFP176_UFBGA176   LL_SYSCFG_TQFP176_UFBGA176_PACKAGE /*!< TQFP176 or UFBGA176 package type */
-#define LL_UTILS_PACKAGETYPE_LQFP208_TFBGA240   LL_SYSCFG_LQFP208_TFBGA240_PACKAGE /*!< LQFP208 or TFBGA240 package type */
-#elif (STM32H7_DEV_ID == 0x480UL)
-#define LL_UTILS_PACKAGETYPE_LQFP64                  0x00000000UL                  /*!< LQFP64 package type              */
-#define LL_UTILS_PACKAGETYPE_TFBGA100_LQFP100        0x00000001UL                  /*!< TFBGA100 or LQFP100 package type */
-#define LL_UTILS_PACKAGETYPE_LQFP100_SMPS            0x00000002UL                  /*!< LQFP100  with SMPS package type  */
-#define LL_UTILS_PACKAGETYPE_TFBGA100_SMPS           0x00000003UL                  /*!< TFBGA100 with SMPS package type  */
-#define LL_UTILS_PACKAGETYPE_WLCSP132_SMPS           0x00000004UL                  /*!< WLCSP132 package type            */
-#define LL_UTILS_PACKAGETYPE_LQFP144                 0x00000005UL                  /*!< LQFP144 package type             */
-#define LL_UTILS_PACKAGETYPE_LQFP144_SMPS            0x00000006UL                  /*!< LQFP144 with SMPS package type   */
-#define LL_UTILS_PACKAGETYPE_UFBGA169                0x00000007UL                  /*!< UFBGA169 package type            */
-#define LL_UTILS_PACKAGETYPE_UFBGA176_LQFP176        0x00000008UL                  /*!< UFBGA176 or LQFP176 package type */
-#define LL_UTILS_PACKAGETYPE_LQFP176_SMPS            0x00000009UL                  /*!< LQFP176 with SMPS package type   */
-#define LL_UTILS_PACKAGETYPE_UFBGA176_SMPS           0x0000000AUL                  /*!< UFBGA176 with SMPS package type  */
-#define LL_UTILS_PACKAGETYPE_TFBGA216                0x0000000CUL                  /*!< TFBGA216  package type           */
-#define LL_UTILS_PACKAGETYPE_TFBGA225                0x0000000EUL                  /*!< TFBGA225  package type           */
-#elif (STM32H7_DEV_ID == 0x483UL)
-#define LL_UTILS_PACKAGETYPE_VFQFPN68_INDUS         LL_SYSCFG_VFQFPN68_INDUS_PACKAGE         /*!< VFQFPN68 Industrial package type */
-#define LL_UTILS_PACKAGETYPE_TFBGA100_LQFP100       LL_SYSCFG_TFBGA100_LQFP100_PACKAGE       /*!< TFBGA100 or LQFP100 Legacy package type */
-#define LL_UTILS_PACKAGETYPE_LQFP100_INDUS          LL_SYSCFG_LQFP100_INDUS_PACKAGE          /*!< LQFP100 Industrial package type  */
-#define LL_UTILS_PACKAGETYPE_TFBGA100_INDUS         LL_SYSCFG_TFBGA100_INDUS_PACKAGE         /*!< TFBGA100 Industrial package type */
-#define LL_UTILS_PACKAGETYPE_WLCSP115_INDUS         LL_SYSCFG_WLCSP115_INDUS_PACKAGE         /*!< WLCSP115 Industrial package type */
-#define LL_UTILS_PACKAGETYPE_LQFP144                LL_SYSCFG_LQFP144_PACKAGE                /*!< LQFP144 Legacy package type      */
-#define LL_UTILS_PACKAGETYPE_UFBGA144               LL_SYSCFG_UFBGA144_PACKAGE               /*!< UFBGA144 Legacy package type     */
-#define LL_UTILS_PACKAGETYPE_LQFP144_INDUS          LL_SYSCFG_LQFP144_INDUS_PACKAGE          /*!< LQFP144 Industrial package type  */
-#define LL_UTILS_PACKAGETYPE_UFBGA169_INDUS         LL_SYSCFG_UFBGA169_INDUS_PACKAGE         /*!< UFBGA169 Industrial package type */
-#define LL_UTILS_PACKAGETYPE_UFBGA176PLUS25_INDUS   LL_SYSCFG_UFBGA176PLUS25_INDUS_PACKAGE   /*!< UFBGA176+25 Industrial package type   */
-#define LL_UTILS_PACKAGETYPE_LQFP176_INDUS          LL_SYSCFG_LQFP176_INDUS_PACKAGE          /*!< LQFP176 Industrial package type  */
-#endif /* STM32H7_DEV_ID == 0x450UL */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
-  * @{
-  */
-
-/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
-  * @{
-  */
-
-/**
-  * @brief  Get Word0 of the unique device identifier (UID based on 96 bits)
-  * @retval UID[31:0]
-  */
-__STATIC_INLINE uint32_t LL_GetUID_Word0(void)
-{
-  return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
-}
-
-/**
-  * @brief  Get Word1 of the unique device identifier (UID based on 96 bits)
-  * @retval UID[63:32]
-  */
-__STATIC_INLINE uint32_t LL_GetUID_Word1(void)
-{
-  return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
-}
-
-/**
-  * @brief  Get Word2 of the unique device identifier (UID based on 96 bits)
-  * @retval UID[95:64]
-  */
-__STATIC_INLINE uint32_t LL_GetUID_Word2(void)
-{
-  return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
-}
-
-/**
-  * @brief  Get Flash memory size
-  * @note   This bitfield indicates the size of the device Flash memory expressed in
-  *         Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
-  * @retval FLASH_SIZE[15:0]: Flash memory size
-  */
-__STATIC_INLINE uint32_t LL_GetFlashSize(void)
-{
-  return (uint16_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)));
-}
-
-/**
-  * @brief  Get Package type
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP100
-  *         @arg @ref LL_UTILS_PACKAGETYPE_TQFP144
-  *         @arg @ref LL_UTILS_PACKAGETYPE_TQFP176_UFBGA176
-  *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP208_TFBGA240
-  *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP64 (*)
-  *         @arg @ref LL_UTILS_PACKAGETYPE_TFBGA100_LQFP100  (*)
-  *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP100_SMPS  (*)
-  *         @arg @ref LL_UTILS_PACKAGETYPE_TFBGA100_SMPS  (*)
-  *         @arg @ref LL_UTILS_PACKAGETYPE_WLCSP132_SMPS  (*)
-  *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP144     (*)
-  *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP144_SMPS (*)
-  *         @arg @ref LL_UTILS_PACKAGETYPE_UFBGA169  (*)
-  *         @arg @ref LL_UTILS_PACKAGETYPE_UFBGA176_LQFP176  (*)
-  *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP176_SMPS    (*)
-  *         @arg @ref LL_UTILS_PACKAGETYPE_UFBGA176_SMPS   (*)
-  *         @arg @ref LL_UTILS_PACKAGETYPE_TFBGA216   (*)
-  *         @arg @ref LL_UTILS_PACKAGETYPE_TFBGA225   (*)
-  *         @arg @ref LL_UTILS_PACKAGETYPE_VFQFPN68_INDUS   (*)
-  *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP100_INDUS   (*)
-  *         @arg @ref LL_UTILS_PACKAGETYPE_TFBGA100_INDUS   (*)
-  *         @arg @ref LL_UTILS_PACKAGETYPE_WLCSP115_INDUS   (*)
-  *         @arg @ref LL_UTILS_PACKAGETYPE_UFBGA144   (*)
-  *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP144_INDUS   (*)
-  *         @arg @ref LL_UTILS_PACKAGETYPE_UFBGA169_INDUS   (*)
-  *         @arg @ref LL_UTILS_PACKAGETYPE_UFBGA176+25_INDUS   (*)
-  *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP176_INDUS   (*)
-  *
-  *        (*) Packages available on some STM32H7 lines only.
-  * @note   For some SM32H7 lines, enabling the SYSCFG clock is mandatory.
-            the SYSCFG clock enabling is ensured by LL_APB4_GRP1_EnableClock
-  */
-__STATIC_INLINE uint32_t LL_GetPackageType(void)
-{
-#if defined(SYSCFG_PKGR_PKG)
-
-  return LL_SYSCFG_GetPackage();
-#else
-   return (uint16_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)));
-
-#endif  /* SYSCFG_PKGR_PKG */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup UTILS_LL_EF_DELAY DELAY
-  * @{
-  */
-
-/**
-  * @brief  This function configures the Cortex-M SysTick source of the time base.
-  * @param  HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
-  * @note   When a RTOS is used, it is recommended to avoid changing the SysTick
-  *         configuration by calling this function, for a delay use rather osDelay RTOS service.
-  * @param  Ticks Number of ticks
-  * @retval None
-  */
-__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
-{
-  /* Configure the SysTick to have interrupt in 1ms time base */
-  SysTick->LOAD  = (uint32_t)((HCLKFrequency / Ticks) - 1UL);  /* set reload register */
-  SysTick->VAL   = 0UL;                                       /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_ENABLE_Msk;                   /* Enable the Systick Timer */
-}
-
-void        LL_Init1msTick(uint32_t CPU_Frequency);
-void        LL_mDelay(uint32_t Delay);
-
-/**
-  * @}
-  */
-
-/** @defgroup UTILS_EF_SYSTEM SYSTEM
-  * @{
-  */
-
-void        LL_SetSystemCoreClock(uint32_t CPU_Frequency);
-ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
-                                         LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
-ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency,
-                                         uint32_t HSEBypass,
-                                         LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
-                                         LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
-ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32H7xx_LL_UTILS_H */
-
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_ll_utils.h
+  * @author  MCD Application Team
+  * @brief   Header file of UTILS LL module.
+  ******************************************************************************
+  * @attention
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    The LL UTILS driver contains a set of generic APIs that can be
+    used by user:
+      (+) Device electronic signature
+      (+) Timing functions
+      (+) PLL configuration functions
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_LL_UTILS_H
+#define STM32H7xx_LL_UTILS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx.h"
+#include "stm32h7xx_ll_system.h"
+#include "stm32h7xx_ll_bus.h"
+
+/** @addtogroup STM32H7xx_LL_Driver
+  * @{
+  */
+
+/** @defgroup UTILS_LL UTILS
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
+  * @{
+  */
+
+/* Max delay can be used in LL_mDelay */
+#define LL_MAX_DELAY                  0xFFFFFFFFU
+
+/**
+ * @brief Unique device ID register base address
+ */
+#define UID_BASE_ADDRESS              UID_BASE
+
+/**
+ * @brief Flash size data register base address
+ */
+#define FLASHSIZE_BASE_ADDRESS        FLASHSIZE_BASE
+
+/**
+ * @brief Package data register base address
+ */
+#define PACKAGE_BASE_ADDRESS          PACKAGE_BASE
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
+  * @{
+  */
+/**
+  * @}
+  */
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
+  * @{
+  */
+/**
+  * @brief  UTILS PLL structure definition
+  */
+typedef struct
+{
+  uint32_t PLLM;   /*!< Division factor for PLL VCO input clock.
+                        This parameter must be a number between Min_Data = 0 and Max_Data = 63
+
+                        This feature can be modified afterwards using unitary function
+                        @ref LL_RCC_PLL1_SetM(). */
+
+  uint32_t PLLN;   /*!< Multiplication factor for PLL VCO output clock.
+                        This parameter must be a number between Min_Data = 4 and Max_Data = 512
+
+                        This feature can be modified afterwards using unitary function
+                        @ref LL_RCC_PLL1_SetN(). */
+
+  uint32_t PLLP;   /*!< Division for the main system clock.
+                        This parameter must be a number between Min_Data = 2 and Max_Data = 128
+                          odd division factors are not allowed
+
+                        This feature can be modified afterwards using unitary function
+                        @ref LL_RCC_PLL1_SetP(). */
+
+  uint32_t FRACN;  /*!< Fractional part of the multiplication factor for PLL VCO.
+                        This parameter can be a value between 0 and 8191
+
+                        This feature can be modified afterwards using unitary function
+                        @ref LL_RCC_PLL1_SetFRACN(). */
+
+  uint32_t VCO_Input;  /*!< PLL clock Input range.
+                        This parameter can be a value of @ref RCC_LL_EC_PLLINPUTRANGE
+
+                        This feature can be modified afterwards using unitary function
+                        @ref LL_RCC_PLL1_SetVCOInputRange(). */
+
+  uint32_t VCO_Output;  /*!< PLL clock Output range.
+                        This parameter can be a value of @ref RCC_LL_EC_PLLVCORANGE
+
+                      This feature can be modified afterwards using unitary function
+                      @ref LL_RCC_PLL1_SetVCOOutputRange(). */
+
+} LL_UTILS_PLLInitTypeDef;
+
+/**
+  * @brief  UTILS System, AHB and APB buses clock configuration structure definition
+  */
+typedef struct
+{
+  uint32_t SYSCLKDivider;         /*!< The System clock (SYSCLK) divider. This clock is derived from the PLL output.
+                                     This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
+
+                                     This feature can be modified afterwards using unitary function
+                                     @ref LL_RCC_SetSysPrescaler(). */
+
+  uint32_t AHBCLKDivider;         /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
+                                       This parameter can be a value of @ref RCC_LL_EC_AHB_DIV
+
+                                       This feature can be modified afterwards using unitary function
+                                       @ref LL_RCC_SetAHBPrescaler(). */
+
+  uint32_t APB1CLKDivider;        /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
+                                       This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
+
+                                       This feature can be modified afterwards using unitary function
+                                       @ref LL_RCC_SetAPB1Prescaler(). */
+
+  uint32_t APB2CLKDivider;        /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
+                                       This parameter can be a value of @ref RCC_LL_EC_APB2_DIV
+
+                                       This feature can be modified afterwards using unitary function
+                                       @ref LL_RCC_SetAPB2Prescaler(). */
+
+  uint32_t APB3CLKDivider;        /*!< The APB2 clock (PCLK3) divider. This clock is derived from the AHB clock (HCLK).
+                                       This parameter can be a value of @ref RCC_LL_EC_APB3_DIV
+
+                                       This feature can be modified afterwards using unitary function
+                                       @ref LL_RCC_SetAPB3Prescaler(). */
+
+  uint32_t APB4CLKDivider;        /*!< The APB4 clock (PCLK4) divider. This clock is derived from the AHB clock (HCLK).
+                                       This parameter can be a value of @ref RCC_LL_EC_APB4_DIV
+
+                                       This feature can be modified afterwards using unitary function
+                                       @ref LL_RCC_SetAPB4Prescaler(). */
+
+} LL_UTILS_ClkInitTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
+  * @{
+  */
+
+/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
+  * @{
+  */
+#define LL_UTILS_HSEBYPASS_OFF        0x00000000U       /*!< HSE Bypass is not enabled                */
+#define LL_UTILS_HSEBYPASS_ON         0x00000001U       /*!< HSE Bypass is enabled                    */
+/**
+  * @}
+  */
+
+/** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE
+  * @{
+  */
+#if (STM32H7_DEV_ID == 0x450UL)
+#define LL_UTILS_PACKAGETYPE_LQFP100            LL_SYSCFG_LQFP100_PACKAGE          /*!< LQFP100 package type             */
+#define LL_UTILS_PACKAGETYPE_TQFP144            LL_SYSCFG_TQFP144_PACKAGE          /*!< TQFP144 package type             */
+#define LL_UTILS_PACKAGETYPE_TQFP176_UFBGA176   LL_SYSCFG_TQFP176_UFBGA176_PACKAGE /*!< TQFP176 or UFBGA176 package type */
+#define LL_UTILS_PACKAGETYPE_LQFP208_TFBGA240   LL_SYSCFG_LQFP208_TFBGA240_PACKAGE /*!< LQFP208 or TFBGA240 package type */
+#elif (STM32H7_DEV_ID == 0x480UL)
+#define LL_UTILS_PACKAGETYPE_LQFP64                  0x00000000UL                  /*!< LQFP64 package type              */
+#define LL_UTILS_PACKAGETYPE_TFBGA100_LQFP100        0x00000001UL                  /*!< TFBGA100 or LQFP100 package type */
+#define LL_UTILS_PACKAGETYPE_LQFP100_SMPS            0x00000002UL                  /*!< LQFP100  with SMPS package type  */
+#define LL_UTILS_PACKAGETYPE_TFBGA100_SMPS           0x00000003UL                  /*!< TFBGA100 with SMPS package type  */
+#define LL_UTILS_PACKAGETYPE_WLCSP132_SMPS           0x00000004UL                  /*!< WLCSP132 package type            */
+#define LL_UTILS_PACKAGETYPE_LQFP144                 0x00000005UL                  /*!< LQFP144 package type             */
+#define LL_UTILS_PACKAGETYPE_LQFP144_SMPS            0x00000006UL                  /*!< LQFP144 with SMPS package type   */
+#define LL_UTILS_PACKAGETYPE_UFBGA169                0x00000007UL                  /*!< UFBGA169 package type            */
+#define LL_UTILS_PACKAGETYPE_UFBGA176_LQFP176        0x00000008UL                  /*!< UFBGA176 or LQFP176 package type */
+#define LL_UTILS_PACKAGETYPE_LQFP176_SMPS            0x00000009UL                  /*!< LQFP176 with SMPS package type   */
+#define LL_UTILS_PACKAGETYPE_UFBGA176_SMPS           0x0000000AUL                  /*!< UFBGA176 with SMPS package type  */
+#define LL_UTILS_PACKAGETYPE_TFBGA216                0x0000000CUL                  /*!< TFBGA216  package type           */
+#define LL_UTILS_PACKAGETYPE_TFBGA225                0x0000000EUL                  /*!< TFBGA225  package type           */
+#elif (STM32H7_DEV_ID == 0x483UL)
+#define LL_UTILS_PACKAGETYPE_VFQFPN68_INDUS         LL_SYSCFG_VFQFPN68_INDUS_PACKAGE         /*!< VFQFPN68 Industrial package type */
+#define LL_UTILS_PACKAGETYPE_TFBGA100_LQFP100       LL_SYSCFG_TFBGA100_LQFP100_PACKAGE       /*!< TFBGA100 or LQFP100 Legacy package type */
+#define LL_UTILS_PACKAGETYPE_LQFP100_INDUS          LL_SYSCFG_LQFP100_INDUS_PACKAGE          /*!< LQFP100 Industrial package type  */
+#define LL_UTILS_PACKAGETYPE_TFBGA100_INDUS         LL_SYSCFG_TFBGA100_INDUS_PACKAGE         /*!< TFBGA100 Industrial package type */
+#define LL_UTILS_PACKAGETYPE_WLCSP115_INDUS         LL_SYSCFG_WLCSP115_INDUS_PACKAGE         /*!< WLCSP115 Industrial package type */
+#define LL_UTILS_PACKAGETYPE_LQFP144                LL_SYSCFG_LQFP144_PACKAGE                /*!< LQFP144 Legacy package type      */
+#define LL_UTILS_PACKAGETYPE_UFBGA144               LL_SYSCFG_UFBGA144_PACKAGE               /*!< UFBGA144 Legacy package type     */
+#define LL_UTILS_PACKAGETYPE_LQFP144_INDUS          LL_SYSCFG_LQFP144_INDUS_PACKAGE          /*!< LQFP144 Industrial package type  */
+#define LL_UTILS_PACKAGETYPE_UFBGA169_INDUS         LL_SYSCFG_UFBGA169_INDUS_PACKAGE         /*!< UFBGA169 Industrial package type */
+#define LL_UTILS_PACKAGETYPE_UFBGA176PLUS25_INDUS   LL_SYSCFG_UFBGA176PLUS25_INDUS_PACKAGE   /*!< UFBGA176+25 Industrial package type   */
+#define LL_UTILS_PACKAGETYPE_LQFP176_INDUS          LL_SYSCFG_LQFP176_INDUS_PACKAGE          /*!< LQFP176 Industrial package type  */
+#endif /* STM32H7_DEV_ID == 0x450UL */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
+  * @{
+  */
+
+/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
+  * @{
+  */
+
+/**
+  * @brief  Get Word0 of the unique device identifier (UID based on 96 bits)
+  * @retval UID[31:0]
+  */
+__STATIC_INLINE uint32_t LL_GetUID_Word0(void)
+{
+  return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
+}
+
+/**
+  * @brief  Get Word1 of the unique device identifier (UID based on 96 bits)
+  * @retval UID[63:32]
+  */
+__STATIC_INLINE uint32_t LL_GetUID_Word1(void)
+{
+  return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
+}
+
+/**
+  * @brief  Get Word2 of the unique device identifier (UID based on 96 bits)
+  * @retval UID[95:64]
+  */
+__STATIC_INLINE uint32_t LL_GetUID_Word2(void)
+{
+  return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
+}
+
+/**
+  * @brief  Get Flash memory size
+  * @note   This bitfield indicates the size of the device Flash memory expressed in
+  *         Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
+  * @retval FLASH_SIZE[15:0]: Flash memory size
+  */
+__STATIC_INLINE uint32_t LL_GetFlashSize(void)
+{
+  return (uint16_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)));
+}
+
+/**
+  * @brief  Get Package type
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP100
+  *         @arg @ref LL_UTILS_PACKAGETYPE_TQFP144
+  *         @arg @ref LL_UTILS_PACKAGETYPE_TQFP176_UFBGA176
+  *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP208_TFBGA240
+  *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP64 (*)
+  *         @arg @ref LL_UTILS_PACKAGETYPE_TFBGA100_LQFP100  (*)
+  *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP100_SMPS  (*)
+  *         @arg @ref LL_UTILS_PACKAGETYPE_TFBGA100_SMPS  (*)
+  *         @arg @ref LL_UTILS_PACKAGETYPE_WLCSP132_SMPS  (*)
+  *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP144     (*)
+  *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP144_SMPS (*)
+  *         @arg @ref LL_UTILS_PACKAGETYPE_UFBGA169  (*)
+  *         @arg @ref LL_UTILS_PACKAGETYPE_UFBGA176_LQFP176  (*)
+  *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP176_SMPS    (*)
+  *         @arg @ref LL_UTILS_PACKAGETYPE_UFBGA176_SMPS   (*)
+  *         @arg @ref LL_UTILS_PACKAGETYPE_TFBGA216   (*)
+  *         @arg @ref LL_UTILS_PACKAGETYPE_TFBGA225   (*)
+  *         @arg @ref LL_UTILS_PACKAGETYPE_VFQFPN68_INDUS   (*)
+  *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP100_INDUS   (*)
+  *         @arg @ref LL_UTILS_PACKAGETYPE_TFBGA100_INDUS   (*)
+  *         @arg @ref LL_UTILS_PACKAGETYPE_WLCSP115_INDUS   (*)
+  *         @arg @ref LL_UTILS_PACKAGETYPE_UFBGA144   (*)
+  *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP144_INDUS   (*)
+  *         @arg @ref LL_UTILS_PACKAGETYPE_UFBGA169_INDUS   (*)
+  *         @arg @ref LL_UTILS_PACKAGETYPE_UFBGA176+25_INDUS   (*)
+  *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP176_INDUS   (*)
+  *
+  *        (*) Packages available on some STM32H7 lines only.
+  * @note   For some SM32H7 lines, enabling the SYSCFG clock is mandatory.
+            the SYSCFG clock enabling is ensured by LL_APB4_GRP1_EnableClock
+  */
+__STATIC_INLINE uint32_t LL_GetPackageType(void)
+{
+#if defined(SYSCFG_PKGR_PKG)
+
+  return LL_SYSCFG_GetPackage();
+#else
+   return (uint16_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)));
+
+#endif  /* SYSCFG_PKGR_PKG */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup UTILS_LL_EF_DELAY DELAY
+  * @{
+  */
+
+/**
+  * @brief  This function configures the Cortex-M SysTick source of the time base.
+  * @param  HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
+  * @note   When a RTOS is used, it is recommended to avoid changing the SysTick
+  *         configuration by calling this function, for a delay use rather osDelay RTOS service.
+  * @param  Ticks Number of ticks
+  * @retval None
+  */
+__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
+{
+  /* Configure the SysTick to have interrupt in 1ms time base */
+  SysTick->LOAD  = (uint32_t)((HCLKFrequency / Ticks) - 1UL);  /* set reload register */
+  SysTick->VAL   = 0UL;                                       /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_ENABLE_Msk;                   /* Enable the Systick Timer */
+}
+
+void        LL_Init1msTick(uint32_t CPU_Frequency);
+void        LL_mDelay(uint32_t Delay);
+
+/**
+  * @}
+  */
+
+/** @defgroup UTILS_EF_SYSTEM SYSTEM
+  * @{
+  */
+
+void        LL_SetSystemCoreClock(uint32_t CPU_Frequency);
+ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
+                                         LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
+ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency,
+                                         uint32_t HSEBypass,
+                                         LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
+                                         LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
+ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_LL_UTILS_H */
+
diff --git a/Drivers/STM32H7xx_HAL_Driver/LICENSE.txt b/Drivers/STM32H7xx_HAL_Driver/LICENSE.txt
index 3edc4d14..b40364c2 100644
--- a/Drivers/STM32H7xx_HAL_Driver/LICENSE.txt
+++ b/Drivers/STM32H7xx_HAL_Driver/LICENSE.txt
@@ -1,6 +1,6 @@
-This software component is provided to you as part of a software package and
-applicable license terms are in the  Package_license file. If you received this
-software component outside of a package or without applicable license terms,
-the terms of the BSD-3-Clause license shall apply. 
-You may obtain a copy of the BSD-3-Clause at:
-https://opensource.org/licenses/BSD-3-Clause
+This software component is provided to you as part of a software package and
+applicable license terms are in the  Package_license file. If you received this
+software component outside of a package or without applicable license terms,
+the terms of the BSD-3-Clause license shall apply. 
+You may obtain a copy of the BSD-3-Clause at:
+https://opensource.org/licenses/BSD-3-Clause
diff --git a/ECU.ioc b/ECU.ioc
index d9c5750f..881466c9 100644
--- a/ECU.ioc
+++ b/ECU.ioc
@@ -33,6 +33,9 @@ ADC1.SamplingTime-3\#ChannelRegularConversion=ADC_SAMPLETIME_810CYCLES_5
 ADC1.SamplingTime-4\#ChannelRegularConversion=ADC_SAMPLETIME_810CYCLES_5
 ADC1.SamplingTime-5\#ChannelRegularConversion=ADC_SAMPLETIME_810CYCLES_5
 ADC1.master=1
+CAD.formats=
+CAD.pinconfig=
+CAD.provider=
 Dma.ADC1.0.Direction=DMA_PERIPH_TO_MEMORY
 Dma.ADC1.0.EventEnable=DISABLE
 Dma.ADC1.0.FIFOMode=DMA_FIFOMODE_DISABLE
@@ -93,7 +96,7 @@ FREERTOS.FootprintOK=true
 FREERTOS.IPParameters=Tasks01,configMINIMAL_STACK_SIZE,FootprintOK,Queues01,configMAX_TASK_NAME_LEN,Mutexes01,configENABLE_FPU,configTOTAL_HEAP_SIZE,configUSE_MALLOC_FAILED_HOOK,configUSE_STATS_FORMATTING_FUNCTIONS,configCHECK_FOR_STACK_OVERFLOW,Timers01,Events01
 FREERTOS.Mutexes01=m_state_parameter_mutex,Dynamic,NULL
 FREERTOS.Queues01=q_encoder_int_message,16,encoder_int_message_t,0,Dynamic,NULL,NULL;q_torque_message,16,torque_message_t,0,Dynamic,NULL,NULL;q_ref_torque_message,16,ref_torque_t,0,Dynamic,NULL,NULL;q_datalog_message,128,datalog_message_t,0,Dynamic,NULL,NULL;q_debug_leds_message,16,debug_led_message_t,0,Dynamic,NULL,NULL;q_rgb_led_message,16,rgb_led_message_t,0,Dynamic,NULL,NULL;q_throttle_control,16,uint16_t,0,Dynamic,NULL,NULL;q_encoder_speeds_message,1,encoder_speeds_message_t,0,Dynamic,NULL,NULL;q_odometer_calc_save_message,1,odometer_message_t,0,Dynamic,NULL,NULL;q_ids_can_inverter,32,uint32_t,0,Dynamic,NULL,NULL
-FREERTOS.Tasks01=t_main_task,24,1024,main_task,As weak,NULL,Dynamic,NULL,NULL;t_torque_parameters,8,1024,torque_parameters,As external,NULL,Dynamic,NULL,NULL;t_datalogger,8,1024,datalogger,As external,NULL,Dynamic,NULL,NULL;t_APPS_read,8,1024,APPS_read,As external,NULL,Dynamic,NULL,NULL;t_steering_read,8,1024,steering_read,As external,NULL,Dynamic,NULL,NULL;t_encoder_speed_calc,8,1024,encoder_speed_calc,As external,NULL,Dynamic,NULL,NULL;t_odometer_calc,8,1024,odometer_calc,As external,NULL,Dynamic,NULL,NULL;t_torque_message,8,1024,torque_message,As external,NULL,Dynamic,NULL,NULL;t_torque_manager,8,1024,torque_manager,As external,NULL,Dynamic,NULL,NULL;t_debug_leds,8,1024,debug_leds,As external,NULL,Dynamic,NULL,NULL;t_rgb_led,8,1024,rgb_led,As external,NULL,Dynamic,NULL,NULL;t_seleciona_modo,8,1024,seleciona_modo,As external,NULL,Dynamic,NULL,NULL;t_RTD,8,1024,RTD,As external,NULL,Dynamic,NULL,NULL;t_throttle_control,8,1024,throttle_control,As external,NULL,Dynamic,NULL,NULL;t_datalog_acquisition,8,1024,datalog_acquisition,As external,NULL,Dynamic,NULL,NULL;t_inverter_comm_error,8,1024,inverter_comm_error,As external,NULL,Dynamic,NULL,NULL;t_inverter_datalog,8,1024,inverter_datalog,As external,NULL,Dynamic,NULL,NULL;t_pilot_reset,8,1024,pilot_reset,As external,NULL,Dynamic,NULL,NULL;t_buttons_handler,8,1024,buttons_handler,As external,NULL,Dynamic,NULL,NULL;t_speed_datalog,8,1024,speed_datalog,As external,NULL,Dynamic,NULL,NULL;t_odometer_save,8,1024,odometer_save,As external,NULL,Dynamic,NULL,NULL;t_dynamic_controls_choice,8,1024,dynamic_controls_choice,As external,NULL,Dynamic,NULL,NULL
+FREERTOS.Tasks01=t_main_task,24,1024,main_task,As weak,NULL,Dynamic,NULL,NULL;t_torque_parameters,8,1024,torque_parameters,As external,NULL,Dynamic,NULL,NULL;t_datalogger,8,1024,datalogger,As external,NULL,Dynamic,NULL,NULL;t_APPS_read,8,1024,APPS_read,As external,NULL,Dynamic,NULL,NULL;t_steering_read,8,1024,steering_read,As external,NULL,Dynamic,NULL,NULL;t_encoder_speed_calc,8,1024,encoder_speed_calc,As external,NULL,Dynamic,NULL,NULL;t_odometer_calc,8,1024,odometer_calc,As external,NULL,Dynamic,NULL,NULL;t_torque_message,8,1024,torque_message,As external,NULL,Dynamic,NULL,NULL;t_torque_manager,8,1024,torque_manager,As external,NULL,Dynamic,NULL,NULL;t_debug_leds,8,1024,debug_leds,As external,NULL,Dynamic,NULL,NULL;t_rgb_led,8,1024,rgb_led,As external,NULL,Dynamic,NULL,NULL;t_seleciona_modo,8,1024,seleciona_modo,As external,NULL,Dynamic,NULL,NULL;t_RTD,8,1024,RTD,As external,NULL,Dynamic,NULL,NULL;t_throttle_control,8,1024,throttle_control,As external,NULL,Dynamic,NULL,NULL;t_datalog_acquisition,8,1024,datalog_acquisition,As external,NULL,Dynamic,NULL,NULL;t_inverter_comm_error,8,1024,inverter_comm_error,As external,NULL,Dynamic,NULL,NULL;t_inverter_datalog,8,1024,inverter_datalog,As external,NULL,Dynamic,NULL,NULL;t_pilot_reset,8,1024,pilot_reset,As external,NULL,Dynamic,NULL,NULL;t_buttons_handler,8,1024,buttons_handler,As external,NULL,Dynamic,NULL,NULL;t_speed_datalog,8,1024,speed_datalog,As external,NULL,Dynamic,NULL,NULL;t_odometer_save,8,1024,odometer_save,As external,NULL,Dynamic,NULL,NULL;t_dynamic_controls_choice,8,1024,dynamic_controls_choice,As external,NULL,Dynamic,NULL,NULL;t_cross_validation,8,1024,cross_validation,As external,NULL,Dynamic,NULL,NULL
 FREERTOS.Timers01=tim_SU_F_error,errors_with_timer_callback,osTimerOnce,As external,SU_F_ERROR_FLAG,Dynamic,NULL;tim_APPS_error,errors_with_timer_callback,osTimerOnce,As external,APPS_ERROR_FLAG,Dynamic,NULL;tim_inverter_BUS_OFF_error,inverter_BUS_OFF_error_callback,osTimerOnce,As external,NULL,Dynamic,NULL;tim_inverter_ready,inverter_ready_callback,osTimerOnce,As external,NULL,Dynamic,NULL;tim_inverter_can_transmit_error,errors_with_timer_callback,osTimerOnce,As external,INVERTER_CAN_TRANSMIT_ERROR_FLAG,Dynamic,NULL;tim_left_inv_error,left_inv_error_callback,osTimerPeriodic,As external,LEFT_INVERTER_COMM_ERROR_FLAG,Dynamic,NULL;tim_right_inv_error,right_inv_error_callback,osTimerPeriodic,As external,RIGHT_INVERTER_COMM_ERROR_FLAG,Dynamic,NULL
 FREERTOS.configCHECK_FOR_STACK_OVERFLOW=2
 FREERTOS.configENABLE_FPU=1
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/LICENSE b/Middlewares/Third_Party/FreeRTOS/Source/LICENSE
index 2ce47118..d479d8b6 100644
--- a/Middlewares/Third_Party/FreeRTOS/Source/LICENSE
+++ b/Middlewares/Third_Party/FreeRTOS/Source/LICENSE
@@ -1,18 +1,18 @@
-Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
-Permission is hereby granted, free of charge, to any person obtaining a copy of
-this software and associated documentation files (the "Software"), to deal in
-the Software without restriction, including without limitation the rights to
-use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
-the Software, and to permit persons to whom the Software is furnished to do so,
-subject to the following conditions:
-
-The above copyright notice and this permission notice shall be included in all
-copies or substantial portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
-FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
-COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
-IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
+Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+Permission is hereby granted, free of charge, to any person obtaining a copy of
+this software and associated documentation files (the "Software"), to deal in
+the Software without restriction, including without limitation the rights to
+use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+the Software, and to permit persons to whom the Software is furnished to do so,
+subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
diff --git a/STM32H743VITX_FLASH.ld b/STM32H743VITX_FLASH.ld
index 47dfab6e..3d1dcb28 100644
--- a/STM32H743VITX_FLASH.ld
+++ b/STM32H743VITX_FLASH.ld
@@ -34,8 +34,8 @@ ENTRY(Reset_Handler)
 /* Highest address of the user mode stack */
 _estack = ORIGIN(RAM_D1) + LENGTH(RAM_D1);	/* end of "RAM_D1" Ram type memory */
 
-_Min_Heap_Size = 0x200 ;	/* required amount of heap  */
-_Min_Stack_Size = 0x400 ;	/* required amount of stack */
+_Min_Heap_Size = 0x200;	/* required amount of heap  */
+_Min_Stack_Size = 0x400;	/* required amount of stack */
 
 /* Memories definition */
 MEMORY

From 9660b35122b420b22ec6a7b8462d58e379a289a0 Mon Sep 17 00:00:00 2001
From: caiussouza <caiuscsouza@gmail.com>
Date: Tue, 7 Mar 2023 15:21:29 -0300
Subject: [PATCH 08/33] creation of timer

---
 .../dynamic_controls/security_architecture.h  |  4 +-
 Core/Inc/util/global_definitions.h            |  2 +-
 Core/Src/CAN/inverter_can_monitor.c           |  2 +-
 .../driver_settings/dynamic_controls_choice.c |  2 +
 .../dynamic_controls/security_architecture.c  | 19 +++++--
 Core/Src/main.c                               |  9 +++
 Core/Src/sensors/sensor_data_processing.c     | 55 +++++++++++++------
 Core/Src/torque_command/torque_manager.c      | 10 ++--
 ECU.ioc                                       |  2 +-
 9 files changed, 73 insertions(+), 32 deletions(-)

diff --git a/Core/Inc/dynamic_controls/security_architecture.h b/Core/Inc/dynamic_controls/security_architecture.h
index 65100a8c..f011d0a9 100644
--- a/Core/Inc/dynamic_controls/security_architecture.h
+++ b/Core/Inc/dynamic_controls/security_architecture.h
@@ -8,11 +8,13 @@
 #ifndef INC_DYNAMIC_CONTROLS_SECURITY_ARCHITECTURE_H_
 #define INC_DYNAMIC_CONTROLS_SECURITY_ARCHITECTURE_H_
 
-// TODO(caius): add the threshold values
+// TODO(caius): add the threshold values and the timer time
 #define IMU_LONG_ACCEL_THRESHOLD 1
 #define SPEED_MIN_THRESHOLD 1
 #define IMU_MAX_LONG_ACCEL_THRESHOLD 1
 
+#define CROSS_VALIDATION_ERROR_TIME 1
+
 uint8_t is_imu_bse_ok();
 uint8_t is_imu_speed_ok();
 
diff --git a/Core/Inc/util/global_definitions.h b/Core/Inc/util/global_definitions.h
index d4552b1f..b8946c31 100644
--- a/Core/Inc/util/global_definitions.h
+++ b/Core/Inc/util/global_definitions.h
@@ -111,12 +111,12 @@ typedef enum {
 #define INVERTER_READY_THREAD_FLAG                      (1 << 6)
 #define ODOMETER_SAVE_THREAD_FLAG                       (1 << 7)
 #define DYNAMIC_CONTROL_THREAD_FLAG                     (1 << 8)
+#define CROSS_VALIDATION_ERROR_THREAD_FLAG	  (1 << 9)
 
 // Warning flags	(No actions necessary)
 #define REGEN_WARN_FLAG           (1 << 10)
 #define DYNAMIC_CONTROL_WARN_FLAG (1 << 11)
 #define FLASH_SAVE_LIMIT_FLAG     (1 << 12)
-#define CROSS_VALIDATION_FLAG	  (1 << 13)
 // Soft error flags (RTD keeps on, torque ref to inverter is set to 0)
 
 #define BSE_ERROR_FLAG  (1 << 16) // Regulamento: EV.5.7 (2021)
diff --git a/Core/Src/CAN/inverter_can_monitor.c b/Core/Src/CAN/inverter_can_monitor.c
index 4e92cb33..88459daf 100644
--- a/Core/Src/CAN/inverter_can_monitor.c
+++ b/Core/Src/CAN/inverter_can_monitor.c
@@ -78,7 +78,7 @@ void right_inv_error_callback() {
 }
 
 void precharge_monitor() {
-    // start the timer only when the flag is reseted and the timer is not alredy
+    // start the timer only when the flag is reseted and the timer is not already
     // running to avoid restarting the timer
     if (!get_individual_flag(e_ECU_control_flagsHandle, INVERTER_READY_THREAD_FLAG)) {
         if (!osTimerIsRunning(tim_inverter_readyHandle)) {
diff --git a/Core/Src/driver_settings/dynamic_controls_choice.c b/Core/Src/driver_settings/dynamic_controls_choice.c
index 686b6473..f91d9572 100644
--- a/Core/Src/driver_settings/dynamic_controls_choice.c
+++ b/Core/Src/driver_settings/dynamic_controls_choice.c
@@ -33,8 +33,10 @@ void dynamic_controls_choice(void* argument) {
 
         if (!is_DYNAMIC_CONTROL_active) {
             osEventFlagsSet(e_ECU_control_flagsHandle, DYNAMIC_CONTROL_THREAD_FLAG);
+            osThreadFlagsSet(t_cross_validationHandle, DYNAMIC_CONTROL_THREAD_FLAG);
         } else {
             osEventFlagsClear(e_ECU_control_flagsHandle, DYNAMIC_CONTROL_THREAD_FLAG);
+            osThreadFlagsClear(DYNAMIC_CONTROL_THREAD_FLAG);
         }
     }
 }
diff --git a/Core/Src/dynamic_controls/security_architecture.c b/Core/Src/dynamic_controls/security_architecture.c
index 71c7fdf9..7baa996c 100644
--- a/Core/Src/dynamic_controls/security_architecture.c
+++ b/Core/Src/dynamic_controls/security_architecture.c
@@ -29,14 +29,19 @@ void cross_validation(void* argument) {
     for (;;) {
         ECU_ENABLE_BREAKPOINT_DEBUG();
 
+        osThreadFlagsWait();
+
+        // TODO(caius): fazer uma média mais genérica usando struct e um serviço pro buffer circular
         moving_average(&IMU_long_accel_filtered, raw_IMU_long_accel_data);
         moving_average(&speed_filtered, raw_speed_data);
 
-        if(!is_imu_bse_ok() || !is_imu_speed_ok())
-        	osEventFlagsSet(e_ECU_control_flagsHandle, CROSS_VALIDATION_FLAG);
-        else
-        	osEventFlagsClear(e_ECU_control_flagsHandle, CROSS_VALIDATION_FLAG);
-
+        if(!is_imu_bse_ok() || !is_imu_speed_ok()){
+        	osTimerStart(tim_cross_validation_errorHandle, CROSS_VALIDATION_ERROR_TIME);
+        }
+        else{
+        	osTimerStop(tim_cross_validation_errorHandle);
+        	osEventFlagsClear(e_ECU_control_flagsHandle, CROSS_VALIDATION_ERROR_THREAD_FLAG);
+        }
     }
 }
 
@@ -53,4 +58,8 @@ uint8_t is_imu_speed_ok(){
 	return 1;
 }
 
+void cross_validation_error_callback(){
+	osEventFlagsSet(e_ECU_control_flagsHandle, CROSS_VALIDATION_ERROR_FLAG);
+}
+
 
diff --git a/Core/Src/main.c b/Core/Src/main.c
index cf73f8bd..51b76f2d 100644
--- a/Core/Src/main.c
+++ b/Core/Src/main.c
@@ -313,6 +313,11 @@ osTimerId_t tim_right_inv_errorHandle;
 const osTimerAttr_t tim_right_inv_error_attributes = {
   .name = "tim_right_inv_error"
 };
+/* Definitions for tim_cross_validation_error */
+osTimerId_t tim_cross_validation_errorHandle;
+const osTimerAttr_t tim_cross_validation_error_attributes = {
+  .name = "tim_cross_validation_error"
+};
 /* Definitions for m_state_parameter_mutex */
 osMutexId_t m_state_parameter_mutexHandle;
 const osMutexAttr_t m_state_parameter_mutex_attributes = {
@@ -367,6 +372,7 @@ extern void inverter_BUS_OFF_error_callback(void *argument);
 extern void inverter_ready_callback(void *argument);
 extern void left_inv_error_callback(void *argument);
 extern void right_inv_error_callback(void *argument);
+extern void cross_validation_error_callback(void *argument);
 
 /* USER CODE BEGIN PFP */
 
@@ -454,6 +460,9 @@ int main(void)
   /* creation of tim_right_inv_error */
   tim_right_inv_errorHandle = osTimerNew(right_inv_error_callback, osTimerPeriodic, (void*) RIGHT_INVERTER_COMM_ERROR_FLAG, &tim_right_inv_error_attributes);
 
+  /* creation of tim_cross_validation_error */
+  tim_cross_validation_errorHandle = osTimerNew(cross_validation_error_callback, osTimerPeriodic, (void*) CROSS_VALIDATION_ERROR_THREAD_FLAG, &tim_cross_validation_error_attributes);
+
   /* USER CODE BEGIN RTOS_TIMERS */
   /* start timers, add new ones, ... */
   /* USER CODE END RTOS_TIMERS */
diff --git a/Core/Src/sensors/sensor_data_processing.c b/Core/Src/sensors/sensor_data_processing.c
index 7b30f33e..a82c7de3 100644
--- a/Core/Src/sensors/sensor_data_processing.c
+++ b/Core/Src/sensors/sensor_data_processing.c
@@ -20,7 +20,6 @@ void moving_average(uint16_t* mov_ave, uint16_t data) {
 	mov_ave = 0;
 
 	// Put the signal value read by sensor into each buffer position
-	movave_buffer[buffer_index] = data;// Put the signal value read by sensor into each buffer position
 	movave_buffer[buffer_index] = data;
 
 	// circular buffer logic
@@ -39,22 +38,42 @@ void moving_average(uint16_t* mov_ave, uint16_t data) {
 	if(buffer_index == 256)
 		buffer_index = 0;
 
-	// circular buffer logic
-	buffer_index = (buffer_index + 1) % BUFFER_SIZE;
-
-
-	// Calculate the moving average based on a mutable value
-	// It requires empirical tests for choosing that value
-	for(uint8_t i = 0; i < BUFFER_SIZE; i++){
-		buffer_sum += movave_buffer[i];
-	}
-	mov_ave = buffer_sum / BUFFER_SIZE;
-
-	// Avoid variable type overflow
-	buffer_sum = 0;
-	if(buffer_index == 256)
-		buffer_index = 0;
-
-
 }
 
+//vc define cada mov_ave pra cada tipo de dado. exemplo pro apps1
+//
+//moving_average_t apps1_mov_ave{
+//	uint16_t buffer_size = BUFFER_SIZE_APPS1;
+//	uint16_t data = uint_t taltaltal do adc talz;
+//};
+//
+// fazer o serviço do buffer circular
+// problemas: e se eu quiser um buffer maior ou um dado do tipo uint32_t?
+// como escolher o dado a partir disso? pré-processamento?
+//
+//void moving_average(moving_average_t* mov_ave){
+//	uint8_t buffer_index = 0;
+//	uint16_t movave_buffer[mov_ave->buffer_size];
+//	uint32_t buffer_sum = 0;
+//
+//	mov_ave = 0;
+//
+//	// Put the signal value read by sensor into each buffer position
+//	movave_buffer[buffer_index] = mov_ave->data;
+//
+//	// circular buffer logic
+//	buffer_index = (buffer_index + 1) % (mov_ave->buffer_size);
+//
+//
+//	// Calculate the moving average based on a mutable value
+//	// It requires empirical tests for choosing that value
+//	for(uint8_t i = 0; i < (mov_ave->buffer_size); i++){
+//		buffer_sum += movave_buffer[i];
+//	}
+//	mov_ave = buffer_sum / (mov_ave->buffer_size);
+//
+//	// Avoid variable type overflow
+//	buffer_sum = 0;
+//	if(buffer_index == 256)
+//		buffer_index = 0;
+//}
diff --git a/Core/Src/torque_command/torque_manager.c b/Core/Src/torque_command/torque_manager.c
index d0f82d0b..cff9d109 100644
--- a/Core/Src/torque_command/torque_manager.c
+++ b/Core/Src/torque_command/torque_manager.c
@@ -35,10 +35,10 @@ void torque_manager(void* argument) {
 
         const bool is_DYNAMIC_CONTROL_active =
             get_individual_flag(e_ECU_control_flagsHandle, DYNAMIC_CONTROL_THREAD_FLAG);
-        const bool is_CROSS_VALIDATION_ok =
-        	get_individual_flag(e_ECU_control_flagsHandle, CROSS_VALIDATION_FLAG); // COLOCA UM TIMER Q SETA ESSA FLAG
+        const bool is_there_CROSS_VALIDATION_error =
+        	get_individual_flag(e_ECU_control_flagsHandle, CROSS_VALIDATION_ERROR_FLAG); // COLOCA UM TIMER Q SETA ESSA FLAG
 
-        select_dynamic_control(is_DYNAMIC_CONTROL_active, is_CROSS_VALIDATION_ok);
+        select_dynamic_control(is_DYNAMIC_CONTROL_active, is_there_CROSS_VALIDATION_error);
 
         // todo (João Pedro): add new "case's" when the integration of controls is
         // implemented
@@ -118,9 +118,9 @@ void send_ref_torque_message(const uint32_t* ref_torque) {
     osMessageQueuePut(q_ref_torque_messageHandle, &ref_torque_message, 0, 0U);
 }
 
-void select_dynamic_control(bool is_DYNAMIC_CONTROL_active, bool is_CROSS_VALIDATION_ok) {
+void select_dynamic_control(bool is_DYNAMIC_CONTROL_active, bool is_there_CROSS_VALIDATION_error) {
     // todo (João Pedro): add new "if's" when the integration of controls is implemented
-    if (is_DYNAMIC_CONTROL_active && is_CROSS_VALIDATION_ok) {
+    if (is_DYNAMIC_CONTROL_active && !is_there_CROSS_VALIDATION_error) {
         if (get_global_var_value(SELECTED_MODE).dif_elt == 1
             && get_global_var_value(SELECTED_MODE).traction_control == 0) {
             g_control_type = LATERAL;
diff --git a/ECU.ioc b/ECU.ioc
index 881466c9..9c9289dc 100644
--- a/ECU.ioc
+++ b/ECU.ioc
@@ -97,7 +97,7 @@ FREERTOS.IPParameters=Tasks01,configMINIMAL_STACK_SIZE,FootprintOK,Queues01,conf
 FREERTOS.Mutexes01=m_state_parameter_mutex,Dynamic,NULL
 FREERTOS.Queues01=q_encoder_int_message,16,encoder_int_message_t,0,Dynamic,NULL,NULL;q_torque_message,16,torque_message_t,0,Dynamic,NULL,NULL;q_ref_torque_message,16,ref_torque_t,0,Dynamic,NULL,NULL;q_datalog_message,128,datalog_message_t,0,Dynamic,NULL,NULL;q_debug_leds_message,16,debug_led_message_t,0,Dynamic,NULL,NULL;q_rgb_led_message,16,rgb_led_message_t,0,Dynamic,NULL,NULL;q_throttle_control,16,uint16_t,0,Dynamic,NULL,NULL;q_encoder_speeds_message,1,encoder_speeds_message_t,0,Dynamic,NULL,NULL;q_odometer_calc_save_message,1,odometer_message_t,0,Dynamic,NULL,NULL;q_ids_can_inverter,32,uint32_t,0,Dynamic,NULL,NULL
 FREERTOS.Tasks01=t_main_task,24,1024,main_task,As weak,NULL,Dynamic,NULL,NULL;t_torque_parameters,8,1024,torque_parameters,As external,NULL,Dynamic,NULL,NULL;t_datalogger,8,1024,datalogger,As external,NULL,Dynamic,NULL,NULL;t_APPS_read,8,1024,APPS_read,As external,NULL,Dynamic,NULL,NULL;t_steering_read,8,1024,steering_read,As external,NULL,Dynamic,NULL,NULL;t_encoder_speed_calc,8,1024,encoder_speed_calc,As external,NULL,Dynamic,NULL,NULL;t_odometer_calc,8,1024,odometer_calc,As external,NULL,Dynamic,NULL,NULL;t_torque_message,8,1024,torque_message,As external,NULL,Dynamic,NULL,NULL;t_torque_manager,8,1024,torque_manager,As external,NULL,Dynamic,NULL,NULL;t_debug_leds,8,1024,debug_leds,As external,NULL,Dynamic,NULL,NULL;t_rgb_led,8,1024,rgb_led,As external,NULL,Dynamic,NULL,NULL;t_seleciona_modo,8,1024,seleciona_modo,As external,NULL,Dynamic,NULL,NULL;t_RTD,8,1024,RTD,As external,NULL,Dynamic,NULL,NULL;t_throttle_control,8,1024,throttle_control,As external,NULL,Dynamic,NULL,NULL;t_datalog_acquisition,8,1024,datalog_acquisition,As external,NULL,Dynamic,NULL,NULL;t_inverter_comm_error,8,1024,inverter_comm_error,As external,NULL,Dynamic,NULL,NULL;t_inverter_datalog,8,1024,inverter_datalog,As external,NULL,Dynamic,NULL,NULL;t_pilot_reset,8,1024,pilot_reset,As external,NULL,Dynamic,NULL,NULL;t_buttons_handler,8,1024,buttons_handler,As external,NULL,Dynamic,NULL,NULL;t_speed_datalog,8,1024,speed_datalog,As external,NULL,Dynamic,NULL,NULL;t_odometer_save,8,1024,odometer_save,As external,NULL,Dynamic,NULL,NULL;t_dynamic_controls_choice,8,1024,dynamic_controls_choice,As external,NULL,Dynamic,NULL,NULL;t_cross_validation,8,1024,cross_validation,As external,NULL,Dynamic,NULL,NULL
-FREERTOS.Timers01=tim_SU_F_error,errors_with_timer_callback,osTimerOnce,As external,SU_F_ERROR_FLAG,Dynamic,NULL;tim_APPS_error,errors_with_timer_callback,osTimerOnce,As external,APPS_ERROR_FLAG,Dynamic,NULL;tim_inverter_BUS_OFF_error,inverter_BUS_OFF_error_callback,osTimerOnce,As external,NULL,Dynamic,NULL;tim_inverter_ready,inverter_ready_callback,osTimerOnce,As external,NULL,Dynamic,NULL;tim_inverter_can_transmit_error,errors_with_timer_callback,osTimerOnce,As external,INVERTER_CAN_TRANSMIT_ERROR_FLAG,Dynamic,NULL;tim_left_inv_error,left_inv_error_callback,osTimerPeriodic,As external,LEFT_INVERTER_COMM_ERROR_FLAG,Dynamic,NULL;tim_right_inv_error,right_inv_error_callback,osTimerPeriodic,As external,RIGHT_INVERTER_COMM_ERROR_FLAG,Dynamic,NULL
+FREERTOS.Timers01=tim_SU_F_error,errors_with_timer_callback,osTimerOnce,As external,SU_F_ERROR_FLAG,Dynamic,NULL;tim_APPS_error,errors_with_timer_callback,osTimerOnce,As external,APPS_ERROR_FLAG,Dynamic,NULL;tim_inverter_BUS_OFF_error,inverter_BUS_OFF_error_callback,osTimerOnce,As external,NULL,Dynamic,NULL;tim_inverter_ready,inverter_ready_callback,osTimerOnce,As external,NULL,Dynamic,NULL;tim_inverter_can_transmit_error,errors_with_timer_callback,osTimerOnce,As external,INVERTER_CAN_TRANSMIT_ERROR_FLAG,Dynamic,NULL;tim_left_inv_error,left_inv_error_callback,osTimerPeriodic,As external,LEFT_INVERTER_COMM_ERROR_FLAG,Dynamic,NULL;tim_right_inv_error,right_inv_error_callback,osTimerPeriodic,As external,RIGHT_INVERTER_COMM_ERROR_FLAG,Dynamic,NULL;tim_cross_validation_error,cross_validation_error_callback,osTimerPeriodic,As external,CROSS_VALIDATION_ERROR_THREAD_FLAG,Dynamic,NULL
 FREERTOS.configCHECK_FOR_STACK_OVERFLOW=2
 FREERTOS.configENABLE_FPU=1
 FREERTOS.configMAX_TASK_NAME_LEN=32

From 4f91fe0600c6dfd343415eee5017b306d9f50057 Mon Sep 17 00:00:00 2001
From: caiussouza <caiuscsouza@gmail.com>
Date: Tue, 7 Mar 2023 15:45:48 -0300
Subject: [PATCH 09/33] debugging

---
 Core/Inc/dynamic_controls/security_architecture.h | 2 +-
 Core/Inc/sensors/sensor_data_processing.h         | 1 +
 Core/Src/sensors/sensor_data_processing.c         | 2 ++
 Core/Src/torque_command/torque_manager.c          | 4 ++--
 4 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/Core/Inc/dynamic_controls/security_architecture.h b/Core/Inc/dynamic_controls/security_architecture.h
index f011d0a9..f4ad8c10 100644
--- a/Core/Inc/dynamic_controls/security_architecture.h
+++ b/Core/Inc/dynamic_controls/security_architecture.h
@@ -1,7 +1,7 @@
 /*
  * security_architecture.h
  *
- *  Created on: 5 de mar de 2023
+ *  Created on: Mar 7, 2023
  *      Author: caius
  */
 
diff --git a/Core/Inc/sensors/sensor_data_processing.h b/Core/Inc/sensors/sensor_data_processing.h
index 25a4ef3e..f911c9e2 100644
--- a/Core/Inc/sensors/sensor_data_processing.h
+++ b/Core/Inc/sensors/sensor_data_processing.h
@@ -8,6 +8,7 @@
 #ifndef INC_SENSORS_SENSOR_DATA_PROCESSING_H_
 #define INC_SENSORS_SENSOR_DATA_PROCESSING_H_
 
+#include "stdint.h"
 #define BUFFER_SIZE 100
 
 void moving_average(uint16_t* mov_ave, uint16_t data);
diff --git a/Core/Src/sensors/sensor_data_processing.c b/Core/Src/sensors/sensor_data_processing.c
index a82c7de3..f467c762 100644
--- a/Core/Src/sensors/sensor_data_processing.c
+++ b/Core/Src/sensors/sensor_data_processing.c
@@ -7,6 +7,8 @@
 
 #include "sensors/sensor_data_processing.h"
 
+#include "stdint.h"
+
 
 
 // Calculate moving average for data logged from any sensor using a circular buffer
diff --git a/Core/Src/torque_command/torque_manager.c b/Core/Src/torque_command/torque_manager.c
index cff9d109..1a9f0086 100644
--- a/Core/Src/torque_command/torque_manager.c
+++ b/Core/Src/torque_command/torque_manager.c
@@ -31,12 +31,12 @@ void torque_manager(void* argument) {
 
         void rampa_torque(uint32_t * ref_torque, const double* ref_torque_decrease);
         void send_ref_torque_message(const uint32_t* ref_torque);
-        void select_dynamic_control(bool is_DYNAMIC_CONTROL_active);
+        void select_dynamic_control(bool is_DYNAMIC_CONTROL_active, bool is_there_CROSS_VALIDATION_error);
 
         const bool is_DYNAMIC_CONTROL_active =
             get_individual_flag(e_ECU_control_flagsHandle, DYNAMIC_CONTROL_THREAD_FLAG);
         const bool is_there_CROSS_VALIDATION_error =
-        	get_individual_flag(e_ECU_control_flagsHandle, CROSS_VALIDATION_ERROR_FLAG); // COLOCA UM TIMER Q SETA ESSA FLAG
+        	get_individual_flag(e_ECU_control_flagsHandle, CROSS_VALIDATION_ERROR_THREAD_FLAG); // COLOCA UM TIMER Q SETA ESSA FLAG
 
         select_dynamic_control(is_DYNAMIC_CONTROL_active, is_there_CROSS_VALIDATION_error);
 

From a2e083ac1a2e73db9c42393a939131b05bfd91d5 Mon Sep 17 00:00:00 2001
From: caiussouza <caiuscsouza@gmail.com>
Date: Wed, 8 Mar 2023 13:26:20 -0300
Subject: [PATCH 10/33] bug fixing

---
 .../dynamic_controls/security_architecture.h  |  3 +++
 .../driver_settings/dynamic_controls_choice.c |  1 +
 .../dynamic_controls/security_architecture.c  | 24 ++++++++++++-------
 3 files changed, 20 insertions(+), 8 deletions(-)

diff --git a/Core/Inc/dynamic_controls/security_architecture.h b/Core/Inc/dynamic_controls/security_architecture.h
index f4ad8c10..d2e95606 100644
--- a/Core/Inc/dynamic_controls/security_architecture.h
+++ b/Core/Inc/dynamic_controls/security_architecture.h
@@ -9,6 +9,9 @@
 #define INC_DYNAMIC_CONTROLS_SECURITY_ARCHITECTURE_H_
 
 // TODO(caius): add the threshold values and the timer time
+
+#include "stdint.h"
+
 #define IMU_LONG_ACCEL_THRESHOLD 1
 #define SPEED_MIN_THRESHOLD 1
 #define IMU_MAX_LONG_ACCEL_THRESHOLD 1
diff --git a/Core/Src/driver_settings/dynamic_controls_choice.c b/Core/Src/driver_settings/dynamic_controls_choice.c
index f91d9572..2485ba74 100644
--- a/Core/Src/driver_settings/dynamic_controls_choice.c
+++ b/Core/Src/driver_settings/dynamic_controls_choice.c
@@ -11,6 +11,7 @@
 #include "util/global_instances.h"
 #include "util/global_variables.h"
 #include "util/util.h"
+#include "cmsis_os2.h"
 
 void dynamic_controls_choice(void* argument) {
     UNUSED(argument);
diff --git a/Core/Src/dynamic_controls/security_architecture.c b/Core/Src/dynamic_controls/security_architecture.c
index 7baa996c..4a9e967b 100644
--- a/Core/Src/dynamic_controls/security_architecture.c
+++ b/Core/Src/dynamic_controls/security_architecture.c
@@ -6,18 +6,22 @@
  */
 
 
-#include "security_architecture.h"
+#include "dynamic_controls/security_architecture.h"
 
-#include "global_variables_handler.h"
-#include "sensor_data_processing.h"
+#include "sensors/sensor_data_processing.h"
 #include "util/CMSIS_extra/global_variables_handler.h"
 #include "util/global_variables.h"
 #include "util/global_definitions.h"
+#include "CAN/general_can_data_manager.h"
+#include "cmsis_os2.h"
+#include "cmsis_os.h"
+#include "stm32h7xx.h"
+#include "stdbool.h"
 
 // Center of gravity speed used in dynamic controls functions
-static uint16_t raw_speed_data = (uint16_t)get_global_var_value(REAR_AVG_SPEED);
+//static uint16_t raw_speed_data = get_global_var_value(REAR_AVG_SPEED);
 
-static uint16_t raw_IMU_long_accel_data = (int16_t)general_get_value(accelerometer_y);
+//static int16_t raw_IMU_long_accel_data = (int16_t)general_get_value(accelerometer_y);
 
 static uint16_t speed_filtered;
 static int16_t IMU_long_accel_filtered;
@@ -29,7 +33,11 @@ void cross_validation(void* argument) {
     for (;;) {
         ECU_ENABLE_BREAKPOINT_DEBUG();
 
-        osThreadFlagsWait();
+        //osThreadFlagsWait();
+
+        int16_t raw_IMU_long_accel_data = (int16_t)general_get_value(accelerometer_y);
+        uint16_t raw_speed_data = get_global_var_value(REAR_AVG_SPEED);
+
 
         // TODO(caius): fazer uma média mais genérica usando struct e um serviço pro buffer circular
         moving_average(&IMU_long_accel_filtered, raw_IMU_long_accel_data);
@@ -53,13 +61,13 @@ uint8_t is_imu_bse_ok(){
 }
 
 uint8_t is_imu_speed_ok(){
-	if((speed < SPEED_MIN_THRESHOLD) && (IMU_long_accel_filtered > IMU_MAX_LONG_ACCEL_THRESHOLD))
+	if((speed_filtered < SPEED_MIN_THRESHOLD) && (IMU_long_accel_filtered > IMU_MAX_LONG_ACCEL_THRESHOLD))
 		return 0;
 	return 1;
 }
 
 void cross_validation_error_callback(){
-	osEventFlagsSet(e_ECU_control_flagsHandle, CROSS_VALIDATION_ERROR_FLAG);
+	osEventFlagsSet(e_ECU_control_flagsHandle, CROSS_VALIDATION_ERROR_THREAD_FLAG);
 }
 
 

From e911744db3b198e38b3305d76a441c8b299b1586 Mon Sep 17 00:00:00 2001
From: caiussouza <caiuscsouza@gmail.com>
Date: Wed, 8 Mar 2023 22:07:11 -0300
Subject: [PATCH 11/33] bug fixing

---
 .../dynamic_controls/security_architecture.h  |  2 +-
 Core/Inc/util/global_definitions.h            |  2 +-
 Core/Inc/util/global_instances.h              |  3 ++-
 .../dynamic_controls/security_architecture.c  | 25 ++++++-------------
 4 files changed, 12 insertions(+), 20 deletions(-)

diff --git a/Core/Inc/dynamic_controls/security_architecture.h b/Core/Inc/dynamic_controls/security_architecture.h
index d2e95606..1ccd0b33 100644
--- a/Core/Inc/dynamic_controls/security_architecture.h
+++ b/Core/Inc/dynamic_controls/security_architecture.h
@@ -14,7 +14,7 @@
 
 #define IMU_LONG_ACCEL_THRESHOLD 1
 #define SPEED_MIN_THRESHOLD 1
-#define IMU_MAX_LONG_ACCEL_THRESHOLD 1
+#define IMU_MAX_LONGIT_ACCEL_THRESHOLD 1
 
 #define CROSS_VALIDATION_ERROR_TIME 1
 
diff --git a/Core/Inc/util/global_definitions.h b/Core/Inc/util/global_definitions.h
index b8946c31..22a0a796 100644
--- a/Core/Inc/util/global_definitions.h
+++ b/Core/Inc/util/global_definitions.h
@@ -111,7 +111,7 @@ typedef enum {
 #define INVERTER_READY_THREAD_FLAG                      (1 << 6)
 #define ODOMETER_SAVE_THREAD_FLAG                       (1 << 7)
 #define DYNAMIC_CONTROL_THREAD_FLAG                     (1 << 8)
-#define CROSS_VALIDATION_ERROR_THREAD_FLAG	  (1 << 9)
+#define CROSS_VALIDATION_ERROR_THREAD_FLAG	  			(1 << 9)
 
 // Warning flags	(No actions necessary)
 #define REGEN_WARN_FLAG           (1 << 10)
diff --git a/Core/Inc/util/global_instances.h b/Core/Inc/util/global_instances.h
index 113de1c7..1d1c35af 100644
--- a/Core/Inc/util/global_instances.h
+++ b/Core/Inc/util/global_instances.h
@@ -33,6 +33,7 @@ extern osThreadId_t t_pilot_resetHandle;
 extern osThreadId_t t_inverter_comm_errorHandle;
 extern osThreadId_t t_odometer_saveHandle;
 extern osThreadId_t t_dynamic_controls_choiceHandle;
+extern osThreadId_t t_cross_validationHandle;
 
 // EVENT FLAGS
 extern osEventFlagsId_t e_ECU_control_flagsHandle;
@@ -45,11 +46,11 @@ extern osMutexId_t m_state_parameter_mutexHandle;
 // TIMERS
 extern osTimerId_t tim_SU_F_errorHandle;
 extern osTimerId_t tim_APPS_errorHandle;
-;
 extern osTimerId_t tim_inverter_BUS_OFF_errorHandle;
 extern osTimerId_t tim_inverter_readyHandle;
 extern osTimerId_t tim_inverter_can_transmit_errorHandle;
 extern osTimerId_t tim_left_inv_errorHandle;
 extern osTimerId_t tim_right_inv_errorHandle;
+extern osTimerId_t tim_cross_validation_errorHandle;
 
 #endif /* INC_GLOBAL_INSTANCES_H_ */
diff --git a/Core/Src/dynamic_controls/security_architecture.c b/Core/Src/dynamic_controls/security_architecture.c
index 4a9e967b..8c2fb60c 100644
--- a/Core/Src/dynamic_controls/security_architecture.c
+++ b/Core/Src/dynamic_controls/security_architecture.c
@@ -9,22 +9,14 @@
 #include "dynamic_controls/security_architecture.h"
 
 #include "sensors/sensor_data_processing.h"
-#include "util/CMSIS_extra/global_variables_handler.h"
-#include "util/global_variables.h"
-#include "util/global_definitions.h"
 #include "CAN/general_can_data_manager.h"
 #include "cmsis_os2.h"
-#include "cmsis_os.h"
-#include "stm32h7xx.h"
-#include "stdbool.h"
+#include "util/util.h"
+#include "util/global_instances.h"
 
-// Center of gravity speed used in dynamic controls functions
-//static uint16_t raw_speed_data = get_global_var_value(REAR_AVG_SPEED);
-
-//static int16_t raw_IMU_long_accel_data = (int16_t)general_get_value(accelerometer_y);
 
 static uint16_t speed_filtered;
-static int16_t IMU_long_accel_filtered;
+static int16_t IMU_longit_accel_filtered;
 static bool bse_active = get_global_var_value(BRAKE_STATUS);
 
 void cross_validation(void* argument) {
@@ -33,14 +25,13 @@ void cross_validation(void* argument) {
     for (;;) {
         ECU_ENABLE_BREAKPOINT_DEBUG();
 
-        //osThreadFlagsWait();
+        osThreadFlagsWait(DYNAMIC_CONTROLS_CHOICE_BTN_PRESSED_THREAD_FLAG, osFlagsWaitAny, osWaitForever);
 
-        int16_t raw_IMU_long_accel_data = (int16_t)general_get_value(accelerometer_y);
+        int16_t raw_IMU_longit_accel_data = (int16_t)general_get_value(accelerometer_y);
         uint16_t raw_speed_data = get_global_var_value(REAR_AVG_SPEED);
 
-
         // TODO(caius): fazer uma média mais genérica usando struct e um serviço pro buffer circular
-        moving_average(&IMU_long_accel_filtered, raw_IMU_long_accel_data);
+        moving_average(&IMU_longit_accel_filtered, raw_IMU_longit_accel_data);
         moving_average(&speed_filtered, raw_speed_data);
 
         if(!is_imu_bse_ok() || !is_imu_speed_ok()){
@@ -55,13 +46,13 @@ void cross_validation(void* argument) {
 
 
 uint8_t is_imu_bse_ok(){
-	if(bse_active && (IMU_long_accel_filtered > IMU_MAX_LONG_ACCEL_THRESHOLD))
+	if(bse_active && (IMU_longit_accel_filtered > IMU_MAX_LONGIT_ACCEL_THRESHOLD))
 		return 0;
 	return 1;
 }
 
 uint8_t is_imu_speed_ok(){
-	if((speed_filtered < SPEED_MIN_THRESHOLD) && (IMU_long_accel_filtered > IMU_MAX_LONG_ACCEL_THRESHOLD))
+	if((speed_filtered < SPEED_MIN_THRESHOLD) && (IMU_longit_accel_filtered > IMU_MAX_LONGIT_ACCEL_THRESHOLD))
 		return 0;
 	return 1;
 }

From 4288f839ab4a273c1e976a0fa7ff8dc60a5831a9 Mon Sep 17 00:00:00 2001
From: caiussouza <caiuscsouza@gmail.com>
Date: Wed, 8 Mar 2023 22:29:20 -0300
Subject: [PATCH 12/33] building errors fixed

---
 Core/Src/dynamic_controls/security_architecture.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Core/Src/dynamic_controls/security_architecture.c b/Core/Src/dynamic_controls/security_architecture.c
index 8c2fb60c..90f593ac 100644
--- a/Core/Src/dynamic_controls/security_architecture.c
+++ b/Core/Src/dynamic_controls/security_architecture.c
@@ -17,7 +17,7 @@
 
 static uint16_t speed_filtered;
 static int16_t IMU_longit_accel_filtered;
-static bool bse_active = get_global_var_value(BRAKE_STATUS);
+static bool bse_active;
 
 void cross_validation(void* argument) {
     UNUSED(argument);
@@ -29,6 +29,7 @@ void cross_validation(void* argument) {
 
         int16_t raw_IMU_longit_accel_data = (int16_t)general_get_value(accelerometer_y);
         uint16_t raw_speed_data = get_global_var_value(REAR_AVG_SPEED);
+        bool bse_active = get_global_var_value(BRAKE_STATUS);
 
         // TODO(caius): fazer uma média mais genérica usando struct e um serviço pro buffer circular
         moving_average(&IMU_longit_accel_filtered, raw_IMU_longit_accel_data);

From 233fbe410ccbc6086c52681e24ab4040e7a07bb6 Mon Sep 17 00:00:00 2001
From: caiussouza <caiuscsouza@gmail.com>
Date: Thu, 9 Mar 2023 01:12:20 -0300
Subject: [PATCH 13/33] ready for tests

---
 .../dynamic_controls/security_architecture.h  | 10 ++--
 Core/Inc/sensors/sensor_data_processing.h     |  3 +-
 .../CMSIS_extra/global_variables_handler.h    |  2 +
 .../dynamic_controls/security_architecture.c  | 41 ++++++-------
 Core/Src/sensors/sensor_data_processing.c     | 59 +++----------------
 5 files changed, 36 insertions(+), 79 deletions(-)

diff --git a/Core/Inc/dynamic_controls/security_architecture.h b/Core/Inc/dynamic_controls/security_architecture.h
index 1ccd0b33..b49bbc57 100644
--- a/Core/Inc/dynamic_controls/security_architecture.h
+++ b/Core/Inc/dynamic_controls/security_architecture.h
@@ -12,13 +12,13 @@
 
 #include "stdint.h"
 
-#define IMU_LONG_ACCEL_THRESHOLD 1
-#define SPEED_MIN_THRESHOLD 1
-#define IMU_MAX_LONGIT_ACCEL_THRESHOLD 1
+#define IMU_NULL_ACCEL_MARGIN_ERROR 1
+#define NULL_SPEED_MARGIN_ERROR 1
 
 #define CROSS_VALIDATION_ERROR_TIME 1
 
-uint8_t is_imu_bse_ok();
-uint8_t is_imu_speed_ok();
+uint8_t is_there_imu_bse_error();
+uint8_t is_there_imu_speed_error();
+void cross_validation_error_callback();
 
 #endif /* INC_DYNAMIC_CONTROLS_SECURITY_ARCHITECTURE_H_ */
diff --git a/Core/Inc/sensors/sensor_data_processing.h b/Core/Inc/sensors/sensor_data_processing.h
index f911c9e2..147e6089 100644
--- a/Core/Inc/sensors/sensor_data_processing.h
+++ b/Core/Inc/sensors/sensor_data_processing.h
@@ -9,8 +9,9 @@
 #define INC_SENSORS_SENSOR_DATA_PROCESSING_H_
 
 #include "stdint.h"
+
 #define BUFFER_SIZE 100
 
-void moving_average(uint16_t* mov_ave, uint16_t data);
+void moving_average(float* mov_avg, float data);
 
 #endif /* INC_SENSORS_SENSOR_DATA_PROCESSING_H_ */
diff --git a/Core/Inc/util/CMSIS_extra/global_variables_handler.h b/Core/Inc/util/CMSIS_extra/global_variables_handler.h
index 7ca190f1..8433253a 100644
--- a/Core/Inc/util/CMSIS_extra/global_variables_handler.h
+++ b/Core/Inc/util/CMSIS_extra/global_variables_handler.h
@@ -19,6 +19,7 @@ typedef uint16_t FRONT_AVG_SPEED_t;
 typedef uint16_t REAR_AVG_SPEED_t;
 typedef uint16_t STEERING_WHEEL_t;
 typedef uint16_t GYRO_YAW_t;
+typedef int16_t IMU_ACCEL_t;
 typedef uint8_t INTERNAL_WHEEL_t;
 typedef race_mode_t RACE_MODE_t;
 typedef uint16_t THROTTLE_PERCENT_t;
@@ -32,6 +33,7 @@ typedef modos SELECTED_MODE_t;
 #define REAR_AVG_SPEED_DEFAULT_VALUE   0
 #define STEERING_WHEEL_DEFAULT_VALUE   0
 #define GYRO_YAW_DEFAULT_VALUE         0
+#define IMU_ACCEL_DEFAULT_VALUE		   0
 #define INTERNAL_WHEEL_DEFAULT_VALUE   0
 #define RACE_MODE_DEFAULT_VALUE        ENDURO
 #define THROTTLE_PERCENT_DEFAULT_VALUE 0
diff --git a/Core/Src/dynamic_controls/security_architecture.c b/Core/Src/dynamic_controls/security_architecture.c
index 90f593ac..a2f38014 100644
--- a/Core/Src/dynamic_controls/security_architecture.c
+++ b/Core/Src/dynamic_controls/security_architecture.c
@@ -5,19 +5,17 @@
  *      Author: caius
  */
 
-
 #include "dynamic_controls/security_architecture.h"
 
-#include "sensors/sensor_data_processing.h"
 #include "CAN/general_can_data_manager.h"
 #include "cmsis_os2.h"
+#include "sensors/sensor_data_processing.h"
 #include "util/util.h"
 #include "util/global_instances.h"
 
-
-static uint16_t speed_filtered;
-static int16_t IMU_longit_accel_filtered;
-static bool bse_active;
+static REAR_AVG_SPEED_t speed_mov_avg;
+static IMU_ACCEL_t IMU_long_accel_mov_avg;
+static BRAKE_STATUS_t bse_active;
 
 void cross_validation(void* argument) {
     UNUSED(argument);
@@ -27,15 +25,14 @@ void cross_validation(void* argument) {
 
         osThreadFlagsWait(DYNAMIC_CONTROLS_CHOICE_BTN_PRESSED_THREAD_FLAG, osFlagsWaitAny, osWaitForever);
 
-        int16_t raw_IMU_longit_accel_data = (int16_t)general_get_value(accelerometer_y);
-        uint16_t raw_speed_data = get_global_var_value(REAR_AVG_SPEED);
-        bool bse_active = get_global_var_value(BRAKE_STATUS);
+        IMU_ACCEL_t IMU_long_accel_data = (int16_t)general_get_value(accelerometer_z);
+        REAR_AVG_SPEED_t speed_data = get_global_var_value(REAR_AVG_SPEED);
+        bse_active = get_global_var_value(BRAKE_STATUS);
 
-        // TODO(caius): fazer uma média mais genérica usando struct e um serviço pro buffer circular
-        moving_average(&IMU_longit_accel_filtered, raw_IMU_longit_accel_data);
-        moving_average(&speed_filtered, raw_speed_data);
+        moving_average(&IMU_long_accel_mov_avg, IMU_long_accel_data);
+        moving_average(&speed_mov_avg, speed_data);
 
-        if(!is_imu_bse_ok() || !is_imu_speed_ok()){
+        if(is_there_imu_bse_error() || is_there_imu_speed_error()){
         	osTimerStart(tim_cross_validation_errorHandle, CROSS_VALIDATION_ERROR_TIME);
         }
         else{
@@ -46,20 +43,18 @@ void cross_validation(void* argument) {
 }
 
 
-uint8_t is_imu_bse_ok(){
-	if(bse_active && (IMU_longit_accel_filtered > IMU_MAX_LONGIT_ACCEL_THRESHOLD))
-		return 0;
-	return 1;
+uint8_t is_there_imu_bse_error(){
+	if(bse_active && (IMU_long_accel_mov_avg > IMU_NULL_ACCEL_MARGIN_ERROR))
+		return 1;
+	return 0;
 }
 
-uint8_t is_imu_speed_ok(){
-	if((speed_filtered < SPEED_MIN_THRESHOLD) && (IMU_longit_accel_filtered > IMU_MAX_LONGIT_ACCEL_THRESHOLD))
-		return 0;
-	return 1;
+uint8_t is_there_imu_speed_error(){
+	if((speed_mov_avg < NULL_SPEED_MARGIN_ERROR) && (IMU_long_accel_mov_avg > IMU_NULL_ACCEL_MARGIN_ERROR))
+		return 1;
+	return 0;
 }
 
 void cross_validation_error_callback(){
 	osEventFlagsSet(e_ECU_control_flagsHandle, CROSS_VALIDATION_ERROR_THREAD_FLAG);
 }
-
-
diff --git a/Core/Src/sensors/sensor_data_processing.c b/Core/Src/sensors/sensor_data_processing.c
index f467c762..a3927c5a 100644
--- a/Core/Src/sensors/sensor_data_processing.c
+++ b/Core/Src/sensors/sensor_data_processing.c
@@ -7,33 +7,30 @@
 
 #include "sensors/sensor_data_processing.h"
 
-#include "stdint.h"
 
+// TODO(caius): Generalize moving average service implementing this sketch, allowing different types. Implement a general circular buffer as well
+// It calculates moving average for data logged from any sensor using a circular buffer
 
-
-// Calculate moving average for data logged from any sensor using a circular buffer
-
-void moving_average(uint16_t* mov_ave, uint16_t data) {
+void moving_average(float* mov_avg, float data) {
 
 	uint8_t buffer_index = 0;
-	uint16_t movave_buffer[BUFFER_SIZE];
-	uint32_t buffer_sum = 0;
+	float mov_avg_buffer[BUFFER_SIZE];
+	float buffer_sum = 0;
 
-	mov_ave = 0;
+	mov_avg = 0;
 
 	// Put the signal value read by sensor into each buffer position
-	movave_buffer[buffer_index] = data;
+	mov_avg_buffer[buffer_index] = data;
 
 	// circular buffer logic
 	buffer_index = (buffer_index + 1) % BUFFER_SIZE;
 
-
 	// Calculate the moving average based on a mutable value
 	// It requires empirical tests for choosing that value
 	for(uint8_t i = 0; i < BUFFER_SIZE; i++){
-		buffer_sum += movave_buffer[i];
+		buffer_sum += mov_avg_buffer[i];
 	}
-	mov_ave = buffer_sum / BUFFER_SIZE;
+	*mov_avg = buffer_sum / (float)BUFFER_SIZE;
 
 	// Avoid variable type overflow
 	buffer_sum = 0;
@@ -41,41 +38,3 @@ void moving_average(uint16_t* mov_ave, uint16_t data) {
 		buffer_index = 0;
 
 }
-
-//vc define cada mov_ave pra cada tipo de dado. exemplo pro apps1
-//
-//moving_average_t apps1_mov_ave{
-//	uint16_t buffer_size = BUFFER_SIZE_APPS1;
-//	uint16_t data = uint_t taltaltal do adc talz;
-//};
-//
-// fazer o serviço do buffer circular
-// problemas: e se eu quiser um buffer maior ou um dado do tipo uint32_t?
-// como escolher o dado a partir disso? pré-processamento?
-//
-//void moving_average(moving_average_t* mov_ave){
-//	uint8_t buffer_index = 0;
-//	uint16_t movave_buffer[mov_ave->buffer_size];
-//	uint32_t buffer_sum = 0;
-//
-//	mov_ave = 0;
-//
-//	// Put the signal value read by sensor into each buffer position
-//	movave_buffer[buffer_index] = mov_ave->data;
-//
-//	// circular buffer logic
-//	buffer_index = (buffer_index + 1) % (mov_ave->buffer_size);
-//
-//
-//	// Calculate the moving average based on a mutable value
-//	// It requires empirical tests for choosing that value
-//	for(uint8_t i = 0; i < (mov_ave->buffer_size); i++){
-//		buffer_sum += movave_buffer[i];
-//	}
-//	mov_ave = buffer_sum / (mov_ave->buffer_size);
-//
-//	// Avoid variable type overflow
-//	buffer_sum = 0;
-//	if(buffer_index == 256)
-//		buffer_index = 0;
-//}

From ca7452c9f96a1df05d9aefffe188d950b6a30ba0 Mon Sep 17 00:00:00 2001
From: caiussouza <caiuscsouza@gmail.com>
Date: Tue, 14 Mar 2023 14:21:20 -0300
Subject: [PATCH 14/33] moving average fixing

---
 Core/Inc/sensors/sensor_data_processing.h         |  2 +-
 Core/Src/dynamic_controls/security_architecture.c |  8 ++++----
 Core/Src/sensors/sensor_data_processing.c         | 12 ++++++------
 3 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/Core/Inc/sensors/sensor_data_processing.h b/Core/Inc/sensors/sensor_data_processing.h
index 147e6089..13eabfed 100644
--- a/Core/Inc/sensors/sensor_data_processing.h
+++ b/Core/Inc/sensors/sensor_data_processing.h
@@ -12,6 +12,6 @@
 
 #define BUFFER_SIZE 100
 
-void moving_average(float* mov_avg, float data);
+void moving_average(float* mov_avg, float* data);
 
 #endif /* INC_SENSORS_SENSOR_DATA_PROCESSING_H_ */
diff --git a/Core/Src/dynamic_controls/security_architecture.c b/Core/Src/dynamic_controls/security_architecture.c
index a2f38014..d7654d7c 100644
--- a/Core/Src/dynamic_controls/security_architecture.c
+++ b/Core/Src/dynamic_controls/security_architecture.c
@@ -29,8 +29,8 @@ void cross_validation(void* argument) {
         REAR_AVG_SPEED_t speed_data = get_global_var_value(REAR_AVG_SPEED);
         bse_active = get_global_var_value(BRAKE_STATUS);
 
-        moving_average(&IMU_long_accel_mov_avg, IMU_long_accel_data);
-        moving_average(&speed_mov_avg, speed_data);
+        moving_average(&IMU_long_accel_mov_avg, &IMU_long_accel_data);
+        moving_average(&speed_mov_avg, &speed_data);
 
         if(is_there_imu_bse_error() || is_there_imu_speed_error()){
         	osTimerStart(tim_cross_validation_errorHandle, CROSS_VALIDATION_ERROR_TIME);
@@ -46,13 +46,13 @@ void cross_validation(void* argument) {
 uint8_t is_there_imu_bse_error(){
 	if(bse_active && (IMU_long_accel_mov_avg > IMU_NULL_ACCEL_MARGIN_ERROR))
 		return 1;
-	return 0;
+	else return 0;
 }
 
 uint8_t is_there_imu_speed_error(){
 	if((speed_mov_avg < NULL_SPEED_MARGIN_ERROR) && (IMU_long_accel_mov_avg > IMU_NULL_ACCEL_MARGIN_ERROR))
 		return 1;
-	return 0;
+	else return 0;
 }
 
 void cross_validation_error_callback(){
diff --git a/Core/Src/sensors/sensor_data_processing.c b/Core/Src/sensors/sensor_data_processing.c
index a3927c5a..e3fee532 100644
--- a/Core/Src/sensors/sensor_data_processing.c
+++ b/Core/Src/sensors/sensor_data_processing.c
@@ -11,16 +11,16 @@
 // TODO(caius): Generalize moving average service implementing this sketch, allowing different types. Implement a general circular buffer as well
 // It calculates moving average for data logged from any sensor using a circular buffer
 
-void moving_average(float* mov_avg, float data) {
+static uint8_t buffer_index = 0;
+static float buffer_sum = 0;
+static float mov_avg_buffer[BUFFER_SIZE] = {0.0};
 
-	uint8_t buffer_index = 0;
-	float mov_avg_buffer[BUFFER_SIZE];
-	float buffer_sum = 0;
+void moving_average(float* mov_avg, float* data) {
 
-	mov_avg = 0;
+	*mov_avg = 0;
 
 	// Put the signal value read by sensor into each buffer position
-	mov_avg_buffer[buffer_index] = data;
+	mov_avg_buffer[buffer_index] = *data;
 
 	// circular buffer logic
 	buffer_index = (buffer_index + 1) % BUFFER_SIZE;

From c37825191a60a335ee0fa7aee2f3e4d205e12cc8 Mon Sep 17 00:00:00 2001
From: caiussouza <caiuscsouza@gmail.com>
Date: Tue, 14 Mar 2023 14:54:41 -0300
Subject: [PATCH 15/33] pr ready version

---
 .../dynamic_controls/security_architecture.h  |  5 +++--
 Core/Inc/util/global_definitions.h            | 22 ++++++++++---------
 .../dynamic_controls/security_architecture.c  | 20 ++++++++++++-----
 3 files changed, 29 insertions(+), 18 deletions(-)

diff --git a/Core/Inc/dynamic_controls/security_architecture.h b/Core/Inc/dynamic_controls/security_architecture.h
index b49bbc57..544d786a 100644
--- a/Core/Inc/dynamic_controls/security_architecture.h
+++ b/Core/Inc/dynamic_controls/security_architecture.h
@@ -11,14 +11,15 @@
 // TODO(caius): add the threshold values and the timer time
 
 #include "stdint.h"
+#include "stdbool.h"
 
 #define IMU_NULL_ACCEL_MARGIN_ERROR 1
 #define NULL_SPEED_MARGIN_ERROR 1
 
 #define CROSS_VALIDATION_ERROR_TIME 1
 
-uint8_t is_there_imu_bse_error();
-uint8_t is_there_imu_speed_error();
+bool is_there_imu_bse_error();
+bool is_there_imu_speed_error();
 void cross_validation_error_callback();
 
 #endif /* INC_DYNAMIC_CONTROLS_SECURITY_ARCHITECTURE_H_ */
diff --git a/Core/Inc/util/global_definitions.h b/Core/Inc/util/global_definitions.h
index 22a0a796..b4e55c5d 100644
--- a/Core/Inc/util/global_definitions.h
+++ b/Core/Inc/util/global_definitions.h
@@ -112,22 +112,24 @@ typedef enum {
 #define ODOMETER_SAVE_THREAD_FLAG                       (1 << 7)
 #define DYNAMIC_CONTROL_THREAD_FLAG                     (1 << 8)
 #define CROSS_VALIDATION_ERROR_THREAD_FLAG	  			(1 << 9)
+#define IMU_BSE_ERROR_THREAD_FLAG						(1 << 10)
+#define IMU_SPEED_ERROR_THREAD_FLAG						(1 << 11)
 
 // Warning flags	(No actions necessary)
-#define REGEN_WARN_FLAG           (1 << 10)
-#define DYNAMIC_CONTROL_WARN_FLAG (1 << 11)
-#define FLASH_SAVE_LIMIT_FLAG     (1 << 12)
+#define REGEN_WARN_FLAG           (1 << 12)
+#define DYNAMIC_CONTROL_WARN_FLAG (1 << 13)
+#define FLASH_SAVE_LIMIT_FLAG     (1 << 14)
 // Soft error flags (RTD keeps on, torque ref to inverter is set to 0)
 
-#define BSE_ERROR_FLAG  (1 << 16) // Regulamento: EV.5.7 (2021)
-#define APPS_ERROR_FLAG (1 << 17) // Regulamento: T.4.2 (2021)
+#define BSE_ERROR_FLAG  (1 << 18) // Regulamento: EV.5.7 (2021)
+#define APPS_ERROR_FLAG (1 << 19) // Regulamento: T.4.2 (2021)
 
 // Hard error flags (RTD disable)
-#define INVERTER_CAN_TRANSMIT_ERROR_FLAG (1 << 19)
-#define SU_F_ERROR_FLAG                  (1 << 20)
-#define INVERTER_BUS_OFF_ERROR_FLAG      (1 << 21)
-#define LEFT_INVERTER_COMM_ERROR_FLAG    (1 << 22)
-#define RIGHT_INVERTER_COMM_ERROR_FLAG   (1 << 23)
+#define INVERTER_CAN_TRANSMIT_ERROR_FLAG (1 << 21)
+#define SU_F_ERROR_FLAG                  (1 << 22)
+#define INVERTER_BUS_OFF_ERROR_FLAG      (1 << 23)
+#define LEFT_INVERTER_COMM_ERROR_FLAG    (1 << 24)
+#define RIGHT_INVERTER_COMM_ERROR_FLAG   (1 << 25)
 
 #define ALL_WARN_FLAG        (REGEN_WARN_FLAG | DYNAMIC_CONTROL_WARN_FLAG)
 #define ALL_MINOR_ERROR_FLAG (APPS_ERROR_FLAG | BSE_ERROR_FLAG)
diff --git a/Core/Src/dynamic_controls/security_architecture.c b/Core/Src/dynamic_controls/security_architecture.c
index d7654d7c..fc0468c9 100644
--- a/Core/Src/dynamic_controls/security_architecture.c
+++ b/Core/Src/dynamic_controls/security_architecture.c
@@ -34,7 +34,15 @@ void cross_validation(void* argument) {
 
         if(is_there_imu_bse_error() || is_there_imu_speed_error()){
         	osTimerStart(tim_cross_validation_errorHandle, CROSS_VALIDATION_ERROR_TIME);
+
+        	if(is_there_imu_bse_error()){
+        		osEventFlagsSet(e_ECU_control_flagsHandle, IMU_BSE_ERROR_THREAD_FLAG);
+        	}
+        	if(is_there_imu_speed_error()){
+        		osEventFlagsSet(e_ECU_control_flagsHandle, IMU_SPEED_ERROR_THREAD_FLAG);
+        	}
         }
+
         else{
         	osTimerStop(tim_cross_validation_errorHandle);
         	osEventFlagsClear(e_ECU_control_flagsHandle, CROSS_VALIDATION_ERROR_THREAD_FLAG);
@@ -43,16 +51,16 @@ void cross_validation(void* argument) {
 }
 
 
-uint8_t is_there_imu_bse_error(){
+bool is_there_imu_bse_error(){
 	if(bse_active && (IMU_long_accel_mov_avg > IMU_NULL_ACCEL_MARGIN_ERROR))
-		return 1;
-	else return 0;
+		return true;
+	else return false;
 }
 
-uint8_t is_there_imu_speed_error(){
+bool is_there_imu_speed_error(){
 	if((speed_mov_avg < NULL_SPEED_MARGIN_ERROR) && (IMU_long_accel_mov_avg > IMU_NULL_ACCEL_MARGIN_ERROR))
-		return 1;
-	else return 0;
+		return true;
+	else return false;
 }
 
 void cross_validation_error_callback(){

From 67af9972c7147f3e8e9d04f8155e4a0c0107f8a4 Mon Sep 17 00:00:00 2001
From: caiussouza <caiuscsouza@gmail.com>
Date: Fri, 17 Mar 2023 10:30:25 -0300
Subject: [PATCH 16/33] refactoring

---
 .cproject                                            | 6 ++++--
 Core/Inc/util/CMSIS_extra/global_variables_handler.h | 1 +
 Core/Inc/util/global_definitions.h                   | 2 +-
 Core/Src/dynamic_controls/security_architecture.c    | 7 +++----
 Core/Src/main.c                                      | 2 +-
 Core/Src/torque_command/torque_manager.c             | 2 +-
 Core/Src/util/CMSIS_extra/global_variables_handler.c | 1 +
 ECU.ioc                                              | 4 +++-
 8 files changed, 15 insertions(+), 10 deletions(-)

diff --git a/.cproject b/.cproject
index 365e8750..d71f3f22 100644
--- a/.cproject
+++ b/.cproject
@@ -25,7 +25,8 @@
 							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.fpu.1971965462" name="Floating-point unit" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.fpu" useByScannerDiscovery="true" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.fpu.value.fpv5-d16" valueType="enumerated"/>
 							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi.434450183" name="Floating-point ABI" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi" useByScannerDiscovery="true" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi.value.hard" valueType="enumerated"/>
 							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board.1189751738" name="Board" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board" useByScannerDiscovery="false" value="genericBoard" valueType="string"/>
-							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults.314650556" name="Defaults" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults" useByScannerDiscovery="false" value="com.st.stm32cube.ide.common.services.build.inputs.revA.1.0.5 || Debug || true || Executable || com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.base.gnu-tools-for-stm32 || STM32H743VITx || 0 || 0 || arm-none-eabi- || ${gnu_tools_for_stm32_compiler_path} || ../Middlewares/Third_Party/FreeRTOS/Source/include | ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F | ../Drivers/CMSIS/Include | ../Core/Inc | ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy | ../Drivers/CMSIS/Device/ST/STM32H7xx/Include | ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 | ../Drivers/STM32H7xx_HAL_Driver/Inc ||  ||  || USE_HAL_DRIVER | STM32H743xx ||  || Drivers | Core/Startup | Middlewares | Core ||  ||  || ${workspace_loc:/${ProjName}/STM32H743VITX_FLASH.ld} || true || NonSecure ||  || secure_nsclib.o ||  || None || " valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults.314650556" name="Defaults" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults" useByScannerDiscovery="false" value="com.st.stm32cube.ide.common.services.build.inputs.revA.1.0.6 || Debug || true || Executable || com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.base.gnu-tools-for-stm32 || STM32H743VITx || 0 || 0 || arm-none-eabi- || ${gnu_tools_for_stm32_compiler_path} || ../Middlewares/Third_Party/FreeRTOS/Source/include | ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F | ../Drivers/CMSIS/Include | ../Core/Inc | ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy | ../Drivers/CMSIS/Device/ST/STM32H7xx/Include | ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 | ../Drivers/STM32H7xx_HAL_Driver/Inc ||  ||  || USE_HAL_DRIVER | STM32H743xx ||  || Drivers | Core/Startup | Middlewares | Core ||  ||  || ${workspace_loc:/${ProjName}/STM32H743VITX_FLASH.ld} || true || NonSecure ||  || secure_nsclib.o ||  || None ||  ||  || " valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.debug.option.cpuclock.808710097" superClass="com.st.stm32cube.ide.mcu.debug.option.cpuclock" value="100" valueType="string"/>
 							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform.490691857" isAbstract="false" osList="all" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform"/>
 							<builder buildPath="${workspace_loc:/ECU}/Debug" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder.1096357141" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder"/>
 							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.796568143" name="MCU GCC Assembler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler">
@@ -112,7 +113,8 @@
 							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.fpu.250658686" name="Floating-point unit" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.fpu" useByScannerDiscovery="true" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.fpu.value.fpv5-d16" valueType="enumerated"/>
 							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi.1204726074" name="Floating-point ABI" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi" useByScannerDiscovery="true" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi.value.hard" valueType="enumerated"/>
 							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board.607280753" name="Board" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board" useByScannerDiscovery="false" value="genericBoard" valueType="string"/>
-							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults.1018201956" name="Defaults" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults" useByScannerDiscovery="false" value="com.st.stm32cube.ide.common.services.build.inputs.revA.1.0.5 || Release || false || Executable || com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.base.gnu-tools-for-stm32 || STM32H743VITx || 0 || 0 || arm-none-eabi- || ${gnu_tools_for_stm32_compiler_path} || ../Middlewares/Third_Party/FreeRTOS/Source/include | ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F | ../Drivers/CMSIS/Include | ../Core/Inc | ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy | ../Drivers/CMSIS/Device/ST/STM32H7xx/Include | ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 | ../Drivers/STM32H7xx_HAL_Driver/Inc ||  ||  || USE_HAL_DRIVER | STM32H743xx ||  || Drivers | Core/Startup | Middlewares | Core ||  ||  || ${workspace_loc:/${ProjName}/STM32H743VITX_FLASH.ld} || true || NonSecure ||  || secure_nsclib.o ||  || None || " valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults.1018201956" name="Defaults" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults" useByScannerDiscovery="false" value="com.st.stm32cube.ide.common.services.build.inputs.revA.1.0.6 || Release || false || Executable || com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.base.gnu-tools-for-stm32 || STM32H743VITx || 0 || 0 || arm-none-eabi- || ${gnu_tools_for_stm32_compiler_path} || ../Middlewares/Third_Party/FreeRTOS/Source/include | ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F | ../Drivers/CMSIS/Include | ../Core/Inc | ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy | ../Drivers/CMSIS/Device/ST/STM32H7xx/Include | ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 | ../Drivers/STM32H7xx_HAL_Driver/Inc ||  ||  || USE_HAL_DRIVER | STM32H743xx ||  || Drivers | Core/Startup | Middlewares | Core ||  ||  || ${workspace_loc:/${ProjName}/STM32H743VITX_FLASH.ld} || true || NonSecure ||  || secure_nsclib.o ||  || None ||  ||  || " valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.debug.option.cpuclock.1127082935" superClass="com.st.stm32cube.ide.mcu.debug.option.cpuclock" useByScannerDiscovery="false" value="100" valueType="string"/>
 							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform.1407912381" isAbstract="false" osList="all" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform"/>
 							<builder buildPath="${workspace_loc:/ECU}/Release" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder.839194533" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder"/>
 							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.326150318" name="MCU GCC Assembler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler">
diff --git a/Core/Inc/util/CMSIS_extra/global_variables_handler.h b/Core/Inc/util/CMSIS_extra/global_variables_handler.h
index 8433253a..df08fc98 100644
--- a/Core/Inc/util/CMSIS_extra/global_variables_handler.h
+++ b/Core/Inc/util/CMSIS_extra/global_variables_handler.h
@@ -49,6 +49,7 @@ typedef enum {
     REAR_AVG_SPEED,
     STEERING_WHEEL,
     GYRO_YAW,
+	IMU_ACCEL,
     INTERNAL_WHEEL,
     RACE_MODE,
     THROTTLE_PERCENT,
diff --git a/Core/Inc/util/global_definitions.h b/Core/Inc/util/global_definitions.h
index b4e55c5d..b8e97573 100644
--- a/Core/Inc/util/global_definitions.h
+++ b/Core/Inc/util/global_definitions.h
@@ -111,7 +111,7 @@ typedef enum {
 #define INVERTER_READY_THREAD_FLAG                      (1 << 6)
 #define ODOMETER_SAVE_THREAD_FLAG                       (1 << 7)
 #define DYNAMIC_CONTROL_THREAD_FLAG                     (1 << 8)
-#define CROSS_VALIDATION_ERROR_THREAD_FLAG	  			(1 << 9)
+#define CROSS_VALIDATION_THREAD_FLAG	  				(1 << 9)
 #define IMU_BSE_ERROR_THREAD_FLAG						(1 << 10)
 #define IMU_SPEED_ERROR_THREAD_FLAG						(1 << 11)
 
diff --git a/Core/Src/dynamic_controls/security_architecture.c b/Core/Src/dynamic_controls/security_architecture.c
index fc0468c9..2f3a49df 100644
--- a/Core/Src/dynamic_controls/security_architecture.c
+++ b/Core/Src/dynamic_controls/security_architecture.c
@@ -8,7 +8,6 @@
 #include "dynamic_controls/security_architecture.h"
 
 #include "CAN/general_can_data_manager.h"
-#include "cmsis_os2.h"
 #include "sensors/sensor_data_processing.h"
 #include "util/util.h"
 #include "util/global_instances.h"
@@ -23,7 +22,7 @@ void cross_validation(void* argument) {
     for (;;) {
         ECU_ENABLE_BREAKPOINT_DEBUG();
 
-        osThreadFlagsWait(DYNAMIC_CONTROLS_CHOICE_BTN_PRESSED_THREAD_FLAG, osFlagsWaitAny, osWaitForever);
+        osThreadFlagsWait(DYNAMIC_CONTROL_THREAD_FLAG, osFlagsWaitAny, osWaitForever);
 
         IMU_ACCEL_t IMU_long_accel_data = (int16_t)general_get_value(accelerometer_z);
         REAR_AVG_SPEED_t speed_data = get_global_var_value(REAR_AVG_SPEED);
@@ -45,7 +44,7 @@ void cross_validation(void* argument) {
 
         else{
         	osTimerStop(tim_cross_validation_errorHandle);
-        	osEventFlagsClear(e_ECU_control_flagsHandle, CROSS_VALIDATION_ERROR_THREAD_FLAG);
+        	osEventFlagsClear(e_ECU_control_flagsHandle, CROSS_VALIDATION_THREAD_FLAG);
         }
     }
 }
@@ -64,5 +63,5 @@ bool is_there_imu_speed_error(){
 }
 
 void cross_validation_error_callback(){
-	osEventFlagsSet(e_ECU_control_flagsHandle, CROSS_VALIDATION_ERROR_THREAD_FLAG);
+	osEventFlagsSet(e_ECU_control_flagsHandle, CROSS_VALIDATION_THREAD_FLAG);
 }
diff --git a/Core/Src/main.c b/Core/Src/main.c
index 51b76f2d..e2d61d4c 100644
--- a/Core/Src/main.c
+++ b/Core/Src/main.c
@@ -461,7 +461,7 @@ int main(void)
   tim_right_inv_errorHandle = osTimerNew(right_inv_error_callback, osTimerPeriodic, (void*) RIGHT_INVERTER_COMM_ERROR_FLAG, &tim_right_inv_error_attributes);
 
   /* creation of tim_cross_validation_error */
-  tim_cross_validation_errorHandle = osTimerNew(cross_validation_error_callback, osTimerPeriodic, (void*) CROSS_VALIDATION_ERROR_THREAD_FLAG, &tim_cross_validation_error_attributes);
+  tim_cross_validation_errorHandle = osTimerNew(cross_validation_error_callback, osTimerPeriodic, (void*) CROSS_VALIDATION_THREAD_FLAG, &tim_cross_validation_error_attributes);
 
   /* USER CODE BEGIN RTOS_TIMERS */
   /* start timers, add new ones, ... */
diff --git a/Core/Src/torque_command/torque_manager.c b/Core/Src/torque_command/torque_manager.c
index 1a9f0086..82af8d78 100644
--- a/Core/Src/torque_command/torque_manager.c
+++ b/Core/Src/torque_command/torque_manager.c
@@ -36,7 +36,7 @@ void torque_manager(void* argument) {
         const bool is_DYNAMIC_CONTROL_active =
             get_individual_flag(e_ECU_control_flagsHandle, DYNAMIC_CONTROL_THREAD_FLAG);
         const bool is_there_CROSS_VALIDATION_error =
-        	get_individual_flag(e_ECU_control_flagsHandle, CROSS_VALIDATION_ERROR_THREAD_FLAG); // COLOCA UM TIMER Q SETA ESSA FLAG
+        	get_individual_flag(e_ECU_control_flagsHandle, CROSS_VALIDATION_THREAD_FLAG); // COLOCA UM TIMER Q SETA ESSA FLAG
 
         select_dynamic_control(is_DYNAMIC_CONTROL_active, is_there_CROSS_VALIDATION_error);
 
diff --git a/Core/Src/util/CMSIS_extra/global_variables_handler.c b/Core/Src/util/CMSIS_extra/global_variables_handler.c
index a1b4c4ca..b43f8a43 100644
--- a/Core/Src/util/CMSIS_extra/global_variables_handler.c
+++ b/Core/Src/util/CMSIS_extra/global_variables_handler.c
@@ -56,6 +56,7 @@ void init_global_variables() {
     INSTANTIATE_GLOBAL_VAR_QUEUE(REAR_AVG_SPEED);
     INSTANTIATE_GLOBAL_VAR_QUEUE(STEERING_WHEEL);
     INSTANTIATE_GLOBAL_VAR_QUEUE(GYRO_YAW);
+    INSTANTIATE_GLOBAL_VAR_QUEUE(IMU_ACCEL);
     INSTANTIATE_GLOBAL_VAR_QUEUE(INTERNAL_WHEEL);
     INSTANTIATE_GLOBAL_VAR_QUEUE(RACE_MODE);
     INSTANTIATE_GLOBAL_VAR_QUEUE(THROTTLE_PERCENT);
diff --git a/ECU.ioc b/ECU.ioc
index 9c9289dc..4e79b7bd 100644
--- a/ECU.ioc
+++ b/ECU.ioc
@@ -97,7 +97,7 @@ FREERTOS.IPParameters=Tasks01,configMINIMAL_STACK_SIZE,FootprintOK,Queues01,conf
 FREERTOS.Mutexes01=m_state_parameter_mutex,Dynamic,NULL
 FREERTOS.Queues01=q_encoder_int_message,16,encoder_int_message_t,0,Dynamic,NULL,NULL;q_torque_message,16,torque_message_t,0,Dynamic,NULL,NULL;q_ref_torque_message,16,ref_torque_t,0,Dynamic,NULL,NULL;q_datalog_message,128,datalog_message_t,0,Dynamic,NULL,NULL;q_debug_leds_message,16,debug_led_message_t,0,Dynamic,NULL,NULL;q_rgb_led_message,16,rgb_led_message_t,0,Dynamic,NULL,NULL;q_throttle_control,16,uint16_t,0,Dynamic,NULL,NULL;q_encoder_speeds_message,1,encoder_speeds_message_t,0,Dynamic,NULL,NULL;q_odometer_calc_save_message,1,odometer_message_t,0,Dynamic,NULL,NULL;q_ids_can_inverter,32,uint32_t,0,Dynamic,NULL,NULL
 FREERTOS.Tasks01=t_main_task,24,1024,main_task,As weak,NULL,Dynamic,NULL,NULL;t_torque_parameters,8,1024,torque_parameters,As external,NULL,Dynamic,NULL,NULL;t_datalogger,8,1024,datalogger,As external,NULL,Dynamic,NULL,NULL;t_APPS_read,8,1024,APPS_read,As external,NULL,Dynamic,NULL,NULL;t_steering_read,8,1024,steering_read,As external,NULL,Dynamic,NULL,NULL;t_encoder_speed_calc,8,1024,encoder_speed_calc,As external,NULL,Dynamic,NULL,NULL;t_odometer_calc,8,1024,odometer_calc,As external,NULL,Dynamic,NULL,NULL;t_torque_message,8,1024,torque_message,As external,NULL,Dynamic,NULL,NULL;t_torque_manager,8,1024,torque_manager,As external,NULL,Dynamic,NULL,NULL;t_debug_leds,8,1024,debug_leds,As external,NULL,Dynamic,NULL,NULL;t_rgb_led,8,1024,rgb_led,As external,NULL,Dynamic,NULL,NULL;t_seleciona_modo,8,1024,seleciona_modo,As external,NULL,Dynamic,NULL,NULL;t_RTD,8,1024,RTD,As external,NULL,Dynamic,NULL,NULL;t_throttle_control,8,1024,throttle_control,As external,NULL,Dynamic,NULL,NULL;t_datalog_acquisition,8,1024,datalog_acquisition,As external,NULL,Dynamic,NULL,NULL;t_inverter_comm_error,8,1024,inverter_comm_error,As external,NULL,Dynamic,NULL,NULL;t_inverter_datalog,8,1024,inverter_datalog,As external,NULL,Dynamic,NULL,NULL;t_pilot_reset,8,1024,pilot_reset,As external,NULL,Dynamic,NULL,NULL;t_buttons_handler,8,1024,buttons_handler,As external,NULL,Dynamic,NULL,NULL;t_speed_datalog,8,1024,speed_datalog,As external,NULL,Dynamic,NULL,NULL;t_odometer_save,8,1024,odometer_save,As external,NULL,Dynamic,NULL,NULL;t_dynamic_controls_choice,8,1024,dynamic_controls_choice,As external,NULL,Dynamic,NULL,NULL;t_cross_validation,8,1024,cross_validation,As external,NULL,Dynamic,NULL,NULL
-FREERTOS.Timers01=tim_SU_F_error,errors_with_timer_callback,osTimerOnce,As external,SU_F_ERROR_FLAG,Dynamic,NULL;tim_APPS_error,errors_with_timer_callback,osTimerOnce,As external,APPS_ERROR_FLAG,Dynamic,NULL;tim_inverter_BUS_OFF_error,inverter_BUS_OFF_error_callback,osTimerOnce,As external,NULL,Dynamic,NULL;tim_inverter_ready,inverter_ready_callback,osTimerOnce,As external,NULL,Dynamic,NULL;tim_inverter_can_transmit_error,errors_with_timer_callback,osTimerOnce,As external,INVERTER_CAN_TRANSMIT_ERROR_FLAG,Dynamic,NULL;tim_left_inv_error,left_inv_error_callback,osTimerPeriodic,As external,LEFT_INVERTER_COMM_ERROR_FLAG,Dynamic,NULL;tim_right_inv_error,right_inv_error_callback,osTimerPeriodic,As external,RIGHT_INVERTER_COMM_ERROR_FLAG,Dynamic,NULL;tim_cross_validation_error,cross_validation_error_callback,osTimerPeriodic,As external,CROSS_VALIDATION_ERROR_THREAD_FLAG,Dynamic,NULL
+FREERTOS.Timers01=tim_SU_F_error,errors_with_timer_callback,osTimerOnce,As external,SU_F_ERROR_FLAG,Dynamic,NULL;tim_APPS_error,errors_with_timer_callback,osTimerOnce,As external,APPS_ERROR_FLAG,Dynamic,NULL;tim_inverter_BUS_OFF_error,inverter_BUS_OFF_error_callback,osTimerOnce,As external,NULL,Dynamic,NULL;tim_inverter_ready,inverter_ready_callback,osTimerOnce,As external,NULL,Dynamic,NULL;tim_inverter_can_transmit_error,errors_with_timer_callback,osTimerOnce,As external,INVERTER_CAN_TRANSMIT_ERROR_FLAG,Dynamic,NULL;tim_left_inv_error,left_inv_error_callback,osTimerPeriodic,As external,LEFT_INVERTER_COMM_ERROR_FLAG,Dynamic,NULL;tim_right_inv_error,right_inv_error_callback,osTimerPeriodic,As external,RIGHT_INVERTER_COMM_ERROR_FLAG,Dynamic,NULL;tim_cross_validation_error,cross_validation_error_callback,osTimerPeriodic,As external,CROSS_VALIDATION_THREAD_FLAG,Dynamic,NULL
 FREERTOS.configCHECK_FOR_STACK_OVERFLOW=2
 FREERTOS.configENABLE_FPU=1
 FREERTOS.configMAX_TASK_NAME_LEN=32
@@ -369,6 +369,7 @@ ProjectManager.PreviousToolchain=STM32CubeIDE
 ProjectManager.ProjectBuild=false
 ProjectManager.ProjectFileName=ECU.ioc
 ProjectManager.ProjectName=ECU
+ProjectManager.ProjectStructure=
 ProjectManager.RegisterCallBack=FDCAN
 ProjectManager.StackSize=0x400
 ProjectManager.TargetToolchain=STM32CubeIDE
@@ -498,4 +499,5 @@ VP_TIM1_VS_ClockSourceINT.Signal=TIM1_VS_ClockSourceINT
 VP_TIM2_VS_ClockSourceINT.Mode=Internal
 VP_TIM2_VS_ClockSourceINT.Signal=TIM2_VS_ClockSourceINT
 board=custom
+rtos.0.ip=FREERTOS
 isbadioc=false

From e68d337e5f7f7e6f317db8aea2e6fab6b237d179 Mon Sep 17 00:00:00 2001
From: caiussouza <caiuscsouza@gmail.com>
Date: Fri, 17 Mar 2023 15:16:26 -0300
Subject: [PATCH 17/33] datalogging function added

---
 Core/Inc/CAN/CAN_IDs.h                        | 63 ++++++++++---------
 .../dynamic_controls/security_architecture.h  |  3 +
 Core/Inc/util/global_definitions.h            |  2 -
 Core/Src/CAN/CAN_IDs.c                        |  2 +
 .../driver_settings/dynamic_controls_choice.c |  1 -
 .../dynamic_controls/security_architecture.c  | 16 ++++-
 6 files changed, 54 insertions(+), 33 deletions(-)

diff --git a/Core/Inc/CAN/CAN_IDs.h b/Core/Inc/CAN/CAN_IDs.h
index f1c322c8..7f50f4cd 100644
--- a/Core/Inc/CAN/CAN_IDs.h
+++ b/Core/Inc/CAN/CAN_IDs.h
@@ -46,35 +46,38 @@
 #define ID_TEMPERATURE2_R       24
 #define ID_TEMPERATURE1_L       25
 #define ID_TEMPERATURE2_L       26
-#define ID_STATUS_DATALOG       27
-#define ID_CURRENT_FLAG         28
-#define ID_PANEL_DEBUG_1        29
-#define ID_PANEL_DEBUG_2        30
-#define ID_PANEL_DEBUG_3        31
-#define ID_PANEL_DEBUG_4        32
-#define ID_REGEN_BRAKE_STATE    33
-#define ID_SPEED_L_MOTOR        34
-#define ID_SPEED_R_MOTOR        35
-#define ID_POWER_L_MOTOR        36
-#define ID_POWER_R_MOTOR        37
-#define ID_ENERGY_L_MOTOR       38
-#define ID_ENERGY_R_MOTOR       39
-#define ID_OVERLOAD_L_MOTOR     40
-#define ID_OVERLOAD_R_MOTOR     41
-#define ID_LOST_MSG_L_MOTOR     42
-#define ID_LOST_MSG_R_MOTOR     43
-#define ID_BUS_OFF_L_MOTOR      44
-#define ID_BUS_OFF_R_MOTOR      45
-#define ID_CAN_STATE_L_MOTOR    46
-#define ID_CAN_STATE_R_MOTOR    47
-#define ID_INV_STATE_L_MOTOR    48
-#define ID_INV_STATE_R_MOTOR    49
-#define ID_FAILURE_L_MOTOR      50
-#define ID_FAILURE_R_MOTOR      51
-#define ID_ALARM_L_MOTOR        52
-#define ID_ALARM_R_MOTOR        53
+#define ID_IMU_BSE_ERROR        27
+#define ID_STATUS_DATALOG       28
+#define ID_IMU_SPEED_ERROR      29
+#define ID_CURRENT_FLAG         30
+#define ID_PANEL_DEBUG_1        31
+#define ID_PANEL_DEBUG_2        32
+#define ID_PANEL_DEBUG_3        33
+#define ID_PANEL_DEBUG_4        34
+#define ID_REGEN_BRAKE_STATE    35
+#define ID_SPEED_L_MOTOR        36
+#define ID_SPEED_R_MOTOR        37
+#define ID_POWER_L_MOTOR        38
+#define ID_POWER_R_MOTOR        39
+#define ID_ENERGY_L_MOTOR       40
+#define ID_ENERGY_R_MOTOR       41
+#define ID_OVERLOAD_L_MOTOR     42
+#define ID_OVERLOAD_R_MOTOR     43
+#define ID_LOST_MSG_L_MOTOR     44
+#define ID_LOST_MSG_R_MOTOR     45
+#define ID_BUS_OFF_L_MOTOR      46
+#define ID_BUS_OFF_R_MOTOR      47
+#define ID_CAN_STATE_L_MOTOR    48
+#define ID_CAN_STATE_R_MOTOR    49
+#define ID_INV_STATE_L_MOTOR    50
+#define ID_INV_STATE_R_MOTOR    51
+#define ID_FAILURE_L_MOTOR      52
+#define ID_FAILURE_R_MOTOR      53
+#define ID_ALARM_L_MOTOR        54
+#define ID_ALARM_R_MOTOR        55
 
-#define CAN_ID_QUAN 54
+
+#define CAN_ID_QUAN 56
 
 typedef struct {
     uint16_t id;
@@ -141,8 +144,12 @@ extern CAN_ID_t CAN_ID_map[CAN_ID_QUAN];
     { 107, 2 }
 #define INTERNAL_ID_TEMPERATURE2_L                                                       \
     { 107, 3 }
+#define INTERNAL_ID_IMU_BSE_ERROR													     \
+	{ 108, 0 }
 #define INTERNAL_ID_STATUS_DATALOG                                                       \
     { 108, 1 }
+#define INTERNAL_ID_IMU_SPEED_ERROR													     \
+	{ 108, 2 }
 #define INTERNAL_ID_CURRENT_FLAG                                                         \
     { 108, 3 }
 #define INTERNAL_ID_PANEL_DEBUG_1                                                        \
diff --git a/Core/Inc/dynamic_controls/security_architecture.h b/Core/Inc/dynamic_controls/security_architecture.h
index 544d786a..ddf97074 100644
--- a/Core/Inc/dynamic_controls/security_architecture.h
+++ b/Core/Inc/dynamic_controls/security_architecture.h
@@ -18,8 +18,11 @@
 
 #define CROSS_VALIDATION_ERROR_TIME 1
 
+
+
 bool is_there_imu_bse_error();
 bool is_there_imu_speed_error();
 void cross_validation_error_callback();
+void cross_validation_status_datalog();
 
 #endif /* INC_DYNAMIC_CONTROLS_SECURITY_ARCHITECTURE_H_ */
diff --git a/Core/Inc/util/global_definitions.h b/Core/Inc/util/global_definitions.h
index b8e97573..7a64a560 100644
--- a/Core/Inc/util/global_definitions.h
+++ b/Core/Inc/util/global_definitions.h
@@ -112,8 +112,6 @@ typedef enum {
 #define ODOMETER_SAVE_THREAD_FLAG                       (1 << 7)
 #define DYNAMIC_CONTROL_THREAD_FLAG                     (1 << 8)
 #define CROSS_VALIDATION_THREAD_FLAG	  				(1 << 9)
-#define IMU_BSE_ERROR_THREAD_FLAG						(1 << 10)
-#define IMU_SPEED_ERROR_THREAD_FLAG						(1 << 11)
 
 // Warning flags	(No actions necessary)
 #define REGEN_WARN_FLAG           (1 << 12)
diff --git a/Core/Src/CAN/CAN_IDs.c b/Core/Src/CAN/CAN_IDs.c
index 95b211fb..2f868a09 100644
--- a/Core/Src/CAN/CAN_IDs.c
+++ b/Core/Src/CAN/CAN_IDs.c
@@ -53,7 +53,9 @@ void initialize_CAN_IDs() {
     CAN_ID_map[ID_TEMPERATURE2_R]       = (CAN_ID_t)INTERNAL_ID_TEMPERATURE2_R;
     CAN_ID_map[ID_TEMPERATURE1_L]       = (CAN_ID_t)INTERNAL_ID_TEMPERATURE1_L;
     CAN_ID_map[ID_TEMPERATURE2_L]       = (CAN_ID_t)INTERNAL_ID_TEMPERATURE2_L;
+    CAN_ID_map[ID_IMU_BSE_ERROR]        = (CAN_ID_t)INTERNAL_ID_IMU_BSE_ERROR;
     CAN_ID_map[ID_STATUS_DATALOG]       = (CAN_ID_t)INTERNAL_ID_STATUS_DATALOG;
+    CAN_ID_map[ID_IMU_SPEED_ERROR]      = (CAN_ID_t)INTERNAL_ID_IMU_SPEED_ERROR;
     CAN_ID_map[ID_CURRENT_FLAG]         = (CAN_ID_t)INTERNAL_ID_CURRENT_FLAG;
     CAN_ID_map[ID_PANEL_DEBUG_1]        = (CAN_ID_t)INTERNAL_ID_PANEL_DEBUG_1;
     CAN_ID_map[ID_PANEL_DEBUG_2]        = (CAN_ID_t)INTERNAL_ID_PANEL_DEBUG_2;
diff --git a/Core/Src/driver_settings/dynamic_controls_choice.c b/Core/Src/driver_settings/dynamic_controls_choice.c
index 2485ba74..f91d9572 100644
--- a/Core/Src/driver_settings/dynamic_controls_choice.c
+++ b/Core/Src/driver_settings/dynamic_controls_choice.c
@@ -11,7 +11,6 @@
 #include "util/global_instances.h"
 #include "util/global_variables.h"
 #include "util/util.h"
-#include "cmsis_os2.h"
 
 void dynamic_controls_choice(void* argument) {
     UNUSED(argument);
diff --git a/Core/Src/dynamic_controls/security_architecture.c b/Core/Src/dynamic_controls/security_architecture.c
index 2f3a49df..bd097d46 100644
--- a/Core/Src/dynamic_controls/security_architecture.c
+++ b/Core/Src/dynamic_controls/security_architecture.c
@@ -16,6 +16,10 @@ static REAR_AVG_SPEED_t speed_mov_avg;
 static IMU_ACCEL_t IMU_long_accel_mov_avg;
 static BRAKE_STATUS_t bse_active;
 
+static bool imu_bse_error_status;
+static bool imu_speed_error_status;
+
+
 void cross_validation(void* argument) {
     UNUSED(argument);
 
@@ -35,17 +39,20 @@ void cross_validation(void* argument) {
         	osTimerStart(tim_cross_validation_errorHandle, CROSS_VALIDATION_ERROR_TIME);
 
         	if(is_there_imu_bse_error()){
-        		osEventFlagsSet(e_ECU_control_flagsHandle, IMU_BSE_ERROR_THREAD_FLAG);
+        		imu_bse_error_status = 1;
         	}
+        	else imu_bse_error_status = 0;
         	if(is_there_imu_speed_error()){
-        		osEventFlagsSet(e_ECU_control_flagsHandle, IMU_SPEED_ERROR_THREAD_FLAG);
+        		imu_speed_error_status = 1;
         	}
+        	else imu_speed_error_status = 0;
         }
 
         else{
         	osTimerStop(tim_cross_validation_errorHandle);
         	osEventFlagsClear(e_ECU_control_flagsHandle, CROSS_VALIDATION_THREAD_FLAG);
         }
+        cross_validation_status_datalog();
     }
 }
 
@@ -65,3 +72,8 @@ bool is_there_imu_speed_error(){
 void cross_validation_error_callback(){
 	osEventFlagsSet(e_ECU_control_flagsHandle, CROSS_VALIDATION_THREAD_FLAG);
 }
+
+void cross_validation_status_datalog(){
+    log_data(ID_IMU_BSE_ERROR, imu_bse_error_status);
+    log_data(ID_IMU_SPEED_ERROR, imu_speed_error_status);
+}

From 877245f4d7049fc7dc105b500acbc36d303404b3 Mon Sep 17 00:00:00 2001
From: caiussouza <caiuscsouza@gmail.com>
Date: Fri, 17 Mar 2023 15:27:00 -0300
Subject: [PATCH 18/33] ready for tests

---
 Core/Inc/CAN/CAN_IDs.h                        |  9 ++-
 .../dynamic_controls/security_architecture.h  |  6 +-
 Core/Inc/util/global_definitions.h            |  2 +-
 .../dynamic_controls/security_architecture.c  | 61 ++++++++++---------
 Core/Src/sensors/sensor_data_processing.c     | 41 ++++++-------
 5 files changed, 58 insertions(+), 61 deletions(-)

diff --git a/Core/Inc/CAN/CAN_IDs.h b/Core/Inc/CAN/CAN_IDs.h
index 7f50f4cd..54432fdd 100644
--- a/Core/Inc/CAN/CAN_IDs.h
+++ b/Core/Inc/CAN/CAN_IDs.h
@@ -76,7 +76,6 @@
 #define ID_ALARM_L_MOTOR        54
 #define ID_ALARM_R_MOTOR        55
 
-
 #define CAN_ID_QUAN 56
 
 typedef struct {
@@ -144,12 +143,12 @@ extern CAN_ID_t CAN_ID_map[CAN_ID_QUAN];
     { 107, 2 }
 #define INTERNAL_ID_TEMPERATURE2_L                                                       \
     { 107, 3 }
-#define INTERNAL_ID_IMU_BSE_ERROR													     \
-	{ 108, 0 }
+#define INTERNAL_ID_IMU_BSE_ERROR                                                        \
+    { 108, 0 }
 #define INTERNAL_ID_STATUS_DATALOG                                                       \
     { 108, 1 }
-#define INTERNAL_ID_IMU_SPEED_ERROR													     \
-	{ 108, 2 }
+#define INTERNAL_ID_IMU_SPEED_ERROR                                                      \
+    { 108, 2 }
 #define INTERNAL_ID_CURRENT_FLAG                                                         \
     { 108, 3 }
 #define INTERNAL_ID_PANEL_DEBUG_1                                                        \
diff --git a/Core/Inc/dynamic_controls/security_architecture.h b/Core/Inc/dynamic_controls/security_architecture.h
index ddf97074..49643afc 100644
--- a/Core/Inc/dynamic_controls/security_architecture.h
+++ b/Core/Inc/dynamic_controls/security_architecture.h
@@ -10,16 +10,14 @@
 
 // TODO(caius): add the threshold values and the timer time
 
-#include "stdint.h"
 #include "stdbool.h"
+#include "stdint.h"
 
 #define IMU_NULL_ACCEL_MARGIN_ERROR 1
-#define NULL_SPEED_MARGIN_ERROR 1
+#define NULL_SPEED_MARGIN_ERROR     1
 
 #define CROSS_VALIDATION_ERROR_TIME 1
 
-
-
 bool is_there_imu_bse_error();
 bool is_there_imu_speed_error();
 void cross_validation_error_callback();
diff --git a/Core/Inc/util/global_definitions.h b/Core/Inc/util/global_definitions.h
index 7a64a560..069244a3 100644
--- a/Core/Inc/util/global_definitions.h
+++ b/Core/Inc/util/global_definitions.h
@@ -111,7 +111,7 @@ typedef enum {
 #define INVERTER_READY_THREAD_FLAG                      (1 << 6)
 #define ODOMETER_SAVE_THREAD_FLAG                       (1 << 7)
 #define DYNAMIC_CONTROL_THREAD_FLAG                     (1 << 8)
-#define CROSS_VALIDATION_THREAD_FLAG	  				(1 << 9)
+#define CROSS_VALIDATION_THREAD_FLAG                    (1 << 9)
 
 // Warning flags	(No actions necessary)
 #define REGEN_WARN_FLAG           (1 << 12)
diff --git a/Core/Src/dynamic_controls/security_architecture.c b/Core/Src/dynamic_controls/security_architecture.c
index bd097d46..1b35a19b 100644
--- a/Core/Src/dynamic_controls/security_architecture.c
+++ b/Core/Src/dynamic_controls/security_architecture.c
@@ -9,8 +9,8 @@
 
 #include "CAN/general_can_data_manager.h"
 #include "sensors/sensor_data_processing.h"
-#include "util/util.h"
 #include "util/global_instances.h"
+#include "util/util.h"
 
 static REAR_AVG_SPEED_t speed_mov_avg;
 static IMU_ACCEL_t IMU_long_accel_mov_avg;
@@ -19,7 +19,6 @@ static BRAKE_STATUS_t bse_active;
 static bool imu_bse_error_status;
 static bool imu_speed_error_status;
 
-
 void cross_validation(void* argument) {
     UNUSED(argument);
 
@@ -29,51 +28,53 @@ void cross_validation(void* argument) {
         osThreadFlagsWait(DYNAMIC_CONTROL_THREAD_FLAG, osFlagsWaitAny, osWaitForever);
 
         IMU_ACCEL_t IMU_long_accel_data = (int16_t)general_get_value(accelerometer_z);
-        REAR_AVG_SPEED_t speed_data = get_global_var_value(REAR_AVG_SPEED);
-        bse_active = get_global_var_value(BRAKE_STATUS);
+        REAR_AVG_SPEED_t speed_data     = get_global_var_value(REAR_AVG_SPEED);
+        bse_active                      = get_global_var_value(BRAKE_STATUS);
 
         moving_average(&IMU_long_accel_mov_avg, &IMU_long_accel_data);
         moving_average(&speed_mov_avg, &speed_data);
 
-        if(is_there_imu_bse_error() || is_there_imu_speed_error()){
-        	osTimerStart(tim_cross_validation_errorHandle, CROSS_VALIDATION_ERROR_TIME);
-
-        	if(is_there_imu_bse_error()){
-        		imu_bse_error_status = 1;
-        	}
-        	else imu_bse_error_status = 0;
-        	if(is_there_imu_speed_error()){
-        		imu_speed_error_status = 1;
-        	}
-        	else imu_speed_error_status = 0;
+        if (is_there_imu_bse_error() || is_there_imu_speed_error()) {
+            osTimerStart(tim_cross_validation_errorHandle, CROSS_VALIDATION_ERROR_TIME);
+
+            if (is_there_imu_bse_error()) {
+                imu_bse_error_status = 1;
+            } else
+                imu_bse_error_status = 0;
+            if (is_there_imu_speed_error()) {
+                imu_speed_error_status = 1;
+            } else
+                imu_speed_error_status = 0;
         }
 
-        else{
-        	osTimerStop(tim_cross_validation_errorHandle);
-        	osEventFlagsClear(e_ECU_control_flagsHandle, CROSS_VALIDATION_THREAD_FLAG);
+        else {
+            osTimerStop(tim_cross_validation_errorHandle);
+            osEventFlagsClear(e_ECU_control_flagsHandle, CROSS_VALIDATION_THREAD_FLAG);
         }
         cross_validation_status_datalog();
     }
 }
 
-
-bool is_there_imu_bse_error(){
-	if(bse_active && (IMU_long_accel_mov_avg > IMU_NULL_ACCEL_MARGIN_ERROR))
-		return true;
-	else return false;
+bool is_there_imu_bse_error() {
+    if (bse_active && (IMU_long_accel_mov_avg > IMU_NULL_ACCEL_MARGIN_ERROR))
+        return true;
+    else
+        return false;
 }
 
-bool is_there_imu_speed_error(){
-	if((speed_mov_avg < NULL_SPEED_MARGIN_ERROR) && (IMU_long_accel_mov_avg > IMU_NULL_ACCEL_MARGIN_ERROR))
-		return true;
-	else return false;
+bool is_there_imu_speed_error() {
+    if ((speed_mov_avg < NULL_SPEED_MARGIN_ERROR)
+        && (IMU_long_accel_mov_avg > IMU_NULL_ACCEL_MARGIN_ERROR))
+        return true;
+    else
+        return false;
 }
 
-void cross_validation_error_callback(){
-	osEventFlagsSet(e_ECU_control_flagsHandle, CROSS_VALIDATION_THREAD_FLAG);
+void cross_validation_error_callback() {
+    osEventFlagsSet(e_ECU_control_flagsHandle, CROSS_VALIDATION_THREAD_FLAG);
 }
 
-void cross_validation_status_datalog(){
+void cross_validation_status_datalog() {
     log_data(ID_IMU_BSE_ERROR, imu_bse_error_status);
     log_data(ID_IMU_SPEED_ERROR, imu_speed_error_status);
 }
diff --git a/Core/Src/sensors/sensor_data_processing.c b/Core/Src/sensors/sensor_data_processing.c
index e3fee532..ebf8cd38 100644
--- a/Core/Src/sensors/sensor_data_processing.c
+++ b/Core/Src/sensors/sensor_data_processing.c
@@ -7,34 +7,33 @@
 
 #include "sensors/sensor_data_processing.h"
 
+// TODO(caius): Generalize moving average service implementing this sketch, allowing
+// different types. Implement a general circular buffer as well It calculates moving
+// average for data logged from any sensor using a circular buffer
 
-// TODO(caius): Generalize moving average service implementing this sketch, allowing different types. Implement a general circular buffer as well
-// It calculates moving average for data logged from any sensor using a circular buffer
-
-static uint8_t buffer_index = 0;
-static float buffer_sum = 0;
+static uint8_t buffer_index              = 0;
+static float buffer_sum                  = 0;
 static float mov_avg_buffer[BUFFER_SIZE] = {0.0};
 
 void moving_average(float* mov_avg, float* data) {
 
-	*mov_avg = 0;
-
-	// Put the signal value read by sensor into each buffer position
-	mov_avg_buffer[buffer_index] = *data;
+    *mov_avg = 0;
 
-	// circular buffer logic
-	buffer_index = (buffer_index + 1) % BUFFER_SIZE;
+    // Put the signal value read by sensor into each buffer position
+    mov_avg_buffer[buffer_index] = *data;
 
-	// Calculate the moving average based on a mutable value
-	// It requires empirical tests for choosing that value
-	for(uint8_t i = 0; i < BUFFER_SIZE; i++){
-		buffer_sum += mov_avg_buffer[i];
-	}
-	*mov_avg = buffer_sum / (float)BUFFER_SIZE;
+    // circular buffer logic
+    buffer_index = (buffer_index + 1) % BUFFER_SIZE;
 
-	// Avoid variable type overflow
-	buffer_sum = 0;
-	if(buffer_index == 256)
-		buffer_index = 0;
+    // Calculate the moving average based on a mutable value
+    // It requires empirical tests for choosing that value
+    for (uint8_t i = 0; i < BUFFER_SIZE; i++) {
+        buffer_sum += mov_avg_buffer[i];
+    }
+    *mov_avg = buffer_sum / (float)BUFFER_SIZE;
 
+    // Avoid variable type overflow
+    buffer_sum = 0;
+    if (buffer_index == 256)
+        buffer_index = 0;
 }

From 283f0d57099f6eff1ae601c9d267e779767b0df0 Mon Sep 17 00:00:00 2001
From: caiussouza <caiuscsouza@gmail.com>
Date: Fri, 17 Mar 2023 15:38:05 -0300
Subject: [PATCH 19/33] clang format fixing

---
 Core/Inc/util/CMSIS_extra/global_variables_handler.h |  4 ++--
 Core/Src/torque_command/torque_manager.c             | 11 +++++++----
 2 files changed, 9 insertions(+), 6 deletions(-)

diff --git a/Core/Inc/util/CMSIS_extra/global_variables_handler.h b/Core/Inc/util/CMSIS_extra/global_variables_handler.h
index df08fc98..e29aa7b0 100644
--- a/Core/Inc/util/CMSIS_extra/global_variables_handler.h
+++ b/Core/Inc/util/CMSIS_extra/global_variables_handler.h
@@ -33,7 +33,7 @@ typedef modos SELECTED_MODE_t;
 #define REAR_AVG_SPEED_DEFAULT_VALUE   0
 #define STEERING_WHEEL_DEFAULT_VALUE   0
 #define GYRO_YAW_DEFAULT_VALUE         0
-#define IMU_ACCEL_DEFAULT_VALUE		   0
+#define IMU_ACCEL_DEFAULT_VALUE        0
 #define INTERNAL_WHEEL_DEFAULT_VALUE   0
 #define RACE_MODE_DEFAULT_VALUE        ENDURO
 #define THROTTLE_PERCENT_DEFAULT_VALUE 0
@@ -49,7 +49,7 @@ typedef enum {
     REAR_AVG_SPEED,
     STEERING_WHEEL,
     GYRO_YAW,
-	IMU_ACCEL,
+    IMU_ACCEL,
     INTERNAL_WHEEL,
     RACE_MODE,
     THROTTLE_PERCENT,
diff --git a/Core/Src/torque_command/torque_manager.c b/Core/Src/torque_command/torque_manager.c
index 82af8d78..509d49c0 100644
--- a/Core/Src/torque_command/torque_manager.c
+++ b/Core/Src/torque_command/torque_manager.c
@@ -31,14 +31,16 @@ void torque_manager(void* argument) {
 
         void rampa_torque(uint32_t * ref_torque, const double* ref_torque_decrease);
         void send_ref_torque_message(const uint32_t* ref_torque);
-        void select_dynamic_control(bool is_DYNAMIC_CONTROL_active, bool is_there_CROSS_VALIDATION_error);
+        void select_dynamic_control(bool is_DYNAMIC_CONTROL_active,
+                                    bool is_there_CROSS_VALIDATION_error);
 
         const bool is_DYNAMIC_CONTROL_active =
             get_individual_flag(e_ECU_control_flagsHandle, DYNAMIC_CONTROL_THREAD_FLAG);
         const bool is_there_CROSS_VALIDATION_error =
-        	get_individual_flag(e_ECU_control_flagsHandle, CROSS_VALIDATION_THREAD_FLAG); // COLOCA UM TIMER Q SETA ESSA FLAG
+            get_individual_flag(e_ECU_control_flagsHandle, CROSS_VALIDATION_THREAD_FLAG);
 
-        select_dynamic_control(is_DYNAMIC_CONTROL_active, is_there_CROSS_VALIDATION_error);
+        select_dynamic_control(is_DYNAMIC_CONTROL_active,
+                               is_there_CROSS_VALIDATION_error);
 
         // todo (João Pedro): add new "case's" when the integration of controls is
         // implemented
@@ -118,7 +120,8 @@ void send_ref_torque_message(const uint32_t* ref_torque) {
     osMessageQueuePut(q_ref_torque_messageHandle, &ref_torque_message, 0, 0U);
 }
 
-void select_dynamic_control(bool is_DYNAMIC_CONTROL_active, bool is_there_CROSS_VALIDATION_error) {
+void select_dynamic_control(bool is_DYNAMIC_CONTROL_active,
+                            bool is_there_CROSS_VALIDATION_error) {
     // todo (João Pedro): add new "if's" when the integration of controls is implemented
     if (is_DYNAMIC_CONTROL_active && !is_there_CROSS_VALIDATION_error) {
         if (get_global_var_value(SELECTED_MODE).dif_elt == 1

From 2a23b7d73dbe9e4fc639ac6264f2054cf4226eb8 Mon Sep 17 00:00:00 2001
From: caiussouza <caiuscsouza@gmail.com>
Date: Fri, 17 Mar 2023 21:09:13 -0300
Subject: [PATCH 20/33] clang tidy fixing

---
 .../dynamic_controls/security_architecture.c   | 18 ++++++++++++------
 Core/Src/sensors/sensor_data_processing.c      |  7 ++++---
 2 files changed, 16 insertions(+), 9 deletions(-)

diff --git a/Core/Src/dynamic_controls/security_architecture.c b/Core/Src/dynamic_controls/security_architecture.c
index 1b35a19b..b1ef7499 100644
--- a/Core/Src/dynamic_controls/security_architecture.c
+++ b/Core/Src/dynamic_controls/security_architecture.c
@@ -11,6 +11,7 @@
 #include "sensors/sensor_data_processing.h"
 #include "util/global_instances.h"
 #include "util/util.h"
+#include "datalogging/datalog_handler.h"
 
 static REAR_AVG_SPEED_t speed_mov_avg;
 static IMU_ACCEL_t IMU_long_accel_mov_avg;
@@ -39,12 +40,16 @@ void cross_validation(void* argument) {
 
             if (is_there_imu_bse_error()) {
                 imu_bse_error_status = 1;
-            } else
+            }
+            else{
                 imu_bse_error_status = 0;
+            }
             if (is_there_imu_speed_error()) {
                 imu_speed_error_status = 1;
-            } else
+            }
+            else{
                 imu_speed_error_status = 0;
+            }
         }
 
         else {
@@ -56,18 +61,19 @@ void cross_validation(void* argument) {
 }
 
 bool is_there_imu_bse_error() {
-    if (bse_active && (IMU_long_accel_mov_avg > IMU_NULL_ACCEL_MARGIN_ERROR))
+    if (bse_active && (IMU_long_accel_mov_avg > IMU_NULL_ACCEL_MARGIN_ERROR)){
         return true;
-    else
+    }
         return false;
 }
 
 bool is_there_imu_speed_error() {
     if ((speed_mov_avg < NULL_SPEED_MARGIN_ERROR)
-        && (IMU_long_accel_mov_avg > IMU_NULL_ACCEL_MARGIN_ERROR))
+        && (IMU_long_accel_mov_avg > IMU_NULL_ACCEL_MARGIN_ERROR)){
         return true;
-    else
+    }
         return false;
+
 }
 
 void cross_validation_error_callback() {
diff --git a/Core/Src/sensors/sensor_data_processing.c b/Core/Src/sensors/sensor_data_processing.c
index ebf8cd38..06790d50 100644
--- a/Core/Src/sensors/sensor_data_processing.c
+++ b/Core/Src/sensors/sensor_data_processing.c
@@ -13,9 +13,9 @@
 
 static uint8_t buffer_index              = 0;
 static float buffer_sum                  = 0;
-static float mov_avg_buffer[BUFFER_SIZE] = {0.0};
+static float mov_avg_buffer[BUFFER_SIZE] = {0};
 
-void moving_average(float* mov_avg, float* data) {
+void moving_average(float* mov_avg, float const* data) {
 
     *mov_avg = 0;
 
@@ -34,6 +34,7 @@ void moving_average(float* mov_avg, float* data) {
 
     // Avoid variable type overflow
     buffer_sum = 0;
-    if (buffer_index == 256)
+    if (buffer_index == 255){
         buffer_index = 0;
+    }
 }

From 55d37ebbbbb6b2eb2be0023d58436de0809e876e Mon Sep 17 00:00:00 2001
From: caiussouza <caiuscsouza@gmail.com>
Date: Fri, 17 Mar 2023 21:11:58 -0300
Subject: [PATCH 21/33] clang format

---
 .../dynamic_controls/security_architecture.c    | 17 +++++++----------
 Core/Src/sensors/sensor_data_processing.c       |  2 +-
 2 files changed, 8 insertions(+), 11 deletions(-)

diff --git a/Core/Src/dynamic_controls/security_architecture.c b/Core/Src/dynamic_controls/security_architecture.c
index b1ef7499..48aee78e 100644
--- a/Core/Src/dynamic_controls/security_architecture.c
+++ b/Core/Src/dynamic_controls/security_architecture.c
@@ -8,10 +8,10 @@
 #include "dynamic_controls/security_architecture.h"
 
 #include "CAN/general_can_data_manager.h"
+#include "datalogging/datalog_handler.h"
 #include "sensors/sensor_data_processing.h"
 #include "util/global_instances.h"
 #include "util/util.h"
-#include "datalogging/datalog_handler.h"
 
 static REAR_AVG_SPEED_t speed_mov_avg;
 static IMU_ACCEL_t IMU_long_accel_mov_avg;
@@ -40,14 +40,12 @@ void cross_validation(void* argument) {
 
             if (is_there_imu_bse_error()) {
                 imu_bse_error_status = 1;
-            }
-            else{
+            } else {
                 imu_bse_error_status = 0;
             }
             if (is_there_imu_speed_error()) {
                 imu_speed_error_status = 1;
-            }
-            else{
+            } else {
                 imu_speed_error_status = 0;
             }
         }
@@ -61,19 +59,18 @@ void cross_validation(void* argument) {
 }
 
 bool is_there_imu_bse_error() {
-    if (bse_active && (IMU_long_accel_mov_avg > IMU_NULL_ACCEL_MARGIN_ERROR)){
+    if (bse_active && (IMU_long_accel_mov_avg > IMU_NULL_ACCEL_MARGIN_ERROR)) {
         return true;
     }
-        return false;
+    return false;
 }
 
 bool is_there_imu_speed_error() {
     if ((speed_mov_avg < NULL_SPEED_MARGIN_ERROR)
-        && (IMU_long_accel_mov_avg > IMU_NULL_ACCEL_MARGIN_ERROR)){
+        && (IMU_long_accel_mov_avg > IMU_NULL_ACCEL_MARGIN_ERROR)) {
         return true;
     }
-        return false;
-
+    return false;
 }
 
 void cross_validation_error_callback() {
diff --git a/Core/Src/sensors/sensor_data_processing.c b/Core/Src/sensors/sensor_data_processing.c
index 06790d50..36a1c730 100644
--- a/Core/Src/sensors/sensor_data_processing.c
+++ b/Core/Src/sensors/sensor_data_processing.c
@@ -34,7 +34,7 @@ void moving_average(float* mov_avg, float const* data) {
 
     // Avoid variable type overflow
     buffer_sum = 0;
-    if (buffer_index == 255){
+    if (buffer_index == 255) {
         buffer_index = 0;
     }
 }

From 9afa923bfff2ad9afe7f6678e881d7def52b96f9 Mon Sep 17 00:00:00 2001
From: caiussouza <caiuscsouza@gmail.com>
Date: Fri, 17 Mar 2023 21:17:38 -0300
Subject: [PATCH 22/33] fixing

---
 Core/Inc/sensors/sensor_data_processing.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Core/Inc/sensors/sensor_data_processing.h b/Core/Inc/sensors/sensor_data_processing.h
index 13eabfed..007ef4f8 100644
--- a/Core/Inc/sensors/sensor_data_processing.h
+++ b/Core/Inc/sensors/sensor_data_processing.h
@@ -12,6 +12,6 @@
 
 #define BUFFER_SIZE 100
 
-void moving_average(float* mov_avg, float* data);
+void moving_average(float* mov_avg, float const* data);
 
 #endif /* INC_SENSORS_SENSOR_DATA_PROCESSING_H_ */

From 9812801611f93c6bea15e9552f448525e6c65417 Mon Sep 17 00:00:00 2001
From: caiussouza <caiuscsouza@gmail.com>
Date: Tue, 21 Mar 2023 17:26:34 -0300
Subject: [PATCH 23/33] Warnings fixing

---
 .../driver_settings/dynamic_controls_choice.c |  1 +
 .../dynamic_controls/security_architecture.c  | 25 ++++++-------------
 Core/Src/sensors/sensor_data_processing.c     | 16 ++++--------
 3 files changed, 14 insertions(+), 28 deletions(-)

diff --git a/Core/Src/driver_settings/dynamic_controls_choice.c b/Core/Src/driver_settings/dynamic_controls_choice.c
index f91d9572..2bd08ec1 100644
--- a/Core/Src/driver_settings/dynamic_controls_choice.c
+++ b/Core/Src/driver_settings/dynamic_controls_choice.c
@@ -34,6 +34,7 @@ void dynamic_controls_choice(void* argument) {
         if (!is_DYNAMIC_CONTROL_active) {
             osEventFlagsSet(e_ECU_control_flagsHandle, DYNAMIC_CONTROL_THREAD_FLAG);
             osThreadFlagsSet(t_cross_validationHandle, DYNAMIC_CONTROL_THREAD_FLAG);
+            osEventFlagsClear(e_ECU_control_flagsHandle, CROSS_VALIDATION_THREAD_FLAG);
         } else {
             osEventFlagsClear(e_ECU_control_flagsHandle, DYNAMIC_CONTROL_THREAD_FLAG);
             osThreadFlagsClear(DYNAMIC_CONTROL_THREAD_FLAG);
diff --git a/Core/Src/dynamic_controls/security_architecture.c b/Core/Src/dynamic_controls/security_architecture.c
index 48aee78e..49568f91 100644
--- a/Core/Src/dynamic_controls/security_architecture.c
+++ b/Core/Src/dynamic_controls/security_architecture.c
@@ -13,8 +13,8 @@
 #include "util/global_instances.h"
 #include "util/util.h"
 
-static REAR_AVG_SPEED_t speed_mov_avg;
-static IMU_ACCEL_t IMU_long_accel_mov_avg;
+static float speed_mov_avg;
+static float IMU_long_accel_mov_avg;
 static BRAKE_STATUS_t bse_active;
 
 static bool imu_bse_error_status;
@@ -28,31 +28,22 @@ void cross_validation(void* argument) {
 
         osThreadFlagsWait(DYNAMIC_CONTROL_THREAD_FLAG, osFlagsWaitAny, osWaitForever);
 
-        IMU_ACCEL_t IMU_long_accel_data = (int16_t)general_get_value(accelerometer_z);
-        REAR_AVG_SPEED_t speed_data     = get_global_var_value(REAR_AVG_SPEED);
-        bse_active                      = get_global_var_value(BRAKE_STATUS);
+        float IMU_long_accel_data = (float)general_get_value(accelerometer_z);
+        float speed_data          = (float)get_global_var_value(REAR_AVG_SPEED);
+        bse_active                = get_global_var_value(BRAKE_STATUS);
 
         moving_average(&IMU_long_accel_mov_avg, &IMU_long_accel_data);
         moving_average(&speed_mov_avg, &speed_data);
 
+        imu_bse_error_status   = is_there_imu_bse_error();
+        imu_speed_error_status = is_there_imu_speed_error();
+
         if (is_there_imu_bse_error() || is_there_imu_speed_error()) {
             osTimerStart(tim_cross_validation_errorHandle, CROSS_VALIDATION_ERROR_TIME);
-
-            if (is_there_imu_bse_error()) {
-                imu_bse_error_status = 1;
-            } else {
-                imu_bse_error_status = 0;
-            }
-            if (is_there_imu_speed_error()) {
-                imu_speed_error_status = 1;
-            } else {
-                imu_speed_error_status = 0;
-            }
         }
 
         else {
             osTimerStop(tim_cross_validation_errorHandle);
-            osEventFlagsClear(e_ECU_control_flagsHandle, CROSS_VALIDATION_THREAD_FLAG);
         }
         cross_validation_status_datalog();
     }
diff --git a/Core/Src/sensors/sensor_data_processing.c b/Core/Src/sensors/sensor_data_processing.c
index 36a1c730..e79584e6 100644
--- a/Core/Src/sensors/sensor_data_processing.c
+++ b/Core/Src/sensors/sensor_data_processing.c
@@ -7,9 +7,8 @@
 
 #include "sensors/sensor_data_processing.h"
 
-// TODO(caius): Generalize moving average service implementing this sketch, allowing
-// different types. Implement a general circular buffer as well It calculates moving
-// average for data logged from any sensor using a circular buffer
+// TODO(caius): It generalizes moving average service implementing this sketch, allowing
+// different types. It implements a general circular buffer as well.
 
 static uint8_t buffer_index              = 0;
 static float buffer_sum                  = 0;
@@ -17,16 +16,11 @@ static float mov_avg_buffer[BUFFER_SIZE] = {0};
 
 void moving_average(float* mov_avg, float const* data) {
 
-    *mov_avg = 0;
-
-    // Put the signal value read by sensor into each buffer position
+    *mov_avg                     = 0;
     mov_avg_buffer[buffer_index] = *data;
+    buffer_index                 = (buffer_index + 1) % BUFFER_SIZE;
 
-    // circular buffer logic
-    buffer_index = (buffer_index + 1) % BUFFER_SIZE;
-
-    // Calculate the moving average based on a mutable value
-    // It requires empirical tests for choosing that value
+    // TODO(caius): It requires empirical tests for choosing that value
     for (uint8_t i = 0; i < BUFFER_SIZE; i++) {
         buffer_sum += mov_avg_buffer[i];
     }

From bd66c2f7935b2a90fd2c517bd63f59b4ccb5394e Mon Sep 17 00:00:00 2001
From: caiussouza <caiuscsouza@gmail.com>
Date: Mon, 3 Apr 2023 01:03:47 -0300
Subject: [PATCH 24/33] flag number fixing

---
 Core/Inc/util/global_definitions.h | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/Core/Inc/util/global_definitions.h b/Core/Inc/util/global_definitions.h
index 069244a3..e112dba3 100644
--- a/Core/Inc/util/global_definitions.h
+++ b/Core/Inc/util/global_definitions.h
@@ -114,20 +114,20 @@ typedef enum {
 #define CROSS_VALIDATION_THREAD_FLAG                    (1 << 9)
 
 // Warning flags	(No actions necessary)
-#define REGEN_WARN_FLAG           (1 << 12)
-#define DYNAMIC_CONTROL_WARN_FLAG (1 << 13)
-#define FLASH_SAVE_LIMIT_FLAG     (1 << 14)
+#define REGEN_WARN_FLAG           (1 << 10)
+#define DYNAMIC_CONTROL_WARN_FLAG (1 << 11)
+#define FLASH_SAVE_LIMIT_FLAG     (1 << 12)
 // Soft error flags (RTD keeps on, torque ref to inverter is set to 0)
 
-#define BSE_ERROR_FLAG  (1 << 18) // Regulamento: EV.5.7 (2021)
-#define APPS_ERROR_FLAG (1 << 19) // Regulamento: T.4.2 (2021)
+#define BSE_ERROR_FLAG  (1 << 16) // Regulamento: EV.5.7 (2021)
+#define APPS_ERROR_FLAG (1 << 17) // Regulamento: T.4.2 (2021)
 
 // Hard error flags (RTD disable)
-#define INVERTER_CAN_TRANSMIT_ERROR_FLAG (1 << 21)
-#define SU_F_ERROR_FLAG                  (1 << 22)
-#define INVERTER_BUS_OFF_ERROR_FLAG      (1 << 23)
-#define LEFT_INVERTER_COMM_ERROR_FLAG    (1 << 24)
-#define RIGHT_INVERTER_COMM_ERROR_FLAG   (1 << 25)
+#define INVERTER_CAN_TRANSMIT_ERROR_FLAG (1 << 19)
+#define SU_F_ERROR_FLAG                  (1 << 20)
+#define INVERTER_BUS_OFF_ERROR_FLAG      (1 << 21)
+#define LEFT_INVERTER_COMM_ERROR_FLAG    (1 << 22)
+#define RIGHT_INVERTER_COMM_ERROR_FLAG   (1 << 23)
 
 #define ALL_WARN_FLAG        (REGEN_WARN_FLAG | DYNAMIC_CONTROL_WARN_FLAG)
 #define ALL_MINOR_ERROR_FLAG (APPS_ERROR_FLAG | BSE_ERROR_FLAG)

From 97edb1ccac2e7fed7a2e6295db110931ba9dc4cd Mon Sep 17 00:00:00 2001
From: caiussouza <caiuscsouza@gmail.com>
Date: Mon, 3 Apr 2023 01:19:13 -0300
Subject: [PATCH 25/33] flag neme fixing

---
 Core/Inc/util/global_definitions.h                 |  2 +-
 Core/Src/driver_settings/dynamic_controls_choice.c | 10 +++++-----
 Core/Src/driver_settings/modo.c                    |  2 +-
 Core/Src/dynamic_controls/security_architecture.c  |  3 ++-
 Core/Src/torque_command/torque_manager.c           |  2 +-
 5 files changed, 10 insertions(+), 9 deletions(-)

diff --git a/Core/Inc/util/global_definitions.h b/Core/Inc/util/global_definitions.h
index e112dba3..2b886d8d 100644
--- a/Core/Inc/util/global_definitions.h
+++ b/Core/Inc/util/global_definitions.h
@@ -110,7 +110,7 @@ typedef enum {
 #define INVERTER_CAN_ACTIVE_THREAD_FLAG                 (1 << 5)
 #define INVERTER_READY_THREAD_FLAG                      (1 << 6)
 #define ODOMETER_SAVE_THREAD_FLAG                       (1 << 7)
-#define DYNAMIC_CONTROL_THREAD_FLAG                     (1 << 8)
+#define DYNAMIC_CONTROL_FLAG                     		(1 << 8)
 #define CROSS_VALIDATION_THREAD_FLAG                    (1 << 9)
 
 // Warning flags	(No actions necessary)
diff --git a/Core/Src/driver_settings/dynamic_controls_choice.c b/Core/Src/driver_settings/dynamic_controls_choice.c
index 2bd08ec1..bb9fbc98 100644
--- a/Core/Src/driver_settings/dynamic_controls_choice.c
+++ b/Core/Src/driver_settings/dynamic_controls_choice.c
@@ -29,15 +29,15 @@ void dynamic_controls_choice(void* argument) {
             continue;
         }
         const bool is_DYNAMIC_CONTROL_active =
-            get_individual_flag(e_ECU_control_flagsHandle, DYNAMIC_CONTROL_THREAD_FLAG);
+            get_individual_flag(e_ECU_control_flagsHandle, DYNAMIC_CONTROL_FLAG);
 
         if (!is_DYNAMIC_CONTROL_active) {
-            osEventFlagsSet(e_ECU_control_flagsHandle, DYNAMIC_CONTROL_THREAD_FLAG);
-            osThreadFlagsSet(t_cross_validationHandle, DYNAMIC_CONTROL_THREAD_FLAG);
+            osEventFlagsSet(e_ECU_control_flagsHandle, DYNAMIC_CONTROL_FLAG);
+            osThreadFlagsSet(t_cross_validationHandle, DYNAMIC_CONTROL_FLAG);
             osEventFlagsClear(e_ECU_control_flagsHandle, CROSS_VALIDATION_THREAD_FLAG);
         } else {
-            osEventFlagsClear(e_ECU_control_flagsHandle, DYNAMIC_CONTROL_THREAD_FLAG);
-            osThreadFlagsClear(DYNAMIC_CONTROL_THREAD_FLAG);
+            osEventFlagsClear(e_ECU_control_flagsHandle, DYNAMIC_CONTROL_FLAG);
+            osThreadFlagsClear(DYNAMIC_CONTROL_FLAG);
         }
     }
 }
diff --git a/Core/Src/driver_settings/modo.c b/Core/Src/driver_settings/modo.c
index 51f1dc76..0ea1046f 100644
--- a/Core/Src/driver_settings/modo.c
+++ b/Core/Src/driver_settings/modo.c
@@ -39,7 +39,7 @@ void seleciona_modo(void* argument) {
             }
 
             set_rgb_led(get_global_var_value(SELECTED_MODE).cor, BLINK200);
-            osEventFlagsClear(e_ECU_control_flagsHandle, DYNAMIC_CONTROL_THREAD_FLAG);
+            osEventFlagsClear(e_ECU_control_flagsHandle, DYNAMIC_CONTROL_FLAG);
         }
         // todo: dataloggar modos
     }
diff --git a/Core/Src/dynamic_controls/security_architecture.c b/Core/Src/dynamic_controls/security_architecture.c
index 49568f91..d77f23b6 100644
--- a/Core/Src/dynamic_controls/security_architecture.c
+++ b/Core/Src/dynamic_controls/security_architecture.c
@@ -26,7 +26,7 @@ void cross_validation(void* argument) {
     for (;;) {
         ECU_ENABLE_BREAKPOINT_DEBUG();
 
-        osThreadFlagsWait(DYNAMIC_CONTROL_THREAD_FLAG, osFlagsWaitAny, osWaitForever);
+        osThreadFlagsWait(DYNAMIC_CONTROL_FLAG, osFlagsNoClear, osWaitForever);
 
         float IMU_long_accel_data = (float)general_get_value(accelerometer_z);
         float speed_data          = (float)get_global_var_value(REAR_AVG_SPEED);
@@ -47,6 +47,7 @@ void cross_validation(void* argument) {
         }
         cross_validation_status_datalog();
     }
+    osDelay(CROSS_VALIDATION_DELAY);
 }
 
 bool is_there_imu_bse_error() {
diff --git a/Core/Src/torque_command/torque_manager.c b/Core/Src/torque_command/torque_manager.c
index 509d49c0..10f36679 100644
--- a/Core/Src/torque_command/torque_manager.c
+++ b/Core/Src/torque_command/torque_manager.c
@@ -35,7 +35,7 @@ void torque_manager(void* argument) {
                                     bool is_there_CROSS_VALIDATION_error);
 
         const bool is_DYNAMIC_CONTROL_active =
-            get_individual_flag(e_ECU_control_flagsHandle, DYNAMIC_CONTROL_THREAD_FLAG);
+            get_individual_flag(e_ECU_control_flagsHandle, DYNAMIC_CONTROL_FLAG);
         const bool is_there_CROSS_VALIDATION_error =
             get_individual_flag(e_ECU_control_flagsHandle, CROSS_VALIDATION_THREAD_FLAG);
 

From 7fb72a3a8ec21c8da4ab80a813198ab2de1babd6 Mon Sep 17 00:00:00 2001
From: caiussouza <caiuscsouza@gmail.com>
Date: Mon, 3 Apr 2023 17:12:35 -0300
Subject: [PATCH 26/33] merge conflicts fixing

---
 .cproject                                     |  2 +-
 Core/Inc/util/global_definitions.h            |  2 +-
 .../driver_settings/dynamic_controls_choice.c |  2 +-
 .../dynamic_controls/security_architecture.c  |  4 +--
 Core/Src/main.c                               | 27 ++++++++++++++++---
 Core/Src/torque_command/torque_manager.c      |  2 +-
 6 files changed, 29 insertions(+), 10 deletions(-)

diff --git a/.cproject b/.cproject
index a1f556e9..efda18d5 100644
--- a/.cproject
+++ b/.cproject
@@ -26,7 +26,7 @@
 							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi.434450183" name="Floating-point ABI" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi" useByScannerDiscovery="true" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi.value.hard" valueType="enumerated"/>
 							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board.1189751738" name="Board" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board" useByScannerDiscovery="false" value="genericBoard" valueType="string"/>
 							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults.314650556" name="Defaults" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults" useByScannerDiscovery="false" value="com.st.stm32cube.ide.common.services.build.inputs.revA.1.0.6 || Debug || true || Executable || com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.base.gnu-tools-for-stm32 || STM32H743VITx || 0 || 0 || arm-none-eabi- || ${gnu_tools_for_stm32_compiler_path} || ../Middlewares/Third_Party/FreeRTOS/Source/include | ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F | ../Drivers/CMSIS/Include | ../Core/Inc | ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy | ../Drivers/CMSIS/Device/ST/STM32H7xx/Include | ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 | ../Drivers/STM32H7xx_HAL_Driver/Inc ||  ||  || USE_HAL_DRIVER | STM32H743xx ||  || Drivers | Core/Startup | Middlewares | Core ||  ||  || ${workspace_loc:/${ProjName}/STM32H743VITX_FLASH.ld} || true || NonSecure ||  || secure_nsclib.o ||  || None ||  ||  || " valueType="string"/>
-							<option id="com.st.stm32cube.ide.mcu.debug.option.cpuclock.808710097" superClass="com.st.stm32cube.ide.mcu.debug.option.cpuclock" value="100" valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.debug.option.cpuclock.808710097" superClass="com.st.stm32cube.ide.mcu.debug.option.cpuclock" useByScannerDiscovery="false" value="100" valueType="string"/>
 							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform.490691857" isAbstract="false" osList="all" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform"/>
 							<builder buildPath="${workspace_loc:/ECU}/Debug" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder.1096357141" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder"/>
 							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.796568143" name="MCU GCC Assembler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler">
diff --git a/Core/Inc/util/global_definitions.h b/Core/Inc/util/global_definitions.h
index e2cc3dcd..658b02d7 100644
--- a/Core/Inc/util/global_definitions.h
+++ b/Core/Inc/util/global_definitions.h
@@ -119,7 +119,7 @@ typedef enum {
 #define GENERAL_BUS_OFF_ERROR_FLAG (1 << 1)
 #define INVERTER_READY_FLAG        (1 << 2)
 #define DYNAMIC_CONTROL_FLAG       (1 << 3)
-#define CROSS_VALIDATION_THREAD_FLAG  (1 << 4) //refatora e tira o 'thread'
+#define CROSS_VALIDATION_FLAG  	   (1 << 4)
 
 // Warning flags	(No actions necessary)
 #define REGEN_WARN_FLAG           (1 << 10)
diff --git a/Core/Src/driver_settings/dynamic_controls_choice.c b/Core/Src/driver_settings/dynamic_controls_choice.c
index a15f5d67..8090a1ea 100644
--- a/Core/Src/driver_settings/dynamic_controls_choice.c
+++ b/Core/Src/driver_settings/dynamic_controls_choice.c
@@ -34,7 +34,7 @@ void dynamic_controls_choice(void* argument) {
 
         if (!is_DYNAMIC_CONTROL_active) {
             osEventFlagsSet(e_ECU_control_flagsHandle, DYNAMIC_CONTROL_FLAG);
-            osEventFlagsClear(e_ECU_control_flagsHandle, CROSS_VALIDATION_THREAD_FLAG);
+            osEventFlagsClear(e_ECU_control_flagsHandle, CROSS_VALIDATION_FLAG);
         } else {
             osEventFlagsClear(e_ECU_control_flagsHandle, DYNAMIC_CONTROL_FLAG);
         }
diff --git a/Core/Src/dynamic_controls/security_architecture.c b/Core/Src/dynamic_controls/security_architecture.c
index d77f23b6..5fb0753d 100644
--- a/Core/Src/dynamic_controls/security_architecture.c
+++ b/Core/Src/dynamic_controls/security_architecture.c
@@ -46,8 +46,8 @@ void cross_validation(void* argument) {
             osTimerStop(tim_cross_validation_errorHandle);
         }
         cross_validation_status_datalog();
+        osDelay(CROSS_VALIDATION_DELAY);
     }
-    osDelay(CROSS_VALIDATION_DELAY);
 }
 
 bool is_there_imu_bse_error() {
@@ -66,7 +66,7 @@ bool is_there_imu_speed_error() {
 }
 
 void cross_validation_error_callback() {
-    osEventFlagsSet(e_ECU_control_flagsHandle, CROSS_VALIDATION_THREAD_FLAG);
+    osEventFlagsSet(e_ECU_control_flagsHandle, CROSS_VALIDATION_FLAG);
 }
 
 void cross_validation_status_datalog() {
diff --git a/Core/Src/main.c b/Core/Src/main.c
index 46b1145d..1b5a7627 100644
--- a/Core/Src/main.c
+++ b/Core/Src/main.c
@@ -217,9 +217,16 @@ const osThreadAttr_t t_odometer_save_attributes = {
 /* Definitions for t_dynamic_controls_choice */
 osThreadId_t t_dynamic_controls_choiceHandle;
 const osThreadAttr_t t_dynamic_controls_choice_attributes = {
-    .name       = "t_dynamic_controls_choice",
-    .stack_size = 1024 * 4,
-    .priority   = (osPriority_t)osPriorityLow,
+  .name = "t_dynamic_controls_choice",
+  .stack_size = 1024 * 4,
+  .priority = (osPriority_t) osPriorityLow,
+};
+/* Definitions for t_cross_validation */
+osThreadId_t t_cross_validationHandle;
+const osThreadAttr_t t_cross_validation_attributes = {
+  .name = "t_cross_validation",
+  .stack_size = 1024 * 4,
+  .priority = (osPriority_t) osPriorityLow,
 };
 /* Definitions for q_encoder_int_message */
 osMessageQueueId_t q_encoder_int_messageHandle;
@@ -306,6 +313,11 @@ osTimerId_t tim_right_inv_errorHandle;
 const osTimerAttr_t tim_right_inv_error_attributes = {
   .name = "tim_right_inv_error"
 };
+/* Definitions for tim_cross_validation_error */
+osTimerId_t tim_cross_validation_errorHandle;
+const osTimerAttr_t tim_cross_validation_error_attributes = {
+  .name = "tim_cross_validation_error"
+};
 /* Definitions for m_state_parameter_mutex */
 osMutexId_t m_state_parameter_mutexHandle;
 const osMutexAttr_t m_state_parameter_mutex_attributes = {
@@ -354,11 +366,13 @@ extern void buttons_handler(void *argument);
 extern void speed_datalog(void *argument);
 extern void odometer_save(void *argument);
 extern void dynamic_controls_choice(void *argument);
+extern void cross_validation(void *argument);
 extern void errors_with_timer_callback(void *argument);
 extern void inverter_BUS_OFF_error_callback(void *argument);
 extern void inverter_ready_callback(void *argument);
 extern void left_inv_error_callback(void *argument);
 extern void right_inv_error_callback(void *argument);
+extern void cross_validation_error_callback(void *argument);
 
 /* USER CODE BEGIN PFP */
 
@@ -446,6 +460,9 @@ int main(void)
   /* creation of tim_right_inv_error */
   tim_right_inv_errorHandle = osTimerNew(right_inv_error_callback, osTimerPeriodic, (void*) RIGHT_INVERTER_COMM_ERROR_FLAG, &tim_right_inv_error_attributes);
 
+  /* creation of tim_cross_validation_error */
+  tim_cross_validation_errorHandle = osTimerNew(cross_validation_error_callback, osTimerPeriodic, (void*) CROSS_VALIDATION_FLAG, &tim_cross_validation_error_attributes);
+
   /* USER CODE BEGIN RTOS_TIMERS */
   /* start timers, add new ones, ... */
   /* USER CODE END RTOS_TIMERS */
@@ -552,6 +569,9 @@ int main(void)
   /* creation of t_dynamic_controls_choice */
   t_dynamic_controls_choiceHandle = osThreadNew(dynamic_controls_choice, NULL, &t_dynamic_controls_choice_attributes);
 
+  /* creation of t_cross_validation */
+  t_cross_validationHandle = osThreadNew(cross_validation, NULL, &t_cross_validation_attributes);
+
   /* USER CODE BEGIN RTOS_THREADS */
   /* add threads, ... */
   /* USER CODE END RTOS_THREADS */
@@ -1197,7 +1217,6 @@ static void MX_GPIO_Init(void)
 /* USER CODE END Header_main_task */
 __weak void main_task(void *argument)
 {
-  UNUSED(argument);
   /* USER CODE BEGIN 5 */
   /* Infinite loop */
   for(;;)
diff --git a/Core/Src/torque_command/torque_manager.c b/Core/Src/torque_command/torque_manager.c
index ad6f38ee..9081761f 100644
--- a/Core/Src/torque_command/torque_manager.c
+++ b/Core/Src/torque_command/torque_manager.c
@@ -38,7 +38,7 @@ void torque_manager(void* argument) {
             get_individual_flag(e_ECU_control_flagsHandle, DYNAMIC_CONTROL_FLAG);
             get_individual_flag(e_ECU_control_flagsHandle, DYNAMIC_CONTROL_FLAG);
         const bool is_there_CROSS_VALIDATION_error =
-            get_individual_flag(e_ECU_control_flagsHandle, CROSS_VALIDATION_THREAD_FLAG);
+            get_individual_flag(e_ECU_control_flagsHandle, CROSS_VALIDATION_FLAG);
 
         select_dynamic_control(is_DYNAMIC_CONTROL_active,
                                is_there_CROSS_VALIDATION_error);

From 41fc941113cb905978efb48cab5840ff73dc2847 Mon Sep 17 00:00:00 2001
From: caiussouza <caiuscsouza@gmail.com>
Date: Mon, 3 Apr 2023 17:33:05 -0300
Subject: [PATCH 27/33] clang format

---
 .../dynamic_controls/security_architecture.h  |  1 +
 Core/Inc/util/global_definitions.h            |  2 +-
 .../driver_settings/dynamic_controls_choice.c |  2 +-
 Core/Src/main.c                               | 27 +++----------------
 Core/Src/torque_command/torque_manager.c      |  2 +-
 5 files changed, 8 insertions(+), 26 deletions(-)

diff --git a/Core/Inc/dynamic_controls/security_architecture.h b/Core/Inc/dynamic_controls/security_architecture.h
index 49643afc..29899dd4 100644
--- a/Core/Inc/dynamic_controls/security_architecture.h
+++ b/Core/Inc/dynamic_controls/security_architecture.h
@@ -17,6 +17,7 @@
 #define NULL_SPEED_MARGIN_ERROR     1
 
 #define CROSS_VALIDATION_ERROR_TIME 1
+#define CROSS_VALIDATION_DELAY      1
 
 bool is_there_imu_bse_error();
 bool is_there_imu_speed_error();
diff --git a/Core/Inc/util/global_definitions.h b/Core/Inc/util/global_definitions.h
index 658b02d7..5bf15bcd 100644
--- a/Core/Inc/util/global_definitions.h
+++ b/Core/Inc/util/global_definitions.h
@@ -119,7 +119,7 @@ typedef enum {
 #define GENERAL_BUS_OFF_ERROR_FLAG (1 << 1)
 #define INVERTER_READY_FLAG        (1 << 2)
 #define DYNAMIC_CONTROL_FLAG       (1 << 3)
-#define CROSS_VALIDATION_FLAG  	   (1 << 4)
+#define CROSS_VALIDATION_FLAG      (1 << 4)
 
 // Warning flags	(No actions necessary)
 #define REGEN_WARN_FLAG           (1 << 10)
diff --git a/Core/Src/driver_settings/dynamic_controls_choice.c b/Core/Src/driver_settings/dynamic_controls_choice.c
index 8090a1ea..67525156 100644
--- a/Core/Src/driver_settings/dynamic_controls_choice.c
+++ b/Core/Src/driver_settings/dynamic_controls_choice.c
@@ -30,7 +30,7 @@ void dynamic_controls_choice(void* argument) {
         }
         const bool is_DYNAMIC_CONTROL_active =
             get_individual_flag(e_ECU_control_flagsHandle, DYNAMIC_CONTROL_FLAG);
-            get_individual_flag(e_ECU_control_flagsHandle, DYNAMIC_CONTROL_FLAG);
+        get_individual_flag(e_ECU_control_flagsHandle, DYNAMIC_CONTROL_FLAG);
 
         if (!is_DYNAMIC_CONTROL_active) {
             osEventFlagsSet(e_ECU_control_flagsHandle, DYNAMIC_CONTROL_FLAG);
diff --git a/Core/Src/main.c b/Core/Src/main.c
index 1b5a7627..46b1145d 100644
--- a/Core/Src/main.c
+++ b/Core/Src/main.c
@@ -217,16 +217,9 @@ const osThreadAttr_t t_odometer_save_attributes = {
 /* Definitions for t_dynamic_controls_choice */
 osThreadId_t t_dynamic_controls_choiceHandle;
 const osThreadAttr_t t_dynamic_controls_choice_attributes = {
-  .name = "t_dynamic_controls_choice",
-  .stack_size = 1024 * 4,
-  .priority = (osPriority_t) osPriorityLow,
-};
-/* Definitions for t_cross_validation */
-osThreadId_t t_cross_validationHandle;
-const osThreadAttr_t t_cross_validation_attributes = {
-  .name = "t_cross_validation",
-  .stack_size = 1024 * 4,
-  .priority = (osPriority_t) osPriorityLow,
+    .name       = "t_dynamic_controls_choice",
+    .stack_size = 1024 * 4,
+    .priority   = (osPriority_t)osPriorityLow,
 };
 /* Definitions for q_encoder_int_message */
 osMessageQueueId_t q_encoder_int_messageHandle;
@@ -313,11 +306,6 @@ osTimerId_t tim_right_inv_errorHandle;
 const osTimerAttr_t tim_right_inv_error_attributes = {
   .name = "tim_right_inv_error"
 };
-/* Definitions for tim_cross_validation_error */
-osTimerId_t tim_cross_validation_errorHandle;
-const osTimerAttr_t tim_cross_validation_error_attributes = {
-  .name = "tim_cross_validation_error"
-};
 /* Definitions for m_state_parameter_mutex */
 osMutexId_t m_state_parameter_mutexHandle;
 const osMutexAttr_t m_state_parameter_mutex_attributes = {
@@ -366,13 +354,11 @@ extern void buttons_handler(void *argument);
 extern void speed_datalog(void *argument);
 extern void odometer_save(void *argument);
 extern void dynamic_controls_choice(void *argument);
-extern void cross_validation(void *argument);
 extern void errors_with_timer_callback(void *argument);
 extern void inverter_BUS_OFF_error_callback(void *argument);
 extern void inverter_ready_callback(void *argument);
 extern void left_inv_error_callback(void *argument);
 extern void right_inv_error_callback(void *argument);
-extern void cross_validation_error_callback(void *argument);
 
 /* USER CODE BEGIN PFP */
 
@@ -460,9 +446,6 @@ int main(void)
   /* creation of tim_right_inv_error */
   tim_right_inv_errorHandle = osTimerNew(right_inv_error_callback, osTimerPeriodic, (void*) RIGHT_INVERTER_COMM_ERROR_FLAG, &tim_right_inv_error_attributes);
 
-  /* creation of tim_cross_validation_error */
-  tim_cross_validation_errorHandle = osTimerNew(cross_validation_error_callback, osTimerPeriodic, (void*) CROSS_VALIDATION_FLAG, &tim_cross_validation_error_attributes);
-
   /* USER CODE BEGIN RTOS_TIMERS */
   /* start timers, add new ones, ... */
   /* USER CODE END RTOS_TIMERS */
@@ -569,9 +552,6 @@ int main(void)
   /* creation of t_dynamic_controls_choice */
   t_dynamic_controls_choiceHandle = osThreadNew(dynamic_controls_choice, NULL, &t_dynamic_controls_choice_attributes);
 
-  /* creation of t_cross_validation */
-  t_cross_validationHandle = osThreadNew(cross_validation, NULL, &t_cross_validation_attributes);
-
   /* USER CODE BEGIN RTOS_THREADS */
   /* add threads, ... */
   /* USER CODE END RTOS_THREADS */
@@ -1217,6 +1197,7 @@ static void MX_GPIO_Init(void)
 /* USER CODE END Header_main_task */
 __weak void main_task(void *argument)
 {
+  UNUSED(argument);
   /* USER CODE BEGIN 5 */
   /* Infinite loop */
   for(;;)
diff --git a/Core/Src/torque_command/torque_manager.c b/Core/Src/torque_command/torque_manager.c
index 9081761f..3849c095 100644
--- a/Core/Src/torque_command/torque_manager.c
+++ b/Core/Src/torque_command/torque_manager.c
@@ -36,7 +36,7 @@ void torque_manager(void* argument) {
 
         const bool is_DYNAMIC_CONTROL_active =
             get_individual_flag(e_ECU_control_flagsHandle, DYNAMIC_CONTROL_FLAG);
-            get_individual_flag(e_ECU_control_flagsHandle, DYNAMIC_CONTROL_FLAG);
+        get_individual_flag(e_ECU_control_flagsHandle, DYNAMIC_CONTROL_FLAG);
         const bool is_there_CROSS_VALIDATION_error =
             get_individual_flag(e_ECU_control_flagsHandle, CROSS_VALIDATION_FLAG);
 

From f18bf21f37ffae3aa03e8e685dbeccf4daa48f65 Mon Sep 17 00:00:00 2001
From: caiussouza <caiuscsouza@gmail.com>
Date: Tue, 4 Apr 2023 11:23:41 -0300
Subject: [PATCH 28/33] .ioc fixing

---
 Core/Src/main.c | 27 +++++++++++++++++++++++----
 1 file changed, 23 insertions(+), 4 deletions(-)

diff --git a/Core/Src/main.c b/Core/Src/main.c
index 46b1145d..e2d61d4c 100644
--- a/Core/Src/main.c
+++ b/Core/Src/main.c
@@ -217,9 +217,16 @@ const osThreadAttr_t t_odometer_save_attributes = {
 /* Definitions for t_dynamic_controls_choice */
 osThreadId_t t_dynamic_controls_choiceHandle;
 const osThreadAttr_t t_dynamic_controls_choice_attributes = {
-    .name       = "t_dynamic_controls_choice",
-    .stack_size = 1024 * 4,
-    .priority   = (osPriority_t)osPriorityLow,
+  .name = "t_dynamic_controls_choice",
+  .stack_size = 1024 * 4,
+  .priority = (osPriority_t) osPriorityLow,
+};
+/* Definitions for t_cross_validation */
+osThreadId_t t_cross_validationHandle;
+const osThreadAttr_t t_cross_validation_attributes = {
+  .name = "t_cross_validation",
+  .stack_size = 1024 * 4,
+  .priority = (osPriority_t) osPriorityLow,
 };
 /* Definitions for q_encoder_int_message */
 osMessageQueueId_t q_encoder_int_messageHandle;
@@ -306,6 +313,11 @@ osTimerId_t tim_right_inv_errorHandle;
 const osTimerAttr_t tim_right_inv_error_attributes = {
   .name = "tim_right_inv_error"
 };
+/* Definitions for tim_cross_validation_error */
+osTimerId_t tim_cross_validation_errorHandle;
+const osTimerAttr_t tim_cross_validation_error_attributes = {
+  .name = "tim_cross_validation_error"
+};
 /* Definitions for m_state_parameter_mutex */
 osMutexId_t m_state_parameter_mutexHandle;
 const osMutexAttr_t m_state_parameter_mutex_attributes = {
@@ -354,11 +366,13 @@ extern void buttons_handler(void *argument);
 extern void speed_datalog(void *argument);
 extern void odometer_save(void *argument);
 extern void dynamic_controls_choice(void *argument);
+extern void cross_validation(void *argument);
 extern void errors_with_timer_callback(void *argument);
 extern void inverter_BUS_OFF_error_callback(void *argument);
 extern void inverter_ready_callback(void *argument);
 extern void left_inv_error_callback(void *argument);
 extern void right_inv_error_callback(void *argument);
+extern void cross_validation_error_callback(void *argument);
 
 /* USER CODE BEGIN PFP */
 
@@ -446,6 +460,9 @@ int main(void)
   /* creation of tim_right_inv_error */
   tim_right_inv_errorHandle = osTimerNew(right_inv_error_callback, osTimerPeriodic, (void*) RIGHT_INVERTER_COMM_ERROR_FLAG, &tim_right_inv_error_attributes);
 
+  /* creation of tim_cross_validation_error */
+  tim_cross_validation_errorHandle = osTimerNew(cross_validation_error_callback, osTimerPeriodic, (void*) CROSS_VALIDATION_THREAD_FLAG, &tim_cross_validation_error_attributes);
+
   /* USER CODE BEGIN RTOS_TIMERS */
   /* start timers, add new ones, ... */
   /* USER CODE END RTOS_TIMERS */
@@ -552,6 +569,9 @@ int main(void)
   /* creation of t_dynamic_controls_choice */
   t_dynamic_controls_choiceHandle = osThreadNew(dynamic_controls_choice, NULL, &t_dynamic_controls_choice_attributes);
 
+  /* creation of t_cross_validation */
+  t_cross_validationHandle = osThreadNew(cross_validation, NULL, &t_cross_validation_attributes);
+
   /* USER CODE BEGIN RTOS_THREADS */
   /* add threads, ... */
   /* USER CODE END RTOS_THREADS */
@@ -1197,7 +1217,6 @@ static void MX_GPIO_Init(void)
 /* USER CODE END Header_main_task */
 __weak void main_task(void *argument)
 {
-  UNUSED(argument);
   /* USER CODE BEGIN 5 */
   /* Infinite loop */
   for(;;)

From 0defa6f4a59adb4a217881b28e873cbb912804eb Mon Sep 17 00:00:00 2001
From: caiussouza <caiuscsouza@gmail.com>
Date: Tue, 4 Apr 2023 11:27:35 -0300
Subject: [PATCH 29/33] variable name refactor on ioc

---
 Core/Src/main.c | 2 +-
 ECU.ioc         | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/Core/Src/main.c b/Core/Src/main.c
index e2d61d4c..1b5a7627 100644
--- a/Core/Src/main.c
+++ b/Core/Src/main.c
@@ -461,7 +461,7 @@ int main(void)
   tim_right_inv_errorHandle = osTimerNew(right_inv_error_callback, osTimerPeriodic, (void*) RIGHT_INVERTER_COMM_ERROR_FLAG, &tim_right_inv_error_attributes);
 
   /* creation of tim_cross_validation_error */
-  tim_cross_validation_errorHandle = osTimerNew(cross_validation_error_callback, osTimerPeriodic, (void*) CROSS_VALIDATION_THREAD_FLAG, &tim_cross_validation_error_attributes);
+  tim_cross_validation_errorHandle = osTimerNew(cross_validation_error_callback, osTimerPeriodic, (void*) CROSS_VALIDATION_FLAG, &tim_cross_validation_error_attributes);
 
   /* USER CODE BEGIN RTOS_TIMERS */
   /* start timers, add new ones, ... */
diff --git a/ECU.ioc b/ECU.ioc
index 4e79b7bd..577d9207 100644
--- a/ECU.ioc
+++ b/ECU.ioc
@@ -97,7 +97,7 @@ FREERTOS.IPParameters=Tasks01,configMINIMAL_STACK_SIZE,FootprintOK,Queues01,conf
 FREERTOS.Mutexes01=m_state_parameter_mutex,Dynamic,NULL
 FREERTOS.Queues01=q_encoder_int_message,16,encoder_int_message_t,0,Dynamic,NULL,NULL;q_torque_message,16,torque_message_t,0,Dynamic,NULL,NULL;q_ref_torque_message,16,ref_torque_t,0,Dynamic,NULL,NULL;q_datalog_message,128,datalog_message_t,0,Dynamic,NULL,NULL;q_debug_leds_message,16,debug_led_message_t,0,Dynamic,NULL,NULL;q_rgb_led_message,16,rgb_led_message_t,0,Dynamic,NULL,NULL;q_throttle_control,16,uint16_t,0,Dynamic,NULL,NULL;q_encoder_speeds_message,1,encoder_speeds_message_t,0,Dynamic,NULL,NULL;q_odometer_calc_save_message,1,odometer_message_t,0,Dynamic,NULL,NULL;q_ids_can_inverter,32,uint32_t,0,Dynamic,NULL,NULL
 FREERTOS.Tasks01=t_main_task,24,1024,main_task,As weak,NULL,Dynamic,NULL,NULL;t_torque_parameters,8,1024,torque_parameters,As external,NULL,Dynamic,NULL,NULL;t_datalogger,8,1024,datalogger,As external,NULL,Dynamic,NULL,NULL;t_APPS_read,8,1024,APPS_read,As external,NULL,Dynamic,NULL,NULL;t_steering_read,8,1024,steering_read,As external,NULL,Dynamic,NULL,NULL;t_encoder_speed_calc,8,1024,encoder_speed_calc,As external,NULL,Dynamic,NULL,NULL;t_odometer_calc,8,1024,odometer_calc,As external,NULL,Dynamic,NULL,NULL;t_torque_message,8,1024,torque_message,As external,NULL,Dynamic,NULL,NULL;t_torque_manager,8,1024,torque_manager,As external,NULL,Dynamic,NULL,NULL;t_debug_leds,8,1024,debug_leds,As external,NULL,Dynamic,NULL,NULL;t_rgb_led,8,1024,rgb_led,As external,NULL,Dynamic,NULL,NULL;t_seleciona_modo,8,1024,seleciona_modo,As external,NULL,Dynamic,NULL,NULL;t_RTD,8,1024,RTD,As external,NULL,Dynamic,NULL,NULL;t_throttle_control,8,1024,throttle_control,As external,NULL,Dynamic,NULL,NULL;t_datalog_acquisition,8,1024,datalog_acquisition,As external,NULL,Dynamic,NULL,NULL;t_inverter_comm_error,8,1024,inverter_comm_error,As external,NULL,Dynamic,NULL,NULL;t_inverter_datalog,8,1024,inverter_datalog,As external,NULL,Dynamic,NULL,NULL;t_pilot_reset,8,1024,pilot_reset,As external,NULL,Dynamic,NULL,NULL;t_buttons_handler,8,1024,buttons_handler,As external,NULL,Dynamic,NULL,NULL;t_speed_datalog,8,1024,speed_datalog,As external,NULL,Dynamic,NULL,NULL;t_odometer_save,8,1024,odometer_save,As external,NULL,Dynamic,NULL,NULL;t_dynamic_controls_choice,8,1024,dynamic_controls_choice,As external,NULL,Dynamic,NULL,NULL;t_cross_validation,8,1024,cross_validation,As external,NULL,Dynamic,NULL,NULL
-FREERTOS.Timers01=tim_SU_F_error,errors_with_timer_callback,osTimerOnce,As external,SU_F_ERROR_FLAG,Dynamic,NULL;tim_APPS_error,errors_with_timer_callback,osTimerOnce,As external,APPS_ERROR_FLAG,Dynamic,NULL;tim_inverter_BUS_OFF_error,inverter_BUS_OFF_error_callback,osTimerOnce,As external,NULL,Dynamic,NULL;tim_inverter_ready,inverter_ready_callback,osTimerOnce,As external,NULL,Dynamic,NULL;tim_inverter_can_transmit_error,errors_with_timer_callback,osTimerOnce,As external,INVERTER_CAN_TRANSMIT_ERROR_FLAG,Dynamic,NULL;tim_left_inv_error,left_inv_error_callback,osTimerPeriodic,As external,LEFT_INVERTER_COMM_ERROR_FLAG,Dynamic,NULL;tim_right_inv_error,right_inv_error_callback,osTimerPeriodic,As external,RIGHT_INVERTER_COMM_ERROR_FLAG,Dynamic,NULL;tim_cross_validation_error,cross_validation_error_callback,osTimerPeriodic,As external,CROSS_VALIDATION_THREAD_FLAG,Dynamic,NULL
+FREERTOS.Timers01=tim_SU_F_error,errors_with_timer_callback,osTimerOnce,As external,SU_F_ERROR_FLAG,Dynamic,NULL;tim_APPS_error,errors_with_timer_callback,osTimerOnce,As external,APPS_ERROR_FLAG,Dynamic,NULL;tim_inverter_BUS_OFF_error,inverter_BUS_OFF_error_callback,osTimerOnce,As external,NULL,Dynamic,NULL;tim_inverter_ready,inverter_ready_callback,osTimerOnce,As external,NULL,Dynamic,NULL;tim_inverter_can_transmit_error,errors_with_timer_callback,osTimerOnce,As external,INVERTER_CAN_TRANSMIT_ERROR_FLAG,Dynamic,NULL;tim_left_inv_error,left_inv_error_callback,osTimerPeriodic,As external,LEFT_INVERTER_COMM_ERROR_FLAG,Dynamic,NULL;tim_right_inv_error,right_inv_error_callback,osTimerPeriodic,As external,RIGHT_INVERTER_COMM_ERROR_FLAG,Dynamic,NULL;tim_cross_validation_error,cross_validation_error_callback,osTimerPeriodic,As external,CROSS_VALIDATION_FLAG,Dynamic,NULL
 FREERTOS.configCHECK_FOR_STACK_OVERFLOW=2
 FREERTOS.configENABLE_FPU=1
 FREERTOS.configMAX_TASK_NAME_LEN=32

From d76d67b8414e62bb783bee3fd3d1de7d4cf24929 Mon Sep 17 00:00:00 2001
From: caiussouza <caiuscsouza@gmail.com>
Date: Tue, 4 Apr 2023 11:37:36 -0300
Subject: [PATCH 30/33] now the task works for all the time the car is active

---
 Core/Src/driver_settings/dynamic_controls_choice.c | 1 -
 Core/Src/dynamic_controls/security_architecture.c  | 2 --
 2 files changed, 3 deletions(-)

diff --git a/Core/Src/driver_settings/dynamic_controls_choice.c b/Core/Src/driver_settings/dynamic_controls_choice.c
index 67525156..7f045b23 100644
--- a/Core/Src/driver_settings/dynamic_controls_choice.c
+++ b/Core/Src/driver_settings/dynamic_controls_choice.c
@@ -30,7 +30,6 @@ void dynamic_controls_choice(void* argument) {
         }
         const bool is_DYNAMIC_CONTROL_active =
             get_individual_flag(e_ECU_control_flagsHandle, DYNAMIC_CONTROL_FLAG);
-        get_individual_flag(e_ECU_control_flagsHandle, DYNAMIC_CONTROL_FLAG);
 
         if (!is_DYNAMIC_CONTROL_active) {
             osEventFlagsSet(e_ECU_control_flagsHandle, DYNAMIC_CONTROL_FLAG);
diff --git a/Core/Src/dynamic_controls/security_architecture.c b/Core/Src/dynamic_controls/security_architecture.c
index 5fb0753d..685250cb 100644
--- a/Core/Src/dynamic_controls/security_architecture.c
+++ b/Core/Src/dynamic_controls/security_architecture.c
@@ -26,8 +26,6 @@ void cross_validation(void* argument) {
     for (;;) {
         ECU_ENABLE_BREAKPOINT_DEBUG();
 
-        osThreadFlagsWait(DYNAMIC_CONTROL_FLAG, osFlagsNoClear, osWaitForever);
-
         float IMU_long_accel_data = (float)general_get_value(accelerometer_z);
         float speed_data          = (float)get_global_var_value(REAR_AVG_SPEED);
         bse_active                = get_global_var_value(BRAKE_STATUS);

From ff6bc57e4bd57f35963697a3c71d1a614c3a5083 Mon Sep 17 00:00:00 2001
From: caiussouza <caiuscsouza@gmail.com>
Date: Thu, 20 Apr 2023 12:05:00 -0300
Subject: [PATCH 31/33] atualizando ids de can

---
 Core/Inc/CAN/CAN_IDs.h | 242 +++++++++++++++++++++++------------------
 Core/Src/CAN/CAN_IDs.c |  99 +++++++++--------
 2 files changed, 191 insertions(+), 150 deletions(-)

diff --git a/Core/Inc/CAN/CAN_IDs.h b/Core/Inc/CAN/CAN_IDs.h
index 54432fdd..7b00b4e1 100644
--- a/Core/Inc/CAN/CAN_IDs.h
+++ b/Core/Inc/CAN/CAN_IDs.h
@@ -20,63 +20,73 @@
 // DATALOGGER
 // LEGENDA:  LABEL    	    	 INTERNAL_ID
 // 0 E RESERVADO PARA LACUNAS NO PACOTE
-#define ID_ECU_TIMER            1
+#define ID_SPEED_AVG            1
 #define ID_STEERING_WHEEL       2
 #define ID_THROTTLE             3
 #define ID_BRAKE                4
 #define ID_MODE                 5
-#define ID_DISTANCE_P_ODOM      6
-#define ID_DISTANCE_T_ODOM      7
-#define ID_TORQUE_R_MOTOR       8
-#define ID_TORQUE_L_MOTOR       9
-#define ID_REF_TORQUE_R_MOTOR   10
-#define ID_REF_TORQUE_L_MOTOR   11
-#define ID_REF_SPEED_R          12
-#define ID_REF_SPEED_L          13
-#define ID_CONTROL_EVENT_FLAG_1 14
-#define ID_CONTROL_EVENT_FLAG_2 15
-#define ID_SPEED_FL             16
-#define ID_SPEED_FR             17
-#define ID_SPEED_RR             18
-#define ID_SPEED_RL             19
-#define ID_TORQUE_GAIN          20
-#define ID_CURRENT_R_MOTOR      21
-#define ID_CURRENT_L_MOTOR      22
-#define ID_TEMPERATURE1_R       23
-#define ID_TEMPERATURE2_R       24
-#define ID_TEMPERATURE1_L       25
-#define ID_TEMPERATURE2_L       26
-#define ID_IMU_BSE_ERROR        27
-#define ID_STATUS_DATALOG       28
-#define ID_IMU_SPEED_ERROR      29
-#define ID_CURRENT_FLAG         30
-#define ID_PANEL_DEBUG_1        31
-#define ID_PANEL_DEBUG_2        32
-#define ID_PANEL_DEBUG_3        33
-#define ID_PANEL_DEBUG_4        34
-#define ID_REGEN_BRAKE_STATE    35
-#define ID_SPEED_L_MOTOR        36
-#define ID_SPEED_R_MOTOR        37
-#define ID_POWER_L_MOTOR        38
-#define ID_POWER_R_MOTOR        39
-#define ID_ENERGY_L_MOTOR       40
-#define ID_ENERGY_R_MOTOR       41
-#define ID_OVERLOAD_L_MOTOR     42
-#define ID_OVERLOAD_R_MOTOR     43
-#define ID_LOST_MSG_L_MOTOR     44
-#define ID_LOST_MSG_R_MOTOR     45
-#define ID_BUS_OFF_L_MOTOR      46
-#define ID_BUS_OFF_R_MOTOR      47
-#define ID_CAN_STATE_L_MOTOR    48
-#define ID_CAN_STATE_R_MOTOR    49
-#define ID_INV_STATE_L_MOTOR    50
-#define ID_INV_STATE_R_MOTOR    51
-#define ID_FAILURE_L_MOTOR      52
-#define ID_FAILURE_R_MOTOR      53
-#define ID_ALARM_L_MOTOR        54
-#define ID_ALARM_R_MOTOR        55
+#define ID_TORQUE_GAIN          6
+#define ID_DISTANCE_P_ODOM      7
+#define ID_DISTANCE_T_ODOM      8
+#define ID_CONTROL_EVENT_FLAG_1 9
+#define ID_CONTROL_EVENT_FLAG_2 10
+#define ID_REF_TORQUE_R_MOTOR   11
+#define ID_REF_TORQUE_L_MOTOR   12
+#define ID_SPEED_FL             13
+#define ID_SPEED_FR             14
+#define ID_SPEED_RL             15
+#define ID_SPEED_RR             16
+// #define /*RED_TORQUE_ROD_ESQ */ 17
+// #define /*RED_TORQUE_ROD_DIR */ 18
+// #define /*EXTRA_CONTROL_DIN  */ 19
+// #define /*EXTRA_CONTROL_DIN  */ 20
+#define ID_REGEN_BRAKE_STATE    21
+#define ID_IMU_BSE_ERROR        22
+#define ID_STATUS_DATALOG       23
+#define ID_IMU_SPEED_ERROR      24
+#define ID_CURRENT_FLAG         25
+#define ID_PANEL_DEBUG_1        26
+#define ID_PANEL_DEBUG_2        27
+#define ID_PANEL_DEBUG_3        28
+#define ID_PANEL_DEBUG_4        29
+#define ID_SPEED_L_MOTOR        30
+#define ID_TORQUE_L_MOTOR       31
+#define ID_POWER_L_MOTOR        32
+#define ID_CURRENT_L_MOTOR      33
+#define ID_ENERGY_L_MOTOR       34
+#define ID_OVERLOAD_L_MOTOR     35
+#define ID_TEMPERATURE1_L       36
+#define ID_TEMPERATURE2_L       37
+#define ID_LOST_MSG_L_MOTOR     38
+#define ID_BUS_OFF_L_MOTOR      39
+#define ID_CAN_STATE_L_MOTOR    40
+#define ID_INV_STATE_L_MOTOR    41
+#define ID_FAILURE_L_MOTOR      42
+#define ID_ALARM_L_MOTOR        43
+#define ID_SPEED_R_MOTOR        44
+#define ID_TORQUE_R_MOTOR       45
+#define ID_POWER_R_MOTOR        46
+#define ID_CURRENT_R_MOTOR      47
+#define ID_ENERGY_R_MOTOR       48
+#define ID_OVERLOAD_R_MOTOR     49
+#define ID_TEMPERATURE1_R       50
+#define ID_TEMPERATURE2_R       51
+#define ID_LOST_MSG_R_MOTOR     52
+#define ID_BUS_OFF_R_MOTOR      53
+#define ID_CAN_STATE_R_MOTOR    54
+#define ID_INV_STATE_R_MOTOR    55
+#define ID_FAILURE_R_MOTOR      56
+#define ID_ALARM_R_MOTOR        57
+// #define /*ACCEL X*/ 58
+// #define /*ACCEL Y*/ 59
+// #define /*ACCEL Z*/ 60
+// #define /*TEMP IMU*/ 61
+// #define /*GYRO X*/ 62
+// #define /*GYRO Y*/ 63
+// #define /*GYRO Z*/ 64
+// #define /*IMU ERROR*/ 65
 
-#define CAN_ID_QUAN 56
+#define CAN_ID_QUAN 65
 
 typedef struct {
     uint16_t id;
@@ -87,11 +97,11 @@ extern CAN_ID_t CAN_ID_map[CAN_ID_QUAN];
 // TODO(renanmoreira): IMPLEMENT X-MACROS FOR CAN_ID'S
 #define ECU_CAN_INITIAL_ID        100
 #define ECU_CAN_FINAL_ID          149
-#define ECU_CAN_LAST_POPULATED_ID 113
+#define ECU_CAN_LAST_POPULATED_ID 131
 #define ECU_CAN_FIRST_DEBUG_ID    351
 #define ECU_CAN_LAST_DEBUG_ID     351
 
-#define INTERNAL_ID_ECU_TIMER                                                            \
+#define INTERNAL_ID_SPEED_AVG                                                            \
     { 101, 0 }
 #define INTERNAL_ID_STEERING_WHEEL                                                       \
     { 101, 1 }
@@ -101,48 +111,38 @@ extern CAN_ID_t CAN_ID_map[CAN_ID_QUAN];
     { 101, 3 }
 #define INTERNAL_ID_MODE                                                                 \
     { 102, 0 }
+#define INTERNAL_ID_TORQUE_GAIN                                                          \
+    { 102, 1 }
 #define INTERNAL_ID_DISTANCE_P_ODOM                                                      \
     { 102, 2 }
 #define INTERNAL_ID_DISTANCE_T_ODOM                                                      \
     { 102, 3 }
-#define INTERNAL_ID_TORQUE_R_MOTOR                                                       \
+#define INTERNAL_ID_CONTROL_EVENT_FLAG_1                                                 \
     { 103, 0 }
-#define INTERNAL_ID_TORQUE_L_MOTOR                                                       \
+#define INTERNAL_ID_CONTROL_EVENT_FLAG_2                                                 \
     { 103, 1 }
 #define INTERNAL_ID_REF_TORQUE_R_MOTOR                                                   \
     { 103, 2 }
 #define INTERNAL_ID_REF_TORQUE_L_MOTOR                                                   \
     { 103, 3 }
-#define INTERNAL_ID_REF_SPEED_R_MOTOR                                                    \
+#define INTERNAL_ID_SPEED_FL                                                             \
     { 104, 0 }
-#define INTERNAL_ID_REF_SPEED_L_MOTOR                                                    \
+#define INTERNAL_ID_SPEED_FR                                                             \
     { 104, 1 }
-#define INTERNAL_ID_CONTROL_EVENT_FLAG_1                                                 \
+#define INTERNAL_ID_SPEED_RL                                                             \
     { 104, 2 }
-#define INTERNAL_ID_CONTROL_EVENT_FLAG_2                                                 \
-    { 104, 3 }
-#define INTERNAL_ID_SPEED_FL                                                             \
-    { 105, 0 }
-#define INTERNAL_ID_SPEED_FR                                                             \
-    { 105, 1 }
 #define INTERNAL_ID_SPEED_RR                                                             \
-    { 105, 2 }
-#define INTERNAL_ID_SPEED_RL                                                             \
-    { 105, 3 }
-#define INTERNAL_ID_TORQUE_GAIN                                                          \
+    { 104, 3 }
+// #define REDUCAO TORQUE RODA ESQUERDA                                                   \
+//     { 105, 0 }
+// #define  || || || DIREITA                                                              \
+//     { 105, 1 }
+// #define  EXTRA CONTROLE DINAMICO   flags crossval?                                     \
+//     { 105, 2 }
+// #define  EXTRA CONTROLE DINAMICO                                                       \
+//     { 105, 3 }
+#define INTERNAL_ID_REGEN_BRAKE_STATE                                                    \
     { 106, 0 }
-#define INTERNAL_ID_CURRENT_R_MOTOR                                                      \
-    { 106, 2 }
-#define INTERNAL_ID_CURRENT_L_MOTOR                                                      \
-    { 106, 3 }
-#define INTERNAL_ID_TEMPERATURE1_R                                                       \
-    { 107, 0 }
-#define INTERNAL_ID_TEMPERATURE2_R                                                       \
-    { 107, 1 }
-#define INTERNAL_ID_TEMPERATURE1_L                                                       \
-    { 107, 2 }
-#define INTERNAL_ID_TEMPERATURE2_L                                                       \
-    { 107, 3 }
 #define INTERNAL_ID_IMU_BSE_ERROR                                                        \
     { 108, 0 }
 #define INTERNAL_ID_STATUS_DATALOG                                                       \
@@ -159,48 +159,78 @@ extern CAN_ID_t CAN_ID_map[CAN_ID_QUAN];
     { 351, 2 }
 #define INTERNAL_ID_PANEL_DEBUG_4                                                        \
     { 351, 3 }
-#define INTERNAL_ID_REGEN_BRAKE_STATE                                                    \
-    { 102, 1 }
 #define INTERNAL_ID_SPEED_L_MOTOR                                                        \
-    { 109, 0 }
-#define INTERNAL_ID_SPEED_R_MOTOR                                                        \
-    { 109, 1 }
-#define INTERNAL_ID_POWER_L_MOTOR                                                        \
-    { 109, 2 }
-#define INTERNAL_ID_POWER_R_MOTOR                                                        \
-    { 109, 3 }
-#define INTERNAL_ID_ENERGY_L_MOTOR                                                       \
     { 110, 0 }
-#define INTERNAL_ID_ENERGY_R_MOTOR                                                       \
+#define INTERNAL_ID_TORQUE_L_MOTOR                                                       \
     { 110, 1 }
-#define INTERNAL_ID_OVERLOAD_L_MOTOR                                                     \
+#define INTERNAL_ID_POWER_L_MOTOR                                                        \
     { 110, 2 }
-#define INTERNAL_ID_OVERLOAD_R_MOTOR                                                     \
+#define INTERNAL_ID_CURRENT_L_MOTOR                                                      \
     { 110, 3 }
-#define INTERNAL_ID_LOST_MSG_L_MOTOR                                                     \
+#define INTERNAL_ID_ENERGY_L_MOTOR                                                       \
     { 111, 0 }
-#define INTERNAL_ID_LOST_MSG_R_MOTOR                                                     \
+#define INTERNAL_ID_OVERLOAD_L_MOTOR                                                     \
     { 111, 1 }
-#define INTERNAL_ID_BUS_OFF_L_MOTOR                                                      \
+#define INTERNAL_ID_TEMPERATURE1_L                                                       \
     { 111, 2 }
-#define INTERNAL_ID_BUS_OFF_R_MOTOR                                                      \
+#define INTERNAL_ID_TEMPERATURE2_L                                                       \
     { 111, 3 }
-#define INTERNAL_ID_CAN_STATE_L_MOTOR                                                    \
+#define INTERNAL_ID_LOST_MSG_L_MOTOR                                                     \
     { 112, 0 }
-#define INTERNAL_ID_CAN_STATE_R_MOTOR                                                    \
+#define INTERNAL_ID_BUS_OFF_L_MOTOR                                                      \
     { 112, 1 }
-#define INTERNAL_ID_INV_STATE_L_MOTOR                                                    \
+#define INTERNAL_ID_CAN_STATE_L_MOTOR                                                    \
     { 112, 2 }
-#define INTERNAL_ID_INV_STATE_R_MOTOR                                                    \
-    { 112, 3 }
-#define INTERNAL_ID_FAILURE_L_MOTOR                                                      \
+#define INTERNAL_ID_INV_STATE_L_MOTOR                                                    \
     { 113, 0 }
-#define INTERNAL_ID_FAILURE_R_MOTOR                                                      \
+#define INTERNAL_ID_FAILURE_L_MOTOR                                                      \
     { 113, 1 }
 #define INTERNAL_ID_ALARM_L_MOTOR                                                        \
     { 113, 2 }
+#define INTERNAL_ID_SPEED_R_MOTOR                                                        \
+    { 120, 0 }
+#define INTERNAL_ID_TORQUE_R_MOTOR                                                       \
+    { 120, 1 }
+#define INTERNAL_ID_POWER_R_MOTOR                                                        \
+    { 120, 2 }
+#define INTERNAL_ID_CURRENT_R_MOTOR                                                      \
+    { 120, 3 }
+#define INTERNAL_ID_ENERGY_R_MOTOR                                                       \
+    { 121, 0 }
+#define INTERNAL_ID_OVERLOAD_R_MOTOR                                                     \
+    { 121, 1 }
+#define INTERNAL_ID_TEMPERATURE1_R                                                       \
+    { 121, 2 }
+#define INTERNAL_ID_TEMPERATURE2_R                                                       \
+    { 121, 3 }
+#define INTERNAL_ID_LOST_MSG_R_MOTOR                                                     \
+    { 122, 0 }
+#define INTERNAL_ID_BUS_OFF_R_MOTOR                                                      \
+    { 122, 1 }
+#define INTERNAL_ID_CAN_STATE_R_MOTOR                                                    \
+    { 122, 2 }
+#define INTERNAL_ID_INV_STATE_R_MOTOR                                                    \
+    { 123, 0 }
+#define INTERNAL_ID_FAILURE_R_MOTOR                                                      \
+    { 123, 1 }
 #define INTERNAL_ID_ALARM_R_MOTOR                                                        \
-    { 113, 3 }
+    { 123, 2 }
+// #define ACCEL X                                                                        \
+//     { 130, 0 }
+// #define ACCEL Y                                                                        \
+//     { 130, 1 }
+// #define ACCEL Z                                                                        \
+//     { 130, 2 }
+// #define TEMP IMU                                                                       \
+//     { 130, 3 }
+// #define GYRO X                                                                         \
+//     { 131, 0 }
+// #define GYRO Y                                                                         \
+//     { 131, 1 }
+// #define GYRO Z                                                                         \
+//     { 131, 2 }
+// #define IMU ERROR                                                                      \
+//     { 131, 3 }
 
 //----------
 
diff --git a/Core/Src/CAN/CAN_IDs.c b/Core/Src/CAN/CAN_IDs.c
index 2f868a09..f03d6b4a 100644
--- a/Core/Src/CAN/CAN_IDs.c
+++ b/Core/Src/CAN/CAN_IDs.c
@@ -27,61 +27,72 @@ uint16_t get_internal_from_id_pos(uint16_t id, uint16_t pos) {
 // PRIMEIRA POSICAO DA MENSAGEM CAN N PODE ESTAR VAZIA
 
 void initialize_CAN_IDs() {
-    CAN_ID_map[ID_ECU_TIMER]            = (CAN_ID_t)INTERNAL_ID_ECU_TIMER;
+    CAN_ID_map[ID_SPEED_AVG]            = (CAN_ID_t)INTERNAL_ID_SPEED_AVG;
     CAN_ID_map[ID_STEERING_WHEEL]       = (CAN_ID_t)INTERNAL_ID_STEERING_WHEEL;
     CAN_ID_map[ID_THROTTLE]             = (CAN_ID_t)INTERNAL_ID_THROTTLE;
     CAN_ID_map[ID_BRAKE]                = (CAN_ID_t)INTERNAL_ID_BRAKE;
     CAN_ID_map[ID_MODE]                 = (CAN_ID_t)INTERNAL_ID_MODE;
+    CAN_ID_map[ID_TORQUE_GAIN]          = (CAN_ID_t)INTERNAL_ID_TORQUE_GAIN;
     CAN_ID_map[ID_DISTANCE_P_ODOM]      = (CAN_ID_t)INTERNAL_ID_DISTANCE_P_ODOM;
     CAN_ID_map[ID_DISTANCE_T_ODOM]      = (CAN_ID_t)INTERNAL_ID_DISTANCE_T_ODOM;
-    CAN_ID_map[ID_TORQUE_R_MOTOR]       = (CAN_ID_t)INTERNAL_ID_TORQUE_R_MOTOR;
-    CAN_ID_map[ID_TORQUE_L_MOTOR]       = (CAN_ID_t)INTERNAL_ID_TORQUE_L_MOTOR;
-    CAN_ID_map[ID_REF_TORQUE_R_MOTOR]   = (CAN_ID_t)INTERNAL_ID_REF_TORQUE_R_MOTOR;
-    CAN_ID_map[ID_REF_TORQUE_L_MOTOR]   = (CAN_ID_t)INTERNAL_ID_REF_TORQUE_L_MOTOR;
-    CAN_ID_map[ID_REF_SPEED_R]          = (CAN_ID_t)INTERNAL_ID_REF_SPEED_R_MOTOR;
-    CAN_ID_map[ID_REF_SPEED_L]          = (CAN_ID_t)INTERNAL_ID_REF_SPEED_L_MOTOR;
     CAN_ID_map[ID_CONTROL_EVENT_FLAG_1] = (CAN_ID_t)INTERNAL_ID_CONTROL_EVENT_FLAG_1;
     CAN_ID_map[ID_CONTROL_EVENT_FLAG_2] = (CAN_ID_t)INTERNAL_ID_CONTROL_EVENT_FLAG_2;
+    CAN_ID_map[ID_REF_TORQUE_R_MOTOR]   = (CAN_ID_t)INTERNAL_ID_REF_TORQUE_R_MOTOR;
+    CAN_ID_map[ID_REF_TORQUE_L_MOTOR]   = (CAN_ID_t)INTERNAL_ID_REF_TORQUE_L_MOTOR;
     CAN_ID_map[ID_SPEED_FL]             = (CAN_ID_t)INTERNAL_ID_SPEED_FL;
     CAN_ID_map[ID_SPEED_FR]             = (CAN_ID_t)INTERNAL_ID_SPEED_FR;
-    CAN_ID_map[ID_SPEED_RR]             = (CAN_ID_t)INTERNAL_ID_SPEED_RR;
     CAN_ID_map[ID_SPEED_RL]             = (CAN_ID_t)INTERNAL_ID_SPEED_RL;
-    CAN_ID_map[ID_TORQUE_GAIN]          = (CAN_ID_t)INTERNAL_ID_TORQUE_GAIN;
-    CAN_ID_map[ID_CURRENT_R_MOTOR]      = (CAN_ID_t)INTERNAL_ID_CURRENT_R_MOTOR;
-    CAN_ID_map[ID_CURRENT_L_MOTOR]      = (CAN_ID_t)INTERNAL_ID_CURRENT_L_MOTOR;
-    CAN_ID_map[ID_TEMPERATURE1_R]       = (CAN_ID_t)INTERNAL_ID_TEMPERATURE1_R;
-    CAN_ID_map[ID_TEMPERATURE2_R]       = (CAN_ID_t)INTERNAL_ID_TEMPERATURE2_R;
-    CAN_ID_map[ID_TEMPERATURE1_L]       = (CAN_ID_t)INTERNAL_ID_TEMPERATURE1_L;
-    CAN_ID_map[ID_TEMPERATURE2_L]       = (CAN_ID_t)INTERNAL_ID_TEMPERATURE2_L;
-    CAN_ID_map[ID_IMU_BSE_ERROR]        = (CAN_ID_t)INTERNAL_ID_IMU_BSE_ERROR;
-    CAN_ID_map[ID_STATUS_DATALOG]       = (CAN_ID_t)INTERNAL_ID_STATUS_DATALOG;
-    CAN_ID_map[ID_IMU_SPEED_ERROR]      = (CAN_ID_t)INTERNAL_ID_IMU_SPEED_ERROR;
-    CAN_ID_map[ID_CURRENT_FLAG]         = (CAN_ID_t)INTERNAL_ID_CURRENT_FLAG;
-    CAN_ID_map[ID_PANEL_DEBUG_1]        = (CAN_ID_t)INTERNAL_ID_PANEL_DEBUG_1;
-    CAN_ID_map[ID_PANEL_DEBUG_2]        = (CAN_ID_t)INTERNAL_ID_PANEL_DEBUG_2;
-    CAN_ID_map[ID_PANEL_DEBUG_3]        = (CAN_ID_t)INTERNAL_ID_PANEL_DEBUG_3;
-    CAN_ID_map[ID_PANEL_DEBUG_4]        = (CAN_ID_t)INTERNAL_ID_PANEL_DEBUG_4;
-    CAN_ID_map[ID_REGEN_BRAKE_STATE]    = (CAN_ID_t)INTERNAL_ID_REGEN_BRAKE_STATE;
-    CAN_ID_map[ID_SPEED_L_MOTOR]        = (CAN_ID_t)INTERNAL_ID_SPEED_L_MOTOR;
-    CAN_ID_map[ID_SPEED_R_MOTOR]        = (CAN_ID_t)INTERNAL_ID_SPEED_R_MOTOR;
-    CAN_ID_map[ID_POWER_L_MOTOR]        = (CAN_ID_t)INTERNAL_ID_POWER_L_MOTOR;
-    CAN_ID_map[ID_POWER_R_MOTOR]        = (CAN_ID_t)INTERNAL_ID_POWER_R_MOTOR;
-    CAN_ID_map[ID_ENERGY_L_MOTOR]       = (CAN_ID_t)INTERNAL_ID_ENERGY_L_MOTOR;
-    CAN_ID_map[ID_ENERGY_R_MOTOR]       = (CAN_ID_t)INTERNAL_ID_ENERGY_R_MOTOR;
-    CAN_ID_map[ID_OVERLOAD_L_MOTOR]     = (CAN_ID_t)INTERNAL_ID_OVERLOAD_L_MOTOR;
-    CAN_ID_map[ID_OVERLOAD_R_MOTOR]     = (CAN_ID_t)INTERNAL_ID_OVERLOAD_R_MOTOR;
-    CAN_ID_map[ID_LOST_MSG_L_MOTOR]     = (CAN_ID_t)INTERNAL_ID_LOST_MSG_L_MOTOR;
-    CAN_ID_map[ID_LOST_MSG_R_MOTOR]     = (CAN_ID_t)INTERNAL_ID_LOST_MSG_R_MOTOR;
-    CAN_ID_map[ID_BUS_OFF_L_MOTOR]      = (CAN_ID_t)INTERNAL_ID_BUS_OFF_L_MOTOR;
-    CAN_ID_map[ID_BUS_OFF_R_MOTOR]      = (CAN_ID_t)INTERNAL_ID_BUS_OFF_R_MOTOR;
-    CAN_ID_map[ID_CAN_STATE_L_MOTOR]    = (CAN_ID_t)INTERNAL_ID_CAN_STATE_L_MOTOR;
-    CAN_ID_map[ID_CAN_STATE_R_MOTOR]    = (CAN_ID_t)INTERNAL_ID_CAN_STATE_R_MOTOR;
-    CAN_ID_map[ID_INV_STATE_L_MOTOR]    = (CAN_ID_t)INTERNAL_ID_INV_STATE_L_MOTOR;
-    CAN_ID_map[ID_INV_STATE_R_MOTOR]    = (CAN_ID_t)INTERNAL_ID_INV_STATE_R_MOTOR;
-    CAN_ID_map[ID_FAILURE_L_MOTOR]      = (CAN_ID_t)INTERNAL_ID_FAILURE_L_MOTOR;
-    CAN_ID_map[ID_FAILURE_R_MOTOR]      = (CAN_ID_t)INTERNAL_ID_FAILURE_R_MOTOR;
-    CAN_ID_map[ID_ALARM_L_MOTOR]        = (CAN_ID_t)INTERNAL_ID_ALARM_L_MOTOR;
-    CAN_ID_map[ID_ALARM_R_MOTOR]        = (CAN_ID_t)INTERNAL_ID_ALARM_R_MOTOR;
+    CAN_ID_map[ID_SPEED_RR]             = (CAN_ID_t)INTERNAL_ID_SPEED_RR;
+    // CAN_ID_map[ID_RED_TORQUE_ROD_ESQ] = (CAN_ID_t)INTERNAL_ID_RED_TORQUE_ROD_ESQ;
+    // CAN_ID_map[ID_RED_TORQUE_ROD_DIR] = (CAN_ID_t)INTERNAL_ID_RED_TORQUE_ROD_DIR;
+    // CAN_ID_map[ID_EXTRA_CONTROL_DIN]          =
+    // (CAN_ID_t)INTERNAL_ID_EXTRA_CONTROL_DIN; CAN_ID_map[ID_EXTRA_CONTROL_DIN]      =
+    // (CAN_ID_t)INTERNAL_ID_EXTRA_CONTROL_DIN;
+    CAN_ID_map[ID_REGEN_BRAKE_STATE] = (CAN_ID_t)INTERNAL_ID_REGEN_BRAKE_STATE;
+    CAN_ID_map[ID_IMU_BSE_ERROR]     = (CAN_ID_t)INTERNAL_ID_IMU_BSE_ERROR;
+    CAN_ID_map[ID_STATUS_DATALOG]    = (CAN_ID_t)INTERNAL_ID_STATUS_DATALOG;
+    CAN_ID_map[ID_IMU_SPEED_ERROR]   = (CAN_ID_t)INTERNAL_ID_IMU_SPEED_ERROR;
+    CAN_ID_map[ID_CURRENT_FLAG]      = (CAN_ID_t)INTERNAL_ID_CURRENT_FLAG;
+    CAN_ID_map[ID_PANEL_DEBUG_1]     = (CAN_ID_t)INTERNAL_ID_PANEL_DEBUG_1;
+    CAN_ID_map[ID_PANEL_DEBUG_2]     = (CAN_ID_t)INTERNAL_ID_PANEL_DEBUG_2;
+    CAN_ID_map[ID_PANEL_DEBUG_3]     = (CAN_ID_t)INTERNAL_ID_PANEL_DEBUG_3;
+    CAN_ID_map[ID_PANEL_DEBUG_4]     = (CAN_ID_t)INTERNAL_ID_PANEL_DEBUG_4;
+    CAN_ID_map[ID_SPEED_L_MOTOR]     = (CAN_ID_t)INTERNAL_ID_SPEED_L_MOTOR;
+    CAN_ID_map[ID_TORQUE_L_MOTOR]    = (CAN_ID_t)INTERNAL_ID_TORQUE_L_MOTOR;
+    CAN_ID_map[ID_POWER_L_MOTOR]     = (CAN_ID_t)INTERNAL_ID_POWER_L_MOTOR;
+    CAN_ID_map[ID_CURRENT_L_MOTOR]   = (CAN_ID_t)INTERNAL_ID_CURRENT_L_MOTOR;
+    CAN_ID_map[ID_ENERGY_L_MOTOR]    = (CAN_ID_t)INTERNAL_ID_ENERGY_L_MOTOR;
+    CAN_ID_map[ID_OVERLOAD_L_MOTOR]  = (CAN_ID_t)INTERNAL_ID_OVERLOAD_L_MOTOR;
+    CAN_ID_map[ID_TEMPERATURE1_L]    = (CAN_ID_t)INTERNAL_ID_TEMPERATURE1_L;
+    CAN_ID_map[ID_TEMPERATURE2_L]    = (CAN_ID_t)INTERNAL_ID_TEMPERATURE2_L;
+    CAN_ID_map[ID_LOST_MSG_L_MOTOR]  = (CAN_ID_t)INTERNAL_ID_LOST_MSG_L_MOTOR;
+    CAN_ID_map[ID_BUS_OFF_L_MOTOR]   = (CAN_ID_t)INTERNAL_ID_BUS_OFF_L_MOTOR;
+    CAN_ID_map[ID_CAN_STATE_L_MOTOR] = (CAN_ID_t)INTERNAL_ID_CAN_STATE_L_MOTOR;
+    CAN_ID_map[ID_INV_STATE_L_MOTOR] = (CAN_ID_t)INTERNAL_ID_INV_STATE_L_MOTOR;
+    CAN_ID_map[ID_FAILURE_L_MOTOR]   = (CAN_ID_t)INTERNAL_ID_FAILURE_L_MOTOR;
+    CAN_ID_map[ID_ALARM_L_MOTOR]     = (CAN_ID_t)INTERNAL_ID_ALARM_L_MOTOR;
+    CAN_ID_map[ID_SPEED_R_MOTOR]     = (CAN_ID_t)INTERNAL_ID_SPEED_R_MOTOR;
+    CAN_ID_map[ID_TORQUE_R_MOTOR]    = (CAN_ID_t)INTERNAL_ID_TORQUE_R_MOTOR;
+    CAN_ID_map[ID_POWER_R_MOTOR]     = (CAN_ID_t)INTERNAL_ID_POWER_R_MOTOR;
+    CAN_ID_map[ID_CURRENT_R_MOTOR]   = (CAN_ID_t)INTERNAL_ID_CURRENT_R_MOTOR;
+    CAN_ID_map[ID_ENERGY_R_MOTOR]    = (CAN_ID_t)INTERNAL_ID_ENERGY_R_MOTOR;
+    CAN_ID_map[ID_OVERLOAD_R_MOTOR]  = (CAN_ID_t)INTERNAL_ID_OVERLOAD_R_MOTOR;
+    CAN_ID_map[ID_TEMPERATURE1_R]    = (CAN_ID_t)INTERNAL_ID_TEMPERATURE1_R;
+    CAN_ID_map[ID_TEMPERATURE2_R]    = (CAN_ID_t)INTERNAL_ID_TEMPERATURE2_R;
+    CAN_ID_map[ID_LOST_MSG_R_MOTOR]  = (CAN_ID_t)INTERNAL_ID_LOST_MSG_R_MOTOR;
+    CAN_ID_map[ID_BUS_OFF_R_MOTOR]   = (CAN_ID_t)INTERNAL_ID_BUS_OFF_R_MOTOR;
+    CAN_ID_map[ID_CAN_STATE_R_MOTOR] = (CAN_ID_t)INTERNAL_ID_CAN_STATE_R_MOTOR;
+    CAN_ID_map[ID_INV_STATE_R_MOTOR] = (CAN_ID_t)INTERNAL_ID_INV_STATE_R_MOTOR;
+    CAN_ID_map[ID_FAILURE_R_MOTOR]   = (CAN_ID_t)INTERNAL_ID_FAILURE_R_MOTOR;
+    CAN_ID_map[ID_ALARM_R_MOTOR]     = (CAN_ID_t)INTERNAL_ID_ALARM_R_MOTOR;
+    // CAN_ID_map[ID_ACCEL X]        = (CAN_ID_t)INTERNAL_ID_ACCEL_X;
+    // CAN_ID_map[ID_ACCEL Y]        = (CAN_ID_t)INTERNAL_ID_ACCEL_Y;
+    // CAN_ID_map[ID_ACCEL Z]        = (CAN_ID_t)INTERNAL_ID_ACCEL_Z;
+    // CAN_ID_map[ID_TEMP_IMU]        = (CAN_ID_t)INTERNAL_ID_TEMP_IMU;
+    // CAN_ID_map[ID_GYRO X]        = (CAN_ID_t)INTERNAL_ID_GYRO_X;
+    // CAN_ID_map[ID_GYRO Y]        = (CAN_ID_t)INTERNAL_ID_GYRO_Y;
+    // CAN_ID_map[ID_GYRO Z]        = (CAN_ID_t)INTERNAL_ID_GYRO_Z;
+    // CAN_ID_map[ID_IMU]        = (CAN_ID_t)INTERNAL_ID_IMU_ERROR;
 
     // define um identificador unico a cada conjunto id & pos. Mapeia esse identificador
     // em outro vetor, para facil acesso posterior no datalog.

From a07503b5c8bf220eb360b6b934b97b2a1fc6cf3d Mon Sep 17 00:00:00 2001
From: caiussouza <caiuscsouza@gmail.com>
Date: Thu, 11 May 2023 21:51:07 -0300
Subject: [PATCH 32/33] reverting can ids changes

---
 Core/Inc/CAN/CAN_IDs.h | 242 ++++++++++++++++++-----------------------
 Core/Src/CAN/CAN_IDs.c |  99 ++++++++---------
 2 files changed, 150 insertions(+), 191 deletions(-)

diff --git a/Core/Inc/CAN/CAN_IDs.h b/Core/Inc/CAN/CAN_IDs.h
index 7b00b4e1..54432fdd 100644
--- a/Core/Inc/CAN/CAN_IDs.h
+++ b/Core/Inc/CAN/CAN_IDs.h
@@ -20,73 +20,63 @@
 // DATALOGGER
 // LEGENDA:  LABEL    	    	 INTERNAL_ID
 // 0 E RESERVADO PARA LACUNAS NO PACOTE
-#define ID_SPEED_AVG            1
+#define ID_ECU_TIMER            1
 #define ID_STEERING_WHEEL       2
 #define ID_THROTTLE             3
 #define ID_BRAKE                4
 #define ID_MODE                 5
-#define ID_TORQUE_GAIN          6
-#define ID_DISTANCE_P_ODOM      7
-#define ID_DISTANCE_T_ODOM      8
-#define ID_CONTROL_EVENT_FLAG_1 9
-#define ID_CONTROL_EVENT_FLAG_2 10
-#define ID_REF_TORQUE_R_MOTOR   11
-#define ID_REF_TORQUE_L_MOTOR   12
-#define ID_SPEED_FL             13
-#define ID_SPEED_FR             14
-#define ID_SPEED_RL             15
-#define ID_SPEED_RR             16
-// #define /*RED_TORQUE_ROD_ESQ */ 17
-// #define /*RED_TORQUE_ROD_DIR */ 18
-// #define /*EXTRA_CONTROL_DIN  */ 19
-// #define /*EXTRA_CONTROL_DIN  */ 20
-#define ID_REGEN_BRAKE_STATE    21
-#define ID_IMU_BSE_ERROR        22
-#define ID_STATUS_DATALOG       23
-#define ID_IMU_SPEED_ERROR      24
-#define ID_CURRENT_FLAG         25
-#define ID_PANEL_DEBUG_1        26
-#define ID_PANEL_DEBUG_2        27
-#define ID_PANEL_DEBUG_3        28
-#define ID_PANEL_DEBUG_4        29
-#define ID_SPEED_L_MOTOR        30
-#define ID_TORQUE_L_MOTOR       31
-#define ID_POWER_L_MOTOR        32
-#define ID_CURRENT_L_MOTOR      33
-#define ID_ENERGY_L_MOTOR       34
-#define ID_OVERLOAD_L_MOTOR     35
-#define ID_TEMPERATURE1_L       36
-#define ID_TEMPERATURE2_L       37
-#define ID_LOST_MSG_L_MOTOR     38
-#define ID_BUS_OFF_L_MOTOR      39
-#define ID_CAN_STATE_L_MOTOR    40
-#define ID_INV_STATE_L_MOTOR    41
-#define ID_FAILURE_L_MOTOR      42
-#define ID_ALARM_L_MOTOR        43
-#define ID_SPEED_R_MOTOR        44
-#define ID_TORQUE_R_MOTOR       45
-#define ID_POWER_R_MOTOR        46
-#define ID_CURRENT_R_MOTOR      47
-#define ID_ENERGY_R_MOTOR       48
-#define ID_OVERLOAD_R_MOTOR     49
-#define ID_TEMPERATURE1_R       50
-#define ID_TEMPERATURE2_R       51
-#define ID_LOST_MSG_R_MOTOR     52
-#define ID_BUS_OFF_R_MOTOR      53
-#define ID_CAN_STATE_R_MOTOR    54
-#define ID_INV_STATE_R_MOTOR    55
-#define ID_FAILURE_R_MOTOR      56
-#define ID_ALARM_R_MOTOR        57
-// #define /*ACCEL X*/ 58
-// #define /*ACCEL Y*/ 59
-// #define /*ACCEL Z*/ 60
-// #define /*TEMP IMU*/ 61
-// #define /*GYRO X*/ 62
-// #define /*GYRO Y*/ 63
-// #define /*GYRO Z*/ 64
-// #define /*IMU ERROR*/ 65
+#define ID_DISTANCE_P_ODOM      6
+#define ID_DISTANCE_T_ODOM      7
+#define ID_TORQUE_R_MOTOR       8
+#define ID_TORQUE_L_MOTOR       9
+#define ID_REF_TORQUE_R_MOTOR   10
+#define ID_REF_TORQUE_L_MOTOR   11
+#define ID_REF_SPEED_R          12
+#define ID_REF_SPEED_L          13
+#define ID_CONTROL_EVENT_FLAG_1 14
+#define ID_CONTROL_EVENT_FLAG_2 15
+#define ID_SPEED_FL             16
+#define ID_SPEED_FR             17
+#define ID_SPEED_RR             18
+#define ID_SPEED_RL             19
+#define ID_TORQUE_GAIN          20
+#define ID_CURRENT_R_MOTOR      21
+#define ID_CURRENT_L_MOTOR      22
+#define ID_TEMPERATURE1_R       23
+#define ID_TEMPERATURE2_R       24
+#define ID_TEMPERATURE1_L       25
+#define ID_TEMPERATURE2_L       26
+#define ID_IMU_BSE_ERROR        27
+#define ID_STATUS_DATALOG       28
+#define ID_IMU_SPEED_ERROR      29
+#define ID_CURRENT_FLAG         30
+#define ID_PANEL_DEBUG_1        31
+#define ID_PANEL_DEBUG_2        32
+#define ID_PANEL_DEBUG_3        33
+#define ID_PANEL_DEBUG_4        34
+#define ID_REGEN_BRAKE_STATE    35
+#define ID_SPEED_L_MOTOR        36
+#define ID_SPEED_R_MOTOR        37
+#define ID_POWER_L_MOTOR        38
+#define ID_POWER_R_MOTOR        39
+#define ID_ENERGY_L_MOTOR       40
+#define ID_ENERGY_R_MOTOR       41
+#define ID_OVERLOAD_L_MOTOR     42
+#define ID_OVERLOAD_R_MOTOR     43
+#define ID_LOST_MSG_L_MOTOR     44
+#define ID_LOST_MSG_R_MOTOR     45
+#define ID_BUS_OFF_L_MOTOR      46
+#define ID_BUS_OFF_R_MOTOR      47
+#define ID_CAN_STATE_L_MOTOR    48
+#define ID_CAN_STATE_R_MOTOR    49
+#define ID_INV_STATE_L_MOTOR    50
+#define ID_INV_STATE_R_MOTOR    51
+#define ID_FAILURE_L_MOTOR      52
+#define ID_FAILURE_R_MOTOR      53
+#define ID_ALARM_L_MOTOR        54
+#define ID_ALARM_R_MOTOR        55
 
-#define CAN_ID_QUAN 65
+#define CAN_ID_QUAN 56
 
 typedef struct {
     uint16_t id;
@@ -97,11 +87,11 @@ extern CAN_ID_t CAN_ID_map[CAN_ID_QUAN];
 // TODO(renanmoreira): IMPLEMENT X-MACROS FOR CAN_ID'S
 #define ECU_CAN_INITIAL_ID        100
 #define ECU_CAN_FINAL_ID          149
-#define ECU_CAN_LAST_POPULATED_ID 131
+#define ECU_CAN_LAST_POPULATED_ID 113
 #define ECU_CAN_FIRST_DEBUG_ID    351
 #define ECU_CAN_LAST_DEBUG_ID     351
 
-#define INTERNAL_ID_SPEED_AVG                                                            \
+#define INTERNAL_ID_ECU_TIMER                                                            \
     { 101, 0 }
 #define INTERNAL_ID_STEERING_WHEEL                                                       \
     { 101, 1 }
@@ -111,38 +101,48 @@ extern CAN_ID_t CAN_ID_map[CAN_ID_QUAN];
     { 101, 3 }
 #define INTERNAL_ID_MODE                                                                 \
     { 102, 0 }
-#define INTERNAL_ID_TORQUE_GAIN                                                          \
-    { 102, 1 }
 #define INTERNAL_ID_DISTANCE_P_ODOM                                                      \
     { 102, 2 }
 #define INTERNAL_ID_DISTANCE_T_ODOM                                                      \
     { 102, 3 }
-#define INTERNAL_ID_CONTROL_EVENT_FLAG_1                                                 \
+#define INTERNAL_ID_TORQUE_R_MOTOR                                                       \
     { 103, 0 }
-#define INTERNAL_ID_CONTROL_EVENT_FLAG_2                                                 \
+#define INTERNAL_ID_TORQUE_L_MOTOR                                                       \
     { 103, 1 }
 #define INTERNAL_ID_REF_TORQUE_R_MOTOR                                                   \
     { 103, 2 }
 #define INTERNAL_ID_REF_TORQUE_L_MOTOR                                                   \
     { 103, 3 }
-#define INTERNAL_ID_SPEED_FL                                                             \
+#define INTERNAL_ID_REF_SPEED_R_MOTOR                                                    \
     { 104, 0 }
-#define INTERNAL_ID_SPEED_FR                                                             \
+#define INTERNAL_ID_REF_SPEED_L_MOTOR                                                    \
     { 104, 1 }
-#define INTERNAL_ID_SPEED_RL                                                             \
+#define INTERNAL_ID_CONTROL_EVENT_FLAG_1                                                 \
     { 104, 2 }
-#define INTERNAL_ID_SPEED_RR                                                             \
+#define INTERNAL_ID_CONTROL_EVENT_FLAG_2                                                 \
     { 104, 3 }
-// #define REDUCAO TORQUE RODA ESQUERDA                                                   \
-//     { 105, 0 }
-// #define  || || || DIREITA                                                              \
-//     { 105, 1 }
-// #define  EXTRA CONTROLE DINAMICO   flags crossval?                                     \
-//     { 105, 2 }
-// #define  EXTRA CONTROLE DINAMICO                                                       \
-//     { 105, 3 }
-#define INTERNAL_ID_REGEN_BRAKE_STATE                                                    \
+#define INTERNAL_ID_SPEED_FL                                                             \
+    { 105, 0 }
+#define INTERNAL_ID_SPEED_FR                                                             \
+    { 105, 1 }
+#define INTERNAL_ID_SPEED_RR                                                             \
+    { 105, 2 }
+#define INTERNAL_ID_SPEED_RL                                                             \
+    { 105, 3 }
+#define INTERNAL_ID_TORQUE_GAIN                                                          \
     { 106, 0 }
+#define INTERNAL_ID_CURRENT_R_MOTOR                                                      \
+    { 106, 2 }
+#define INTERNAL_ID_CURRENT_L_MOTOR                                                      \
+    { 106, 3 }
+#define INTERNAL_ID_TEMPERATURE1_R                                                       \
+    { 107, 0 }
+#define INTERNAL_ID_TEMPERATURE2_R                                                       \
+    { 107, 1 }
+#define INTERNAL_ID_TEMPERATURE1_L                                                       \
+    { 107, 2 }
+#define INTERNAL_ID_TEMPERATURE2_L                                                       \
+    { 107, 3 }
 #define INTERNAL_ID_IMU_BSE_ERROR                                                        \
     { 108, 0 }
 #define INTERNAL_ID_STATUS_DATALOG                                                       \
@@ -159,78 +159,48 @@ extern CAN_ID_t CAN_ID_map[CAN_ID_QUAN];
     { 351, 2 }
 #define INTERNAL_ID_PANEL_DEBUG_4                                                        \
     { 351, 3 }
+#define INTERNAL_ID_REGEN_BRAKE_STATE                                                    \
+    { 102, 1 }
 #define INTERNAL_ID_SPEED_L_MOTOR                                                        \
+    { 109, 0 }
+#define INTERNAL_ID_SPEED_R_MOTOR                                                        \
+    { 109, 1 }
+#define INTERNAL_ID_POWER_L_MOTOR                                                        \
+    { 109, 2 }
+#define INTERNAL_ID_POWER_R_MOTOR                                                        \
+    { 109, 3 }
+#define INTERNAL_ID_ENERGY_L_MOTOR                                                       \
     { 110, 0 }
-#define INTERNAL_ID_TORQUE_L_MOTOR                                                       \
+#define INTERNAL_ID_ENERGY_R_MOTOR                                                       \
     { 110, 1 }
-#define INTERNAL_ID_POWER_L_MOTOR                                                        \
+#define INTERNAL_ID_OVERLOAD_L_MOTOR                                                     \
     { 110, 2 }
-#define INTERNAL_ID_CURRENT_L_MOTOR                                                      \
+#define INTERNAL_ID_OVERLOAD_R_MOTOR                                                     \
     { 110, 3 }
-#define INTERNAL_ID_ENERGY_L_MOTOR                                                       \
+#define INTERNAL_ID_LOST_MSG_L_MOTOR                                                     \
     { 111, 0 }
-#define INTERNAL_ID_OVERLOAD_L_MOTOR                                                     \
+#define INTERNAL_ID_LOST_MSG_R_MOTOR                                                     \
     { 111, 1 }
-#define INTERNAL_ID_TEMPERATURE1_L                                                       \
+#define INTERNAL_ID_BUS_OFF_L_MOTOR                                                      \
     { 111, 2 }
-#define INTERNAL_ID_TEMPERATURE2_L                                                       \
+#define INTERNAL_ID_BUS_OFF_R_MOTOR                                                      \
     { 111, 3 }
-#define INTERNAL_ID_LOST_MSG_L_MOTOR                                                     \
+#define INTERNAL_ID_CAN_STATE_L_MOTOR                                                    \
     { 112, 0 }
-#define INTERNAL_ID_BUS_OFF_L_MOTOR                                                      \
+#define INTERNAL_ID_CAN_STATE_R_MOTOR                                                    \
     { 112, 1 }
-#define INTERNAL_ID_CAN_STATE_L_MOTOR                                                    \
-    { 112, 2 }
 #define INTERNAL_ID_INV_STATE_L_MOTOR                                                    \
-    { 113, 0 }
+    { 112, 2 }
+#define INTERNAL_ID_INV_STATE_R_MOTOR                                                    \
+    { 112, 3 }
 #define INTERNAL_ID_FAILURE_L_MOTOR                                                      \
+    { 113, 0 }
+#define INTERNAL_ID_FAILURE_R_MOTOR                                                      \
     { 113, 1 }
 #define INTERNAL_ID_ALARM_L_MOTOR                                                        \
     { 113, 2 }
-#define INTERNAL_ID_SPEED_R_MOTOR                                                        \
-    { 120, 0 }
-#define INTERNAL_ID_TORQUE_R_MOTOR                                                       \
-    { 120, 1 }
-#define INTERNAL_ID_POWER_R_MOTOR                                                        \
-    { 120, 2 }
-#define INTERNAL_ID_CURRENT_R_MOTOR                                                      \
-    { 120, 3 }
-#define INTERNAL_ID_ENERGY_R_MOTOR                                                       \
-    { 121, 0 }
-#define INTERNAL_ID_OVERLOAD_R_MOTOR                                                     \
-    { 121, 1 }
-#define INTERNAL_ID_TEMPERATURE1_R                                                       \
-    { 121, 2 }
-#define INTERNAL_ID_TEMPERATURE2_R                                                       \
-    { 121, 3 }
-#define INTERNAL_ID_LOST_MSG_R_MOTOR                                                     \
-    { 122, 0 }
-#define INTERNAL_ID_BUS_OFF_R_MOTOR                                                      \
-    { 122, 1 }
-#define INTERNAL_ID_CAN_STATE_R_MOTOR                                                    \
-    { 122, 2 }
-#define INTERNAL_ID_INV_STATE_R_MOTOR                                                    \
-    { 123, 0 }
-#define INTERNAL_ID_FAILURE_R_MOTOR                                                      \
-    { 123, 1 }
 #define INTERNAL_ID_ALARM_R_MOTOR                                                        \
-    { 123, 2 }
-// #define ACCEL X                                                                        \
-//     { 130, 0 }
-// #define ACCEL Y                                                                        \
-//     { 130, 1 }
-// #define ACCEL Z                                                                        \
-//     { 130, 2 }
-// #define TEMP IMU                                                                       \
-//     { 130, 3 }
-// #define GYRO X                                                                         \
-//     { 131, 0 }
-// #define GYRO Y                                                                         \
-//     { 131, 1 }
-// #define GYRO Z                                                                         \
-//     { 131, 2 }
-// #define IMU ERROR                                                                      \
-//     { 131, 3 }
+    { 113, 3 }
 
 //----------
 
diff --git a/Core/Src/CAN/CAN_IDs.c b/Core/Src/CAN/CAN_IDs.c
index f03d6b4a..2f868a09 100644
--- a/Core/Src/CAN/CAN_IDs.c
+++ b/Core/Src/CAN/CAN_IDs.c
@@ -27,72 +27,61 @@ uint16_t get_internal_from_id_pos(uint16_t id, uint16_t pos) {
 // PRIMEIRA POSICAO DA MENSAGEM CAN N PODE ESTAR VAZIA
 
 void initialize_CAN_IDs() {
-    CAN_ID_map[ID_SPEED_AVG]            = (CAN_ID_t)INTERNAL_ID_SPEED_AVG;
+    CAN_ID_map[ID_ECU_TIMER]            = (CAN_ID_t)INTERNAL_ID_ECU_TIMER;
     CAN_ID_map[ID_STEERING_WHEEL]       = (CAN_ID_t)INTERNAL_ID_STEERING_WHEEL;
     CAN_ID_map[ID_THROTTLE]             = (CAN_ID_t)INTERNAL_ID_THROTTLE;
     CAN_ID_map[ID_BRAKE]                = (CAN_ID_t)INTERNAL_ID_BRAKE;
     CAN_ID_map[ID_MODE]                 = (CAN_ID_t)INTERNAL_ID_MODE;
-    CAN_ID_map[ID_TORQUE_GAIN]          = (CAN_ID_t)INTERNAL_ID_TORQUE_GAIN;
     CAN_ID_map[ID_DISTANCE_P_ODOM]      = (CAN_ID_t)INTERNAL_ID_DISTANCE_P_ODOM;
     CAN_ID_map[ID_DISTANCE_T_ODOM]      = (CAN_ID_t)INTERNAL_ID_DISTANCE_T_ODOM;
-    CAN_ID_map[ID_CONTROL_EVENT_FLAG_1] = (CAN_ID_t)INTERNAL_ID_CONTROL_EVENT_FLAG_1;
-    CAN_ID_map[ID_CONTROL_EVENT_FLAG_2] = (CAN_ID_t)INTERNAL_ID_CONTROL_EVENT_FLAG_2;
+    CAN_ID_map[ID_TORQUE_R_MOTOR]       = (CAN_ID_t)INTERNAL_ID_TORQUE_R_MOTOR;
+    CAN_ID_map[ID_TORQUE_L_MOTOR]       = (CAN_ID_t)INTERNAL_ID_TORQUE_L_MOTOR;
     CAN_ID_map[ID_REF_TORQUE_R_MOTOR]   = (CAN_ID_t)INTERNAL_ID_REF_TORQUE_R_MOTOR;
     CAN_ID_map[ID_REF_TORQUE_L_MOTOR]   = (CAN_ID_t)INTERNAL_ID_REF_TORQUE_L_MOTOR;
+    CAN_ID_map[ID_REF_SPEED_R]          = (CAN_ID_t)INTERNAL_ID_REF_SPEED_R_MOTOR;
+    CAN_ID_map[ID_REF_SPEED_L]          = (CAN_ID_t)INTERNAL_ID_REF_SPEED_L_MOTOR;
+    CAN_ID_map[ID_CONTROL_EVENT_FLAG_1] = (CAN_ID_t)INTERNAL_ID_CONTROL_EVENT_FLAG_1;
+    CAN_ID_map[ID_CONTROL_EVENT_FLAG_2] = (CAN_ID_t)INTERNAL_ID_CONTROL_EVENT_FLAG_2;
     CAN_ID_map[ID_SPEED_FL]             = (CAN_ID_t)INTERNAL_ID_SPEED_FL;
     CAN_ID_map[ID_SPEED_FR]             = (CAN_ID_t)INTERNAL_ID_SPEED_FR;
-    CAN_ID_map[ID_SPEED_RL]             = (CAN_ID_t)INTERNAL_ID_SPEED_RL;
     CAN_ID_map[ID_SPEED_RR]             = (CAN_ID_t)INTERNAL_ID_SPEED_RR;
-    // CAN_ID_map[ID_RED_TORQUE_ROD_ESQ] = (CAN_ID_t)INTERNAL_ID_RED_TORQUE_ROD_ESQ;
-    // CAN_ID_map[ID_RED_TORQUE_ROD_DIR] = (CAN_ID_t)INTERNAL_ID_RED_TORQUE_ROD_DIR;
-    // CAN_ID_map[ID_EXTRA_CONTROL_DIN]          =
-    // (CAN_ID_t)INTERNAL_ID_EXTRA_CONTROL_DIN; CAN_ID_map[ID_EXTRA_CONTROL_DIN]      =
-    // (CAN_ID_t)INTERNAL_ID_EXTRA_CONTROL_DIN;
-    CAN_ID_map[ID_REGEN_BRAKE_STATE] = (CAN_ID_t)INTERNAL_ID_REGEN_BRAKE_STATE;
-    CAN_ID_map[ID_IMU_BSE_ERROR]     = (CAN_ID_t)INTERNAL_ID_IMU_BSE_ERROR;
-    CAN_ID_map[ID_STATUS_DATALOG]    = (CAN_ID_t)INTERNAL_ID_STATUS_DATALOG;
-    CAN_ID_map[ID_IMU_SPEED_ERROR]   = (CAN_ID_t)INTERNAL_ID_IMU_SPEED_ERROR;
-    CAN_ID_map[ID_CURRENT_FLAG]      = (CAN_ID_t)INTERNAL_ID_CURRENT_FLAG;
-    CAN_ID_map[ID_PANEL_DEBUG_1]     = (CAN_ID_t)INTERNAL_ID_PANEL_DEBUG_1;
-    CAN_ID_map[ID_PANEL_DEBUG_2]     = (CAN_ID_t)INTERNAL_ID_PANEL_DEBUG_2;
-    CAN_ID_map[ID_PANEL_DEBUG_3]     = (CAN_ID_t)INTERNAL_ID_PANEL_DEBUG_3;
-    CAN_ID_map[ID_PANEL_DEBUG_4]     = (CAN_ID_t)INTERNAL_ID_PANEL_DEBUG_4;
-    CAN_ID_map[ID_SPEED_L_MOTOR]     = (CAN_ID_t)INTERNAL_ID_SPEED_L_MOTOR;
-    CAN_ID_map[ID_TORQUE_L_MOTOR]    = (CAN_ID_t)INTERNAL_ID_TORQUE_L_MOTOR;
-    CAN_ID_map[ID_POWER_L_MOTOR]     = (CAN_ID_t)INTERNAL_ID_POWER_L_MOTOR;
-    CAN_ID_map[ID_CURRENT_L_MOTOR]   = (CAN_ID_t)INTERNAL_ID_CURRENT_L_MOTOR;
-    CAN_ID_map[ID_ENERGY_L_MOTOR]    = (CAN_ID_t)INTERNAL_ID_ENERGY_L_MOTOR;
-    CAN_ID_map[ID_OVERLOAD_L_MOTOR]  = (CAN_ID_t)INTERNAL_ID_OVERLOAD_L_MOTOR;
-    CAN_ID_map[ID_TEMPERATURE1_L]    = (CAN_ID_t)INTERNAL_ID_TEMPERATURE1_L;
-    CAN_ID_map[ID_TEMPERATURE2_L]    = (CAN_ID_t)INTERNAL_ID_TEMPERATURE2_L;
-    CAN_ID_map[ID_LOST_MSG_L_MOTOR]  = (CAN_ID_t)INTERNAL_ID_LOST_MSG_L_MOTOR;
-    CAN_ID_map[ID_BUS_OFF_L_MOTOR]   = (CAN_ID_t)INTERNAL_ID_BUS_OFF_L_MOTOR;
-    CAN_ID_map[ID_CAN_STATE_L_MOTOR] = (CAN_ID_t)INTERNAL_ID_CAN_STATE_L_MOTOR;
-    CAN_ID_map[ID_INV_STATE_L_MOTOR] = (CAN_ID_t)INTERNAL_ID_INV_STATE_L_MOTOR;
-    CAN_ID_map[ID_FAILURE_L_MOTOR]   = (CAN_ID_t)INTERNAL_ID_FAILURE_L_MOTOR;
-    CAN_ID_map[ID_ALARM_L_MOTOR]     = (CAN_ID_t)INTERNAL_ID_ALARM_L_MOTOR;
-    CAN_ID_map[ID_SPEED_R_MOTOR]     = (CAN_ID_t)INTERNAL_ID_SPEED_R_MOTOR;
-    CAN_ID_map[ID_TORQUE_R_MOTOR]    = (CAN_ID_t)INTERNAL_ID_TORQUE_R_MOTOR;
-    CAN_ID_map[ID_POWER_R_MOTOR]     = (CAN_ID_t)INTERNAL_ID_POWER_R_MOTOR;
-    CAN_ID_map[ID_CURRENT_R_MOTOR]   = (CAN_ID_t)INTERNAL_ID_CURRENT_R_MOTOR;
-    CAN_ID_map[ID_ENERGY_R_MOTOR]    = (CAN_ID_t)INTERNAL_ID_ENERGY_R_MOTOR;
-    CAN_ID_map[ID_OVERLOAD_R_MOTOR]  = (CAN_ID_t)INTERNAL_ID_OVERLOAD_R_MOTOR;
-    CAN_ID_map[ID_TEMPERATURE1_R]    = (CAN_ID_t)INTERNAL_ID_TEMPERATURE1_R;
-    CAN_ID_map[ID_TEMPERATURE2_R]    = (CAN_ID_t)INTERNAL_ID_TEMPERATURE2_R;
-    CAN_ID_map[ID_LOST_MSG_R_MOTOR]  = (CAN_ID_t)INTERNAL_ID_LOST_MSG_R_MOTOR;
-    CAN_ID_map[ID_BUS_OFF_R_MOTOR]   = (CAN_ID_t)INTERNAL_ID_BUS_OFF_R_MOTOR;
-    CAN_ID_map[ID_CAN_STATE_R_MOTOR] = (CAN_ID_t)INTERNAL_ID_CAN_STATE_R_MOTOR;
-    CAN_ID_map[ID_INV_STATE_R_MOTOR] = (CAN_ID_t)INTERNAL_ID_INV_STATE_R_MOTOR;
-    CAN_ID_map[ID_FAILURE_R_MOTOR]   = (CAN_ID_t)INTERNAL_ID_FAILURE_R_MOTOR;
-    CAN_ID_map[ID_ALARM_R_MOTOR]     = (CAN_ID_t)INTERNAL_ID_ALARM_R_MOTOR;
-    // CAN_ID_map[ID_ACCEL X]        = (CAN_ID_t)INTERNAL_ID_ACCEL_X;
-    // CAN_ID_map[ID_ACCEL Y]        = (CAN_ID_t)INTERNAL_ID_ACCEL_Y;
-    // CAN_ID_map[ID_ACCEL Z]        = (CAN_ID_t)INTERNAL_ID_ACCEL_Z;
-    // CAN_ID_map[ID_TEMP_IMU]        = (CAN_ID_t)INTERNAL_ID_TEMP_IMU;
-    // CAN_ID_map[ID_GYRO X]        = (CAN_ID_t)INTERNAL_ID_GYRO_X;
-    // CAN_ID_map[ID_GYRO Y]        = (CAN_ID_t)INTERNAL_ID_GYRO_Y;
-    // CAN_ID_map[ID_GYRO Z]        = (CAN_ID_t)INTERNAL_ID_GYRO_Z;
-    // CAN_ID_map[ID_IMU]        = (CAN_ID_t)INTERNAL_ID_IMU_ERROR;
+    CAN_ID_map[ID_SPEED_RL]             = (CAN_ID_t)INTERNAL_ID_SPEED_RL;
+    CAN_ID_map[ID_TORQUE_GAIN]          = (CAN_ID_t)INTERNAL_ID_TORQUE_GAIN;
+    CAN_ID_map[ID_CURRENT_R_MOTOR]      = (CAN_ID_t)INTERNAL_ID_CURRENT_R_MOTOR;
+    CAN_ID_map[ID_CURRENT_L_MOTOR]      = (CAN_ID_t)INTERNAL_ID_CURRENT_L_MOTOR;
+    CAN_ID_map[ID_TEMPERATURE1_R]       = (CAN_ID_t)INTERNAL_ID_TEMPERATURE1_R;
+    CAN_ID_map[ID_TEMPERATURE2_R]       = (CAN_ID_t)INTERNAL_ID_TEMPERATURE2_R;
+    CAN_ID_map[ID_TEMPERATURE1_L]       = (CAN_ID_t)INTERNAL_ID_TEMPERATURE1_L;
+    CAN_ID_map[ID_TEMPERATURE2_L]       = (CAN_ID_t)INTERNAL_ID_TEMPERATURE2_L;
+    CAN_ID_map[ID_IMU_BSE_ERROR]        = (CAN_ID_t)INTERNAL_ID_IMU_BSE_ERROR;
+    CAN_ID_map[ID_STATUS_DATALOG]       = (CAN_ID_t)INTERNAL_ID_STATUS_DATALOG;
+    CAN_ID_map[ID_IMU_SPEED_ERROR]      = (CAN_ID_t)INTERNAL_ID_IMU_SPEED_ERROR;
+    CAN_ID_map[ID_CURRENT_FLAG]         = (CAN_ID_t)INTERNAL_ID_CURRENT_FLAG;
+    CAN_ID_map[ID_PANEL_DEBUG_1]        = (CAN_ID_t)INTERNAL_ID_PANEL_DEBUG_1;
+    CAN_ID_map[ID_PANEL_DEBUG_2]        = (CAN_ID_t)INTERNAL_ID_PANEL_DEBUG_2;
+    CAN_ID_map[ID_PANEL_DEBUG_3]        = (CAN_ID_t)INTERNAL_ID_PANEL_DEBUG_3;
+    CAN_ID_map[ID_PANEL_DEBUG_4]        = (CAN_ID_t)INTERNAL_ID_PANEL_DEBUG_4;
+    CAN_ID_map[ID_REGEN_BRAKE_STATE]    = (CAN_ID_t)INTERNAL_ID_REGEN_BRAKE_STATE;
+    CAN_ID_map[ID_SPEED_L_MOTOR]        = (CAN_ID_t)INTERNAL_ID_SPEED_L_MOTOR;
+    CAN_ID_map[ID_SPEED_R_MOTOR]        = (CAN_ID_t)INTERNAL_ID_SPEED_R_MOTOR;
+    CAN_ID_map[ID_POWER_L_MOTOR]        = (CAN_ID_t)INTERNAL_ID_POWER_L_MOTOR;
+    CAN_ID_map[ID_POWER_R_MOTOR]        = (CAN_ID_t)INTERNAL_ID_POWER_R_MOTOR;
+    CAN_ID_map[ID_ENERGY_L_MOTOR]       = (CAN_ID_t)INTERNAL_ID_ENERGY_L_MOTOR;
+    CAN_ID_map[ID_ENERGY_R_MOTOR]       = (CAN_ID_t)INTERNAL_ID_ENERGY_R_MOTOR;
+    CAN_ID_map[ID_OVERLOAD_L_MOTOR]     = (CAN_ID_t)INTERNAL_ID_OVERLOAD_L_MOTOR;
+    CAN_ID_map[ID_OVERLOAD_R_MOTOR]     = (CAN_ID_t)INTERNAL_ID_OVERLOAD_R_MOTOR;
+    CAN_ID_map[ID_LOST_MSG_L_MOTOR]     = (CAN_ID_t)INTERNAL_ID_LOST_MSG_L_MOTOR;
+    CAN_ID_map[ID_LOST_MSG_R_MOTOR]     = (CAN_ID_t)INTERNAL_ID_LOST_MSG_R_MOTOR;
+    CAN_ID_map[ID_BUS_OFF_L_MOTOR]      = (CAN_ID_t)INTERNAL_ID_BUS_OFF_L_MOTOR;
+    CAN_ID_map[ID_BUS_OFF_R_MOTOR]      = (CAN_ID_t)INTERNAL_ID_BUS_OFF_R_MOTOR;
+    CAN_ID_map[ID_CAN_STATE_L_MOTOR]    = (CAN_ID_t)INTERNAL_ID_CAN_STATE_L_MOTOR;
+    CAN_ID_map[ID_CAN_STATE_R_MOTOR]    = (CAN_ID_t)INTERNAL_ID_CAN_STATE_R_MOTOR;
+    CAN_ID_map[ID_INV_STATE_L_MOTOR]    = (CAN_ID_t)INTERNAL_ID_INV_STATE_L_MOTOR;
+    CAN_ID_map[ID_INV_STATE_R_MOTOR]    = (CAN_ID_t)INTERNAL_ID_INV_STATE_R_MOTOR;
+    CAN_ID_map[ID_FAILURE_L_MOTOR]      = (CAN_ID_t)INTERNAL_ID_FAILURE_L_MOTOR;
+    CAN_ID_map[ID_FAILURE_R_MOTOR]      = (CAN_ID_t)INTERNAL_ID_FAILURE_R_MOTOR;
+    CAN_ID_map[ID_ALARM_L_MOTOR]        = (CAN_ID_t)INTERNAL_ID_ALARM_L_MOTOR;
+    CAN_ID_map[ID_ALARM_R_MOTOR]        = (CAN_ID_t)INTERNAL_ID_ALARM_R_MOTOR;
 
     // define um identificador unico a cada conjunto id & pos. Mapeia esse identificador
     // em outro vetor, para facil acesso posterior no datalog.

From 133028ea74abaa1e7c496785ae28a5d5d77bf70e Mon Sep 17 00:00:00 2001
From: caiussouza <caiuscsouza@gmail.com>
Date: Tue, 16 May 2023 15:43:05 -0300
Subject: [PATCH 33/33] ready for tests

---
 Core/Inc/sensors/sensor_data_processing.h     | 13 ++++++--
 .../CMSIS_extra/global_variables_handler.h    | 12 +++++--
 Core/Inc/util/global_definitions.h            | 10 +++---
 .../driver_settings/dynamic_controls_choice.c |  7 +++--
 .../dynamic_controls/security_architecture.c  | 22 +++++++------
 Core/Src/main.c                               |  2 +-
 Core/Src/sensors/sensor_data_processing.c     | 31 +++++++------------
 Core/Src/torque_command/torque_manager.c      | 20 ++++++------
 8 files changed, 64 insertions(+), 53 deletions(-)

diff --git a/Core/Inc/sensors/sensor_data_processing.h b/Core/Inc/sensors/sensor_data_processing.h
index 007ef4f8..9dfcc1b5 100644
--- a/Core/Inc/sensors/sensor_data_processing.h
+++ b/Core/Inc/sensors/sensor_data_processing.h
@@ -8,10 +8,19 @@
 #ifndef INC_SENSORS_SENSOR_DATA_PROCESSING_H_
 #define INC_SENSORS_SENSOR_DATA_PROCESSING_H_
 
+#include "stdbool.h"
 #include "stdint.h"
 
-#define BUFFER_SIZE 100
+#define MAX_BUFFER_SIZE 100
 
-void moving_average(float* mov_avg, float const* data);
+typedef struct {
+    float buffer[MAX_BUFFER_SIZE];
+    uint8_t index;
+    uint8_t size;
+    bool max_points_reached;
+} moving_average_t;
+
+// void moving_average(float* mov_avg, float const* data);
+float get_add_moving_average(moving_average_t* moving_average, float const data);
 
 #endif /* INC_SENSORS_SENSOR_DATA_PROCESSING_H_ */
diff --git a/Core/Inc/util/CMSIS_extra/global_variables_handler.h b/Core/Inc/util/CMSIS_extra/global_variables_handler.h
index 16fa66a2..bb3acfef 100644
--- a/Core/Inc/util/CMSIS_extra/global_variables_handler.h
+++ b/Core/Inc/util/CMSIS_extra/global_variables_handler.h
@@ -15,11 +15,14 @@
 typedef struct {
     uint16_t wheels[4];
 } SPEEDS_t;
+typedef struct {
+    int16_t accel_axes[3];
+} IMU_ACCEL_t;
+
 typedef uint16_t FRONT_AVG_SPEED_t;
 typedef uint16_t REAR_AVG_SPEED_t;
 typedef uint16_t STEERING_WHEEL_t;
 typedef uint16_t GYRO_YAW_t;
-typedef int16_t IMU_ACCEL_t;
 typedef uint8_t INTERNAL_WHEEL_t;
 typedef race_mode_t RACE_MODE_t;
 typedef uint16_t THROTTLE_PERCENT_t;
@@ -31,11 +34,14 @@ typedef modos SELECTED_MODE_t;
     {                                                                                    \
         { 0, 0, 0, 0 }                                                                   \
     }
+#define IMU_ACCEL_DEFAULT_VALUE                                                          \
+    {                                                                                    \
+        { 0, 0, 0 }                                                                      \
+    }
 #define FRONT_AVG_SPEED_DEFAULT_VALUE  0
 #define REAR_AVG_SPEED_DEFAULT_VALUE   0
 #define STEERING_WHEEL_DEFAULT_VALUE   0
 #define GYRO_YAW_DEFAULT_VALUE         0
-#define IMU_ACCEL_DEFAULT_VALUE        0
 #define INTERNAL_WHEEL_DEFAULT_VALUE   0
 #define RACE_MODE_DEFAULT_VALUE        ENDURO
 #define THROTTLE_PERCENT_DEFAULT_VALUE 0
@@ -46,12 +52,12 @@ typedef modos SELECTED_MODE_t;
 
 typedef enum {
     SPEEDS,
+    IMU_ACCEL,
     WHEEL_ENCODER_SPEEDS,
     FRONT_AVG_SPEED,
     REAR_AVG_SPEED,
     STEERING_WHEEL,
     GYRO_YAW,
-    IMU_ACCEL,
     INTERNAL_WHEEL,
     RACE_MODE,
     THROTTLE_PERCENT,
diff --git a/Core/Inc/util/global_definitions.h b/Core/Inc/util/global_definitions.h
index 5bf15bcd..c0534f39 100644
--- a/Core/Inc/util/global_definitions.h
+++ b/Core/Inc/util/global_definitions.h
@@ -28,7 +28,7 @@ typedef enum modos_desempenho {
     AUTOX
 } race_mode_t;
 
-typedef struct // struct de modo
+typedef struct        // struct de modo
 {
     int tor_max;      // torque maximo (de 0 a 4000)
     int vel_max;      // velocidade maxima (de 0 a 9000)
@@ -119,12 +119,12 @@ typedef enum {
 #define GENERAL_BUS_OFF_ERROR_FLAG (1 << 1)
 #define INVERTER_READY_FLAG        (1 << 2)
 #define DYNAMIC_CONTROL_FLAG       (1 << 3)
-#define CROSS_VALIDATION_FLAG      (1 << 4)
 
 // Warning flags	(No actions necessary)
-#define REGEN_WARN_FLAG           (1 << 10)
-#define DYNAMIC_CONTROL_WARN_FLAG (1 << 11)
-#define FLASH_SAVE_LIMIT_FLAG     (1 << 12)
+#define REGEN_WARN_FLAG                  (1 << 10)
+#define DYNAMIC_CONTROL_WARN_FLAG        (1 << 11)
+#define FLASH_SAVE_LIMIT_FLAG            (1 << 12)
+#define CROSS_VALIDATION_ERROR_WARN_FLAG (1 << 13)
 // Soft error flags (RTD keeps on, torque ref to inverter is set to 0)
 
 #define BSE_ERROR_FLAG  (1 << 16) // FSAE Rules: EV.5.7 (2021)
diff --git a/Core/Src/driver_settings/dynamic_controls_choice.c b/Core/Src/driver_settings/dynamic_controls_choice.c
index 7f045b23..7a31f546 100644
--- a/Core/Src/driver_settings/dynamic_controls_choice.c
+++ b/Core/Src/driver_settings/dynamic_controls_choice.c
@@ -28,12 +28,13 @@ void dynamic_controls_choice(void* argument) {
         if (is_RTD_active()) {
             continue;
         }
-        const bool is_DYNAMIC_CONTROL_active =
+        const bool is_dynamic_control_active =
             get_individual_flag(e_ECU_control_flagsHandle, DYNAMIC_CONTROL_FLAG);
 
-        if (!is_DYNAMIC_CONTROL_active) {
+        if (!is_dynamic_control_active) {
             osEventFlagsSet(e_ECU_control_flagsHandle, DYNAMIC_CONTROL_FLAG);
-            osEventFlagsClear(e_ECU_control_flagsHandle, CROSS_VALIDATION_FLAG);
+            osEventFlagsClear(e_ECU_control_flagsHandle,
+                              CROSS_VALIDATION_ERROR_WARN_FLAG);
         } else {
             osEventFlagsClear(e_ECU_control_flagsHandle, DYNAMIC_CONTROL_FLAG);
         }
diff --git a/Core/Src/dynamic_controls/security_architecture.c b/Core/Src/dynamic_controls/security_architecture.c
index 685250cb..6eb7df6b 100644
--- a/Core/Src/dynamic_controls/security_architecture.c
+++ b/Core/Src/dynamic_controls/security_architecture.c
@@ -13,10 +13,13 @@
 #include "util/global_instances.h"
 #include "util/util.h"
 
-static float speed_mov_avg;
-static float IMU_long_accel_mov_avg;
+static moving_average_t speed_mov_avg;
+static moving_average_t IMU_long_accel_mov_avg;
 static BRAKE_STATUS_t bse_active;
 
+static float speed_mov_ave_value; // fazer pros 4 sensores
+static float IMU_long_accel_mov_ave_value;
+
 static bool imu_bse_error_status;
 static bool imu_speed_error_status;
 
@@ -30,13 +33,14 @@ void cross_validation(void* argument) {
         float speed_data          = (float)get_global_var_value(REAR_AVG_SPEED);
         bse_active                = get_global_var_value(BRAKE_STATUS);
 
-        moving_average(&IMU_long_accel_mov_avg, &IMU_long_accel_data);
-        moving_average(&speed_mov_avg, &speed_data);
+        IMU_long_accel_mov_ave_value =
+            get_add_moving_average(&IMU_long_accel_mov_avg, IMU_long_accel_data);
+        speed_mov_ave_value = get_add_moving_average(&speed_mov_avg, speed_data);
 
         imu_bse_error_status   = is_there_imu_bse_error();
         imu_speed_error_status = is_there_imu_speed_error();
 
-        if (is_there_imu_bse_error() || is_there_imu_speed_error()) {
+        if (imu_bse_error_status || imu_speed_error_status) {
             osTimerStart(tim_cross_validation_errorHandle, CROSS_VALIDATION_ERROR_TIME);
         }
 
@@ -49,22 +53,22 @@ void cross_validation(void* argument) {
 }
 
 bool is_there_imu_bse_error() {
-    if (bse_active && (IMU_long_accel_mov_avg > IMU_NULL_ACCEL_MARGIN_ERROR)) {
+    if (bse_active && (IMU_long_accel_mov_ave_value > IMU_NULL_ACCEL_MARGIN_ERROR)) {
         return true;
     }
     return false;
 }
 
 bool is_there_imu_speed_error() {
-    if ((speed_mov_avg < NULL_SPEED_MARGIN_ERROR)
-        && (IMU_long_accel_mov_avg > IMU_NULL_ACCEL_MARGIN_ERROR)) {
+    if ((speed_mov_ave_value < NULL_SPEED_MARGIN_ERROR)
+        && (IMU_long_accel_mov_ave_value > IMU_NULL_ACCEL_MARGIN_ERROR)) {
         return true;
     }
     return false;
 }
 
 void cross_validation_error_callback() {
-    osEventFlagsSet(e_ECU_control_flagsHandle, CROSS_VALIDATION_FLAG);
+    osEventFlagsSet(e_ECU_control_flagsHandle, CROSS_VALIDATION_ERROR_WARN_FLAG);
 }
 
 void cross_validation_status_datalog() {
diff --git a/Core/Src/main.c b/Core/Src/main.c
index 1b5a7627..505c04a8 100644
--- a/Core/Src/main.c
+++ b/Core/Src/main.c
@@ -461,7 +461,7 @@ int main(void)
   tim_right_inv_errorHandle = osTimerNew(right_inv_error_callback, osTimerPeriodic, (void*) RIGHT_INVERTER_COMM_ERROR_FLAG, &tim_right_inv_error_attributes);
 
   /* creation of tim_cross_validation_error */
-  tim_cross_validation_errorHandle = osTimerNew(cross_validation_error_callback, osTimerPeriodic, (void*) CROSS_VALIDATION_FLAG, &tim_cross_validation_error_attributes);
+  tim_cross_validation_errorHandle = osTimerNew(cross_validation_error_callback, osTimerPeriodic, (void*) CROSS_VALIDATION_ERROR_WARN_FLAG, &tim_cross_validation_error_attributes);
 
   /* USER CODE BEGIN RTOS_TIMERS */
   /* start timers, add new ones, ... */
diff --git a/Core/Src/sensors/sensor_data_processing.c b/Core/Src/sensors/sensor_data_processing.c
index e79584e6..7f6064ca 100644
--- a/Core/Src/sensors/sensor_data_processing.c
+++ b/Core/Src/sensors/sensor_data_processing.c
@@ -7,28 +7,19 @@
 
 #include "sensors/sensor_data_processing.h"
 
-// TODO(caius): It generalizes moving average service implementing this sketch, allowing
-// different types. It implements a general circular buffer as well.
+float get_add_moving_average(moving_average_t* moving_average, float const data) {
+    float buffer_sum                              = 0;
+    moving_average->buffer[moving_average->index] = data;
 
-static uint8_t buffer_index              = 0;
-static float buffer_sum                  = 0;
-static float mov_avg_buffer[BUFFER_SIZE] = {0};
-
-void moving_average(float* mov_avg, float const* data) {
-
-    *mov_avg                     = 0;
-    mov_avg_buffer[buffer_index] = *data;
-    buffer_index                 = (buffer_index + 1) % BUFFER_SIZE;
-
-    // TODO(caius): It requires empirical tests for choosing that value
-    for (uint8_t i = 0; i < BUFFER_SIZE; i++) {
-        buffer_sum += mov_avg_buffer[i];
+    if (++moving_average->index == moving_average->size) {
+        moving_average->index              = 0;
+        moving_average->max_points_reached = true;
     }
-    *mov_avg = buffer_sum / (float)BUFFER_SIZE;
+    const uint8_t current_size =
+        moving_average->max_points_reached ? moving_average->size : moving_average->index;
 
-    // Avoid variable type overflow
-    buffer_sum = 0;
-    if (buffer_index == 255) {
-        buffer_index = 0;
+    for (uint8_t i = 0; i < current_size; ++i) {
+        buffer_sum += moving_average->buffer[i];
     }
+    return (buffer_sum / current_size);
 }
diff --git a/Core/Src/torque_command/torque_manager.c b/Core/Src/torque_command/torque_manager.c
index 3849c095..fb7ddd88 100644
--- a/Core/Src/torque_command/torque_manager.c
+++ b/Core/Src/torque_command/torque_manager.c
@@ -31,17 +31,17 @@ void torque_manager(void* argument) {
 
         void rampa_torque(uint32_t * ref_torque, const double* ref_torque_decrease);
         void send_ref_torque_message(const uint32_t* ref_torque);
-        void select_dynamic_control(bool is_DYNAMIC_CONTROL_active,
-                                    bool is_there_CROSS_VALIDATION_error);
+        void select_dynamic_control(bool is_dynamic_control_active,
+                                    bool is_there_cross_validation_error);
 
-        const bool is_DYNAMIC_CONTROL_active =
+        const bool is_dynamic_control_active =
             get_individual_flag(e_ECU_control_flagsHandle, DYNAMIC_CONTROL_FLAG);
         get_individual_flag(e_ECU_control_flagsHandle, DYNAMIC_CONTROL_FLAG);
-        const bool is_there_CROSS_VALIDATION_error =
-            get_individual_flag(e_ECU_control_flagsHandle, CROSS_VALIDATION_FLAG);
+        const bool is_there_cross_validation_error = get_individual_flag(
+            e_ECU_control_flagsHandle, CROSS_VALIDATION_ERROR_WARN_FLAG);
 
-        select_dynamic_control(is_DYNAMIC_CONTROL_active,
-                               is_there_CROSS_VALIDATION_error);
+        select_dynamic_control(is_dynamic_control_active,
+                               is_there_cross_validation_error);
 
         // todo (João Pedro): add new "case's" when the integration of controls is
         // implemented
@@ -121,10 +121,10 @@ void send_ref_torque_message(const uint32_t* ref_torque) {
     osMessageQueuePut(q_ref_torque_messageHandle, &ref_torque_message, 0, 0U);
 }
 
-void select_dynamic_control(bool is_DYNAMIC_CONTROL_active,
-                            bool is_there_CROSS_VALIDATION_error) {
+void select_dynamic_control(bool is_dynamic_control_active,
+                            bool is_there_cross_validation_error) {
     // todo (João Pedro): add new "if's" when the integration of controls is implemented
-    if (is_DYNAMIC_CONTROL_active && !is_there_CROSS_VALIDATION_error) {
+    if (is_dynamic_control_active && !is_there_cross_validation_error) {
         if (get_global_var_value(SELECTED_MODE).dif_elt == 1
             && get_global_var_value(SELECTED_MODE).traction_control == 0) {
             g_control_type = LATERAL;