Summary
There are two different issues depending on the boot method:
- ACPI boot
- CPU topology is detected correctly.
- CPU frequencies are reported correctly.
- L1, L2, and L3 cache information is missing from both lscpu and hwloc.
- Device Tree (DTB) boot
- L1, L2, and L3 cache information is exposed correctly.
- CPU frequency information becomes incorrect and reports bogus values.
It seems that neither boot method currently exposes all CPU topology information correctly.
Hardware
- Board: Orange Pi 6 Plus
- SoC: CIX Sky1 / CD8180 (CD8160 compatible branding)
- CPU: 8x Cortex-A720 + 4x Cortex-A520
- Firmware: SystemReady ACPI firmware
- Kernel: 6.19.14
Expected CPU frequencies
According to the board specifications, the CPU frequencies should be approximately:
- Cortex-A720 cluster: up to 2.6 GHz
- Cortex-A520 cluster: up to 1.8 GHz
These frequencies are reported correctly when booting with ACPI
Problem 1: ACPI mode
lscpu and hwloc do not report cache hierarchy information.
Expected:
- L1d cache
- L1i cache
- L2 cache
- L3 cache
Actual:
Cache information is missing entirely.
This also affects tools such as hwloc-ls and lstopo, which cannot build the proper cache topology.
Problem 2: Device Tree mode
When booting using a DTB file, cache information becomes available and is reported correctly.
However, CPU frequencies become incorrect and show unrealistic values.
Example:
Expected:
- Cortex-A720: 2.6 GHz
- Cortex-A520: 1.8 GHz
Actual:
- Cortex-A720: 1.5 GHz
- Cortex-A520: 1.8 GHz
Reproduction
ACPI boot
lscpu
lstopo
hwloc-info
Device Tree boot
lscpu
lstopo
hwloc-info
Question
It looks like the cache hierarchy information exists in the Device Tree but is not exposed properly through ACPI, while the CPU frequency information behaves in the opposite way.
Could this be caused by:
- incomplete PPTT (Processor Properties Topology Table) information in ACPI?
- missing cache nodes in the ACPI tables?
- incorrect OPP or cpufreq information in the Device Tree?
- missing cache descriptors in firmware?
Summary
There are two different issues depending on the boot method:
It seems that neither boot method currently exposes all CPU topology information correctly.
Hardware
Expected CPU frequencies
According to the board specifications, the CPU frequencies should be approximately:
These frequencies are reported correctly when booting with ACPI
Problem 1: ACPI mode
lscpu and hwloc do not report cache hierarchy information.
Expected:
Actual:
Cache information is missing entirely.
This also affects tools such as hwloc-ls and lstopo, which cannot build the proper cache topology.
Problem 2: Device Tree mode
When booting using a DTB file, cache information becomes available and is reported correctly.
However, CPU frequencies become incorrect and show unrealistic values.
Example:
Expected:
Actual:
Reproduction
ACPI boot
lscpu
lstopo
hwloc-info
Device Tree boot
lscpu
lstopo
hwloc-info
Question
It looks like the cache hierarchy information exists in the Device Tree but is not exposed properly through ACPI, while the CPU frequency information behaves in the opposite way.
Could this be caused by: