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[TASK] Add Initial RISC-V AME Support to LLVM #21

Description

@zhanghb97

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Task Description

Based on the RISC-V Attached Matrix Extension specification:

Add initial AME support to the LLVM RISC-V backend, including:

  1. AME target feature support.
  2. Matrix register definitions.
  3. AME instruction definitions and encodings.
  4. Intrinsic support.
  5. Other required components.

The implementation should cover a representative set of AME instructions and provide a foundation for completing the remaining instruction support.

Timeline

  • Coding Phase: 2026-07-13 – 2026-07-19
  • Code Review Begins: 2026-07-20

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