Deliverables
- A pull request adding initial RISC-V AME backend support to:
- Tests for the implemented AME instructions.
Task Description
Based on the RISC-V Attached Matrix Extension specification:
Add initial AME support to the LLVM RISC-V backend, including:
- AME target feature support.
- Matrix register definitions.
- AME instruction definitions and encodings.
- Intrinsic support.
- Other required components.
The implementation should cover a representative set of AME instructions and provide a foundation for completing the remaining instruction support.
Timeline
- Coding Phase: 2026-07-13 – 2026-07-19
- Code Review Begins: 2026-07-20
Deliverables
Task Description
Based on the RISC-V Attached Matrix Extension specification:
Add initial AME support to the LLVM RISC-V backend, including:
The implementation should cover a representative set of AME instructions and provide a foundation for completing the remaining instruction support.
Timeline