From 812a996eea25a5ee4c80bc6106cd522f778fa1a3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Duje=20Mihanovi=C4=87?= Date: Sun, 7 Jan 2024 12:46:59 +0100 Subject: [PATCH 1/7] dt-bindings: pxa-pwm: Convert to YAML MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit mainline inclusion from mainline-v6.9-rc1 commit bdc585f987a0 ("dt-bindings: pxa-pwm: Convert to YAML") category: feature bugzilla: https://github.com/RVCK-Project/rvck/issues/317 -------------------------------- Convert the PXA PWM binding file from TXT to YAML. The original binding does not mention any clocks, but the PWM controller will not probe without a clock. Reviewed-by: Uwe Kleine-König Signed-off-by: Duje Mihanović Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240107-pxa-pwm-yaml-v3-1-92ac90911c3f@skole.hr Signed-off-by: Uwe Kleine-König Signed-off-by: Yongchao Jia --- .../bindings/pwm/marvell,pxa-pwm.yaml | 51 +++++++++++++++++++ .../devicetree/bindings/pwm/pxa-pwm.txt | 30 ----------- 2 files changed, 51 insertions(+), 30 deletions(-) create mode 100644 Documentation/devicetree/bindings/pwm/marvell,pxa-pwm.yaml delete mode 100644 Documentation/devicetree/bindings/pwm/pxa-pwm.txt diff --git a/Documentation/devicetree/bindings/pwm/marvell,pxa-pwm.yaml b/Documentation/devicetree/bindings/pwm/marvell,pxa-pwm.yaml new file mode 100644 index 0000000000000..ba6325575ea04 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/marvell,pxa-pwm.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/marvell,pxa-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell PXA PWM + +maintainers: + - Duje Mihanović + +allOf: + - $ref: pwm.yaml# + +properties: + compatible: + enum: + - marvell,pxa250-pwm + - marvell,pxa270-pwm + - marvell,pxa168-pwm + - marvell,pxa910-pwm + + reg: + # Length should be 0x10 + maxItems: 1 + + "#pwm-cells": + # Used for specifying the period length in nanoseconds + const: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - "#pwm-cells" + - clocks + +additionalProperties: false + +examples: + - | + #include + + pwm0: pwm@40b00000 { + compatible = "marvell,pxa250-pwm"; + reg = <0x40b00000 0x10>; + #pwm-cells = <1>; + clocks = <&clks CLK_PWM0>; + }; diff --git a/Documentation/devicetree/bindings/pwm/pxa-pwm.txt b/Documentation/devicetree/bindings/pwm/pxa-pwm.txt deleted file mode 100644 index 5ae9f1e3c3389..0000000000000 --- a/Documentation/devicetree/bindings/pwm/pxa-pwm.txt +++ /dev/null @@ -1,30 +0,0 @@ -Marvell PWM controller - -Required properties: -- compatible: should be one or more of: - - "marvell,pxa250-pwm" - - "marvell,pxa270-pwm" - - "marvell,pxa168-pwm" - - "marvell,pxa910-pwm" -- reg: Physical base address and length of the registers used by the PWM channel - Note that one device instance must be created for each PWM that is used, so the - length covers only the register window for one PWM output, not that of the - entire PWM controller. Currently length is 0x10 for all supported devices. -- #pwm-cells: Should be 1. This cell is used to specify the period in - nanoseconds. - -Example PWM device node: - -pwm0: pwm@40b00000 { - compatible = "marvell,pxa250-pwm"; - reg = <0x40b00000 0x10>; - #pwm-cells = <1>; -}; - -Example PWM client node: - -backlight { - compatible = "pwm-backlight"; - pwms = <&pwm0 5000000>; - ... -} From 306782ee0a6f7a3d31d4e4346a3aee78b6ab8116 Mon Sep 17 00:00:00 2001 From: Binbin Zhou Date: Tue, 30 Apr 2024 15:32:04 +0800 Subject: [PATCH 2/7] dt-bindings: pwm: marvell,pxa: Do not require pwm-cells twice MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit mainline inclusion from mainline-v6.10-rc1 commit b3d8d1205104 ("dt-bindings: pwm: marvell,pxa: Do not require pwm-cells twice") category: feature bugzilla: https://github.com/RVCK-Project/rvck/issues/317 -------------------------------- pwm-cells property is already required by pwm.yaml schema. Signed-off-by: Binbin Zhou Acked-by: Conor Dooley Link: https://lore.kernel.org/r/06765e0dd9a842dc51ff9c9cea93f26b8792e44b.1714450308.git.zhoubinbin@loongson.cn Signed-off-by: Uwe Kleine-König Signed-off-by: Yongchao Jia --- Documentation/devicetree/bindings/pwm/marvell,pxa-pwm.yaml | 1 - 1 file changed, 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pwm/marvell,pxa-pwm.yaml b/Documentation/devicetree/bindings/pwm/marvell,pxa-pwm.yaml index ba6325575ea04..9ee1946dc2e12 100644 --- a/Documentation/devicetree/bindings/pwm/marvell,pxa-pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/marvell,pxa-pwm.yaml @@ -34,7 +34,6 @@ properties: required: - compatible - reg - - "#pwm-cells" - clocks additionalProperties: false From bd8862d594f27f84ed1a6daff2c3822f9d6ec1dd Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Tue, 29 Apr 2025 16:50:43 +0800 Subject: [PATCH 3/7] dt-bindings: pwm: marvell,pxa-pwm: Add SpacemiT K1 PWM support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit mainline inclusion from mainline-v6.17-rc1 commit 08e0b981231f ("dt-bindings: pwm: marvell,pxa-pwm: Add SpacemiT K1 PWM support") category: feature bugzilla: https://github.com/RVCK-Project/rvck/issues/317 -------------------------------- The SpacemiT K1 SoC reuses the Marvell PXA910-compatible PWM controller with one notable difference: the addition of a resets property. To make the device tree pass schema validation (make dtbs_check W=3), this patch updates the binding to accept spacemit,k1-pwm as a compatible string, when used in conjunction with the fallback marvell,pxa910-pwm. Support for the optional resets property is also added, as it is required by the K1 integration but was not present in the original Marvell bindings. Since the PWM reset line may be deasserted during the early bootloader stage, making the resets property optional avoids potential double-deassertion, which could otherwise cause flickering on displays that use PWM for backlight control. Additionally, this patch adjusts the required value of the #pwm-cells property for the new compatible string: - For "spacemit,k1-pwm", #pwm-cells must be set to 3. - For existing Marvell compatibles, #pwm-cells remains 1. Background of #pwm-cells change is by an ongoing community discussion about increasing the #pwm-cells value from 1 to 3 for all Marvell PXA PWM devices. These devices are currently the only ones whose bindings do not pass the line index as the first argument. See [1] for further details. [1] https://lore.kernel.org/all/cover.1738842938.git.u.kleine-koenig@baylibre.com/ Reviewed-by: Rob Herring (Arm) # v2 Signed-off-by: Guodong Xu Link: https://lore.kernel.org/r/20250429085048.1310409-2-guodong@riscstar.com Signed-off-by: Uwe Kleine-König Signed-off-by: Yongchao Jia --- .../bindings/pwm/marvell,pxa-pwm.yaml | 35 +++++++++++++++---- 1 file changed, 28 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/pwm/marvell,pxa-pwm.yaml b/Documentation/devicetree/bindings/pwm/marvell,pxa-pwm.yaml index 9ee1946dc2e12..8df327e528107 100644 --- a/Documentation/devicetree/bindings/pwm/marvell,pxa-pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/marvell,pxa-pwm.yaml @@ -11,26 +11,47 @@ maintainers: allOf: - $ref: pwm.yaml# + - if: + properties: + compatible: + contains: + const: spacemit,k1-pwm + then: + properties: + "#pwm-cells": + const: 3 + else: + properties: + "#pwm-cells": + const: 1 + description: | + Used for specifying the period length in nanoseconds. properties: compatible: - enum: - - marvell,pxa250-pwm - - marvell,pxa270-pwm - - marvell,pxa168-pwm - - marvell,pxa910-pwm + oneOf: + - enum: + - marvell,pxa250-pwm + - marvell,pxa270-pwm + - marvell,pxa168-pwm + - marvell,pxa910-pwm + - items: + - const: spacemit,k1-pwm + - const: marvell,pxa910-pwm reg: # Length should be 0x10 maxItems: 1 "#pwm-cells": - # Used for specifying the period length in nanoseconds - const: 1 + description: Number of cells in a pwm specifier. clocks: maxItems: 1 + resets: + maxItems: 1 + required: - compatible - reg From eec8806e0e34ea2421e31eb2e67f09b260761726 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Tue, 28 Apr 2026 10:46:50 +0000 Subject: [PATCH 4/7] dt-bindings: pwm: marvell,pxa-pwm: Add SpacemiT K3 PWM support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit mainline inclusion from mainline-v7.2-rc1 commit e7abbff5e8b2 category: feature bugzilla: https://github.com/RVCK-Project/rvck/issues/317 -------------------------------- The PWM controller in SpacemiT K3 SoC reuse the same IP as previous K1 generation, while the difference is that one additional bus clock is added. Signed-off-by: Yixun Lan Acked-by: Conor Dooley Link: https://patch.msgid.link/20260428-03-k3-pwm-drv-v2-1-a532bbe45556@kernel.org Signed-off-by: Uwe Kleine-König Signed-off-by: Yongchao Jia --- .../bindings/pwm/marvell,pxa-pwm.yaml | 41 +++++++++++++++++-- 1 file changed, 38 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/pwm/marvell,pxa-pwm.yaml b/Documentation/devicetree/bindings/pwm/marvell,pxa-pwm.yaml index 8df327e528107..f1422a401b6ba 100644 --- a/Documentation/devicetree/bindings/pwm/marvell,pxa-pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/marvell,pxa-pwm.yaml @@ -15,7 +15,9 @@ allOf: properties: compatible: contains: - const: spacemit,k1-pwm + enum: + - spacemit,k1-pwm + - spacemit,k3-pwm then: properties: "#pwm-cells": @@ -26,6 +28,26 @@ allOf: const: 1 description: | Used for specifying the period length in nanoseconds. + - if: + properties: + compatible: + contains: + enum: + - spacemit,k3-pwm + then: + required: + - clock-names + properties: + clocks: + minItems: 2 + clock-names: + minItems: 2 + else: + properties: + clocks: + maxItems: 1 + clock-names: + maxItems: 1 properties: compatible: @@ -36,7 +58,9 @@ properties: - marvell,pxa168-pwm - marvell,pxa910-pwm - items: - - const: spacemit,k1-pwm + - enum: + - spacemit,k1-pwm + - spacemit,k3-pwm - const: marvell,pxa910-pwm reg: @@ -47,7 +71,18 @@ properties: description: Number of cells in a pwm specifier. clocks: - maxItems: 1 + minItems: 1 + items: + - description: The function clock + - description: An optional bus clock + + clock-names: + minItems: 1 + maxItems: 2 + oneOf: + - items: + - const: func + - const: bus resets: maxItems: 1 From 80c7936bc094b0350c749f465a150f9e5ef3b950 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Tue, 28 Apr 2026 10:46:51 +0000 Subject: [PATCH 5/7] pwm: pxa: Add optional bus clock MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit mainline inclusion from mainline-7.2-rc1 commit 74bca0f category: feature bugzilla: https://github.com/RVCK-Project/rvck/issues/317 -------------------------------- Add one secondary optional bus clock for the PWM PXA driver, also keep it compatible with old single clock. The SpacemiT K3 SoC require a bus clock for PWM controller, acquire and enable it during probe phase. Signed-off-by: Yixun Lan Link: https://patch.msgid.link/20260428-03-k3-pwm-drv-v2-2-a532bbe45556@kernel.org Signed-off-by: Uwe Kleine-König Signed-off-by: Yongchao Jia --- drivers/pwm/pwm-pxa.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/pwm/pwm-pxa.c b/drivers/pwm/pwm-pxa.c index 2a0b0d75f1bd9..6e406cb3382f4 100644 --- a/drivers/pwm/pwm-pxa.c +++ b/drivers/pwm/pwm-pxa.c @@ -164,6 +164,8 @@ static int pwm_probe(struct platform_device *pdev) { const struct platform_device_id *id = platform_get_device_id(pdev); struct pxa_pwm_chip *pc; + struct clk *bus_clk; + struct device *dev = &pdev->dev; int ret = 0; if (IS_ENABLED(CONFIG_OF) && id == NULL) @@ -176,7 +178,12 @@ static int pwm_probe(struct platform_device *pdev) if (pc == NULL) return -ENOMEM; - pc->clk = devm_clk_get(&pdev->dev, NULL); + bus_clk = devm_clk_get_optional_enabled(dev, "bus"); + if (IS_ERR(bus_clk)) + return dev_err_probe(dev, PTR_ERR(bus_clk), "Failed to get bus clock\n"); + + /* Get named func clk if bus clock is valid */ + pc->clk = devm_clk_get(dev, bus_clk ? "func" : NULL); if (IS_ERR(pc->clk)) return PTR_ERR(pc->clk); From f020e13d946eca52b038aa218f67d0cadf5b9a64 Mon Sep 17 00:00:00 2001 From: Yongchao Jia Date: Thu, 2 Jul 2026 17:17:24 +0800 Subject: [PATCH 6/7] pwm: pxa: Adapt SpacemiT K3 PWM support rvck inclusion category: feature bugzilla: https://github.com/RVCK-Project/rvck/issues/317 -------------------------------- This commit adapts the upstream SpacemiT K3 PWM backport to make it compile and work correctly on our older v6.6 kernel base. Since the upstream patches are based on a newer kernel tree (v7.2), applying them directly caused context conflicts and API mismatches. This commit resolves those issues to ensure a clean build. Adaptation details: - Adjusted the clock and reset control initialization sequences to match the v6.6 driver structure. - Removed dependencies on v7.2 specific macros and structures that do not exist in our tree. - Manually resolved conflicts in drivers/pwm/pwm-pxa.c due to differences in the original file layout. Signed-off-by: Yongchao Jia --- drivers/pwm/pwm-pxa.c | 57 +++++++++++++++++-------------------------- 1 file changed, 23 insertions(+), 34 deletions(-) diff --git a/drivers/pwm/pwm-pxa.c b/drivers/pwm/pwm-pxa.c index 6e406cb3382f4..6c2ae36e89bbc 100644 --- a/drivers/pwm/pwm-pxa.c +++ b/drivers/pwm/pwm-pxa.c @@ -22,10 +22,10 @@ #include #include #include -#include #include #include -#include +#include +#include #include @@ -54,7 +54,6 @@ struct pxa_pwm_chip { struct device *dev; struct clk *clk; - struct reset_control *reset; void __iomem *mmio_base; }; @@ -137,7 +136,6 @@ static int pxa_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, static const struct pwm_ops pxa_pwm_ops = { .apply = pxa_pwm_apply, - .owner = THIS_MODULE, }; #ifdef CONFIG_OF @@ -152,7 +150,6 @@ static const struct of_device_id pwm_of_match[] = { { .compatible = "marvell,pxa270-pwm", .data = &pwm_id_table[0]}, { .compatible = "marvell,pxa168-pwm", .data = &pwm_id_table[0]}, { .compatible = "marvell,pxa910-pwm", .data = &pwm_id_table[0]}, - { .compatible = "spacemit,k1-pwm", .data = &pwm_id_table[0]}, { } }; MODULE_DEVICE_TABLE(of, pwm_of_match); @@ -163,20 +160,23 @@ MODULE_DEVICE_TABLE(of, pwm_of_match); static int pwm_probe(struct platform_device *pdev) { const struct platform_device_id *id = platform_get_device_id(pdev); + struct pwm_chip *chip; struct pxa_pwm_chip *pc; struct clk *bus_clk; struct device *dev = &pdev->dev; + struct reset_control *rst; int ret = 0; if (IS_ENABLED(CONFIG_OF) && id == NULL) - id = of_device_get_match_data(&pdev->dev); + id = of_device_get_match_data(dev); if (id == NULL) return -EINVAL; - pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL); + pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL); if (pc == NULL) return -ENOMEM; + chip = &pc->chip; bus_clk = devm_clk_get_optional_enabled(dev, "bus"); if (IS_ERR(bus_clk)) @@ -185,43 +185,31 @@ static int pwm_probe(struct platform_device *pdev) /* Get named func clk if bus clock is valid */ pc->clk = devm_clk_get(dev, bus_clk ? "func" : NULL); if (IS_ERR(pc->clk)) - return PTR_ERR(pc->clk); + return dev_err_probe(dev, PTR_ERR(pc->clk), "Failed to get clock\n"); - pc->reset = devm_reset_control_get_optional(&pdev->dev, NULL); - if (!IS_ERR(pc->reset)) - reset_control_deassert(pc->reset); + rst = devm_reset_control_get_optional_exclusive(dev, NULL); + if (IS_ERR(rst)) + return PTR_ERR(rst); + reset_control_deassert(rst); - pc->chip.dev = &pdev->dev; - pc->chip.ops = &pxa_pwm_ops; - pc->chip.npwm = (id->driver_data & HAS_SECONDARY_PWM) ? 2 : 1; + chip->dev = dev; + chip->ops = &pxa_pwm_ops; + chip->npwm = (id->driver_data & HAS_SECONDARY_PWM) ? 2 : 1; - if (IS_ENABLED(CONFIG_OF)) { - pc->chip.of_xlate = of_pwm_single_xlate; - pc->chip.of_pwm_n_cells = 1; - } + if (IS_ENABLED(CONFIG_OF)) + chip->of_xlate = of_pwm_single_xlate; pc->mmio_base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(pc->mmio_base)) { - ret = PTR_ERR(pc->mmio_base); - goto err_rst; - } + if (IS_ERR(pc->mmio_base)) + return PTR_ERR(pc->mmio_base); - ret = devm_pwmchip_add(&pdev->dev, &pc->chip); - if (ret < 0) { - dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret); - goto err_rst; - } + ret = devm_pwmchip_add(dev, chip); + if (ret < 0) + return dev_err_probe(dev, ret, "pwmchip_add() failed\n"); return 0; - -err_rst: - if (!IS_ERR(pc->reset)) - reset_control_assert(pc->reset); - - return ret; } - static struct platform_driver pwm_driver = { .driver = { .name = "pxa25x-pwm", @@ -233,4 +221,5 @@ static struct platform_driver pwm_driver = { module_platform_driver(pwm_driver); +MODULE_DESCRIPTION("PXA Pulse Width Modulator driver"); MODULE_LICENSE("GPL v2"); From eb1eddeb8616df7d04d289d9c65b92f511eb1249 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Thu, 2 Jul 2026 17:17:24 +0800 Subject: [PATCH 7/7] riscv: dts: spacemit: k3: Add pwm support mainline inclusion from mainline-7.2-rc1 commit 844c291 category: feature bugzilla: https://github.com/RVCK-Project/rvck/issues/317 -------------------------------- Populate all pwm device tree nodes for SpacemiT K3 SoC, also documents the pinctrl info which would easily help to enable them in future. Link: https://lore.kernel.org/all/20260521-04-k3-pwm-dts-v4-1-04d4de0f2fc8@kernel.org Signed-off-by: Yixun Lan Signed-off-by: Yongchao Jia --- arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi | 376 +++++++++++-------- arch/riscv/boot/dts/spacemit/k3.dtsi | 220 +++++++++++ 2 files changed, 438 insertions(+), 158 deletions(-) diff --git a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi index 6e0c741b0ca26..462bad4b072c7 100644 --- a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi +++ b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi @@ -811,537 +811,597 @@ }; }; + /omit-if-no-ref/ pwm0_0_cfg: pwm0-0-cfg { pwm0-0-pins { pinmux = ; /* pwm0 */ - bias-pull-up; /* normal pull-up */ - drive-strength = <25>; /* DS8 */ + bias-pull-up = <0>; + drive-strength = <25>; }; }; + /omit-if-no-ref/ pwm0_1_cfg: pwm0-1-cfg { - pwm0-0-pins { + pwm0-1-pins { pinmux = ; /* pwm0 */ - bias-pull-up; /* normal pull-up */ - drive-strength = <25>; /* DS8 */ + bias-pull-up = <0>; + drive-strength = <25>; }; }; + /omit-if-no-ref/ pwm1_0_cfg: pwm1-0-cfg { pwm1-0-pins { pinmux = ; /* pwm1 */ - bias-pull-up; /* normal pull-up */ - drive-strength = <25>; /* DS8 */ + bias-pull-up = <0>; + drive-strength = <25>; }; }; - pwm1_1_cfg: pwm0-0-cfg { - pwm0-0-pins { + /omit-if-no-ref/ + pwm1_1_cfg: pwm1-1-cfg { + pwm1-1-pins { pinmux = ; /* pwm1 */ - bias-pull-up; /* normal pull-up */ - drive-strength = <25>; /* DS8 */ + bias-pull-up = <0>; + drive-strength = <25>; }; }; + /omit-if-no-ref/ pwm1_2_cfg: pwm1-2-cfg { - pwm1-0-pins { + pwm1-2-pins { pinmux = ; /* pwm1 */ - bias-pull-up; /* normal pull-up */ - drive-strength = <25>; /* DS8 */ + bias-pull-up = <0>; + drive-strength = <25>; }; }; + /omit-if-no-ref/ pwm2_0_cfg: pwm2-0-cfg { pwm2-0-pins { pinmux = ; /* pwm2 */ - bias-pull-up; /* normal pull-up */ - drive-strength = <25>; /* DS8 */ + bias-pull-up = <0>; + drive-strength = <25>; }; }; + /omit-if-no-ref/ pwm2_1_cfg: pwm2-1-cfg { - pwm2-0-pins { + pwm2-1-pins { pinmux = ; /* pwm2 */ - bias-pull-up; /* normal pull-up */ - drive-strength = <25>; /* DS8 */ + bias-pull-up = <0>; + drive-strength = <25>; }; }; + /omit-if-no-ref/ pwm2_2_cfg: pwm2-2-cfg { - pwm2-0-pins { + pwm2-2-pins { pinmux = ; /* pwm2 */ - bias-pull-up; /* normal pull-up */ - drive-strength = <25>; /* DS8 */ + bias-pull-up = <0>; + drive-strength = <25>; }; }; + /omit-if-no-ref/ pwm2_3_cfg: pwm2-3-cfg { - pwm2-0-pins { + pwm2-3-pins { pinmux = ; /* pwm2 */ - bias-pull-up; /* normal pull-up */ - drive-strength = <25>; /* DS8 */ + bias-pull-up = <0>; + drive-strength = <25>; }; }; + /omit-if-no-ref/ pwm3_0_cfg: pwm3-0-cfg { pwm3-0-pins { pinmux = ; /* pwm3 */ - bias-pull-up; /* normal pull-up */ - drive-strength = <25>; /* DS8 */ + bias-pull-up = <0>; + drive-strength = <25>; }; }; + /omit-if-no-ref/ pwm3_1_cfg: pwm3-1-cfg { - pwm3-0-pins { + pwm3-1-pins { pinmux = ; /* pwm3 */ - bias-pull-up; /* normal pull-up */ - drive-strength = <25>; /* DS8 */ + bias-pull-up = <0>; + drive-strength = <25>; }; }; + /omit-if-no-ref/ pwm3_2_cfg: pwm3-2-cfg { - pwm3-0-pins { + pwm3-2-pins { pinmux = ; /* pwm3 */ - bias-pull-up; /* normal pull-up */ - drive-strength = <25>; /* DS8 */ + bias-pull-up = <0>; + drive-strength = <25>; }; }; + /omit-if-no-ref/ pwm3_3_cfg: pwm3-3-cfg { - pwm3-0-pins { + pwm3-3-pins { pinmux = ; /* pwm3 */ - bias-pull-up; /* normal pull-up */ - drive-strength = <25>; /* DS8 */ + bias-pull-up = <0>; + drive-strength = <25>; }; }; + /omit-if-no-ref/ pwm4_0_cfg: pwm4-0-cfg { pwm4-0-pins { pinmux = ; /* pwm4 */ - bias-pull-up; /* normal pull-up */ - drive-strength = <25>; /* DS8 */ + bias-pull-up = <0>; + drive-strength = <25>; }; }; + /omit-if-no-ref/ pwm4_1_cfg: pwm4-1-cfg { - pwm4-0-pins { + pwm4-1-pins { pinmux = ; /* pwm4 */ - bias-pull-up; /* normal pull-up */ - drive-strength = <25>; /* DS8 */ + bias-pull-up = <0>; + drive-strength = <25>; }; }; + /omit-if-no-ref/ pwm4_2_cfg: pwm4-2-cfg { - pwm4-0-pins { + pwm4-2-pins { pinmux = ; /* pwm4 */ - bias-pull-up; /* normal pull-up */ - drive-strength = <25>; /* DS8 */ + bias-pull-up = <0>; + drive-strength = <25>; }; }; + /omit-if-no-ref/ pwm5_0_cfg: pwm5-0-cfg { pwm5-0-pins { pinmux = ; /* pwm5 */ - bias-pull-up; /* normal pull-up */ - drive-strength = <25>; /* DS8 */ + bias-pull-up = <0>; + drive-strength = <25>; }; }; + /omit-if-no-ref/ pwm5_1_cfg: pwm5-1-cfg { - pwm5-0-pins { + pwm5-1-pins { pinmux = ; /* pwm5 */ - bias-pull-up; /* normal pull-up */ - drive-strength = <25>; /* DS8 */ + bias-pull-up = <0>; + drive-strength = <25>; }; }; + /omit-if-no-ref/ pwm5_2_cfg: pwm5-2-cfg { - pwm5-0-pins { + pwm5-2-pins { pinmux = ; /* pwm5 */ - bias-pull-up; /* normal pull-up */ - drive-strength = <25>; /* DS8 */ + bias-pull-up = <0>; + drive-strength = <25>; }; }; + /omit-if-no-ref/ pwm6_0_cfg: pwm6-0-cfg { pwm6-0-pins { pinmux = ; /* pwm6 */ - bias-pull-up; /* normal pull-up */ - drive-strength = <25>; /* DS8 */ + bias-pull-up = <0>; + drive-strength = <25>; }; }; + /omit-if-no-ref/ pwm6_1_cfg: pwm6-1-cfg { - pwm6-0-pins { + pwm6-1-pins { pinmux = ; /* pwm6 */ - bias-pull-up; /* normal pull-up */ - drive-strength = <25>; /* DS8 */ + bias-pull-up = <0>; + drive-strength = <25>; }; }; + /omit-if-no-ref/ pwm6_2_cfg: pwm6-2-cfg { - pwm6-0-pins { + pwm6-2-pins { pinmux = ; /* pwm6 */ - bias-pull-up; /* normal pull-up */ - drive-strength = <25>; /* DS8 */ + bias-pull-up = <0>; + drive-strength = <25>; }; }; + /omit-if-no-ref/ pwm7_0_cfg: pwm7-0-cfg { pwm7-0-pins { pinmux = ; /* pwm7 */ - bias-pull-up; /* normal pull-up */ - drive-strength = <25>; /* DS8 */ + bias-pull-up = <0>; + drive-strength = <25>; }; }; + /omit-if-no-ref/ pwm7_1_cfg: pwm7-1-cfg { - pwm7-0-pins { + pwm7-1-pins { pinmux = ; /* pwm7 */ - bias-pull-up; /* normal pull-up */ - drive-strength = <25>; /* DS8 */ + bias-pull-up = <0>; + drive-strength = <25>; }; }; + /omit-if-no-ref/ pwm7_2_cfg: pwm7-2-cfg { - pwm7-0-pins { + pwm7-2-pins { pinmux = ; /* pwm7 */ - bias-pull-up; /* normal pull-up */ - drive-strength = <25>; /* DS8 */ + bias-pull-up = <0>; + drive-strength = <25>; }; }; + /omit-if-no-ref/ pwm8_0_cfg: pwm8-0-cfg { pwm8-0-pins { pinmux = ; /* pwm8 */ - bias-pull-up; /* normal pull-up */ - drive-strength = <25>; /* DS8 */ + bias-pull-up = <0>; + drive-strength = <25>; }; }; + /omit-if-no-ref/ pwm8_1_cfg: pwm8-1-cfg { - pwm8-0-pins { + pwm8-1-pins { pinmux = ; /* pwm8 */ - bias-pull-up; /* normal pull-up */ - drive-strength = <25>; /* DS8 */ + bias-pull-up = <0>; + drive-strength = <25>; }; }; + /omit-if-no-ref/ pwm8_2_cfg: pwm8-2-cfg { - pwm8-0-pins { + pwm8-2-pins { pinmux = ; /* pwm8 */ - bias-pull-up; /* normal pull-up */ - drive-strength = <25>; /* DS8 */ + bias-pull-up = <0>; + drive-strength = <25>; }; }; + /omit-if-no-ref/ pwm9_0_cfg: pwm9-0-cfg { pwm9-0-pins { pinmux = ; /* pwm9 */ - bias-pull-up; /* normal pull-up */ - drive-strength = <25>; /* DS8 */ + bias-pull-up = <0>; + drive-strength = <25>; }; }; + /omit-if-no-ref/ pwm9_1_cfg: pwm9-1-cfg { - pwm9-0-pins { + pwm9-1-pins { pinmux = ; /* pwm9 */ - bias-pull-up; /* normal pull-up */ - drive-strength = <25>; /* DS8 */ + bias-pull-up = <0>; + drive-strength = <25>; }; }; + /omit-if-no-ref/ pwm9_2_cfg: pwm9-2-cfg { - pwm9-0-pins { + pwm9-2-pins { pinmux = ; /* pwm9 */ - bias-pull-up; /* normal pull-up */ - drive-strength = <25>; /* DS8 */ + bias-pull-up = <0>; + drive-strength = <25>; }; }; + /omit-if-no-ref/ pwm10_0_cfg: pwm10-0-cfg { pwm10-0-pins { pinmux = ; /* pwm10 */ - bias-pull-up; /* normal pull-up */ - drive-strength = <25>; /* DS8 */ + bias-pull-up = <0>; + drive-strength = <25>; }; }; + /omit-if-no-ref/ pwm10_1_cfg: pwm10-1-cfg { - pwm10-0-pins { + pwm10-1-pins { pinmux = ; /* pwm10 */ - bias-pull-up; /* normal pull-up */ - drive-strength = <25>; /* DS8 */ + bias-pull-up = <0>; + drive-strength = <25>; }; }; + /omit-if-no-ref/ pwm10_2_cfg: pwm10-2-cfg { - pwm10-0-pins { + pwm10-2-pins { pinmux = ; /* pwm10 */ - bias-pull-up; /* normal pull-up */ - drive-strength = <25>; /* DS8 */ + bias-pull-up = <0>; + drive-strength = <25>; }; }; + /omit-if-no-ref/ pwm11_0_cfg: pwm11-0-cfg { pwm11-0-pins { pinmux = ; /* pwm11 */ - bias-pull-up; /* normal pull-up */ - drive-strength = <25>; /* DS8 */ + bias-pull-up = <0>; + drive-strength = <25>; }; }; + /omit-if-no-ref/ pwm11_1_cfg: pwm11-1-cfg { - pwm11-0-pins { + pwm11-1-pins { pinmux = ; /* pwm11 */ - bias-pull-up; /* normal pull-up */ - drive-strength = <25>; /* DS8 */ + bias-pull-up = <0>; + drive-strength = <25>; }; }; + /omit-if-no-ref/ pwm12_0_cfg: pwm12-0-cfg { pwm12-0-pins { pinmux = ; /* pwm12 */ - bias-pull-up; /* normal pull-up */ - drive-strength = <25>; /* DS8 */ + bias-pull-up = <0>; + drive-strength = <25>; }; }; + /omit-if-no-ref/ pwm12_1_cfg: pwm12-1-cfg { - pwm12-0-pins { + pwm12-1-pins { pinmux = ; /* pwm12 */ - bias-pull-up; /* normal pull-up */ - drive-strength = <25>; /* DS8 */ + bias-pull-up = <0>; + drive-strength = <25>; }; }; + /omit-if-no-ref/ pwm13_0_cfg: pwm13-0-cfg { pwm13-0-pins { pinmux = ; /* pwm13 */ - bias-pull-up; /* normal pull-up */ - drive-strength = <25>; /* DS8 */ + bias-pull-up = <0>; + drive-strength = <25>; }; }; + /omit-if-no-ref/ pwm13_1_cfg: pwm13-1-cfg { - pwm13-0-pins { + pwm13-1-pins { pinmux = ; /* pwm13 */ - bias-pull-up; /* normal pull-up */ - drive-strength = <25>; /* DS8 */ + bias-pull-up = <0>; + drive-strength = <25>; }; }; + /omit-if-no-ref/ pwm13_2_cfg: pwm13-2-cfg { - pwm13-0-pins { + pwm13-2-pins { pinmux = ; /* pwm13 */ - bias-pull-up; /* normal pull-up */ - drive-strength = <25>; /* DS8 */ + bias-pull-up = <0>; + drive-strength = <25>; }; }; + /omit-if-no-ref/ pwm14_0_cfg: pwm14-0-cfg { pwm14-0-pins { pinmux = ; /* pwm14 */ - bias-pull-up; /* normal pull-up */ - drive-strength = <25>; /* DS8 */ + bias-pull-up = <0>; + drive-strength = <25>; }; }; + /omit-if-no-ref/ pwm14_1_cfg: pwm14-1-cfg { - pwm14-0-pins { + pwm14-1-pins { pinmux = ; /* pwm14 */ - bias-pull-up; /* normal pull-up */ - drive-strength = <25>; /* DS8 */ + bias-pull-up = <0>; + drive-strength = <25>; }; }; + /omit-if-no-ref/ pwm14_2_cfg: pwm14-2-cfg { - pwm14-0-pins { + pwm14-2-pins { pinmux = ; /* pwm14 */ - bias-pull-up; /* normal pull-up */ - drive-strength = <25>; /* DS8 */ + bias-pull-up = <0>; + drive-strength = <25>; }; }; + /omit-if-no-ref/ pwm15_0_cfg: pwm15-0-cfg { pwm15-0-pins { pinmux = ; /* pwm15 */ - bias-pull-up; /* normal pull-up */ - drive-strength = <25>; /* DS8 */ + bias-pull-up = <0>; + drive-strength = <25>; }; }; + /omit-if-no-ref/ pwm15_1_cfg: pwm15-1-cfg { - pwm15-0-pins { + pwm15-1-pins { pinmux = ; /* pwm15 */ - bias-pull-up; /* normal pull-up */ - drive-strength = <25>; /* DS8 */ + bias-pull-up = <0>; + drive-strength = <25>; }; }; + /omit-if-no-ref/ pwm15_2_cfg: pwm15-2-cfg { - pwm15-0-pins { + pwm15-2-pins { pinmux = ; /* pwm15 */ - bias-pull-up; /* normal pull-up */ - drive-strength = <25>; /* DS8 */ + bias-pull-up = <0>; + drive-strength = <25>; }; }; + /omit-if-no-ref/ pwm16_0_cfg: pwm16-0-cfg { pwm16-0-pins { pinmux = ; /* pwm16 */ - bias-pull-up; /* normal pull-up */ - drive-strength = <25>; /* DS8 */ + bias-pull-up = <0>; + drive-strength = <25>; }; }; + /omit-if-no-ref/ pwm16_1_cfg: pwm16-1-cfg { - pwm16-0-pins { + pwm16-1-pins { pinmux = ; /* pwm16 */ - bias-pull-up; /* normal pull-up */ - drive-strength = <25>; /* DS8 */ + bias-pull-up = <0>; + drive-strength = <25>; }; }; + /omit-if-no-ref/ pwm16_2_cfg: pwm16-2-cfg { - pwm16-0-pins { + pwm16-2-pins { pinmux = ; /* pwm16 */ - bias-pull-up; /* normal pull-up */ - drive-strength = <25>; /* DS8 */ + bias-pull-up = <0>; + drive-strength = <25>; }; }; + /omit-if-no-ref/ pwm17_0_cfg: pwm17-0-cfg { pwm17-0-pins { pinmux = ; /* pwm17 */ - bias-pull-up; /* normal pull-up */ - drive-strength = <25>; /* DS8 */ + bias-pull-up = <0>; + drive-strength = <25>; }; }; + /omit-if-no-ref/ pwm17_1_cfg: pwm17-1-cfg { - pwm17-0-pins { + pwm17-1-pins { pinmux = ; /* pwm17 */ - bias-pull-up; /* normal pull-up */ - drive-strength = <25>; /* DS8 */ + bias-pull-up = <0>; + drive-strength = <25>; }; }; + /omit-if-no-ref/ pwm17_2_cfg: pwm17-2-cfg { - pwm17-0-pins { + pwm17-2-pins { pinmux = ; /* pwm17 */ - bias-pull-up; /* normal pull-up */ - drive-strength = <25>; /* DS8 */ + bias-pull-up = <0>; + drive-strength = <25>; }; }; + /omit-if-no-ref/ pwm18_0_cfg: pwm18-0-cfg { pwm18-0-pins { pinmux = ; /* pwm18 */ - bias-pull-up; /* normal pull-up */ - drive-strength = <25>; /* DS8 */ + bias-pull-up = <0>; + drive-strength = <25>; }; }; + /omit-if-no-ref/ pwm18_1_cfg: pwm18-1-cfg { - pwm18-0-pins { + pwm18-1-pins { pinmux = ; /* pwm18 */ - bias-pull-up; /* normal pull-up */ - drive-strength = <25>; /* DS8 */ + bias-pull-up = <0>; + drive-strength = <25>; }; }; + /omit-if-no-ref/ pwm18_2_cfg: pwm18-2-cfg { - pwm18-0-pins { + pwm18-2-pins { pinmux = ; /* pwm18 */ - bias-pull-up; /* normal pull-up */ - drive-strength = <25>; /* DS8 */ + bias-pull-up = <0>; + drive-strength = <25>; }; }; + /omit-if-no-ref/ pwm19_0_cfg: pwm19-0-cfg { pwm19-0-pins { pinmux = ; /* pwm19 */ - bias-pull-up; /* normal pull-up */ - drive-strength = <25>; /* DS8 */ + bias-pull-up = <0>; + drive-strength = <25>; }; }; + /omit-if-no-ref/ pwm19_1_cfg: pwm19-1-cfg { - pwm19-0-pins { + pwm19-1-pins { pinmux = ; /* pwm19 */ - bias-pull-up; /* normal pull-up */ - drive-strength = <25>; /* DS8 */ + bias-pull-up = <0>; + drive-strength = <25>; }; }; + /omit-if-no-ref/ pwm19_2_cfg: pwm19-2-cfg { - pwm19-0-pins { + pwm19-2-pins { pinmux = ; /* pwm19 */ - bias-pull-up; /* normal pull-up */ - drive-strength = <25>; /* DS8 */ + bias-pull-up = <0>; + drive-strength = <25>; }; }; + rpwm0_0_cfg: rpwm0-0-cfg { rpwm0-0-pins { pinmux = ; /* rpwm0 */ diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi index 974ea1ea6cf05..29bcf7ed897a3 100644 --- a/arch/riscv/boot/dts/spacemit/k3.dtsi +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi @@ -761,6 +761,226 @@ status = "disabled"; }; + pwm0: pwm@d401a000 { + compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; + reg = <0x0 0xd401a000 0x0 0x10>; + clocks = <&syscon_apbc CLK_APBC_PWM0>, + <&syscon_apbc CLK_APBC_PWM0_BUS>; + clock-names = "func", "bus"; + resets = <&syscon_apbc RESET_APBC_PWM0>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm1: pwm@d401a400 { + compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; + reg = <0x0 0xd401a400 0x0 0x10>; + clocks = <&syscon_apbc CLK_APBC_PWM1>, + <&syscon_apbc CLK_APBC_PWM1_BUS>; + clock-names = "func", "bus"; + resets = <&syscon_apbc RESET_APBC_PWM1>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm2: pwm@d401a800 { + compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; + reg = <0x0 0xd401a800 0x0 0x10>; + clocks = <&syscon_apbc CLK_APBC_PWM2>, + <&syscon_apbc CLK_APBC_PWM2_BUS>; + clock-names = "func", "bus"; + resets = <&syscon_apbc RESET_APBC_PWM2>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm3: pwm@d401ac00 { + compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; + reg = <0x0 0xd401ac00 0x0 0x10>; + clocks = <&syscon_apbc CLK_APBC_PWM3>, + <&syscon_apbc CLK_APBC_PWM3_BUS>; + clock-names = "func", "bus"; + resets = <&syscon_apbc RESET_APBC_PWM3>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm4: pwm@d401b000 { + compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; + reg = <0x0 0xd401b000 0x0 0x10>; + clocks = <&syscon_apbc CLK_APBC_PWM4>, + <&syscon_apbc CLK_APBC_PWM4_BUS>; + clock-names = "func", "bus"; + resets = <&syscon_apbc RESET_APBC_PWM4>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm5: pwm@d401b400 { + compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; + reg = <0x0 0xd401b400 0x0 0x10>; + clocks = <&syscon_apbc CLK_APBC_PWM5>, + <&syscon_apbc CLK_APBC_PWM5_BUS>; + clock-names = "func", "bus"; + resets = <&syscon_apbc RESET_APBC_PWM5>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm6: pwm@d401b800 { + compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; + reg = <0x0 0xd401b800 0x0 0x10>; + clocks = <&syscon_apbc CLK_APBC_PWM6>, + <&syscon_apbc CLK_APBC_PWM6_BUS>; + clock-names = "func", "bus"; + resets = <&syscon_apbc RESET_APBC_PWM6>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm7: pwm@d401bc00 { + compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; + reg = <0x0 0xd401bc00 0x0 0x10>; + clocks = <&syscon_apbc CLK_APBC_PWM7>, + <&syscon_apbc CLK_APBC_PWM7_BUS>; + clock-names = "func", "bus"; + resets = <&syscon_apbc RESET_APBC_PWM7>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm8: pwm@d4020000 { + compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; + reg = <0x0 0xd4020000 0x0 0x10>; + clocks = <&syscon_apbc CLK_APBC_PWM8>, + <&syscon_apbc CLK_APBC_PWM8_BUS>; + clock-names = "func", "bus"; + resets = <&syscon_apbc RESET_APBC_PWM8>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm9: pwm@d4020400 { + compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; + reg = <0x0 0xd4020400 0x0 0x10>; + clocks = <&syscon_apbc CLK_APBC_PWM9>, + <&syscon_apbc CLK_APBC_PWM9_BUS>; + clock-names = "func", "bus"; + resets = <&syscon_apbc RESET_APBC_PWM9>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm10: pwm@d4020800 { + compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; + reg = <0x0 0xd4020800 0x0 0x10>; + clocks = <&syscon_apbc CLK_APBC_PWM10>, + <&syscon_apbc CLK_APBC_PWM10_BUS>; + clock-names = "func", "bus"; + resets = <&syscon_apbc RESET_APBC_PWM10>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm11: pwm@d4020c00 { + compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; + reg = <0x0 0xd4020c00 0x0 0x10>; + clocks = <&syscon_apbc CLK_APBC_PWM11>, + <&syscon_apbc CLK_APBC_PWM11_BUS>; + clock-names = "func", "bus"; + resets = <&syscon_apbc RESET_APBC_PWM11>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm12: pwm@d4021000 { + compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; + reg = <0x0 0xd4021000 0x0 0x10>; + clocks = <&syscon_apbc CLK_APBC_PWM12>, + <&syscon_apbc CLK_APBC_PWM12_BUS>; + clock-names = "func", "bus"; + resets = <&syscon_apbc RESET_APBC_PWM12>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm13: pwm@d4021400 { + compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; + reg = <0x0 0xd4021400 0x0 0x10>; + clocks = <&syscon_apbc CLK_APBC_PWM13>, + <&syscon_apbc CLK_APBC_PWM13_BUS>; + clock-names = "func", "bus"; + resets = <&syscon_apbc RESET_APBC_PWM13>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm14: pwm@d4021800 { + compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; + reg = <0x0 0xd4021800 0x0 0x10>; + clocks = <&syscon_apbc CLK_APBC_PWM14>, + <&syscon_apbc CLK_APBC_PWM14_BUS>; + clock-names = "func", "bus"; + resets = <&syscon_apbc RESET_APBC_PWM14>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm15: pwm@d4021c00 { + compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; + reg = <0x0 0xd4021c00 0x0 0x10>; + clocks = <&syscon_apbc CLK_APBC_PWM15>, + <&syscon_apbc CLK_APBC_PWM15_BUS>; + clock-names = "func", "bus"; + resets = <&syscon_apbc RESET_APBC_PWM15>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm16: pwm@d4022000 { + compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; + reg = <0x0 0xd4022000 0x0 0x10>; + clocks = <&syscon_apbc CLK_APBC_PWM16>, + <&syscon_apbc CLK_APBC_PWM16_BUS>; + clock-names = "func", "bus"; + resets = <&syscon_apbc RESET_APBC_PWM16>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm17: pwm@d4022400 { + compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; + reg = <0x0 0xd4022400 0x0 0x10>; + clocks = <&syscon_apbc CLK_APBC_PWM17>, + <&syscon_apbc CLK_APBC_PWM17_BUS>; + clock-names = "func", "bus"; + resets = <&syscon_apbc RESET_APBC_PWM17>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm18: pwm@d4022800 { + compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; + reg = <0x0 0xd4022800 0x0 0x10>; + clocks = <&syscon_apbc CLK_APBC_PWM18>, + <&syscon_apbc CLK_APBC_PWM18_BUS>; + clock-names = "func", "bus"; + resets = <&syscon_apbc RESET_APBC_PWM18>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm19: pwm@d4022c00 { + compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; + reg = <0x0 0xd4022c00 0x0 0x10>; + clocks = <&syscon_apbc CLK_APBC_PWM19>, + <&syscon_apbc CLK_APBC_PWM19_BUS>; + clock-names = "func", "bus"; + resets = <&syscon_apbc RESET_APBC_PWM19>; + #pwm-cells = <3>; + status = "disabled"; + }; + syscon_gpio: syscon-gpio{ compatible = "syscon"; reg = <0x0 0xd4019000 0x0 0x800>;