RISC-V: ASID-related and UP-related TLB flush enhancement

[zhuzhenxxx-collab]

Backport Samuel Holland's v6 patch series (upstream) which:

• Unifies SMP and UP TLB flush code paths, enabling UP builds to benefit from
  batching and ASID/range-based flush optimizations
• Avoids unnecessary IPIs and SBI calls when only one CPU is online
• Uses single-ASID flushes where possible to prevent unnecessary TLB misses on
  kernel mappings