Skip to content

Add Zilsd/Zclsd support in hwprobe and KVM#305

Merged
sterling-teng merged 28 commits into
RVCK-Project:rvck-6.6from
uestc-gr:Zilsd
Jul 14, 2026
Merged

Add Zilsd/Zclsd support in hwprobe and KVM#305
sterling-teng merged 28 commits into
RVCK-Project:rvck-6.6from
uestc-gr:Zilsd

Conversation

@uestc-gr

@uestc-gr uestc-gr commented Jun 10, 2026

Copy link
Copy Markdown
Contributor

fixed: #304

为已批准的 RISC-V ISA 扩展 Zilsd(Load/Store pair)和 Zclsd(Compressed Load/Store pair)添加内核支持,使用户空间(如 glibc)能够通过 hwprobe 和运行时检测机制发现并使用这些扩展。

所有补丁均来自L0社区,并自测通过

测试方法
在qemu11.0上启动一个32bit的虚拟机(-cpu rv32,v=true,f=on,zilsd=on,zclsd=off )

cat /proc/cpuinfo
processor : 0
hart : 32
isa : rv32imafdcvh_zicbom_zicbop_zicboz_ziccrse_zicntr_zicsr_zifencei_zihintntl_zihintpause_zihpm_zaamo_zalrsc_zawrs_zfa_zca_zcd_zilsd_zba_zbb_zbc_zbs_zve32f_zve32x_smaia_ssaia_sstc_svadu_svvptc
mmu : sv32
mvendorid : 0x0
marchid : 0x0
mimpid : 0x0
hart isa : rv32imafdcvh_zicbom_zicbop_zicboz_ziccrse_zicntr_zicsr_zifencei_zihintntl_zihintpause_zihpm_zaamo_zalrsc_zawrs_zfa_zca_zcd_zilsd_zba_zbb_zbc_zbs_zve32f_zve32x_smaia_ssaia_sstc_svadu_svvptc

~ # hwprobe
TAP version 13
1..5
ok 1 NULL CPU set
ok 2 Bad CPU set
ok 3 NULL CPU set with non-zero size
ok 4 Existing key is maintained
ok 5 Unknown key overwritten with -1 and doesn't block other elements

Totals: pass:5 fail:0 xfail:0 xpass:0 skip:0 error:0

@github-actions

github-actions Bot commented Jun 10, 2026

Copy link
Copy Markdown

开始测试 log: https://github.com/RVCK-Project/rvck/actions/runs/27261703212

参数解析结果
args value
repository RVCK-Project/rvck
head ref pull/305/head
base ref rvck-6.6
LAVA repo RVCK-Project/lavaci
LAVA hardware ['qemu']
LAVA Testcase path lava-testcases/common-test/ltp/ltp.yaml
need run job kunit-test,kernel-build,check-patch,lava-trigger

测试完成

详细结果:
check result
kunit-test success
kernel-build success
check-patch success
lava-trigger-qemu success
lava-trigger-sg2042 skipped
lava-trigger-k1 skipped
lava-trigger-lpi4a skipped

Kunit Test Result

[07:58:42] Testing complete. Ran 482 tests: passed: 466, skipped: 16

Kernel Build Result

Check Patch Result

Total Errors 0
Total Warnings 5

LAVA Check (qemu)

args value
testcase_repo RVCK-Project/lavaci
lava_template lava-job-template/qemu/qemu-ltp.yaml
testcase_path lava-testcases/common-test/ltp/ltp.yaml
kernel_download_url http://10.30.190.110/openEuler-RISC-V/RVCK/OERV-RVCI/RVCK-Project/rvck/305_27261703212_1/Image
initramfs_download_url http://10.30.190.110/openEuler-RISC-V/RVCK/OERV-RVCI/RVCK-Project/rvck/305_27261703212_1/initramfs.img
rootfs_download_url https://fast-mirror.isrc.ac.cn/openeuler-sig-riscv/openEuler-RISC-V/RVCK/openEuler24.03-LTS-SP1/openeuler-rootfs.img.zst
testcase_ref main
testitem_name RVCK-Project_rvck_pull_request_target_305__common-test_qemu

result: Lava check done!

@uestc-gr

Copy link
Copy Markdown
Contributor Author

该pr已完成,请老师评审合入,多谢

@sterling-teng

Copy link
Copy Markdown
Contributor

该pr已完成,请老师评审合入,多谢

正常审阅中,争取周内合并。

@unicornx
unicornx self-requested a review June 28, 2026 07:01
@unicornx

Copy link
Copy Markdown

@uestc-gr 你好,貌似有些文件冲突,请帮忙解决一下先,谢谢。

@github-actions

github-actions Bot commented Jun 29, 2026

Copy link
Copy Markdown

开始测试 log: https://github.com/RVCK-Project/rvck/actions/runs/28352134931

参数解析结果
args value
repository RVCK-Project/rvck
head ref pull/305/head
base ref rvck-6.6
LAVA repo RVCK-Project/lavaci
LAVA hardware ['qemu']
LAVA Testcase path lava-testcases/common-test/ltp/ltp.yaml
need run job kunit-test,kernel-build,check-patch,lava-trigger

测试完成

详细结果:
check result
kunit-test success
kernel-build success
check-patch success
lava-trigger-qemu success
lava-trigger-sg2042 skipped
lava-trigger-k1 skipped
lava-trigger-lpi4a skipped

Kunit Test Result

[06:11:48] Testing complete. Ran 482 tests: passed: 466, skipped: 16

Kernel Build Result

Check Patch Result

Total Errors 0
Total Warnings 5

LAVA Check (qemu)

args value
testcase_repo RVCK-Project/lavaci
lava_template lava-job-template/qemu/qemu-ltp.yaml
testcase_path lava-testcases/common-test/ltp/ltp.yaml
kernel_download_url http://10.30.190.110/openEuler-RISC-V/RVCK/OERV-RVCI/RVCK-Project/rvck/305_28352134931_1/Image
initramfs_download_url http://10.30.190.110/openEuler-RISC-V/RVCK/OERV-RVCI/RVCK-Project/rvck/305_28352134931_1/initramfs.img
rootfs_download_url https://fast-mirror.isrc.ac.cn/openeuler-sig-riscv/openEuler-RISC-V/RVCK/openEuler24.03-LTS-SP1/openeuler-rootfs.img.zst
testcase_ref main
testitem_name RVCK-Project_rvck_pull_request_target_305__common-test_qemu

result: Lava check done!

@uestc-gr

Copy link
Copy Markdown
Contributor Author

@uestc-gr 你好,貌似有些文件冲突,请帮忙解决一下先,谢谢。

已更新,请评审

@unicornx
unicornx requested a review from sterling-teng June 30, 2026 08:06

@unicornx unicornx left a comment

Copy link
Copy Markdown

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

看了一下有几个问题,可能不是本 PR 引入的,但需要讨论一下。

Copy link
Copy Markdown

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

上游 commit (4115155) 中除了在 “riscv,isa-extensions” 中添加 zilsd 和 zclsd 外, 还有对 Zclsd 的依赖检查 以及对 Zilsd 必须不可在 rv64 上存在的断定。这部分内容我发现你在 pick 上游补丁时没有合入。需要补充。

另外我有一个疑问,看上去 Zclsd 会依赖于 Zca. 但在 rvck-6.6 中貌似合入了一些 zca 的代码处理,但是 binding 这边(特别是这个文件有关 zca, 乃至 zc* 的改动丢失了),我查了一下 zca 的相关upsteram PR 是在 https://lore.kernel.org/linux-riscv/20240619113529.676940-1-cleger@rivosinc.com/。
@sterling-teng 是在哪个 PR 里合入的 Zca 的改动?貌似对这个上游的 PR,rvck 中合并了一部分,丢失了一部分?

需要搞清楚,感觉这里存在混乱。

Copy link
Copy Markdown
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

上游 commit (4115155) 中除了在 “riscv,isa-extensions” 中添加 zilsd 和 zclsd 外, 还有对 Zclsd 的依赖检查 以及对 Zilsd 必须不可在 rv64 上存在的断定。这部分内容我发现你在 pick 上游补丁时没有合入。需要补充。

另外我有一个疑问,看上去 Zclsd 会依赖于 Zca. 但在 rvck-6.6 中貌似合入了一些 zca 的代码处理,但是 binding 这边(特别是这个文件有关 zca, 乃至 zc* 的改动丢失了),我查了一下 zca 的相关upsteram PR 是在 https://lore.kernel.org/linux-riscv/20240619113529.676940-1-cleger@rivosinc.com/。 @sterling-teng 是在哪个 PR 里合入的 Zca 的改动?貌似对这个上游的 PR,rvck 中合并了一部分,丢失了一部分?

需要搞清楚,感觉这里存在混乱。

可能差异有点大,我尝试修改下

Copy link
Copy Markdown

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

好奇怪,本该在这个 commit 中合入的

--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -108,6 +108,8 @@
 #define RISCV_ISA_EXT_ZICBOP           99
 #define RISCV_ISA_EXT_SVRSW60T59B      100
 #define RISCV_ISA_EXT_ZALASR           101
+#define RISCV_ISA_EXT_ZILSD            102
+#define RISCV_ISA_EXT_ZCLSD            103

这个改动,在 rvck-6.6 上竟然已经存在了,查了一下,是 9906c3c 合入的,当时那个 PR 为何要改这个?@sterling-teng

@sterling-teng 想到一个问题,rvck-6.6 分支中,如果找到了一个我们的 commit 改动,想反查是哪个 PR 合入的,有什么好方法?貌似比较困难,以后是否可以在升级 rvck-6.6 分支 的时候在将 merge 节点与 riscv patch 节点合并的时候可以在 patch 节点中加个 PR# 的信息,或者我理解就应该保留 merge 节点信息,这样就可以方便查看是哪个 PR 合入了哪些 commit 了。

Copy link
Copy Markdown
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

release的tag里有merge节点,git log --all能搜到,当然,建仓早期的滚动没打patch。

Copy link
Copy Markdown

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

release 的 tag 里是有,但是我们看代码的时候一般都是基于最新的 rvck-6.6 分支上的 commit,如果去 release 的tag 的分支上找,得用 commit 的 title 重新匹配一下,感觉会比较麻烦。
anyway,这个问题先保留吧,后面如果实在感觉不方便再说。

@unicornx

Copy link
Copy Markdown

@uestc-gr 我尝试用 qemu 跑了一下。有几个问题想讨论一下:

1)你那边编译 hwprobe 是怎么弄的,我这里尝试了好几种方法,目前采用的是:

手动修改 Makefile, 去掉 cbo,否则编译会报错

diff --git a/tools/testing/selftests/riscv/hwprobe/Makefile b/tools/testing/selftests/riscv/hwprobe/Makefile
index f224b84591fb..f8d0b7422bc4 100644
--- a/tools/testing/selftests/riscv/hwprobe/Makefile
+++ b/tools/testing/selftests/riscv/hwprobe/Makefile
@@ -4,7 +4,8 @@
 
 CFLAGS += -I$(top_srcdir)/tools/include
 
-TEST_GEN_PROGS := hwprobe cbo
+#TEST_GEN_PROGS := hwprobe cbo
+TEST_GEN_PROGS := hwprobe

运行如下命令:

make ARCH=riscv CROSS_COMPILE=riscv32-linux- -C tools/testing/selftests/ TARGETS=riscv/hwprobe CFLAGS="-static -march=rv32g -I$(pwd)/tools/include -I$(pwd)/arch/riscv/include/uapi"

感觉有点繁琐,不知道你有没有更好的构建方法?

  1. 我认为测试的时候简单地运行 hwprobe 是不够的。因为内核提供的 hwprobe 并没有仔细检查实际支持的 ext 中是否有我们关心的 zilsd,所以我建议测试时手动修改 hwprobe.c 的源码:
diff --git a/tools/testing/selftests/riscv/hwprobe/hwprobe.c b/tools/testing/selftests/riscv/hwprobe/hwprobe.c
index d53e0889b59e..9d0730ee41d5 100644
--- a/tools/testing/selftests/riscv/hwprobe/hwprobe.c
+++ b/tools/testing/selftests/riscv/hwprobe/hwprobe.c
@@ -40,6 +40,11 @@ int main(int argc, char **argv)
                ksft_exit_fail_msg("Unexpected pair: (%ld, %ld)\n", pairs[i].key, pairs[i].value);
        }
 
+       if (pairs[4].value & RISCV_HWPROBE_EXT_ZILSD)
+               printf("Zilsd is SUPPORTED\n");
+       else
+               printf("Zilsd is NOT supported\n");
+
        out = riscv_hwprobe(pairs, 8, 0, 0, 0);
        ksft_test_result(out == 0, "NULL CPU set\n");

@uestc-gr

Copy link
Copy Markdown
Contributor Author

@uestc-gr 我尝试用 qemu 跑了一下。有几个问题想讨论一下:

1)你那边编译 hwprobe 是怎么弄的,我这里尝试了好几种方法,目前采用的是:

手动修改 Makefile, 去掉 cbo,否则编译会报错

diff --git a/tools/testing/selftests/riscv/hwprobe/Makefile b/tools/testing/selftests/riscv/hwprobe/Makefile
index f224b84591fb..f8d0b7422bc4 100644
--- a/tools/testing/selftests/riscv/hwprobe/Makefile
+++ b/tools/testing/selftests/riscv/hwprobe/Makefile
@@ -4,7 +4,8 @@
 
 CFLAGS += -I$(top_srcdir)/tools/include
 
-TEST_GEN_PROGS := hwprobe cbo
+#TEST_GEN_PROGS := hwprobe cbo
+TEST_GEN_PROGS := hwprobe

运行如下命令:

make ARCH=riscv CROSS_COMPILE=riscv32-linux- -C tools/testing/selftests/ TARGETS=riscv/hwprobe CFLAGS="-static -march=rv32g -I$(pwd)/tools/include -I$(pwd)/arch/riscv/include/uapi"

感觉有点繁琐,不知道你有没有更好的构建方法?

  1. 我认为测试的时候简单地运行 hwprobe 是不够的。因为内核提供的 hwprobe 并没有仔细检查实际支持的 ext 中是否有我们关心的 zilsd,所以我建议测试时手动修改 hwprobe.c 的源码:
diff --git a/tools/testing/selftests/riscv/hwprobe/hwprobe.c b/tools/testing/selftests/riscv/hwprobe/hwprobe.c
index d53e0889b59e..9d0730ee41d5 100644
--- a/tools/testing/selftests/riscv/hwprobe/hwprobe.c
+++ b/tools/testing/selftests/riscv/hwprobe/hwprobe.c
@@ -40,6 +40,11 @@ int main(int argc, char **argv)
                ksft_exit_fail_msg("Unexpected pair: (%ld, %ld)\n", pairs[i].key, pairs[i].value);
        }
 
+       if (pairs[4].value & RISCV_HWPROBE_EXT_ZILSD)
+               printf("Zilsd is SUPPORTED\n");
+       else
+               printf("Zilsd is NOT supported\n");
+
        out = riscv_hwprobe(pairs, 8, 0, 0, 0);
        ksft_test_result(out == 0, "NULL CPU set\n");

因为之前的很多合入没有合selftest的改动,导致会出现编译错误,我是用开源内核编译出的hwprobe进行的测试

avpatel and others added 16 commits July 1, 2026 14:17
mainline inclusion
from mainline-6.6-rc6
commit 00c6f39
category: feature
bugzilla: RVCK-Project#304

--------------------------------

Add an entry for the Zicond extension to the riscv,isa-extensions property.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
mainline inclusion
from mainline-6.7-rc6
commit 9376396
category: feature
bugzilla: RVCK-Project#304

--------------------------------

Add description for scalar crypto ISA extensions:

- Zbkb
- Zbkc
- Zbkx
- Zknd
- Zkne
- Zknh
- Zkr
- Zksed
- Zksh
- Zkt

Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20231114141256.126749-6-cleger@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
mainline inclusion
from mainline-6.7-rc6
commit 1081553
category: feature
bugzilla: RVCK-Project#304

--------------------------------

Add Zv* vector crypto extensions that were added in "RISC-V Cryptography
Extensions Volume II" specificationi[1]:

- Zvbb: Vector Basic Bit-manipulation
- Zvbc: Vector Carryless Multiplication
- Zvkb: Vector Cryptography Bit-manipulation
- Zvkg: Vector GCM/GMAC.
- Zvkned: NIST Suite: Vector AES Block Cipher
- Zvknh[ab]: NIST Suite: Vector SHA-2 Secure Hash
- Zvksed: ShangMi Suite: SM4 Block Cipher
- Zvksh: ShangMi Suite: SM3 Secure Hash
- Zvkn: NIST Algorithm Suite
- Zvknc: NIST Algorithm Suite with carryless multiply
- Zvkng: NIST Algorithm Suite with GCM.
- Zvks: ShangMi Algorithm Suite
- Zvksc: ShangMi Algorithm Suite with carryless multiplication
- Zvksg: ShangMi Algorithm Suite with GCM.
- Zvkt: Vector Data-Independent Execution Latency.

Link: https://drive.google.com/file/d/1gb9OLH-DhbCgWp7VwpPOVrrY6f3oSJLL/view [1]
Signed-off-by: Clément Léger <cleger@rivosinc.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20231114141256.126749-9-cleger@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
mainline inclusion
from mainline-6.7-rc6
commit c44714c
category: feature
bugzilla: RVCK-Project#304

--------------------------------

Add description of Zfh[min] ISA extensions[1].

Link: https://drive.google.com/file/d/1z3tQQLm5ALsAD77PM0l0CHnapxWCeVzP/view [1]
Signed-off-by: Clément Léger <cleger@rivosinc.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20231114141256.126749-12-cleger@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
mainline inclusion
from mainline-6.7-rc6
commit 892f10c
category: feature
bugzilla: RVCK-Project#304

--------------------------------

Add description for Zihintntl ISA extension[1].

Link: https://drive.google.com/file/d/13_wsN8YmRfH8YWysFyTX-DjTkCnBd9hj/view [1]
Signed-off-by: Clément Léger <cleger@rivosinc.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20231114141256.126749-15-cleger@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
mainline inclusion
from mainline-6.7-rc6
commit e11880b
category: feature
bugzilla: RVCK-Project#304

--------------------------------

Add description for Zvfh[min] ISA extension[1].

Link: https://drive.google.com/file/d/1_Yt60HGAf1r1hx7JnsIptw0sqkBd9BQ8/view [1]
Signed-off-by: Clément Léger <cleger@rivosinc.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20231114141256.126749-18-cleger@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
mainline inclusion
from mainline-6.7-rc6
commit 9726acf
category: feature
bugzilla: RVCK-Project#304

--------------------------------

Add description for the Zfa ISA extension[1].

Link: https://drive.google.com/file/d/1VT6QIggpb59-8QRV266dEE4T8FZTxGq4/view [1]
Signed-off-by: Clément Léger <cleger@rivosinc.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20231114141256.126749-21-cleger@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
mainline inclusion
from mainline-6.8-rc1
commit cd7be4d
category: feature
bugzilla: RVCK-Project#304

--------------------------------

Add description for the Zacas ISA extension which was ratified recently.

Signed-off-by: Clément Léger <cleger@rivosinc.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20231220155723.684081-4-cleger@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
mainline inclusion
from mainline-6.8-rc1
commit 07df87c
category: feature
bugzilla: RVCK-Project#304

--------------------------------

There are some extensions that contain numbers, such as Zve32f, which
are enabled by the "max" cpu type in QEMU.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20231208-uncolored-oxidant-5ab37dd3ab84@spud
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
mainline inclusion
from mainline-6.9-rc1
commit 61609bf
category: feature
bugzilla: RVCK-Project#304

--------------------------------

Document the ISA string for Andes Technology performance monitor
extension which provides counter overflow interrupt and mode
filtering mechanisms.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20240222083946.3977135-9-peterlin@andestech.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
mainline inclusion
from mainline-6.10-rc2
commit 037df29
category: feature
bugzilla: RVCK-Project#304

--------------------------------

Add description for Zve32x Zve32f Zve64x Zve64f Zve64d ISA extensions.

Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20240510-zve-detection-v5-4-0711bdd26c12@sifive.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
mainline inclusion
from mainline-6.10-rc6
commit a57b68b
category: feature
bugzilla: RVCK-Project#304

--------------------------------

Add description for the Zimop (May-Be-Operations) ISA extension which
was ratified in commit 58220614a5f of the riscv-isa-manual.

Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Charlie Jenkins <charlie@rivosinc.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20240619113529.676940-2-cleger@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
mainline inclusion
from mainline-6.10-rc6
commit e9f9946
category: feature
bugzilla: RVCK-Project#304

--------------------------------

Add description for Zca, Zcf, Zcd and Zcb extensions which are part the
Zc* standard extensions for code size reduction. Additional validation
rules are added since Zcb depends on Zca, Zcf, depends on Zca and F, Zcd
depends on Zca and D and finally, Zcf can not be present on rv64.

Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Charlie Jenkins <charlie@rivosinc.com>
Link: https://lore.kernel.org/r/20240619113529.676940-7-cleger@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
mainline inclusion
from mainline-6.10-rc6
commit 700556a
category: feature
bugzilla: RVCK-Project#304

--------------------------------

Add description for the Zcmop (Compressed May-Be-Operations) ISA
extension which was ratified in commit c732a4f39a4c ("Zcmop is
ratified/1.0") of the riscv-isa-manual.

Signed-off-by: Clément Léger <cleger@rivosinc.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20240619113529.676940-13-cleger@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
mainline inclusion
from mainline-6.14
commit 35bc188
category: feature
bugzilla: RVCK-Project#304

--------------------------------

Add description for the BFloat16 precision Floating-Point ISA extension,
(Zfbfmin, Zvfbfmin, Zvfbfwma). which was ratified in commit 4dc23d62
("Added Chapter title to BF16") of the riscv-isa-manual.

Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20250213003849.147358-2-inochiama@gmail.com
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
mainline inclusion
from mainline-6.10
commit 6d58528
category: feature
bugzilla: RVCK-Project#304

--------------------------------

Add description for the Zawrs (Wait-on-Reservation-Set) ISA extension
which was ratified in commit 98918c844281 of riscv-isa-manual.

Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20240426100820.14762-10-ajones@ventanamicro.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
Alexandre Ghiti and others added 12 commits July 1, 2026 14:17
mainline inclusion
from mainline-6.11
commit d25599b
category: feature
bugzilla: RVCK-Project#304

--------------------------------

Add description for the Svvptc ISA extension which was ratified recently.

Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20240717060125.139416-3-alexghiti@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
mainline inclusion
from mainline-6.12-rc5
commit 8727163
category: feature
bugzilla: RVCK-Project#304

--------------------------------

The RISC-V Pointer Masking specification defines three extensions:
Smmpm, Smnpm, and Ssnpm. Document the behavior of these extensions as
following the ratified version 1.0 of the specification.

Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Charlie Jenkins <charlie@rivosinc.com>
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
Link: https://lore.kernel.org/r/20241016202814.4061541-2-samuel.holland@sifive.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
mainline inclusion
from mainline-6.12
commit 51624dd
category: feature
bugzilla: RVCK-Project#304

--------------------------------

Add description for the Zabha ISA extension which was ratified in April
2024.

Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Reviewed-by: Guo Ren <guoren@kernel.org>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Andrea Parri <parri.andrea@gmail.com>
Link: https://lore.kernel.org/r/20241103145153.105097-5-alexghiti@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
mainline inclusion
from mainline-6.14
commit a65e0f6
category: feature
bugzilla: RVCK-Project#304

--------------------------------

Add description for the Zaamo and Zalrsc ISA extension[1].

Link: https://github.com/riscv/riscv-zaamo-zalrsc [1]
Signed-off-by: Clément Léger <cleger@rivosinc.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20240619153913.867263-2-cleger@rivosinc.com
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>

Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
mainline inclusion
from mainline-6.15-rc1
commit 534d813
category: feature
bugzilla: RVCK-Project#304

--------------------------------

Per the specifications, the d extension for double-precision floating
point operations depends on the f extension for single-precision floating
point. Add that requirement to the bindings. This differs from the
Linux implementation, where single-precious only is not supported.

Reviewed-by: Clément Léger <cleger@rivosinc.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20250312-perpetual-daunting-ad489c9a857a@spud
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
mainline inclusion
from mainline-6.15-rc1
commit e9f1d61
category: feature
bugzilla: RVCK-Project#304

--------------------------------
Section 33.18.2. Zve*: Vector Extensions for Embedded Processors
in [1] says:
| The Zve32f and Zve64x extensions depend on the Zve32x extension. The Zve64f extension depends
| on the Zve32f and Zve64x extensions. The Zve64d extension depends on the Zve64f extension

| The Zve32x extension depends on the Zicsr extension. The Zve32f and Zve64f extensions depend
| upon the F extension

| The Zve64d extension depends upon the D extension

Apply these rules to the bindings to help prevent invalid combinations.

Link: https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-isa-release-698e64a-2024-09-09 [1]
Reviewed-by: Clément Léger <cleger@rivosinc.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20250312-banking-crestless-58f3259a5018@spud
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
mainline inclusion
from mainline-6.15-rc1
commit a0d8572
category: feature
bugzilla: RVCK-Project#304

--------------------------------

The Unpriv spec states:
| The Zvknhb and Zvbc Vector Crypto Extensions --and accordingly the
| composite extensions Zvkn, Zvknc, Zvkng, and Zvksc-- require a Zve64x
| base, or application ("V") base Vector Extension. All of the other
| Vector Crypto Extensions can be built on any embedded (Zve*) or
| application ("V") base Vector Extension.

Enforce the minimum requirement via schema.

Link: https://github.com/riscv/riscv-isa-manual/blob/main/src/vector-crypto.adoc#extensions-overview
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20250312-flask-relay-b36ee622b2c8@spud
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
mainline inclusion
from mainline-6.19-rc2
commit 4115155
category: feature
bugzilla: RVCK-Project#304

--------------------------------

Add descriptions for the Zilsd (Load/Store pair instructions) and
Zclsd (Compressed Load/Store pair instructions) ISA extensions
which were ratified in commit f88abf1 ("Integrating load/store
pair for RV32 with the main manual") of the riscv-isa-manual.

Signed-off-by: Pincheng Wang <pincheng.plct@isrc.iscas.ac.cn>
Reviewed-by: Nutty Liu <nutty.liu@hotmail.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://patch.msgid.link/20250826162939.1494021-2-pincheng.plct@isrc.iscas.ac.cn
Signed-off-by: Paul Walmsley <pjw@kernel.org>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
mainline inclusion
from mainline-6.19-rc2
commit 3f0cbfb
category: feature
bugzilla: RVCK-Project#304

--------------------------------

Add parsing for Zilsd and Zclsd ISA extensions which were ratified in
commit f88abf1 ("Integrating load/store pair for RV32 with the
main manual") of the riscv-isa-manual.

Signed-off-by: Pincheng Wang <pincheng.plct@isrc.iscas.ac.cn>
Reviewed-by: Nutty Liu <nutty.liu@hotmail.com>
Link: https://patch.msgid.link/20250826162939.1494021-3-pincheng.plct@isrc.iscas.ac.cn
[pjw@kernel.org: cleaned up checkpatch issues, whitespace; updated to apply]
Signed-off-by: Paul Walmsley <pjw@kernel.org>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
mainline inclusion
from mainline-6.19-rc2
commit 6118ebe
category: feature
bugzilla: RVCK-Project#304

--------------------------------

Export Zilsd and Zclsd ISA extensions through hwprobe.

Signed-off-by: Pincheng Wang <pincheng.plct@isrc.iscas.ac.cn>
Reviewed-by: Nutty Liu <nutty.liu@hotmail.com>
Link: https://patch.msgid.link/20250826162939.1494021-4-pincheng.plct@isrc.iscas.ac.cn
[pjw@kernel.org: fixed whitespace; updated to apply]
Signed-off-by: Paul Walmsley <pjw@kernel.org>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
mainline inclusion
from mainline-6.19-rc2
commit f326e84
category: feature
bugzilla: RVCK-Project#304

--------------------------------

Extend the KVM ISA extension ONE_REG interface to allow KVM user space
to detect and enable Zilsd and Zclsd extensions for Guest/VM.

Signed-off-by: Pincheng Wang <pincheng.plct@isrc.iscas.ac.cn>
Reviewed-by: Nutty Liu <nutty.liu@hotmail.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Link: https://lore.kernel.org/r/20250826162939.1494021-5-pincheng.plct@isrc.iscas.ac.cn
Signed-off-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
…test

mainline inclusion
from mainline-6.19-rc2
commit ab2a7b7
category: feature
bugzilla: RVCK-Project#304

--------------------------------

The KVM RISC-V allows Zilsd and Zclsd extensions for Guest/VM so add
this extension to get-reg-list test.

Signed-off-by: Pincheng Wang <pincheng.plct@isrc.iscas.ac.cn>
Reviewed-by: Nutty Liu <nutty.liu@hotmail.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Link: https://lore.kernel.org/r/20250826162939.1494021-6-pincheng.plct@isrc.iscas.ac.cn
Signed-off-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
@github-actions

github-actions Bot commented Jul 1, 2026

Copy link
Copy Markdown

开始测试 log: https://github.com/RVCK-Project/rvck/actions/runs/28497794520

参数解析结果
args value
repository RVCK-Project/rvck
head ref pull/305/head
base ref rvck-6.6
LAVA repo RVCK-Project/lavaci
LAVA hardware ['qemu']
LAVA Testcase path lava-testcases/common-test/ltp/ltp.yaml
need run job kunit-test,kernel-build,check-patch,lava-trigger

测试完成

详细结果:
check result
kunit-test success
kernel-build success
check-patch success
lava-trigger-qemu success
lava-trigger-sg2042 skipped
lava-trigger-k1 skipped
lava-trigger-lpi4a skipped

Kunit Test Result

[06:23:24] Testing complete. Ran 482 tests: passed: 465, skipped: 17

Kernel Build Result

Check Patch Result

Total Errors 0
Total Warnings 31

LAVA Check (qemu)

args value
testcase_repo RVCK-Project/lavaci
lava_template lava-job-template/qemu/qemu-ltp.yaml
testcase_path lava-testcases/common-test/ltp/ltp.yaml
kernel_download_url http://10.30.190.110/openEuler-RISC-V/RVCK/OERV-RVCI/RVCK-Project/rvck/305_28497794520_1/Image
initramfs_download_url http://10.30.190.110/openEuler-RISC-V/RVCK/OERV-RVCI/RVCK-Project/rvck/305_28497794520_1/initramfs.img
rootfs_download_url https://fast-mirror.isrc.ac.cn/openeuler-sig-riscv/openEuler-RISC-V/RVCK/openEuler24.03-LTS-SP1/openeuler-rootfs.img.zst
testcase_ref main
testitem_name RVCK-Project_rvck_pull_request_target_305__common-test_qemu

result: Lava check done!

@unicornx

unicornx commented Jul 1, 2026

Copy link
Copy Markdown

@uestc-gr 我看到 binding 那个文件你补充了非常多的扩展,请问一下你是根据什么原则加的呢,是因为逐级依赖的原因,还是说这些扩展的确已经在 6.6.y 中(包括 rvck 中)支持了?

我开始以为只要补充一个 Zca, 怎么补充了那么多?:(

@uestc-gr

uestc-gr commented Jul 1, 2026

Copy link
Copy Markdown
Contributor Author

@uestc-gr 我看到 binding 那个文件你补充了非常多的扩展,请问一下你是根据什么原则加的呢,是因为逐级依赖的原因,还是说这些扩展的确已经在 6.6.y 中(包括 rvck 中)支持了?

我开始以为只要补充一个 Zca, 怎么补充了那么多?:(

这些都是rva23的扩展,这些特性都已经支持了,因为前面的补丁都没合dt-bings,我把缺的都补充了

@unicornx unicornx left a comment

Copy link
Copy Markdown

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Reviewed-by: wangchen20@iscas.ac.cn

@sterling-teng

Copy link
Copy Markdown
Contributor

已经合并进rvck-6.6。

@sterling-teng
sterling-teng merged commit cc8d212 into RVCK-Project:rvck-6.6 Jul 14, 2026
53 checks passed
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels

Projects

None yet

Development

Successfully merging this pull request may close these issues.

【Backport】Add Zilsd/Zclsd support in hwprobe and KVM