diff --git a/tools/perf/pmu-events/arch/riscv/lrw/lrw-core/exception.json b/tools/perf/pmu-events/arch/riscv/lrw/lrw-core/exception.json index 26b10dbd2e4f..cb77fdc90c8e 100644 --- a/tools/perf/pmu-events/arch/riscv/lrw/lrw-core/exception.json +++ b/tools/perf/pmu-events/arch/riscv/lrw/lrw-core/exception.json @@ -5,14 +5,14 @@ "BriefDescription": "Exception taken" }, { - "EventName": "EXC_RETURN", + "EventName": "FLUSH_RETURN", "EventCode": "0x0000020a", - "BriefDescription": "Exception return" + "BriefDescription": "Flush return" }, { - "EventName": "EXC_UNDEF", + "EventName": "EXC_ILL_INS", "EventCode": "0x0000040a", - "BriefDescription": "Undefined exception taken locally" + "BriefDescription": "Illegal Instruction exception taken locally" }, { "EventName": "EXC_ECALL_U", @@ -20,24 +20,24 @@ "BriefDescription": "User Call exception taken locally" }, { - "EventName": "EXC_PABORT", + "EventName": "EXC_PA", "EventCode": "0x0000100a", - "BriefDescription": "Instruction abort exception taken locally" + "BriefDescription": "Instruction exception or debug breakpoint taken locally" }, { - "EventName": "EXC_DABORT", + "EventName": "EXC_DA", "EventCode": "0x0000200a", - "BriefDescription": "Data abort or SError taken locally" + "BriefDescription": "Data access or address breakpoint taken locally" }, { - "EventName": "EXC_IRQ", + "EventName": "EXC_INT_S", "EventCode": "0x0000400a", - "BriefDescription": "IRQ exception taken locally" + "BriefDescription": "S/VS mode interrupt taken locally" }, { - "EventName": "EXC_FIQ", + "EventName": "EXC_INT_M", "EventCode": "0x0000800a", - "BriefDescription": "FIQ exception taken locally" + "BriefDescription": "M mode interrupt taken locally" }, { "EventName": "EXC_ECALL_M", @@ -50,14 +50,14 @@ "BriefDescription": "S-mode Call exception" }, { - "EventName": "EXC_TRAP_PABORT", + "EventName": "EXC_TRAP_PA", "EventCode": "0x0004000a", - "BriefDescription": "Instruction abort exception not taken locally" + "BriefDescription": "Instruction exception or debug breakpoint not taken locally" }, { - "EventName": "EXC_TRAP_DABORT", + "EventName": "EXC_TRAP_DA", "EventCode": "0x0008000a", - "BriefDescription": "Data abort or SError not taken locally" + "BriefDescription": "Data access or address breakpoint not taken locally" }, { "EventName": "EXC_ECALL_VS", @@ -65,14 +65,14 @@ "BriefDescription": "VS-mode Call exception" }, { - "EventName": "EXC_TRAP_IRQ", + "EventName": "EXC_TRAP_INT_S", "EventCode": "0x0020000a", - "BriefDescription": "IRQ exception not taken locally" + "BriefDescription": "S/VS mode interrupt not taken locally" }, { - "EventName": "EXC_TRAP_FIQ", + "EventName": "EXC_TRAP_INT_M", "EventCode": "0x0040000a", - "BriefDescription": "FIQ exception not taken locally" + "BriefDescription": "M mode interrupt exception not taken locally" }, { "EventName": "FLUSH", diff --git a/tools/perf/pmu-events/arch/riscv/lrw/lrw-core/l1dcache.json b/tools/perf/pmu-events/arch/riscv/lrw/lrw-core/l1dcache.json index e66a559c69f6..bca76be0e815 100644 --- a/tools/perf/pmu-events/arch/riscv/lrw/lrw-core/l1dcache.json +++ b/tools/perf/pmu-events/arch/riscv/lrw/lrw-core/l1dcache.json @@ -22,42 +22,42 @@ { "EventName": "L1D_CACHE_RD", "EventCode": "0x00001001", - "BriefDescription": "L1 data cache read" + "BriefDescription": "L1 data cache access, read" }, { "EventName": "L1D_CACHE_WR", "EventCode": "0x00002001", - "BriefDescription": "L1 data cache write" + "BriefDescription": "L1 data cache access, write" }, { "EventName": "L1D_CACHE_REFILL_RD", "EventCode": "0x00004001", - "BriefDescription": "L1 data cache refill read" + "BriefDescription": "L1 data cache refill, read" }, { "EventName": "L1D_CACHE_REFILL_WR", "EventCode": "0x00008001", - "BriefDescription": "L1 data cache refill write" + "BriefDescription": "L1 data cache refill, write" }, { "EventName": "L1D_CACHE_REFILL_INNER", "EventCode": "0x00010001", - "BriefDescription": "L1 data cache refill inner" + "BriefDescription": "L1 data cache refill, inner" }, { "EventName": "L1D_CACHE_REFILL_OUTER", "EventCode": "0x00020001", - "BriefDescription": "L1 data cache refill outer" + "BriefDescription": "L1 data cache refill, outer" }, { "EventName": "L1D_CACHE_WB_VICTIM", "EventCode": "0x00040001", - "BriefDescription": "L1 data cache write-back victim" + "BriefDescription": "L1 data cache write-back, victim" }, { "EventName": "L1D_CACHE_WB_CLEAN", "EventCode": "0x00080001", - "BriefDescription": "L1 data cache write-back clean" + "BriefDescription": "L1 data cache write-back cleaning and coherency" }, { "EventName": "L1D_CACHE_INVAL", diff --git a/tools/perf/pmu-events/arch/riscv/lrw/lrw-core/l2cache.json b/tools/perf/pmu-events/arch/riscv/lrw/lrw-core/l2cache.json index 0751e31b1610..8e82fd4757af 100644 --- a/tools/perf/pmu-events/arch/riscv/lrw/lrw-core/l2cache.json +++ b/tools/perf/pmu-events/arch/riscv/lrw/lrw-core/l2cache.json @@ -7,7 +7,7 @@ { "EventName": "L2_CACHE_REFILL", "EventCode": "0x00000203", - "BriefDescription": "L2cache refill" + "BriefDescription": "L2 cache refill" }, { "EventName": "L2_CACHE_WB", diff --git a/tools/perf/pmu-events/arch/riscv/lrw/lrw-core/l3cache.json b/tools/perf/pmu-events/arch/riscv/lrw/lrw-core/l3cache.json index a76e53da9296..40d4e9bee919 100644 --- a/tools/perf/pmu-events/arch/riscv/lrw/lrw-core/l3cache.json +++ b/tools/perf/pmu-events/arch/riscv/lrw/lrw-core/l3cache.json @@ -10,23 +10,8 @@ "BriefDescription": "Last level cache access, read" }, { - "EventName": "L3_CACHE_REFILL", + "EventName": "EXT_DATSRC_CACHE_REFILL", "EventCode": "0x00000404", - "BriefDescription": "Attributable L3 unified cache refill" - }, - { - "EventName": "L3_CACHE_RD", - "EventCode": "0x00000804", - "BriefDescription": "L3 cache read" - }, - { - "EventName": "L3_CACHE_ALLOCATE", - "EventCode": "0x00001004", - "BriefDescription": "Attributable L3 data cache allocation without refill" - }, - { - "EventName": "L3_CACHE", - "EventCode": "0x00002004", - "BriefDescription": "Attributable Level 3 unified cache access" + "BriefDescription": "External data source cache" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/riscv/lrw/lrw-core/ldst.json b/tools/perf/pmu-events/arch/riscv/lrw/lrw-core/ldst.json index 1ff880296cbf..0c944a3dcc94 100644 --- a/tools/perf/pmu-events/arch/riscv/lrw/lrw-core/ldst.json +++ b/tools/perf/pmu-events/arch/riscv/lrw/lrw-core/ldst.json @@ -2,27 +2,27 @@ { "EventName": "UNALIGNED_LD_SPEC", "EventCode": "0x00000107", - "BriefDescription": "Unaligned load speculation" + "BriefDescription": "Unaligned access, read" }, { "EventName": "UNALIGNED_ST_SPEC", "EventCode": "0x00000207", - "BriefDescription": "Unaligned store speculation" + "BriefDescription": "Unaligned access, write" }, { "EventName": "UNALIGNED_LDST_SPEC", "EventCode": "0x00000407", - "BriefDescription": "Unaligned load/store speculation" + "BriefDescription": "Unaligned access" }, { "EventName": "LD_SPEC", "EventCode": "0x00000807", - "BriefDescription": "Load speculation" + "BriefDescription": "Load instruction speculatively executed" }, { "EventName": "ST_SPEC", "EventCode": "0x00001007", - "BriefDescription": "Store speculation" + "BriefDescription": "Store instruction speculatively executed" }, { "EventName": "SFENCE_SPEC", @@ -37,12 +37,12 @@ { "EventName": "RC_LD_SPEC", "EventCode": "0x00008007", - "BriefDescription": "RC load speculation" + "BriefDescription": "Load-acquire operation speculatively executed" }, { "EventName": "RC_ST_SPEC", "EventCode": "0x00010007", - "BriefDescription": "RC store speculation" + "BriefDescription": "Store-release operation speculatively executed" }, { "EventName": "LR_SPEC", @@ -52,16 +52,16 @@ { "EventName": "SC_PASS_SPEC", "EventCode": "0x00040007", - "BriefDescription": "Successful store-condiitional speculatively executed" + "BriefDescription": "Successful store-conditional speculatively executed" }, { - "EventName": "SC_FAlL_SPEC", + "EventName": "SC_FAIL_SPEC", "EventCode": "0x00080007", - "BriefDescription": "Failed store-condiitional speculatively executed" + "BriefDescription": "Failed store-conditional speculatively executed" }, { "EventName": "SC_SPEC", "EventCode": "0x00100007", - "BriefDescription": "Store-condiitional speculatively executed" + "BriefDescription": "Store-conditional speculatively executed" } ] diff --git a/tools/perf/pmu-events/arch/riscv/lrw/lrw-core/mem.json b/tools/perf/pmu-events/arch/riscv/lrw/lrw-core/mem.json index 3f9371de2af7..25915eccfaf9 100644 --- a/tools/perf/pmu-events/arch/riscv/lrw/lrw-core/mem.json +++ b/tools/perf/pmu-events/arch/riscv/lrw/lrw-core/mem.json @@ -2,7 +2,7 @@ { "EventName": "MEM_ACCESS", "EventCode": "0x00000105", - "BriefDescription": "Memory access" + "BriefDescription": "Data memory access" }, { "EventName": "BUS_ACCESS", @@ -12,12 +12,12 @@ { "EventName": "MEMORY_ERROR", "EventCode": "0x00000405", - "BriefDescription": "Memory error" + "BriefDescription": "Local memory error" }, { "EventName": "REMOTE_ACCESS", "EventCode": "0x00000805", - "BriefDescription": "Remote access" + "BriefDescription": "Access to another socket in a multi-socket system" }, { "EventName": "BUS_ACCESS_RD", @@ -32,27 +32,27 @@ { "EventName": "MEM_ACCESS_RD", "EventCode": "0x00004005", - "BriefDescription": "Memory access read" + "BriefDescription": "Data memory access, read" }, { "EventName": "MEM_ACCESS_WR", "EventCode": "0x00008005", - "BriefDescription": "Memory access write" + "BriefDescription": "Data memory access, write" }, { "EventName": "LDST_ALIGN_LAT", "EventCode": "0x00010005", - "BriefDescription": "Load/store align latency" + "BriefDescription": "Access with additional latency from alignment" }, { "EventName": "LD_ALIGN_LAT", "EventCode": "0x00020005", - "BriefDescription": "Load align latency" + "BriefDescription": "Load with additional latency from alignment" }, { "EventName": "ST_ALIGN_LAT", "EventCode": "0x00040005", - "BriefDescription": "Store align latency" + "BriefDescription": "Store with additional latency from alignment" }, { "EventName": "BUS_REQUEST_REQ", @@ -82,12 +82,12 @@ { "EventName": "TBW_DESC", "EventCode": "0x008000005", - "BriefDescription": "Page Table Walk Descriptor" + "BriefDescription": "TBW descriptor" }, { "EventName": "S1L2_HIT", "EventCode": "0x010000005", - "BriefDescription": "Stage1 level 2 page table hit" + "BriefDescription": "Stage 1 level 2 page table hit" }, { "EventName": "S1L1_HIT", @@ -142,7 +142,7 @@ { "EventName": "MTT_L3_HIT", "EventCode": "0x8000000005", - "BriefDescription": "Memory tracking table level 3 hit" + "BriefDescription": "Memory tracking table level 3 hit" }, { "EventName": "MTT_L2_HIT", diff --git a/tools/perf/pmu-events/arch/riscv/lrw/lrw-core/pipeline.json b/tools/perf/pmu-events/arch/riscv/lrw/lrw-core/pipeline.json index 1773b59e4aca..2a03a943382f 100644 --- a/tools/perf/pmu-events/arch/riscv/lrw/lrw-core/pipeline.json +++ b/tools/perf/pmu-events/arch/riscv/lrw/lrw-core/pipeline.json @@ -2,55 +2,55 @@ { "EventName": "STALL_FRONTEND", "EventCode": "0x00000106", - "BriefDescription": "Frontend stall" + "BriefDescription": "No operation issued due to the frontend" }, { "EventName": "STALL_BACKEND", "EventCode": "0x00000206", - "BriefDescription": "Backend stall" + "BriefDescription": "No operation issued due to the backend" }, { "EventName": "STALL", "EventCode": "0x00000406", - "BriefDescription": "Stall" + "BriefDescription": "No operation sent for execution" }, { "EventName": "STALL_SLOT_BACKEND", "EventCode": "0x00000806", - "BriefDescription": "Backend stall slot" + "BriefDescription": "No operation sent for execution on a slot due to the backend" }, { "EventName": "STALL_SLOT_FRONTEND", "EventCode": "0x00001006", - "BriefDescription": "Frontend stall slot" + "BriefDescription": "No operation sent for execution on a slot due to the frontend" }, { "EventName": "STALL_SLOT", "EventCode": "0x00002006", - "BriefDescription": "Stall slot" + "BriefDescription": "No operation sent for execution on a slot" }, { "EventName": "STALL_BACKEND_MEM", "EventCode": "0x00004006", - "BriefDescription": "Backend stall due to memory" + "BriefDescription": "No operation sent due to the backend and memory stalls" }, { "EventName": "IDR_STALL_IXU_SCHED", "EventCode": "0x00008006", - "BriefDescription": "IXU scheduler stall" + "BriefDescription": "Dispatch stall due to IXU scheduler entries" }, { - "EventName": "VX_IQ_STALL", + "EventName": "IDR_STALL_FSU_SCHED", "EventCode": "0x00010006", "BriefDescription": "Dispatch stall due to VX scheduler entries" }, { - "EventName": "MCQ_FULL_STALL", + "EventName": "IDR_STALL_ROB_ID", "EventCode": "0x00020006", "BriefDescription": "Dispatch stall due to MCQ entries" }, { - "EventName": "STALL_FRONTED_FLUSH", + "EventName": "IDR_STALL_FLUSH", "EventCode": "0x00040006", "BriefDescription": "Dispatch stall due to fronted flush" }, @@ -120,13 +120,13 @@ "BriefDescription": "No operation issued due to the front cache" }, { - "EventName": "FPG", + "EventName": "LIVELOCK", "EventCode": "0x200000006", - "BriefDescription": "Front-End Pipeline Gating" + "BriefDescription": "Livelock" }, { - "EventName": "VTYPE_FLUSH", + "EventName": "FLUSH_VTYPE", "EventCode": "0x400000006", - "BriefDescription": "Flush due to fialed prediction of writing vtype csr" + "BriefDescription": "Flush due to failed prediction of writing vtype csr" } ] diff --git a/tools/perf/pmu-events/arch/riscv/lrw/lrw-core/spe.json b/tools/perf/pmu-events/arch/riscv/lrw/lrw-core/spe.json deleted file mode 100644 index 08e80365e044..000000000000 --- a/tools/perf/pmu-events/arch/riscv/lrw/lrw-core/spe.json +++ /dev/null @@ -1,7 +0,0 @@ -[ - { - "EventName": "SAMPLE_POP", - "EventCode": "0x0000010d", - "BriefDescription": "Sample population" - } -] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/riscv/lrw/lrw-core/tlb.json b/tools/perf/pmu-events/arch/riscv/lrw/lrw-core/tlb.json index d1deb3496cb4..cb2b445b101d 100644 --- a/tools/perf/pmu-events/arch/riscv/lrw/lrw-core/tlb.json +++ b/tools/perf/pmu-events/arch/riscv/lrw/lrw-core/tlb.json @@ -42,22 +42,22 @@ { "EventName": "L1D_TLB_REFILL_RD", "EventCode": "0x00020000", - "BriefDescription": "L1 data TLB refill read" + "BriefDescription": "L1 data TLB refill, read" }, { "EventName": "L1D_TLB_REFILL_WR", "EventCode": "0x00040000", - "BriefDescription": "L1 data TLB refill write" + "BriefDescription": "L1 data TLB refill, write" }, { "EventName": "L1D_TLB_RD", "EventCode": "0x00080000", - "BriefDescription": "L1 data TLB read" + "BriefDescription": "L1 data TLB access, read" }, { "EventName": "L1D_TLB_WR", "EventCode": "0x00100000", - "BriefDescription": "L1 data TLB write" + "BriefDescription": "L1 data TLB access, write" }, { "EventName": "L2_TLB_REFILL_RD", diff --git a/tools/perf/pmu-events/arch/riscv/lrw/lrw-core/vec.json b/tools/perf/pmu-events/arch/riscv/lrw/lrw-core/vec.json index fe8c4c9fedc5..1b1ed6a3d7bd 100644 --- a/tools/perf/pmu-events/arch/riscv/lrw/lrw-core/vec.json +++ b/tools/perf/pmu-events/arch/riscv/lrw/lrw-core/vec.json @@ -51,32 +51,32 @@ }, { "EventName": "FP_VEC_SPEC", - "EventCode": "0x010000c", + "EventCode": "0x0010000c", "BriefDescription": "Vector floating-point element operations speculatively executed" }, { "EventName": "FP_SCALE_SPEC", - "EventCode": "0x020000c", + "EventCode": "0x0020000c", "BriefDescription": "Scalable floating-point element operations speculatively executed" }, { "EventName": "VEC_INT08_SPEC", - "EventCode": "0x040000c", + "EventCode": "0x0040000c", "BriefDescription": "Operation counted by VEC_INT_SPEC where the largest type is 8-bit integer" }, { "EventName": "VEC_INT16_SPEC", - "EventCode": "0x080000c", + "EventCode": "0x0080000c", "BriefDescription": "Operation counted by ASE_SVE_INT_SPEC where the largest type is 16-bit integer" }, { "EventName": "VEC_INT32_SPEC", - "EventCode": "0x100000c", + "EventCode": "0x0100000c", "BriefDescription": "Operation counted by ASE_SVE_INT_SPEC where the largest type is 32-bit integer" }, { "EventName": "VEC_INT64_SPEC", - "EventCode": "0x200000c", + "EventCode": "0x0200000c", "BriefDescription": "Operation counted by ASE_SVE_INT_SPEC where the largest type is 64-bit integer" } ]