GPIO Pin Layout

[PlasmaTrout]

How should we do the PIN layouts. Essentially there are two sections P8 and P9 each starting at Pin 1. I think the whole underscore P8_1 thing is a little terse. Maybe we could just take header as a separate argument?

[DropChain]

Unless you want to try and map it to like Con1_1 which would correspond to
P8_1. If you you are trying to apply a common name to it then that is going
to be hard depending on the component that connected to it and how you are
applying the voltage. We could derive a common name by exploring the
community to find out the most common uses for each of the pins and which
mux they are using. So you could have several different common names for
each pin and mux setting. If I remember right, there are 7 mux setttings
for each pin. I'm sure on average, there are at most 3 popular mux
settings. We could come up with a common name for each of them.

I'm messing with my router as I speak so I can have the bone directly on
the internet full time, so I will be up and down all night.

On Fri, Mar 23, 2012 at 8:29 PM, PlasmaTrout <
reply@reply.github.com

wrote:

How should we do the PIN layouts. Essentially there are two sections P8
and P9 each starting at Pin 1. I think the whole underscore P8_1 thing is a
little terse. Maybe we could just take header as a separate argument?

---

Reply to this email directly or view it on GitHub:
#1

[PlasmaTrout]

I did the whole PIN8_X thing in the last header I just uploaded. The next issue is that each PIN has 7 mux modes and I need to be able to resolve their mux name to make it work. Bah I'm going to bed.

[PlasmaTrout]

https://github.com/PlasmaTrout/Beaglebone-CLIB/blob/master/include/beaglepins.h