diff --git a/src/glayout/cells/composite/diffpair_cmirror_bias/diff_pair_cmirrorbias.py b/src/glayout/cells/composite/diffpair_cmirror_bias/diff_pair_cmirrorbias.py
index c1a47743..63a63a7d 100644
--- a/src/glayout/cells/composite/diffpair_cmirror_bias/diff_pair_cmirrorbias.py
+++ b/src/glayout/cells/composite/diffpair_cmirror_bias/diff_pair_cmirrorbias.py
@@ -163,7 +163,7 @@ def diff_pair_ibias(
         gate_route_topmet="met3",
         sd_route_topmet="met3",
         rmult=rmult,
-        tie_layers=("met2", "met2"),
+        tie_layers=("met2", "met1"),
     )
     # cmirror routing
     metal_sep = pdk.util_max_metal_seperation()
@@ -194,6 +194,12 @@ def diff_pair_ibias(
         viaoffset=None,
     )
     cmirror.add_ports(srcshort.get_ports_list(), prefix="purposegndports")
+    _lastcol = diffpair_bias[2] - 1
+    # Ground the outer dummies to the welltie — same recipe as the standalone
+    # current_mirror cell (which passes DRC+LVS on both PDKs): met1 strap to
+    # the ring's met1 vertical segment.
+    cmirror << straight_route(pdk, cmirror.ports["A_0_dummy_L_gsdcon_top_met_W"], cmirror.ports["welltie_W_top_met_W"], glayer2="met1")
+    cmirror << straight_route(pdk, cmirror.ports[f"B_{_lastcol}_dummy_R_gsdcon_top_met_E"], cmirror.ports["welltie_E_top_met_E"], glayer2="met1")
     # current mirror netlist — gf180 needs `dummies_tied_to_bulk=False`
     # because here we use raw two_nfet_interdigitized + custom routing,
     # NOT current_mirror, so the standalone-cell's straight_route from
@@ -201,9 +207,7 @@ def diff_pair_ibias(
     # cmirror dummies on a per-cell floating net. sky130 magic merges
     # the floating dummies into the bulk so the schematic must keep
     # them tied to VB or magic counts an extra net.
-    ## HACK: Note that this is a hack for magic LVS, and it's likely incorrect
-    ##       we probably want to fix it properly
-    _dummies_tied = (pdk.name.lower() == "sky130")
+    _dummies_tied = True
     cmirror.info['netlist'] = current_mirror_netlist(
         pdk,
         width=diffpair_bias[0],
@@ -297,3 +301,5 @@ def diff_pair_ibias(
     diffpair_i_flat.info['netlist'] = diff_pair_ibias_netlist(center_diffpair_comp, cmirror, antenna_diode_comp)
     return diffpair_i_flat
 
+
+
diff --git a/src/glayout/cells/composite/opamp/opamp.py b/src/glayout/cells/composite/opamp/opamp.py
index cf9d1c0f..9ae9ce2d 100644
--- a/src/glayout/cells/composite/opamp/opamp.py
+++ b/src/glayout/cells/composite/opamp/opamp.py
@@ -356,7 +356,7 @@ def opamp(
         # already match an opamp top-level pin. We purge them all because
         # the opamp's add_opamp_labels below re-emits the right set on
         # the right metal.
-        ["VP", "VN", "VDD1", "VDD2", "IBIAS", "VSS", "B"],
+        ["VP", "VN", "VDD1", "VDD2", "IBIAS", "VSS", "B", "VTAIL"],
     )
     # add LVS pin/label rects so netgen can name-match the top-level signals
     opamp_top = add_opamp_labels(opamp_top, pdk, add_output_stage=add_output_stage)