Integration with GHDL

[pidgeon777]

Hi Nic30, if I recall correctly you are amongst the developers behind some of the schematic libraries used for HDL language, maybe this topic could interest you:

ghdl/ghdl#1519

Do you think that it could make sense to parse the XML produced by GHDL and represent it using your library? Or maybe the netlist generated by GHDL synthesis?

I was trying to understand what could be the most simple, easiest and efficient way to generate a simple schematic starting from a VHDL source file. We have the dumps, we have the parsers, we have the layout and schematic generation tools, the only thing needed is to put them together. I was trying to estimate the possible effort of doing this, in terms of time needed.

[Nic30]

Hello,

actually today I was doing something similar
(I parsed and elaborated Verilog design with DSPs and I used d3-hwschematic to see how things are dependent on parameters. I used hdlConvertor but it definitely does not work out of the box.)

Theoretically GHDL XML -> d3-hwschematic is easy to do and very useful.
If you are using Python you can reuse hwtGraph/elk/containers

However everything related to ASIC/FPGA/VHDL/SV usually turns out to be very complex.
I guess that you can write a prototype in the day, but GHDL has its own quirks.
Note that 1:1 translation to graph would look very ugly.

If you are going to write such a SW please keep me in the loop. I may be able to help.
Also there is a VHDL module for Yosys and Yosys can produce same thing as ghdl and does support System Verilog as well.

[pidgeon777]

Hi and first of all, thank you.

Theoretically GHDL XML -> d3-hwschematic is easy to do and very useful.
If you are using Python you can reuse hwtGraph/elk/containers

In the GHDL topic they suggested me not to use the XML because it is huge and unstable. I was directed to the libghdl Python interface instead.

The most important thing to do, is to decide which source to use for parsing all of the necessary information. So, actually:

• libghdl

• XML

• Something else...?

Anyway is that hwtGraph/elk/containers something which I could use to directly parse the XML file, or does it involve other tasks?

Also there is a VHDL module for Yosys and Yosys can produce same thing as ghdl and does support System Verilog as well.

Where could I find more info about that? And what kind of output are you referring to? Regarding the same Yosis and GHDL output statement.

[Nic30]

which source to use?

https://github.com/forflo/yodl
https://github.com/ghdl/ghdl-yosys-plugin

But I am not sure how stable it is. The reason why I am thinking more about yosys than pure GHDL is that it has larger user base.

is that hwtGraph/elk/containers something which I could use to directly parse the XML file?

The hwtGraph library is quite complicated and not so well documented. But the ELK container module is an exception and you need something to represented ELK object anyway. All classes in hwtGraph/elk/containers do have toElkJson() https://github.com/Nic30/hwtGraph/blob/master/hwtGraph/elk/containers/lNode.py#L166
which generates the ELK json. I do not think that it is good idea to use whole library for you, but I can extract some parts in to dependency free pip package if you want to.

[nobodywasishere]

@pidgeon777 ghdl-yosys-plugin can be used with ghdl and yosys to take in vhdl and generate a json file, which is what netlistsvg uses. Here's a short guide https://blog.eowyn.net/netlistsvg/