From cbfc7c5341f104a7c453d6dd6be744da7f4f1881 Mon Sep 17 00:00:00 2001 From: Mac Date: Tue, 7 Apr 2026 15:20:56 +0800 Subject: [PATCH 01/12] docs(outerCube): add VEC-4K vector4k spec and PTOISA reference MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit - vector4k.md: dataflow (TRegFile, control, crossbar, 128 groups, ping-pong Acc), N_run/N_tree/#W scheduling, simplified §9.7 shape table, Acc RMW vs bypass-to-DFF - PTOISA/: tile ISA reference (linked from vector4k.md) Made-with: Cursor --- designs/outerCube/PTOISA/MGATHER.md | 100 ++ designs/outerCube/PTOISA/MGATHER_zh.md | 100 ++ designs/outerCube/PTOISA/MSCATTER.md | 105 ++ designs/outerCube/PTOISA/MSCATTER_zh.md | 105 ++ designs/outerCube/PTOISA/PTOISA.md | 152 +++ designs/outerCube/PTOISA/README.md | 153 +++ designs/outerCube/PTOISA/README_zh.md | 153 +++ designs/outerCube/PTOISA/TABS.md | 133 +++ designs/outerCube/PTOISA/TABS_zh.md | 106 ++ designs/outerCube/PTOISA/TADD.md | 129 +++ designs/outerCube/PTOISA/TADDC.md | 103 ++ designs/outerCube/PTOISA/TADDC_zh.md | 76 ++ designs/outerCube/PTOISA/TADDS.md | 134 +++ designs/outerCube/PTOISA/TADDSC.md | 116 +++ designs/outerCube/PTOISA/TADDSC_zh.md | 89 ++ designs/outerCube/PTOISA/TADDS_zh.md | 107 ++ designs/outerCube/PTOISA/TADD_zh.md | 102 ++ designs/outerCube/PTOISA/TALIAS.md | 40 + designs/outerCube/PTOISA/TALIAS_zh.md | 41 + designs/outerCube/PTOISA/TAND.md | 103 ++ designs/outerCube/PTOISA/TANDS.md | 106 ++ designs/outerCube/PTOISA/TANDS_zh.md | 106 ++ designs/outerCube/PTOISA/TAND_zh.md | 103 ++ designs/outerCube/PTOISA/TASSIGN.md | 219 ++++ designs/outerCube/PTOISA/TASSIGN_zh.md | 192 ++++ designs/outerCube/PTOISA/TAXPY.md | 40 + designs/outerCube/PTOISA/TAXPY_zh.md | 41 + designs/outerCube/PTOISA/TCI.md | 133 +++ designs/outerCube/PTOISA/TCI_zh.md | 106 ++ designs/outerCube/PTOISA/TCMP.md | 142 +++ designs/outerCube/PTOISA/TCMPS.md | 140 +++ designs/outerCube/PTOISA/TCMPS_zh.md | 113 ++ designs/outerCube/PTOISA/TCMP_zh.md | 115 +++ designs/outerCube/PTOISA/TCOLARGMAX.md | 178 ++++ designs/outerCube/PTOISA/TCOLARGMAX_zh.md | 178 ++++ designs/outerCube/PTOISA/TCOLARGMIN.md | 172 ++++ designs/outerCube/PTOISA/TCOLARGMIN_zh.md | 172 ++++ designs/outerCube/PTOISA/TCOLEXPAND.md | 103 ++ designs/outerCube/PTOISA/TCOLEXPANDADD.md | 89 ++ designs/outerCube/PTOISA/TCOLEXPANDADD_zh.md | 89 ++ designs/outerCube/PTOISA/TCOLEXPANDDIV.md | 89 ++ designs/outerCube/PTOISA/TCOLEXPANDDIV_zh.md | 89 ++ designs/outerCube/PTOISA/TCOLEXPANDEXPDIF.md | 89 ++ .../outerCube/PTOISA/TCOLEXPANDEXPDIF_zh.md | 89 ++ designs/outerCube/PTOISA/TCOLEXPANDMAX.md | 90 ++ designs/outerCube/PTOISA/TCOLEXPANDMAX_zh.md | 89 ++ designs/outerCube/PTOISA/TCOLEXPANDMIN.md | 90 ++ designs/outerCube/PTOISA/TCOLEXPANDMIN_zh.md | 89 ++ designs/outerCube/PTOISA/TCOLEXPANDMUL.md | 89 ++ designs/outerCube/PTOISA/TCOLEXPANDMUL_zh.md | 89 ++ designs/outerCube/PTOISA/TCOLEXPANDSUB.md | 89 ++ designs/outerCube/PTOISA/TCOLEXPANDSUB_zh.md | 89 ++ designs/outerCube/PTOISA/TCOLEXPAND_zh.md | 76 ++ designs/outerCube/PTOISA/TCOLMAX.md | 135 +++ designs/outerCube/PTOISA/TCOLMAX_zh.md | 108 ++ designs/outerCube/PTOISA/TCOLMIN.md | 135 +++ designs/outerCube/PTOISA/TCOLMIN_zh.md | 108 ++ designs/outerCube/PTOISA/TCOLPROD.md | 135 +++ designs/outerCube/PTOISA/TCOLPROD_zh.md | 108 ++ designs/outerCube/PTOISA/TCOLSUM.md | 149 +++ designs/outerCube/PTOISA/TCOLSUM_zh.md | 122 +++ designs/outerCube/PTOISA/TCONCAT.md | 40 + designs/outerCube/PTOISA/TCONCAT_zh.md | 41 + designs/outerCube/PTOISA/TCVT.md | 124 +++ designs/outerCube/PTOISA/TCVT_zh.md | 124 +++ designs/outerCube/PTOISA/TDEQUANT.md | 40 + designs/outerCube/PTOISA/TDEQUANT_zh.md | 41 + designs/outerCube/PTOISA/TDIV.md | 137 +++ designs/outerCube/PTOISA/TDIVS.md | 155 +++ designs/outerCube/PTOISA/TDIVS_zh.md | 128 +++ designs/outerCube/PTOISA/TDIV_zh.md | 110 ++ designs/outerCube/PTOISA/TEXP.md | 128 +++ designs/outerCube/PTOISA/TEXPANDS.md | 146 +++ designs/outerCube/PTOISA/TEXPANDS_zh.md | 134 +++ designs/outerCube/PTOISA/TEXP_zh.md | 101 ++ designs/outerCube/PTOISA/TEXTRACT.md | 138 +++ designs/outerCube/PTOISA/TEXTRACT_FP.md | 90 ++ designs/outerCube/PTOISA/TEXTRACT_FP_zh.md | 59 ++ designs/outerCube/PTOISA/TEXTRACT_zh.md | 138 +++ designs/outerCube/PTOISA/TFILLPAD.md | 133 +++ designs/outerCube/PTOISA/TFILLPAD_EXPAND.md | 89 ++ .../outerCube/PTOISA/TFILLPAD_EXPAND_zh.md | 58 ++ designs/outerCube/PTOISA/TFILLPAD_INPLACE.md | 89 ++ .../outerCube/PTOISA/TFILLPAD_INPLACE_zh.md | 58 ++ designs/outerCube/PTOISA/TFILLPAD_zh.md | 108 ++ designs/outerCube/PTOISA/TFMOD.md | 104 ++ designs/outerCube/PTOISA/TFMODS.md | 107 ++ designs/outerCube/PTOISA/TFMODS_zh.md | 107 ++ designs/outerCube/PTOISA/TFMOD_zh.md | 77 ++ designs/outerCube/PTOISA/TFREE.md | 40 + designs/outerCube/PTOISA/TFREE_zh.md | 41 + designs/outerCube/PTOISA/TGATHER.md | 156 +++ designs/outerCube/PTOISA/TGATHERB.md | 141 +++ designs/outerCube/PTOISA/TGATHERB_zh.md | 114 +++ designs/outerCube/PTOISA/TGATHER_zh.md | 154 +++ designs/outerCube/PTOISA/TGEMV.md | 282 +++++ designs/outerCube/PTOISA/TGEMV_ACC.md | 166 +++ designs/outerCube/PTOISA/TGEMV_ACC_zh.md | 165 +++ designs/outerCube/PTOISA/TGEMV_BIAS.md | 178 ++++ designs/outerCube/PTOISA/TGEMV_BIAS_zh.md | 177 ++++ designs/outerCube/PTOISA/TGEMV_MX.md | 127 +++ designs/outerCube/PTOISA/TGEMV_MX_zh.md | 98 ++ designs/outerCube/PTOISA/TGEMV_zh.md | 282 +++++ designs/outerCube/PTOISA/TGET_SCALE_ADDR.md | 83 ++ .../outerCube/PTOISA/TGET_SCALE_ADDR_zh.md | 81 ++ designs/outerCube/PTOISA/THISTOGRAM.md | 40 + designs/outerCube/PTOISA/THISTOGRAM_zh.md | 41 + designs/outerCube/PTOISA/TIMG2COL.md | 85 ++ designs/outerCube/PTOISA/TIMG2COL_zh.md | 58 ++ designs/outerCube/PTOISA/TINSERT.md | 107 ++ designs/outerCube/PTOISA/TINSERT_FP.md | 90 ++ designs/outerCube/PTOISA/TINSERT_FP_zh.md | 59 ++ designs/outerCube/PTOISA/TINSERT_zh.md | 107 ++ designs/outerCube/PTOISA/TLOAD.md | 159 +++ designs/outerCube/PTOISA/TLOAD_zh.md | 132 +++ designs/outerCube/PTOISA/TLOG.md | 114 +++ designs/outerCube/PTOISA/TLOG_zh.md | 85 ++ designs/outerCube/PTOISA/TLRELU.md | 104 ++ designs/outerCube/PTOISA/TLRELU_zh.md | 104 ++ designs/outerCube/PTOISA/TMATMUL.md | 159 +++ designs/outerCube/PTOISA/TMATMUL_ACC.md | 147 +++ designs/outerCube/PTOISA/TMATMUL_ACC_zh.md | 120 +++ designs/outerCube/PTOISA/TMATMUL_BIAS.md | 153 +++ designs/outerCube/PTOISA/TMATMUL_BIAS_zh.md | 126 +++ designs/outerCube/PTOISA/TMATMUL_MX.md | 202 ++++ designs/outerCube/PTOISA/TMATMUL_MX_zh.md | 173 ++++ designs/outerCube/PTOISA/TMATMUL_zh.md | 132 +++ designs/outerCube/PTOISA/TMAX.md | 135 +++ designs/outerCube/PTOISA/TMAXS.md | 104 ++ designs/outerCube/PTOISA/TMAXS_zh.md | 104 ++ designs/outerCube/PTOISA/TMAX_zh.md | 108 ++ designs/outerCube/PTOISA/TMIN.md | 135 +++ designs/outerCube/PTOISA/TMINS.md | 121 +++ designs/outerCube/PTOISA/TMINS_zh.md | 121 +++ designs/outerCube/PTOISA/TMIN_zh.md | 108 ++ designs/outerCube/PTOISA/TMOV.md | 161 +++ designs/outerCube/PTOISA/TMOV_FP.md | 141 +++ designs/outerCube/PTOISA/TMOV_FP_zh.md | 112 ++ designs/outerCube/PTOISA/TMOV_zh.md | 161 +++ designs/outerCube/PTOISA/TMRGSORT.md | 155 +++ designs/outerCube/PTOISA/TMRGSORT_zh.md | 128 +++ designs/outerCube/PTOISA/TMUL.md | 135 +++ designs/outerCube/PTOISA/TMULS.md | 134 +++ designs/outerCube/PTOISA/TMULS_zh.md | 107 ++ designs/outerCube/PTOISA/TMUL_zh.md | 108 ++ designs/outerCube/PTOISA/TNEG.md | 103 ++ designs/outerCube/PTOISA/TNEG_zh.md | 76 ++ designs/outerCube/PTOISA/TNOT.md | 119 +++ designs/outerCube/PTOISA/TNOT_zh.md | 89 ++ designs/outerCube/PTOISA/TOR.md | 103 ++ designs/outerCube/PTOISA/TORS.md | 106 ++ designs/outerCube/PTOISA/TORS_zh.md | 106 ++ designs/outerCube/PTOISA/TOR_zh.md | 103 ++ designs/outerCube/PTOISA/TPACK.md | 40 + designs/outerCube/PTOISA/TPACK_zh.md | 41 + designs/outerCube/PTOISA/TPARTADD.md | 137 +++ designs/outerCube/PTOISA/TPARTADD_zh.md | 110 ++ designs/outerCube/PTOISA/TPARTMAX.md | 137 +++ designs/outerCube/PTOISA/TPARTMAX_zh.md | 110 ++ designs/outerCube/PTOISA/TPARTMIN.md | 137 +++ designs/outerCube/PTOISA/TPARTMIN_zh.md | 110 ++ designs/outerCube/PTOISA/TPARTMUL.md | 129 +++ designs/outerCube/PTOISA/TPARTMUL_zh.md | 102 ++ designs/outerCube/PTOISA/TPOP.md | 40 + designs/outerCube/PTOISA/TPOP_zh.md | 41 + designs/outerCube/PTOISA/TPREFETCH.md | 94 ++ designs/outerCube/PTOISA/TPREFETCH_zh.md | 65 ++ designs/outerCube/PTOISA/TPRELU.md | 106 ++ designs/outerCube/PTOISA/TPRELU_zh.md | 79 ++ designs/outerCube/PTOISA/TPRINT.md | 157 +++ designs/outerCube/PTOISA/TPRINT_zh.md | 113 ++ designs/outerCube/PTOISA/TPUSH.md | 40 + designs/outerCube/PTOISA/TPUSH_zh.md | 41 + designs/outerCube/PTOISA/TQUANT.md | 94 ++ designs/outerCube/PTOISA/TQUANT_zh.md | 67 ++ designs/outerCube/PTOISA/TRANDOM.md | 122 +++ designs/outerCube/PTOISA/TRANDOM_zh.md | 122 +++ designs/outerCube/PTOISA/TRECIP.md | 113 ++ designs/outerCube/PTOISA/TRECIP_zh.md | 86 ++ designs/outerCube/PTOISA/TRELU.md | 116 +++ designs/outerCube/PTOISA/TRELU_zh.md | 89 ++ designs/outerCube/PTOISA/TREM.md | 115 +++ designs/outerCube/PTOISA/TREMS.md | 115 +++ designs/outerCube/PTOISA/TREMS_zh.md | 115 +++ designs/outerCube/PTOISA/TREM_zh.md | 113 ++ designs/outerCube/PTOISA/TRESHAPE.md | 115 +++ designs/outerCube/PTOISA/TRESHAPE_zh.md | 81 ++ designs/outerCube/PTOISA/TROWARGMAX.md | 148 +++ designs/outerCube/PTOISA/TROWARGMAX_zh.md | 147 +++ designs/outerCube/PTOISA/TROWARGMIN.md | 148 +++ designs/outerCube/PTOISA/TROWARGMIN_zh.md | 147 +++ designs/outerCube/PTOISA/TROWEXPAND.md | 132 +++ designs/outerCube/PTOISA/TROWEXPANDADD.md | 106 ++ designs/outerCube/PTOISA/TROWEXPANDADD_zh.md | 79 ++ designs/outerCube/PTOISA/TROWEXPANDDIV.md | 126 +++ designs/outerCube/PTOISA/TROWEXPANDDIV_zh.md | 126 +++ designs/outerCube/PTOISA/TROWEXPANDEXPDIF.md | 106 ++ .../outerCube/PTOISA/TROWEXPANDEXPDIF_zh.md | 79 ++ designs/outerCube/PTOISA/TROWEXPANDMAX.md | 106 ++ designs/outerCube/PTOISA/TROWEXPANDMAX_zh.md | 79 ++ designs/outerCube/PTOISA/TROWEXPANDMIN.md | 106 ++ designs/outerCube/PTOISA/TROWEXPANDMIN_zh.md | 79 ++ designs/outerCube/PTOISA/TROWEXPANDMUL.md | 126 +++ designs/outerCube/PTOISA/TROWEXPANDMUL_zh.md | 126 +++ designs/outerCube/PTOISA/TROWEXPANDSUB.md | 126 +++ designs/outerCube/PTOISA/TROWEXPANDSUB_zh.md | 126 +++ designs/outerCube/PTOISA/TROWEXPAND_zh.md | 105 ++ designs/outerCube/PTOISA/TROWMAX.md | 135 +++ designs/outerCube/PTOISA/TROWMAX_zh.md | 135 +++ designs/outerCube/PTOISA/TROWMIN.md | 135 +++ designs/outerCube/PTOISA/TROWMIN_zh.md | 135 +++ designs/outerCube/PTOISA/TROWPROD.md | 150 +++ designs/outerCube/PTOISA/TROWPROD_zh.md | 115 +++ designs/outerCube/PTOISA/TROWSUM.md | 147 +++ designs/outerCube/PTOISA/TROWSUM_zh.md | 120 +++ designs/outerCube/PTOISA/TRSQRT.md | 134 +++ designs/outerCube/PTOISA/TRSQRT_zh.md | 107 ++ designs/outerCube/PTOISA/TSCATTER.md | 139 +++ designs/outerCube/PTOISA/TSCATTER_zh.md | 112 ++ designs/outerCube/PTOISA/TSEL.md | 140 +++ designs/outerCube/PTOISA/TSELS.md | 157 +++ designs/outerCube/PTOISA/TSELS_zh.md | 147 +++ designs/outerCube/PTOISA/TSEL_zh.md | 140 +++ designs/outerCube/PTOISA/TSETFMATRIX.md | 89 ++ designs/outerCube/PTOISA/TSETFMATRIX_zh.md | 58 ++ designs/outerCube/PTOISA/TSETHF32MODE.md | 62 ++ designs/outerCube/PTOISA/TSETHF32MODE_zh.md | 61 ++ designs/outerCube/PTOISA/TSETTF32MODE.md | 62 ++ designs/outerCube/PTOISA/TSETTF32MODE_zh.md | 61 ++ .../outerCube/PTOISA/TSET_IMG2COL_PADDING.md | 106 ++ .../PTOISA/TSET_IMG2COL_PADDING_zh.md | 80 ++ designs/outerCube/PTOISA/TSET_IMG2COL_RPT.md | 106 ++ .../outerCube/PTOISA/TSET_IMG2COL_RPT_zh.md | 80 ++ designs/outerCube/PTOISA/TSHL.md | 103 ++ designs/outerCube/PTOISA/TSHLS.md | 108 ++ designs/outerCube/PTOISA/TSHLS_zh.md | 108 ++ designs/outerCube/PTOISA/TSHL_zh.md | 103 ++ designs/outerCube/PTOISA/TSHR.md | 103 ++ designs/outerCube/PTOISA/TSHRS.md | 108 ++ designs/outerCube/PTOISA/TSHRS_zh.md | 108 ++ designs/outerCube/PTOISA/TSHR_zh.md | 103 ++ designs/outerCube/PTOISA/TSORT32.md | 150 +++ designs/outerCube/PTOISA/TSORT32_zh.md | 150 +++ designs/outerCube/PTOISA/TSQRT.md | 130 +++ designs/outerCube/PTOISA/TSQRT_zh.md | 103 ++ designs/outerCube/PTOISA/TSTORE.md | 158 +++ designs/outerCube/PTOISA/TSTORE_FP.md | 147 +++ designs/outerCube/PTOISA/TSTORE_FP_zh.md | 118 +++ designs/outerCube/PTOISA/TSTORE_zh.md | 131 +++ designs/outerCube/PTOISA/TSUB.md | 135 +++ designs/outerCube/PTOISA/TSUBC.md | 103 ++ designs/outerCube/PTOISA/TSUBC_zh.md | 76 ++ designs/outerCube/PTOISA/TSUBS.md | 105 ++ designs/outerCube/PTOISA/TSUBSC.md | 116 +++ designs/outerCube/PTOISA/TSUBSC_zh.md | 89 ++ designs/outerCube/PTOISA/TSUBS_zh.md | 105 ++ designs/outerCube/PTOISA/TSUBVIEW.md | 89 ++ designs/outerCube/PTOISA/TSUBVIEW_zh.md | 87 ++ designs/outerCube/PTOISA/TSUB_zh.md | 108 ++ designs/outerCube/PTOISA/TSYNC.md | 143 +++ designs/outerCube/PTOISA/TSYNC_zh.md | 141 +++ designs/outerCube/PTOISA/TTRANS.md | 144 +++ designs/outerCube/PTOISA/TTRANS_zh.md | 144 +++ designs/outerCube/PTOISA/TTRI.md | 98 ++ designs/outerCube/PTOISA/TTRI_zh.md | 71 ++ designs/outerCube/PTOISA/TXOR.md | 110 ++ designs/outerCube/PTOISA/TXORS.md | 105 ++ designs/outerCube/PTOISA/TXORS_zh.md | 105 ++ designs/outerCube/PTOISA/TXOR_zh.md | 110 ++ designs/outerCube/PTOISA/comm/README.md | 130 +++ designs/outerCube/PTOISA/comm/README_zh.md | 131 +++ designs/outerCube/PTOISA/comm/TBROADCAST.md | 122 +++ .../outerCube/PTOISA/comm/TBROADCAST_zh.md | 123 +++ designs/outerCube/PTOISA/comm/TGATHER.md | 128 +++ designs/outerCube/PTOISA/comm/TGATHER_zh.md | 121 +++ designs/outerCube/PTOISA/comm/TGET.md | 109 ++ designs/outerCube/PTOISA/comm/TGET_ASYNC.md | 130 +++ .../outerCube/PTOISA/comm/TGET_ASYNC_zh.md | 126 +++ designs/outerCube/PTOISA/comm/TGET_zh.md | 106 ++ designs/outerCube/PTOISA/comm/TNOTIFY.md | 100 ++ designs/outerCube/PTOISA/comm/TNOTIFY_zh.md | 101 ++ designs/outerCube/PTOISA/comm/TPUT.md | 131 +++ designs/outerCube/PTOISA/comm/TPUT_ASYNC.md | 132 +++ .../outerCube/PTOISA/comm/TPUT_ASYNC_zh.md | 126 +++ designs/outerCube/PTOISA/comm/TPUT_zh.md | 128 +++ designs/outerCube/PTOISA/comm/TREDUCE.md | 118 +++ designs/outerCube/PTOISA/comm/TREDUCE_zh.md | 112 ++ designs/outerCube/PTOISA/comm/TSCATTER.md | 126 +++ designs/outerCube/PTOISA/comm/TSCATTER_zh.md | 120 +++ designs/outerCube/PTOISA/comm/TTEST.md | 150 +++ designs/outerCube/PTOISA/comm/TTEST_zh.md | 151 +++ designs/outerCube/PTOISA/comm/TWAIT.md | 131 +++ designs/outerCube/PTOISA/comm/TWAIT_zh.md | 131 +++ designs/outerCube/PTOISA/conventions.md | 41 + designs/outerCube/PTOISA/conventions_zh.md | 42 + designs/outerCube/vector4k.md | 962 ++++++++++++++++++ 296 files changed, 34170 insertions(+) create mode 100644 designs/outerCube/PTOISA/MGATHER.md create mode 100644 designs/outerCube/PTOISA/MGATHER_zh.md create mode 100644 designs/outerCube/PTOISA/MSCATTER.md create mode 100644 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mode 100644 designs/outerCube/PTOISA/TCOLEXPANDADD_zh.md create mode 100644 designs/outerCube/PTOISA/TCOLEXPANDDIV.md create mode 100644 designs/outerCube/PTOISA/TCOLEXPANDDIV_zh.md create mode 100644 designs/outerCube/PTOISA/TCOLEXPANDEXPDIF.md create mode 100644 designs/outerCube/PTOISA/TCOLEXPANDEXPDIF_zh.md create mode 100644 designs/outerCube/PTOISA/TCOLEXPANDMAX.md create mode 100644 designs/outerCube/PTOISA/TCOLEXPANDMAX_zh.md create mode 100644 designs/outerCube/PTOISA/TCOLEXPANDMIN.md create mode 100644 designs/outerCube/PTOISA/TCOLEXPANDMIN_zh.md create mode 100644 designs/outerCube/PTOISA/TCOLEXPANDMUL.md create mode 100644 designs/outerCube/PTOISA/TCOLEXPANDMUL_zh.md create mode 100644 designs/outerCube/PTOISA/TCOLEXPANDSUB.md create mode 100644 designs/outerCube/PTOISA/TCOLEXPANDSUB_zh.md create mode 100644 designs/outerCube/PTOISA/TCOLEXPAND_zh.md create mode 100644 designs/outerCube/PTOISA/TCOLMAX.md create mode 100644 designs/outerCube/PTOISA/TCOLMAX_zh.md create mode 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a/designs/outerCube/PTOISA/MGATHER.md b/designs/outerCube/PTOISA/MGATHER.md new file mode 100644 index 00000000..e092860b --- /dev/null +++ b/designs/outerCube/PTOISA/MGATHER.md @@ -0,0 +1,100 @@ +# MGATHER + + +## Tile Operation Diagram + +![MGATHER tile operation](../figures/isa/MGATHER.svg) + +## Introduction + +Gather-load elements from global memory into a tile using per-element indices. + +## Math Interpretation + +For each element `(i, j)` in the destination valid region: + +$$ \mathrm{dst}_{i,j} = \mathrm{mem}[\mathrm{idx}_{i,j}] $$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = mgather %mem, %idx : !pto.memref<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.mgather %mem, %idx : (!pto.partition_tensor_view, pto.tile<...>) +-> !pto.tile +``` + +### AS Level 2 (DPS) + +```text +pto.mgather ins(%mem, %idx : !pto.partition_tensor_view, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent MGATHER(TileDst &dst, GlobalData &src, TileInd &indexes, WaitEvents &... events); +``` + +## Constraints + +- **Supported data types**: + - `dst`/`src` element type must be one of: `uint8_t`, `int8_t`, `uint16_t`, `int16_t`, `uint32_t`, `int32_t`, `half`, `bfloat16_t`, `float`. + - On AICore targets, `float8_e4m3_t` and `float8_e5m2_t` are also supported. + - `indexes` element type must be `int32_t` or `uint32_t`. +- **Tile and memory types**: + - `dst` must be a vector tile (`TileType::Vec`). + - `indexes` must be a vector tile (`TileType::Vec`). + - `dst` and `indexes` must use row-major layout. + - `src` must be a `GlobalTensor` in GM memory. + - `src` must use `ND` layout. +- **Shape constraints**: + - `dst.Rows == indexes.Rows`. + - `indexes` must be shaped as `[N, 1]` for row-indexed gather or `[N, M]` for element-indexed gather. + - `dst` row width must be 32-byte aligned, that is, `dst.Cols * sizeof(DType)` must be a multiple of 32. + - `src` static shape must satisfy `Shape<1, 1, 1, TableRows, RowWidth>`. +- **Index interpretation**: + - Index interpretation is target-defined. The CPU simulator treats indices as linear element indices into `src.data()`. + - The CPU simulator does not enforce bounds checks on `indexes`. + +## Examples + +See related examples in `docs/isa/` and `docs/coding/tutorials/`. + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.mgather %mem, %idx : (!pto.partition_tensor_view, pto.tile<...>) +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.mgather %mem, %idx : (!pto.partition_tensor_view, pto.tile<...>) +``` + +### PTO Assembly Form + +```text +%dst = mgather %mem, %idx : !pto.memref<...>, !pto.tile<...> -> !pto.tile<...> +# AS Level 2 (DPS) +pto.mgather ins(%mem, %idx : !pto.partition_tensor_view, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/MGATHER_zh.md b/designs/outerCube/PTOISA/MGATHER_zh.md new file mode 100644 index 00000000..1b0ba2a3 --- /dev/null +++ b/designs/outerCube/PTOISA/MGATHER_zh.md @@ -0,0 +1,100 @@ +# MGATHER + +## 指令示意图 + +![MGATHER tile operation](../figures/isa/MGATHER.svg) + +## 简介 + +使用逐元素索引从全局内存收集加载元素到 Tile 中。 + +## 数学语义 + +对目标有效区域中的每个元素 `(i, j)`： + +$$ \mathrm{dst}_{i,j} = \mathrm{mem}[\mathrm{idx}_{i,j}] $$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS 规范](../assembly/PTO-AS_zh.md)。 + +同步形式： + +```text +%dst = mgather %mem, %idx : !pto.memref<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 1（SSA） + +```text +%dst = pto.mgather %mem, %idx : (!pto.partition_tensor_view, pto.tile<...>) +-> !pto.tile +``` + +### AS Level 2（DPS） + +```text +pto.mgather ins(%mem, %idx : !pto.partition_tensor_view, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`： + +```cpp +template +PTO_INST RecordEvent MGATHER(TileDst &dst, GlobalData &src, TileInd &indexes, WaitEvents &... events); +``` + +## 约束 + +- **支持的数据类型**： + - `dst`/`src` 的元素类型必须是以下之一：`uint8_t`、`int8_t`、`uint16_t`、`int16_t`、`uint32_t`、`int32_t`、`half`、`bfloat16_t`、`float`。 + - 在 AICore 目标上，还支持 `float8_e4m3_t` 和 `float8_e5m2_t`。 + - `indexes` 的元素类型必须是 `int32_t` 或 `uint32_t`。 +- **Tile 与内存类型约束**： + - `dst` 必须是向量 Tile（`TileType::Vec`）。 + - `indexes` 必须是向量 Tile（`TileType::Vec`）。 + - `dst` 和 `indexes` 必须使用行主序布局。 + - `src` 必须是位于 GM 内存中的 `GlobalTensor`。 + - `src` 必须使用 `ND` 布局。 +- **形状约束**： + - `dst.Rows == indexes.Rows`。 + - `indexes` 的形状必须为 `[N, 1]`（按行 gather）或 `[N, M]`（按元素 gather）。 + - `dst` 的行宽必须满足 32 字节对齐，即 `dst.Cols * sizeof(DType)` 必须是 32 的倍数。 + - `src` 的静态 shape 必须满足 `Shape<1, 1, 1, TableRows, RowWidth>`。 +- **索引解释**： + - 索引解释由目标定义。CPU 模拟器将索引视为 `src.data()` 中的线性元素索引。 + - CPU 模拟器不对 `indexes` 强制执行边界检查。 + +## 示例 + +参见 `docs/isa/` 和 `docs/coding/tutorials/` 中的相关示例。 + +## 汇编示例（ASM） + +### 自动模式 + +```text +# 自动模式：由编译器/运行时负责资源放置与调度。 +%dst = pto.mgather %mem, %idx : (!pto.partition_tensor_view, pto.tile<...>) +``` + +### 手动模式 + +```text +# 手动模式：先显式绑定资源，再发射指令。 +# 可选（当该指令包含 tile 操作数时）： +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.mgather %mem, %idx : (!pto.partition_tensor_view, pto.tile<...>) +``` + +### PTO 汇编形式 + +```text +%dst = mgather %mem, %idx : !pto.memref<...>, !pto.tile<...> -> !pto.tile<...> +# AS Level 2 (DPS) +pto.mgather ins(%mem, %idx : !pto.partition_tensor_view, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/MSCATTER.md b/designs/outerCube/PTOISA/MSCATTER.md new file mode 100644 index 00000000..f7b34223 --- /dev/null +++ b/designs/outerCube/PTOISA/MSCATTER.md @@ -0,0 +1,105 @@ +# MSCATTER + + +## Tile Operation Diagram + +![MSCATTER tile operation](../figures/isa/MSCATTER.svg) + +## Introduction + +Scatter-store elements from a tile into global memory using per-element indices. + +## Math Interpretation + +For each element `(i, j)` in the source valid region: + +$$ \mathrm{mem}[\mathrm{idx}_{i,j}] = \mathrm{src}_{i,j} $$ + +If multiple elements map to the same destination location, the final value is implementation-defined (CPU simulator: last writer wins in row-major iteration order). + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +mscatter %src, %mem, %idx : !pto.memref<...>, !pto.tile<...>, !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +pto.mscatter %src, %idx, %mem : (!pto.tile<...>, !pto.tile<...>, !pto.partition_tensor_view) -> () +``` + +### AS Level 2 (DPS) + +```text +pto.mscatter ins(%src, %idx : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%mem : !pto.partition_tensor_view) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent MSCATTER(GlobalData &dst, TileSrc &src, TileInd &indexes, WaitEvents &... events); +``` + +## Constraints + +- **Supported data types**: + - `src`/`dst` element type must be one of: `int8_t`, `uint8_t`, `int16_t`, `uint16_t`, `int32_t`, `uint32_t`, `half`, `bfloat16_t`, `float`. + - On AICore targets, `float8_e4m3_t` and `float8_e5m2_t` are also supported. + - `indexes` element type must be `int32_t` or `uint32_t`. +- **Tile and memory types**: + - `src` must be a vector tile (`TileType::Vec`). + - `indexes` must be a vector tile (`TileType::Vec`). + - `src` and `indexes` must use row-major layout. + - `dst` must be a `GlobalTensor` in GM memory. + - `dst` must use `ND` layout. +- **Atomic operation constraints**: + - Non-atomic scatter is supported for all supported element types. + - `Add` atomic mode requires `int32_t`, `uint32_t`, `float`, or `half`. + - `Max`/`Min` atomic mode requires `int32_t` or `float`. +- **Shape constraints**: + - `src.Rows == indexes.Rows`. + - `indexes` must be shaped as `[N, 1]` for row-indexed scatter or `[N, M]` for element-indexed scatter. + - `src` row width must be 32-byte aligned, that is, `src.Cols * sizeof(DType)` must be a multiple of 32. + - `dst` static shape must satisfy `Shape<1, 1, 1, TableRows, RowWidth>`. +- **Index interpretation**: + - Index interpretation is target-defined. The CPU simulator treats indices as linear element indices into `dst.data()`. + - The CPU simulator does not enforce bounds checks on `indexes`. + +## Examples + +See related examples in `docs/isa/` and `docs/coding/tutorials/`. + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +pto.mscatter %src, %idx, %mem : (!pto.tile<...>, !pto.tile<...>, !pto.partition_tensor_view) -> () +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +pto.mscatter %src, %idx, %mem : (!pto.tile<...>, !pto.tile<...>, !pto.partition_tensor_view) -> () +``` + +### PTO Assembly Form + +```text +mscatter %src, %mem, %idx : !pto.memref<...>, !pto.tile<...>, !pto.tile<...> +# AS Level 2 (DPS) +pto.mscatter ins(%src, %idx : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%mem : !pto.partition_tensor_view) +``` + diff --git a/designs/outerCube/PTOISA/MSCATTER_zh.md b/designs/outerCube/PTOISA/MSCATTER_zh.md new file mode 100644 index 00000000..c0d9efdf --- /dev/null +++ b/designs/outerCube/PTOISA/MSCATTER_zh.md @@ -0,0 +1,105 @@ +# MSCATTER + +## 指令示意图 + +![MSCATTER tile operation](../figures/isa/MSCATTER.svg) + +## 简介 + +使用逐元素索引将 Tile 中的元素散播存储到全局内存。 + +## 数学语义 + +对源有效区域中的每个元素 `(i, j)`： + +$$ \mathrm{mem}[\mathrm{idx}_{i,j}] = \mathrm{src}_{i,j} $$ + +如果多个元素映射到同一目标位置，最终值由实现定义（CPU 模拟器：按行主序迭代顺序，最后写入者获胜）。 + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS 规范](../assembly/PTO-AS_zh.md)。 + +同步形式： + +```text +mscatter %src, %mem, %idx : !pto.memref<...>, !pto.tile<...>, !pto.tile<...> +``` + +### AS Level 1（SSA） + +```text +pto.mscatter %src, %idx, %mem : (!pto.tile<...>, !pto.tile<...>, !pto.partition_tensor_view) -> () +``` + +### AS Level 2（DPS） + +```text +pto.mscatter ins(%src, %idx : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%mem : !pto.partition_tensor_view) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`： + +```cpp +template +PTO_INST RecordEvent MSCATTER(GlobalData &dst, TileSrc &src, TileInd &indexes, WaitEvents &... events); +``` + +## 约束 + +- **支持的数据类型**： + - `src`/`dst` 的元素类型必须是以下之一：`int8_t`、`uint8_t`、`int16_t`、`uint16_t`、`int32_t`、`uint32_t`、`half`、`bfloat16_t`、`float`。 + - 在 AICore 目标上，还支持 `float8_e4m3_t` 和 `float8_e5m2_t`。 + - `indexes` 的元素类型必须是 `int32_t` 或 `uint32_t`。 +- **Tile 与内存类型约束**： + - `src` 必须是向量 Tile（`TileType::Vec`）。 + - `indexes` 必须是向量 Tile（`TileType::Vec`）。 + - `src` 和 `indexes` 必须使用行主序布局。 + - `dst` 必须是位于 GM 内存中的 `GlobalTensor`。 + - `dst` 必须使用 `ND` 布局。 +- **原子操作约束**： + - 非原子 scatter 对所有受支持元素类型都可用。 + - `Add` 原子模式要求元素类型为 `int32_t`、`uint32_t`、`float` 或 `half`。 + - `Max`/`Min` 原子模式要求元素类型为 `int32_t` 或 `float`。 +- **形状约束**： + - `src.Rows == indexes.Rows`。 + - `indexes` 的形状必须为 `[N, 1]`（按行 scatter）或 `[N, M]`（按元素 scatter）。 + - `src` 的行宽必须满足 32 字节对齐，即 `src.Cols * sizeof(DType)` 必须是 32 的倍数。 + - `dst` 的静态 shape 必须满足 `Shape<1, 1, 1, TableRows, RowWidth>`。 +- **索引解释**： + - 索引解释由目标定义。CPU 模拟器将索引视为 `dst.data()` 中的线性元素索引。 + - CPU 模拟器不对 `indexes` 强制执行边界检查。 + +## 示例 + +参见 `docs/isa/` 和 `docs/coding/tutorials/` 中的相关示例。 + +## 汇编示例（ASM） + +### 自动模式 + +```text +# 自动模式：由编译器/运行时负责资源放置与调度。 +pto.mscatter %src, %idx, %mem : (!pto.tile<...>, !pto.tile<...>, !pto.partition_tensor_view) -> () +``` + +### 手动模式 + +```text +# 手动模式：先显式绑定资源，再发射指令。 +# 可选（当该指令包含 tile 操作数时）： +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +pto.mscatter %src, %idx, %mem : (!pto.tile<...>, !pto.tile<...>, !pto.partition_tensor_view) -> () +``` + +### PTO 汇编形式 + +```text +mscatter %src, %mem, %idx : !pto.memref<...>, !pto.tile<...>, !pto.tile<...> +# AS Level 2 (DPS) +pto.mscatter ins(%src, %idx : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%mem : !pto.partition_tensor_view) +``` + diff --git a/designs/outerCube/PTOISA/PTOISA.md b/designs/outerCube/PTOISA/PTOISA.md new file mode 100644 index 00000000..75fd1802 --- /dev/null +++ b/designs/outerCube/PTOISA/PTOISA.md @@ -0,0 +1,152 @@ +# PTO ISA Overview + +This page is the source-synchronized ISA index generated from `docs/isa/manifest.yaml`. + +## Docs Contents + +| Area | Page | Description | +|---|---|---| +| Overview | [`docs/README.md`](README.md) | PTO ISA guide entry point and navigation. | +| Overview | [`docs/PTOISA.md`](PTOISA.md) | This page (overview + full instruction index). | +| ISA reference | [`docs/isa/README.md`](isa/README.md) | Per-instruction reference directory index. | +| ISA reference | [`docs/isa/conventions.md`](isa/conventions.md) | Shared notation, operands, events, and modifiers. | +| Assembly (PTO-AS) | [`docs/assembly/PTO-AS.md`](assembly/PTO-AS.md) | PTO-AS syntax reference. | +| Source of truth | [`include/pto/common/pto_instr.hpp`](reference/pto-intrinsics-header.md) | C++ intrinsic API (authoritative). | +| PTO Auto Mode | [`docs/auto_mode/README.md`](README.md) | PTO auto mode guide entry point. | + +## Instruction Index (All PTO Instructions) + +| Category | Instruction | Description | +|---|---|---| +| Synchronization | [`TSYNC`](isa/TSYNC.md) | Synchronize PTO execution (wait on events or insert a per-op pipeline barrier). | +| Manual / Resource Binding | [`TASSIGN`](isa/TASSIGN.md) | Bind a Tile object to an implementation-defined on-chip address (manual placement). | +| Manual / Resource Binding | [`TSETFMATRIX`](isa/TSETFMATRIX.md) | Set FMATRIX register(s) for IMG2COL-like ops. | +| Manual / Resource Binding | [`TSET_IMG2COL_RPT`](isa/TSET_IMG2COL_RPT.md) | Set IMG2COL repeat metadata from an IMG2COL configuration tile. | +| Manual / Resource Binding | [`TSET_IMG2COL_PADDING`](isa/TSET_IMG2COL_PADDING.md) | Set IMG2COL padding metadata from an IMG2COL configuration tile. | +| Elementwise (Tile-Tile) | [`TADD`](isa/TADD.md) | Elementwise add of two tiles. | +| Elementwise (Tile-Tile) | [`TABS`](isa/TABS.md) | Elementwise absolute value of a tile. | +| Elementwise (Tile-Tile) | [`TAND`](isa/TAND.md) | Elementwise bitwise AND of two tiles. | +| Elementwise (Tile-Tile) | [`TOR`](isa/TOR.md) | Elementwise bitwise OR of two tiles. | +| Elementwise (Tile-Tile) | [`TSUB`](isa/TSUB.md) | Elementwise subtract of two tiles. | +| Elementwise (Tile-Tile) | [`TMUL`](isa/TMUL.md) | Elementwise multiply of two tiles. | +| Elementwise (Tile-Tile) | [`TMIN`](isa/TMIN.md) | Elementwise minimum of two tiles. | +| Elementwise (Tile-Tile) | [`TMAX`](isa/TMAX.md) | Elementwise maximum of two tiles. | +| Elementwise (Tile-Tile) | [`TCMP`](isa/TCMP.md) | Compare two tiles and write a packed predicate mask. | +| Elementwise (Tile-Tile) | [`TDIV`](isa/TDIV.md) | Elementwise division of two tiles. | +| Elementwise (Tile-Tile) | [`TSHL`](isa/TSHL.md) | Elementwise shift-left of two tiles. | +| Elementwise (Tile-Tile) | [`TSHR`](isa/TSHR.md) | Elementwise shift-right of two tiles. | +| Elementwise (Tile-Tile) | [`TXOR`](isa/TXOR.md) | Elementwise bitwise XOR of two tiles. | +| Elementwise (Tile-Tile) | [`TLOG`](isa/TLOG.md) | Elementwise natural logarithm of a tile. | +| Elementwise (Tile-Tile) | [`TRECIP`](isa/TRECIP.md) | Elementwise reciprocal of a tile. | +| Elementwise (Tile-Tile) | [`TPRELU`](isa/TPRELU.md) | Elementwise PReLU (parametric ReLU) with a per-element slope tile. | +| Elementwise (Tile-Tile) | [`TADDC`](isa/TADDC.md) | Elementwise ternary add: `src0 + src1 + src2`. | +| Elementwise (Tile-Tile) | [`TSUBC`](isa/TSUBC.md) | Elementwise ternary op: `src0 - src1 + src2`. | +| Elementwise (Tile-Tile) | [`TCVT`](isa/TCVT.md) | Elementwise type conversion with a specified rounding mode. | +| Elementwise (Tile-Tile) | [`TSEL`](isa/TSEL.md) | Select between two tiles using a mask tile (per-element selection). | +| Elementwise (Tile-Tile) | [`TRSQRT`](isa/TRSQRT.md) | Elementwise reciprocal square root. | +| Elementwise (Tile-Tile) | [`TSQRT`](isa/TSQRT.md) | Elementwise square root. | +| Elementwise (Tile-Tile) | [`TEXP`](isa/TEXP.md) | Elementwise exponential. | +| Elementwise (Tile-Tile) | [`TNOT`](isa/TNOT.md) | Elementwise bitwise NOT of a tile. | +| Elementwise (Tile-Tile) | [`TRELU`](isa/TRELU.md) | Elementwise ReLU of a tile. | +| Elementwise (Tile-Tile) | [`TNEG`](isa/TNEG.md) | Elementwise negation of a tile. | +| Elementwise (Tile-Tile) | [`TREM`](isa/TREM.md) | Elementwise remainder of two tiles. | +| Elementwise (Tile-Tile) | [`TFMOD`](isa/TFMOD.md) | Elementwise fmod of two tiles. | +| Tile-Scalar / Tile-Immediate | [`TEXPANDS`](isa/TEXPANDS.md) | Broadcast a scalar into a destination tile. | +| Tile-Scalar / Tile-Immediate | [`TCMPS`](isa/TCMPS.md) | Compare a tile against a scalar and write per-element comparison results. | +| Tile-Scalar / Tile-Immediate | [`TSELS`](isa/TSELS.md) | Select between source tile and scalar using a mask tile (per-element selection for source tile). | +| Tile-Scalar / Tile-Immediate | [`TMINS`](isa/TMINS.md) | Elementwise minimum of a tile and a scalar. | +| Tile-Scalar / Tile-Immediate | [`TADDS`](isa/TADDS.md) | Elementwise add a scalar to a tile. | +| Tile-Scalar / Tile-Immediate | [`TSUBS`](isa/TSUBS.md) | Elementwise subtract a scalar from a tile. | +| Tile-Scalar / Tile-Immediate | [`TDIVS`](isa/TDIVS.md) | Elementwise division with a scalar (tile/scalar or scalar/tile). | +| Tile-Scalar / Tile-Immediate | [`TMULS`](isa/TMULS.md) | Elementwise multiply a tile by a scalar. | +| Tile-Scalar / Tile-Immediate | [`TFMODS`](isa/TFMODS.md) | Elementwise remainder with a scalar: `fmod(src, scalar)`. | +| Tile-Scalar / Tile-Immediate | [`TREMS`](isa/TREMS.md) | Elementwise remainder with a scalar: `remainder(src, scalar)`. | +| Tile-Scalar / Tile-Immediate | [`TMAXS`](isa/TMAXS.md) | Elementwise max of a tile and a scalar: `max(src, scalar)`. | +| Tile-Scalar / Tile-Immediate | [`TANDS`](isa/TANDS.md) | Elementwise bitwise AND of a tile and a scalar. | +| Tile-Scalar / Tile-Immediate | [`TORS`](isa/TORS.md) | Elementwise bitwise OR of a tile and a scalar. | +| Tile-Scalar / Tile-Immediate | [`TSHLS`](isa/TSHLS.md) | Elementwise shift-left a tile by a scalar. | +| Tile-Scalar / Tile-Immediate | [`TSHRS`](isa/TSHRS.md) | Elementwise shift-right a tile by a scalar. | +| Tile-Scalar / Tile-Immediate | [`TXORS`](isa/TXORS.md) | Elementwise bitwise XOR of a tile and a scalar. | +| Tile-Scalar / Tile-Immediate | [`TLRELU`](isa/TLRELU.md) | Leaky ReLU with a scalar slope. | +| Tile-Scalar / Tile-Immediate | [`TADDSC`](isa/TADDSC.md) | Elementwise fused add with scalar and a second tile: `src0 + scalar + src1`. | +| Tile-Scalar / Tile-Immediate | [`TSUBSC`](isa/TSUBSC.md) | Elementwise fused op: `src0 - scalar + src1`. | +| Axis Reduce / Expand | [`TROWSUM`](isa/TROWSUM.md) | Reduce each row by summing across columns. | +| Axis Reduce / Expand | [`TROWPROD`](isa/TROWPROD.md) | Reduce each row by multiplying across columns. | +| Axis Reduce / Expand | [`TCOLSUM`](isa/TCOLSUM.md) | Reduce each column by summing across rows. | +| Axis Reduce / Expand | [`TCOLPROD`](isa/TCOLPROD.md) | Reduce each column by multiplying across rows. | +| Axis Reduce / Expand | [`TCOLMAX`](isa/TCOLMAX.md) | Reduce each column by taking the maximum across rows. | +| Axis Reduce / Expand | [`TROWMAX`](isa/TROWMAX.md) | Reduce each row by taking the maximum across columns. | +| Axis Reduce / Expand | [`TROWMIN`](isa/TROWMIN.md) | Reduce each row by taking the minimum across columns. | +| Axis Reduce / Expand | [`TROWARGMAX`](isa/TROWARGMAX.md) | Get the column index of the maximum element for each row. | +| Axis Reduce / Expand | [`TROWARGMIN`](isa/TROWARGMIN.md) | Get the column index of the minimum element for each row. | +| Axis Reduce / Expand | [`TCOLARGMAX`](isa/TCOLARGMAX.md) | Get the row index of the maximum element for each column. | +| Axis Reduce / Expand | [`TCOLARGMIN`](isa/TCOLARGMIN.md) | Get the row index of the minimum element for each column. | +| Axis Reduce / Expand | [`TROWEXPAND`](isa/TROWEXPAND.md) | Broadcast the first element of each source row across the destination row. | +| Axis Reduce / Expand | [`TROWEXPANDDIV`](isa/TROWEXPANDDIV.md) | Row-wise broadcast divide: divide each row of `src0` by a per-row scalar vector `src1`. | +| Axis Reduce / Expand | [`TROWEXPANDMUL`](isa/TROWEXPANDMUL.md) | Row-wise broadcast multiply: multiply each row of `src0` by a per-row scalar vector `src1`. | +| Axis Reduce / Expand | [`TROWEXPANDSUB`](isa/TROWEXPANDSUB.md) | Row-wise broadcast subtract: subtract a per-row scalar vector `src1` from each row of `src0`. | +| Axis Reduce / Expand | [`TROWEXPANDADD`](isa/TROWEXPANDADD.md) | Row-wise broadcast add: add a per-row scalar vector. | +| Axis Reduce / Expand | [`TROWEXPANDMAX`](isa/TROWEXPANDMAX.md) | Row-wise broadcast max with a per-row scalar vector. | +| Axis Reduce / Expand | [`TROWEXPANDMIN`](isa/TROWEXPANDMIN.md) | Row-wise broadcast min with a per-row scalar vector. | +| Axis Reduce / Expand | [`TROWEXPANDEXPDIF`](isa/TROWEXPANDEXPDIF.md) | Row-wise exp-diff: compute exp(src0 - src1) with per-row scalars. | +| Axis Reduce / Expand | [`TCOLMIN`](isa/TCOLMIN.md) | Reduce each column by taking the minimum across rows. | +| Axis Reduce / Expand | [`TCOLEXPAND`](isa/TCOLEXPAND.md) | Broadcast the first element of each source column across the destination column. | +| Axis Reduce / Expand | [`TCOLEXPANDDIV`](isa/TCOLEXPANDDIV.md) | Column-wise broadcast divide: divide each column by a per-column scalar vector. | +| Axis Reduce / Expand | [`TCOLEXPANDMUL`](isa/TCOLEXPANDMUL.md) | Column-wise broadcast multiply: multiply each column by a per-column scalar vector. | +| Axis Reduce / Expand | [`TCOLEXPANDADD`](isa/TCOLEXPANDADD.md) | Column-wise broadcast add with per-column scalar vector. | +| Axis Reduce / Expand | [`TCOLEXPANDMAX`](isa/TCOLEXPANDMAX.md) | Column-wise broadcast max with per-column scalar vector. | +| Axis Reduce / Expand | [`TCOLEXPANDMIN`](isa/TCOLEXPANDMIN.md) | Column-wise broadcast min with per-column scalar vector. | +| Axis Reduce / Expand | [`TCOLEXPANDSUB`](isa/TCOLEXPANDSUB.md) | Column-wise broadcast subtract: subtract a per-column scalar vector from each column. | +| Axis Reduce / Expand | [`TCOLEXPANDEXPDIF`](isa/TCOLEXPANDEXPDIF.md) | Column-wise exp-diff: compute exp(src0 - src1) with per-column scalars. | +| Memory (GM <-> Tile) | [`TLOAD`](isa/TLOAD.md) | Load data from a GlobalTensor (GM) into a Tile. | +| Memory (GM <-> Tile) | [`TPREFETCH`](isa/TPREFETCH.md) | Prefetch data from global memory into a tile-local cache/buffer (hint). | +| Memory (GM <-> Tile) | [`TSTORE`](isa/TSTORE.md) | Store data from a Tile into a GlobalTensor (GM), optionally using atomic write or quantization parameters. | +| Memory (GM <-> Tile) | [`TSTORE_FP`](isa/TSTORE_FP.md) | Store an accumulator tile into global memory using a scaling (`fp`) tile for vector quantization parameters. | +| Memory (GM <-> Tile) | [`MGATHER`](isa/MGATHER.md) | Gather-load elements from global memory into a tile using per-element indices. | +| Memory (GM <-> Tile) | [`MSCATTER`](isa/MSCATTER.md) | Scatter-store elements from a tile into global memory using per-element indices. | +| Matrix Multiply | [`TGEMV_MX`](isa/TGEMV_MX.md) | GEMV with additional scaling tiles for mixed-precision / quantized matrix-vector compute. | +| Matrix Multiply | [`TMATMUL_MX`](isa/TMATMUL_MX.md) | Matrix multiply (GEMM) with additional scaling tiles for mixed-precision / quantized matmul on supported targets. | +| Matrix Multiply | [`TMATMUL`](isa/TMATMUL.md) | Matrix multiply (GEMM) producing an accumulator/output tile. | +| Matrix Multiply | [`TMATMUL_ACC`](isa/TMATMUL_ACC.md) | Matrix multiply with accumulator input (fused accumulate). | +| Matrix Multiply | [`TMATMUL_BIAS`](isa/TMATMUL_BIAS.md) | Matrix multiply with bias add. | +| Matrix Multiply | [`TGEMV`](isa/TGEMV.md) | General Matrix-Vector multiplication producing an accumulator/output tile. | +| Matrix Multiply | [`TGEMV_ACC`](isa/TGEMV_ACC.md) | GEMV with explicit accumulator input/output tiles. | +| Matrix Multiply | [`TGEMV_BIAS`](isa/TGEMV_BIAS.md) | GEMV with bias add. | +| Data Movement / Layout | [`TEXTRACT`](isa/TEXTRACT.md) | Extract a sub-tile from a source tile. | +| Data Movement / Layout | [`TEXTRACT_FP`](isa/TEXTRACT_FP.md) | Extract with fp/scaling tile (vector-quantization parameters). | +| Data Movement / Layout | [`TIMG2COL`](isa/TIMG2COL.md) | Image-to-column transform for convolution-like workloads. | +| Data Movement / Layout | [`TINSERT`](isa/TINSERT.md) | Insert a sub-tile into a destination tile at an (indexRow, indexCol) offset. | +| Data Movement / Layout | [`TINSERT_FP`](isa/TINSERT_FP.md) | Insert with fp/scaling tile (vector-quantization parameters). | +| Data Movement / Layout | [`TFILLPAD`](isa/TFILLPAD.md) | Copy+pad a tile outside the valid region with a compile-time pad value. | +| Data Movement / Layout | [`TFILLPAD_INPLACE`](isa/TFILLPAD_INPLACE.md) | In-place fill/pad variant. | +| Data Movement / Layout | [`TFILLPAD_EXPAND`](isa/TFILLPAD_EXPAND.md) | Fill/pad while allowing dst to be larger than src. | +| Data Movement / Layout | [`TMOV`](isa/TMOV.md) | Move/copy between tiles, optionally applying implementation-defined conversion modes. | +| Data Movement / Layout | [`TMOV_FP`](isa/TMOV_FP.md) | Move/convert from an accumulator tile into a destination tile, using a scaling (`fp`) tile for vector quantization parameters. | +| Data Movement / Layout | [`TRESHAPE`](isa/TRESHAPE.md) | Reinterpret a tile as another tile type/shape while preserving the underlying bytes. | +| Data Movement / Layout | [`TTRANS`](isa/TTRANS.md) | Transpose with an implementation-defined temporary tile. | +| Data Movement / Layout | [`TSUBVIEW`](isa/TSUBVIEW.md) | Reinterpret a tile as a subtile of another tile. | +| Data Movement / Layout | [`TGET_SCALE_ADDR`](isa/TGET_SCALE_ADDR.md) | Bind the on-chip address of output tile to a scaled factor of that of input tile. | +| Complex | [`TPRINT`](isa/TPRINT.md) | Debug/print elements from a tile (implementation-defined). | +| Complex | [`TMRGSORT`](isa/TMRGSORT.md) | Merge sort for multiple sorted lists (implementation-defined element format and layout). | +| Complex | [`TSORT32`](isa/TSORT32.md) | Sort 32-element blocks of `src` with accompanying `idx` entries and output sorted value-index pairs. | +| Complex | [`TGATHER`](isa/TGATHER.md) | Gather/select elements using either an index tile or a compile-time mask pattern. | +| Complex | [`TCI`](isa/TCI.md) | Generate a contiguous integer sequence into a destination tile. | +| Complex | [`TTRI`](isa/TTRI.md) | Generate a triangular (lower/upper) mask tile. | +| Complex | [`TPARTADD`](isa/TPARTADD.md) | Partial elementwise add with implementation-defined handling of mismatched valid regions. | +| Complex | [`TPARTMUL`](isa/TPARTMUL.md) | Partial elementwise multiply with implementation-defined handling of mismatched valid regions. | +| Complex | [`TPARTMAX`](isa/TPARTMAX.md) | Partial elementwise max with implementation-defined handling of mismatched valid regions. | +| Complex | [`TPARTMIN`](isa/TPARTMIN.md) | Partial elementwise min with implementation-defined handling of mismatched valid regions. | +| Complex | [`TGATHERB`](isa/TGATHERB.md) | Gather elements using byte offsets. | +| Complex | [`TSCATTER`](isa/TSCATTER.md) | Scatter rows of a source tile into a destination tile using per-element row indices. | +| Complex | [`TQUANT`](isa/TQUANT.md) | Quantize a tile (e.g. FP32 to FP8) producing exponent/scaling/max outputs. | +| Communication | [`TPUT`](isa/comm/TPUT.md) | Remote write: transfer local data to remote NPU memory (GM → UB → GM). | +| Communication | [`TGET`](isa/comm/TGET.md) | Remote read: read remote NPU data to local memory (GM → UB → GM). | +| Communication | [`TPUT_ASYNC`](isa/comm/TPUT_ASYNC.md) | Asynchronous remote write (local GM → DMA engine → remote GM). | +| Communication | [`TGET_ASYNC`](isa/comm/TGET_ASYNC.md) | Asynchronous remote read (remote GM → DMA engine → local GM). | +| Communication | [`TNOTIFY`](isa/comm/TNOTIFY.md) | Send flag notification to remote NPU. | +| Communication | [`TWAIT`](isa/comm/TWAIT.md) | Blocking wait until signal(s) meet comparison condition. | +| Communication | [`TTEST`](isa/comm/TTEST.md) | Non-blocking test if signal(s) meet comparison condition. | +| Communication | [`TGATHER`](isa/comm/TGATHER.md) | Gather data from all ranks and concatenate along DIM_3. | +| Communication | [`TSCATTER`](isa/comm/TSCATTER.md) | Scatter data to all ranks by splitting along DIM_3. | +| Communication | [`TREDUCE`](isa/comm/TREDUCE.md) | Gather and reduce data from all ranks element-wise to local. | +| Communication | [`TBROADCAST`](isa/comm/TBROADCAST.md) | Broadcast data from current NPU to all ranks. | diff --git a/designs/outerCube/PTOISA/README.md b/designs/outerCube/PTOISA/README.md new file mode 100644 index 00000000..a637245d --- /dev/null +++ b/designs/outerCube/PTOISA/README.md @@ -0,0 +1,153 @@ +

+ PTO Tile Lib +

+ +# PTO ISA Reference + +This directory contains the per-instruction reference for the PTO Tile Lib ISA. + +- Source of truth (C++ intrinsics): `include/pto/common/pto_instr.hpp` +- [Common conventions (operands, events, modifiers)](conventions.md) + +## Synchronization +- [TSYNC](TSYNC.md) - Synchronize PTO execution (wait on events or insert a per-op pipeline barrier). + +## Manual / Resource Binding +- [TASSIGN](TASSIGN.md) - Bind a Tile object to an implementation-defined on-chip address (manual placement). +- [TSETFMATRIX](TSETFMATRIX.md) - Set FMATRIX register(s) for IMG2COL-like ops. +- [TSET_IMG2COL_RPT](TSET_IMG2COL_RPT.md) - Set IMG2COL repeat metadata from an IMG2COL configuration tile. +- [TSET_IMG2COL_PADDING](TSET_IMG2COL_PADDING.md) - Set IMG2COL padding metadata from an IMG2COL configuration tile. + +## Elementwise (Tile-Tile) +- [TADD](TADD.md) - Elementwise add of two tiles. +- [TABS](TABS.md) - Elementwise absolute value of a tile. +- [TAND](TAND.md) - Elementwise bitwise AND of two tiles. +- [TOR](TOR.md) - Elementwise bitwise OR of two tiles. +- [TSUB](TSUB.md) - Elementwise subtract of two tiles. +- [TMUL](TMUL.md) - Elementwise multiply of two tiles. +- [TMIN](TMIN.md) - Elementwise minimum of two tiles. +- [TMAX](TMAX.md) - Elementwise maximum of two tiles. +- [TCMP](TCMP.md) - Compare two tiles and write a packed predicate mask. +- [TDIV](TDIV.md) - Elementwise division of two tiles. +- [TSHL](TSHL.md) - Elementwise shift-left of two tiles. +- [TSHR](TSHR.md) - Elementwise shift-right of two tiles. +- [TXOR](TXOR.md) - Elementwise bitwise XOR of two tiles. +- [TLOG](TLOG.md) - Elementwise natural logarithm of a tile. +- [TRECIP](TRECIP.md) - Elementwise reciprocal of a tile. +- [TPRELU](TPRELU.md) - Elementwise PReLU (parametric ReLU) with a per-element slope tile. +- [TADDC](TADDC.md) - Elementwise ternary add: `src0 + src1 + src2`. +- [TSUBC](TSUBC.md) - Elementwise ternary op: `src0 - src1 + src2`. +- [TCVT](TCVT.md) - Elementwise type conversion with a specified rounding mode. +- [TSEL](TSEL.md) - Select between two tiles using a mask tile (per-element selection). +- [TRSQRT](TRSQRT.md) - Elementwise reciprocal square root. +- [TSQRT](TSQRT.md) - Elementwise square root. +- [TEXP](TEXP.md) - Elementwise exponential. +- [TNOT](TNOT.md) - Elementwise bitwise NOT of a tile. +- [TRELU](TRELU.md) - Elementwise ReLU of a tile. +- [TNEG](TNEG.md) - Elementwise negation of a tile. +- [TREM](TREM.md) - Elementwise remainder of two tiles. +- [TFMOD](TFMOD.md) - Elementwise fmod of two tiles. + +## Tile-Scalar / Tile-Immediate +- [TEXPANDS](TEXPANDS.md) - Broadcast a scalar into a destination tile. +- [TCMPS](TCMPS.md) - Compare a tile against a scalar and write per-element comparison results. +- [TSELS](TSELS.md) - Select between source tile and scalar using a mask tile (per-element selection for source tile). +- [TMINS](TMINS.md) - Elementwise minimum of a tile and a scalar. +- [TADDS](TADDS.md) - Elementwise add a scalar to a tile. +- [TSUBS](TSUBS.md) - Elementwise subtract a scalar from a tile. +- [TDIVS](TDIVS.md) - Elementwise division with a scalar (tile/scalar or scalar/tile). +- [TMULS](TMULS.md) - Elementwise multiply a tile by a scalar. +- [TFMODS](TFMODS.md) - Elementwise remainder with a scalar: `fmod(src, scalar)`. +- [TREMS](TREMS.md) - Elementwise remainder with a scalar: `remainder(src, scalar)`. +- [TMAXS](TMAXS.md) - Elementwise max of a tile and a scalar: `max(src, scalar)`. +- [TANDS](TANDS.md) - Elementwise bitwise AND of a tile and a scalar. +- [TORS](TORS.md) - Elementwise bitwise OR of a tile and a scalar. +- [TSHLS](TSHLS.md) - Elementwise shift-left a tile by a scalar. +- [TSHRS](TSHRS.md) - Elementwise shift-right a tile by a scalar. +- [TXORS](TXORS.md) - Elementwise bitwise XOR of a tile and a scalar. +- [TLRELU](TLRELU.md) - Leaky ReLU with a scalar slope. +- [TADDSC](TADDSC.md) - Elementwise fused add with scalar and a second tile: `src0 + scalar + src1`. +- [TSUBSC](TSUBSC.md) - Elementwise fused op: `src0 - scalar + src1`. + +## Axis Reduce / Expand +- [TROWSUM](TROWSUM.md) - Reduce each row by summing across columns. +- [TROWPROD](TROWPROD.md) - Reduce each row by multiplying across columns. +- [TCOLSUM](TCOLSUM.md) - Reduce each column by summing across rows. +- [TCOLPROD](TCOLPROD.md) - Reduce each column by multiplying across rows. +- [TCOLMAX](TCOLMAX.md) - Reduce each column by taking the maximum across rows. +- [TROWMAX](TROWMAX.md) - Reduce each row by taking the maximum across columns. +- [TROWMIN](TROWMIN.md) - Reduce each row by taking the minimum across columns. +- [TROWARGMAX](TROWARGMAX.md) - Get the column index of the maximum element for each row. +- [TROWARGMIN](TROWARGMIN.md) - Get the column index of the minimum element for each row. +- [TCOLARGMAX](TCOLARGMAX.md) - Get the row index of the maximum element for each column. +- [TCOLARGMIN](TCOLARGMIN.md) - Get the row index of the minimum element for each column. +- [TROWEXPAND](TROWEXPAND.md) - Broadcast the first element of each source row across the destination row. +- [TROWEXPANDDIV](TROWEXPANDDIV.md) - Row-wise broadcast divide: divide each row of `src0` by a per-row scalar vector `src1`. +- [TROWEXPANDMUL](TROWEXPANDMUL.md) - Row-wise broadcast multiply: multiply each row of `src0` by a per-row scalar vector `src1`. +- [TROWEXPANDSUB](TROWEXPANDSUB.md) - Row-wise broadcast subtract: subtract a per-row scalar vector `src1` from each row of `src0`. +- [TROWEXPANDADD](TROWEXPANDADD.md) - Row-wise broadcast add: add a per-row scalar vector. +- [TROWEXPANDMAX](TROWEXPANDMAX.md) - Row-wise broadcast max with a per-row scalar vector. +- [TROWEXPANDMIN](TROWEXPANDMIN.md) - Row-wise broadcast min with a per-row scalar vector. +- [TROWEXPANDEXPDIF](TROWEXPANDEXPDIF.md) - Row-wise exp-diff: compute exp(src0 - src1) with per-row scalars. +- [TCOLMIN](TCOLMIN.md) - Reduce each column by taking the minimum across rows. +- [TCOLEXPAND](TCOLEXPAND.md) - Broadcast the first element of each source column across the destination column. +- [TCOLEXPANDDIV](TCOLEXPANDDIV.md) - Column-wise broadcast divide: divide each column by a per-column scalar vector. +- [TCOLEXPANDMUL](TCOLEXPANDMUL.md) - Column-wise broadcast multiply: multiply each column by a per-column scalar vector. +- [TCOLEXPANDADD](TCOLEXPANDADD.md) - Column-wise broadcast add with per-column scalar vector. +- [TCOLEXPANDMAX](TCOLEXPANDMAX.md) - Column-wise broadcast max with per-column scalar vector. +- [TCOLEXPANDMIN](TCOLEXPANDMIN.md) - Column-wise broadcast min with per-column scalar vector. +- [TCOLEXPANDSUB](TCOLEXPANDSUB.md) - Column-wise broadcast subtract: subtract a per-column scalar vector from each column. +- [TCOLEXPANDEXPDIF](TCOLEXPANDEXPDIF.md) - Column-wise exp-diff: compute exp(src0 - src1) with per-column scalars. + +## Memory (GM <-> Tile) +- [TLOAD](TLOAD.md) - Load data from a GlobalTensor (GM) into a Tile. +- [TPREFETCH](TPREFETCH.md) - Prefetch data from global memory into a tile-local cache/buffer (hint). +- [TSTORE](TSTORE.md) - Store data from a Tile into a GlobalTensor (GM), optionally using atomic write or quantization parameters. +- [TSTORE_FP](TSTORE_FP.md) - Store an accumulator tile into global memory using a scaling (`fp`) tile for vector quantization parameters. +- [MGATHER](MGATHER.md) - Gather-load elements from global memory into a tile using per-element indices. +- [MSCATTER](MSCATTER.md) - Scatter-store elements from a tile into global memory using per-element indices. + +## Matrix Multiply +- [TGEMV_MX](TGEMV_MX.md) - GEMV with additional scaling tiles for mixed-precision / quantized matrix-vector compute. +- [TMATMUL_MX](TMATMUL_MX.md) - Matrix multiply (GEMM) with additional scaling tiles for mixed-precision / quantized matmul on supported targets. +- [TMATMUL](TMATMUL.md) - Matrix multiply (GEMM) producing an accumulator/output tile. +- [TMATMUL_ACC](TMATMUL_ACC.md) - Matrix multiply with accumulator input (fused accumulate). +- [TMATMUL_BIAS](TMATMUL_BIAS.md) - Matrix multiply with bias add. +- [TGEMV](TGEMV.md) - General Matrix-Vector multiplication producing an accumulator/output tile. +- [TGEMV_ACC](TGEMV_ACC.md) - GEMV with explicit accumulator input/output tiles. +- [TGEMV_BIAS](TGEMV_BIAS.md) - GEMV with bias add. + +## Data Movement / Layout +- [TEXTRACT](TEXTRACT.md) - Extract a sub-tile from a source tile. +- [TEXTRACT_FP](TEXTRACT_FP.md) - Extract with fp/scaling tile (vector-quantization parameters). +- [TIMG2COL](TIMG2COL.md) - Image-to-column transform for convolution-like workloads. +- [TINSERT](TINSERT.md) - Insert a sub-tile into a destination tile at an (indexRow, indexCol) offset. +- [TINSERT_FP](TINSERT_FP.md) - Insert with fp/scaling tile (vector-quantization parameters). +- [TFILLPAD](TFILLPAD.md) - Copy+pad a tile outside the valid region with a compile-time pad value. +- [TFILLPAD_INPLACE](TFILLPAD_INPLACE.md) - In-place fill/pad variant. +- [TFILLPAD_EXPAND](TFILLPAD_EXPAND.md) - Fill/pad while allowing dst to be larger than src. +- [TMOV](TMOV.md) - Move/copy between tiles, optionally applying implementation-defined conversion modes. +- [TMOV_FP](TMOV_FP.md) - Move/convert from an accumulator tile into a destination tile, using a scaling (`fp`) tile for vector quantization parameters. +- [TRESHAPE](TRESHAPE.md) - Reinterpret a tile as another tile type/shape while preserving the underlying bytes. +- [TTRANS](TTRANS.md) - Transpose with an implementation-defined temporary tile. +- [TSUBVIEW](TSUBVIEW.md) - Reinterpret a tile as a subtile of another tile. +- [TGET_SCALE_ADDR](TGET_SCALE_ADDR.md) - Bind the on-chip address of output tile to a scaled factor of that of input tile. + +## Complex +- [TPRINT](TPRINT.md) - Debug/print elements from a tile (implementation-defined). +- [TMRGSORT](TMRGSORT.md) - Merge sort for multiple sorted lists (implementation-defined element format and layout). +- [TSORT32](TSORT32.md) - Sort each 32-element block of `src` together with the corresponding indices from `idx`, and write the sorted value-index pairs into `dst`. +- [TGATHER](TGATHER.md) - Gather/select elements using either an index tile or a compile-time mask pattern. +- [TCI](TCI.md) - Generate a contiguous integer sequence into a destination tile. +- [TTRI](TTRI.md) - Generate a triangular (lower/upper) mask tile. +- [TPARTADD](TPARTADD.md) - Partial elementwise add with implementation-defined handling of mismatched valid regions. +- [TPARTMUL](TPARTMUL.md) - Partial elementwise multiply with implementation-defined handling of mismatched valid regions. +- [TPARTMAX](TPARTMAX.md) - Partial elementwise max with implementation-defined handling of mismatched valid regions. +- [TPARTMIN](TPARTMIN.md) - Partial elementwise min with implementation-defined handling of mismatched valid regions. +- [TGATHERB](TGATHERB.md) - Gather elements using byte offsets. +- [TSCATTER](TSCATTER.md) - Scatter rows of a source tile into a destination tile using per-element row indices. +- [TQUANT](TQUANT.md) - Quantize a tile (e.g. FP32 to FP8) producing exponent/scaling/max outputs. + +## Communication + +See [comm/README.md](comm/README.md) for the full per-instruction communication ISA reference (point-to-point, async, synchronization, and collective operations). diff --git a/designs/outerCube/PTOISA/README_zh.md b/designs/outerCube/PTOISA/README_zh.md new file mode 100644 index 00000000..00d087e3 --- /dev/null +++ b/designs/outerCube/PTOISA/README_zh.md @@ -0,0 +1,153 @@ +

+ PTO Tile Lib +

+ +# PTO ISA 参考 + +本目录是 PTO Tile Lib ISA 的指令参考（每条指令一页）。 + +- 权威来源（C++ 内建函数）：`include/pto/common/pto_instr.hpp` +- [通用约定（操作数、事件、修饰符）](conventions_zh.md) + +## 同步 +- [TSYNC](TSYNC_zh.md) - 同步 PTO 执行（等待事件或插入每操作流水线屏障）。 + +## 手动 / 资源绑定 +- [TASSIGN](TASSIGN_zh.md) - 将 Tile 对象绑定到实现定义的片上地址（手动放置）。 +- [TSETFMATRIX](TSETFMATRIX_zh.md) - 为类 IMG2COL 操作设置 FMATRIX 寄存器。 +- [TSET_IMG2COL_RPT](TSET_IMG2COL_RPT_zh.md) - 从 IMG2COL 配置 Tile 设置 IMG2COL 重复次数元数据。 +- [TSET_IMG2COL_PADDING](TSET_IMG2COL_PADDING_zh.md) - 从 IMG2COL 配置 Tile 设置 IMG2COL 填充元数据。 + +## 逐元素（Tile-Tile） +- [TADD](TADD_zh.md) - 两个 Tile 的逐元素加法。 +- [TABS](TABS_zh.md) - Tile 的逐元素绝对值。 +- [TAND](TAND_zh.md) - 两个 Tile 的逐元素按位与。 +- [TOR](TOR_zh.md) - 两个 Tile 的逐元素按位或。 +- [TSUB](TSUB_zh.md) - 两个 Tile 的逐元素减法。 +- [TMUL](TMUL_zh.md) - 两个 Tile 的逐元素乘法。 +- [TMIN](TMIN_zh.md) - 两个 Tile 的逐元素最小值。 +- [TMAX](TMAX_zh.md) - 两个 Tile 的逐元素最大值。 +- [TCMP](TCMP_zh.md) - 比较两个 Tile 并写入一个打包的谓词掩码。 +- [TDIV](TDIV_zh.md) - 两个 Tile 的逐元素除法。 +- [TSHL](TSHL_zh.md) - 两个 Tile 的逐元素左移。 +- [TSHR](TSHR_zh.md) - 两个 Tile 的逐元素右移。 +- [TXOR](TXOR_zh.md) - 两个 Tile 的逐元素按位异或。 +- [TLOG](TLOG_zh.md) - Tile 的逐元素自然对数。 +- [TRECIP](TRECIP_zh.md) - Tile 的逐元素倒数。 +- [TPRELU](TPRELU_zh.md) - 带逐元素斜率 Tile 的逐元素参数化 ReLU (PReLU)。 +- [TADDC](TADDC_zh.md) - 三元逐元素加法：`src0 + src1 + src2`。 +- [TSUBC](TSUBC_zh.md) - 三元逐元素运算：`src0 - src1 + src2`。 +- [TCVT](TCVT_zh.md) - 带指定舍入模式的逐元素类型转换。 +- [TSEL](TSEL_zh.md) - 使用掩码 Tile 在两个 Tile 之间进行选择（逐元素选择）。 +- [TRSQRT](TRSQRT_zh.md) - 逐元素倒数平方根。 +- [TSQRT](TSQRT_zh.md) - 逐元素平方根。 +- [TEXP](TEXP_zh.md) - 逐元素指数运算。 +- [TNOT](TNOT_zh.md) - Tile 的逐元素按位取反。 +- [TRELU](TRELU_zh.md) - Tile 的逐元素 ReLU。 +- [TNEG](TNEG_zh.md) - Tile 的逐元素取负。 +- [TREM](TREM_zh.md) - 两个 Tile 的逐元素余数，余数符号与除数相同。 +- [TFMOD](TFMOD_zh.md) - 两个 Tile 的逐元素余数，余数符号与被除数相同。 + +## Tile-标量 / Tile-立即数 +- [TEXPANDS](TEXPANDS_zh.md) - 将标量广播到目标 Tile 中。 +- [TCMPS](TCMPS_zh.md) - 将 Tile 与标量比较并写入逐元素比较结果。 +- [TSELS](TSELS_zh.md) - 使用掩码 Tile 在源 Tile 和标量之间进行选择（源 Tile 逐元素选择）。 +- [TMINS](TMINS_zh.md) - Tile 与标量的逐元素最小值。 +- [TADDS](TADDS_zh.md) - Tile 与标量的逐元素加法。 +- [TSUBS](TSUBS_zh.md) - 从 Tile 中逐元素减去一个标量。 +- [TDIVS](TDIVS_zh.md) - 与标量的逐元素除法（Tile/标量 或 标量/Tile）。 +- [TMULS](TMULS_zh.md) - Tile 与标量的逐元素乘法。 +- [TFMODS](TFMODS_zh.md) - 与标量的逐元素余数：`fmod(src, scalar)`。 +- [TREMS](TREMS_zh.md) - 与标量的逐元素余数：`remainder(src, scalar)`。 +- [TMAXS](TMAXS_zh.md) - Tile 与标量的逐元素最大值：`max(src, scalar)`。 +- [TANDS](TANDS_zh.md) - Tile 与标量的逐元素按位与。 +- [TORS](TORS_zh.md) - Tile 与标量的逐元素按位或。 +- [TSHLS](TSHLS_zh.md) - Tile 按标量逐元素左移。 +- [TSHRS](TSHRS_zh.md) - Tile 按标量逐元素右移。 +- [TXORS](TXORS_zh.md) - Tile 与标量的逐元素按位异或。 +- [TLRELU](TLRELU_zh.md) - 带标量斜率的 Leaky ReLU。 +- [TADDSC](TADDSC_zh.md) - 与标量和第二个 Tile 的融合逐元素加法：`src0 + scalar + src1`。 +- [TSUBSC](TSUBSC_zh.md) - 融合逐元素运算：`src0 - scalar + src1`。 + +## 轴归约 / 扩展 +- [TROWSUM](TROWSUM_zh.md) - 通过对列求和来归约每一行。 +- [TROWPROD](TROWPROD_zh.md) - 通过跨列乘积来归约每一行。 +- [TCOLSUM](TCOLSUM_zh.md) - 通过对行求和来归约每一列。 +- [TCOLPROD](TCOLPROD_zh.md) - 通过跨行乘积来归约每一列。 +- [TCOLMAX](TCOLMAX_zh.md) - 通过取行间最大值来归约每一列。 +- [TROWMAX](TROWMAX_zh.md) - 通过取列间最大值来归约每一行。 +- [TROWMIN](TROWMIN_zh.md) - 通过取列间最小值来归约每一行。 +- [TROWARGMAX](TROWARGMAX_zh.md) - 获取每行最大值对应列索引。 +- [TROWARGMIN](TROWARGMIN_zh.md) - 获取每行最小值对应列索引。 +- [TCOLARGMAX](TCOLARGMAX_zh.md) - 获取每列最大值对应行索引。 +- [TCOLARGMIN](TCOLARGMIN_zh.md) - 获取每列最小值对应行索引。 +- [TROWEXPAND](TROWEXPAND_zh.md) - 将每个源行的第一个元素广播到目标行中。 +- [TROWEXPANDDIV](TROWEXPANDDIV_zh.md) - 行广播除法：将 `src0` 的每一行除以一个每行标量向量 `src1`。 +- [TROWEXPANDMUL](TROWEXPANDMUL_zh.md) - 行广播乘法：将 `src0` 的每一行乘以一个每行标量向量 `src1`。 +- [TROWEXPANDSUB](TROWEXPANDSUB_zh.md) - 行广播减法：从 `src0` 的每一行中减去一个每行标量向量 `src1`。 +- [TROWEXPANDADD](TROWEXPANDADD_zh.md) - 行广播加法：加上一个每行标量向量。 +- [TROWEXPANDMAX](TROWEXPANDMAX_zh.md) - 行广播最大值：与每行标量向量取最大值。 +- [TROWEXPANDMIN](TROWEXPANDMIN_zh.md) - 行广播最小值：与每行标量向量取最小值。 +- [TROWEXPANDEXPDIF](TROWEXPANDEXPDIF_zh.md) - 行指数差运算：计算 exp(src0 - src1)，其中 src1 为每行标量。 +- [TCOLMIN](TCOLMIN_zh.md) - 通过取行间最小值来归约每一列。 +- [TCOLEXPAND](TCOLEXPAND_zh.md) - 将每个源列的第一个元素广播到目标列中。 +- [TCOLEXPANDDIV](TCOLEXPANDDIV_zh.md) - 列广播除法：将每一列除以一个每列标量向量。 +- [TCOLEXPANDMUL](TCOLEXPANDMUL_zh.md) - 列广播乘法：将每一列乘以一个每列标量向量。 +- [TCOLEXPANDADD](TCOLEXPANDADD_zh.md) - 列广播加法：对每一列加上每列标量向量。 +- [TCOLEXPANDMAX](TCOLEXPANDMAX_zh.md) - 列广播最大值：与每列标量向量取最大值。 +- [TCOLEXPANDMIN](TCOLEXPANDMIN_zh.md) - 列广播最小值：与每列标量向量取最小值。 +- [TCOLEXPANDSUB](TCOLEXPANDSUB_zh.md) - 列广播减法：从每一列中减去一个每列标量向量。 +- [TCOLEXPANDEXPDIF](TCOLEXPANDEXPDIF_zh.md) - 列指数差运算：计算 exp(src0 - src1)，其中 src1 为每列标量。 + +## 内存（GM <-> Tile） +- [TLOAD](TLOAD_zh.md) - 从 GlobalTensor (GM) 加载数据到 Tile。 +- [TPREFETCH](TPREFETCH_zh.md) - 将数据从全局内存预取到 Tile 本地缓存/缓冲区（提示）。 +- [TSTORE](TSTORE_zh.md) - 将 Tile 中的数据存储到 GlobalTensor (GM)，可选使用原子写入或量化参数。 +- [TSTORE_FP](TSTORE_FP_zh.md) - 使用缩放 (`fp`) Tile 作为向量量化参数，将累加器 Tile 存储到全局内存。 +- [MGATHER](MGATHER_zh.md) - 使用逐元素索引从全局内存收集加载元素到 Tile 中。 +- [MSCATTER](MSCATTER_zh.md) - 使用逐元素索引将 Tile 中的元素散播存储到全局内存。 + +## 矩阵乘 +- [TGEMV_MX](TGEMV_MX_zh.md) - 带缩放 Tile 的 GEMV 变体，支持混合精度/量化矩阵向量计算。 +- [TMATMUL_MX](TMATMUL_MX_zh.md) - 带额外缩放 Tile 的矩阵乘法 (GEMM)，用于支持目标上的混合精度/量化矩阵乘法。 +- [TMATMUL](TMATMUL_zh.md) - 矩阵乘法 (GEMM)，生成累加器/输出 Tile。 +- [TMATMUL_ACC](TMATMUL_ACC_zh.md) - 带累加器输入的矩阵乘法（融合累加）。 +- [TMATMUL_BIAS](TMATMUL_BIAS_zh.md) - 带偏置加法的矩阵乘法。 +- [TGEMV](TGEMV_zh.md) - 通用矩阵-向量乘法，生成累加器/输出 Tile。 +- [TGEMV_ACC](TGEMV_ACC_zh.md) - 带显式累加器输入/输出 Tile 的 GEMV。 +- [TGEMV_BIAS](TGEMV_BIAS_zh.md) - 带偏置加法的 GEMV。 + +## 数据搬运 / 布局 +- [TEXTRACT](TEXTRACT_zh.md) - 从源 Tile 中提取子 Tile。 +- [TEXTRACT_FP](TEXTRACT_FP_zh.md) - 带 fp/缩放 Tile 的提取（向量量化参数）。 +- [TIMG2COL](TIMG2COL_zh.md) - 用于类卷积工作负载的图像到列变换。 +- [TINSERT](TINSERT_zh.md) - 在 (indexRow, indexCol) 偏移处将子 Tile 插入到目标 Tile 中。 +- [TINSERT_FP](TINSERT_FP_zh.md) - 带 fp/缩放 Tile 的插入（向量量化参数）。 +- [TFILLPAD](TFILLPAD_zh.md) - 复制 Tile 并在有效区域外使用编译时填充值进行填充。 +- [TFILLPAD_INPLACE](TFILLPAD_INPLACE_zh.md) - 原地填充/填充变体。 +- [TFILLPAD_EXPAND](TFILLPAD_EXPAND_zh.md) - 填充/填充时允许目标大于源。 +- [TMOV](TMOV_zh.md) - 在 Tile 之间移动/复制，可选应用实现定义的转换模式。 +- [TMOV_FP](TMOV_FP_zh.md) - 使用缩放 (`fp`) Tile 作为向量量化参数，将累加器 Tile 移动/转换到目标 Tile。 +- [TRESHAPE](TRESHAPE_zh.md) - 将 Tile 重新解释为另一种 Tile 类型/形状，同时保留底层字节。 +- [TTRANS](TTRANS_zh.md) - 使用实现定义的临时 Tile 进行转置。 +- [TSUBVIEW](TSUBVIEW_zh.md) - 表达一个tile是另一个tile的subview。 +- [TGET_SCALE_ADDR](TGET_SCALE_ADDR_zh.md) - 将输出tile的片上内存值绑定为扩展后的输入tile内存的值。 + +## 复杂指令 +- [TPRINT](TPRINT_zh.md) - 调试/打印 Tile 中的元素（实现定义）。 +- [TMRGSORT](TMRGSORT_zh.md) - 用于多个已排序列表的归并排序（实现定义的元素格式和布局）。 +- [TSORT32](TSORT32_zh.md) - 对 `src` 的每个 32 元素块，与 `idx` 中对应的索引一起进行排序，并将排序后的值-索引对写入 `dst`。 +- [TGATHER](TGATHER_zh.md) - 使用索引 Tile 或编译时掩码模式来收集/选择元素。 +- [TCI](TCI_zh.md) - 生成连续整数序列到目标 Tile 中。 +- [TTRI](TTRI_zh.md) - 生成三角（下/上）掩码 Tile。 +- [TPARTADD](TPARTADD_zh.md) - 部分逐元素加法，对不匹配的有效区域具有实现定义的处理方式。 +- [TPARTMUL](TPARTMUL_zh.md) - 部分逐元素乘法，对有效区域不一致的处理为实现定义。 +- [TPARTMAX](TPARTMAX_zh.md) - 部分逐元素最大值，对不匹配的有效区域具有实现定义的处理方式。 +- [TPARTMIN](TPARTMIN_zh.md) - 部分逐元素最小值，对不匹配的有效区域具有实现定义的处理方式。 +- [TGATHERB](TGATHERB_zh.md) - 使用字节偏移量收集元素。 +- [TSCATTER](TSCATTER_zh.md) - 使用逐元素行索引将源 Tile 的行散播到目标 Tile 中。 +- [TQUANT](TQUANT_zh.md) - 量化 Tile（例如 FP32 到 FP8），生成指数/缩放/最大值输出。 + +## 通信 + +完整的通信 ISA 指令参考（点对点、异步、同步原语及集合通信）见 [comm/README_zh.md](comm/README_zh.md)。 diff --git a/designs/outerCube/PTOISA/TABS.md b/designs/outerCube/PTOISA/TABS.md new file mode 100644 index 00000000..3931b44e --- /dev/null +++ b/designs/outerCube/PTOISA/TABS.md @@ -0,0 +1,133 @@ +# TABS + + +## Tile Operation Diagram + +![TABS tile operation](../figures/isa/TABS.svg) + +## Introduction + +Elementwise absolute value of a tile. + +## Math Interpretation + +For each element `(i, j)` in the valid region: + +$$ \mathrm{dst}_{i,j} = \left|\mathrm{src}_{i,j}\right| $$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = tabs %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tabs %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tabs ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### IR Level 1 (SSA) + +```text +%dst = pto.tabs %src : !pto.tile<...> -> !pto.tile<...> +``` + +### IR Level 2 (DPS) + +```text +pto.tabs ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TABS(TileDataDst &dst, TileDataSrc &src, WaitEvents &... events); +``` + +## Constraints + +- **Implementation checks (CPU sim)**: + - `TileData::DType` must be one of: `int32_t`, `int`, `int16_t`, `half`, `float`. + - The implementation iterates over `dst.GetValidRow()` / `dst.GetValidCol()`. +- **Implementation checks (Costmodel)**: + - `TileData::DType` must be one of: `int32_t`、`int16_t`、`int8_t`、`uint8_t`、`half`、`float`. +- **Implementation checks (NPU)**: + - `TileData::DType` must be one of: `float` or `half`; + - Tile location must be vector (`TileData::Loc == TileType::Vec`); + - Static valid bounds: `TileData::ValidRow <= TileData::Rows` and `TileData::ValidCol <= TileData::Cols`; + - Runtime: `src.GetValidRow() == dst.GetValidRow()` and `src.GetValidCol() == dst.GetValidCol()`; + - Tile layout must be row-major (`TileData::isRowMajor`). +- **Valid region**: + - The op uses `dst.GetValidRow()` / `dst.GetValidCol()` as the iteration domain. + +## Examples + +### Auto + +```cpp +#include + +using namespace pto; + +void example_auto() { + using TileT = Tile; + TileT src, dst; + TABS(dst, src); +} +``` + +### Manual + +```cpp +#include + +using namespace pto; + +void example_manual() { + using TileT = Tile; + TileT src, dst; + TASSIGN(src, 0x1000); + TASSIGN(dst, 0x2000); + TABS(dst, src); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.tabs %src : !pto.tile<...> -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tabs %src : !pto.tile<...> -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = tabs %src : !pto.tile<...> -> !pto.tile<...> +# AS Level 2 (DPS) +pto.tabs ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TABS_zh.md b/designs/outerCube/PTOISA/TABS_zh.md new file mode 100644 index 00000000..3b7f23ce --- /dev/null +++ b/designs/outerCube/PTOISA/TABS_zh.md @@ -0,0 +1,106 @@ +# TABS + +## 指令示意图 + +![TABS tile operation](../figures/isa/TABS.svg) + +## 简介 + +Tile 的逐元素绝对值。 + +## 数学语义 + +对每个元素 `(i, j)` 在有效区域内： + +$$ \mathrm{dst}_{i,j} = \left|\mathrm{src}_{i,j}\right| $$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS Specification](../assembly/PTO-AS.md). + +同步形式： + +```text +%dst = tabs %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tabs %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tabs ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### AS Level 1（SSA） + +```text +%dst = pto.tabs %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.tabs ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TABS(TileDataDst &dst, TileDataSrc &src, WaitEvents &... events); +``` + +## 约束 + +- **实现检查 (CPU sim)**: + - `TileData::DType` must be one of: `int32_t`, `int`, `int16_t`, `half`, `float`. + - The implementation iterates over `dst.GetValidRow()` / `dst.GetValidCol()`. +- **实现检查 (Costmodel)**: + - `TileData::DType` must be one of: `int32_t`、`int16_t`、`int8_t`、`uint8_t`、`half`、`float`. +- **实现检查 (NPU)**: + - `TileData::DType` must be one of: `float` or `half`; + - Tile location must be vector (`TileData::Loc == TileType::Vec`); + - Static valid bounds: `TileData::ValidRow <= TileData::Rows` and `TileData::ValidCol <= TileData::Cols`; + - Runtime: `src.GetValidRow() == dst.GetValidRow()` and `src.GetValidCol() == dst.GetValidCol()`; + - Tile 布局 must be row-major (`TileData::isRowMajor`). +- **有效区域**: + - The op uses `dst.GetValidRow()` / `dst.GetValidCol()` as the iteration domain. + +## 示例 + +### 自动（Auto） + +```cpp +#include + +using namespace pto; + +void example_auto() { + using TileT = Tile; + TileT src, dst; + TABS(dst, src); +} +``` + +### 手动（Manual） + +```cpp +#include + +using namespace pto; + +void example_manual() { + using TileT = Tile; + TileT src, dst; + TASSIGN(src, 0x1000); + TASSIGN(dst, 0x2000); + TABS(dst, src); +} +``` diff --git a/designs/outerCube/PTOISA/TADD.md b/designs/outerCube/PTOISA/TADD.md new file mode 100644 index 00000000..d6b4a5ad --- /dev/null +++ b/designs/outerCube/PTOISA/TADD.md @@ -0,0 +1,129 @@ +# TADD + + +## Tile Operation Diagram + +![TADD tile operation](../figures/isa/TADD.svg) + +## Introduction + +Elementwise add of two tiles. + +## Math Interpretation + +For each element `(i, j)` in the valid region: + +$$ \mathrm{dst}_{i,j} = \mathrm{src0}_{i,j} + \mathrm{src1}_{i,j} $$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = tadd %src0, %src1 : !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tadd %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tadd ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### IR Level 1 (SSA) + +```text +%dst = pto.tadd %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### IR Level 2 (DPS) + +```text +pto.tadd ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TADD(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, WaitEvents &... events); +``` + +## Constraints + +- **Implementation checks (A2A3)**: + - `TileData::DType` must be one of: `int32_t`, `int16_t`, `half`, `float`. + - Tile layout must be row-major (`TileData::isRowMajor`). +- **Implementation checks (A5)**: + - `TileData::DType` must be one of: `int32_t`, `uint32_t`, `float`, `int16_t`, `uint16_t`, `half`, `bfloat16_t`, `uint8_t`, `int8_t`. + - Tile layout must be row-major (`TileData::isRowMajor`). +- **Valid region**: + - The op uses `dst.GetValidRow()` / `dst.GetValidCol()` as the iteration domain; `src0/src1` are assumed to be compatible (not validated by explicit runtime checks in this op). + +## Examples + +### Auto + +```cpp +#include + +using namespace pto; + +void example_auto() { + using TileT = Tile; + TileT src0, src1, dst; + TADD(dst, src0, src1); +} +``` + +### Manual + +```cpp +#include + +using namespace pto; + +void example_manual() { + using TileT = Tile; + TileT src0, src1, dst; + TASSIGN(src0, 0x1000); + TASSIGN(src1, 0x2000); + TASSIGN(dst, 0x3000); + TADD(dst, src0, src1); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.tadd %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tadd %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = tadd %src0, %src1 : !pto.tile<...> +# AS Level 2 (DPS) +pto.tadd ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TADDC.md b/designs/outerCube/PTOISA/TADDC.md new file mode 100644 index 00000000..f91ad263 --- /dev/null +++ b/designs/outerCube/PTOISA/TADDC.md @@ -0,0 +1,103 @@ +# TADDC + + +## Tile Operation Diagram + +![TADDC tile operation](../figures/isa/TADDC.svg) + +## Introduction + +Elementwise ternary add: `src0 + src1 + src2`. + +## Math Interpretation + +For each element `(i, j)` in the valid region: + +$$ \mathrm{dst}_{i,j} = \mathrm{src0}_{i,j} + \mathrm{src1}_{i,j} + \mathrm{src2}_{i,j} $$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = taddc %src0, %src1, %src2 : !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.taddc %src0, %src1, %src2 : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.taddc ins(%src0, %src1, %src2 : !pto.tile_buf<...>, !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### IR Level 1 (SSA) + +```text +%dst = pto.taddc %src0, %src1, %src2 : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### IR Level 2 (DPS) + +```text +pto.taddc ins(%src0, %src1, %src2 : !pto.tile_buf<...>, !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TADDC(TileData &dst, TileData &src0, TileData &src1, TileData &src2, WaitEvents &... events); +``` + +## Constraints + +- The op iterates over `dst.GetValidRow()` / `dst.GetValidCol()`. + +## Examples + +```cpp +#include + +using namespace pto; + +void example() { + using TileT = Tile; + TileT a, b, c, out; + TADDC(out, a, b, c); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.taddc %src0, %src1, %src2 : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.taddc %src0, %src1, %src2 : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = taddc %src0, %src1, %src2 : !pto.tile<...> +# AS Level 2 (DPS) +pto.taddc ins(%src0, %src1, %src2 : !pto.tile_buf<...>, !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TADDC_zh.md b/designs/outerCube/PTOISA/TADDC_zh.md new file mode 100644 index 00000000..1a9fec65 --- /dev/null +++ b/designs/outerCube/PTOISA/TADDC_zh.md @@ -0,0 +1,76 @@ +# TADDC + +## 指令示意图 + +![TADDC tile operation](../figures/isa/TADDC.svg) + +## 简介 + +三元逐元素加法：`src0 + src1 + src2`。 + +## 数学语义 + +对每个元素 `(i, j)` 在有效区域内： + +$$ \mathrm{dst}_{i,j} = \mathrm{src0}_{i,j} + \mathrm{src1}_{i,j} + \mathrm{src2}_{i,j} $$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS Specification](../assembly/PTO-AS.md). + +同步形式： + +```text +%dst = taddc %src0, %src1, %src2 : !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.taddc %src0, %src1, %src2 : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.taddc ins(%src0, %src1, %src2 : !pto.tile_buf<...>, !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### AS Level 1（SSA） + +```text +%dst = pto.taddc %src0, %src1, %src2 : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.taddc ins(%src0, %src1, %src2 : !pto.tile_buf<...>, !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TADDC(TileData &dst, TileData &src0, TileData &src1, TileData &src2, WaitEvents &... events); +``` + +## 约束 + +- The op iterates over `dst.GetValidRow()` / `dst.GetValidCol()`. + +## 示例 + +```cpp +#include + +using namespace pto; + +void example() { + using TileT = Tile; + TileT a, b, c, out; + TADDC(out, a, b, c); +} +``` diff --git a/designs/outerCube/PTOISA/TADDS.md b/designs/outerCube/PTOISA/TADDS.md new file mode 100644 index 00000000..c30212cc --- /dev/null +++ b/designs/outerCube/PTOISA/TADDS.md @@ -0,0 +1,134 @@ +# TADDS + + +## Tile Operation Diagram + +![TADDS tile operation](../figures/isa/TADDS.svg) + +## Introduction + +Elementwise add a scalar to a tile. + +## Math Interpretation + +For each element `(i, j)` in the valid region: + +$$ \mathrm{dst}_{i,j} = \mathrm{src}_{i,j} + \mathrm{scalar} $$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = tadds %src, %scalar : !pto.tile<...>, f32 +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tadds %src, %scalar : (!pto.tile<...>,dtype) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tadds ins(%src, %scalar : !pto.tile_buf<...>, dtype) outs(%dst : !pto.tile_buf<...>) +``` + +### IR Level 1 (SSA) + +```text +%dst = pto.tadds %src, %scalar : (!pto.tile<...>,dtype) -> !pto.tile<...> +``` + +### IR Level 2 (DPS) + +```text +pto.tadds ins(%src, %scalar : !pto.tile_buf<...>, dtype) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TADDS(TileDataDst &dst, TileDataSrc &src0, typename TileDataSrc::DType scalar, WaitEvents &... events); +``` + +## Constraints + +- **Implementation checks (A2A3)**: + - `TileData::DType` must be one of: `int32_t`, `int`, `int16_t`, `half`, `float16_t`, `float`, `float32_t`. + - Tile location must be vector (`TileData::Loc == TileType::Vec`). + - Static valid bounds: `TileData::ValidRow <= TileData::Rows` and `TileData::ValidCol <= TileData::Cols`. + - Runtime: `src0.GetValidRow() == dst.GetValidRow()` and `src0.GetValidCol() == dst.GetValidCol()`. + - Tile layout must be row-major (`TileData::isRowMajor`). +- **Implementation checks (A5)**: + - `TileData::DType` must be one of: `uint8_t`, `int8_t`, `uint16_t`, `int16_t`, `uint32_t`, `int32_t`, `half`, `float`, `bfloat16_t`. + - Tile location must be vector (`TileData::Loc == TileType::Vec`). + - Static valid bounds: `TileData::ValidRow <= TileData::Rows` and `TileData::ValidCol <= TileData::Cols`. + - Runtime: `src0.GetValidCol() == dst.GetValidCol()`. + - Tile layout must be row-major (`TileData::isRowMajor`). +- **Valid region**: + - The op uses `dst.GetValidRow()` / `dst.GetValidCol()` as the iteration domain. + +## Examples + +### Auto + +```cpp +#include + +using namespace pto; + +void example_auto() { + using TileT = Tile; + TileT src, dst; + TADDS(dst, src, 1.0f); +} +``` + +### Manual + +```cpp +#include + +using namespace pto; + +void example_manual() { + using TileT = Tile; + TileT src, dst; + TASSIGN(src, 0x1000); + TASSIGN(dst, 0x2000); + TADDS(dst, src, 1.0f); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.tadds %src, %scalar : (!pto.tile<...>,dtype) -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tadds %src, %scalar : (!pto.tile<...>,dtype) -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = tadds %src, %scalar : !pto.tile<...>, f32 +# AS Level 2 (DPS) +pto.tadds ins(%src, %scalar : !pto.tile_buf<...>, dtype) outs(%dst : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TADDSC.md b/designs/outerCube/PTOISA/TADDSC.md new file mode 100644 index 00000000..697dcef1 --- /dev/null +++ b/designs/outerCube/PTOISA/TADDSC.md @@ -0,0 +1,116 @@ +# TADDSC + + +## Tile Operation Diagram + +![TADDSC tile operation](../figures/isa/TADDSC.svg) + +## Introduction + +Elementwise fused add with scalar and a second tile: `src0 + scalar + src1`. + +## Math Interpretation + +For each element `(i, j)` in the valid region: + +$$ \mathrm{dst}_{i,j} = \mathrm{src0}_{i,j} + \mathrm{scalar} + \mathrm{src1}_{i,j} $$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = taddsc %src0, %scalar, %src1 : !pto.tile<...>, f32, !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.taddsc %src0, %scalar, %src1 : (!pto.tile<...>, dtype, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.taddsc ins(%src0, %scalar, %src1 : !pto.tile_buf<...>, dtype, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### IR Level 1 (SSA) + +```text +%dst = pto.taddsc %src0, %scalar, %src1 : (!pto.tile<...>, dtype, !pto.tile<...>) -> !pto.tile<...> +``` + +### IR Level 2 (DPS) + +```text +pto.taddsc ins(%src0, %scalar, %src1 : !pto.tile_buf<...>, dtype, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TADDSC(TileData& dst, TileData& src0, typename TileData::DType scalar, TileData& src1, + WaitEvents&... events); +``` + +## Constraints + +- **Implementation checks (A2A3)**: + - `TileData::DType` must be one of: `int32_t`, `int16_t`, `half`, `float`. + - Tile layout must be row-major (`TileData::isRowMajor`). +- **Implementation checks (A5)**: + - `TileData::DType` must be one of: `int32_t`, `int16_t`, `half`, `float`. + - Tile layout must be row-major (`TileData::isRowMajor`). +- **Common constraints**: + - Tile location must be vector (`TileData::Loc == TileType::Vec`). + - Static valid bounds: `TileData::ValidRow <= TileData::Rows` and `TileData::ValidCol <= TileData::Cols`. + - Runtime: `dst`, `src0` and `src1` must have the same valid row/col. + - Scalar type must match the Tile data type. +- **Valid region**: + - The op uses `dst.GetValidRow()` / `dst.GetValidCol()` as the iteration domain. + +## Examples + +```cpp +#include + +using namespace pto; + +void example() { + using TileT = Tile; + TileT a, b, out; + TADDSC(out, a, 2.0f, b); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.taddsc %src0, %scalar, %src1 : (!pto.tile<...>, dtype, !pto.tile<...>) -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.taddsc %src0, %scalar, %src1 : (!pto.tile<...>, dtype, !pto.tile<...>) -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = taddsc %src0, %scalar, %src1 : !pto.tile<...>, f32, !pto.tile<...> +# AS Level 2 (DPS) +pto.taddsc ins(%src0, %scalar, %src1 : !pto.tile_buf<...>, dtype, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TADDSC_zh.md b/designs/outerCube/PTOISA/TADDSC_zh.md new file mode 100644 index 00000000..b3920061 --- /dev/null +++ b/designs/outerCube/PTOISA/TADDSC_zh.md @@ -0,0 +1,89 @@ +# TADDSC + +## 指令示意图 + +![TADDSC tile operation](../figures/isa/TADDSC.svg) + +## 简介 + +与标量和第二个 Tile 的融合逐元素加法：`src0 + scalar + src1`。 + +## 数学语义 + +对每个元素 `(i, j)` 在有效区域内： + +$$ \mathrm{dst}_{i,j} = \mathrm{src0}_{i,j} + \mathrm{scalar} + \mathrm{src1}_{i,j} $$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS Specification](../assembly/PTO-AS.md). + +同步形式： + +```text +%dst = taddsc %src0, %scalar, %src1 : !pto.tile<...>, f32, !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.taddsc %src0, %scalar, %src1 : (!pto.tile<...>, dtype, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.taddsc ins(%src0, %scalar, %src1 : !pto.tile_buf<...>, dtype, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### AS Level 1（SSA） + +```text +%dst = pto.taddsc %src0, %scalar, %src1 : (!pto.tile<...>, dtype, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.taddsc ins(%src0, %scalar, %src1 : !pto.tile_buf<...>, dtype, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TADDSC(TileData& dst, TileData& src0, typename TileData::DType scalar, TileData& src1, + WaitEvents&... events); +``` + +## 约束 + +- **实现检查 (A2A3)**: + - `TileData::DType` must be one of: `int32_t`, `int16_t`, `half`, `float`. + - Tile 布局 must be row-major (`TileData::isRowMajor`). +- **实现检查 (A5)**: + - `TileData::DType` must be one of: `int32_t`, `int16_t`, `half`, `float`. + - Tile 布局 must be row-major (`TileData::isRowMajor`). +- **Common constraints**: + - Tile location must be vector (`TileData::Loc == TileType::Vec`). + - Static valid bounds: `TileData::ValidRow <= TileData::Rows` and `TileData::ValidCol <= TileData::Cols`. + - Runtime: `dst`, `src0` and `src1` must have the same valid row/col. + - Scalar type must match the Tile data type. +- **有效区域**: + - The op uses `dst.GetValidRow()` / `dst.GetValidCol()` as the iteration domain. + +## 示例 + +```cpp +#include + +using namespace pto; + +void example() { + using TileT = Tile; + TileT a, b, out; + TADDSC(out, a, 2.0f, b); +} +``` diff --git a/designs/outerCube/PTOISA/TADDS_zh.md b/designs/outerCube/PTOISA/TADDS_zh.md new file mode 100644 index 00000000..1ab2a003 --- /dev/null +++ b/designs/outerCube/PTOISA/TADDS_zh.md @@ -0,0 +1,107 @@ +# TADDS + +## 指令示意图 + +![TADDS tile operation](../figures/isa/TADDS.svg) + +## 简介 + +Tile 与标量的逐元素加法。 + +## 数学语义 + +对每个元素 `(i, j)` 在有效区域内： + +$$ \mathrm{dst}_{i,j} = \mathrm{src}_{i,j} + \mathrm{scalar} $$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS Specification](../assembly/PTO-AS.md). + +同步形式： + +```text +%dst = tadds %src, %scalar : !pto.tile<...>, f32 +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tadds %src, %scalar : (!pto.tile<...>,dtype) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tadds ins(%src, %scalar : !pto.tile_buf<...>, dtype) outs(%dst : !pto.tile_buf<...>) +``` + +### AS Level 1（SSA） + +```text +%dst = pto.tadds %src, %scalar : (!pto.tile<...>,dtype) -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.tadds ins(%src, %scalar : !pto.tile_buf<...>, dtype) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TADDS(TileDataDst &dst, TileDataSrc &src0, typename TileDataSrc::DType scalar, WaitEvents &... events); +``` + +## 约束 + +- **实现检查 (A2A3)**: + - `TileData::DType` must be one of: `int32_t`, `int`, `int16_t`, `half`, `float16_t`, `float`, `float32_t`. + - Tile location must be vector (`TileData::Loc == TileType::Vec`). + - Static valid bounds: `TileData::ValidRow <= TileData::Rows` and `TileData::ValidCol <= TileData::Cols`. + - Runtime: `src0.GetValidRow() == dst.GetValidRow()` and `src0.GetValidCol() == dst.GetValidCol()`. + - Tile 布局 must be row-major (`TileData::isRowMajor`). +- **实现检查 (A5)**: + - `TileData::DType` must be one of: `uint8_t`, `int8_t`, `uint16_t`, `int16_t`, `uint32_t`, `int32_t`, `half`, `float`, `bfloat16_t`. + - Tile location must be vector (`TileData::Loc == TileType::Vec`). + - Static valid bounds: `TileData::ValidRow <= TileData::Rows` and `TileData::ValidCol <= TileData::Cols`. + - Runtime: `src0.GetValidCol() == dst.GetValidCol()`. + - Tile 布局 must be row-major (`TileData::isRowMajor`). +- **有效区域**: + - The op uses `dst.GetValidRow()` / `dst.GetValidCol()` as the iteration domain. + +## 示例 + +### 自动（Auto） + +```cpp +#include + +using namespace pto; + +void example_auto() { + using TileT = Tile; + TileT src, dst; + TADDS(dst, src, 1.0f); +} +``` + +### 手动（Manual） + +```cpp +#include + +using namespace pto; + +void example_manual() { + using TileT = Tile; + TileT src, dst; + TASSIGN(src, 0x1000); + TASSIGN(dst, 0x2000); + TADDS(dst, src, 1.0f); +} +``` diff --git a/designs/outerCube/PTOISA/TADD_zh.md b/designs/outerCube/PTOISA/TADD_zh.md new file mode 100644 index 00000000..8041e0fe --- /dev/null +++ b/designs/outerCube/PTOISA/TADD_zh.md @@ -0,0 +1,102 @@ +# TADD + +## 指令示意图 + +![TADD tile operation](../figures/isa/TADD.svg) + +## 简介 + +两个 Tile 的逐元素加法。 + +## 数学语义 + +对每个元素 `(i, j)` 在有效区域内： + +$$ \mathrm{dst}_{i,j} = \mathrm{src0}_{i,j} + \mathrm{src1}_{i,j} $$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS Specification](../assembly/PTO-AS.md). + +同步形式： + +```text +%dst = tadd %src0, %src1 : !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tadd %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tadd ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### AS Level 1（SSA） + +```text +%dst = pto.tadd %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.tadd ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TADD(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, WaitEvents &... events); +``` + +## 约束 + +- **实现检查 (A2A3)**: + - `TileData::DType` must be one of: `int32_t`, `int16_t`, `half`, `float`. + - Tile 布局 must be row-major (`TileData::isRowMajor`). +- **实现检查 (A5)**: + - `TileData::DType` must be one of: `int32_t`, `uint32_t`, `float`, `int16_t`, `uint16_t`, `half`, `bfloat16_t`, `uint8_t`, `int8_t`. + - Tile 布局 must be row-major (`TileData::isRowMajor`). +- **有效区域**: + - The op uses `dst.GetValidRow()` / `dst.GetValidCol()` as the iteration domain; `src0/src1` are assumed to be compatible (not validated by explicit runtime checks in this op). + +## 示例 + +### 自动（Auto） + +```cpp +#include + +using namespace pto; + +void example_auto() { + using TileT = Tile; + TileT src0, src1, dst; + TADD(dst, src0, src1); +} +``` + +### 手动（Manual） + +```cpp +#include + +using namespace pto; + +void example_manual() { + using TileT = Tile; + TileT src0, src1, dst; + TASSIGN(src0, 0x1000); + TASSIGN(src1, 0x2000); + TASSIGN(dst, 0x3000); + TADD(dst, src0, src1); +} +``` diff --git a/designs/outerCube/PTOISA/TALIAS.md b/designs/outerCube/PTOISA/TALIAS.md new file mode 100644 index 00000000..a827762d --- /dev/null +++ b/designs/outerCube/PTOISA/TALIAS.md @@ -0,0 +1,40 @@ +# TALIAS + +## Tile Operation Diagram + +![TALIAS tile operation](../figures/isa/TALIAS.svg) + +## Introduction + +Create an alias tile view that shares the original tile storage. + +## Math Interpretation + +Semantics are instruction-specific. Unless stated otherwise, behavior is defined over the destination valid region. + +## Assembly Syntax + +PTO-AS form: see `docs/assembly/PTO-AS.md`. + +### IR Level 1 (SSA) + +```text +%dst = pto.talias ... +``` + +### IR Level 2 (DPS) + +```text +pto.talias ins(...) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`. + +## Constraints + +Refer to backend-specific legality checks for data type/layout/location/shape constraints. + +## Examples + +See related instruction pages in `docs/isa/` for concrete Auto/Manual usage patterns. diff --git a/designs/outerCube/PTOISA/TALIAS_zh.md b/designs/outerCube/PTOISA/TALIAS_zh.md new file mode 100644 index 00000000..d182462c --- /dev/null +++ b/designs/outerCube/PTOISA/TALIAS_zh.md @@ -0,0 +1,41 @@ +# TALIAS + +## 指令示意图 + +![TALIAS tile operation](../figures/isa/TALIAS.svg) + +## 简介 + +创建一个与原始 Tile 共享底层存储的别名视图。 + +## 数学语义 + +语义随指令而变化。 Unless stated otherwise, behavior is defined over the destination valid region. + +## 汇编语法 + +PTO-AS 形式：参见 `docs/assembly/PTO-AS.md`. + +### AS Level 1（SSA） + +```text +%dst = pto.talias ... +``` + +### AS Level 2（DPS） + +```text +pto.talias ins(...) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`. + +## 约束 + +Refer to backend-specific legality checks for data type/layout/location/shape constraints. + +## 示例 + +See related instruction pages in `docs/isa/` for concrete Auto/Manual usage patterns. diff --git a/designs/outerCube/PTOISA/TAND.md b/designs/outerCube/PTOISA/TAND.md new file mode 100644 index 00000000..cb660442 --- /dev/null +++ b/designs/outerCube/PTOISA/TAND.md @@ -0,0 +1,103 @@ +# TAND + + +## Tile Operation Diagram + +![TAND tile operation](../figures/isa/TAND.svg) + +## Introduction + +Elementwise bitwise AND of two tiles. + +## Math Interpretation + +For each element `(i, j)` in the valid region: + +$$ \mathrm{dst}_{i,j} = \mathrm{src0}_{i,j} \;\&\; \mathrm{src1}_{i,j} $$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = tand %src0, %src1 : !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tand %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tand ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TAND(TileData &dst, TileData &src0, TileData &src1, WaitEvents &... events); +``` + +## Constraints + +- **Implementation checks (A2A3)**: + - Supported element types are 1-byte or 2-byte integral types. + - `dst`, `src0`, and `src1` must use the same element type. + - `dst`, `src0`, and `src1` must be row-major. + - Runtime: `src0.GetValidRow()/GetValidCol()` and `src1.GetValidRow()/GetValidCol()` must match `dst`. +- **Implementation checks (A5)**: + - Supported element types are 1-byte, 2-byte, or 4-byte integral types. + - `dst`, `src0`, and `src1` must use the same element type. + - `dst`, `src0`, and `src1` must be row-major. + - Runtime: `src0.GetValidRow()/GetValidCol()` and `src1.GetValidRow()/GetValidCol()` must match `dst`. +- **Valid region**: + - The op uses `dst.GetValidRow()` / `dst.GetValidCol()` as the iteration domain. + +## Examples + +```cpp +#include + +using namespace pto; + +void example() { + using TileT = Tile; + TileT a, b, out; + TAND(out, a, b); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.tand %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tand %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = tand %src0, %src1 : !pto.tile<...> +# AS Level 2 (DPS) +pto.tand ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/TANDS.md b/designs/outerCube/PTOISA/TANDS.md new file mode 100644 index 00000000..e829518b --- /dev/null +++ b/designs/outerCube/PTOISA/TANDS.md @@ -0,0 +1,106 @@ +# TANDS + + +## Tile Operation Diagram + +![TANDS tile operation](../figures/isa/TANDS.svg) + +## Introduction + +Elementwise bitwise AND of a tile and a scalar. + +## Math Interpretation + +For each element `(i, j)` in the valid region: + +$$ \mathrm{dst}_{i,j} = \mathrm{src}_{i,j} \;\&\; \mathrm{scalar} $$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = tands %src, %scalar : !pto.tile<...>, i32 +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tands %src, %scalar : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tands ins(%src, %scalar : !pto.tile_buf<...>, dtype) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TANDS(TileDataDst &dst, TileDataSrc &src, typename TileDataDst::DType scalar, WaitEvents &... events); +``` + +## Constraints + +- **Implementation checks (A2A3)**: + - Intended for integral element types. + - `dst` and `src` must use the same element type. + - `dst` and `src` must be vector tiles. + - Runtime: `src.GetValidRow() == dst.GetValidRow()` and `src.GetValidCol() == dst.GetValidCol()`. + - In manual mode, setting the source tile and destination tile to the same memory is unsupported. +- **Implementation checks (A5)**: + - Intended for integral element types supported by `TEXPANDS` and `TAND`. + - `dst` and `src` must use the same element type. + - `dst` and `src` must be vector tiles. + - In manual mode, setting the source tile and destination tile to the same memory is unsupported. +- **Valid region**: + - The op uses `dst.GetValidRow()` / `dst.GetValidCol()` as the iteration domain. + +## Examples + +```cpp +#include + +using namespace pto; + +void example() { + using TileDst = Tile; + using TileSrc = Tile; + TileDst dst; + TileSrc src; + TANDS(dst, src, 0xffu); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.tands %src, %scalar : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tands %src, %scalar : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = tands %src, %scalar : !pto.tile<...>, i32 +# AS Level 2 (DPS) +pto.tands ins(%src, %scalar : !pto.tile_buf<...>, dtype) outs(%dst : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/TANDS_zh.md b/designs/outerCube/PTOISA/TANDS_zh.md new file mode 100644 index 00000000..0968ae50 --- /dev/null +++ b/designs/outerCube/PTOISA/TANDS_zh.md @@ -0,0 +1,106 @@ +# TANDS + +## 指令示意图 + +![TANDS tile operation](../figures/isa/TANDS.svg) + +## 简介 + +Tile 与标量的逐元素按位与。 + +## 数学语义 + +对每个元素 `(i, j)` 在有效区域内： + +$$ \mathrm{dst}_{i,j} = \mathrm{src}_{i,j} \;\&\; \mathrm{scalar} $$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS 规范](../assembly/PTO-AS_zh.md)。 + +同步形式： + +```text +%dst = tands %src, %scalar : !pto.tile<...>, i32 +``` + +### AS Level 1（SSA） + +```text +%dst = pto.tands %src, %scalar : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.tands ins(%src, %scalar : !pto.tile_buf<...>, dtype) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`： + +```cpp +template +PTO_INST RecordEvent TANDS(TileDataDst &dst, TileDataSrc &src, typename TileDataDst::DType scalar, WaitEvents &... events); +``` + +## 约束 + +- **实现检查 (A2A3)**: + - 适用于整数元素类型。 + - `dst` 和 `src` 必须使用相同的元素类型。 + - `dst` 和 `src` 必须是向量 Tile。 + - 运行时：`src.GetValidRow() == dst.GetValidRow()` 且 `src.GetValidCol() == dst.GetValidCol()`。 + - 在手动模式下，不支持将源 Tile 和目标 Tile 设置为相同的内存。 +- **实现检查 (A5)**: + - 适用于 `TEXPANDS` 和 `TAND` 支持的整数元素类型。 + - `dst` 和 `src` 必须使用相同的元素类型。 + - `dst` 和 `src` 必须是向量 Tile。 + - 在手动模式下，不支持将源 Tile 和目标 Tile 设置为相同的内存。 +- **有效区域**: + - 该操作使用 `dst.GetValidRow()` / `dst.GetValidCol()` 作为迭代域。 + +## 示例 + +```cpp +#include + +using namespace pto; + +void example() { + using TileDst = Tile; + using TileSrc = Tile; + TileDst dst; + TileSrc src; + TANDS(dst, src, 0xffu); +} +``` + +## 汇编示例（ASM） + +### 自动模式 + +```text +# 自动模式：由编译器/运行时负责资源放置与调度。 +%dst = pto.tands %src, %scalar : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### 手动模式 + +```text +# 手动模式：先显式绑定资源，再发射指令。 +# 可选（当该指令包含 tile 操作数时）： +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tands %src, %scalar : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### PTO 汇编形式 + +```text +%dst = tands %src, %scalar : !pto.tile<...>, i32 +# AS Level 2 (DPS) +pto.tands ins(%src, %scalar : !pto.tile_buf<...>, dtype) outs(%dst : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/TAND_zh.md b/designs/outerCube/PTOISA/TAND_zh.md new file mode 100644 index 00000000..e91e08bd --- /dev/null +++ b/designs/outerCube/PTOISA/TAND_zh.md @@ -0,0 +1,103 @@ +# TAND + +## 指令示意图 + +![TAND tile operation](../figures/isa/TAND.svg) + +## 简介 + +两个 Tile 的逐元素按位与。 + +## 数学语义 + +对每个元素 `(i, j)` 在有效区域内： + +$$ \mathrm{dst}_{i,j} = \mathrm{src0}_{i,j} \;\&\; \mathrm{src1}_{i,j} $$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS 规范](../assembly/PTO-AS_zh.md)。 + +同步形式： + +```text +%dst = tand %src0, %src1 : !pto.tile<...> +``` + +### AS Level 1（SSA） + +```text +%dst = pto.tand %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.tand ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`： + +```cpp +template +PTO_INST RecordEvent TAND(TileData &dst, TileData &src0, TileData &src1, WaitEvents &... events); +``` + +## 约束 + +- **实现检查 (A2A3)**: + - 支持的元素类型为 1 字节或 2 字节整数类型。 + - `dst`、`src0` 和 `src1` 必须使用相同的元素类型。 + - `dst`、`src0` 和 `src1` 必须是行主序。 + - 运行时：`src0.GetValidRow()/GetValidCol()` 和 `src1.GetValidRow()/GetValidCol()` 必须与 `dst` 一致。 +- **实现检查 (A5)**: + - 支持的元素类型为 1 字节、2 字节或 4 字节整数类型。 + - `dst`、`src0` 和 `src1` 必须使用相同的元素类型。 + - `dst`、`src0` 和 `src1` 必须是行主序。 + - 运行时：`src0.GetValidRow()/GetValidCol()` 和 `src1.GetValidRow()/GetValidCol()` 必须与 `dst` 一致。 +- **有效区域**: + - 该操作使用 `dst.GetValidRow()` / `dst.GetValidCol()` 作为迭代域。 + +## 示例 + +```cpp +#include + +using namespace pto; + +void example() { + using TileT = Tile; + TileT a, b, out; + TAND(out, a, b); +} +``` + +## 汇编示例（ASM） + +### 自动模式 + +```text +# 自动模式：由编译器/运行时负责资源放置与调度。 +%dst = pto.tand %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### 手动模式 + +```text +# 手动模式：先显式绑定资源，再发射指令。 +# 可选（当该指令包含 tile 操作数时）： +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tand %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### PTO 汇编形式 + +```text +%dst = tand %src0, %src1 : !pto.tile<...> +# AS Level 2 (DPS) +pto.tand ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/TASSIGN.md b/designs/outerCube/PTOISA/TASSIGN.md new file mode 100644 index 00000000..92ad1c2c --- /dev/null +++ b/designs/outerCube/PTOISA/TASSIGN.md @@ -0,0 +1,219 @@ +# TASSIGN + + +## Tile Operation Diagram + +![TASSIGN tile operation](../figures/isa/TASSIGN.svg) + +## Introduction + +Bind a Tile object to an implementation-defined on-chip address (manual placement). + +## Math Interpretation + +Not applicable. + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +`TASSIGN` is typically introduced by bufferization/lowering when mapping SSA tiles to physical storage. + +Synchronous form: + +```text +tassign %tile, %addr : !pto.tile<...>, index +``` + +### AS Level 1 (SSA) + +```text +pto.tassign %tile, %addr : !pto.tile<...>, dtype +``` + +### AS Level 2 (DPS) + +```text +pto.tassign ins(%tile, %addr : !pto.tile_buf<...>, dtype) +``` + +### IR Level 1 (SSA) + +```text +pto.tassign %tile, %addr : !pto.tile<...>, dtype +``` + +### IR Level 2 (DPS) + +```text +pto.tassign ins(%tile, %addr : !pto.tile_buf<...>, dtype) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`. + +### Form 1: Runtime address + +```cpp +template +PTO_INST void TASSIGN(T& obj, AddrType addr); +``` + +Binds `obj` to the on-chip address `addr`. No compile-time bounds checking is +performed (the address value is not available at compile time). + +### Form 2: Compile-time address (with static bounds check) + +```cpp +template +PTO_INST void TASSIGN(T& obj); +``` + +Binds `obj` to the on-chip address `Addr`. Because `Addr` is a non-type +template parameter, the compiler performs the following **compile-time** checks +via `static_assert`: + +| Check | Condition | Assertion ID | Error message | +|-------|-----------|--------------|---------------| +| Memory space exists | `capacity > 0` | SA-0351 | Memory space is not available on this architecture. | +| Tile fits in memory | `tile_size <= capacity` | SA-0352 | Tile storage size exceeds memory space capacity. | +| Address in bounds | `Addr + tile_size <= capacity` | SA-0353 | addr + tile_size exceeds memory space capacity (out of bounds). | +| Address aligned | `Addr % alignment == 0` | SA-0354 | addr is not properly aligned for the target memory space. | + +See `docs/coding/debug.md` (fix recipe `FIX-A12`) for suggested remedies. + +The memory space, capacity, and alignment are determined automatically from the +Tile's `TileType` (i.e. `Loc` template parameter): + +| TileType | Memory | Capacity (A2A3) | Capacity (A5) | Capacity (Kirin9030) | Capacity (KirinX90) | Alignment | +|----------|--------|-----------------|---------------|----------------------|---------------------|-----------| +| Vec | UB | 192 KB | 256 KB | 128 KB | 128 KB | 32 B | +| Mat | L1 | 512 KB | 512 KB | 512 KB | 1024 KB | 32 B | +| Left | L0A | 64 KB | 64 KB | 32 KB | 64 KB | 32 B | +| Right | L0B | 64 KB | 64 KB | 32 KB | 64 KB | 32 B | +| Acc | L0C | 128 KB | 256 KB | 64 KB | 128 KB | 32 B | +| Bias | Bias | 1 KB | 4 KB | 1 KB | 1 KB | 32 B | +| Scaling | FBuffer | 2 KB | 4 KB | 7 KB | 6 KB | 32 B | +| ScaleLeft | L0A | N/A | 4 KB | N/A | N/A | 32 B | +| ScaleRight | L0B | N/A | 4 KB | N/A | N/A | 32 B | + +Capacities can be overridden at build time via `-D` flags (e.g. +`-DPTO_UBUF_SIZE_BYTES=262144`). See `include/pto/common/buffer_limits.hpp`. + +**Note:** This overload is only available for `Tile` and `ConvTile` types. For +`GlobalTensor`, use `TASSIGN(obj, pointer)` (Form 1). + +## Constraints + +- **Implementation checks**: + - If `obj` is a Tile: + - In manual mode (when `__PTO_AUTO__` is not defined), `addr` must be an integral type and is reinterpreted as the tile's storage address. + - In auto mode (when `__PTO_AUTO__` is defined), `TASSIGN(tile, addr)` is a no-op. + - If `obj` is a `GlobalTensor`: + - `addr` must be a pointer type. + - The pointed-to element type must match `GlobalTensor::DType`. + +## Examples + +### Runtime address (no compile-time check) + +```cpp +#include + +using namespace pto; + +void example_runtime() { + using TileT = Tile; + TileT a, b, c; + TASSIGN(a, 0x1000); + TASSIGN(b, 0x2000); + TASSIGN(c, 0x3000); + TADD(c, a, b); +} +``` + +### Compile-time address (with static bounds check) + +```cpp +#include + +using namespace pto; + +void example_checked() { + using TileT = Tile; + TileT a, b, c; + + TASSIGN<0x0000>(a); // OK: 0x0000 + 1024 <= 192KB + TASSIGN<0x0400>(b); // OK: 0x0400 + 1024 <= 192KB + TASSIGN<0x0800>(c); // OK: 0x0800 + 1024 <= 192KB + TADD(c, a, b); +} +``` + +The following triggers a compile error: + +```cpp +void example_oob() { + // Tile occupies 256*256*4 = 256KB + using BigTile = Tile; + BigTile t; + + // static_assert fires: tile_size (256KB) > UB capacity (192KB on A2A3) + TASSIGN<0x0>(t); +} +``` + +```cpp +void example_oob_addr() { + using TileT = Tile; // 64KB + TileT t; + + // static_assert fires: 0x20000 (128KB) + 64KB = 192KB, + // but 0x20001 + 64KB > 192KB + TASSIGN<0x20001>(t); +} +``` + +### Ping-pong L0 buffer allocation + +```cpp +void example_pingpong() { + using L0ATile = TileLeft; // L0A tile + using L0BTile = TileRight; // L0B tile + + L0ATile a0, a1; + L0BTile b0, b1; + + TASSIGN<0x0000>(a0); // L0A ping + TASSIGN<0x8000>(a1); // L0A pong + TASSIGN<0x0000>(b0); // L0B ping (separate physical memory from L0A) + TASSIGN<0x8000>(b1); // L0B pong +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +pto.tassign %tile, %addr : !pto.tile<...>, dtype +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +pto.tassign %tile, %addr : !pto.tile<...>, dtype +``` + +### PTO Assembly Form + +```text +tassign %tile, %addr : !pto.tile<...>, index +# AS Level 2 (DPS) +pto.tassign ins(%tile, %addr : !pto.tile_buf<...>, dtype) +``` diff --git a/designs/outerCube/PTOISA/TASSIGN_zh.md b/designs/outerCube/PTOISA/TASSIGN_zh.md new file mode 100644 index 00000000..cdf0ce03 --- /dev/null +++ b/designs/outerCube/PTOISA/TASSIGN_zh.md @@ -0,0 +1,192 @@ +# TASSIGN + +## 指令示意图 + +![TASSIGN tile operation](../figures/isa/TASSIGN.svg) + +## 简介 + +将 Tile 对象绑定到实现定义的片上地址（手动放置）。 + +## 数学语义 + +Not applicable. + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS Specification](../assembly/PTO-AS.md). + +`TASSIGN` is typically introduced by bufferization/lowering when mapping SSA tiles to physical storage. + +同步形式： + +```text +tassign %tile, %addr : !pto.tile<...>, index +``` + +### AS Level 1 (SSA) + +```text +pto.tassign %tile, %addr : !pto.tile<...>, dtype +``` + +### AS Level 2 (DPS) + +```text +pto.tassign ins(%tile, %addr : !pto.tile_buf<...>, dtype) +``` + +### AS Level 1（SSA） + +```text +pto.tassign %tile, %addr : !pto.tile<...>, dtype +``` + +### AS Level 2（DPS） + +```text +pto.tassign ins(%tile, %addr : !pto.tile_buf<...>, dtype) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`. + +### Form 1: Runtime address + +```cpp +template +PTO_INST void TASSIGN(T& obj, AddrType addr); +``` + +Binds `obj` to the on-chip address `addr`. No compile-time bounds checking is +performed (the address value is not available at compile time). + +### Form 2: Compile-time address (with static bounds check) + +```cpp +template +PTO_INST void TASSIGN(T& obj); +``` + +Binds `obj` to the on-chip address `Addr`. Because `Addr` is a non-type +template parameter, the compiler performs the following **compile-time** checks +via `static_assert`: + +| Check | Condition | Assertion ID | Error message | +|-------|-----------|--------------|---------------| +| Memory space exists | `capacity > 0` | SA-0351 | Memory space is not available on this architecture. | +| Tile fits in memory | `tile_size <= capacity` | SA-0352 | Tile storage size exceeds memory space capacity. | +| Address in bounds | `Addr + tile_size <= capacity` | SA-0353 | addr + tile_size exceeds memory space capacity (out of bounds). | +| Address aligned | `Addr % alignment == 0` | SA-0354 | addr is not properly aligned for the target memory space. | + +See `docs/coding/debug.md` (fix recipe `FIX-A12`) for suggested remedies. + +The memory space, capacity, and alignment are determined automatically from the +Tile's `TileType` (i.e. `Loc` template parameter): + +| TileType | Memory | Capacity (A2A3) | Capacity (A5) | Capacity (Kirin9030) | Capacity (KirinX90) | Alignment | +|----------|--------|-----------------|---------------|----------------------|---------------------|-----------| +| Vec | UB | 192 KB | 256 KB | 128 KB | 128 KB | 32 B | +| Mat | L1 | 512 KB | 512 KB | 512 KB | 1024 KB | 32 B | +| Left | L0A | 64 KB | 64 KB | 32 KB | 64 KB | 32 B | +| Right | L0B | 64 KB | 64 KB | 32 KB | 64 KB | 32 B | +| Acc | L0C | 128 KB | 256 KB | 64 KB | 128 KB | 32 B | +| Bias | Bias | 1 KB | 4 KB | 1 KB | 1 KB | 32 B | +| Scaling | FBuffer | 2 KB | 4 KB | 7 KB | 6 KB | 32 B | +| ScaleLeft | L0A | N/A | 4 KB | N/A | N/A | 32 B | +| ScaleRight | L0B | N/A | 4 KB | N/A | N/A | 32 B | + +Capacities can be overridden at build time via `-D` flags (e.g. +`-DPTO_UBUF_SIZE_BYTES=262144`). See `include/pto/common/buffer_limits.hpp`. + +**Note:** This overload is only available for `Tile` and `ConvTile` types. For +`GlobalTensor`, use `TASSIGN(obj, pointer)` (Form 1). + +## 约束 + +- **实现检查**: + - If `obj` is a Tile: + - In manual mode (when `__PTO_AUTO__` is not defined), `addr` must be an integral type and is reinterpreted as the tile's storage address. + - In auto mode (when `__PTO_AUTO__` is defined), `TASSIGN(tile, addr)` is a no-op. + - If `obj` is a `GlobalTensor`: + - `addr` must be a pointer type. + - The pointed-to element type must match `GlobalTensor::DType`. + +## 示例 + +### Runtime address (no compile-time check) + +```cpp +#include + +using namespace pto; + +void example_runtime() { + using TileT = Tile; + TileT a, b, c; + TASSIGN(a, 0x1000); + TASSIGN(b, 0x2000); + TASSIGN(c, 0x3000); + TADD(c, a, b); +} +``` + +### Compile-time address (with static bounds check) + +```cpp +#include + +using namespace pto; + +void example_checked() { + using TileT = Tile; + TileT a, b, c; + + TASSIGN<0x0000>(a); // OK: 0x0000 + 1024 <= 192KB + TASSIGN<0x0400>(b); // OK: 0x0400 + 1024 <= 192KB + TASSIGN<0x0800>(c); // OK: 0x0800 + 1024 <= 192KB + TADD(c, a, b); +} +``` + +The following triggers a compile error: + +```cpp +void example_oob() { + // Tile occupies 256*256*4 = 256KB + using BigTile = Tile; + BigTile t; + + // static_assert fires: tile_size (256KB) > UB capacity (192KB on A2A3) + TASSIGN<0x0>(t); +} +``` + +```cpp +void example_oob_addr() { + using TileT = Tile; // 64KB + TileT t; + + // static_assert fires: 0x20000 (128KB) + 64KB = 192KB, + // but 0x20001 + 64KB > 192KB + TASSIGN<0x20001>(t); +} +``` + +### Ping-pong L0 buffer allocation + +```cpp +void example_pingpong() { + using L0ATile = TileLeft; // L0A tile + using L0BTile = TileRight; // L0B tile + + L0ATile a0, a1; + L0BTile b0, b1; + + TASSIGN<0x0000>(a0); // L0A ping + TASSIGN<0x8000>(a1); // L0A pong + TASSIGN<0x0000>(b0); // L0B ping (separate physical memory from L0A) + TASSIGN<0x8000>(b1); // L0B pong +} +``` diff --git a/designs/outerCube/PTOISA/TAXPY.md b/designs/outerCube/PTOISA/TAXPY.md new file mode 100644 index 00000000..ffe6e549 --- /dev/null +++ b/designs/outerCube/PTOISA/TAXPY.md @@ -0,0 +1,40 @@ +# TAXPY + +## Tile Operation Diagram + +![TAXPY tile operation](../figures/isa/TAXPY.svg) + +## Introduction + +AXPY-style fused update: multiply a tile by a scalar and accumulate into the destination tile. + +## Math Interpretation + +Semantics are instruction-specific. Unless stated otherwise, behavior is defined over the destination valid region. + +## Assembly Syntax + +PTO-AS form: see `docs/assembly/PTO-AS.md`. + +### IR Level 1 (SSA) + +```text +%dst = pto.taxpy ... +``` + +### IR Level 2 (DPS) + +```text +pto.taxpy ins(...) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`. + +## Constraints + +Refer to backend-specific legality checks for data type/layout/location/shape constraints. + +## Examples + +See related instruction pages in `docs/isa/` for concrete Auto/Manual usage patterns. diff --git a/designs/outerCube/PTOISA/TAXPY_zh.md b/designs/outerCube/PTOISA/TAXPY_zh.md new file mode 100644 index 00000000..df5907e8 --- /dev/null +++ b/designs/outerCube/PTOISA/TAXPY_zh.md @@ -0,0 +1,41 @@ +# TAXPY + +## 指令示意图 + +![TAXPY tile operation](../figures/isa/TAXPY.svg) + +## 简介 + +AXPY 风格融合更新：将 Tile 乘以标量并累加到目标 Tile。 + +## 数学语义 + +语义随指令而变化。 Unless stated otherwise, behavior is defined over the destination valid region. + +## 汇编语法 + +PTO-AS 形式：参见 `docs/assembly/PTO-AS.md`. + +### AS Level 1（SSA） + +```text +%dst = pto.taxpy ... +``` + +### AS Level 2（DPS） + +```text +pto.taxpy ins(...) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`. + +## 约束 + +Refer to backend-specific legality checks for data type/layout/location/shape constraints. + +## 示例 + +See related instruction pages in `docs/isa/` for concrete Auto/Manual usage patterns. diff --git a/designs/outerCube/PTOISA/TCI.md b/designs/outerCube/PTOISA/TCI.md new file mode 100644 index 00000000..ee4ab171 --- /dev/null +++ b/designs/outerCube/PTOISA/TCI.md @@ -0,0 +1,133 @@ +# TCI + + +## Tile Operation Diagram + +![TCI tile operation](../figures/isa/TCI.svg) + +## Introduction + +Generate a contiguous integer sequence into a destination tile. + +## Math Interpretation + +For a linearized index `k` over the valid elements: + +- Ascending: + + $$ \mathrm{dst}_{k} = S + k $$ + +- Descending: + + $$ \mathrm{dst}_{k} = S - k $$ + +The linearization order depends on the tile layout (implementation-defined). + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = tci %S {descending = false} : !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tci %scalar {descending = false} : dtype -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tci ins(%scalar {descending = false} : dtype) outs(%dst : !pto.tile_buf<...>) +``` + +### IR Level 1 (SSA) + +```text +%dst = pto.tci %scalar {descending = false} : dtype -> !pto.tile<...> +``` + +### IR Level 2 (DPS) + +```text +pto.tci ins(%scalar {descending = false} : dtype) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TCI(TileData &dst, T start, WaitEvents &... events); +``` + +## Constraints + +- **Implementation checks (A2A3/A5)**: + - `TileData::DType` must be exactly the same type as the scalar template parameter `T`. + - `dst/scalar` element types must be identical, and must be one of: `int32_t`, `uint32_t`, `int16_t`, `uint16_t`. + - `TileData::Cols != 1` (this is the condition enforced by the implementation). +- **Valid region**: + - The implementation uses `dst.GetValidCol()` as the sequence length and does not consult `dst.GetValidRow()`. + +## Examples + +### Auto + +```cpp +#include + +using namespace pto; + +void example_auto() { + using TileT = Tile; + TileT dst; + TCI(dst, /*S=*/0); +} +``` + +### Manual + +```cpp +#include + +using namespace pto; + +void example_manual() { + using TileT = Tile; + TileT dst; + TASSIGN(dst, 0x1000); + TCI(dst, /*S=*/100); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.tci %scalar {descending = false} : dtype -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tci %scalar {descending = false} : dtype -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = tci %S {descending = false} : !pto.tile<...> +# AS Level 2 (DPS) +pto.tci ins(%scalar {descending = false} : dtype) outs(%dst : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TCI_zh.md b/designs/outerCube/PTOISA/TCI_zh.md new file mode 100644 index 00000000..ba405600 --- /dev/null +++ b/designs/outerCube/PTOISA/TCI_zh.md @@ -0,0 +1,106 @@ +# TCI + +## 指令示意图 + +![TCI tile operation](../figures/isa/TCI.svg) + +## 简介 + +生成连续整数序列到目标 Tile 中。 + +## 数学语义 + +For a linearized index `k` over the valid elements: + +- Ascending: + + $$ \mathrm{dst}_{k} = S + k $$ + +- Descending: + + $$ \mathrm{dst}_{k} = S - k $$ + +The linearization order depends on the tile layout (implementation-defined). + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS Specification](../assembly/PTO-AS.md). + +同步形式： + +```text +%dst = tci %S {descending = false} : !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tci %scalar {descending = false} : dtype -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tci ins(%scalar {descending = false} : dtype) outs(%dst : !pto.tile_buf<...>) +``` + +### AS Level 1（SSA） + +```text +%dst = pto.tci %scalar {descending = false} : dtype -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.tci ins(%scalar {descending = false} : dtype) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TCI(TileData &dst, T start, WaitEvents &... events); +``` + +## 约束 + +- **实现检查 (A2A3/A5)**: + - `TileData::DType` must be exactly the same type as the scalar template parameter `T`. + - `dst/scalar` element types must be identical, and must be one of: `int32_t`, `uint32_t`, `int16_t`, `uint16_t`. + - `TileData::Cols != 1` (this is the condition enforced by the implementation). +- **有效区域**: + - The implementation uses `dst.GetValidCol()` as the sequence length and does not consult `dst.GetValidRow()`. + +## 示例 + +### 自动（Auto） + +```cpp +#include + +using namespace pto; + +void example_auto() { + using TileT = Tile; + TileT dst; + TCI(dst, /*S=*/0); +} +``` + +### 手动（Manual） + +```cpp +#include + +using namespace pto; + +void example_manual() { + using TileT = Tile; + TileT dst; + TASSIGN(dst, 0x1000); + TCI(dst, /*S=*/100); +} +``` diff --git a/designs/outerCube/PTOISA/TCMP.md b/designs/outerCube/PTOISA/TCMP.md new file mode 100644 index 00000000..8e6db2f0 --- /dev/null +++ b/designs/outerCube/PTOISA/TCMP.md @@ -0,0 +1,142 @@ +# TCMP + + +## Tile Operation Diagram + +![TCMP tile operation](../figures/isa/TCMP.svg) + +## Introduction + +Compare two tiles and write a packed predicate mask. + +## Math Interpretation + +Conceptually, for each element `(i, j)` in the valid region, define a predicate: + +$$ p_{i,j} = \left(\mathrm{src0}_{i,j}\ \mathrm{cmpMode}\ \mathrm{src1}_{i,j}\right) $$ + +The predicate mask is stored in `dst` using an implementation-defined packed layout. + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = tcmp %src0, %src1 {cmpMode = #pto.cmp} : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tcmp %src0, %src1{cmpMode = #pto}: (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tcmp ins(%src0, %src1{cmpMode = #pto}: !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### IR Level 1 (SSA) + +```text +%dst = pto.tcmp %src0, %src1{cmpMode = #pto}: (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### IR Level 2 (DPS) + +```text +pto.tcmp ins(%src0, %src1{cmpMode = #pto}: !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp` and `include/pto/common/type.hpp`: + +```cpp +template +PTO_INST RecordEvent TCMP(TileDataDst &dst, TileDataSrc &src0, TileDataSrc &src1, CmpMode cmpMode, WaitEvents &... events); +``` + +## Constraints + +- **Implementation checks (A2A3)**: + - Input type must be one of: `int32_t`, `half`, `float`. + - Output type must be `uint8_t`. + - `src0/src1/dst` tile location must be `TileType::Vec`. + - Static valid bounds: `TileDataSrc::ValidRow <= TileDataSrc::Rows` and `TileDataSrc::ValidCol <= TileDataSrc::Cols`. + - Runtime: `src0.GetValidRow() == dst.GetValidRow()` and `src0.GetValidCol() == dst.GetValidCol()`. + - Note: `src1` shape/valid is not validated by explicit runtime assertions in this implementation. + - For `TileDataSrc::DType == int32_t`, the implementation uses the `EQ` compare path regardless of `cmpMode`. +- **Implementation checks (A5)**: + - Input type must be one of: `uint32_t`, `int32_t`, `uint16_t`, `int16_t`, `uint8_t`, `int8_t`, `float`, `half`. + - Output type must be `uint32_t`. + - Implemented (see `include/pto/npu/a5/TCmp.hpp`). + - The A5 implementation uses `dst.GetValidRow()` / `dst.GetValidCol()` as the iteration domain and writes a packed predicate mask into `dst` (target-defined packing). +- **Mask encoding**: + - The mask tile is interpreted as packed predicate bits in a target-defined layout. + +## Examples + +### Auto + +```cpp +#include + +using namespace pto; + +void example_auto() { + using SrcT = Tile; + using MaskT = Tile; + SrcT src0, src1; + MaskT mask(16, 2); + TCMP(mask, src0, src1, CmpMode::GT); +} +``` + +### Manual + +```cpp +#include + +using namespace pto; + +void example_manual() { + using SrcT = Tile; + using MaskT = Tile; + SrcT src0, src1; + MaskT mask(16, 2); + TASSIGN(src0, 0x1000); + TASSIGN(src1, 0x2000); + TASSIGN(mask, 0x3000); + TCMP(mask, src0, src1, CmpMode::GT); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.tcmp %src0, %src1{cmpMode = #pto}: (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tcmp %src0, %src1{cmpMode = #pto}: (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = tcmp %src0, %src1 {cmpMode = #pto.cmp} : !pto.tile<...> -> !pto.tile<...> +# AS Level 2 (DPS) +pto.tcmp ins(%src0, %src1{cmpMode = #pto}: !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TCMPS.md b/designs/outerCube/PTOISA/TCMPS.md new file mode 100644 index 00000000..d3d199f6 --- /dev/null +++ b/designs/outerCube/PTOISA/TCMPS.md @@ -0,0 +1,140 @@ +# TCMPS + + +## Tile Operation Diagram + +![TCMPS tile operation](../figures/isa/TCMPS.svg) + +## Introduction + +Compare a tile against a scalar and write per-element comparison results. + +## Math Interpretation + +For each element `(i, j)` in the valid region: + +$$ \mathrm{dst}_{i,j} = \left(\mathrm{src}_{i,j}\ \mathrm{cmpMode}\ \mathrm{scalar}\right) $$ + +The encoding/type of `dst` is implementation-defined (often a mask-like tile). + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = tcmps %src, %scalar {cmpMode = #pto.cmp} : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tcmps %src, %scalar {cmpMode = #pto} : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tcmps ins(%src, %scalar{cmpMode = #pto}: !pto.tile_buf<...>, dtype) outs(%dst : !pto.tile_buf<...>) +``` + +### IR Level 1 (SSA) + +```text +%dst = pto.tcmps %src, %scalar {cmpMode = #pto} : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### IR Level 2 (DPS) + +```text +pto.tcmps ins(%src, %scalar{cmpMode = #pto}: !pto.tile_buf<...>, dtype) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp` and `include/pto/common/type.hpp`: + +```cpp +template +PTO_INST RecordEvent TCMPS(TileDataDst& dst, TileDataSrc0& src0, T src1, CmpMode cmpMode, WaitEvents&... events); +``` + +## Constraints + +- **Implementation checks (A2A3)**: + - `TileData::DType` must be one of: `int32_t`, `float`, `half`, `uint16_t`, `int16_t`. + - Tile layout must be row-major (`TileData::isRowMajor`). +- **Implementation checks (A5)**: + - `TileData::DType` must be one of: `int32_t`, `float`, `half`, `uint16_t`, `int16_t`. + - Tile layout must be row-major (`TileData::isRowMajor`). +- **Common constraints**: + - Tile location must be vector (`TileData::Loc == TileType::Vec`). + - Static valid bounds: `TileData::ValidRow <= TileData::Rows` and `TileData::ValidCol <= TileData::Cols`. + - Runtime: `src0` and `dst` must have the same valid row/col. +- **Valid region**: + - The op uses `dst.GetValidRow()` / `dst.GetValidCol()` as the iteration domain. +- **Comparison modes**: + - Supports `CmpMode::EQ`, `CmpMode::NE`, `CmpMode::LT`, `CmpMode::GT`, `CmpMode::LE`, `CmpMode::GE`. + +## Examples + +### Auto + +```cpp +#include + +using namespace pto; + +void example_auto() { + using SrcT = Tile; + using DstT = Tile; + SrcT src; + DstT dst(16, 2); + TCMPS(dst, src, 0.0f, CmpMode::GT); +} +``` + +### Manual + +```cpp +#include + +using namespace pto; + +void example_manual() { + using SrcT = Tile; + using DstT = Tile; + SrcT src; + DstT dst(16, 2); + TASSIGN(src, 0x1000); + TASSIGN(dst, 0x2000); + TCMPS(dst, src, 0.0f, CmpMode::GT); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.tcmps %src, %scalar {cmpMode = #pto} : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tcmps %src, %scalar {cmpMode = #pto} : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = tcmps %src, %scalar {cmpMode = #pto.cmp} : !pto.tile<...> -> !pto.tile<...> +# AS Level 2 (DPS) +pto.tcmps ins(%src, %scalar{cmpMode = #pto}: !pto.tile_buf<...>, dtype) outs(%dst : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TCMPS_zh.md b/designs/outerCube/PTOISA/TCMPS_zh.md new file mode 100644 index 00000000..a697b3e0 --- /dev/null +++ b/designs/outerCube/PTOISA/TCMPS_zh.md @@ -0,0 +1,113 @@ +# TCMPS + +## 指令示意图 + +![TCMPS tile operation](../figures/isa/TCMPS.svg) + +## 简介 + +将 Tile 与标量比较并写入逐元素比较结果。 + +## 数学语义 + +对每个元素 `(i, j)` 在有效区域内： + +$$ \mathrm{dst}_{i,j} = \left(\mathrm{src}_{i,j}\ \mathrm{cmpMode}\ \mathrm{scalar}\right) $$ + +The encoding/type of `dst` is implementation-defined (often a mask-like tile). + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS Specification](../assembly/PTO-AS.md). + +同步形式： + +```text +%dst = tcmps %src, %scalar {cmpMode = #pto.cmp} : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tcmps %src, %scalar {cmpMode = #pto} : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tcmps ins(%src, %scalar{cmpMode = #pto}: !pto.tile_buf<...>, dtype) outs(%dst : !pto.tile_buf<...>) +``` + +### AS Level 1（SSA） + +```text +%dst = pto.tcmps %src, %scalar {cmpMode = #pto} : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.tcmps ins(%src, %scalar{cmpMode = #pto}: !pto.tile_buf<...>, dtype) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp` and `include/pto/common/type.hpp`: + +```cpp +template +PTO_INST RecordEvent TCMPS(TileDataDst& dst, TileDataSrc0& src0, T src1, CmpMode cmpMode, WaitEvents&... events); +``` + +## 约束 + +- **实现检查 (A2A3)**: + - `TileData::DType` must be one of: `int32_t`, `float`, `half`, `uint16_t`, `int16_t`. + - Tile 布局 must be row-major (`TileData::isRowMajor`). +- **实现检查 (A5)**: + - `TileData::DType` must be one of: `int32_t`, `float`, `half`, `uint16_t`, `int16_t`. + - Tile 布局 must be row-major (`TileData::isRowMajor`). +- **Common constraints**: + - Tile location must be vector (`TileData::Loc == TileType::Vec`). + - Static valid bounds: `TileData::ValidRow <= TileData::Rows` and `TileData::ValidCol <= TileData::Cols`. + - Runtime: `src0` and `dst` must have the same valid row/col. +- **有效区域**: + - The op uses `dst.GetValidRow()` / `dst.GetValidCol()` as the iteration domain. +- **Comparison modes**: + - Supports `CmpMode::EQ`, `CmpMode::NE`, `CmpMode::LT`, `CmpMode::GT`, `CmpMode::LE`, `CmpMode::GE`. + +## 示例 + +### 自动（Auto） + +```cpp +#include + +using namespace pto; + +void example_auto() { + using SrcT = Tile; + using DstT = Tile; + SrcT src; + DstT dst(16, 2); + TCMPS(dst, src, 0.0f, CmpMode::GT); +} +``` + +### 手动（Manual） + +```cpp +#include + +using namespace pto; + +void example_manual() { + using SrcT = Tile; + using DstT = Tile; + SrcT src; + DstT dst(16, 2); + TASSIGN(src, 0x1000); + TASSIGN(dst, 0x2000); + TCMPS(dst, src, 0.0f, CmpMode::GT); +} +``` diff --git a/designs/outerCube/PTOISA/TCMP_zh.md b/designs/outerCube/PTOISA/TCMP_zh.md new file mode 100644 index 00000000..1d7b93dd --- /dev/null +++ b/designs/outerCube/PTOISA/TCMP_zh.md @@ -0,0 +1,115 @@ +# TCMP + +## 指令示意图 + +![TCMP tile operation](../figures/isa/TCMP.svg) + +## 简介 + +比较两个 Tile 并写入一个打包的谓词掩码。 + +## 数学语义 + +Conceptually, for each element `(i, j)` in the valid region, define a predicate: + +$$ p_{i,j} = \left(\mathrm{src0}_{i,j}\ \mathrm{cmpMode}\ \mathrm{src1}_{i,j}\right) $$ + +The predicate mask is stored in `dst` using an implementation-defined packed layout. + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS Specification](../assembly/PTO-AS.md). + +同步形式： + +```text +%dst = tcmp %src0, %src1 {cmpMode = #pto.cmp} : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tcmp %src0, %src1{cmpMode = #pto}: (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tcmp ins(%src0, %src1{cmpMode = #pto}: !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### AS Level 1（SSA） + +```text +%dst = pto.tcmp %src0, %src1{cmpMode = #pto}: (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.tcmp ins(%src0, %src1{cmpMode = #pto}: !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp` and `include/pto/common/type.hpp`: + +```cpp +template +PTO_INST RecordEvent TCMP(TileDataDst &dst, TileDataSrc &src0, TileDataSrc &src1, CmpMode cmpMode, WaitEvents &... events); +``` + +## 约束 + +- **实现检查 (A2A3)**: + - Input type must be one of: `int32_t`, `half`, `float`. + - Output type must be `uint8_t`. + - `src0/src1/dst` tile location must be `TileType::Vec`. + - Static valid bounds: `TileDataSrc::ValidRow <= TileDataSrc::Rows` and `TileDataSrc::ValidCol <= TileDataSrc::Cols`. + - Runtime: `src0.GetValidRow() == dst.GetValidRow()` and `src0.GetValidCol() == dst.GetValidCol()`. + - Note: `src1` shape/valid is not validated by explicit runtime assertions in this implementation. + - For `TileDataSrc::DType == int32_t`, the implementation uses the `EQ` compare path regardless of `cmpMode`. +- **实现检查 (A5)**: + - Input type must be one of: `uint32_t`, `int32_t`, `uint16_t`, `int16_t`, `uint8_t`, `int8_t`, `float`, `half`. + - Output type must be `uint32_t`. + - Implemented (see `include/pto/npu/a5/TCmp.hpp`). + - The A5 implementation uses `dst.GetValidRow()` / `dst.GetValidCol()` as the iteration domain and writes a packed predicate mask into `dst` (target-defined packing). +- **Mask encoding**: + - The mask tile is interpreted as packed predicate bits in a target-defined layout. + +## 示例 + +### 自动（Auto） + +```cpp +#include + +using namespace pto; + +void example_auto() { + using SrcT = Tile; + using MaskT = Tile; + SrcT src0, src1; + MaskT mask(16, 2); + TCMP(mask, src0, src1, CmpMode::GT); +} +``` + +### 手动（Manual） + +```cpp +#include + +using namespace pto; + +void example_manual() { + using SrcT = Tile; + using MaskT = Tile; + SrcT src0, src1; + MaskT mask(16, 2); + TASSIGN(src0, 0x1000); + TASSIGN(src1, 0x2000); + TASSIGN(mask, 0x3000); + TCMP(mask, src0, src1, CmpMode::GT); +} +``` diff --git a/designs/outerCube/PTOISA/TCOLARGMAX.md b/designs/outerCube/PTOISA/TCOLARGMAX.md new file mode 100644 index 00000000..a69a8a3c --- /dev/null +++ b/designs/outerCube/PTOISA/TCOLARGMAX.md @@ -0,0 +1,178 @@ +# TCOLARGMAX + + +## Tile Operation Diagram + +![TCOLARGMAX tile operation](../figures/isa/TCOLARGMAX.svg) + +## Introduction + +Get the row index of the maximum element for each column. + +## Math Interpretation + +Let `R = src.GetValidRow()` and `C = src.GetValidCol()`. For `0 <= j < C`: + +$$ \mathrm{dst}_{0,j} = \underset{0 \le i < R}{\operatorname{argmax}} \; \mathrm{src}_{i,j} $$ + +## Assembly Syntax + +PTO-AS form: see `docs/grammar/PTO-AS.md`. + +Synchronous form: + +```text +%dst = tcolargmax %src : !pto.tile<...> -> !pto.tile<...> +``` +Lowering may introduce internal scratch tiles; the C++ intrinsic requires an explicit `tmp` operand. + +### IR Level 1 (SSA) + +```text +%dst = pto.tcolargmax %src, %tmp : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### IR Level 2 (DPS) + +```text +pto.tcolargmax ins(%src, %tmp : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TCOLARGMAX(TileDataOut& dst, TileDataIn& src, TileDataTmp& tmp, WaitEvents&... events); +``` + +## Constraints + +Implementation checks (NPU): + +- A2A3: + - Tile location: `dst` and `src` must be `TileType::Vec`. + - Tile layout of `src`: ND fractal (`isRowMajor` and `SLayout::NoneBox`). + - Tile layout of `dst`: ND fractal (`isRowMajor` and `SLayout::NoneBox`). + - Source data types: `half`, `float`, `uint16_t`, `uint32_t`. + - Destination data types: `uint32_t` or `int32_t`. + - `tmp` data type must be consistent with `src` data type. + - Compile-time check: `src.ValidCol` must be `1` or `-1` (dynamic). + - Runtime valid checks: + - `srcValidCol != 0` and `srcValidRow != 0`. + - `dstValidRow == 1`. + - `srcValidCol == dstValidCol`. +- A5: + - Tile location: `dst` and `src` must be `TileType::Vec`. + - Tile layout of `src`: ND fractal (`isRowMajor` and `SLayout::NoneBox`). + - Tile layout of `dst`: ND fractal (`isRowMajor` and `SLayout::NoneBox`). + - Source data types: `int8_t`, `uint8_t`, `int16_t`, `uint16_t`, `int32_t`, `uint32_t`, `half`, `float`. + - Destination data types: `uint32_t` or `int32_t`. + - Compile-time check: `src.ValidCol` must be `1` or `-1` (dynamic). + - Runtime valid checks: + - `srcValidCol != 0` and `srcValidRow != 0`. + - `dstValidRow == 1`. + - `srcValidCol == dstValidCol`. + - `tmp` temporary tile is not used, only for compatibility. + +### About temporary tile `tmp` for A2A3 + +* `tmp` is always used in the A2A3 implementation as scratch space for intermediate results (current index, argmax index, and current max elements). +* `tmp` tile's data type must be the same as `src`'s data type. +* `tmp` tile is organized into three regions within a single row: + - Region 0 (`[0, tmpGapEles)`): current row index counter (incremented per row). + - Region 1 (`[tmpGapEles, 2 * tmpGapEles)`): current maximum elements for comparison. + - Region 2 (`[2 * tmpGapEles, 3 * tmpGapEles)`): argmax index result (before final conversion to `dst`). +* `tmpGapEles` is determined as follows: + - When `srcValidCol >= elemPerRpt`: `tmpGapEles = elemPerRpt`. + - When `srcValidCol < elemPerRpt`: `tmpGapEles = ceil(srcValidCol / elemPerBlock) * elemPerBlock`. +* Simply set `tmp` tile size the same as `src` when `src` is small, or calculate the required stride based on `src`'s `validCol` using the following formula: + +```text +repeats = ceil(validCol / elementPerRepeat) +stride = ceil(repeats * 2 / elementPerBlock) * elementPerBlock + ceil(repeats / elementPerBlock) * elementPerBlock +``` + +### About temporary tile `tmp` for A5 + +* `tmp` temporary tile is **not used** in the A5 implementation. The A5 uses vector register-based computation (`__VEC_SCOPE__`) and does not require scratch tile storage. +* `tmp` is retained in the C++ intrinsic signature solely for API compatibility with A2A3. + +## Examples + +### Auto + +```cpp +#include + +using namespace pto; + +void example_auto() { + using SrcT = Tile; + using DstT = Tile; + using TmpT = Tile; + SrcT src(16, 255); + DstT dst(1, 255); + TmpT tmp(1, 32); + TCOLARGMAX(dst, src, tmp); +} +``` + +### Manual + +```cpp +#include + +using namespace pto; + +void example_manual() { + using SrcT = Tile; + using DstT = Tile; + using TmpT = Tile; + SrcT src(16, 255); + DstT dst(1, 255); + TmpT tmp(1, 32); + TASSIGN(src, 0x0); + TASSIGN(dst, 0x1000); + TASSIGN(tmp, 0x2000); + TCOLARGMAX(dst, src, tmp); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.tcolargmax %src, %tmp : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tcolargmax %src, %tmp : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = tcolargmax %src : !pto.tile<...> -> !pto.tile<...> +# IR Level 2 (DPS) +pto.tcolargmax ins(%src, %tmp : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +- [x] Explore existing docs/isa for documentation style and format +- [x] Read tcolargmax and tcolargmin A2A3 implementation in include/ +- [x] Read tcolargmax and tcolargmin A5 implementation in include/ +- [x] Read test cases for tcolargmax and tcolargmin +- [x] Understand A2A3 vs A5 differences and tmp handling +- [x] Write tcolargmax English documentation (docs/isa/TCOLARGMAX.md) +- [ ] Write tcolargmax Chinese documentation (docs/isa/TCOLARGMAX_zh.md) +- [ ] Verify documentation completeness and accuracy + + \ No newline at end of file diff --git a/designs/outerCube/PTOISA/TCOLARGMAX_zh.md b/designs/outerCube/PTOISA/TCOLARGMAX_zh.md new file mode 100644 index 00000000..91268287 --- /dev/null +++ b/designs/outerCube/PTOISA/TCOLARGMAX_zh.md @@ -0,0 +1,178 @@ +# TCOLARGMAX + +## 指令示意图 + +![TCOLARGMAX tile operation](../figures/isa/TCOLARGMAX.svg) + +## 简介 + +获取每列最大值对应行索引。 + +## 数学语义 + +Let `R = src.GetValidRow()` and `C = src.GetValidCol()`. For `0 <= j < C`: + +$$ \mathrm{dst}_{0,j} = \underset{0 \le i < R}{\operatorname{argmax}} \; \mathrm{src}_{i,j} $$ + +## 汇编语法 + +PTO-AS 形式：参见 `docs/grammar/PTO-AS.md`. + +同步形式： + +```text +%dst = tcolargmax %src : !pto.tile<...> -> !pto.tile<...> +``` +Lowering may introduce internal scratch tiles; the C++ intrinsic requires an explicit `tmp` operand. + +### IR Level 1（SSA） + +```text +%dst = pto.tcolargmax %src, %tmp : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### IR Level 2（DPS） + +```text +pto.tcolargmax ins(%src, %tmp : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TCOLARGMAX(TileDataOut& dst, TileDataIn& src, TileDataTmp& tmp, WaitEvents&... events); +``` + +## 约束 + +实现检查 (NPU): + +- A2A3: + - Tile location: `dst` 和 `src` 必须为 `TileType::Vec`。 + - Tile 布局 of `src`: ND fractal (`isRowMajor` and `SLayout::NoneBox`)。 + - Tile 布局 of `dst`: ND fractal (`isRowMajor` and `SLayout::NoneBox`)。 + - 源数据类型: `half`、`float`、`uint16_t`、`uint32_t`。 + - 目标数据类型: `uint32_t` 或 `int32_t`。 + - `tmp` 数据类型必须与 `src` 数据类型一致。 + - 编译期检查: `src.ValidCol` 必须为 `1` 或 `-1`（动态）。 + - 运行期有效区域检查: + - `srcValidCol != 0` 且 `srcValidRow != 0`。 + - `dstValidRow == 1`。 + - `srcValidCol == dstValidCol`。 +- A5: + - Tile location: `dst` 和 `src` 必须为 `TileType::Vec`。 + - Tile 布局 of `src`: ND fractal (`isRowMajor` and `SLayout::NoneBox`)。 + - Tile 布局 of `dst`: ND fractal (`isRowMajor` and `SLayout::NoneBox`)。 + - 源数据类型: `int8_t`、`uint8_t`、`int16_t`、`uint16_t`、`int32_t`、`uint32_t`、`half`、`float`。 + - 目标数据类型: `uint32_t` 或 `int32_t`。 + - 编译期检查: `src.ValidCol` 必须为 `1` 或 `-1`（动态）。 + - 运行期有效区域检查: + - `srcValidCol != 0` 且 `srcValidRow != 0`。 + - `dstValidRow == 1`。 + - `srcValidCol == dstValidCol`。 + - `tmp` 临时 Tile 不使用，仅做兼容。 + +### A2A3 `tmp` 临时 Tile 相关说明 + +* A2A3 实现中 `tmp` **始终被使用**，作为中间结果的临时存储空间（当前行索引、argmax 索引、当前最大值元素）。 +* `tmp` Tile 的数据类型必须与 `src` 的数据类型一致。 +* `tmp` Tile 在单行内被划分为三个区域： + - 区域 0（`[0, tmpGapEles)`）：当前行索引计数器（每行递增）。 + - 区域 1（`[tmpGapEles, 2 * tmpGapEles)`）：当前最大值元素，用于比较。 + - 区域 2（`[2 * tmpGapEles, 3 * tmpGapEles)`）：argmax 索引结果（最终转换后写入 `dst`）。 +* `tmpGapEles` 的确定方式： + - 当 `srcValidCol >= elemPerRpt` 时：`tmpGapEles = elemPerRpt`。 + - 当 `srcValidCol < elemPerRpt` 时：`tmpGapEles = ceil(srcValidCol / elemPerBlock) * elemPerBlock`。 +* 当 `src` 较小时，可直接将 `tmp` Tile 大小设为与 `src` 相同；也可按以下公式根据 `src` 的 `validCol` 算出 `tmp` Tile 所需 stride： + +```text +repeats = ceil(validCol / elementPerRepeat) +stride = ceil(repeats * 2 / elementPerBlock) * elementPerBlock + ceil(repeats / elementPerBlock) * elementPerBlock +``` + +### A5 `tmp` 临时 Tile 相关说明 + +* A5 实现中 `tmp` 临时 Tile **不使用**。A5 使用基于向量寄存器的计算方式（`__VEC_SCOPE__`），不需要临时 Tile 存储。 +* `tmp` 在 C++ 内建接口签名中保留，仅为了与 A2A3 的 API 兼容。 + +## 示例 + +### 自动（Auto） + +```cpp +#include + +using namespace pto; + +void example_auto() { + using SrcT = Tile; + using DstT = Tile; + using TmpT = Tile; + SrcT src(16, 255); + DstT dst(1, 255); + TmpT tmp(1, 32); + TCOLARGMAX(dst, src, tmp); +} +``` + +### 手动（Manual） + +```cpp +#include + +using namespace pto; + +void example_manual() { + using SrcT = Tile; + using DstT = Tile; + using TmpT = Tile; + SrcT src(16, 255); + DstT dst(1, 255); + TmpT tmp(1, 32); + TASSIGN(src, 0x0); + TASSIGN(dst, 0x1000); + TASSIGN(tmp, 0x2000); + TCOLARGMAX(dst, src, tmp); +} +``` + +## 汇编示例（ASM） + +### 自动模式 + +```text +# 自动模式：由编译器/运行时负责资源放置与调度。 +%dst = pto.tcolargmax %src, %tmp : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### 手动模式 + +```text +# 手动模式：先显式绑定资源，再发射指令。 +# 可选（当该指令包含 tile 操作数时）： +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tcolargmax %src, %tmp : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### PTO 汇编形式 + +```text +%dst = tcolargmax %src : !pto.tile<...> -> !pto.tile<...> +# IR Level 2 (DPS) +pto.tcolargmax ins(%src, %tmp : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +- [x] Explore existing docs/isa for documentation style and format +- [x] Read tcolargmax and tcolargmin A2A3 implementation in include/ +- [x] Read tcolargmax and tcolargmin A5 implementation in include/ +- [x] Read test cases for tcolargmax and tcolargmin +- [x] Understand A2A3 vs A5 differences and tmp handling +- [x] Write tcolargmax English documentation (docs/isa/TCOLARGMAX.md) +- [x] Write tcolargmax Chinese documentation (docs/isa/TCOLARGMAX_zh.md) +- [ ] Verify documentation completeness and accuracy + + \ No newline at end of file diff --git a/designs/outerCube/PTOISA/TCOLARGMIN.md b/designs/outerCube/PTOISA/TCOLARGMIN.md new file mode 100644 index 00000000..63df789f --- /dev/null +++ b/designs/outerCube/PTOISA/TCOLARGMIN.md @@ -0,0 +1,172 @@ +# TCOLARGMIN + + +## Tile Operation Diagram + +![TCOLARGMIN tile operation](../figures/isa/TCOLARGMIN.svg) + +## Introduction + +Get the row index of the minimum element for each column. + +## Math Interpretation + +Let `R = src.GetValidRow()` and `C = src.GetValidCol()`. For `0 <= j < C`: + +$$ \mathrm{dst}_{0,j} = \underset{0 \le i < R}{\operatorname{argmin}} \; \mathrm{src}_{i,j} $$ + +## Assembly Syntax + +PTO-AS form: see `docs/grammar/PTO-AS.md`. + +Synchronous form: + +```text +%dst = tcolargmin %src : !pto.tile<...> -> !pto.tile<...> +``` +Lowering may introduce internal scratch tiles; the C++ intrinsic requires an explicit `tmp` operand. + +### IR Level 1 (SSA) + +```text +%dst = pto.tcolargmin %src, %tmp : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### IR Level 2 (DPS) + +```text +pto.tcolargmin ins(%src, %tmp : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TCOLARGMIN(TileDataOut& dst, TileDataIn& src, TileDataTmp& tmp, WaitEvents&... events); +``` + +## Constraints + +Implementation checks (NPU): + +- A2A3: + - Tile location: `dst` and `src` must be `TileType::Vec`. + - Tile layout of `src`: ND fractal (`isRowMajor` and `SLayout::NoneBox`). + - Tile layout of `dst`: ND fractal (`isRowMajor` and `SLayout::NoneBox`). + - Source data types: `half`, `float`, `uint16_t`, `uint32_t`. + - Destination data types: `uint32_t` or `int32_t`. + - `tmp` data type must be consistent with `src` data type. + - Compile-time check: `src.ValidCol` must be `1` or `-1` (dynamic). + - Runtime valid checks: + - `srcValidCol != 0` and `srcValidRow != 0`. + - `dstValidRow == 1`. + - `srcValidCol == dstValidCol`. +- A5: + - Tile location: `dst` and `src` must be `TileType::Vec`. + - Tile layout of `src`: ND fractal (`isRowMajor` and `SLayout::NoneBox`). + - Tile layout of `dst`: ND fractal (`isRowMajor` and `SLayout::NoneBox`). + - Source data types: `int8_t`, `uint8_t`, `int16_t`, `uint16_t`, `int32_t`, `uint32_t`, `half`, `float`. + - Destination data types: `uint32_t` or `int32_t`. + - Compile-time check: `src.ValidCol` must be `1` or `-1` (dynamic). + - Runtime valid checks: + - `srcValidCol != 0` and `srcValidRow != 0`. + - `dstValidRow == 1`. + - `srcValidCol == dstValidCol`. + - `tmp` temporary tile is not used, only for compatibility. + +### About temporary tile `tmp` for A2A3 + +* `tmp` is always used in the A2A3 implementation as scratch space for intermediate results (current index, argmin index, and current min elements). +* `tmp` tile's data type must be the same as `src`'s data type. +* `tmp` tile is organized into three regions within a single row: + - Region 0 (`[0, tmpGapEles)`): current row index counter (incremented per row). + - Region 1 (`[tmpGapEles, 2 * tmpGapEles)`): current minimum elements for comparison. + - Region 2 (`[2 * tmpGapEles, 3 * tmpGapEles)`): argmin index result (before final conversion to `dst`). +* `tmpGapEles` is determined as follows: + - When `srcValidCol >= elemPerRpt`: `tmpGapEles = elemPerRpt`. + - When `srcValidCol < elemPerRpt`: `tmpGapEles = ceil(srcValidCol / elemPerBlock) * elemPerBlock`. +* Simply set `tmp` tile size the same as `src` when `src` is small, or calculate the required stride based on `src`'s `validCol` using the following formula: + +```text +repeats = ceil(validCol / elementPerRepeat) +stride = ceil(repeats * 2 / elementPerBlock) * elementPerBlock + ceil(repeats / elementPerBlock) * elementPerBlock +``` + +### About temporary tile `tmp` for A5 + +* `tmp` temporary tile is **not used** in the A5 implementation. The A5 uses vector register-based computation (`__VEC_SCOPE__`) and does not require scratch tile storage. +* `tmp` is retained in the C++ intrinsic signature solely for API compatibility with A2A3. + +## Examples + +### Auto + +```cpp +#include + +using namespace pto; + +void example_auto() { + using SrcT = Tile; + using DstT = Tile; + using TmpT = Tile; + SrcT src(16, 255); + DstT dst(1, 255); + TmpT tmp(1, 32); + TCOLARGMIN(dst, src, tmp); +} +``` + +### Manual + +```cpp +#include + +using namespace pto; + +void example_manual() { + using SrcT = Tile; + using DstT = Tile; + using TmpT = Tile; + SrcT src(16, 255); + DstT dst(1, 255); + TmpT tmp(1, 32); + TASSIGN(src, 0x0); + TASSIGN(dst, 0x1000); + TASSIGN(tmp, 0x2000); + TCOLARGMIN(dst, src, tmp); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.tcolargmin %src, %tmp : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tcolargmin %src, %tmp : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = tcolargmin %src : !pto.tile<...> -> !pto.tile<...> +# IR Level 2 (DPS) +pto.tcolargmin ins(%src, %tmp : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +- [x] Write tcolargmin English documentation (docs/isa/TCOLARGMIN.md) +- [ ] Write tcolargmin Chinese documentation (docs/isa/TCOLARGMIN_zh.md) + + \ No newline at end of file diff --git a/designs/outerCube/PTOISA/TCOLARGMIN_zh.md b/designs/outerCube/PTOISA/TCOLARGMIN_zh.md new file mode 100644 index 00000000..33fe2a24 --- /dev/null +++ b/designs/outerCube/PTOISA/TCOLARGMIN_zh.md @@ -0,0 +1,172 @@ +# TCOLARGMIN + +## 指令示意图 + +![TCOLARGMIN tile operation](../figures/isa/TCOLARGMIN.svg) + +## 简介 + +获取每列最小值对应行索引。 + +## 数学语义 + +Let `R = src.GetValidRow()` and `C = src.GetValidCol()`. For `0 <= j < C`: + +$$ \mathrm{dst}_{0,j} = \underset{0 \le i < R}{\operatorname{argmin}} \; \mathrm{src}_{i,j} $$ + +## 汇编语法 + +PTO-AS 形式：参见 `docs/grammar/PTO-AS.md`. + +同步形式： + +```text +%dst = tcolargmin %src : !pto.tile<...> -> !pto.tile<...> +``` +Lowering may introduce internal scratch tiles; the C++ intrinsic requires an explicit `tmp` operand. + +### IR Level 1（SSA） + +```text +%dst = pto.tcolargmin %src, %tmp : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### IR Level 2（DPS） + +```text +pto.tcolargmin ins(%src, %tmp : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TCOLARGMIN(TileDataOut& dst, TileDataIn& src, TileDataTmp& tmp, WaitEvents&... events); +``` + +## 约束 + +实现检查 (NPU): + +- A2A3: + - Tile location: `dst` 和 `src` 必须为 `TileType::Vec`。 + - Tile 布局 of `src`: ND fractal (`isRowMajor` and `SLayout::NoneBox`)。 + - Tile 布局 of `dst`: ND fractal (`isRowMajor` and `SLayout::NoneBox`)。 + - 源数据类型: `half`、`float`、`uint16_t`、`uint32_t`。 + - 目标数据类型: `uint32_t` 或 `int32_t`。 + - `tmp` 数据类型必须与 `src` 数据类型一致。 + - 编译期检查: `src.ValidCol` 必须为 `1` 或 `-1`（动态）。 + - 运行期有效区域检查: + - `srcValidCol != 0` 且 `srcValidRow != 0`。 + - `dstValidRow == 1`。 + - `srcValidCol == dstValidCol`。 +- A5: + - Tile location: `dst` 和 `src` 必须为 `TileType::Vec`。 + - Tile 布局 of `src`: ND fractal (`isRowMajor` and `SLayout::NoneBox`)。 + - Tile 布局 of `dst`: ND fractal (`isRowMajor` and `SLayout::NoneBox`)。 + - 源数据类型: `int8_t`、`uint8_t`、`int16_t`、`uint16_t`、`int32_t`、`uint32_t`、`half`、`float`。 + - 目标数据类型: `uint32_t` 或 `int32_t`。 + - 编译期检查: `src.ValidCol` 必须为 `1` 或 `-1`（动态）。 + - 运行期有效区域检查: + - `srcValidCol != 0` 且 `srcValidRow != 0`。 + - `dstValidRow == 1`。 + - `srcValidCol == dstValidCol`。 + - `tmp` 临时 Tile 不使用，仅做兼容。 + +### A2A3 `tmp` 临时 Tile 相关说明 + +* A2A3 实现中 `tmp` **始终被使用**，作为中间结果的临时存储空间（当前行索引、argmin 索引、当前最小值元素）。 +* `tmp` Tile 的数据类型必须与 `src` 的数据类型一致。 +* `tmp` Tile 在单行内被划分为三个区域： + - 区域 0（`[0, tmpGapEles)`）：当前行索引计数器（每行递增）。 + - 区域 1（`[tmpGapEles, 2 * tmpGapEles)`）：当前最小值元素，用于比较。 + - 区域 2（`[2 * tmpGapEles, 3 * tmpGapEles)`）：argmin 索引结果（最终转换后写入 `dst`）。 +* `tmpGapEles` 的确定方式： + - 当 `srcValidCol >= elemPerRpt` 时：`tmpGapEles = elemPerRpt`。 + - 当 `srcValidCol < elemPerRpt` 时：`tmpGapEles = ceil(srcValidCol / elemPerBlock) * elemPerBlock`。 +* 当 `src` 较小时，可直接将 `tmp` Tile 大小设为与 `src` 相同；也可按以下公式根据 `src` 的 `validCol` 算出 `tmp` Tile 所需 stride： + +```text +repeats = ceil(validCol / elementPerRepeat) +stride = ceil(repeats * 2 / elementPerBlock) * elementPerBlock + ceil(repeats / elementPerBlock) * elementPerBlock +``` + +### A5 `tmp` 临时 Tile 相关说明 + +* A5 实现中 `tmp` 临时 Tile **不使用**。A5 使用基于向量寄存器的计算方式（`__VEC_SCOPE__`），不需要临时 Tile 存储。 +* `tmp` 在 C++ 内建接口签名中保留，仅为了与 A2A3 的 API 兼容。 + +## 示例 + +### 自动（Auto） + +```cpp +#include + +using namespace pto; + +void example_auto() { + using SrcT = Tile; + using DstT = Tile; + using TmpT = Tile; + SrcT src(16, 255); + DstT dst(1, 255); + TmpT tmp(1, 32); + TCOLARGMIN(dst, src, tmp); +} +``` + +### 手动（Manual） + +```cpp +#include + +using namespace pto; + +void example_manual() { + using SrcT = Tile; + using DstT = Tile; + using TmpT = Tile; + SrcT src(16, 255); + DstT dst(1, 255); + TmpT tmp(1, 32); + TASSIGN(src, 0x0); + TASSIGN(dst, 0x1000); + TASSIGN(tmp, 0x2000); + TCOLARGMIN(dst, src, tmp); +} +``` + +## 汇编示例（ASM） + +### 自动模式 + +```text +# 自动模式：由编译器/运行时负责资源放置与调度。 +%dst = pto.tcolargmin %src, %tmp : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### 手动模式 + +```text +# 手动模式：先显式绑定资源，再发射指令。 +# 可选（当该指令包含 tile 操作数时）： +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tcolargmin %src, %tmp : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### PTO 汇编形式 + +```text +%dst = tcolargmin %src : !pto.tile<...> -> !pto.tile<...> +# IR Level 2 (DPS) +pto.tcolargmin ins(%src, %tmp : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +- [x] Write tcolargmin English documentation (docs/isa/TCOLARGMIN.md) +- [x] Write tcolargmin Chinese documentation (docs/isa/TCOLARGMIN_zh.md) + + \ No newline at end of file diff --git a/designs/outerCube/PTOISA/TCOLEXPAND.md b/designs/outerCube/PTOISA/TCOLEXPAND.md new file mode 100644 index 00000000..6ccf4b10 --- /dev/null +++ b/designs/outerCube/PTOISA/TCOLEXPAND.md @@ -0,0 +1,103 @@ +# TCOLEXPAND + + +## Tile Operation Diagram + +![TCOLEXPAND tile operation](../figures/isa/TCOLEXPAND.svg) + +## Introduction + +Broadcast the first element of each source column across the destination column. + +## Math Interpretation + +Let `R = dst.GetValidRow()` and `C = dst.GetValidCol()`. For `0 <= i < R` and `0 <= j < C`: + +$$ \mathrm{dst}_{i,j} = \mathrm{src}_{0,j} $$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = tcolexpand %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tcolexpand %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tcolexpand ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### IR Level 1 (SSA) + +```text +%dst = pto.tcolexpand %src : !pto.tile<...> -> !pto.tile<...> +``` + +### IR Level 2 (DPS) + +```text +pto.tcolexpand ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TCOLEXPAND(TileDataDst &dst, TileDataSrc &src, WaitEvents &... events); +``` + +## Constraints + +- The op iterates over `dst.GetValidRow()` / `dst.GetValidCol()`. + +## Examples + +```cpp +#include + +using namespace pto; + +void example() { + using TileT = Tile; + TileT src, dst; + TCOLEXPAND(dst, src); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.tcolexpand %src : !pto.tile<...> -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tcolexpand %src : !pto.tile<...> -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = tcolexpand %src : !pto.tile<...> -> !pto.tile<...> +# AS Level 2 (DPS) +pto.tcolexpand ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TCOLEXPANDADD.md b/designs/outerCube/PTOISA/TCOLEXPANDADD.md new file mode 100644 index 00000000..49b22407 --- /dev/null +++ b/designs/outerCube/PTOISA/TCOLEXPANDADD.md @@ -0,0 +1,89 @@ +# TCOLEXPANDADD + + +## Tile Operation Diagram + +![TCOLEXPANDADD tile operation](../figures/isa/TCOLEXPANDADD.svg) + +## Introduction + +Column-wise broadcast add: add each element of `src0` by a per-column scalar vector `src1`. + +## Math Interpretation + +Let `R = dst.GetValidRow()` and `C = dst.GetValidCol()`. Let `s_j` be the per-column scalar taken from `src1` (one value per column). + +For `0 <= i < R` and `0 <= j < C`: + +$$ +\mathrm{dst}_{i,j} = \mathrm{src0}_{i,j} + s_j +$$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = tcolexpandadd %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tcolexpandadd %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tcolexpandadd ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TCOLEXPANDADD(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, WaitEvents &... events); +``` + +## Constraints + +- `TileDataDst::DType`, `TileDataSrc1::DType` must be one of: `half`, `float`. +- Tile shape/layout constraint (compile-time): `TileDataDst::isRowMajor`. +- `src1` is expected to provide **one scalar per column** (i.e., its valid shape must cover `C` values). +- Exact layout/fractal constraints are target-specific; see backend headers under `include/pto/npu/*/TColExpand*.hpp`. + +## Examples + +See related examples in `docs/isa/` and `docs/coding/tutorials/`. + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.tcolexpandadd %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tcolexpandadd %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = tcolexpandadd %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +# AS Level 2 (DPS) +pto.tcolexpandadd ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/TCOLEXPANDADD_zh.md b/designs/outerCube/PTOISA/TCOLEXPANDADD_zh.md new file mode 100644 index 00000000..a4983a95 --- /dev/null +++ b/designs/outerCube/PTOISA/TCOLEXPANDADD_zh.md @@ -0,0 +1,89 @@ +# TCOLEXPANDADD + +## 指令示意图 + +![TCOLEXPANDADD tile operation](../figures/isa/TCOLEXPANDADD.svg) + +## 简介 + +列广播加法：对每一列加上每列标量向量。 + +## 数学语义 + +设 `R = dst.GetValidRow()` 和 `C = dst.GetValidCol()`。设 `s_j` 为从 `src1` 中获取的每列标量（每列一个值）。 + +对于 `0 <= i < R` 和 `0 <= j < C`： + +$$ +\mathrm{dst}_{i,j} = \mathrm{src0}_{i,j} + s_j +$$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS 规范](../assembly/PTO-AS_zh.md)。 + +同步形式： + +```text +%dst = tcolexpandadd %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 1（SSA） + +```text +%dst = pto.tcolexpandadd %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.tcolexpandadd ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`： + +```cpp +template +PTO_INST RecordEvent TCOLEXPANDADD(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, WaitEvents &... events); +``` + +## 约束 + +- `TileDataDst::DType`、`TileDataSrc1::DType` 必须是以下之一：`half`、`float`。 +- Tile 形状/布局约束（编译时）：`TileDataDst::isRowMajor`。 +- `src1` 预期提供**每列一个标量**（即，其有效形状必须覆盖 `C` 个值）。 +- 确切的布局/分形约束是目标特定的；参见 `include/pto/npu/*/TColExpand*.hpp` 下的后端头文件。 + +## 示例 + +参见 `docs/isa/` 和 `docs/coding/tutorials/` 中的相关示例。 + +## 汇编示例（ASM） + +### 自动模式 + +```text +# 自动模式：由编译器/运行时负责资源放置与调度。 +%dst = pto.tcolexpandadd %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### 手动模式 + +```text +# 手动模式：先显式绑定资源，再发射指令。 +# 可选（当该指令包含 tile 操作数时）： +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tcolexpandadd %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### PTO 汇编形式 + +```text +%dst = tcolexpandadd %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +# AS Level 2 (DPS) +pto.tcolexpandadd ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/TCOLEXPANDDIV.md b/designs/outerCube/PTOISA/TCOLEXPANDDIV.md new file mode 100644 index 00000000..6cc63a92 --- /dev/null +++ b/designs/outerCube/PTOISA/TCOLEXPANDDIV.md @@ -0,0 +1,89 @@ +# TCOLEXPANDDIV + + +## Tile Operation Diagram + +![TCOLEXPANDDIV tile operation](../figures/isa/TCOLEXPANDDIV.svg) + +## Introduction + +Column-wise broadcast divide: divide each element of `src0` by a per-column scalar vector `src1`. + +## Math Interpretation + +Let `R = dst.GetValidRow()` and `C = dst.GetValidCol()`. Let `s_j` be the per-column scalar taken from `src1` (one value per column). + +For `0 <= i < R` and `0 <= j < C`: + +$$ +\mathrm{dst}_{i,j} = \mathrm{src0}_{i,j} / s_j +$$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = tcolexpanddiv %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tcolexpanddiv %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tcolexpanddiv ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TCOLEXPANDDIV(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, WaitEvents &... events); +``` + +## Constraints + +- `TileDataDst::DType`, `TileDataSrc1::DType` must be one of: `half`, `float`. +- Tile shape/layout constraint (compile-time): `TileDataDst::isRowMajor`. +- `src1` is expected to provide **one scalar per column** (i.e., its valid shape must cover `C` values). +- Exact layout/fractal constraints are target-specific; see backend headers under `include/pto/npu/*/TColExpand*.hpp`. + +## Examples + +See related examples in `docs/isa/` and `docs/coding/tutorials/`. + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.tcolexpanddiv %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tcolexpanddiv %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = tcolexpanddiv %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +# AS Level 2 (DPS) +pto.tcolexpanddiv ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/TCOLEXPANDDIV_zh.md b/designs/outerCube/PTOISA/TCOLEXPANDDIV_zh.md new file mode 100644 index 00000000..8816edbd --- /dev/null +++ b/designs/outerCube/PTOISA/TCOLEXPANDDIV_zh.md @@ -0,0 +1,89 @@ +# TCOLEXPANDDIV + +## 指令示意图 + +![TCOLEXPANDDIV tile operation](../figures/isa/TCOLEXPANDDIV.svg) + +## 简介 + +列广播除法：将每一列除以一个每列标量向量。 + +## 数学语义 + +设 `R = dst.GetValidRow()` 和 `C = dst.GetValidCol()`。设 `s_j` 为从 `src1` 中获取的每列标量（每列一个值）。 + +对于 `0 <= i < R` 和 `0 <= j < C`： + +$$ +\mathrm{dst}_{i,j} = \mathrm{src0}_{i,j} / s_j +$$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS 规范](../assembly/PTO-AS_zh.md)。 + +同步形式： + +```text +%dst = tcolexpanddiv %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 1（SSA） + +```text +%dst = pto.tcolexpanddiv %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.tcolexpanddiv ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`： + +```cpp +template +PTO_INST RecordEvent TCOLEXPANDDIV(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, WaitEvents &... events); +``` + +## 约束 + +- `TileDataDst::DType`、`TileDataSrc1::DType` 必须是以下之一：`half`、`float`。 +- Tile 形状/布局约束（编译时）：`TileDataDst::isRowMajor`。 +- `src1` 预期提供**每列一个标量**（即，其有效形状必须覆盖 `C` 个值）。 +- 确切的布局/分形约束是目标特定的；参见 `include/pto/npu/*/TColExpand*.hpp` 下的后端头文件。 + +## 示例 + +参见 `docs/isa/` 和 `docs/coding/tutorials/` 中的相关示例。 + +## 汇编示例（ASM） + +### 自动模式 + +```text +# 自动模式：由编译器/运行时负责资源放置与调度。 +%dst = pto.tcolexpanddiv %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### 手动模式 + +```text +# 手动模式：先显式绑定资源，再发射指令。 +# 可选（当该指令包含 tile 操作数时）： +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tcolexpanddiv %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### PTO 汇编形式 + +```text +%dst = tcolexpanddiv %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +# AS Level 2 (DPS) +pto.tcolexpanddiv ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/TCOLEXPANDEXPDIF.md b/designs/outerCube/PTOISA/TCOLEXPANDEXPDIF.md new file mode 100644 index 00000000..ea7d54b0 --- /dev/null +++ b/designs/outerCube/PTOISA/TCOLEXPANDEXPDIF.md @@ -0,0 +1,89 @@ +# TCOLEXPANDEXPDIF + + +## Tile Operation Diagram + +![TCOLEXPANDEXPDIF tile operation](../figures/isa/TCOLEXPANDEXPDIF.svg) + +## Introduction + +Column-wise exp-diff: compute `exp(src0 - src1)` using a per-column scalar vector `src1`. + +## Math Interpretation + +Let `R = dst.GetValidRow()` and `C = dst.GetValidCol()`. Let `s_j` be the per-column scalar taken from `src1` (one value per column). + +For `0 <= i < R` and `0 <= j < C`: + +$$ +\mathrm{dst}_{i,j} = \exp(\mathrm{src0}_{i,j} - s_j) +$$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = tcolexpandexpdif %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tcolexpandexpdif %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tcolexpandexpdif ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TCOLEXPANDEXPDIF(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, WaitEvents &... events); +``` + +## Constraints + +- `TileDataDst::DType`, `TileDataSrc1::DType` must be one of: `half`, `float`. +- Tile shape/layout constraint (compile-time): `TileDataDst::isRowMajor`. +- `src1` is expected to provide **one scalar per column** (i.e., its valid shape must cover `C` values). +- Exact layout/fractal constraints are target-specific; see backend headers under `include/pto/npu/*/TColExpand*.hpp`. + +## Examples + +See related examples in `docs/isa/` and `docs/coding/tutorials/`. + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.tcolexpandexpdif %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tcolexpandexpdif %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = tcolexpandexpdif %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +# AS Level 2 (DPS) +pto.tcolexpandexpdif ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/TCOLEXPANDEXPDIF_zh.md b/designs/outerCube/PTOISA/TCOLEXPANDEXPDIF_zh.md new file mode 100644 index 00000000..b2fdc7ed --- /dev/null +++ b/designs/outerCube/PTOISA/TCOLEXPANDEXPDIF_zh.md @@ -0,0 +1,89 @@ +# TCOLEXPANDEXPDIF + +## 指令示意图 + +![TCOLEXPANDEXPDIF tile operation](../figures/isa/TCOLEXPANDEXPDIF.svg) + +## 简介 + +列指数差运算：计算 exp(src0 - src1)，其中 src1 为每列标量。 + +## 数学语义 + +设 `R = dst.GetValidRow()` 和 `C = dst.GetValidCol()`。设 `s_j` 为从 `src1` 中获取的每列标量（每列一个值）。 + +对于 `0 <= i < R` 和 `0 <= j < C`： + +$$ +\mathrm{dst}_{i,j} = \exp(\mathrm{src0}_{i,j} - s_j) +$$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS 规范](../assembly/PTO-AS_zh.md)。 + +同步形式： + +```text +%dst = tcolexpandexpdif %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 1（SSA） + +```text +%dst = pto.tcolexpandexpdif %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.tcolexpandexpdif ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`： + +```cpp +template +PTO_INST RecordEvent TCOLEXPANDEXPDIF(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, WaitEvents &... events); +``` + +## 约束 + +- `TileDataDst::DType`、`TileDataSrc1::DType` 必须是以下之一：`half`、`float`。 +- Tile 形状/布局约束（编译时）：`TileDataDst::isRowMajor`。 +- `src1` 预期提供**每列一个标量**（即，其有效形状必须覆盖 `C` 个值）。 +- 确切的布局/分形约束是目标特定的；参见 `include/pto/npu/*/TColExpand*.hpp` 下的后端头文件。 + +## 示例 + +参见 `docs/isa/` 和 `docs/coding/tutorials/` 中的相关示例。 + +## 汇编示例（ASM） + +### 自动模式 + +```text +# 自动模式：由编译器/运行时负责资源放置与调度。 +%dst = pto.tcolexpandexpdif %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### 手动模式 + +```text +# 手动模式：先显式绑定资源，再发射指令。 +# 可选（当该指令包含 tile 操作数时）： +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tcolexpandexpdif %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### PTO 汇编形式 + +```text +%dst = tcolexpandexpdif %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +# AS Level 2 (DPS) +pto.tcolexpandexpdif ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/TCOLEXPANDMAX.md b/designs/outerCube/PTOISA/TCOLEXPANDMAX.md new file mode 100644 index 00000000..85337c45 --- /dev/null +++ b/designs/outerCube/PTOISA/TCOLEXPANDMAX.md @@ -0,0 +1,90 @@ +# TCOLEXPANDMAX + + +## Tile Operation Diagram + +![TCOLEXPANDMAX tile operation](../figures/isa/TCOLEXPANDMAX.svg) + +## Introduction + +Column-wise broadcast max: take `max(src0, src1)` where `src1` provides one scalar per column. + + +## Math Interpretation + +Let `R = dst.GetValidRow()` and `C = dst.GetValidCol()`. Let `s_j` be the per-column scalar taken from `src1` (one value per column). + +For `0 <= i < R` and `0 <= j < C`: + +$$ +\mathrm{dst}_{i,j} = \max(\mathrm{src0}_{i,j}, s_j) +$$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = tcolexpandmax %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tcolexpandmax %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tcolexpandmax ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TCOLEXPANDMAX(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, WaitEvents &... events); +``` + +## Constraints + +- `TileDataDst::DType`, `TileDataSrc1::DType` must be one of: `half`, `float`. +- Tile shape/layout constraint (compile-time): `TileDataDst::isRowMajor`. +- `src1` is expected to provide **one scalar per column** (i.e., its valid shape must cover `C` values). +- Exact layout/fractal constraints are target-specific; see backend headers under `include/pto/npu/*/TColExpand*.hpp`. + +## Examples + +See related examples in `docs/isa/` and `docs/coding/tutorials/`. + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.tcolexpandmax %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tcolexpandmax %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = tcolexpandmax %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +# AS Level 2 (DPS) +pto.tcolexpandmax ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/TCOLEXPANDMAX_zh.md b/designs/outerCube/PTOISA/TCOLEXPANDMAX_zh.md new file mode 100644 index 00000000..ddd493b4 --- /dev/null +++ b/designs/outerCube/PTOISA/TCOLEXPANDMAX_zh.md @@ -0,0 +1,89 @@ +# TCOLEXPANDMAX + +## 指令示意图 + +![TCOLEXPANDMAX tile operation](../figures/isa/TCOLEXPANDMAX.svg) + +## 简介 + +列广播最大值：与每列标量向量取最大值。 + +## 数学语义 + +设 `R = dst.GetValidRow()` 和 `C = dst.GetValidCol()`。设 `s_j` 为从 `src1` 中获取的每列标量（每列一个值）。 + +对于 `0 <= i < R` 和 `0 <= j < C`： + +$$ +\mathrm{dst}_{i,j} = \max(\mathrm{src0}_{i,j}, s_j) +$$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS 规范](../assembly/PTO-AS_zh.md)。 + +同步形式： + +```text +%dst = tcolexpandmax %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 1（SSA） + +```text +%dst = pto.tcolexpandmax %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.tcolexpandmax ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`： + +```cpp +template +PTO_INST RecordEvent TCOLEXPANDMAX(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, WaitEvents &... events); +``` + +## 约束 + +- `TileDataDst::DType`、`TileDataSrc1::DType` 必须是以下之一：`half`、`float`。 +- Tile 形状/布局约束（编译时）：`TileDataDst::isRowMajor`。 +- `src1` 预期提供**每列一个标量**（即，其有效形状必须覆盖 `C` 个值）。 +- 确切的布局/分形约束是目标特定的；参见 `include/pto/npu/*/TColExpand*.hpp` 下的后端头文件。 + +## 示例 + +参见 `docs/isa/` 和 `docs/coding/tutorials/` 中的相关示例。 + +## 汇编示例（ASM） + +### 自动模式 + +```text +# 自动模式：由编译器/运行时负责资源放置与调度。 +%dst = pto.tcolexpandmax %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### 手动模式 + +```text +# 手动模式：先显式绑定资源，再发射指令。 +# 可选（当该指令包含 tile 操作数时）： +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tcolexpandmax %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### PTO 汇编形式 + +```text +%dst = tcolexpandmax %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +# AS Level 2 (DPS) +pto.tcolexpandmax ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/TCOLEXPANDMIN.md b/designs/outerCube/PTOISA/TCOLEXPANDMIN.md new file mode 100644 index 00000000..0cd2eec5 --- /dev/null +++ b/designs/outerCube/PTOISA/TCOLEXPANDMIN.md @@ -0,0 +1,90 @@ +# TCOLEXPANDMIN + + +## Tile Operation Diagram + +![TCOLEXPANDMIN tile operation](../figures/isa/TCOLEXPANDMIN.svg) + +## Introduction + +Column-wise broadcast min: take `min(src0, src1)` where `src1` provides one scalar per column. + + +## Math Interpretation + +Let `R = dst.GetValidRow()` and `C = dst.GetValidCol()`. Let `s_j` be the per-column scalar taken from `src1` (one value per column). + +For `0 <= i < R` and `0 <= j < C`: + +$$ +\mathrm{dst}_{i,j} = \min(\mathrm{src0}_{i,j}, s_j) +$$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = tcolexpandmin %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tcolexpandmin %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tcolexpandmin ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TCOLEXPANDMIN(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, WaitEvents &... events); +``` + +## Constraints + +- `TileDataDst::DType`, `TileDataSrc1::DType` must be one of: `half`, `float`. +- Tile shape/layout constraint (compile-time): `TileDataDst::isRowMajor`. +- `src1` is expected to provide **one scalar per column** (i.e., its valid shape must cover `C` values). +- Exact layout/fractal constraints are target-specific; see backend headers under `include/pto/npu/*/TColExpand*.hpp`. + +## Examples + +See related examples in `docs/isa/` and `docs/coding/tutorials/`. + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.tcolexpandmin %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tcolexpandmin %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = tcolexpandmin %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +# AS Level 2 (DPS) +pto.tcolexpandmin ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/TCOLEXPANDMIN_zh.md b/designs/outerCube/PTOISA/TCOLEXPANDMIN_zh.md new file mode 100644 index 00000000..11c7bae7 --- /dev/null +++ b/designs/outerCube/PTOISA/TCOLEXPANDMIN_zh.md @@ -0,0 +1,89 @@ +# TCOLEXPANDMIN + +## 指令示意图 + +![TCOLEXPANDMIN tile operation](../figures/isa/TCOLEXPANDMIN.svg) + +## 简介 + +列广播最小值：与每列标量向量取最小值。 + +## 数学语义 + +设 `R = dst.GetValidRow()` 和 `C = dst.GetValidCol()`。设 `s_j` 为从 `src1` 中获取的每列标量（每列一个值）。 + +对于 `0 <= i < R` 和 `0 <= j < C`： + +$$ +\mathrm{dst}_{i,j} = \min(\mathrm{src0}_{i,j}, s_j) +$$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS 规范](../assembly/PTO-AS_zh.md)。 + +同步形式： + +```text +%dst = tcolexpandmin %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 1（SSA） + +```text +%dst = pto.tcolexpandmin %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.tcolexpandmin ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`： + +```cpp +template +PTO_INST RecordEvent TCOLEXPANDMIN(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, WaitEvents &... events); +``` + +## 约束 + +- `TileDataDst::DType`、`TileDataSrc1::DType` 必须是以下之一：`half`、`float`。 +- Tile 形状/布局约束（编译时）：`TileDataDst::isRowMajor`。 +- `src1` 预期提供**每列一个标量**（即，其有效形状必须覆盖 `C` 个值）。 +- 确切的布局/分形约束是目标特定的；参见 `include/pto/npu/*/TColExpand*.hpp` 下的后端头文件。 + +## 示例 + +参见 `docs/isa/` 和 `docs/coding/tutorials/` 中的相关示例。 + +## 汇编示例（ASM） + +### 自动模式 + +```text +# 自动模式：由编译器/运行时负责资源放置与调度。 +%dst = pto.tcolexpandmin %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### 手动模式 + +```text +# 手动模式：先显式绑定资源，再发射指令。 +# 可选（当该指令包含 tile 操作数时）： +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tcolexpandmin %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### PTO 汇编形式 + +```text +%dst = tcolexpandmin %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +# AS Level 2 (DPS) +pto.tcolexpandmin ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/TCOLEXPANDMUL.md b/designs/outerCube/PTOISA/TCOLEXPANDMUL.md new file mode 100644 index 00000000..c1bcc7d6 --- /dev/null +++ b/designs/outerCube/PTOISA/TCOLEXPANDMUL.md @@ -0,0 +1,89 @@ +# TCOLEXPANDMUL + + +## Tile Operation Diagram + +![TCOLEXPANDMUL tile operation](../figures/isa/TCOLEXPANDMUL.svg) + +## Introduction + +Column-wise broadcast multiply: multiply each element of `src0` by a per-column scalar vector `src1`. + +## Math Interpretation + +Let `R = dst.GetValidRow()` and `C = dst.GetValidCol()`. Let `s_j` be the per-column scalar taken from `src1` (one value per column). + +For `0 <= i < R` and `0 <= j < C`: + +$$ +\mathrm{dst}_{i,j} = \mathrm{src0}_{i,j} \cdot s_j +$$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = tcolexpandmul %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tcolexpandmul %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tcolexpandmul ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TCOLEXPANDMUL(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, WaitEvents &... events); +``` + +## Constraints + +- `TileDataDst::DType`, `TileDataSrc1::DType` must be one of: `half`, `float`. +- Tile shape/layout constraint (compile-time): `TileDataDst::isRowMajor`. +- `src1` is expected to provide **one scalar per column** (i.e., its valid shape must cover `C` values). +- Exact layout/fractal constraints are target-specific; see backend headers under `include/pto/npu/*/TColExpand*.hpp`. + +## Examples + +See related examples in `docs/isa/` and `docs/coding/tutorials/`. + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.tcolexpandmul %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tcolexpandmul %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = tcolexpandmul %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +# AS Level 2 (DPS) +pto.tcolexpandmul ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/TCOLEXPANDMUL_zh.md b/designs/outerCube/PTOISA/TCOLEXPANDMUL_zh.md new file mode 100644 index 00000000..4bd2711b --- /dev/null +++ b/designs/outerCube/PTOISA/TCOLEXPANDMUL_zh.md @@ -0,0 +1,89 @@ +# TCOLEXPANDMUL + +## 指令示意图 + +![TCOLEXPANDMUL tile operation](../figures/isa/TCOLEXPANDMUL.svg) + +## 简介 + +列广播乘法：将每一列乘以一个每列标量向量。 + +## 数学语义 + +设 `R = dst.GetValidRow()` 和 `C = dst.GetValidCol()`。设 `s_j` 为从 `src1` 中获取的每列标量（每列一个值）。 + +对于 `0 <= i < R` 和 `0 <= j < C`： + +$$ +\mathrm{dst}_{i,j} = \mathrm{src0}_{i,j} \cdot s_j +$$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS 规范](../assembly/PTO-AS_zh.md)。 + +同步形式： + +```text +%dst = tcolexpandmul %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 1（SSA） + +```text +%dst = pto.tcolexpandmul %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.tcolexpandmul ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`： + +```cpp +template +PTO_INST RecordEvent TCOLEXPANDMUL(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, WaitEvents &... events); +``` + +## 约束 + +- `TileDataDst::DType`、`TileDataSrc1::DType` 必须是以下之一：`half`、`float`。 +- Tile 形状/布局约束（编译时）：`TileDataDst::isRowMajor`。 +- `src1` 预期提供**每列一个标量**（即，其有效形状必须覆盖 `C` 个值）。 +- 确切的布局/分形约束是目标特定的；参见 `include/pto/npu/*/TColExpand*.hpp` 下的后端头文件。 + +## 示例 + +参见 `docs/isa/` 和 `docs/coding/tutorials/` 中的相关示例。 + +## 汇编示例（ASM） + +### 自动模式 + +```text +# 自动模式：由编译器/运行时负责资源放置与调度。 +%dst = pto.tcolexpandmul %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### 手动模式 + +```text +# 手动模式：先显式绑定资源，再发射指令。 +# 可选（当该指令包含 tile 操作数时）： +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tcolexpandmul %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### PTO 汇编形式 + +```text +%dst = tcolexpandmul %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +# AS Level 2 (DPS) +pto.tcolexpandmul ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/TCOLEXPANDSUB.md b/designs/outerCube/PTOISA/TCOLEXPANDSUB.md new file mode 100644 index 00000000..6330e1a1 --- /dev/null +++ b/designs/outerCube/PTOISA/TCOLEXPANDSUB.md @@ -0,0 +1,89 @@ +# TCOLEXPANDSUB + + +## Tile Operation Diagram + +![TCOLEXPANDSUB tile operation](../figures/isa/TCOLEXPANDSUB.svg) + +## Introduction + +Column-wise broadcast subtract: subtract a per-column scalar vector `src1` from `src0`. + +## Math Interpretation + +Let `R = dst.GetValidRow()` and `C = dst.GetValidCol()`. Let `s_j` be the per-column scalar taken from `src1` (one value per column). + +For `0 <= i < R` and `0 <= j < C`: + +$$ +\mathrm{dst}_{i,j} = \mathrm{src0}_{i,j} - s_j +$$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = tcolexpandsub %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tcolexpandsub %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tcolexpandsub ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TCOLEXPANDSUB(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, WaitEvents &... events); +``` + +## Constraints + +- `TileDataDst::DType`, `TileDataSrc1::DType` must be one of: `half`, `float`. +- Tile shape/layout constraint (compile-time): `TileDataDst::isRowMajor`. +- `src1` is expected to provide **one scalar per column** (i.e., its valid shape must cover `C` values). +- Exact layout/fractal constraints are target-specific; see backend headers under `include/pto/npu/*/TColExpand*.hpp`. + +## Examples + +See related examples in `docs/isa/` and `docs/coding/tutorials/`. + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.tcolexpandsub %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tcolexpandsub %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = tcolexpandsub %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +# AS Level 2 (DPS) +pto.tcolexpandsub ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/TCOLEXPANDSUB_zh.md b/designs/outerCube/PTOISA/TCOLEXPANDSUB_zh.md new file mode 100644 index 00000000..5a28c2d1 --- /dev/null +++ b/designs/outerCube/PTOISA/TCOLEXPANDSUB_zh.md @@ -0,0 +1,89 @@ +# TCOLEXPANDSUB + +## 指令示意图 + +![TCOLEXPANDSUB tile operation](../figures/isa/TCOLEXPANDSUB.svg) + +## 简介 + +列广播减法：从每一列中减去一个每列标量向量。 + +## 数学语义 + +设 `R = dst.GetValidRow()` 和 `C = dst.GetValidCol()`。设 `s_j` 为从 `src1` 中获取的每列标量（每列一个值）。 + +对于 `0 <= i < R` 和 `0 <= j < C`： + +$$ +\mathrm{dst}_{i,j} = \mathrm{src0}_{i,j} - s_j +$$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS 规范](../assembly/PTO-AS_zh.md)。 + +同步形式： + +```text +%dst = tcolexpandsub %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 1（SSA） + +```text +%dst = pto.tcolexpandsub %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.tcolexpandsub ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`： + +```cpp +template +PTO_INST RecordEvent TCOLEXPANDSUB(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, WaitEvents &... events); +``` + +## 约束 + +- `TileDataDst::DType`、`TileDataSrc1::DType` 必须是以下之一：`half`、`float`。 +- Tile 形状/布局约束（编译时）：`TileDataDst::isRowMajor`。 +- `src1` 预期提供**每列一个标量**（即，其有效形状必须覆盖 `C` 个值）。 +- 确切的布局/分形约束是目标特定的；参见 `include/pto/npu/*/TColExpand*.hpp` 下的后端头文件。 + +## 示例 + +参见 `docs/isa/` 和 `docs/coding/tutorials/` 中的相关示例。 + +## 汇编示例（ASM） + +### 自动模式 + +```text +# 自动模式：由编译器/运行时负责资源放置与调度。 +%dst = pto.tcolexpandsub %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### 手动模式 + +```text +# 手动模式：先显式绑定资源，再发射指令。 +# 可选（当该指令包含 tile 操作数时）： +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tcolexpandsub %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### PTO 汇编形式 + +```text +%dst = tcolexpandsub %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +# AS Level 2 (DPS) +pto.tcolexpandsub ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/TCOLEXPAND_zh.md b/designs/outerCube/PTOISA/TCOLEXPAND_zh.md new file mode 100644 index 00000000..6d966964 --- /dev/null +++ b/designs/outerCube/PTOISA/TCOLEXPAND_zh.md @@ -0,0 +1,76 @@ +# TCOLEXPAND + +## 指令示意图 + +![TCOLEXPAND tile operation](../figures/isa/TCOLEXPAND.svg) + +## 简介 + +将每个源列的第一个元素广播到目标列中。 + +## 数学语义 + +Let `R = dst.GetValidRow()` and `C = dst.GetValidCol()`. For `0 <= i < R` and `0 <= j < C`: + +$$ \mathrm{dst}_{i,j} = \mathrm{src}_{0,j} $$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS Specification](../assembly/PTO-AS.md). + +同步形式： + +```text +%dst = tcolexpand %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tcolexpand %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tcolexpand ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### AS Level 1（SSA） + +```text +%dst = pto.tcolexpand %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.tcolexpand ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TCOLEXPAND(TileDataDst &dst, TileDataSrc &src, WaitEvents &... events); +``` + +## 约束 + +- The op iterates over `dst.GetValidRow()` / `dst.GetValidCol()`. + +## 示例 + +```cpp +#include + +using namespace pto; + +void example() { + using TileT = Tile; + TileT src, dst; + TCOLEXPAND(dst, src); +} +``` diff --git a/designs/outerCube/PTOISA/TCOLMAX.md b/designs/outerCube/PTOISA/TCOLMAX.md new file mode 100644 index 00000000..fdfed987 --- /dev/null +++ b/designs/outerCube/PTOISA/TCOLMAX.md @@ -0,0 +1,135 @@ +# TCOLMAX + + +## Tile Operation Diagram + +![TCOLMAX tile operation](../figures/isa/TCOLMAX.svg) + +## Introduction + +Reduce each column by taking the maximum across rows. + +## Math Interpretation + +Let `R = src.GetValidRow()` and `C = src.GetValidCol()`. For `0 <= j < C`: + +$$ \mathrm{dst}_{0,j} = \max_{0 \le i < R} \mathrm{src}_{i,j} $$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = tcolmax %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tcolmax %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tcolmax ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### IR Level 1 (SSA) + +```text +%dst = pto.tcolmax %src : !pto.tile<...> -> !pto.tile<...> +``` + +### IR Level 2 (DPS) + +```text +pto.tcolmax ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TCOLMAX(TileDataOut &dst, TileDataIn &src, WaitEvents &... events); +``` + +## Constraints + +Implementation checks (NPU): + +- Tile location: `dst` and `src` must be `TileType::Vec`. +- Tile layout: both tiles must be ND fractal (`isRowMajor` and `SLayout::NoneBox`). +- Data types: + - A2A3: `half`, `float`, `int16_t`, `int32_t`. + - A5: `half`, `float`, `int8_t`, `uint8_t`, `int16_t`, `uint16_t`, `int32_t`, `uint32_t`, `bfloat16_t`. +- DType consistency: `dst.DType == src.DType`. +- Runtime valid checks: + - `src.GetValidCol() == dst.GetValidCol()`. + - If `src.GetValidRow() == 0` or `src.GetValidCol() == 0`, the implementation returns early. + +## Examples + +### Auto + +```cpp +#include + +using namespace pto; + +void example_auto() { + using SrcT = Tile; + using DstT = Tile; + SrcT src; + DstT dst; + TCOLMAX(dst, src); +} +``` + +### Manual + +```cpp +#include + +using namespace pto; + +void example_manual() { + using SrcT = Tile; + using DstT = Tile; + SrcT src; + DstT dst; + TASSIGN(src, 0x1000); + TASSIGN(dst, 0x2000); + TCOLMAX(dst, src); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.tcolmax %src : !pto.tile<...> -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tcolmax %src : !pto.tile<...> -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = tcolmax %src : !pto.tile<...> -> !pto.tile<...> +# AS Level 2 (DPS) +pto.tcolmax ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TCOLMAX_zh.md b/designs/outerCube/PTOISA/TCOLMAX_zh.md new file mode 100644 index 00000000..a958f1c4 --- /dev/null +++ b/designs/outerCube/PTOISA/TCOLMAX_zh.md @@ -0,0 +1,108 @@ +# TCOLMAX + +## 指令示意图 + +![TCOLMAX tile operation](../figures/isa/TCOLMAX.svg) + +## 简介 + +通过取行间最大值来归约每一列。 + +## 数学语义 + +Let `R = src.GetValidRow()` and `C = src.GetValidCol()`. For `0 <= j < C`: + +$$ \mathrm{dst}_{0,j} = \max_{0 \le i < R} \mathrm{src}_{i,j} $$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS Specification](../assembly/PTO-AS.md). + +同步形式： + +```text +%dst = tcolmax %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tcolmax %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tcolmax ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### AS Level 1（SSA） + +```text +%dst = pto.tcolmax %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.tcolmax ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TCOLMAX(TileDataOut &dst, TileDataIn &src, WaitEvents &... events); +``` + +## 约束 + +实现检查 (NPU): + +- Tile location: `dst` and `src` must be `TileType::Vec`. +- Tile 布局: both tiles must be ND fractal (`isRowMajor` and `SLayout::NoneBox`). +- 数据类型: + - A2A3: `half`, `float`, `int16_t`, `int32_t`. + - A5: `half`, `float`, `int8_t`, `uint8_t`, `int16_t`, `uint16_t`, `int32_t`, `uint32_t`, `bfloat16_t`. +- 数据类型一致性: `dst.DType == src.DType`. +- 运行期有效区域检查: + - `src.GetValidCol() == dst.GetValidCol()`. + - If `src.GetValidRow() == 0` or `src.GetValidCol() == 0`, the implementation returns early. + +## 示例 + +### 自动（Auto） + +```cpp +#include + +using namespace pto; + +void example_auto() { + using SrcT = Tile; + using DstT = Tile; + SrcT src; + DstT dst; + TCOLMAX(dst, src); +} +``` + +### 手动（Manual） + +```cpp +#include + +using namespace pto; + +void example_manual() { + using SrcT = Tile; + using DstT = Tile; + SrcT src; + DstT dst; + TASSIGN(src, 0x1000); + TASSIGN(dst, 0x2000); + TCOLMAX(dst, src); +} +``` diff --git a/designs/outerCube/PTOISA/TCOLMIN.md b/designs/outerCube/PTOISA/TCOLMIN.md new file mode 100644 index 00000000..1cfdcd35 --- /dev/null +++ b/designs/outerCube/PTOISA/TCOLMIN.md @@ -0,0 +1,135 @@ +# TCOLMIN + + +## Tile Operation Diagram + +![TCOLMIN tile operation](../figures/isa/TCOLMIN.svg) + +## Introduction + +Reduce each column by taking the minimum across rows. + +## Math Interpretation + +Let `R = src.GetValidRow()` and `C = src.GetValidCol()`. For `0 <= j < C`: + +$$ \mathrm{dst}_{0,j} = \min_{0 \le i < R} \mathrm{src}_{i,j} $$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = tcolmin %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tcolmin %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tcolmin ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### IR Level 1 (SSA) + +```text +%dst = pto.tcolmin %src : !pto.tile<...> -> !pto.tile<...> +``` + +### IR Level 2 (DPS) + +```text +pto.tcolmin ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TCOLMIN(TileDataOut &dst, TileDataIn &src, WaitEvents &... events); +``` + +## Constraints + +Implementation checks (NPU): + +- Tile location: `dst` and `src` must be `TileType::Vec`. +- Tile layout: both tiles must be ND fractal (`isRowMajor` and `SLayout::NoneBox`). +- Data types: + - A2A3: `half`, `float`, `int16_t`, `int32_t`. + - A5: `half`, `float`, `int8_t`, `uint8_t`, `int16_t`, `uint16_t`, `int32_t`, `uint32_t`, `bfloat16_t`. +- DType consistency: `dst.DType == src.DType`. +- Runtime valid checks: + - `src.GetValidCol() == dst.GetValidCol()`. + - If `src.GetValidRow() == 0` or `src.GetValidCol() == 0`, the implementation returns early. + +## Examples + +### Auto + +```cpp +#include + +using namespace pto; + +void example_auto() { + using SrcT = Tile; + using DstT = Tile; + SrcT src; + DstT dst; + TCOLMIN(dst, src); +} +``` + +### Manual + +```cpp +#include + +using namespace pto; + +void example_manual() { + using SrcT = Tile; + using DstT = Tile; + SrcT src; + DstT dst; + TASSIGN(src, 0x1000); + TASSIGN(dst, 0x2000); + TCOLMIN(dst, src); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.tcolmin %src : !pto.tile<...> -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tcolmin %src : !pto.tile<...> -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = tcolmin %src : !pto.tile<...> -> !pto.tile<...> +# AS Level 2 (DPS) +pto.tcolmin ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TCOLMIN_zh.md b/designs/outerCube/PTOISA/TCOLMIN_zh.md new file mode 100644 index 00000000..9a6fcadf --- /dev/null +++ b/designs/outerCube/PTOISA/TCOLMIN_zh.md @@ -0,0 +1,108 @@ +# TCOLMIN + +## 指令示意图 + +![TCOLMIN tile operation](../figures/isa/TCOLMIN.svg) + +## 简介 + +通过取行间最小值来归约每一列。 + +## 数学语义 + +Let `R = src.GetValidRow()` and `C = src.GetValidCol()`. For `0 <= j < C`: + +$$ \mathrm{dst}_{0,j} = \min_{0 \le i < R} \mathrm{src}_{i,j} $$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS Specification](../assembly/PTO-AS.md). + +同步形式： + +```text +%dst = tcolmin %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tcolmin %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tcolmin ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### AS Level 1（SSA） + +```text +%dst = pto.tcolmin %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.tcolmin ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TCOLMIN(TileDataOut &dst, TileDataIn &src, WaitEvents &... events); +``` + +## 约束 + +实现检查 (NPU): + +- Tile location: `dst` and `src` must be `TileType::Vec`. +- Tile 布局: both tiles must be ND fractal (`isRowMajor` and `SLayout::NoneBox`). +- 数据类型: + - A2A3: `half`, `float`, `int16_t`, `int32_t`. + - A5: `half`, `float`, `int8_t`, `uint8_t`, `int16_t`, `uint16_t`, `int32_t`, `uint32_t`, `bfloat16_t`. +- 数据类型一致性: `dst.DType == src.DType`. +- 运行期有效区域检查: + - `src.GetValidCol() == dst.GetValidCol()`. + - If `src.GetValidRow() == 0` or `src.GetValidCol() == 0`, the implementation returns early. + +## 示例 + +### 自动（Auto） + +```cpp +#include + +using namespace pto; + +void example_auto() { + using SrcT = Tile; + using DstT = Tile; + SrcT src; + DstT dst; + TCOLMIN(dst, src); +} +``` + +### 手动（Manual） + +```cpp +#include + +using namespace pto; + +void example_manual() { + using SrcT = Tile; + using DstT = Tile; + SrcT src; + DstT dst; + TASSIGN(src, 0x1000); + TASSIGN(dst, 0x2000); + TCOLMIN(dst, src); +} +``` diff --git a/designs/outerCube/PTOISA/TCOLPROD.md b/designs/outerCube/PTOISA/TCOLPROD.md new file mode 100644 index 00000000..d0d050b6 --- /dev/null +++ b/designs/outerCube/PTOISA/TCOLPROD.md @@ -0,0 +1,135 @@ +# TCOLPROD + + +## Tile Operation Diagram + +![TCOLPROD tile operation](../figures/isa/TCOLPROD.svg) + +## Introduction + +Reduce each column by multiplying across rows. + +## Math Interpretation + +Let `R = src.GetValidRow()` and `C = src.GetValidCol()`. For `0 <= j < C`: + +$$ \mathrm{dst}_{0,j} = \prod_{i=0}^{R-1} \mathrm{src}_{i,j} $$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = tcolprod %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tcolprod %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tcolprod ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### IR Level 1 (SSA) + +```text +%dst = pto.tcolprod %src : !pto.tile<...> -> !pto.tile<...> +``` + +### IR Level 2 (DPS) + +```text +pto.tcolprod ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TCOLPROD(TileDataOut &dst, TileDataIn &src, WaitEvents &... events); +``` + +## Constraints + +Implementation checks (NPU): + +- Tile location: `dst` and `src` must be `TileType::Vec`. +- Tile layout: both tiles must be ND fractal (`isRowMajor` and `SLayout::NoneBox`). +- DType consistency: `dst.DType == src.DType`. +- Supported `src.DType`: + - A2A3: `half`, `float`, `int16_t`, `int32_t`. + - A5: `half`, `float`, `bfloat16`, `int16_t`, `int32_t`, `uint16_t`, `uint32_t`. +- Runtime valid checks: + - `src.GetValidCol() == dst.GetValidCol()`. + - If `src.GetValidRow() == 0` or `src.GetValidCol() == 0`, the implementation returns early. + +## Examples + +### Auto + +```cpp +#include + +using namespace pto; + +void example_auto() { + using SrcT = Tile; + using DstT = Tile; + SrcT src; + DstT dst; + TCOLPROD(dst, src); +} +``` + +### Manual + +```cpp +#include + +using namespace pto; + +void example_manual() { + using SrcT = Tile; + using DstT = Tile; + SrcT src; + DstT dst; + TASSIGN(src, 0x1000); + TASSIGN(dst, 0x2000); + TCOLPROD(dst, src); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.tcolprod %src : !pto.tile<...> -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tcolprod %src : !pto.tile<...> -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = tcolprod %src : !pto.tile<...> -> !pto.tile<...> +# AS Level 2 (DPS) +pto.tcolprod ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TCOLPROD_zh.md b/designs/outerCube/PTOISA/TCOLPROD_zh.md new file mode 100644 index 00000000..36ef0001 --- /dev/null +++ b/designs/outerCube/PTOISA/TCOLPROD_zh.md @@ -0,0 +1,108 @@ +# TCOLPROD + +## 指令示意图 + +![TCOLPROD tile operation](../figures/isa/TCOLPROD.svg) + +## 简介 + +通过跨行乘积来归约每一列。 + +## 数学语义 + +Let `R = src.GetValidRow()` and `C = src.GetValidCol()`. For `0 <= j < C`: + +$$ \mathrm{dst}_{0,j} = \prod_{i=0}^{R-1} \mathrm{src}_{i,j} $$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS Specification](../assembly/PTO-AS.md). + +同步形式： + +```text +%dst = tcolprod %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tcolprod %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tcolprod ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### AS Level 1（SSA） + +```text +%dst = pto.tcolprod %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.tcolprod ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TCOLPROD(TileDataOut &dst, TileDataIn &src, WaitEvents &... events); +``` + +## 约束 + +实现检查 (NPU): + +- Tile location: `dst` and `src` must be `TileType::Vec`. +- Tile 布局: both tiles must be ND fractal (`isRowMajor` and `SLayout::NoneBox`). +- 数据类型一致性: `dst.DType == src.DType`. +- Supported `src.DType`: + - A2A3: `half`, `float`, `int16_t`, `int32_t`. + - A5: `half`, `float`, `bfloat16`, `int16_t`, `int32_t`, `uint16_t`, `uint32_t`. +- 运行期有效区域检查: + - `src.GetValidCol() == dst.GetValidCol()`. + - If `src.GetValidRow() == 0` or `src.GetValidCol() == 0`, the implementation returns early. + +## 示例 + +### 自动（Auto） + +```cpp +#include + +using namespace pto; + +void example_auto() { + using SrcT = Tile; + using DstT = Tile; + SrcT src; + DstT dst; + TCOLPROD(dst, src); +} +``` + +### 手动（Manual） + +```cpp +#include + +using namespace pto; + +void example_manual() { + using SrcT = Tile; + using DstT = Tile; + SrcT src; + DstT dst; + TASSIGN(src, 0x1000); + TASSIGN(dst, 0x2000); + TCOLPROD(dst, src); +} +``` diff --git a/designs/outerCube/PTOISA/TCOLSUM.md b/designs/outerCube/PTOISA/TCOLSUM.md new file mode 100644 index 00000000..ef4ec250 --- /dev/null +++ b/designs/outerCube/PTOISA/TCOLSUM.md @@ -0,0 +1,149 @@ +# TCOLSUM + + +## Tile Operation Diagram + +![TCOLSUM tile operation](../figures/isa/TCOLSUM.svg) + +## Introduction + +Reduce each column by summing across rows. + +## Math Interpretation + +Let `R = src.GetValidRow()` and `C = src.GetValidCol()`. For `0 <= j < C`: + +$$ \mathrm{dst}_{0,j} = \sum_{i=0}^{R-1} \mathrm{src}_{i,j} $$ + +`isBinary` selects the implementation path (binary-tree accumulation vs. sequential accumulation). + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = tcolsum %src {isBinary = false} : !pto.tile<...> -> !pto.tile<...> +``` +Lowering may introduce internal scratch tiles; the C++ intrinsic requires an explicit `tmp` operand. + +### AS Level 1 (SSA) + +```text +%dst = pto.tcolsum %src : !pto.tile<...> -> !pto.tile<...> +%dst = pto.tcolsum %src, %tmp {isBinary = false} : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tcolsum ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +pto.tcolsum ins(%src, %tmp {isBinary = false} : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### IR Level 1 (SSA) + +```text +%dst = pto.tcolsum %src : !pto.tile<...> -> !pto.tile<...> +%dst = pto.tcolsum %src, %tmp {isBinary = false} : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### IR Level 2 (DPS) + +```text +pto.tcolsum ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +pto.tcolsum ins(%src, %tmp {isBinary = false} : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TCOLSUM(TileDataOut &dst, TileDataIn &src, WaitEvents &... events); + +template +PTO_INST RecordEvent TCOLSUM(TileDataOut &dst, TileDataIn &src, TileDataTmp &tmp, bool isBinary, WaitEvents &... events); +``` + +## Constraints + +Implementation checks (NPU): + +- Tile location: `dst`, `src`, `tmp` must be `TileType::Vec`. +- Tile layout: all tiles must be ND fractal (`isRowMajor` and `SLayout::NoneBox`). +- DType consistency: + - A2A3: `src.DType` must be one of `half`, `float`, `int16_t`, `int32_t`, and `dst.DType == tmp.DType == src.DType`. + - A5: `dst.DType == src.DType` is required by `TColReduceCheck`; the exact supported `src.DType` set is target-defined (see `include/pto/npu/a5/TColReduceOps.hpp`). +- Runtime valid checks: + - A2A3: `src.GetValidCol() == dst.GetValidCol()`; returns early if `src.GetValidRow() == 0` or `src.GetValidCol() == 0`. + - A5: `srcValidRow` and `srcValidCol` must be non-zero; `srcValidCol == dstValidCol` is asserted by `TColReduceCheck`. + +## Examples + +### Auto + +```cpp +#include + +using namespace pto; + +void example_auto() { + using SrcT = Tile; + using DstT = Tile; + using TmpT = Tile; + SrcT src; + DstT dst; + TmpT tmp; + TCOLSUM(dst, src, tmp, /*isBinary=*/false); +} +``` + +### Manual + +```cpp +#include + +using namespace pto; + +void example_manual() { + using SrcT = Tile; + using DstT = Tile; + using TmpT = Tile; + SrcT src; + DstT dst; + TmpT tmp; + TASSIGN(src, 0x1000); + TASSIGN(dst, 0x2000); + TASSIGN(tmp, 0x3000); + TCOLSUM(dst, src, tmp, /*isBinary=*/false); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.tcolsum %src : !pto.tile<...> -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tcolsum %src : !pto.tile<...> -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = tcolsum %src {isBinary = false} : !pto.tile<...> -> !pto.tile<...> +# AS Level 2 (DPS) +pto.tcolsum ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TCOLSUM_zh.md b/designs/outerCube/PTOISA/TCOLSUM_zh.md new file mode 100644 index 00000000..b15c5ad6 --- /dev/null +++ b/designs/outerCube/PTOISA/TCOLSUM_zh.md @@ -0,0 +1,122 @@ +# TCOLSUM + +## 指令示意图 + +![TCOLSUM tile operation](../figures/isa/TCOLSUM.svg) + +## 简介 + +通过对行求和来归约每一列。 + +## 数学语义 + +Let `R = src.GetValidRow()` and `C = src.GetValidCol()`. For `0 <= j < C`: + +$$ \mathrm{dst}_{0,j} = \sum_{i=0}^{R-1} \mathrm{src}_{i,j} $$ + +`isBinary` selects the implementation path (binary-tree accumulation vs. sequential accumulation). + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS Specification](../assembly/PTO-AS.md). + +同步形式： + +```text +%dst = tcolsum %src {isBinary = false} : !pto.tile<...> -> !pto.tile<...> +``` +Lowering may introduce internal scratch tiles; the C++ intrinsic requires an explicit `tmp` operand. + +### AS Level 1 (SSA) + +```text +%dst = pto.tcolsum %src : !pto.tile<...> -> !pto.tile<...> +%dst = pto.tcolsum %src, %tmp {isBinary = false} : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tcolsum ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +pto.tcolsum ins(%src, %tmp {isBinary = false} : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### AS Level 1（SSA） + +```text +%dst = pto.tcolsum %src : !pto.tile<...> -> !pto.tile<...> +%dst = pto.tcolsum %src, %tmp {isBinary = false} : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.tcolsum ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +pto.tcolsum ins(%src, %tmp {isBinary = false} : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TCOLSUM(TileDataOut &dst, TileDataIn &src, WaitEvents &... events); + +template +PTO_INST RecordEvent TCOLSUM(TileDataOut &dst, TileDataIn &src, TileDataTmp &tmp, bool isBinary, WaitEvents &... events); +``` + +## 约束 + +实现检查 (NPU): + +- Tile location: `dst`, `src`, `tmp` must be `TileType::Vec`. +- Tile 布局: all tiles must be ND fractal (`isRowMajor` and `SLayout::NoneBox`). +- 数据类型一致性: + - A2A3: `src.DType` must be one of `half`, `float`, `int16_t`, `int32_t`, and `dst.DType == tmp.DType == src.DType`. + - A5: `dst.DType == src.DType` is required by `TColReduceCheck`; the exact supported `src.DType` set is target-defined (see `include/pto/npu/a5/TColReduceOps.hpp`). +- 运行期有效区域检查: + - A2A3: `src.GetValidCol() == dst.GetValidCol()`; returns early if `src.GetValidRow() == 0` or `src.GetValidCol() == 0`. + - A5: `srcValidRow` and `srcValidCol` must be non-zero; `srcValidCol == dstValidCol` is asserted by `TColReduceCheck`. + +## 示例 + +### 自动（Auto） + +```cpp +#include + +using namespace pto; + +void example_auto() { + using SrcT = Tile; + using DstT = Tile; + using TmpT = Tile; + SrcT src; + DstT dst; + TmpT tmp; + TCOLSUM(dst, src, tmp, /*isBinary=*/false); +} +``` + +### 手动（Manual） + +```cpp +#include + +using namespace pto; + +void example_manual() { + using SrcT = Tile; + using DstT = Tile; + using TmpT = Tile; + SrcT src; + DstT dst; + TmpT tmp; + TASSIGN(src, 0x1000); + TASSIGN(dst, 0x2000); + TASSIGN(tmp, 0x3000); + TCOLSUM(dst, src, tmp, /*isBinary=*/false); +} +``` diff --git a/designs/outerCube/PTOISA/TCONCAT.md b/designs/outerCube/PTOISA/TCONCAT.md new file mode 100644 index 00000000..e24be1e1 --- /dev/null +++ b/designs/outerCube/PTOISA/TCONCAT.md @@ -0,0 +1,40 @@ +# TCONCAT + +## Tile Operation Diagram + +![TCONCAT tile operation](../figures/isa/TCONCAT.svg) + +## Introduction + +Concatenate two source tiles along the column dimension into a destination tile. + +## Math Interpretation + +Semantics are instruction-specific. Unless stated otherwise, behavior is defined over the destination valid region. + +## Assembly Syntax + +PTO-AS form: see `docs/assembly/PTO-AS.md`. + +### IR Level 1 (SSA) + +```text +%dst = pto.tconcat ... +``` + +### IR Level 2 (DPS) + +```text +pto.tconcat ins(...) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`. + +## Constraints + +Refer to backend-specific legality checks for data type/layout/location/shape constraints. + +## Examples + +See related instruction pages in `docs/isa/` for concrete Auto/Manual usage patterns. diff --git a/designs/outerCube/PTOISA/TCONCAT_zh.md b/designs/outerCube/PTOISA/TCONCAT_zh.md new file mode 100644 index 00000000..3a050b7e --- /dev/null +++ b/designs/outerCube/PTOISA/TCONCAT_zh.md @@ -0,0 +1,41 @@ +# TCONCAT + +## 指令示意图 + +![TCONCAT tile operation](../figures/isa/TCONCAT.svg) + +## 简介 + +沿列维将两个源 Tile 拼接到目标 Tile。 + +## 数学语义 + +语义随指令而变化。 Unless stated otherwise, behavior is defined over the destination valid region. + +## 汇编语法 + +PTO-AS 形式：参见 `docs/assembly/PTO-AS.md`. + +### AS Level 1（SSA） + +```text +%dst = pto.tconcat ... +``` + +### AS Level 2（DPS） + +```text +pto.tconcat ins(...) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`. + +## 约束 + +Refer to backend-specific legality checks for data type/layout/location/shape constraints. + +## 示例 + +See related instruction pages in `docs/isa/` for concrete Auto/Manual usage patterns. diff --git a/designs/outerCube/PTOISA/TCVT.md b/designs/outerCube/PTOISA/TCVT.md new file mode 100644 index 00000000..72bdccf0 --- /dev/null +++ b/designs/outerCube/PTOISA/TCVT.md @@ -0,0 +1,124 @@ +# TCVT + + +## Tile Operation Diagram + +![TCVT tile operation](../figures/isa/TCVT.svg) + +## Introduction + +Elementwise type conversion with a specified rounding mode. + +## Math Interpretation + +For each element `(i, j)` in the valid region: + +$$ \mathrm{dst}_{i,j} = \mathrm{cast}_{\mathrm{rmode}}\!\left(\mathrm{src}_{i,j}\right) $$ + +where `rmode` is a rounding policy (see `pto::RoundMode`). + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = tcvt %src {rmode = #pto.round_mode} : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tcvt %src{rmode = #pto}: !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tcvt ins(%src{rmode = #pto}: !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp` and `include/pto/common/constants.hpp`: + +```cpp +template +PTO_INST RecordEvent TCVT(TileDataD &dst, TileDataS &src, RoundMode mode, SaturationMode satMode, WaitEvents &... events); + +template +PTO_INST RecordEvent TCVT(TileDataD &dst, TileDataS &src, RoundMode mode, WaitEvents &... events); +``` + +## Constraints + +- `dst` and `src` must be compatible in shape/valid region as required by the implementation. +- The conversion `(src element type) -> (dst element type)` must be supported by the target for the given `RoundMode`. +- **Implementation notes (A2A3/A5)**: + - One form accepts an explicit `SaturationMode`, and the specified saturation behavior is forwarded directly to the implementation. + - The other form omits `SaturationMode`; in that case, the implementation chooses a target-defined default saturation behavior for the specific type pair. + - On CPU, only the form without explicit `SaturationMode` is currently implemented. + +## Examples + +### Auto + +```cpp +#include + +using namespace pto; + +void example_auto() { + using SrcT = Tile; + using DstT = Tile; + SrcT src; + DstT dst; + TCVT(dst, src, RoundMode::CAST_RINT); +} +``` + +### Manual + +```cpp +#include + +using namespace pto; + +void example_manual() { + using SrcT = Tile; + using DstT = Tile; + SrcT src; + DstT dst; + TASSIGN(src, 0x1000); + TASSIGN(dst, 0x2000); + TCVT(dst, src, RoundMode::CAST_RINT); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.tcvt %src{rmode = #pto}: !pto.tile<...> -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tcvt %src{rmode = #pto}: !pto.tile<...> -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = tcvt %src {rmode = #pto.round_mode} : !pto.tile<...> -> !pto.tile<...> +# AS Level 2 (DPS) +pto.tcvt ins(%src{rmode = #pto}: !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/TCVT_zh.md b/designs/outerCube/PTOISA/TCVT_zh.md new file mode 100644 index 00000000..fddd187a --- /dev/null +++ b/designs/outerCube/PTOISA/TCVT_zh.md @@ -0,0 +1,124 @@ +# TCVT + +## 指令示意图 + +![TCVT tile operation](../figures/isa/TCVT.svg) + +## 简介 + +带指定舍入模式的逐元素类型转换。 + +## 数学语义 + +对每个元素 `(i, j)` 在有效区域内： + +$$ \mathrm{dst}_{i,j} = \mathrm{cast}_{\mathrm{rmode}}\!\left(\mathrm{src}_{i,j}\right) $$ + +其中 `rmode` 是舍入策略（参见 `pto::RoundMode`）。 + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS 规范](../assembly/PTO-AS_zh.md)。 + +同步形式： + +```text +%dst = tcvt %src {rmode = #pto.round_mode} : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 1（SSA） + +```text +%dst = pto.tcvt %src{rmode = #pto}: !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.tcvt ins(%src{rmode = #pto}: !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp` 和 `include/pto/common/constants.hpp`： + +```cpp +template +PTO_INST RecordEvent TCVT(TileDataD &dst, TileDataS &src, RoundMode mode, SaturationMode satMode, WaitEvents &... events); + +template +PTO_INST RecordEvent TCVT(TileDataD &dst, TileDataS &src, RoundMode mode, WaitEvents &... events); +``` + +## 约束 + +- `dst` 和 `src` 必须在形状/有效区域方面兼容，如实现所要求的。 +- 对于给定的 `RoundMode`，转换 `(src 元素类型) -> (dst 元素类型)` 必须被目标支持。 +- **实现说明 (A2A3/A5)**: + - 一种形式接受显式的 `SaturationMode`，指定的饱和行为会直接传递给实现。 + - 另一种形式不显式给出 `SaturationMode`；此时实现会针对具体类型对选择目标定义的默认饱和行为。 + - 在 CPU 实现中，目前仅实现了不显式传入 `SaturationMode` 的形式。 + +## 示例 + +### 自动（Auto） + +```cpp +#include + +using namespace pto; + +void example_auto() { + using SrcT = Tile; + using DstT = Tile; + SrcT src; + DstT dst; + TCVT(dst, src, RoundMode::CAST_RINT); +} +``` + +### 手动（Manual） + +```cpp +#include + +using namespace pto; + +void example_manual() { + using SrcT = Tile; + using DstT = Tile; + SrcT src; + DstT dst; + TASSIGN(src, 0x1000); + TASSIGN(dst, 0x2000); + TCVT(dst, src, RoundMode::CAST_RINT); +} +``` + +## 汇编示例（ASM） + +### 自动模式 + +```text +# 自动模式：由编译器/运行时负责资源放置与调度。 +%dst = pto.tcvt %src{rmode = #pto}: !pto.tile<...> -> !pto.tile<...> +``` + +### 手动模式 + +```text +# 手动模式：先显式绑定资源，再发射指令。 +# 可选（当该指令包含 tile 操作数时）： +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tcvt %src{rmode = #pto}: !pto.tile<...> -> !pto.tile<...> +``` + +### PTO 汇编形式 + +```text +%dst = tcvt %src {rmode = #pto.round_mode} : !pto.tile<...> -> !pto.tile<...> +# AS Level 2 (DPS) +pto.tcvt ins(%src{rmode = #pto}: !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/TDEQUANT.md b/designs/outerCube/PTOISA/TDEQUANT.md new file mode 100644 index 00000000..8204ce03 --- /dev/null +++ b/designs/outerCube/PTOISA/TDEQUANT.md @@ -0,0 +1,40 @@ +# TDEQUANT + +## Tile Operation Diagram + +![TDEQUANT tile operation](../figures/isa/TDEQUANT.svg) + +## Introduction + +Dequantize an integer tile into a floating-point tile using scale and offset tiles. + +## Math Interpretation + +Semantics are instruction-specific. Unless stated otherwise, behavior is defined over the destination valid region. + +## Assembly Syntax + +PTO-AS form: see `docs/assembly/PTO-AS.md`. + +### IR Level 1 (SSA) + +```text +%dst = pto.tdequant ... +``` + +### IR Level 2 (DPS) + +```text +pto.tdequant ins(...) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`. + +## Constraints + +Refer to backend-specific legality checks for data type/layout/location/shape constraints. + +## Examples + +See related instruction pages in `docs/isa/` for concrete Auto/Manual usage patterns. diff --git a/designs/outerCube/PTOISA/TDEQUANT_zh.md b/designs/outerCube/PTOISA/TDEQUANT_zh.md new file mode 100644 index 00000000..9f07b6c4 --- /dev/null +++ b/designs/outerCube/PTOISA/TDEQUANT_zh.md @@ -0,0 +1,41 @@ +# TDEQUANT + +## 指令示意图 + +![TDEQUANT tile operation](../figures/isa/TDEQUANT.svg) + +## 简介 + +使用 scale 与 offset Tile 将整数量化 Tile 反量化为浮点 Tile。 + +## 数学语义 + +语义随指令而变化。 Unless stated otherwise, behavior is defined over the destination valid region. + +## 汇编语法 + +PTO-AS 形式：参见 `docs/assembly/PTO-AS.md`. + +### AS Level 1（SSA） + +```text +%dst = pto.tdequant ... +``` + +### AS Level 2（DPS） + +```text +pto.tdequant ins(...) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`. + +## 约束 + +Refer to backend-specific legality checks for data type/layout/location/shape constraints. + +## 示例 + +See related instruction pages in `docs/isa/` for concrete Auto/Manual usage patterns. diff --git a/designs/outerCube/PTOISA/TDIV.md b/designs/outerCube/PTOISA/TDIV.md new file mode 100644 index 00000000..7c10a875 --- /dev/null +++ b/designs/outerCube/PTOISA/TDIV.md @@ -0,0 +1,137 @@ +# TDIV + + +## Tile Operation Diagram + +![TDIV tile operation](../figures/isa/TDIV.svg) + +## Introduction + +Elementwise division of two tiles. + +## Math Interpretation + +For each element `(i, j)` in the valid region: + +$$ \mathrm{dst}_{i,j} = \frac{\mathrm{src0}_{i,j}}{\mathrm{src1}_{i,j}} $$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = tdiv %src0, %src1 : !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tdiv %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tdiv ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### IR Level 1 (SSA) + +```text +%dst = pto.tdiv %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### IR Level 2 (DPS) + +```text +pto.tdiv ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TDIV(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, WaitEvents &... events); +``` + +## Constraints + +- **Implementation checks (A2A3)**: + - `TileData::DType` must be one of: `half`, `float`. + - Tile layout must be row-major (`TileData::isRowMajor`). + - Tile location must be vector (`TileData::Loc == TileType::Vec`). + - Static valid bounds: `TileData::ValidRow <= TileData::Rows` and `TileData::ValidCol <= TileData::Cols`. + - Runtime: `src0`, `src1` and `dst` tiles should have the same `validRow/validCol`. +- **Implementation checks (A5)**: + - `TileData::DType` must be one of: `int32_t`, `uint32_t`, `float`, `int16_t`, `uint16_t`, `half`. + - Tile layout must be row-major (`TileData::isRowMajor`). + - Tile location must be vector (`TileData::Loc == TileType::Vec`). + - Static valid bounds: `TileData::ValidRow <= TileData::Rows` and `TileData::ValidCol <= TileData::Cols`. + - Runtime: `src0`, `src1` and `dst` tiles should have the same `validRow/validCol`. +- **Valid region**: + - The op uses `dst.GetValidRow()` / `dst.GetValidCol()` as the iteration domain;. +- **Division-by-zero**: + - Behavior is target-defined. + +## Examples + +### Auto + +```cpp +#include + +using namespace pto; + +void example_auto() { + using TileT = Tile; + TileT src0, src1, dst; + TDIV(dst, src0, src1); +} +``` + +### Manual + +```cpp +#include + +using namespace pto; + +void example_manual() { + using TileT = Tile; + TileT src0, src1, dst; + TASSIGN(src0, 0x1000); + TASSIGN(src1, 0x2000); + TASSIGN(dst, 0x3000); + TDIV(dst, src0, src1); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.tdiv %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tdiv %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = tdiv %src0, %src1 : !pto.tile<...> +# AS Level 2 (DPS) +pto.tdiv ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TDIVS.md b/designs/outerCube/PTOISA/TDIVS.md new file mode 100644 index 00000000..23905d8d --- /dev/null +++ b/designs/outerCube/PTOISA/TDIVS.md @@ -0,0 +1,155 @@ +# TDIVS + + +## Tile Operation Diagram + +![TDIVS tile operation](../figures/isa/TDIVS.svg) + +## Introduction + +Elementwise division with a scalar (tile/scalar or scalar/tile). + +## Math Interpretation + +For each element `(i, j)` in the valid region: + +- Tile/scalar: + + $$ \mathrm{dst}_{i,j} = \frac{\mathrm{src}_{i,j}}{\mathrm{scalar}} $$ + +- Scalar/tile: + + $$ \mathrm{dst}_{i,j} = \frac{\mathrm{scalar}}{\mathrm{src}_{i,j}} $$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Tile/scalar form: + +```text +%dst = tdivs %src, %scalar : !pto.tile<...>, f32 +``` + +Scalar/tile form: + +```text +%dst = tdivs %scalar, %src : f32, !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tdivs %src, %scalar : (!pto.tile<...>, dtype) -> !pto.tile<...> +%dst = pto.tdivs %scalar, %src : (dtype, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tdivs ins(%src, %scalar : !pto.tile_buf<...>, dtype) outs(%dst : !pto.tile_buf<...>) +pto.tdivs ins(%scalar, %src : dtype, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### IR Level 1 (SSA) + +```text +%dst = pto.tdivs %src, %scalar : (!pto.tile<...>, dtype) -> !pto.tile<...> +%dst = pto.tdivs %scalar, %src : (dtype, !pto.tile<...>) -> !pto.tile<...> +``` + +### IR Level 2 (DPS) + +```text +pto.tdivs ins(%src, %scalar : !pto.tile_buf<...>, dtype) outs(%dst : !pto.tile_buf<...>) +pto.tdivs ins(%scalar, %src : dtype, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TDIVS(TileDataDst &dst, TileDataSrc &src0, typename TileDataSrc::DType scalar, WaitEvents &... events); + +template +PTO_INST RecordEvent TDIVS(TileDataDst &dst, typename TileDataDst::DType scalar, TileDataSrc &src0, WaitEvents &... events); +``` + +## Constraints + +- **Implementation checks (A2A3)** (both overloads): + - `TileData::DType` must be one of: `int32_t`, `int`, `int16_t`, `half`, `float16_t`, `float`, `float32_t`. + - Tile location must be vector (`TileData::Loc == TileType::Vec`). + - Static valid bounds: `TileData::ValidRow <= TileData::Rows` and `TileData::ValidCol <= TileData::Cols`. + - Runtime: `src0.GetValidRow() == dst.GetValidRow()` and `src0.GetValidCol() == dst.GetValidCol()`. + - Tile layout must be row-major (`TileData::isRowMajor`). +- **Implementation checks (A5)** (both overloads): + - `TileData::DType` must be one of: `uint8_t`, `int8_t`, `uint16_t`, `int16_t`, `uint32_t`, `int32_t`, `half`, `float`. + - Tile location must be vector (`TileData::Loc == TileType::Vec`). + - Static valid bounds: `TileData::ValidRow <= TileData::Rows` and `TileData::ValidCol <= TileData::Cols`. + - Runtime: `src0.GetValidRow() == dst.GetValidRow()` and `src0.GetValidCol() == dst.GetValidCol()`. + - Tile layout must be row-major (`TileData::isRowMajor`). +- **Valid region**: + - The op uses `dst.GetValidRow()` / `dst.GetValidCol()` as the iteration domain. +- **Division-by-zero**: + - Behavior is target-defined; on A5 the tile/scalar form maps to multiply-by-reciprocal and uses `1/0 -> +inf` for `scalar == 0`. + +## Examples + +### Auto + +```cpp +#include + +using namespace pto; + +void example_auto() { + using TileT = Tile; + TileT src, dst; + TDIVS(dst, src, 2.0f); +} +``` + +### Manual + +```cpp +#include + +using namespace pto; + +void example_manual() { + using TileT = Tile; + TileT src, dst; + TASSIGN(src, 0x1000); + TASSIGN(dst, 0x2000); + TDIVS(dst, 2.0f, src); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.tdivs %src, %scalar : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tdivs %src, %scalar : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = pto.tdivs %src, %scalar : (!pto.tile<...>, dtype) -> !pto.tile<...> +# AS Level 2 (DPS) +pto.tdivs ins(%src, %scalar : !pto.tile_buf<...>, dtype) outs(%dst : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TDIVS_zh.md b/designs/outerCube/PTOISA/TDIVS_zh.md new file mode 100644 index 00000000..060f5c64 --- /dev/null +++ b/designs/outerCube/PTOISA/TDIVS_zh.md @@ -0,0 +1,128 @@ +# TDIVS + +## 指令示意图 + +![TDIVS tile operation](../figures/isa/TDIVS.svg) + +## 简介 + +与标量的逐元素除法（Tile/标量 或 标量/Tile）。 + +## 数学语义 + +对每个元素 `(i, j)` 在有效区域内： + +- Tile/scalar: + + $$ \mathrm{dst}_{i,j} = \frac{\mathrm{src}_{i,j}}{\mathrm{scalar}} $$ + +- Scalar/tile: + + $$ \mathrm{dst}_{i,j} = \frac{\mathrm{scalar}}{\mathrm{src}_{i,j}} $$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS Specification](../assembly/PTO-AS.md). + +Tile/scalar form: + +```text +%dst = tdivs %src, %scalar : !pto.tile<...>, f32 +``` + +Scalar/tile form: + +```text +%dst = tdivs %scalar, %src : f32, !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tdivs %src, %scalar : (!pto.tile<...>, dtype) -> !pto.tile<...> +%dst = pto.tdivs %scalar, %src : (dtype, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tdivs ins(%src, %scalar : !pto.tile_buf<...>, dtype) outs(%dst : !pto.tile_buf<...>) +pto.tdivs ins(%scalar, %src : dtype, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### AS Level 1（SSA） + +```text +%dst = pto.tdivs %src, %scalar : (!pto.tile<...>, dtype) -> !pto.tile<...> +%dst = pto.tdivs %scalar, %src : (dtype, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.tdivs ins(%src, %scalar : !pto.tile_buf<...>, dtype) outs(%dst : !pto.tile_buf<...>) +pto.tdivs ins(%scalar, %src : dtype, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TDIVS(TileDataDst &dst, TileDataSrc &src0, typename TileDataSrc::DType scalar, WaitEvents &... events); + +template +PTO_INST RecordEvent TDIVS(TileDataDst &dst, typename TileDataDst::DType scalar, TileDataSrc &src0, WaitEvents &... events); +``` + +## 约束 + +- **实现检查 (A2A3)** (both overloads): + - `TileData::DType` must be one of: `int32_t`, `int`, `int16_t`, `half`, `float16_t`, `float`, `float32_t`. + - Tile location must be vector (`TileData::Loc == TileType::Vec`). + - Static valid bounds: `TileData::ValidRow <= TileData::Rows` and `TileData::ValidCol <= TileData::Cols`. + - Runtime: `src0.GetValidRow() == dst.GetValidRow()` and `src0.GetValidCol() == dst.GetValidCol()`. + - Tile 布局 must be row-major (`TileData::isRowMajor`). +- **实现检查 (A5)** (both overloads): + - `TileData::DType` must be one of: `uint8_t`, `int8_t`, `uint16_t`, `int16_t`, `uint32_t`, `int32_t`, `half`, `float`. + - Tile location must be vector (`TileData::Loc == TileType::Vec`). + - Static valid bounds: `TileData::ValidRow <= TileData::Rows` and `TileData::ValidCol <= TileData::Cols`. + - Runtime: `src0.GetValidRow() == dst.GetValidRow()` and `src0.GetValidCol() == dst.GetValidCol()`. + - Tile 布局 must be row-major (`TileData::isRowMajor`). +- **有效区域**: + - The op uses `dst.GetValidRow()` / `dst.GetValidCol()` as the iteration domain. +- **Division-by-zero**: + - Behavior is target-defined; on A5 the tile/scalar form maps to multiply-by-reciprocal and uses `1/0 -> +inf` for `scalar == 0`. + +## 示例 + +### 自动（Auto） + +```cpp +#include + +using namespace pto; + +void example_auto() { + using TileT = Tile; + TileT src, dst; + TDIVS(dst, src, 2.0f); +} +``` + +### 手动（Manual） + +```cpp +#include + +using namespace pto; + +void example_manual() { + using TileT = Tile; + TileT src, dst; + TASSIGN(src, 0x1000); + TASSIGN(dst, 0x2000); + TDIVS(dst, 2.0f, src); +} +``` diff --git a/designs/outerCube/PTOISA/TDIV_zh.md b/designs/outerCube/PTOISA/TDIV_zh.md new file mode 100644 index 00000000..c9d13a40 --- /dev/null +++ b/designs/outerCube/PTOISA/TDIV_zh.md @@ -0,0 +1,110 @@ +# TDIV + +## 指令示意图 + +![TDIV tile operation](../figures/isa/TDIV.svg) + +## 简介 + +两个 Tile 的逐元素除法。 + +## 数学语义 + +对每个元素 `(i, j)` 在有效区域内： + +$$ \mathrm{dst}_{i,j} = \frac{\mathrm{src0}_{i,j}}{\mathrm{src1}_{i,j}} $$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS Specification](../assembly/PTO-AS.md). + +同步形式： + +```text +%dst = tdiv %src0, %src1 : !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tdiv %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tdiv ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### AS Level 1（SSA） + +```text +%dst = pto.tdiv %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.tdiv ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TDIV(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, WaitEvents &... events); +``` + +## 约束 + +- **实现检查 (A2A3)**: + - `TileData::DType` must be one of: `half`, `float`. + - Tile 布局 must be row-major (`TileData::isRowMajor`). + - Tile location must be vector (`TileData::Loc == TileType::Vec`). + - Static valid bounds: `TileData::ValidRow <= TileData::Rows` and `TileData::ValidCol <= TileData::Cols`. + - Runtime: `src0`, `src1` and `dst` tiles should have the same `validRow/validCol`. +- **实现检查 (A5)**: + - `TileData::DType` must be one of: `int32_t`, `uint32_t`, `float`, `int16_t`, `uint16_t`, `half`. + - Tile 布局 must be row-major (`TileData::isRowMajor`). + - Tile location must be vector (`TileData::Loc == TileType::Vec`). + - Static valid bounds: `TileData::ValidRow <= TileData::Rows` and `TileData::ValidCol <= TileData::Cols`. + - Runtime: `src0`, `src1` and `dst` tiles should have the same `validRow/validCol`. +- **有效区域**: + - The op uses `dst.GetValidRow()` / `dst.GetValidCol()` as the iteration domain;. +- **Division-by-zero**: + - Behavior is target-defined. + +## 示例 + +### 自动（Auto） + +```cpp +#include + +using namespace pto; + +void example_auto() { + using TileT = Tile; + TileT src0, src1, dst; + TDIV(dst, src0, src1); +} +``` + +### 手动（Manual） + +```cpp +#include + +using namespace pto; + +void example_manual() { + using TileT = Tile; + TileT src0, src1, dst; + TASSIGN(src0, 0x1000); + TASSIGN(src1, 0x2000); + TASSIGN(dst, 0x3000); + TDIV(dst, src0, src1); +} +``` diff --git a/designs/outerCube/PTOISA/TEXP.md b/designs/outerCube/PTOISA/TEXP.md new file mode 100644 index 00000000..f4abc35a --- /dev/null +++ b/designs/outerCube/PTOISA/TEXP.md @@ -0,0 +1,128 @@ +# TEXP + + +## Tile Operation Diagram + +![TEXP tile operation](../figures/isa/TEXP.svg) + +## Introduction + +Elementwise exponential. + +## Math Interpretation + +For each element `(i, j)` in the valid region: + +$$ \mathrm{dst}_{i,j} = \exp(\mathrm{src}_{i,j}) $$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = texp %src : !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.texp %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.texp ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### IR Level 1 (SSA) + +```text +%dst = pto.texp %src : !pto.tile<...> -> !pto.tile<...> +``` + +### IR Level 2 (DPS) + +```text +pto.texp ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TEXP(TileDataDst &dst, TileDataSrc &src, WaitEvents &... events); +``` + +## Constraints + +- **Implementation checks (NPU)**: + - `TileData::DType` must be one of: `float` or `half`; + - Tile location must be vector (`TileData::Loc == TileType::Vec`); + - Static valid bounds: `TileData::ValidRow <= TileData::Rows` and `TileData::ValidCol <= TileData::Cols`; + - Runtime: `src.GetValidRow() == dst.GetValidRow()` and `src.GetValidCol() == dst.GetValidCol()`; + - Tile layout must be row-major (`TileData::isRowMajor`). +- **Valid region**: + - The op uses `dst.GetValidRow()` / `dst.GetValidCol()` as the iteration domain. + +## Examples + +### Auto + +```cpp +#include + +using namespace pto; + +void example_auto() { + using TileT = Tile; + TileT src, dst; + TEXP(dst, src); +} +``` + +### Manual + +```cpp +#include + +using namespace pto; + +void example_manual() { + using TileT = Tile; + TileT src, dst; + TASSIGN(src, 0x1000); + TASSIGN(dst, 0x2000); + TEXP(dst, src); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.texp %src : !pto.tile<...> -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.texp %src : !pto.tile<...> -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = texp %src : !pto.tile<...> +# AS Level 2 (DPS) +pto.texp ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TEXPANDS.md b/designs/outerCube/PTOISA/TEXPANDS.md new file mode 100644 index 00000000..2fa9271d --- /dev/null +++ b/designs/outerCube/PTOISA/TEXPANDS.md @@ -0,0 +1,146 @@ +# TEXPANDS + +## Tile Operation Diagram + +![TEXPANDS tile operation](../figures/isa/TEXPANDS.svg) + +## Introduction + +Broadcast a scalar into a destination tile. + +## Math Interpretation + +For each element `(i, j)` in the valid region: + +$$ \mathrm{dst}_{i,j} = \mathrm{scalar} $$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = texpands %scalar : f32, !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.texpands %scalar : dtype -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.texpands ins(%scalar : dtype) outs(%dst : !pto.tile_buf<...>) +``` + +### IR Level 1 (SSA) + +```text +%dst = pto.texpands %scalar : dtype -> !pto.tile<...> +``` + +### IR Level 2 (DPS) + +```text +pto.texpands ins(%scalar : dtype) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TEXPANDS(TileData &dst, typename TileData::DType scalar, WaitEvents &... events); +``` + +## Constraints + +- **Implementation checks (A2A3)**: + - For `TileType::Vec`: + - `TileData::DType` must be one of: `uint8_t`, `int8_t`, `uint16_t`, `int16_t`, `uint32_t`, `int32_t`, `half`, `bfloat16_t`, `float`. + - Row-major and col-major vector tiles are both supported. + - Static valid bounds: `TileData::ValidRow <= TileData::Rows` and `TileData::ValidCol <= TileData::Cols`. + - For `TileType::Mat`: + - `TileData::DType` must be one of: `uint8_t`, `int8_t`, `uint16_t`, `int16_t`, `uint32_t`, `int32_t`, `half`, `bfloat16_t`, `float`. + - Static valid bounds: `TileData::Rows * TileData::Cols * sizeof(T) / 32` must be in `[1, 32767]`. +- **Implementation checks (A5)**: + - For `TileType::Vec`: + - `TileData::DType` must be one of: `uint8_t`, `int8_t`, `uint16_t`, `int16_t`, `uint32_t`, `int32_t`, `half`, `bfloat16_t`, `float`. + - Row-major and col-major vector tiles are both supported. + - Static valid bounds: `TileData::ValidRow <= TileData::Rows` and `TileData::ValidCol <= TileData::Cols`. + - For `TileType::Mat`: + - `TileData::DType` must be one of: `uint8_t`, `int8_t`, `uint16_t`, `int16_t`, `uint32_t`, `int32_t`, `half`, `bfloat16_t`, `float`. + - For `TileData::layout == pto::Layout::NC1HWC0 || TileData::layout == pto::Layout::FRACTAL_Z`: + - `shape0 * shape1 * shape2 * shape3` must be in `[1, 32767]`. + - For `TileData::layout == pto::Layout::NDC1HWC0 || TileData::layout == pto::Layout::FRACTAL_Z_3D`: + - `shape0 * shape1 * shape2 * shape3 * shape4` must be in `[1, 32767]`. +- **Valid region**: + - For `TileType::Vec`: + - The op fills `dst` over `dst.GetValidRow()` / `dst.GetValidCol()`. + - For `TileType::Mat`: + - For tile operands, the op fills `dst` over `TileData::Rows` / `TileData::Cols`. + - For conv tiles, the op fills `dst` over the conv-tile shape. + +## Examples + +### Auto + +```cpp +#include + +using namespace pto; + +void example_auto() +{ + using TileT = Tile; + TileT dst; + TEXPANDS(dst, 0.0f); +} +``` + +### Manual + +```cpp +#include + +using namespace pto; + +void example_manual() +{ + using TileT = Tile; + TileT dst; + TASSIGN(dst, 0x1000); + TEXPANDS(dst, 0.0f); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.texpands %scalar : dtype -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.texpands %scalar : dtype -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = texpands %scalar : f32, !pto.tile<...> +# AS Level 2 (DPS) +pto.texpands ins(%scalar : dtype) outs(%dst : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TEXPANDS_zh.md b/designs/outerCube/PTOISA/TEXPANDS_zh.md new file mode 100644 index 00000000..63753d2f --- /dev/null +++ b/designs/outerCube/PTOISA/TEXPANDS_zh.md @@ -0,0 +1,134 @@ +# TEXPANDS + +## 指令示意图 + +![TEXPANDS tile operation](../figures/isa/TEXPANDS.svg) + +## 简介 + +将标量广播到目标 Tile 中。 + +## 数学语义 + +对每个元素 `(i, j)` 在有效区域内： + +$$ \mathrm{dst}_{i,j} = \mathrm{scalar} $$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS 规范](../assembly/PTO-AS_zh.md)。 + +同步形式： + +```text +%dst = texpands %scalar : f32, !pto.tile<...> +``` + +### AS Level 1（SSA） + +```text +%dst = pto.texpands %scalar : dtype -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.texpands ins(%scalar : dtype) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`： + +```cpp +template +PTO_INST RecordEvent TEXPANDS(TileData &dst, typename TileData::DType scalar, WaitEvents &... events); +``` + +## 约束 + +- **实现检查（A2A3）**： + - 对于 `TileType::Vec`： + - `TileData::DType` 必须是以下之一：`uint8_t`、`int8_t`、`uint16_t`、`int16_t`、`uint32_t`、`int32_t`、`half`、`bfloat16_t`、`float`。 + - 支持行优先和列优先向量 Tile。 + - 静态有效边界：`TileData::ValidRow <= TileData::Rows` 且 `TileData::ValidCol <= TileData::Cols`。 + - 对于 `TileType::Mat`： + - `TileData::DType` 必须是以下之一：`uint8_t`、`int8_t`、`uint16_t`、`int16_t`、`uint32_t`、`int32_t`、`half`、`bfloat16_t`、`float`。 + - 静态有效边界：`TileData::Rows * TileData::Cols * sizeof(T) / 32` 必须在 `[1, 32767]` 范围内。 +- **实现检查（A5）**： + - 对于 `TileType::Vec`： + - `TileData::DType` 必须是以下之一：`uint8_t`、`int8_t`、`uint16_t`、`int16_t`、`uint32_t`、`int32_t`、`half`、`bfloat16_t`、`float`。 + - 支持行优先和列优先向量 Tile。 + - 静态有效边界：`TileData::ValidRow <= TileData::Rows` 且 `TileData::ValidCol <= TileData::Cols`。 + - 对于 `TileType::Mat`： + - `TileData::DType` 必须是以下之一：`uint8_t`、`int8_t`、`uint16_t`、`int16_t`、`uint32_t`、`int32_t`、`half`、`bfloat16_t`、`float`。 + - 对于 `TileData::layout == pto::Layout::NC1HWC0 || TileData::layout == pto::Layout::FRACTAL_Z`： + - `shape0 * shape1 * shape2 * shape3` 必须在 `[1, 32767]` 范围内。 + - 对于 `TileData::layout == pto::Layout::NDC1HWC0 || TileData::layout == pto::Layout::FRACTAL_Z_3D`： + - `shape0 * shape1 * shape2 * shape3 * shape4` 必须在 `[1, 32767]` 范围内。 +- **有效区域**： + - 对于 `TileType::Vec`： + - 该操作在 `dst.GetValidRow()` / `dst.GetValidCol()` 上填充 `dst`。 + - 对于 `TileType::Mat`： + - 对于普通 Tile，该操作在 `TileData::Rows` / `TileData::Cols` 上填充 `dst`。 + - 对于 ConvTile，该操作在 conv-tile 的 shape 范围内填充 `dst`。 + +## 示例 + +### 自动（Auto） + +```cpp +#include + +using namespace pto; + +void example_auto() +{ + using TileT = Tile; + TileT dst; + TEXPANDS(dst, 0.0f); +} +``` + +### 手动（Manual） + +```cpp +#include + +using namespace pto; + +void example_manual() +{ + using TileT = Tile; + TileT dst; + TASSIGN(dst, 0x1000); + TEXPANDS(dst, 0.0f); +} +``` + +## 汇编示例（ASM） + +### 自动模式 + +```text +# 自动模式：由编译器/运行时负责资源放置与调度。 +%dst = pto.texpands %scalar : dtype -> !pto.tile<...> +``` + +### 手动模式 + +```text +# 手动模式：先显式绑定资源，再发射指令。 +# 可选（当该指令包含 tile 操作数时）： +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.texpands %scalar : dtype -> !pto.tile<...> +``` + +### PTO 汇编形式 + +```text +%dst = texpands %scalar : f32, !pto.tile<...> +# AS Level 2 (DPS) +pto.texpands ins(%scalar : dtype) outs(%dst : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TEXP_zh.md b/designs/outerCube/PTOISA/TEXP_zh.md new file mode 100644 index 00000000..d871a692 --- /dev/null +++ b/designs/outerCube/PTOISA/TEXP_zh.md @@ -0,0 +1,101 @@ +# TEXP + +## 指令示意图 + +![TEXP tile operation](../figures/isa/TEXP.svg) + +## 简介 + +逐元素指数运算。 + +## 数学语义 + +对每个元素 `(i, j)` 在有效区域内： + +$$ \mathrm{dst}_{i,j} = \exp(\mathrm{src}_{i,j}) $$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS Specification](../assembly/PTO-AS.md). + +同步形式： + +```text +%dst = texp %src : !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.texp %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.texp ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### AS Level 1（SSA） + +```text +%dst = pto.texp %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.texp ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TEXP(TileDataDst &dst, TileDataSrc &src, WaitEvents &... events); +``` + +## 约束 + +- **实现检查 (NPU)**: + - `TileData::DType` must be one of: `float` or `half`; + - Tile location must be vector (`TileData::Loc == TileType::Vec`); + - Static valid bounds: `TileData::ValidRow <= TileData::Rows` and `TileData::ValidCol <= TileData::Cols`; + - Runtime: `src.GetValidRow() == dst.GetValidRow()` and `src.GetValidCol() == dst.GetValidCol()`; + - Tile 布局 must be row-major (`TileData::isRowMajor`). +- **有效区域**: + - The op uses `dst.GetValidRow()` / `dst.GetValidCol()` as the iteration domain. + +## 示例 + +### 自动（Auto） + +```cpp +#include + +using namespace pto; + +void example_auto() { + using TileT = Tile; + TileT src, dst; + TEXP(dst, src); +} +``` + +### 手动（Manual） + +```cpp +#include + +using namespace pto; + +void example_manual() { + using TileT = Tile; + TileT src, dst; + TASSIGN(src, 0x1000); + TASSIGN(dst, 0x2000); + TEXP(dst, src); +} +``` diff --git a/designs/outerCube/PTOISA/TEXTRACT.md b/designs/outerCube/PTOISA/TEXTRACT.md new file mode 100644 index 00000000..957e2e68 --- /dev/null +++ b/designs/outerCube/PTOISA/TEXTRACT.md @@ -0,0 +1,138 @@ +# TEXTRACT + + +## Tile Operation Diagram + +![TEXTRACT tile operation](../figures/isa/TEXTRACT.svg) + +## Introduction + +Extract a sub-tile from a source tile. + +## Math Interpretation + +Conceptually copies a window starting at `(indexRow, indexCol)` from `src` into `dst`. Exact mapping depends on layouts. + +Let `R = dst.GetValidRow()` and `C = dst.GetValidCol()`. For `0 <= i < R` and `0 <= j < C`: + +$$ \mathrm{dst}_{i,j} = \mathrm{src}_{\mathrm{indexRow}+i,\; \mathrm{indexCol}+j} $$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = textract %src[%r0, %r1] : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.textract %src, %idxrow, %idxcol : (!pto.tile<...>, dtype, dtype) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.textract ins(%src, %idxrow, %idxcol : !pto.tile_buf<...>, dtype, dtype) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TEXTRACT(DstTileData &dst, SrcTileData &src, uint16_t indexRow = 0, uint16_t indexCol = 0, WaitEvents &... events); + +template +PTO_INST RecordEvent TEXTRACT(DstTileData &dst, SrcTileData &src, uint16_t indexRow, uint16_t indexCol, WaitEvents &... events); + +template +PTO_INST RecordEvent TEXTRACT(DstTileData &dst, SrcTileData &src, uint64_t preQuantScalar, uint16_t indexRow, uint16_t indexCol, WaitEvents &... events); + +template +PTO_INST RecordEvent TEXTRACT_FP(DstTileData &dst, SrcTileData &src, FpTileData &fp, uint16_t indexRow, uint16_t indexCol, WaitEvents &... events); +``` + +## Constraints + +- **Implementation checks (A2A3)**: + - `DstTileData::DType` must equal `SrcTileData::DType` and must be one of: `int8_t`, `half`, `bfloat16_t`, `float`. + - Source fractal must satisfy: `(SFractal == ColMajor && isRowMajor)` or `(SFractal == RowMajor && !isRowMajor)`. In GEMV scenarios, the source fractal satisfies `(SrcTileData::Rows == 1 && SrcTileData::isRowMajor)` for Left. + - Runtime bounds checks: + - `indexRow + DstTileData::Rows <= SrcTileData::Rows` + - `indexCol + DstTileData::Cols <= SrcTileData::Cols` + - Destination must be `TileType::Left` or `TileType::Right` with a target-supported fractal configuration. +- **Implementation checks (A5)**: + - `DstTileData::DType` must equal `SrcTileData::DType` and must be one of: `int8_t`, `hifloat8_t`, `float8_e5m2_t`, `float8_e4m3_t`, `half`, `bfloat16_t`, `float`, `float4_e2m1x2_t`, `float4_e1m2x2_t`, `float8_e8m0_t`. + - Source fractal must satisfy: `(SFractal == ColMajor && isRowMajor)` or `(SFractal == RowMajor && !isRowMajor)` for Left/Right, In GEMV scenarios, the source fractal satisfies `(SrcTileData::Rows == 1 && SrcTileData::isRowMajor)` for Left. `(SFractal == RowMajor && isRowMajor)` for ScaleLeft, `(SFractal == ColMajor && !isRowMajor)` for ScaleRight. + - Destination supports `Mat -> Left/Right/Scale`, `Acc -> Mat` (including relu/scalar-quant/vector-quant forms), and also supports specific `Vec -> Mat` extraction paths. + - The vector-quantized form additionally requires an `FpTileData` scaling operand, matching the `TEXTRACT_FP(...)` interface shown above. + +## Examples + +### Auto + +```cpp +#include + +using namespace pto; + +void example_auto() { + using SrcT = Tile; + using DstT = TileLeft; + SrcT src; + DstT dst; + TEXTRACT(dst, src, /*indexRow=*/0, /*indexCol=*/0); +} +``` + +### Manual + +```cpp +#include + +using namespace pto; + +void example_manual() { + using SrcT = Tile; + using DstT = TileLeft; + SrcT src; + DstT dst; + TASSIGN(src, 0x1000); + TASSIGN(dst, 0x2000); + TEXTRACT(dst, src, /*indexRow=*/0, /*indexCol=*/0); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.textract %src, %idxrow, %idxcol : (!pto.tile<...>, dtype, dtype) -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.textract %src, %idxrow, %idxcol : (!pto.tile<...>, dtype, dtype) -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = textract %src[%r0, %r1] : !pto.tile<...> -> !pto.tile<...> +# AS Level 2 (DPS) +pto.textract ins(%src, %idxrow, %idxcol : !pto.tile_buf<...>, dtype, dtype) outs(%dst : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/TEXTRACT_FP.md b/designs/outerCube/PTOISA/TEXTRACT_FP.md new file mode 100644 index 00000000..757e4a5b --- /dev/null +++ b/designs/outerCube/PTOISA/TEXTRACT_FP.md @@ -0,0 +1,90 @@ +# TEXTRACT_FP + + +## Tile Operation Diagram + +![TEXTRACT_FP tile operation](../figures/isa/TEXTRACT_FP.svg) + +## Introduction + +Extract a sub-tile from a source tile, while also providing an `fp` (scaling) tile used for vector quantization parameters (target/implementation-defined). + +## See also + +- TEXTRACT base instruction: `docs/isa/TEXTRACT.md`. + +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TEXTRACT_FP(DstTileData &dst, SrcTileData &src, FpTileData &fp, uint16_t indexRow, uint16_t indexCol, WaitEvents &... events); +``` + +## Math Interpretation + +Unless otherwise specified, semantics are defined over the valid region and target-dependent behavior is marked as implementation-defined. + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +### AS Level 1 (SSA) + +```text +%dst = pto.textract_fp %src, %idxrow, %idxcol : (!pto.tile<...>, dtype, dtype) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.textract_fp ins(%src, %idxrow, %idxcol : !pto.tile_buf<...>, dtype, dtype) outs(%dst : !pto.tile_buf<...>) +``` + +### IR Level 1 (SSA) + +```text +%dst = pto.textract_fp %src, %idxrow, %idxcol : (!pto.tile<...>, dtype, dtype) -> !pto.tile<...> +``` + +### IR Level 2 (DPS) + +```text +pto.textract_fp ins(%src, %idxrow, %idxcol : !pto.tile_buf<...>, dtype, dtype) outs(%dst : !pto.tile_buf<...>) +``` +## Constraints + +Type/layout/location/shape legality is backend-dependent; treat implementation-specific notes as normative for that backend. + +## Examples + +See related examples in `docs/isa/` and `docs/coding/tutorials/`. + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.textract_fp %src, %idxrow, %idxcol : (!pto.tile<...>, dtype, dtype) -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.textract_fp %src, %idxrow, %idxcol : (!pto.tile<...>, dtype, dtype) -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = pto.textract_fp %src, %idxrow, %idxcol : (!pto.tile<...>, dtype, dtype) -> !pto.tile<...> +# AS Level 2 (DPS) +pto.textract_fp ins(%src, %idxrow, %idxcol : !pto.tile_buf<...>, dtype, dtype) outs(%dst : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TEXTRACT_FP_zh.md b/designs/outerCube/PTOISA/TEXTRACT_FP_zh.md new file mode 100644 index 00000000..9f18d61c --- /dev/null +++ b/designs/outerCube/PTOISA/TEXTRACT_FP_zh.md @@ -0,0 +1,59 @@ +# TEXTRACT_FP + +## 指令示意图 + +![TEXTRACT_FP tile operation](../figures/isa/TEXTRACT_FP.svg) + +## 简介 + +带 fp/缩放 Tile 的提取（向量量化参数）。 + +## 数学语义 + +除非另有说明, semantics are defined over the valid region and target-dependent behavior is marked as implementation-defined. + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS Specification](../assembly/PTO-AS.md). + +### AS Level 1 (SSA) + +```text +%dst = pto.textract_fp %src, %idxrow, %idxcol : (!pto.tile<...>, dtype, dtype) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.textract_fp ins(%src, %idxrow, %idxcol : !pto.tile_buf<...>, dtype, dtype) outs(%dst : !pto.tile_buf<...>) +``` + +### AS Level 1（SSA） + +```text +%dst = pto.textract_fp %src, %idxrow, %idxcol : (!pto.tile<...>, dtype, dtype) -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.textract_fp ins(%src, %idxrow, %idxcol : !pto.tile_buf<...>, dtype, dtype) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TEXTRACT_FP(DstTileData &dst, SrcTileData &src, FpTileData &fp, uint16_t indexRow, uint16_t indexCol, WaitEvents &... events); +``` + +## 约束 + +Type/layout/location/shape legality is backend-dependent; treat implementation-specific notes as normative for that backend. + +## 示例 + +See related examples in `docs/isa/` and `docs/coding/tutorials/`. diff --git a/designs/outerCube/PTOISA/TEXTRACT_zh.md b/designs/outerCube/PTOISA/TEXTRACT_zh.md new file mode 100644 index 00000000..827a6046 --- /dev/null +++ b/designs/outerCube/PTOISA/TEXTRACT_zh.md @@ -0,0 +1,138 @@ +# TEXTRACT + +## 指令示意图 + +![TEXTRACT tile operation](../figures/isa/TEXTRACT.svg) + +## 简介 + +从源 Tile 中提取子 Tile。 + +## 数学语义 + +概念上从 `src` 中复制从 `(indexRow, indexCol)` 开始的窗口到 `dst`。确切的映射取决于布局。 + +设 `R = dst.GetValidRow()` 和 `C = dst.GetValidCol()`。对于 `0 <= i < R` 和 `0 <= j < C`： + +$$ \mathrm{dst}_{i,j} = \mathrm{src}_{\mathrm{indexRow}+i,\; \mathrm{indexCol}+j} $$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS 规范](../assembly/PTO-AS_zh.md)。 + +同步形式： + +```text +%dst = textract %src[%r0, %r1] : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 1（SSA） + +```text +%dst = pto.textract %src, %idxrow, %idxcol : (!pto.tile<...>, dtype, dtype) -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.textract ins(%src, %idxrow, %idxcol : !pto.tile_buf<...>, dtype, dtype) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`： + +```cpp +template +PTO_INST RecordEvent TEXTRACT(DstTileData &dst, SrcTileData &src, uint16_t indexRow = 0, uint16_t indexCol = 0, WaitEvents &... events); + +template +PTO_INST RecordEvent TEXTRACT(DstTileData &dst, SrcTileData &src, uint16_t indexRow, uint16_t indexCol, WaitEvents &... events); + +template +PTO_INST RecordEvent TEXTRACT(DstTileData &dst, SrcTileData &src, uint64_t preQuantScalar, uint16_t indexRow, uint16_t indexCol, WaitEvents &... events); + +template +PTO_INST RecordEvent TEXTRACT_FP(DstTileData &dst, SrcTileData &src, FpTileData &fp, uint16_t indexRow, uint16_t indexCol, WaitEvents &... events); +``` + +## 约束 + +- **实现检查 (A2A3)**: + - `DstTileData::DType` 必须等于 `SrcTileData::DType` 且必须是以下之一：`int8_t`、`half`、`bfloat16_t`、`float`。 + - 源分形必须满足：`(SFractal == ColMajor && isRowMajor)` 或 `(SFractal == RowMajor && !isRowMajor)`，GEMV场景中，目标为Left时，源分形满足`(SrcTileData::Rows == 1 && SrcTileData::isRowMajor)` + - 运行时边界检查： + - `indexRow + DstTileData::Rows <= SrcTileData::Rows` + - `indexCol + DstTileData::Cols <= SrcTileData::Cols` + - 目标必须是 `TileType::Left` 或 `TileType::Right`，具有目标支持的分形配置。 +- **实现检查 (A5)**: + - `DstTileData::DType` 必须等于 `SrcTileData::DType` 且必须是以下之一：`int8_t`、`hifloat8_t`、`float8_e5m2_t`、`float8_e4m3_t`、`half`、`bfloat16_t`、`float`、`float4_e2m1x2_t`、`float4_e1m2x2_t`、`float8_e8m0_t`。 + - 源分形必须满足：对于 Left/Right 为 `(SFractal == ColMajor && isRowMajor)` 或 `(SFractal == RowMajor && !isRowMajor)`，GEMV场景中，目标为Left时，源分形满足`(SrcTileData::Rows == 1 && SrcTileData::isRowMajor)`；对于 ScaleLeft 为 `(SFractal == RowMajor && isRowMajor)`，对于 ScaleRight 为 `(SFractal == ColMajor && !isRowMajor)`。 + - 目标支持 `Mat -> Left/Right/Scale`、`Acc -> Mat`（含 relu / 标量量化 / 向量量化形式），也支持特定 tile 位置的 `Vec -> Mat` 提取路径。 + - 向量量化形式额外要求提供 `FpTileData` 缩放操作数，对应上文展示的 `TEXTRACT_FP(...)` 接口。 + +## 示例 + +### 自动（Auto） + +```cpp +#include + +using namespace pto; + +void example_auto() { + using SrcT = Tile; + using DstT = TileLeft; + SrcT src; + DstT dst; + TEXTRACT(dst, src, /*indexRow=*/0, /*indexCol=*/0); +} +``` + +### 手动（Manual） + +```cpp +#include + +using namespace pto; + +void example_manual() { + using SrcT = Tile; + using DstT = TileLeft; + SrcT src; + DstT dst; + TASSIGN(src, 0x1000); + TASSIGN(dst, 0x2000); + TEXTRACT(dst, src, /*indexRow=*/0, /*indexCol=*/0); +} +``` + +## 汇编示例（ASM） + +### 自动模式 + +```text +# 自动模式：由编译器/运行时负责资源放置与调度。 +%dst = pto.textract %src, %idxrow, %idxcol : (!pto.tile<...>, dtype, dtype) -> !pto.tile<...> +``` + +### 手动模式 + +```text +# 手动模式：先显式绑定资源，再发射指令。 +# 可选（当该指令包含 tile 操作数时）： +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.textract %src, %idxrow, %idxcol : (!pto.tile<...>, dtype, dtype) -> !pto.tile<...> +``` + +### PTO 汇编形式 + +```text +%dst = textract %src[%r0, %r1] : !pto.tile<...> -> !pto.tile<...> +# AS Level 2 (DPS) +pto.textract ins(%src, %idxrow, %idxcol : !pto.tile_buf<...>, dtype, dtype) outs(%dst : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/TFILLPAD.md b/designs/outerCube/PTOISA/TFILLPAD.md new file mode 100644 index 00000000..b670bb02 --- /dev/null +++ b/designs/outerCube/PTOISA/TFILLPAD.md @@ -0,0 +1,133 @@ +# TFILLPAD + + +## Tile Operation Diagram + +![TFILLPAD tile operation](../figures/isa/TFILLPAD.svg) + +## Introduction + +Copy a source tile into a destination tile and fill the remaining (padded) elements with a compile-time pad value +selected by `TileDataDst::PadVal` (e.g., `PadValue::Min`/`PadValue::Max`). + +This is commonly used to materialize deterministic values outside the runtime valid region so that subsequent ops can +operate on a full static tile shape. + +## Math Interpretation + +Let `VR = src.GetValidRow()` and `VC = src.GetValidCol()`. For each destination element `(i, j)`: + +$$ +\mathrm{dst}_{i,j} = +\begin{cases} +\mathrm{src}_{i,j} & \text{if } i < VR \text{ and } j < VC \\ +\mathrm{pad} & \text{otherwise} +\end{cases} +$$ + +`pad` is determined by `TileDataDst::PadVal` and the element type (e.g., `+inf/-inf` for floating types when available, +otherwise `std::numeric_limits::max()/min()`). + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form (conceptual): + +```text +%dst = tfillpad %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tfillpad %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tfillpad ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### IR Level 1 (SSA) + +```text +%dst = pto.tfillpad %src : !pto.tile<...> -> !pto.tile<...> +``` + +### IR Level 2 (DPS) + +```text +pto.tfillpad ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Implemented in the backend headers pulled in by `include/pto/common/pto_instr_impl.hpp`: + +```cpp +template +PTO_INST RecordEvent TFILLPAD(TileData &dst, TileData &src, WaitEvents &... events); + +template +PTO_INST RecordEvent TFILLPAD(DstTileData &dst, SrcTileData &src, WaitEvents &... events); +``` + +## Constraints + +- `TileDataDst::PadVal != PadValue::Null`. +- `sizeof(TileDataDst::DType) == sizeof(TileDataSrc::DType)` and element size must be `1`, `2`, or `4` bytes. +- `TFILLPAD`: `TileDataDst::Rows/Cols` must match `TileDataSrc::Rows/Cols`. +- `TFILLPAD_EXPAND`: `TileDataDst::Rows >= TileDataSrc::Rows` and `TileDataDst::Cols >= TileDataSrc::Cols`. +- `TFILLPAD(TileData &dst, TileData &src)`:`if TileData::TileType is Mat, layout only support (!TileData::isRowMajor && TileData::Slayout::RowMajor), and PadVal only support PadValue::Zero` + +## Examples + +```cpp +#include + +using namespace pto; + +void example1() { + using SrcT = Tile; + using DstT = Tile; + + SrcT src; + DstT dst; + TFILLPAD(dst, src); +} + +void example2() { + using TileMatData = Tile; + + TileMatData matTile; + TFILLPAD(matTile, matTile); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.tfillpad %src : !pto.tile<...> -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tfillpad %src : !pto.tile<...> -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = pto.tfillpad %src : !pto.tile<...> -> !pto.tile<...> +# AS Level 2 (DPS) +pto.tfillpad ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TFILLPAD_EXPAND.md b/designs/outerCube/PTOISA/TFILLPAD_EXPAND.md new file mode 100644 index 00000000..e8d59a45 --- /dev/null +++ b/designs/outerCube/PTOISA/TFILLPAD_EXPAND.md @@ -0,0 +1,89 @@ +# TFILLPAD_EXPAND + + +## Tile Operation Diagram + +![TFILLPAD_EXPAND tile operation](../figures/isa/TFILLPAD_EXPAND.svg) + +## Introduction + +Expand fill/pad variant of TFILLPAD (allows dst to be larger than src; implementation-defined). + +## See also + +- TFILLPAD overview and constraints: `docs/isa/TFILLPAD.md`. + +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TFILLPAD_EXPAND(DstTileData &dst, SrcTileData &src, WaitEvents &... events); +``` + +## Math Interpretation + +Unless otherwise specified, semantics are defined over the valid region and target-dependent behavior is marked as implementation-defined. + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +### AS Level 1 (SSA) + +```text +%dst = pto.tfillpad_expand %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tfillpad_expand ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### IR Level 1 (SSA) + +```text +%dst = pto.tfillpad_expand %src : !pto.tile<...> -> !pto.tile<...> +``` + +### IR Level 2 (DPS) + +```text +pto.tfillpad_expand ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## Constraints + +Type/layout/location/shape legality is backend-dependent; treat implementation-specific notes as normative for that backend. + +## Examples + +See related examples in `docs/isa/` and `docs/coding/tutorials/`. + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.tfillpad_expand %src : !pto.tile<...> -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tfillpad_expand %src : !pto.tile<...> -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = pto.tfillpad_expand %src : !pto.tile<...> -> !pto.tile<...> +# AS Level 2 (DPS) +pto.tfillpad_expand ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TFILLPAD_EXPAND_zh.md b/designs/outerCube/PTOISA/TFILLPAD_EXPAND_zh.md new file mode 100644 index 00000000..1711c218 --- /dev/null +++ b/designs/outerCube/PTOISA/TFILLPAD_EXPAND_zh.md @@ -0,0 +1,58 @@ +# TFILLPAD_EXPAND + +## 指令示意图 + +![TFILLPAD_EXPAND tile operation](../figures/isa/TFILLPAD_EXPAND.svg) + +## 简介 + +填充/填充时允许目标大于源。 + +## 数学语义 + +除非另有说明, semantics are defined over the valid region and target-dependent behavior is marked as implementation-defined. + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS Specification](../assembly/PTO-AS.md). + +### AS Level 1 (SSA) + +```text +%dst = pto.tfillpad_expand %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tfillpad_expand ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### AS Level 1（SSA） + +```text +%dst = pto.tfillpad_expand %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.tfillpad_expand ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TFILLPAD_EXPAND(DstTileData &dst, SrcTileData &src, WaitEvents &... events); +``` + +## 约束 + +Type/layout/location/shape legality is backend-dependent; treat implementation-specific notes as normative for that backend. + +## 示例 + +See related examples in `docs/isa/` and `docs/coding/tutorials/`. diff --git a/designs/outerCube/PTOISA/TFILLPAD_INPLACE.md b/designs/outerCube/PTOISA/TFILLPAD_INPLACE.md new file mode 100644 index 00000000..29134773 --- /dev/null +++ b/designs/outerCube/PTOISA/TFILLPAD_INPLACE.md @@ -0,0 +1,89 @@ +# TFILLPAD_INPLACE + + +## Tile Operation Diagram + +![TFILLPAD_INPLACE tile operation](../figures/isa/TFILLPAD_INPLACE.svg) + +## Introduction + +In-place fill/pad variant of TFILLPAD (implementation-defined). + +## See also + +- TFILLPAD overview and constraints: `docs/isa/TFILLPAD.md`. + +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TFILLPAD_INPLACE(DstTileData &dst, SrcTileData &src, WaitEvents &... events); +``` + +## Math Interpretation + +Unless otherwise specified, semantics are defined over the valid region and target-dependent behavior is marked as implementation-defined. + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +### AS Level 1 (SSA) + +```text +%dst = pto.tfillpad_inplace %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tfillpad_inplace ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### IR Level 1 (SSA) + +```text +%dst = pto.tfillpad_inplace %src : !pto.tile<...> -> !pto.tile<...> +``` + +### IR Level 2 (DPS) + +```text +pto.tfillpad_inplace ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## Constraints + +Type/layout/location/shape legality is backend-dependent; treat implementation-specific notes as normative for that backend. + +## Examples + +See related examples in `docs/isa/` and `docs/coding/tutorials/`. + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.tfillpad_inplace %src : !pto.tile<...> -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tfillpad_inplace %src : !pto.tile<...> -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = pto.tfillpad_inplace %src : !pto.tile<...> -> !pto.tile<...> +# AS Level 2 (DPS) +pto.tfillpad_inplace ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TFILLPAD_INPLACE_zh.md b/designs/outerCube/PTOISA/TFILLPAD_INPLACE_zh.md new file mode 100644 index 00000000..9900b46f --- /dev/null +++ b/designs/outerCube/PTOISA/TFILLPAD_INPLACE_zh.md @@ -0,0 +1,58 @@ +# TFILLPAD_INPLACE + +## 指令示意图 + +![TFILLPAD_INPLACE tile operation](../figures/isa/TFILLPAD_INPLACE.svg) + +## 简介 + +原地填充/填充变体。 + +## 数学语义 + +除非另有说明, semantics are defined over the valid region and target-dependent behavior is marked as implementation-defined. + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS Specification](../assembly/PTO-AS.md). + +### AS Level 1 (SSA) + +```text +%dst = pto.tfillpad_inplace %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tfillpad_inplace ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### AS Level 1（SSA） + +```text +%dst = pto.tfillpad_inplace %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.tfillpad_inplace ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TFILLPAD_INPLACE(DstTileData &dst, SrcTileData &src, WaitEvents &... events); +``` + +## 约束 + +Type/layout/location/shape legality is backend-dependent; treat implementation-specific notes as normative for that backend. + +## 示例 + +See related examples in `docs/isa/` and `docs/coding/tutorials/`. diff --git a/designs/outerCube/PTOISA/TFILLPAD_zh.md b/designs/outerCube/PTOISA/TFILLPAD_zh.md new file mode 100644 index 00000000..d6975b6f --- /dev/null +++ b/designs/outerCube/PTOISA/TFILLPAD_zh.md @@ -0,0 +1,108 @@ +# TFILLPAD + +## 指令示意图 + +![TFILLPAD tile operation](../figures/isa/TFILLPAD.svg) + +## 简介 + +复制 Tile 并在有效区域外使用编译时填充值进行填充。 + +Copy a source tile into a destination tile and fill the remaining (padded) elements with a compile-time pad value +selected by `TileDataDst::PadVal` (e.g., `PadValue::Min`/`PadValue::Max`). + +This is commonly used to materialize deterministic values outside the runtime valid region so that subsequent ops can +operate on a full static tile shape. + +## 数学语义 + +Let `VR = src.GetValidRow()` and `VC = src.GetValidCol()`. 对每个 destination element `(i, j)`: + +$$ +\mathrm{dst}_{i,j} = +\begin{cases} +\mathrm{src}_{i,j} & \text{if } i < VR \text{ and } j < VC \\ +\mathrm{pad} & \text{otherwise} +\end{cases} +$$ + +`pad` is determined by `TileDataDst::PadVal` and the element type (e.g., `+inf/-inf` for floating types when available, +otherwise `std::numeric_limits::max()/min()`). + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form (conceptual): + +```text +%dst = tfillpad %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tfillpad %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tfillpad ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### AS Level 1（SSA） + +```text +%dst = pto.tfillpad %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.tfillpad ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +Implemented in the backend headers pulled in by `include/pto/common/pto_instr_impl.hpp`: + +```cpp +template +PTO_INST RecordEvent TFILLPAD(TileData &dst, TileData &src, WaitEvents &... events); + +template +PTO_INST RecordEvent TFILLPAD(DstTileData &dst, SrcTileData &src, WaitEvents &... events); +``` + +## 约束 + +- `TileDataDst::PadVal != PadValue::Null`. +- `sizeof(TileDataDst::DType) == sizeof(TileDataSrc::DType)` and element size must be `1`, `2`, or `4` bytes. +- `TFILLPAD`: `TileDataDst::Rows/Cols` must match `TileDataSrc::Rows/Cols`. +- `TFILLPAD_EXPAND`: `TileDataDst::Rows >= TileDataSrc::Rows` and `TileDataDst::Cols >= TileDataSrc::Cols`. +- `TFILLPAD(TileData &dst, TileData &src)`:`if TileData::TileType is Mat, layout only support (!TileData::isRowMajor && TileData::Slayout::RowMajor), and PadVal only support PadValue::Zero` + +## 示例 + +```cpp +#include + +using namespace pto; + +void example1() { + using SrcT = Tile; + using DstT = Tile; + + SrcT src; + DstT dst; + TFILLPAD(dst, src); +} + +void example2() { + using TileMatData = Tile; + + TileMatData matTile; + TFILLPAD(matTile, matTile); +} +``` diff --git a/designs/outerCube/PTOISA/TFMOD.md b/designs/outerCube/PTOISA/TFMOD.md new file mode 100644 index 00000000..bf647996 --- /dev/null +++ b/designs/outerCube/PTOISA/TFMOD.md @@ -0,0 +1,104 @@ +# TFMOD + + +## Tile Operation Diagram + +![TFMOD tile operation](../figures/isa/TFMOD.svg) + +## Introduction + +Elementwise floor of two tiles. + +## Math Interpretation + +For each element `(i, j)` in the valid region: + +$$\mathrm{dst}_{i,j} = \mathrm{fmod}(\mathrm{src0}_{i,j}, \mathrm{src1}_{i,j})$$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = tfmod %src0, %src1 : !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tfmod %src0, %src1 : !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tfmod ins(%src0, %src1 : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### IR Level 1 (SSA) + +```text +%dst = pto.tfmod %src0, %src1 : !pto.tile<...> +``` + +### IR Level 2 (DPS) + +```text +pto.tfmod ins(%src0, %src1 : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TFMOD(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, WaitEvents &... events); +``` + +## Constraints + +- The op iterates over `dst.GetValidRow()` / `dst.GetValidCol()`. +- Division-by-zero behavior is target-defined; the CPU simulator asserts in debug builds. + +## Examples + +```cpp +#include + +using namespace pto; + +void example() { + using TileT = Tile; + TileT out, a, b; + TFMOD(out, a, b); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.tfmod %src0, %src1 : !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tfmod %src0, %src1 : !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = tfmod %src0, %src1 : !pto.tile<...> +# AS Level 2 (DPS) +pto.tfmod ins(%src0, %src1 : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TFMODS.md b/designs/outerCube/PTOISA/TFMODS.md new file mode 100644 index 00000000..41034bb0 --- /dev/null +++ b/designs/outerCube/PTOISA/TFMODS.md @@ -0,0 +1,107 @@ +# TFMODS + + +## Tile Operation Diagram + +![TFMODS tile operation](../figures/isa/TFMODS.svg) + +## Introduction + +Elementwise floor with a scalar: `fmod(src, scalar)`. + +## Math Interpretation + +For each element `(i, j)` in the valid region: + +$$\mathrm{dst}_{i,j} = \mathrm{fmod}(\mathrm{src}_{i,j}, \mathrm{scalar})$$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = tfmods %src, %scalar : !pto.tile<...>, f32 +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tfmods %src, %scalar : !pto.tile<...>, f32 +``` + +### AS Level 2 (DPS) + +```text +pto.tfmods ins(%src, %scalar : !pto.tile_buf<...>, f32) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TFMODS(TileDataDst &dst, TileDataSrc &src, typename TileDataSrc::DType scalar, WaitEvents &... events); +``` + +## Constraints + +- **Implementation checks (A2A3)**: + - `dst` and `src` must use the same element type. + - Supported element types are `float` and `float32_t`. + - `dst` and `src` must be vector tiles. + - `dst` and `src` must be row-major. + - Runtime: `dst.GetValidRow() == src.GetValidRow() > 0` and `dst.GetValidCol() == src.GetValidCol() > 0`. +- **Implementation checks (A5)**: + - `dst` and `src` must use the same element type. + - Supported element types are 2-byte or 4-byte types supported by the target implementation (including `half` and `float`). + - `dst` and `src` must be vector tiles. + - Static valid bounds must satisfy `ValidRow <= Rows` and `ValidCol <= Cols` for both tiles. + - Runtime: `dst.GetValidRow() == src.GetValidRow()` and `dst.GetValidCol() == src.GetValidCol()`. +- **Division-by-zero**: + - Behavior is target-defined; the CPU simulator asserts in debug builds. +- **Valid region**: + - The op uses `dst.GetValidRow()` / `dst.GetValidCol()` as the iteration domain. + +## Examples + +```cpp +#include + +using namespace pto; + +void example() { + using TileT = Tile; + TileT x, out; + TFMODS(out, x, 3.0f); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.tfmods %src, %scalar : !pto.tile<...>, f32 +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tfmods %src, %scalar : !pto.tile<...>, f32 +``` + +### PTO Assembly Form + +```text +%dst = tfmods %src, %scalar : !pto.tile<...>, f32 +# AS Level 2 (DPS) +pto.tfmods ins(%src, %scalar : !pto.tile_buf<...>, f32) outs(%dst : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/TFMODS_zh.md b/designs/outerCube/PTOISA/TFMODS_zh.md new file mode 100644 index 00000000..4726099f --- /dev/null +++ b/designs/outerCube/PTOISA/TFMODS_zh.md @@ -0,0 +1,107 @@ +# TFMODS + +## 指令示意图 + +![TFMODS tile operation](../figures/isa/TFMODS.svg) + +## 简介 + +与标量的逐元素余数：`fmod(src, scalar)`。 + +## 数学语义 + +对每个元素 `(i, j)` 在有效区域内： + +$$\mathrm{dst}_{i,j} = \mathrm{fmod}(\mathrm{src}_{i,j}, \mathrm{scalar})$$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS 规范](../assembly/PTO-AS_zh.md)。 + +同步形式： + +```text +%dst = tfmods %src, %scalar : !pto.tile<...>, f32 +``` + +### AS Level 1（SSA） + +```text +%dst = pto.tfmods %src, %scalar : !pto.tile<...>, f32 +``` + +### AS Level 2（DPS） + +```text +pto.tfmods ins(%src, %scalar : !pto.tile_buf<...>, f32) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`： + +```cpp +template +PTO_INST RecordEvent TFMODS(TileDataDst &dst, TileDataSrc &src, typename TileDataSrc::DType scalar, WaitEvents &... events); +``` + +## 约束 + +- **实现检查 (A2A3)**: + - `dst` 和 `src` 必须使用相同的元素类型。 + - 支持的元素类型为 `float` 和 `float32_t`。 + - `dst` 和 `src` 必须是向量 Tile。 + - `dst` 和 `src` 必须是行主序。 + - 运行时：`dst.GetValidRow() == src.GetValidRow() > 0` 且 `dst.GetValidCol() == src.GetValidCol() > 0`。 +- **实现检查 (A5)**: + - `dst` 和 `src` 必须使用相同的元素类型。 + - 支持的元素类型为目标实现支持的 2 字节或 4 字节类型（包括 `half` 和 `float`）。 + - `dst` 和 `src` 必须是向量 Tile。 + - 两个 Tile 的静态有效边界都必须满足 `ValidRow <= Rows` 且 `ValidCol <= Cols`。 + - 运行时：`dst.GetValidRow() == src.GetValidRow()` 且 `dst.GetValidCol() == src.GetValidCol()`。 +- **除零**: + - 行为由目标定义；CPU 模拟器在调试构建中会断言。 +- **有效区域**: + - 该操作使用 `dst.GetValidRow()` / `dst.GetValidCol()` 作为迭代域。 + +## 示例 + +```cpp +#include + +using namespace pto; + +void example() { + using TileT = Tile; + TileT x, out; + TFMODS(out, x, 3.0f); +} +``` + +## 汇编示例（ASM） + +### 自动模式 + +```text +# 自动模式：由编译器/运行时负责资源放置与调度。 +%dst = pto.tfmods %src, %scalar : !pto.tile<...>, f32 +``` + +### 手动模式 + +```text +# 手动模式：先显式绑定资源，再发射指令。 +# 可选（当该指令包含 tile 操作数时）： +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tfmods %src, %scalar : !pto.tile<...>, f32 +``` + +### PTO 汇编形式 + +```text +%dst = tfmods %src, %scalar : !pto.tile<...>, f32 +# AS Level 2 (DPS) +pto.tfmods ins(%src, %scalar : !pto.tile_buf<...>, f32) outs(%dst : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/TFMOD_zh.md b/designs/outerCube/PTOISA/TFMOD_zh.md new file mode 100644 index 00000000..1dfe85fa --- /dev/null +++ b/designs/outerCube/PTOISA/TFMOD_zh.md @@ -0,0 +1,77 @@ +# TFMOD + +## 指令示意图 + +![TFMOD tile operation](../figures/isa/TFMOD.svg) + +## 简介 + +两个 Tile 的逐元素余数，余数符号与被除数相同。 + +## 数学语义 + +对每个元素 `(i, j)` 在有效区域内： + +$$\mathrm{dst}_{i,j} = \mathrm{fmod}(\mathrm{src0}_{i,j}, \mathrm{src1}_{i,j})$$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS Specification](../assembly/PTO-AS.md). + +同步形式： + +```text +%dst = tfmod %src0, %src1 : !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tfmod %src0, %src1 : !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tfmod ins(%src0, %src1 : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### AS Level 1（SSA） + +```text +%dst = pto.tfmod %src0, %src1 : !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.tfmod ins(%src0, %src1 : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TFMOD(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, WaitEvents &... events); +``` + +## 约束 + +- The op iterates over `dst.GetValidRow()` / `dst.GetValidCol()`. +- Division-by-zero behavior is target-defined; the CPU simulator asserts in debug builds. + +## 示例 + +```cpp +#include + +using namespace pto; + +void example() { + using TileT = Tile; + TileT out, a, b; + TFMOD(out, a, b); +} +``` diff --git a/designs/outerCube/PTOISA/TFREE.md b/designs/outerCube/PTOISA/TFREE.md new file mode 100644 index 00000000..f13f9709 --- /dev/null +++ b/designs/outerCube/PTOISA/TFREE.md @@ -0,0 +1,40 @@ +# TFREE + +## Tile Operation Diagram + +![TFREE tile operation](../figures/isa/TFREE.svg) + +## Introduction + +Release the currently held pipe or FIFO slot back to the producer. + +## Math Interpretation + +Semantics are instruction-specific. Unless stated otherwise, behavior is defined over the destination valid region. + +## Assembly Syntax + +PTO-AS form: see `docs/assembly/PTO-AS.md`. + +### IR Level 1 (SSA) + +```text +%dst = pto.tfree ... +``` + +### IR Level 2 (DPS) + +```text +pto.tfree ins(...) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`. + +## Constraints + +Refer to backend-specific legality checks for data type/layout/location/shape constraints. + +## Examples + +See related instruction pages in `docs/isa/` for concrete Auto/Manual usage patterns. diff --git a/designs/outerCube/PTOISA/TFREE_zh.md b/designs/outerCube/PTOISA/TFREE_zh.md new file mode 100644 index 00000000..3e7be0d2 --- /dev/null +++ b/designs/outerCube/PTOISA/TFREE_zh.md @@ -0,0 +1,41 @@ +# TFREE + +## 指令示意图 + +![TFREE tile operation](../figures/isa/TFREE.svg) + +## 简介 + +将当前占用的 pipe 或 FIFO 槽位释放回生产者。 + +## 数学语义 + +语义随指令而变化。 Unless stated otherwise, behavior is defined over the destination valid region. + +## 汇编语法 + +PTO-AS 形式：参见 `docs/assembly/PTO-AS.md`. + +### AS Level 1（SSA） + +```text +%dst = pto.tfree ... +``` + +### AS Level 2（DPS） + +```text +pto.tfree ins(...) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`. + +## 约束 + +Refer to backend-specific legality checks for data type/layout/location/shape constraints. + +## 示例 + +See related instruction pages in `docs/isa/` for concrete Auto/Manual usage patterns. diff --git a/designs/outerCube/PTOISA/TGATHER.md b/designs/outerCube/PTOISA/TGATHER.md new file mode 100644 index 00000000..911dfba7 --- /dev/null +++ b/designs/outerCube/PTOISA/TGATHER.md @@ -0,0 +1,156 @@ +# TGATHER + + +## Tile Operation Diagram + +![TGATHER tile operation](../figures/isa/TGATHER.svg) + +## Introduction + +Gather/select elements using either an index tile or a compile-time mask pattern. + +## Math Interpretation + +Index-based gather (conceptual): + +Let `R = dst.GetValidRow()` and `C = dst.GetValidCol()`. For `0 <= i < R` and `0 <= j < C`: + +$$ \mathrm{dst}_{i,j} = \mathrm{src0}\!\left[\mathrm{indices}_{i,j}\right] $$ + +Exact index interpretation and bounds behavior are implementation-defined. + +Mask-pattern gather is an implementation-defined selection/reduction controlled by `pto::MaskPattern`. + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Index-based gather: + +```text +%dst = tgather %src0, %indices : !pto.tile<...> -> !pto.tile<...> +``` + +Mask-pattern gather: + +```text +%dst = tgather %src {maskPattern = #pto.mask_pattern} : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tgather %src, %indices : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +%dst = pto.tgather %src {maskPattern = #pto.mask_pattern}: !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tgather ins(%src, %indices : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +pto.tgather ins(%src, {maskPattern = #pto.mask_pattern} : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TGATHER(TileDataD &dst, TileDataS0 &src0, TileDataS1 &src1, TileDataTmp &tmp, WaitEvents &... events); + +template +PTO_INST RecordEvent TGATHER(DstTileData &dst, SrcTileData &src, WaitEvents &... events); +``` + +## Constraints + +- **Index-based gather: implementation checks (A2A3)**: + - `sizeof(DstTileData::DType)` must be must be `int16_t`, `uint16_t`, `int32_t`, `uint32_t`, `half`, `float`. + - `sizeof(Src1TileData::DType)` must be must be `int32_t`, `uint32_t`. + - `DstTileData::DType` must be the same type as `Src0TileData::DType`. + - `src1.GetValidCol() == Src1TileData::Cols` and `dst.GetValidCol() == DstTileData::Cols`. +- **Index-based gather: implementation checks (A5)**: + - `sizeof(DstTileData::DType)` must be must be `int16_t`, `uint16_t`, `int32_t`, `uint32_t`, `half`, `float`. + - `sizeof(Src1TileData::DType)` must be must be `int16_t`, `uint16_t`, `int32_t`, `uint32_t`. + - `DstTileData::DType` must be the same type as `Src0TileData::DType`. + - `src1.GetValidCol() == Src1TileData::Cols` and `dst.GetValidCol() == DstTileData::Cols`. +- **Mask-pattern gather: implementation checks (A2A3)**: + - Source element size must be `2` or `4` bytes. + - `SrcTileData::DType`/`DstTileData::DType` must be `int16_t` or `uint16_t` or `int32_t` or `uint32_t` + or `half` or `bfloat16_t` or `float`. + - `dst` and `src` must both be `TileType::Vec` and row-major. + - `sizeof(dst element) == sizeof(src element)` and `dst.GetValidCol() == DstTileData::Cols` (continuous dst storage). +- **Mask-pattern gather: implementation checks (A5)**: + - Source element size must be `1` or `2` or `4` bytes. + - `dst` and `src` must both be `TileType::Vec` and row-major. + - `SrcTileData::DType`/`DstTileData::DType` must be `int8_t` or `uint8_t` or `int16_t` or `uint16_t` or `int32_t` or `uint32_t` + or `half` or `bfloat16_t` or `float` or `float8_e4m3_t`or `float8_e5m2_t` or `hifloat8_t`. + - Supported dtypes are restricted to a target-defined set (checked via `static_assert` in the implementation), and `sizeof(dst element) == sizeof(src element)`, `dst.GetValidCol() == DstTileData::Cols` (continuous dst storage). +- **Bounds / validity**: + - Index bounds are not validated by explicit runtime assertions; out-of-range indices are target-defined. + +## Examples + +### Auto + +```cpp +#include + +using namespace pto; + +void example_auto() { + using SrcT = Tile; + using IdxT = Tile; + using DstT = Tile; + SrcT src0; + IdxT idx; + DstT dst; + TGATHER(dst, src0, idx); +} +``` + +### Manual + +```cpp +#include + +using namespace pto; + +void example_manual() { + using SrcT = Tile; + using DstT = Tile; + SrcT src; + DstT dst; + TASSIGN(src, 0x1000); + TASSIGN(dst, 0x2000); + TGATHER(dst, src); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.tgather %src, %indices : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tgather %src, %indices : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = pto.tgather %src, %indices : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +# AS Level 2 (DPS) +pto.tgather ins(%src, %indices : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/TGATHERB.md b/designs/outerCube/PTOISA/TGATHERB.md new file mode 100644 index 00000000..3ee1b4ef --- /dev/null +++ b/designs/outerCube/PTOISA/TGATHERB.md @@ -0,0 +1,141 @@ +# TGATHERB + + +## Tile Operation Diagram + +![TGATHERB tile operation](../figures/isa/TGATHERB.svg) + +## Introduction + +Gather elements using byte offsets. + +## Math Interpretation + +For each element in the valid region: + +$$ \mathrm{dst}_{i,j} = *\left(\mathrm{srcBase} + \mathrm{offset}_{i,j}\right) $$ + +Exact bounds behavior is implementation-defined. + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = tgatherb %src, %offsets : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tgatherb %src, %offsets : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tgatherb ins(%src, %offsets : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### IR Level 1 (SSA) + +```text +%dst = pto.tgatherb %src, %offsets : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### IR Level 2 (DPS) + +```text +pto.tgatherb ins(%src, %offsets : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TGATHERB(TileDataDst &dst, TileDataSrc &src, TileDataOffset &offset, WaitEvents &... events); +``` + +## Constraints + +- **Implementation checks (A2A3)**: + - Destination layout must be row-major (`TileDataDst::isRowMajor`). + - Destination element size must be `1`, `2`, or `4` bytes (enforced via `static_assert` in the helper). + - `SrcTileData::DType`/`DstTileData::DType` must be `int8_t` or `uint8_t` or `int16_t` or `uint16_t` or `int32_t` or `uint32_t` or `half` or `bfloat16_t` or `float`. +- **Implementation checks (A5)**: + - Destination element size must be `1`, `2`, or `4` bytes. + - `SrcTileData::DType`/`DstTileData::DType` must be `int8_t` or `uint8_t` or `int16_t` or `uint16_t` or `int32_t` or `uint32_t` or `half` or `bfloat16_t` or `float`. +- **Offset interpretation**: + - Offsets are interpreted as `uint32_t` values (byte offsets) by the implementation. + - Offset bounds are not validated by explicit runtime assertions; out-of-range offsets are target-defined. + +## Examples + +### Auto + +```cpp +#include + +using namespace pto; + +void example_auto() { + using SrcT = Tile; + using OffT = Tile; + using DstT = Tile; + SrcT src; + OffT off; + DstT dst; + TGATHERB(dst, src, off); +} +``` + +### Manual + +```cpp +#include + +using namespace pto; + +void example_manual() { + using SrcT = Tile; + using OffT = Tile; + using DstT = Tile; + SrcT src; + OffT off; + DstT dst; + TASSIGN(src, 0x1000); + TASSIGN(off, 0x2000); + TASSIGN(dst, 0x3000); + TGATHERB(dst, src, off); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.tgatherb %src, %offsets : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tgatherb %src, %offsets : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = tgatherb %src, %offsets : !pto.tile<...> -> !pto.tile<...> +# AS Level 2 (DPS) +pto.tgatherb ins(%src, %offsets : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TGATHERB_zh.md b/designs/outerCube/PTOISA/TGATHERB_zh.md new file mode 100644 index 00000000..64652ef2 --- /dev/null +++ b/designs/outerCube/PTOISA/TGATHERB_zh.md @@ -0,0 +1,114 @@ +# TGATHERB + +## 指令示意图 + +![TGATHERB tile operation](../figures/isa/TGATHERB.svg) + +## 简介 + +使用字节偏移量收集元素。 + +## 数学语义 + +对每个元素 在有效区域内： + +$$ \mathrm{dst}_{i,j} = *\left(\mathrm{srcBase} + \mathrm{offset}_{i,j}\right) $$ + +Exact bounds behavior is implementation-defined. + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS Specification](../assembly/PTO-AS.md). + +同步形式： + +```text +%dst = tgatherb %src, %offsets : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tgatherb %src, %offsets : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tgatherb ins(%src, %offsets : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### AS Level 1（SSA） + +```text +%dst = pto.tgatherb %src, %offsets : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.tgatherb ins(%src, %offsets : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TGATHERB(TileDataDst &dst, TileDataSrc &src, TileDataOffset &offset, WaitEvents &... events); +``` + +## 约束 + +- **实现检查 (A2A3)**: + - Destination layout must be row-major (`TileDataDst::isRowMajor`). + - Destination element size must be `1`, `2`, or `4` bytes (enforced via `static_assert` in the helper). + - `SrcTileData::DType`/`DstTileData::DType` must be `int8_t` or `uint8_t` or `int16_t` or `uint16_t` or `int32_t` or `uint32_t` or `half` or `bfloat16_t` or `float`. +- **实现检查 (A5)**: + - Destination element size must be `1`, `2`, or `4` bytes. + - `SrcTileData::DType`/`DstTileData::DType` must be `int8_t` or `uint8_t` or `int16_t` or `uint16_t` or `int32_t` or `uint32_t` or `half` or `bfloat16_t` or `float`. +- **Offset interpretation**: + - Offsets are interpreted as `uint32_t` values (byte offsets) by the implementation. + - Offset bounds are not validated by explicit runtime assertions; out-of-range offsets are target-defined. + +## 示例 + +### 自动（Auto） + +```cpp +#include + +using namespace pto; + +void example_auto() { + using SrcT = Tile; + using OffT = Tile; + using DstT = Tile; + SrcT src; + OffT off; + DstT dst; + TGATHERB(dst, src, off); +} +``` + +### 手动（Manual） + +```cpp +#include + +using namespace pto; + +void example_manual() { + using SrcT = Tile; + using OffT = Tile; + using DstT = Tile; + SrcT src; + OffT off; + DstT dst; + TASSIGN(src, 0x1000); + TASSIGN(off, 0x2000); + TASSIGN(dst, 0x3000); + TGATHERB(dst, src, off); +} +``` diff --git a/designs/outerCube/PTOISA/TGATHER_zh.md b/designs/outerCube/PTOISA/TGATHER_zh.md new file mode 100644 index 00000000..731801d2 --- /dev/null +++ b/designs/outerCube/PTOISA/TGATHER_zh.md @@ -0,0 +1,154 @@ +# TGATHER + +## 指令示意图 + +![TGATHER tile operation](../figures/isa/TGATHER.svg) + +## 简介 + +使用索引 Tile 或编译时掩码模式来收集/选择元素。 + +## 数学语义 + +基于索引的 gather（概念性定义）： + +设 `R = dst.GetValidRow()`，`C = dst.GetValidCol()`。对于 `0 <= i < R` 且 `0 <= j < C`： + +$$ \mathrm{dst}_{i,j} = \mathrm{src0}\!\left[\mathrm{indices}_{i,j}\right] $$ + +确切的索引解释和边界行为由实现定义。 + +基于掩码模式的 gather 是由 `pto::MaskPattern` 控制的实现定义的选择/归约操作。 + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS 规范](../assembly/PTO-AS_zh.md)。 + +基于索引的 gather： + +```text +%dst = tgather %src0, %indices : !pto.tile<...> -> !pto.tile<...> +``` + +基于掩码模式的 gather： + +```text +%dst = tgather %src {maskPattern = #pto.mask_pattern} : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 1（SSA） + +```text +%dst = pto.tgather %src, %indices : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +%dst = pto.tgather %src {maskPattern = #pto.mask_pattern}: !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.tgather ins(%src, %indices : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +pto.tgather ins(%src, {maskPattern = #pto.mask_pattern} : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`： + +```cpp +template +PTO_INST RecordEvent TGATHER(TileDataD &dst, TileDataS0 &src0, TileDataS1 &src1, TileDataTmp &tmp, WaitEvents &... events); + +template +PTO_INST RecordEvent TGATHER(DstTileData &dst, SrcTileData &src, WaitEvents &... events); +``` + +## 约束 + +- **基于索引的 gather：实现检查 (A2A3)**: + - `sizeof(DstTileData::DType)` 对应类型必须是 `int16_t`、`uint16_t`、`int32_t`、`uint32_t`、`half`、`float` 之一。 + - `sizeof(Src1TileData::DType)` 对应类型必须是 `int32_t`、`uint32_t` 之一。 + - `DstTileData::DType` 必须与 `Src0TileData::DType` 类型相同。 + - `src1.GetValidCol() == Src1TileData::Cols` 且 `dst.GetValidCol() == DstTileData::Cols`。 +- **基于索引的 gather：实现检查 (A5)**: + - `sizeof(DstTileData::DType)` 对应类型必须是 `int16_t`、`uint16_t`、`int32_t`、`uint32_t`、`half`、`float` 之一。 + - `sizeof(Src1TileData::DType)` 对应类型必须是 `int16_t`、`uint16_t`、`int32_t`、`uint32_t` 之一。 + - `DstTileData::DType` 必须与 `Src0TileData::DType` 类型相同。 + - `src1.GetValidCol() == Src1TileData::Cols` 且 `dst.GetValidCol() == DstTileData::Cols`。 +- **基于掩码模式的 gather：实现检查 (A2A3)**: + - 源元素大小必须是 `2` 或 `4` 字节。 + - `SrcTileData::DType`/`DstTileData::DType` 必须是 `int16_t`、`uint16_t`、`int32_t`、`uint32_t`、`half`、`bfloat16_t` 或 `float` 之一。 + - `dst` 和 `src` 必须都是 `TileType::Vec` 且行主序。 + - `sizeof(dst element) == sizeof(src element)` 且 `dst.GetValidCol() == DstTileData::Cols`（连续的目标存储）。 +- **基于掩码模式的 gather：实现检查 (A5)**: + - 源元素大小必须是 `1`、`2` 或 `4` 字节。 + - `dst` 和 `src` 必须都是 `TileType::Vec` 且行主序。 + - `SrcTileData::DType`/`DstTileData::DType` 必须是 `int8_t`、`uint8_t`、`int16_t`、`uint16_t`、`int32_t`、`uint32_t`、`half`、`bfloat16_t`、`float`、`float8_e4m3_t`、`float8_e5m2_t` 或 `hifloat8_t` 之一。 + - 支持的数据类型限制为目标定义的集合（通过实现中的 `static_assert` 强制执行），且 `sizeof(dst element) == sizeof(src element)`，`dst.GetValidCol() == DstTileData::Cols`（连续的目标存储）。 +- **边界 / 有效性**: + - 索引边界不通过显式运行时断言进行验证；超出范围的索引行为由目标定义。 + +## 示例 + +### 自动（Auto） + +```cpp +#include + +using namespace pto; + +void example_auto() { + using SrcT = Tile; + using IdxT = Tile; + using DstT = Tile; + SrcT src0; + IdxT idx; + DstT dst; + TGATHER(dst, src0, idx); +} +``` + +### 手动（Manual） + +```cpp +#include + +using namespace pto; + +void example_manual() { + using SrcT = Tile; + using DstT = Tile; + SrcT src; + DstT dst; + TASSIGN(src, 0x1000); + TASSIGN(dst, 0x2000); + TGATHER(dst, src); +} +``` + +## 汇编示例（ASM） + +### 自动模式 + +```text +# 自动模式：由编译器/运行时负责资源放置与调度。 +%dst = pto.tgather %src, %indices : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### 手动模式 + +```text +# 手动模式：先显式绑定资源，再发射指令。 +# 可选（当该指令包含 tile 操作数时）： +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tgather %src, %indices : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### PTO 汇编形式 + +```text +%dst = pto.tgather %src, %indices : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +# AS Level 2 (DPS) +pto.tgather ins(%src, %indices : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/TGEMV.md b/designs/outerCube/PTOISA/TGEMV.md new file mode 100644 index 00000000..1a8253ee --- /dev/null +++ b/designs/outerCube/PTOISA/TGEMV.md @@ -0,0 +1,282 @@ +# TGEMV + + +## Tile Operation Diagram + +![TGEMV tile operation](../figures/isa/TGEMV.svg) + +## Introduction + +General Matrix-Vector multiplication (GEMV) producing an accumulator/output tile. + +## Math Interpretation + +Let: + +- `M = 1` +- `K = bMatrix.GetValidRow()` +- `N = bMatrix.GetValidCol()` + +### 1. TGEMV (Tile-based GEMV) + +For `0 <= j < N` (output elements in the effective matmul domain): + +$$ \mathrm{C}_{0,j} = \sum_{k=0}^{K-1} \mathrm{A}_{0,k} \cdot \mathrm{B}_{k,j} $$ + +### 2. TGEMV_ACC (Tile-based GEMV with Accumulation) + +For `0 <= j < N` (accumulates into existing tile): + +$$ \mathrm{C}_{0,j} \gets \mathrm{C}_{0,j} + \sum_{k=0}^{K-1} \mathrm{A}_{0,k} \cdot \mathrm{B}_{k,j} $$ + +### 3. TGEMV_BIAS (Tile-based GEMV with Bias) + +For `0 <= j < N` (adds bias term to matrix product): + +$$ \mathrm{C}_{0,j} = \mathrm{Bias}_{0,j} + \sum_{k=0}^{K-1} \mathrm{A}_{0,k} \cdot \mathrm{B}_{k,j} $$ + +**Note:** Exact accumulator behavior and datatype promotion are target/implementation-defined. + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%acc = tgemv %a, %b : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> + +%acc1 = tgemv.acc %acc0, %a, %b : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> + +%acc = tgemv.bias %a, %b, %bias : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%c = pto.tgemv %a, %b : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +%c_out = pto.tgemv.acc %c_in, %a, %b : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +%c = pto.tgemv.bias %a, %b, %bias : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tgemv ins(%a, %b : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%c : !pto.tile_buf<...>) +pto.tgemv.acc ins(%c_in, %a, %b : !pto.tile_buf<...>, !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%c_out : !pto.tile_buf<...>) +pto.tgemv.bias ins(%a, %b, %bias : !pto.tile_buf<...>, !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%c : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TGEMV(TileRes &cMatrix, TileLeft &aMatrix, TileRight &bMatrix, WaitEvents&... events); + +template +PTO_INST RecordEvent TGEMV_ACC(TileRes &cOutMatrix, TileRes &cInMatrix, TileLeft &aMatrix, TileRight &bMatrix, WaitEvents&... events); + +template +PTO_INST RecordEvent TGEMV_BIAS(TileRes &cMatrix, TileLeft &aMatrix, TileRight &bMatrix, TileBias &biasData, WaitEvents&... events); +``` + +## Constraints + +### Common shape and location constraints + +These constraints apply to `TGEMV`, `TGEMV_ACC`, and `TGEMV_BIAS` unless otherwise noted. + +- Static shape constraints: + - `TileLeft::Rows == TileRes::Rows` + - `TileLeft::Cols == TileRight::Rows` + - `TileRight::Cols == TileRes::Cols` +- Tile locations: + - `TileLeft::Loc == Left` + - `TileRight::Loc == Right` + - `TileRes::Loc == Acc` +- Runtime valid-size constraints: + - `m` must be `1` + - `k` and `n` (taken from `bMatrix.GetValidRow()` and `bMatrix.GetValidCol()`) must be in `[1, 4095]` + +### TGEMV / TGEMV_ACC datatype constraints + +- **Implementation checks (A2A3)**: + - Supported `(CType, AType, BType)` triples: + - `(int32_t, int8_t, int8_t)` + - `(float, half, half)` + - `(float, float, float)` + - `(float, bfloat16_t, bfloat16_t)` +- **Implementation checks (A5)**: + - Accumulator type must be `int32_t` or `float`. + - If `int32_t`: `AType == int8_t` and `BType == int8_t`. + - If `float`: supports `half`, `bfloat16_t`, `float`, and selected fp8 pairs (target-defined). + - Fractal/layout constraints are enforced: + - Left: `Loc == Left`, `!isRowMajor`, `SFractal == RowMajor` + - Right: `Loc == Right`, `isRowMajor`, `SFractal == ColMajor` + - Acc: `Loc == Acc`, `!isRowMajor`, `SFractal == RowMajor` + +### TGEMV_BIAS additional constraints + +- Bias tile datatype must exactly match `TileRes::DType`. +- Bias tile must be configured as a single row. +- Bias tile location must be `TileType::Bias`. +- **Additional A5 note**: + - No separate explicit `m/k/n` runtime assertions are enforced in the underlying A5 matmul implementation beyond the GEMV contract described above. + +## Examples + +### Auto + +#### 1. TGEMV + +```cpp +#include + +using namespace pto; + +void example_auto() { + using A = TileLeft; + using B = TileRight; + using C = TileAcc; + A a; + B b; + C c; + TGEMV(c, a, b); +} +``` + +#### 2. TGEMV_ACC + +```cpp +#include + +using namespace pto; + +void example_auto() { + using A = TileLeft; + using B = TileRight; + using C = TileAcc; + A a; + B b; + C c0, c1; + TGEMV_ACC(c1, c0, a, b); +} +``` + +#### 3. TGEMV_BIAS + +```cpp +#include + +using namespace pto; + +void example_auto() { + using A = TileLeft; + using B = TileRight; + using Bias = Tile; + using C = TileAcc; + A a; + B b; + Bias bias; + C c; + TGEMV_BIAS(c, a, b, bias); +} +``` + +### Manual + +#### 1. TGEMV + +```cpp +#include + +using namespace pto; + +void example_manual() { + using A = TileLeft; + using B = TileRight; + using C = TileAcc; + A a; + B b; + C c; + TASSIGN(a, 0x1000); + TASSIGN(b, 0x2000); + TASSIGN(c, 0x3000); + TGEMV(c, a, b); +} +``` + +#### 2. TGEMV_ACC + +```cpp +#include + +using namespace pto; + +void example_manual() { + using A = TileLeft; + using B = TileRight; + using C = TileAcc; + A a; + B b; + C c0, c1; + TASSIGN(a, 0x1000); + TASSIGN(b, 0x2000); + TASSIGN(c0, 0x3000); + TASSIGN(c1, 0x4000); + TGEMV_ACC(c1, c0, a, b); +} +``` + +#### 3. TGEMV_BIAS + +```cpp +#include + +using namespace pto; + +void example_manual() { + using A = TileLeft; + using B = TileRight; + using Bias = Tile; + using C = TileAcc; + A a; + B b; + Bias bias; + C c; + TASSIGN(a, 0x1000); + TASSIGN(b, 0x2000); + TASSIGN(bias, 0x3000); + TASSIGN(c, 0x4000); + TGEMV_BIAS(c, a, b, bias); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%c = pto.tgemv %a, %b : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%c = pto.tgemv %a, %b : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%acc = tgemv %a, %b : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +# AS Level 2 (DPS) +pto.tgemv ins(%a, %b : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%c : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/TGEMV_ACC.md b/designs/outerCube/PTOISA/TGEMV_ACC.md new file mode 100644 index 00000000..7bad9382 --- /dev/null +++ b/designs/outerCube/PTOISA/TGEMV_ACC.md @@ -0,0 +1,166 @@ +# TGEMV_ACC + + +## Tile Operation Diagram + +![TGEMV_ACC tile operation](../figures/isa/TGEMV_ACC.svg) + +## Introduction + +Tile-based GEMV with explicit accumulator input tile (`cInMatrix`) and output tile (`cOutMatrix`). + +## See also + +- Base GEMV instruction: `docs/isa/TGEMV.md`. +- Bias variant: `docs/isa/TGEMV_BIAS.md`. + +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TGEMV_ACC(TileRes &cOutMatrix, TileRes &cInMatrix, TileLeft &aMatrix, TileRight &bMatrix, WaitEvents &... events); + +template +PTO_INST RecordEvent TGEMV_ACC(TileRes &cOutMatrix, TileRes &cInMatrix, TileLeft &aMatrix, TileRight &bMatrix, WaitEvents &... events); +``` + +## Math Interpretation + +Let: + +- `M = 1` +- `K = bMatrix.GetValidRow()` +- `N = bMatrix.GetValidCol()` + +For `0 <= j < N` (accumulates into the existing output tile): + +$$ \mathrm{C}_{0,j} \gets \mathrm{C}_{0,j} + \sum_{k=0}^{K-1} \mathrm{A}_{0,k} \cdot \mathrm{B}_{k,j} $$ + +**Note:** Exact accumulator behavior and datatype promotion are target/implementation-defined. + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%acc1 = tgemv.acc %acc0, %a, %b : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%c_out = pto.tgemv.acc %c_in, %a, %b : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tgemv.acc ins(%c_in, %a, %b : !pto.tile_buf<...>, !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%c_out : !pto.tile_buf<...>) +``` + +## Constraints + +### Common shape and location constraints + +- Static shape constraints: + - `TileLeft::Rows == TileRes::Rows` + - `TileLeft::Cols == TileRight::Rows` + - `TileRight::Cols == TileRes::Cols` +- Tile locations: + - `TileLeft::Loc == Left` + - `TileRight::Loc == Right` + - `TileRes::Loc == Acc` +- Runtime valid-size constraints: + - `m` must be `1` + - `k` and `n` (taken from `bMatrix.GetValidRow()` and `bMatrix.GetValidCol()`) must be in `[1, 4095]` + +### Datatype constraints + +- **Implementation checks (A2A3)**: + - Supported `(CType, AType, BType)` triples: + - `(int32_t, int8_t, int8_t)` + - `(float, half, half)` + - `(float, float, float)` + - `(float, bfloat16_t, bfloat16_t)` +- **Implementation checks (A5)**: + - Accumulator type must be `int32_t` or `float`. + - If `int32_t`: `AType == int8_t` and `BType == int8_t`. + - If `float`: supports `half`, `bfloat16_t`, `float`, and selected fp8 pairs (target-defined). + - Fractal/layout constraints are enforced: + - Left: `Loc == Left`, `!isRowMajor`, `SFractal == RowMajor` + - Right: `Loc == Right`, `isRowMajor`, `SFractal == ColMajor` + - Acc: `Loc == Acc`, `!isRowMajor`, `SFractal == RowMajor` + - No separate explicit `m/k/n` runtime assertions are enforced in the underlying A5 matmul implementation beyond the GEMV contract described above. + +## Examples + +### Auto + +```cpp +#include + +using namespace pto; + +void example_auto() { + using A = TileLeft; + using B = TileRight; + using C = TileAcc; + A a; + B b; + C c0, c1; + TGEMV_ACC(c1, c0, a, b); +} +``` + +### Manual + +```cpp +#include + +using namespace pto; + +void example_manual() { + using A = TileLeft; + using B = TileRight; + using C = TileAcc; + A a; + B b; + C c0, c1; + TASSIGN(a, 0x1000); + TASSIGN(b, 0x2000); + TASSIGN(c0, 0x3000); + TASSIGN(c1, 0x4000); + TGEMV_ACC(c1, c0, a, b); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%c_out = pto.tgemv.acc %c_in, %a, %b : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%c_out = pto.tgemv.acc %c_in, %a, %b : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%acc1 = tgemv.acc %acc0, %a, %b : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +# AS Level 2 (DPS) +pto.tgemv.acc ins(%c_in, %a, %b : !pto.tile_buf<...>, !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%c_out : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TGEMV_ACC_zh.md b/designs/outerCube/PTOISA/TGEMV_ACC_zh.md new file mode 100644 index 00000000..7a79476d --- /dev/null +++ b/designs/outerCube/PTOISA/TGEMV_ACC_zh.md @@ -0,0 +1,165 @@ +# TGEMV_ACC + +## 指令示意图 + +![TGEMV_ACC tile operation](../figures/isa/TGEMV_ACC.svg) + +## 简介 + +带显式累加器输入 Tile（`cInMatrix`）和输出 Tile（`cOutMatrix`）的 GEMV。 + +## 另请参见 + +- 基础 GEMV 指令：`docs/isa/TGEMV.md`。 +- 偏置变体：`docs/isa/TGEMV_BIAS.md`。 + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`： + +```cpp +template +PTO_INST RecordEvent TGEMV_ACC(TileRes &cOutMatrix, TileRes &cInMatrix, TileLeft &aMatrix, TileRight &bMatrix, WaitEvents &... events); + +template +PTO_INST RecordEvent TGEMV_ACC(TileRes &cOutMatrix, TileRes &cInMatrix, TileLeft &aMatrix, TileRight &bMatrix, WaitEvents &... events); +``` + +## 数学语义 + +设： + +- `M = 1` +- `K = bMatrix.GetValidRow()` +- `N = bMatrix.GetValidCol()` + +对于 `0 <= j < N`（累加到已有输出 Tile）： + +$$ \mathrm{C}_{0,j} \gets \mathrm{C}_{0,j} + \sum_{k=0}^{K-1} \mathrm{A}_{0,k} \cdot \mathrm{B}_{k,j} $$ + +**注意：** 精确的累加器行为和数据类型提升由目标/实现定义。 + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS 规范](../assembly/PTO-AS_zh.md)。 + +同步形式： + +```text +%acc1 = tgemv.acc %acc0, %a, %b : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 1（SSA） + +```text +%c_out = pto.tgemv.acc %c_in, %a, %b : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.tgemv.acc ins(%c_in, %a, %b : !pto.tile_buf<...>, !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%c_out : !pto.tile_buf<...>) +``` + +## 约束 + +### 通用形状与位置约束 + +- 静态形状约束： + - `TileLeft::Rows == TileRes::Rows` + - `TileLeft::Cols == TileRight::Rows` + - `TileRight::Cols == TileRes::Cols` +- Tile 位置约束： + - `TileLeft::Loc == Left` + - `TileRight::Loc == Right` + - `TileRes::Loc == Acc` +- 运行时有效尺寸约束： + - `m` 必须为 `1` + - `k` 和 `n`（取自 `bMatrix.GetValidRow()` 与 `bMatrix.GetValidCol()`）必须位于 `[1, 4095]` + +### 数据类型约束 + +- **实现检查 (A2A3)**: + - 支持的 `(CType, AType, BType)` 三元组： + - `(int32_t, int8_t, int8_t)` + - `(float, half, half)` + - `(float, float, float)` + - `(float, bfloat16_t, bfloat16_t)` +- **实现检查 (A5)**: + - 累加器类型必须是 `int32_t` 或 `float`。 + - 如果为 `int32_t`：`AType == int8_t` 且 `BType == int8_t`。 + - 如果为 `float`：支持 `half`、`bfloat16_t`、`float` 以及选定的 fp8 组合（目标定义）。 + - 会强制执行以下分形/布局约束： + - Left：`Loc == Left`、`!isRowMajor`、`SFractal == RowMajor` + - Right：`Loc == Right`、`isRowMajor`、`SFractal == ColMajor` + - Acc：`Loc == Acc`、`!isRowMajor`、`SFractal == RowMajor` + - 除上述 GEMV 约定外，底层 A5 matmul 实现不会再单独补充一组显式的 `m/k/n` 运行时断言。 + +## 示例 + +### 自动（Auto） + +```cpp +#include + +using namespace pto; + +void example_auto() { + using A = TileLeft; + using B = TileRight; + using C = TileAcc; + A a; + B b; + C c0, c1; + TGEMV_ACC(c1, c0, a, b); +} +``` + +### 手动（Manual） + +```cpp +#include + +using namespace pto; + +void example_manual() { + using A = TileLeft; + using B = TileRight; + using C = TileAcc; + A a; + B b; + C c0, c1; + TASSIGN(a, 0x1000); + TASSIGN(b, 0x2000); + TASSIGN(c0, 0x3000); + TASSIGN(c1, 0x4000); + TGEMV_ACC(c1, c0, a, b); +} +``` + +## 汇编示例（ASM） + +### 自动模式 + +```text +# 自动模式：由编译器/运行时负责资源放置与调度。 +%c_out = pto.tgemv.acc %c_in, %a, %b : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### 手动模式 + +```text +# 手动模式：先显式绑定资源，再发射指令。 +# 可选（当该指令包含 tile 操作数时）： +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%c_out = pto.tgemv.acc %c_in, %a, %b : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### PTO 汇编形式 + +```text +%acc1 = tgemv.acc %acc0, %a, %b : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +# AS Level 2 (DPS) +pto.tgemv.acc ins(%c_in, %a, %b : !pto.tile_buf<...>, !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%c_out : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TGEMV_BIAS.md b/designs/outerCube/PTOISA/TGEMV_BIAS.md new file mode 100644 index 00000000..08a40fcf --- /dev/null +++ b/designs/outerCube/PTOISA/TGEMV_BIAS.md @@ -0,0 +1,178 @@ +# TGEMV_BIAS + + +## Tile Operation Diagram + +![TGEMV_BIAS tile operation](../figures/isa/TGEMV_BIAS.svg) + +## Introduction + +Tile-based GEMV with bias add. + +## See also + +- Base GEMV instruction: `docs/isa/TGEMV.md`. +- Accumulation variant: `docs/isa/TGEMV_ACC.md`. + +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TGEMV_BIAS(TileRes &cMatrix, TileLeft &aMatrix, TileRight &bMatrix, TileBias &biasData, WaitEvents &... events); + +template +PTO_INST RecordEvent TGEMV_BIAS(TileRes &cMatrix, TileLeft &aMatrix, TileRight &bMatrix, TileBias &biasData, WaitEvents &... events); +``` + +## Math Interpretation + +Let: + +- `M = 1` +- `K = bMatrix.GetValidRow()` +- `N = bMatrix.GetValidCol()` + +For `0 <= j < N` (adds a bias term to the matrix product): + +$$ \mathrm{C}_{0,j} = \mathrm{Bias}_{0,j} + \sum_{k=0}^{K-1} \mathrm{A}_{0,k} \cdot \mathrm{B}_{k,j} $$ + +**Note:** Exact accumulator behavior and datatype promotion are target/implementation-defined. + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%acc = tgemv.bias %a, %b, %bias : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%c = pto.tgemv.bias %a, %b, %bias : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tgemv.bias ins(%a, %b, %bias : !pto.tile_buf<...>, !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%c : !pto.tile_buf<...>) +``` + +## Constraints + +### Common shape and location constraints + +- Static shape constraints: + - `TileLeft::Rows == TileRes::Rows` + - `TileLeft::Cols == TileRight::Rows` + - `TileRight::Cols == TileRes::Cols` +- Tile locations: + - `TileLeft::Loc == Left` + - `TileRight::Loc == Right` + - `TileRes::Loc == Acc` +- Runtime valid-size constraints: + - `m` must be `1` + - `k` and `n` (taken from `bMatrix.GetValidRow()` and `bMatrix.GetValidCol()`) must be in `[1, 4095]` + +### Datatype constraints + +- **Implementation checks (A2A3)**: + - Supported `(CType, AType, BType)` triples: + - `(int32_t, int8_t, int8_t)` + - `(float, half, half)` + - `(float, float, float)` + - `(float, bfloat16_t, bfloat16_t)` +- **Implementation checks (A5)**: + - Accumulator type must be `int32_t` or `float`. + - If `int32_t`: `AType == int8_t` and `BType == int8_t`. + - If `float`: supports `half`, `bfloat16_t`, `float`, and selected fp8 pairs (target-defined). + - Fractal/layout constraints are enforced: + - Left: `Loc == Left`, `!isRowMajor`, `SFractal == RowMajor` + - Right: `Loc == Right`, `isRowMajor`, `SFractal == ColMajor` + - Acc: `Loc == Acc`, `!isRowMajor`, `SFractal == RowMajor` + +### Bias-specific constraints + +- Bias tile datatype must exactly match `TileRes::DType`. +- Bias tile must be configured as a single row. +- Bias tile location must be `TileType::Bias`. +- **Additional A5 note**: + - No separate explicit `m/k/n` runtime assertions are enforced in the underlying A5 matmul implementation beyond the GEMV contract described above. + +## Examples + +### Auto + +```cpp +#include + +using namespace pto; + +void example_auto() { + using A = TileLeft; + using B = TileRight; + using Bias = Tile; + using C = TileAcc; + A a; + B b; + Bias bias; + C c; + TGEMV_BIAS(c, a, b, bias); +} +``` + +### Manual + +```cpp +#include + +using namespace pto; + +void example_manual() { + using A = TileLeft; + using B = TileRight; + using Bias = Tile; + using C = TileAcc; + A a; + B b; + Bias bias; + C c; + TASSIGN(a, 0x1000); + TASSIGN(b, 0x2000); + TASSIGN(bias, 0x3000); + TASSIGN(c, 0x4000); + TGEMV_BIAS(c, a, b, bias); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%c = pto.tgemv.bias %a, %b, %bias : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%c = pto.tgemv.bias %a, %b, %bias : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%acc = tgemv.bias %a, %b, %bias : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +# AS Level 2 (DPS) +pto.tgemv.bias ins(%a, %b, %bias : !pto.tile_buf<...>, !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%c : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TGEMV_BIAS_zh.md b/designs/outerCube/PTOISA/TGEMV_BIAS_zh.md new file mode 100644 index 00000000..5e78f56a --- /dev/null +++ b/designs/outerCube/PTOISA/TGEMV_BIAS_zh.md @@ -0,0 +1,177 @@ +# TGEMV_BIAS + +## 指令示意图 + +![TGEMV_BIAS tile operation](../figures/isa/TGEMV_BIAS.svg) + +## 简介 + +带偏置加法的 GEMV。 + +## 另请参见 + +- 基础 GEMV 指令：`docs/isa/TGEMV.md`。 +- 累加变体：`docs/isa/TGEMV_ACC.md`。 + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`： + +```cpp +template +PTO_INST RecordEvent TGEMV_BIAS(TileRes &cMatrix, TileLeft &aMatrix, TileRight &bMatrix, TileBias &biasData, WaitEvents &... events); + +template +PTO_INST RecordEvent TGEMV_BIAS(TileRes &cMatrix, TileLeft &aMatrix, TileRight &bMatrix, TileBias &biasData, WaitEvents &... events); +``` + +## 数学语义 + +设： + +- `M = 1` +- `K = bMatrix.GetValidRow()` +- `N = bMatrix.GetValidCol()` + +对于 `0 <= j < N`（将偏置项加入矩阵乘积）： + +$$ \mathrm{C}_{0,j} = \mathrm{Bias}_{0,j} + \sum_{k=0}^{K-1} \mathrm{A}_{0,k} \cdot \mathrm{B}_{k,j} $$ + +**注意：** 精确的累加器行为和数据类型提升由目标/实现定义。 + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS 规范](../assembly/PTO-AS_zh.md)。 + +同步形式： + +```text +%acc = tgemv.bias %a, %b, %bias : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 1（SSA） + +```text +%c = pto.tgemv.bias %a, %b, %bias : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.tgemv.bias ins(%a, %b, %bias : !pto.tile_buf<...>, !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%c : !pto.tile_buf<...>) +``` + +## 约束 + +### 通用形状与位置约束 + +- 静态形状约束： + - `TileLeft::Rows == TileRes::Rows` + - `TileLeft::Cols == TileRight::Rows` + - `TileRight::Cols == TileRes::Cols` +- Tile 位置约束： + - `TileLeft::Loc == Left` + - `TileRight::Loc == Right` + - `TileRes::Loc == Acc` +- 运行时有效尺寸约束： + - `m` 必须为 `1` + - `k` 和 `n`（取自 `bMatrix.GetValidRow()` 与 `bMatrix.GetValidCol()`）必须位于 `[1, 4095]` + +### 数据类型约束 + +- **实现检查 (A2A3)**: + - 支持的 `(CType, AType, BType)` 三元组： + - `(int32_t, int8_t, int8_t)` + - `(float, half, half)` + - `(float, float, float)` + - `(float, bfloat16_t, bfloat16_t)` +- **实现检查 (A5)**: + - 累加器类型必须是 `int32_t` 或 `float`。 + - 如果为 `int32_t`：`AType == int8_t` 且 `BType == int8_t`。 + - 如果为 `float`：支持 `half`、`bfloat16_t`、`float` 以及选定的 fp8 组合（目标定义）。 + - 会强制执行以下分形/布局约束： + - Left：`Loc == Left`、`!isRowMajor`、`SFractal == RowMajor` + - Right：`Loc == Right`、`isRowMajor`、`SFractal == ColMajor` + - Acc：`Loc == Acc`、`!isRowMajor`、`SFractal == RowMajor` + +### 偏置专属约束 + +- 偏置 tile 的数据类型必须与 `TileRes::DType` 完全一致。 +- 偏置 tile 必须配置为单行。 +- 偏置 tile 的位置必须为 `TileType::Bias`。 +- **A5 附加说明**： + - 除上述 GEMV 约定外，底层 A5 matmul 实现不会再单独补充一组显式的 `m/k/n` 运行时断言。 + +## 示例 + +### 自动（Auto） + +```cpp +#include + +using namespace pto; + +void example_auto() { + using A = TileLeft; + using B = TileRight; + using Bias = Tile; + using C = TileAcc; + A a; + B b; + Bias bias; + C c; + TGEMV_BIAS(c, a, b, bias); +} +``` + +### 手动（Manual） + +```cpp +#include + +using namespace pto; + +void example_manual() { + using A = TileLeft; + using B = TileRight; + using Bias = Tile; + using C = TileAcc; + A a; + B b; + Bias bias; + C c; + TASSIGN(a, 0x1000); + TASSIGN(b, 0x2000); + TASSIGN(bias, 0x3000); + TASSIGN(c, 0x4000); + TGEMV_BIAS(c, a, b, bias); +} +``` + +## 汇编示例（ASM） + +### 自动模式 + +```text +# 自动模式：由编译器/运行时负责资源放置与调度。 +%c = pto.tgemv.bias %a, %b, %bias : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### 手动模式 + +```text +# 手动模式：先显式绑定资源，再发射指令。 +# 可选（当该指令包含 tile 操作数时）： +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%c = pto.tgemv.bias %a, %b, %bias : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### PTO 汇编形式 + +```text +%acc = tgemv.bias %a, %b, %bias : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +# AS Level 2 (DPS) +pto.tgemv.bias ins(%a, %b, %bias : !pto.tile_buf<...>, !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%c : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TGEMV_MX.md b/designs/outerCube/PTOISA/TGEMV_MX.md new file mode 100644 index 00000000..7d117ba7 --- /dev/null +++ b/designs/outerCube/PTOISA/TGEMV_MX.md @@ -0,0 +1,127 @@ +# TGEMV_MX + + +## Tile Operation Diagram + +![TGEMV_MX tile operation](../figures/isa/TGEMV_MX.svg) + +## Introduction + +GEMV with scaling tiles for mixed-precision / quantized matrix-vector compute on supported targets. + +This instruction family extends `TGEMV` with additional scale operands (mx path). Accumulator and scale handling are target-dependent. + +## Math Interpretation + +Conceptually (base GEMV path): + +$$ +\mathrm{C}_{0,j} = \sum_{k=0}^{K-1} \mathrm{A}_{0,k} \cdot \mathrm{B}_{k,j} +$$ + +For `TGEMV_MX`, scale tiles participate in implementation-defined mixed-precision reconstruction / scaling. The architectural contract is that output corresponds to the target-defined mx GEMV semantics. + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Schematic form: + +```text +%acc = tgemv.mx %a, %a_scale, %b, %b_scale : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%acc = pto.tgemv.mx %a, %a_scale, %b, %b_scale : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tgemv.mx ins(%a, %a_scale, %b, %b_scale : (!pto.tile_buf<...>, !pto.tile_buf<...>, !pto.tile_buf<...>, !pto.tile_buf<...>)) outs(%acc : !pto.tile_buf<...>) +``` + +### IR Level 1 (SSA) + +```text +%acc = pto.tgemv.mx %a, %a_scale, %b, %b_scale : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### IR Level 2 (DPS) + +```text +pto.tgemv.mx ins(%a, %a_scale, %b, %b_scale : (!pto.tile_buf<...>, !pto.tile_buf<...>, !pto.tile_buf<...>, !pto.tile_buf<...>)) outs(%acc : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TGEMV_MX(TileRes &cMatrix, TileLeft &aMatrix, TileLeftScale &aScaleMatrix, TileRight &bMatrix, TileRightScale &bScaleMatrix, WaitEvents &... events); + +template +PTO_INST RecordEvent TGEMV_MX(TileRes &cMatrix, TileLeft &aMatrix, TileLeftScale &aScaleMatrix, TileRight &bMatrix, TileRightScale &bScaleMatrix, WaitEvents &... events); + +template +PTO_INST RecordEvent TGEMV_MX(TileRes &cOutMatrix, TileRes &cInMatrix, TileLeft &aMatrix, TileLeftScale &aScaleMatrix, TileRight &bMatrix, TileRightScale &bScaleMatrix, WaitEvents &... events); + +template +PTO_INST RecordEvent TGEMV_MX(TileRes &cOutMatrix, TileRes &cInMatrix, TileLeft &aMatrix, TileLeftScale &aScaleMatrix, TileRight &bMatrix, TileRightScale &bScaleMatrix, WaitEvents &... events); + +template +PTO_INST RecordEvent TGEMV_MX(TileRes &cMatrix, TileLeft &aMatrix, TileLeftScale &aScaleMatrix, TileRight &bMatrix, TileRightScale &bScaleMatrix, TileBias &biasData, WaitEvents &... events); + +template +PTO_INST RecordEvent TGEMV_MX(TileRes &cMatrix, TileLeft &aMatrix, TileLeftScale &aScaleMatrix, TileRight &bMatrix, TileRightScale &bScaleMatrix, TileBias &biasData, WaitEvents &... events); +``` + +Additional overloads support accumulation/bias variants and `AccPhase` selection. + +## Constraints + +- Uses backend-specific mx legality checks for data types, tile locations, fractal/layout combinations, and scaling formats. +- Scale tile compatibility and accumulator promotion are implementation-defined by target backend. +- For portability, validate the exact `(A, B, scaleA, scaleB, C)` type tuple and tile layout against target implementation constraints. + +## Examples + +For practical usage patterns, see: + +- `docs/isa/TMATMUL_MX.md` +- `docs/isa/TGEMV.md` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%acc = pto.tgemv.mx %a, %a_scale, %b, %b_scale : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%acc = pto.tgemv.mx %a, %a_scale, %b, %b_scale : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%acc = pto.tgemv.mx %a, %a_scale, %b, %b_scale : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +# AS Level 2 (DPS) +pto.tgemv.mx ins(%a, %a_scale, %b, %b_scale : (!pto.tile_buf<...>, !pto.tile_buf<...>, !pto.tile_buf<...>, !pto.tile_buf<...>)) outs(%acc : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TGEMV_MX_zh.md b/designs/outerCube/PTOISA/TGEMV_MX_zh.md new file mode 100644 index 00000000..1b7e9d31 --- /dev/null +++ b/designs/outerCube/PTOISA/TGEMV_MX_zh.md @@ -0,0 +1,98 @@ +# TGEMV_MX + +## 指令示意图 + +![TGEMV_MX tile operation](../figures/isa/TGEMV_MX.svg) + +## 简介 + +带缩放 Tile 的 GEMV 变体，支持混合精度/量化矩阵向量计算。 + +## 数学语义 + +Conceptually (base GEMV path): + +$$ +\mathrm{C}_{0,j} = \sum_{k=0}^{K-1} \mathrm{A}_{0,k} \cdot \mathrm{B}_{k,j} +$$ + +For `TGEMV_MX`, scale tiles participate in implementation-defined mixed-precision reconstruction / scaling. The architectural contract is that output corresponds to the target-defined mx GEMV semantics. + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS Specification](../assembly/PTO-AS.md). + +Schematic form: + +```text +%acc = tgemv.mx %a, %a_scale, %b, %b_scale : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%acc = pto.tgemv.mx %a, %a_scale, %b, %b_scale : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tgemv.mx ins(%a, %a_scale, %b, %b_scale : (!pto.tile_buf<...>, !pto.tile_buf<...>, !pto.tile_buf<...>, !pto.tile_buf<...>)) outs(%acc : !pto.tile_buf<...>) +``` + +### AS Level 1（SSA） + +```text +%acc = pto.tgemv.mx %a, %a_scale, %b, %b_scale : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.tgemv.mx ins(%a, %a_scale, %b, %b_scale : (!pto.tile_buf<...>, !pto.tile_buf<...>, !pto.tile_buf<...>, !pto.tile_buf<...>)) outs(%acc : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TGEMV_MX(TileRes &cMatrix, TileLeft &aMatrix, TileLeftScale &aScaleMatrix, TileRight &bMatrix, TileRightScale &bScaleMatrix, WaitEvents &... events); + +template +PTO_INST RecordEvent TGEMV_MX(TileRes &cMatrix, TileLeft &aMatrix, TileLeftScale &aScaleMatrix, TileRight &bMatrix, TileRightScale &bScaleMatrix, WaitEvents &... events); + +template +PTO_INST RecordEvent TGEMV_MX(TileRes &cOutMatrix, TileRes &cInMatrix, TileLeft &aMatrix, TileLeftScale &aScaleMatrix, TileRight &bMatrix, TileRightScale &bScaleMatrix, WaitEvents &... events); + +template +PTO_INST RecordEvent TGEMV_MX(TileRes &cOutMatrix, TileRes &cInMatrix, TileLeft &aMatrix, TileLeftScale &aScaleMatrix, TileRight &bMatrix, TileRightScale &bScaleMatrix, WaitEvents &... events); + +template +PTO_INST RecordEvent TGEMV_MX(TileRes &cMatrix, TileLeft &aMatrix, TileLeftScale &aScaleMatrix, TileRight &bMatrix, TileRightScale &bScaleMatrix, TileBias &biasData, WaitEvents &... events); + +template +PTO_INST RecordEvent TGEMV_MX(TileRes &cMatrix, TileLeft &aMatrix, TileLeftScale &aScaleMatrix, TileRight &bMatrix, TileRightScale &bScaleMatrix, TileBias &biasData, WaitEvents &... events); +``` + +Additional overloads support accumulation/bias variants and `AccPhase` selection. + +## 约束 + +- Uses backend-specific mx legality checks for data types, tile locations, fractal/layout combinations, and scaling formats. +- Scale tile compatibility and accumulator promotion are implementation-defined by target backend. +- For portability, validate the exact `(A, B, scaleA, scaleB, C)` type tuple and tile layout against target implementation constraints. + +## 示例 + +For practical usage patterns, see: + +- `docs/isa/TMATMUL_MX.md` +- `docs/isa/TGEMV.md` diff --git a/designs/outerCube/PTOISA/TGEMV_zh.md b/designs/outerCube/PTOISA/TGEMV_zh.md new file mode 100644 index 00000000..f17168fe --- /dev/null +++ b/designs/outerCube/PTOISA/TGEMV_zh.md @@ -0,0 +1,282 @@ +# TGEMV + +## 指令示意图 + +![TGEMV tile operation](../figures/isa/TGEMV.svg) + +## 简介 + +通用矩阵-向量乘法，生成累加器/输出 Tile。 + +## 数学语义 + +设： + +- `M = 1` +- `K = bMatrix.GetValidRow()` +- `N = bMatrix.GetValidCol()` + +### 1. TGEMV（基于 Tile 的 GEMV） + +对于 `0 <= j < N`（有效矩阵乘法域中的输出元素）： + +$$ \mathrm{C}_{0,j} = \sum_{k=0}^{K-1} \mathrm{A}_{0,k} \cdot \mathrm{B}_{k,j} $$ + +### 2. TGEMV_ACC（带累加的基于 Tile 的 GEMV） + +对于 `0 <= j < N`（累加到现有 tile）： + +$$ \mathrm{C}_{0,j} \gets \mathrm{C}_{0,j} + \sum_{k=0}^{K-1} \mathrm{A}_{0,k} \cdot \mathrm{B}_{k,j} $$ + +### 3. TGEMV_BIAS（带偏置的基于 Tile 的 GEMV） + +对于 `0 <= j < N`（将偏置项添加到矩阵乘积）： + +$$ \mathrm{C}_{0,j} = \mathrm{Bias}_{0,j} + \sum_{k=0}^{K-1} \mathrm{A}_{0,k} \cdot \mathrm{B}_{k,j} $$ + +**注意：** 精确的累加器行为和数据类型提升由目标/实现定义。 + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS 规范](../assembly/PTO-AS_zh.md)。 + +同步形式： + +```text +%acc = tgemv %a, %b : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> + +%acc1 = tgemv.acc %acc0, %a, %b : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> + +%acc = tgemv.bias %a, %b, %bias : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 1（SSA） + +```text +%c = pto.tgemv %a, %b : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +%c_out = pto.tgemv.acc %c_in, %a, %b : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +%c = pto.tgemv.bias %a, %b, %bias : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.tgemv ins(%a, %b : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%c : !pto.tile_buf<...>) +pto.tgemv.acc ins(%c_in, %a, %b : !pto.tile_buf<...>, !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%c_out : !pto.tile_buf<...>) +pto.tgemv.bias ins(%a, %b, %bias : !pto.tile_buf<...>, !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%c : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`： + +```cpp +template +PTO_INST RecordEvent TGEMV(TileRes &cMatrix, TileLeft &aMatrix, TileRight &bMatrix, WaitEvents&... events); + +template +PTO_INST RecordEvent TGEMV_ACC(TileRes &cOutMatrix, TileRes &cInMatrix, TileLeft &aMatrix, TileRight &bMatrix, WaitEvents&... events); + +template +PTO_INST RecordEvent TGEMV_BIAS(TileRes &cMatrix, TileLeft &aMatrix, TileRight &bMatrix, TileBias &biasData, WaitEvents&... events); +``` + +## 约束 + +### 通用形状与位置约束 + +以下约束在未特别说明时同时适用于 `TGEMV`、`TGEMV_ACC` 和 `TGEMV_BIAS`。 + +- 静态形状约束： + - `TileLeft::Rows == TileRes::Rows` + - `TileLeft::Cols == TileRight::Rows` + - `TileRight::Cols == TileRes::Cols` +- Tile 位置约束： + - `TileLeft::Loc == Left` + - `TileRight::Loc == Right` + - `TileRes::Loc == Acc` +- 运行时有效尺寸约束： + - `m` 必须为 `1` + - `k` 和 `n`（取自 `bMatrix.GetValidRow()` 与 `bMatrix.GetValidCol()`）必须位于 `[1, 4095]` + +### TGEMV / TGEMV_ACC 数据类型约束 + +- **实现检查 (A2A3)**: + - 支持的 `(CType, AType, BType)` 三元组： + - `(int32_t, int8_t, int8_t)` + - `(float, half, half)` + - `(float, float, float)` + - `(float, bfloat16_t, bfloat16_t)` +- **实现检查 (A5)**: + - 累加器类型必须是 `int32_t` 或 `float`。 + - 如果为 `int32_t`：`AType == int8_t` 且 `BType == int8_t`。 + - 如果为 `float`：支持 `half`、`bfloat16_t`、`float` 以及选定的 fp8 组合（目标定义）。 + - 会强制执行以下分形/布局约束： + - Left：`Loc == Left`、`!isRowMajor`、`SFractal == RowMajor` + - Right：`Loc == Right`、`isRowMajor`、`SFractal == ColMajor` + - Acc：`Loc == Acc`、`!isRowMajor`、`SFractal == RowMajor` + +### TGEMV_BIAS 的附加约束 + +- 偏置 tile 的数据类型必须与 `TileRes::DType` 完全一致。 +- 偏置 tile 必须配置为单行。 +- 偏置 tile 的位置必须为 `TileType::Bias`。 +- **A5 附加说明**： + - 除上述 GEMV 约定外，底层 A5 matmul 实现不会再单独补充一组显式的 `m/k/n` 运行时断言。 + +## 示例 + +### 自动（Auto） + +#### 1. TGEMV + +```cpp +#include + +using namespace pto; + +void example_auto() { + using A = TileLeft; + using B = TileRight; + using C = TileAcc; + A a; + B b; + C c; + TGEMV(c, a, b); +} +``` + +#### 2. TGEMV_ACC + +```cpp +#include + +using namespace pto; + +void example_auto() { + using A = TileLeft; + using B = TileRight; + using C = TileAcc; + A a; + B b; + C c0, c1; + TGEMV_ACC(c1, c0, a, b); +} +``` + +#### 3. TGEMV_BIAS + +```cpp +#include + +using namespace pto; + +void example_auto() { + using A = TileLeft; + using B = TileRight; + using Bias = Tile; + using C = TileAcc; + A a; + B b; + Bias bias; + C c; + TGEMV_BIAS(c, a, b, bias); +} +``` + +### 手动（Manual） + +#### 1. TGEMV + +```cpp +#include + +using namespace pto; + +void example_manual() { + using A = TileLeft; + using B = TileRight; + using C = TileAcc; + A a; + B b; + C c; + TASSIGN(a, 0x1000); + TASSIGN(b, 0x2000); + TASSIGN(c, 0x3000); + TGEMV(c, a, b); +} +``` + +#### 2. TGEMV_ACC + +```cpp +#include + +using namespace pto; + +void example_manual() { + using A = TileLeft; + using B = TileRight; + using C = TileAcc; + A a; + B b; + C c0, c1; + TASSIGN(a, 0x1000); + TASSIGN(b, 0x2000); + TASSIGN(c0, 0x3000); + TASSIGN(c1, 0x4000); + TGEMV_ACC(c1, c0, a, b); +} +``` + +#### 3. TGEMV_BIAS + +```cpp +#include + +using namespace pto; + +void example_manual() { + using A = TileLeft; + using B = TileRight; + using Bias = Tile; + using C = TileAcc; + A a; + B b; + Bias bias; + C c; + TASSIGN(a, 0x1000); + TASSIGN(b, 0x2000); + TASSIGN(bias, 0x3000); + TASSIGN(c, 0x4000); + TGEMV_BIAS(c, a, b, bias); +} +``` + +## 汇编示例（ASM） + +### 自动模式 + +```text +# 自动模式：由编译器/运行时负责资源放置与调度。 +%c = pto.tgemv %a, %b : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### 手动模式 + +```text +# 手动模式：先显式绑定资源，再发射指令。 +# 可选（当该指令包含 tile 操作数时）： +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%c = pto.tgemv %a, %b : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### PTO 汇编形式 + +```text +%acc = tgemv %a, %b : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +# AS Level 2 (DPS) +pto.tgemv ins(%a, %b : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%c : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/TGET_SCALE_ADDR.md b/designs/outerCube/PTOISA/TGET_SCALE_ADDR.md new file mode 100644 index 00000000..458b05ba --- /dev/null +++ b/designs/outerCube/PTOISA/TGET_SCALE_ADDR.md @@ -0,0 +1,83 @@ +# TGET_SCALE_ADDR + +## Tile Operation Diagram + +![TGET_SCALE_ADDR tile operation](../figures/isa/TGET_SCALE_ADDR.svg) + +## Introduction + +Bind the on-chip address of output tile as a scaled address of the input tile. + +The scaling factor is defined by a right-shift amount `SHIFT_MX_ADDR` in `include/pto/npu/a5/utils.hpp`. + +## Math Interpretation + +Address(`dst`) = Address(`src`) >> `SHIFT_MX_ADDR` + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +### IR Level 1 (SSA) + +TODO + +### IR Level 2 (DPS) + +TODO + +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TGET_SCALE_ADDR(TileDataDst &dst, TileDataSrc &src, aitEvents&... events); +``` + +## Constraints + +Enforced by `TGET_SCALE_ADDR_IMPL`: + +- **Both `src` and `dst` must be Tile instances** +- **Currently only work in auto mode** (will support manual mode in the future) + +## Examples + +```cpp +#include + +> wa +using namespace pto; + +template +void example() { + using LeftTile = TileLeft; + using RightTile = TileRight; + + using LeftScaleTile = TileLeftScale; + using RightScaleTile = TileRightScale; + + LeftTile aTile; + RightTile bTile; + LeftScaleTile aScaleTile; + RightScaleTile bScaleTile; + + TGET_SCALE_ADDR(aScaleTile, aTile); + TGET_SCALE_ADDR(bScaleTile, bTile); +} +``` + +## asm form examples + +### Auto Mode + +TODO + +### Manual Mode + +TODO + +### PTO Assembly Form + +TODO diff --git a/designs/outerCube/PTOISA/TGET_SCALE_ADDR_zh.md b/designs/outerCube/PTOISA/TGET_SCALE_ADDR_zh.md new file mode 100644 index 00000000..0dad8946 --- /dev/null +++ b/designs/outerCube/PTOISA/TGET_SCALE_ADDR_zh.md @@ -0,0 +1,81 @@ +# TGET_SCALE_ADDR + +## Tile Operation Diagram + +![TGET_SCALE_ADDR tile operation](../figures/isa/TGET_SCALE_ADDR.svg) + +## Introduction + +将输入Tile的片上地址数值按比例扩展，将其结果数值绑定为输出Tile的片上地址。 + +这个扩展因子是由`include/pto/npu/a5/utils.hpp`中的右移值`SHIFT_MX_ADDR`定义的。 + +## 数学语义 + +Address(`dst`) = Address(`src`) >> `SHIFT_MX_ADDR` + +## 汇编语法 + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +### IR Level 1 (SSA) + +TODO + +### IR Level 2 (DPS) + +TODO + +## C++ 内建接口 + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TGET_SCALE_ADDR(TileDataDst &dst, TileDataSrc &src, aitEvents&... events); +``` + +## 约束 + +- **输入和输出都必须为Tile对象** +- **目前只能用在auto模式下**（以后会将支持manual模式下的实现） + +## 示例 + +```cpp +#include + +> wa +using namespace pto; + +template +void example() { + using LeftTile = TileLeft; + using RightTile = TileRight; + + using LeftScaleTile = TileLeftScale; + using RightScaleTile = TileRightScale; + + LeftTile aTile; + RightTile bTile; + LeftScaleTile aScaleTile; + RightScaleTile bScaleTile; + + TGET_SCALE_ADDR(aScaleTile, aTile); + TGET_SCALE_ADDR(bScaleTile, bTile); +} +``` + +## asm form examples + +### Auto Mode + +TODO + +### Manual Mode + +TODO + +### PTO Assembly Form + +TODO diff --git a/designs/outerCube/PTOISA/THISTOGRAM.md b/designs/outerCube/PTOISA/THISTOGRAM.md new file mode 100644 index 00000000..62186da0 --- /dev/null +++ b/designs/outerCube/PTOISA/THISTOGRAM.md @@ -0,0 +1,40 @@ +# THISTOGRAM + +## Tile Operation Diagram + +![THISTOGRAM tile operation](../figures/isa/THISTOGRAM.svg) + +## Introduction + +Accumulate histogram bin counts from source values using an index tile. + +## Math Interpretation + +Semantics are instruction-specific. Unless stated otherwise, behavior is defined over the destination valid region. + +## Assembly Syntax + +PTO-AS form: see `docs/assembly/PTO-AS.md`. + +### IR Level 1 (SSA) + +```text +%dst = pto.thistogram ... +``` + +### IR Level 2 (DPS) + +```text +pto.thistogram ins(...) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`. + +## Constraints + +Refer to backend-specific legality checks for data type/layout/location/shape constraints. + +## Examples + +See related instruction pages in `docs/isa/` for concrete Auto/Manual usage patterns. diff --git a/designs/outerCube/PTOISA/THISTOGRAM_zh.md b/designs/outerCube/PTOISA/THISTOGRAM_zh.md new file mode 100644 index 00000000..1f352be5 --- /dev/null +++ b/designs/outerCube/PTOISA/THISTOGRAM_zh.md @@ -0,0 +1,41 @@ +# THISTOGRAM + +## 指令示意图 + +![THISTOGRAM tile operation](../figures/isa/THISTOGRAM.svg) + +## 简介 + +使用索引 Tile 从源值中累计直方图 bin 计数。 + +## 数学语义 + +语义随指令而变化。 Unless stated otherwise, behavior is defined over the destination valid region. + +## 汇编语法 + +PTO-AS 形式：参见 `docs/assembly/PTO-AS.md`. + +### AS Level 1（SSA） + +```text +%dst = pto.thistogram ... +``` + +### AS Level 2（DPS） + +```text +pto.thistogram ins(...) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`. + +## 约束 + +Refer to backend-specific legality checks for data type/layout/location/shape constraints. + +## 示例 + +See related instruction pages in `docs/isa/` for concrete Auto/Manual usage patterns. diff --git a/designs/outerCube/PTOISA/TIMG2COL.md b/designs/outerCube/PTOISA/TIMG2COL.md new file mode 100644 index 00000000..5cba652d --- /dev/null +++ b/designs/outerCube/PTOISA/TIMG2COL.md @@ -0,0 +1,85 @@ +# TIMG2COL + + +## Tile Operation Diagram + +![TIMG2COL tile operation](../figures/isa/TIMG2COL.svg) + +## Introduction + +Transform an input feature-map tile (e.g. NC1HWC0 layout) into an im2col-style matrix tile for convolution-like workloads. Parameters are provided via `Img2colTileConfig` and `(posM, posK)` offsets. + +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +PTO_INST RecordEvent TIMG2COL(TileData &dst, ConvTileData &src, uint16_t posM = 0, uint16_t posK = 0, + WaitEvents&... events); +``` + +## Constraints + +- This instruction is target/implementation-specific. See `include/pto/npu/*/TImg2col.hpp` for the supported tile types/layouts and config fields. + +## Math Interpretation + +Unless otherwise specified, semantics are defined over the valid region and target-dependent behavior is marked as implementation-defined. + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +### AS Level 1 (SSA) + +```text +%dst = pto.timg2col %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.timg2col ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### IR Level 1 (SSA) + +```text +%dst = pto.timg2col %src : !pto.tile<...> -> !pto.tile<...> +``` + +### IR Level 2 (DPS) + +```text +pto.timg2col ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## Examples + +See related examples in `docs/isa/` and `docs/coding/tutorials/`. + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.timg2col %src : !pto.tile<...> -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.timg2col %src : !pto.tile<...> -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = pto.timg2col %src : !pto.tile<...> -> !pto.tile<...> +# AS Level 2 (DPS) +pto.timg2col ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TIMG2COL_zh.md b/designs/outerCube/PTOISA/TIMG2COL_zh.md new file mode 100644 index 00000000..c13dacf8 --- /dev/null +++ b/designs/outerCube/PTOISA/TIMG2COL_zh.md @@ -0,0 +1,58 @@ +# TIMG2COL + +## 指令示意图 + +![TIMG2COL tile operation](../figures/isa/TIMG2COL.svg) + +## 简介 + +用于类卷积工作负载的图像到列变换。 + +## 数学语义 + +除非另有说明, semantics are defined over the valid region and target-dependent behavior is marked as implementation-defined. + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS Specification](../assembly/PTO-AS.md). + +### AS Level 1 (SSA) + +```text +%dst = pto.timg2col %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.timg2col ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### AS Level 1（SSA） + +```text +%dst = pto.timg2col %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.timg2col ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`: + +```cpp +PTO_INST RecordEvent TIMG2COL(TileData &dst, ConvTileData &src, uint16_t posM = 0, uint16_t posK = 0, + WaitEvents&... events); +``` + +## 约束 + +- This instruction is target/implementation-specific. See `include/pto/npu/*/TImg2col.hpp` for the supported tile types/layouts and config fields. + +## 示例 + +See related examples in `docs/isa/` and `docs/coding/tutorials/`. diff --git a/designs/outerCube/PTOISA/TINSERT.md b/designs/outerCube/PTOISA/TINSERT.md new file mode 100644 index 00000000..c5f02509 --- /dev/null +++ b/designs/outerCube/PTOISA/TINSERT.md @@ -0,0 +1,107 @@ +# TINSERT + + +## Tile Operation Diagram + +![TINSERT tile operation](../figures/isa/TINSERT.svg) + +## Introduction + +Insert a source sub-tile into a destination tile at `(indexRow, indexCol)`. This is conceptually the inverse of `TEXTRACT` for many layouts. + +## Math Interpretation + +Let `R = src.GetValidRow()` and `C = src.GetValidCol()`. Conceptually, for `0 <= i < R` and `0 <= j < C`: + +$$ +\mathrm{dst}_{\mathrm{indexRow}+i,\;\mathrm{indexCol}+j} = \mathrm{src}_{i,j} +$$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = tinsert %src[%r0, %r1] : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tinsert %src[%r0, %r1] : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tinsert ins(%src[%r0, %r1] : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TINSERT(DstTileData &dst, SrcTileData &src, uint16_t indexRow, uint16_t indexCol, WaitEvents &... events); + +template +PTO_INST RecordEvent TINSERT(DstTileData &dst, SrcTileData &src, uint16_t indexRow, uint16_t indexCol, WaitEvents &... events); + +template +PTO_INST RecordEvent TINSERT(DstTileData &dst, SrcTileData &src, uint64_t preQuantScalar, uint16_t indexRow, uint16_t indexCol, WaitEvents &... events); + +template +PTO_INST RecordEvent TINSERT_FP(DstTileData &dst, SrcTileData &src, FpTileData &fp, uint16_t indexRow, uint16_t indexCol, WaitEvents &... events); + +#ifdef PTO_NPU_ARCH_A5 +template +PTO_INST RecordEvent TINSERT(DstTileData &dst, SrcTileData &src, uint32_t indexRow = 0, uint32_t indexCol = 0, WaitEvents &... events); +#endif +``` + +## Constraints + +- **A2/A3**: + - The documented overloads map to `Acc -> Mat` insertion paths, including plain, `reluMode`, scalar pre-quant, and vector pre-quant (`TINSERT_FP`) forms. + - Runtime bounds must satisfy `indexRow + src.Rows <= dst.Rows` and `indexCol + src.Cols <= dst.Cols`. +- **A5**: + - In addition to the `Acc -> Mat` insertion paths above, A5 also exposes `template TINSERT(...)` for `Vec -> Mat` and `Vec -> Vec` insertion variants. + - `mode == TInsertMode::ND` requires a row-major source vector tile and inserts into a matrix tile in ND layout. + - `mode == TInsertMode::ND_VEC` requires both source and destination to be row-major vector tiles. + - NZ-family modes (`NZ`, `NZ_PLUS_1`, `SPLIT2_NZ_PLUS_1`, `SPLIT4_NZ_PLUS_1`) require an NZ-format source vector tile and a matrix destination tile. + +## Examples + +See related examples in `docs/isa/` and `docs/coding/tutorials/`. + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.tinsert %src[%r0, %r1] : !pto.tile<...> -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tinsert %src[%r0, %r1] : !pto.tile<...> -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = tinsert %src[%r0, %r1] : !pto.tile<...> -> !pto.tile<...> +# AS Level 2 (DPS) +pto.tinsert ins(%src[%r0, %r1] : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/TINSERT_FP.md b/designs/outerCube/PTOISA/TINSERT_FP.md new file mode 100644 index 00000000..ce12ec57 --- /dev/null +++ b/designs/outerCube/PTOISA/TINSERT_FP.md @@ -0,0 +1,90 @@ +# TINSERT_FP + + +## Tile Operation Diagram + +![TINSERT_FP tile operation](../figures/isa/TINSERT_FP.svg) + +## Introduction + +Vector-quantization variant of `TINSERT` that also takes an `fp` (scaling) tile. + +## See also + +- TINSERT base instruction: `docs/isa/TINSERT.md`. + +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TINSERT_FP(DstTileData &dst, SrcTileData &src, FpTileData &fp, uint16_t indexRow, uint16_t indexCol, WaitEvents &... events); +``` + +## Math Interpretation + +Unless otherwise specified, semantics are defined over the valid region and target-dependent behavior is marked as implementation-defined. + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +### AS Level 1 (SSA) + +```text +%dst = pto.tinsert_fp %src, %fp, %idxrow, %idxcol : (!pto.tile<...>, !pto.tile<...>, dtype, dtype) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tinsert_fp ins(%src, %fp, %idxrow, %idxcol : !pto.tile_buf<...>, !pto.tile_buf<...>, dtype, dtype) outs(%dst : !pto.tile_buf<...>) +``` + +### IR Level 1 (SSA) + +```text +%dst = pto.tinsert_fp %src, %fp, %idxrow, %idxcol : (!pto.tile<...>, !pto.tile<...>, dtype, dtype) -> !pto.tile<...> +``` + +### IR Level 2 (DPS) + +```text +pto.tinsert_fp ins(%src, %fp, %idxrow, %idxcol : !pto.tile_buf<...>, !pto.tile_buf<...>, dtype, dtype) outs(%dst : !pto.tile_buf<...>) +``` +## Constraints + +Type/layout/location/shape legality is backend-dependent; treat implementation-specific notes as normative for that backend. + +## Examples + +See related examples in `docs/isa/` and `docs/coding/tutorials/`. + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.tinsert_fp %src, %fp, %idxrow, %idxcol : (!pto.tile<...>, !pto.tile<...>, dtype, dtype) -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tinsert_fp %src, %fp, %idxrow, %idxcol : (!pto.tile<...>, !pto.tile<...>, dtype, dtype) -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = pto.tinsert_fp %src, %fp, %idxrow, %idxcol : (!pto.tile<...>, !pto.tile<...>, dtype, dtype) -> !pto.tile<...> +# AS Level 2 (DPS) +pto.tinsert_fp ins(%src, %fp, %idxrow, %idxcol : !pto.tile_buf<...>, !pto.tile_buf<...>, dtype, dtype) outs(%dst : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TINSERT_FP_zh.md b/designs/outerCube/PTOISA/TINSERT_FP_zh.md new file mode 100644 index 00000000..5dc56ee3 --- /dev/null +++ b/designs/outerCube/PTOISA/TINSERT_FP_zh.md @@ -0,0 +1,59 @@ +# TINSERT_FP + +## 指令示意图 + +![TINSERT_FP tile operation](../figures/isa/TINSERT_FP.svg) + +## 简介 + +带 fp/缩放 Tile 的插入（向量量化参数）。 + +## 数学语义 + +除非另有说明, semantics are defined over the valid region and target-dependent behavior is marked as implementation-defined. + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS Specification](../assembly/PTO-AS.md). + +### AS Level 1 (SSA) + +```text +%dst = pto.tinsert_fp %src, %fp, %idxrow, %idxcol : (!pto.tile<...>, !pto.tile<...>, dtype, dtype) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tinsert_fp ins(%src, %fp, %idxrow, %idxcol : !pto.tile_buf<...>, !pto.tile_buf<...>, dtype, dtype) outs(%dst : !pto.tile_buf<...>) +``` + +### AS Level 1（SSA） + +```text +%dst = pto.tinsert_fp %src, %fp, %idxrow, %idxcol : (!pto.tile<...>, !pto.tile<...>, dtype, dtype) -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.tinsert_fp ins(%src, %fp, %idxrow, %idxcol : !pto.tile_buf<...>, !pto.tile_buf<...>, dtype, dtype) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TINSERT_FP(DstTileData &dst, SrcTileData &src, FpTileData &fp, uint16_t indexRow, uint16_t indexCol, WaitEvents &... events); +``` + +## 约束 + +Type/layout/location/shape legality is backend-dependent; treat implementation-specific notes as normative for that backend. + +## 示例 + +See related examples in `docs/isa/` and `docs/coding/tutorials/`. diff --git a/designs/outerCube/PTOISA/TINSERT_zh.md b/designs/outerCube/PTOISA/TINSERT_zh.md new file mode 100644 index 00000000..80448b6d --- /dev/null +++ b/designs/outerCube/PTOISA/TINSERT_zh.md @@ -0,0 +1,107 @@ +# TINSERT + +## 指令示意图 + +![TINSERT tile operation](../figures/isa/TINSERT.svg) + +## 简介 + +在 (indexRow, indexCol) 偏移处将子 Tile 插入到目标 Tile 中。 + +## 数学语义 + +设 `R = src.GetValidRow()` 和 `C = src.GetValidCol()`。概念上，对于 `0 <= i < R` 和 `0 <= j < C`： + +$$ +\mathrm{dst}_{\mathrm{indexRow}+i,\;\mathrm{indexCol}+j} = \mathrm{src}_{i,j} +$$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS 规范](../assembly/PTO-AS_zh.md)。 + +同步形式： + +```text +%dst = tinsert %src[%r0, %r1] : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 1（SSA） + +```text +%dst = pto.tinsert %src[%r0, %r1] : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.tinsert ins(%src[%r0, %r1] : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`： + +```cpp +template +PTO_INST RecordEvent TINSERT(DstTileData &dst, SrcTileData &src, uint16_t indexRow, uint16_t indexCol, WaitEvents &... events); + +template +PTO_INST RecordEvent TINSERT(DstTileData &dst, SrcTileData &src, uint16_t indexRow, uint16_t indexCol, WaitEvents &... events); + +template +PTO_INST RecordEvent TINSERT(DstTileData &dst, SrcTileData &src, uint64_t preQuantScalar, uint16_t indexRow, uint16_t indexCol, WaitEvents &... events); + +template +PTO_INST RecordEvent TINSERT_FP(DstTileData &dst, SrcTileData &src, FpTileData &fp, uint16_t indexRow, uint16_t indexCol, WaitEvents &... events); + +#ifdef PTO_NPU_ARCH_A5 +template +PTO_INST RecordEvent TINSERT(DstTileData &dst, SrcTileData &src, uint32_t indexRow = 0, uint32_t indexCol = 0, WaitEvents &... events); +#endif +``` + +## 约束 + +- **A2/A3**: + - 文档中列出的这些重载对应 `Acc -> Mat` 插入路径，包括普通形式、`reluMode` 形式、标量预量化形式以及向量预量化（`TINSERT_FP`）形式。 + - 运行时边界必须满足 `indexRow + src.Rows <= dst.Rows` 且 `indexCol + src.Cols <= dst.Cols`。 +- **A5**: + - 除了上面的 `Acc -> Mat` 插入路径外，A5 还额外提供 `template TINSERT(...)`，用于 `Vec -> Mat` 与 `Vec -> Vec` 插入变体。 + - `mode == TInsertMode::ND` 要求源向量 tile 为行优先，并以 ND 布局插入到矩阵 tile。 + - `mode == TInsertMode::ND_VEC` 要求源和目的都为行优先向量 tile。 + - NZ 系列模式（`NZ`、`NZ_PLUS_1`、`SPLIT2_NZ_PLUS_1`、`SPLIT4_NZ_PLUS_1`）要求源向量 tile 为 NZ 格式，目的为矩阵 tile。 + +## 示例 + +参见 `docs/isa/` 和 `docs/coding/tutorials/` 中的相关示例。 + +## 汇编示例（ASM） + +### 自动模式 + +```text +# 自动模式：由编译器/运行时负责资源放置与调度。 +%dst = pto.tinsert %src[%r0, %r1] : !pto.tile<...> -> !pto.tile<...> +``` + +### 手动模式 + +```text +# 手动模式：先显式绑定资源，再发射指令。 +# 可选（当该指令包含 tile 操作数时）： +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tinsert %src[%r0, %r1] : !pto.tile<...> -> !pto.tile<...> +``` + +### PTO 汇编形式 + +```text +%dst = tinsert %src[%r0, %r1] : !pto.tile<...> -> !pto.tile<...> +# AS Level 2 (DPS) +pto.tinsert ins(%src[%r0, %r1] : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/TLOAD.md b/designs/outerCube/PTOISA/TLOAD.md new file mode 100644 index 00000000..3f36e1ee --- /dev/null +++ b/designs/outerCube/PTOISA/TLOAD.md @@ -0,0 +1,159 @@ +# TLOAD + + +## Tile Operation Diagram + +![TLOAD tile operation](../figures/isa/TLOAD.svg) + +## Introduction + +Load data from a GlobalTensor (GM) into a Tile. + +## Math Interpretation + +Notation depends on the `GlobalTensor` shape/stride and the `Tile` layout. Conceptually (2D view, with a base offset): + +$$ \mathrm{dst}_{i,j} = \mathrm{src}_{r_0 + i,\; c_0 + j} $$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%t0 = tload %sv[%c0, %c0] : (!pto.memref<...>, index, index) -> !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tload %mem : !pto.partition_tensor_view -> +!pto.tile +``` + +### AS Level 2 (DPS) + +```text +pto.tload ins(%mem : !pto.partition_tensor_view) outs(%dst : !pto.tile_buf<...>) +``` + +### IR Level 1 (SSA) + +```text +%dst = pto.tload %mem : !pto.partition_tensor_view -> +!pto.tile +``` + +### IR Level 2 (DPS) + +```text +pto.tload ins(%mem : !pto.partition_tensor_view) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TLOAD(TileData &dst, GlobalData &src, WaitEvents &... events); +``` + +## Constraints + +- **Implementation checks (A2A3)**: + - `TileData::DType` must be one of: `int8_t`, `uint8_t`, `int16_t`, `uint16_t`, `int32_t`, `uint32_t`, `int64_t`, `uint64_t`, `half`, `bfloat16_t`, `float`. + - Destination tile location must be `TileType::Vec` or `TileType::Mat`. + - `sizeof(TileData::DType) == sizeof(GlobalData::DType)`. + - Runtime: all `src.GetShape(dim)` values and `dst.GetValidRow()/GetValidCol()` must be `> 0`. + - `TileType::Vec` loads only support matching layouts: ND->ND, DN->DN, NZ->NZ. + - `TileType::Mat` loads support: ND->ND, DN->DN, NZ->NZ, plus ND->NZ and DN->ZN. + - For ND->NZ or DN->ZN: `GlobalData::staticShape[0..2] == 1` and `TileData::SFractalSize == 512`. + - For `int64_t/uint64_t`, only ND->ND or DN->DN are supported. +- **Implementation checks (A5)**: + - `sizeof(TileData::DType)` must be `1`, `2`, `4`, or `8` bytes, and must match `sizeof(GlobalData::DType)`. + - For `int64_t/uint64_t`, `TileData::PadVal` must be `PadValue::Null` or `PadValue::Zero`. + - `TileType::Vec` loads require one of the following layout pairs: + - ND with row-major + `SLayout::NoneBox` (ND->ND), + - DN with col-major + `SLayout::NoneBox` (DN->DN), + - NZ with `SLayout::RowMajor` (NZ->NZ). + - For row-major ND->ND with compile-time-known shapes, `TileData::ValidCol` must equal `GlobalData::staticShape[4]`, and `TileData::ValidRow` must equal the product of `GlobalData::staticShape[0..3]`. + - `TileType::Mat` loads are additionally constrained by `TLoadCubeCheck` (e.g., only specific ND/DN/NZ conversions and L1-size limits). + - `TileType::Mat` loads also handle loads for mx format, which include `MX_A_ZZ/MX_A_ND/MX_A_DN` to ZZ for scalarA and `MX_B_NN/MX_B_ND/MX_B_DN` to NN for scalarB. + - for `MX_A_ZZ/MX_B_NN`: `GlobalData::staticShape[3] == 16` and `GlobalData::staticShape[4] == 2`. + - for `MX_A_ND/MX_ADN/MX_B_ND/MX_B_DN`: `GlobalData::staticShape[0] == 1` and `GlobalData::staticShape[1] == 1` and `GlobalData::staticShape[4] == 2`. + - for scaleA, `dst.GetValidCol() % 2 == 0`. + - for scaleB, `dst.GetValidRow() % 2 == 0` + +- **Valid region**: + - The implementation uses `dst.GetValidRow()` / `dst.GetValidCol()` as the transfer size. + +## Examples + +### Auto + +```cpp +#include + +using namespace pto; + +template +void example_auto(__gm__ T* in) { + using TileT = Tile; + using GShape = Shape<1, 1, 1, 16, 16>; + using GStride = BaseShape2D; + using GTensor = GlobalTensor; + + GTensor gin(in); + TileT t; + TLOAD(t, gin); +} +``` + +### Manual + +```cpp +#include + +using namespace pto; + +template +void example_manual(__gm__ T* in) { + using TileT = Tile; + using GShape = Shape<1, 1, 1, 16, 16>; + using GStride = BaseShape2D; + using GTensor = GlobalTensor; + + GTensor gin(in); + TileT t; + TASSIGN(t, 0x1000); + TLOAD(t, gin); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.tload %mem : !pto.partition_tensor_view -> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tload %mem : !pto.partition_tensor_view -> +``` + +### PTO Assembly Form + +```text +%t0 = tload %sv[%c0, %c0] : (!pto.memref<...>, index, index) -> !pto.tile<...> +# AS Level 2 (DPS) +pto.tload ins(%mem : !pto.partition_tensor_view) outs(%dst : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TLOAD_zh.md b/designs/outerCube/PTOISA/TLOAD_zh.md new file mode 100644 index 00000000..47b25f99 --- /dev/null +++ b/designs/outerCube/PTOISA/TLOAD_zh.md @@ -0,0 +1,132 @@ +# TLOAD + +## 指令示意图 + +![TLOAD tile operation](../figures/isa/TLOAD.svg) + +## 简介 + +从 GlobalTensor (GM) 加载数据到 Tile。 + +## 数学语义 + +Notation depends on the `GlobalTensor` shape/stride and the `Tile` layout. Conceptually (2D view, with a base offset): + +$$ \mathrm{dst}_{i,j} = \mathrm{src}_{r_0 + i,\; c_0 + j} $$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS Specification](../assembly/PTO-AS.md). + +同步形式： + +```text +%t0 = tload %sv[%c0, %c0] : (!pto.memref<...>, index, index) -> !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tload %mem : !pto.partition_tensor_view -> +!pto.tile +``` + +### AS Level 2 (DPS) + +```text +pto.tload ins(%mem : !pto.partition_tensor_view) outs(%dst : !pto.tile_buf<...>) +``` + +### AS Level 1（SSA） + +```text +%dst = pto.tload %mem : !pto.partition_tensor_view -> +!pto.tile +``` + +### AS Level 2（DPS） + +```text +pto.tload ins(%mem : !pto.partition_tensor_view) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TLOAD(TileData &dst, GlobalData &src, WaitEvents &... events); +``` + +## 约束 + +- **实现检查 (A2A3)**: + - `TileData::DType` must be one of: `int8_t`, `uint8_t`, `int16_t`, `uint16_t`, `int32_t`, `uint32_t`, `int64_t`, `uint64_t`, `half`, `bfloat16_t`, `float`. + - Destination tile location must be `TileType::Vec` or `TileType::Mat`. + - `sizeof(TileData::DType) == sizeof(GlobalData::DType)`. + - Runtime: all `src.GetShape(dim)` values and `dst.GetValidRow()/GetValidCol()` must be `> 0`. + - `TileType::Vec` loads only support matching layouts: ND->ND, DN->DN, NZ->NZ. + - `TileType::Mat` loads support: ND->ND, DN->DN, NZ->NZ, plus ND->NZ and DN->ZN. + - For ND->NZ or DN->ZN: `GlobalData::staticShape[0..2] == 1` and `TileData::SFractalSize == 512`. + - For `int64_t/uint64_t`, only ND->ND or DN->DN are supported. +- **实现检查 (A5)**: + - `sizeof(TileData::DType)` must be `1`, `2`, `4`, or `8` bytes, and must match `sizeof(GlobalData::DType)`. + - For `int64_t/uint64_t`, `TileData::PadVal` must be `PadValue::Null` or `PadValue::Zero`. + - `TileType::Vec` loads require one of the following layout pairs: + - ND with row-major + `SLayout::NoneBox` (ND->ND), + - DN with col-major + `SLayout::NoneBox` (DN->DN), + - NZ with `SLayout::RowMajor` (NZ->NZ). + - For row-major ND->ND with compile-time-known shapes, `TileData::ValidCol` must equal `GlobalData::staticShape[4]`, and `TileData::ValidRow` must equal the product of `GlobalData::staticShape[0..3]`. + - `TileType::Mat` loads are additionally constrained by `TLoadCubeCheck` (e.g., only specific ND/DN/NZ conversions and L1-size limits). + - `TileType::Mat` loads also handle loads for mx format, which include `MX_A_ZZ/MX_A_ND/MX_A_DN` to ZZ for scalarA and `MX_B_NN/MX_B_ND/MX_B_DN` to NN for scalarB. + - for `MX_A_ZZ/MX_B_NN`: `GlobalData::staticShape[3] == 16` and `GlobalData::staticShape[4] == 2`. + - for `MX_A_ND/MX_ADN/MX_B_ND/MX_B_DN`: `GlobalData::staticShape[0] == 1` and `GlobalData::staticShape[1] == 1` and `GlobalData::staticShape[4] == 2`. + - for scaleA, `dst.GetValidCol() % 2 == 0`. + - for scaleB, `dst.GetValidRow() % 2 == 0` + +- **有效区域**: + - The implementation uses `dst.GetValidRow()` / `dst.GetValidCol()` as the transfer size. + +## 示例 + +### 自动（Auto） + +```cpp +#include + +using namespace pto; + +template +void example_auto(__gm__ T* in) { + using TileT = Tile; + using GShape = Shape<1, 1, 1, 16, 16>; + using GStride = BaseShape2D; + using GTensor = GlobalTensor; + + GTensor gin(in); + TileT t; + TLOAD(t, gin); +} +``` + +### 手动（Manual） + +```cpp +#include + +using namespace pto; + +template +void example_manual(__gm__ T* in) { + using TileT = Tile; + using GShape = Shape<1, 1, 1, 16, 16>; + using GStride = BaseShape2D; + using GTensor = GlobalTensor; + + GTensor gin(in); + TileT t; + TASSIGN(t, 0x1000); + TLOAD(t, gin); +} +``` diff --git a/designs/outerCube/PTOISA/TLOG.md b/designs/outerCube/PTOISA/TLOG.md new file mode 100644 index 00000000..46148513 --- /dev/null +++ b/designs/outerCube/PTOISA/TLOG.md @@ -0,0 +1,114 @@ +# TLOG + + +## Tile Operation Diagram + +![TLOG tile operation](../figures/isa/TLOG.svg) + +## Introduction + +Elementwise natural logarithm of a tile. + +## Math Interpretation + +For each element `(i, j)` in the valid region: + +$$ \mathrm{dst}_{i,j} = \log(\mathrm{src}_{i,j}) $$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = tlog %src : !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tlog %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tlog ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### IR Level 1 (SSA) + +```text +%dst = pto.tlog %src : !pto.tile<...> -> !pto.tile<...> +``` + +### IR Level 2 (DPS) + +```text +pto.tlog ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TLOG(TileDataDst &dst, TileDataSrc &src, WaitEvents &... events); +``` + +## Constraints + +- **Implementation checks (NPU)**: + - `TileData::DType` must be one of: `float` or `half`; + - Tile location must be vector (`TileData::Loc == TileType::Vec`); + - Static valid bounds: `TileData::ValidRow <= TileData::Rows` and `TileData::ValidCol <= TileData::Cols`; + - Runtime: `src.GetValidRow() == dst.GetValidRow()` and `src.GetValidCol() == dst.GetValidCol()`; + - Tile layout must be row-major (`TileData::isRowMajor`). +- **Valid region**: + - The op uses `dst.GetValidRow()` / `dst.GetValidCol()` as the iteration domain. +- **Domain / NaN**: + - Domain behavior (e.g., `log(<=0)`) is target-defined. + + + +## Examples + +```cpp +#include + +using namespace pto; + +void example() { + using TileT = Tile; + TileT x, out; + TLOG(out, x); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.tlog %src : !pto.tile<...> -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tlog %src : !pto.tile<...> -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = tlog %src : !pto.tile<...> +# AS Level 2 (DPS) +pto.tlog ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TLOG_zh.md b/designs/outerCube/PTOISA/TLOG_zh.md new file mode 100644 index 00000000..67f5924b --- /dev/null +++ b/designs/outerCube/PTOISA/TLOG_zh.md @@ -0,0 +1,85 @@ +# TLOG + +## 指令示意图 + +![TLOG tile operation](../figures/isa/TLOG.svg) + +## 简介 + +Tile 的逐元素自然对数。 + +## 数学语义 + +对每个元素 `(i, j)` 在有效区域内： + +$$ \mathrm{dst}_{i,j} = \log(\mathrm{src}_{i,j}) $$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS Specification](../assembly/PTO-AS.md). + +同步形式： + +```text +%dst = tlog %src : !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tlog %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tlog ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### AS Level 1（SSA） + +```text +%dst = pto.tlog %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.tlog ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TLOG(TileDataDst &dst, TileDataSrc &src, WaitEvents &... events); +``` + +## 约束 + +- **实现检查 (NPU)**: + - `TileData::DType` must be one of: `float` or `half`; + - Tile location must be vector (`TileData::Loc == TileType::Vec`); + - Static valid bounds: `TileData::ValidRow <= TileData::Rows` and `TileData::ValidCol <= TileData::Cols`; + - Runtime: `src.GetValidRow() == dst.GetValidRow()` and `src.GetValidCol() == dst.GetValidCol()`; + - Tile 布局 must be row-major (`TileData::isRowMajor`). +- **有效区域**: + - The op uses `dst.GetValidRow()` / `dst.GetValidCol()` as the iteration domain. +- **Domain / NaN**: + - Domain behavior (e.g., `log(<=0)`) is target-defined. + +## 示例 + +```cpp +#include + +using namespace pto; + +void example() { + using TileT = Tile; + TileT x, out; + TLOG(out, x); +} +``` diff --git a/designs/outerCube/PTOISA/TLRELU.md b/designs/outerCube/PTOISA/TLRELU.md new file mode 100644 index 00000000..3f66bc86 --- /dev/null +++ b/designs/outerCube/PTOISA/TLRELU.md @@ -0,0 +1,104 @@ +# TLRELU + + +## Tile Operation Diagram + +![TLRELU tile operation](../figures/isa/TLRELU.svg) + +## Introduction + +Leaky ReLU with a scalar slope. + +## Math Interpretation + +For each element `(i, j)` in the valid region: + +$$ \mathrm{dst}_{i,j} = (\mathrm{src}_{i,j} > 0) ? \mathrm{src}_{i,j} : (\mathrm{src}_{i,j} \cdot \mathrm{slope}) $$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = tlrelu %src, %slope : !pto.tile<...>, f32 +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tlrelu %src, %scalar : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tlrelu ins(%src, %scalar : !pto.tile_buf<...>, dtype) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TLRELU(TileDataDst& dst, TileDataSrc& src, typename TileDataSrc::DType scalar, WaitEvents&... events); +``` + +## Constraints + +- **Implementation checks (A2A3)**: + - `TileData::DType` must be one of: `half`, `float16_t`, `float`, `float32_t` (floating-point types only). + - Tile layout must be row-major (`TileData::isRowMajor`). +- **Implementation checks (A5)**: + - `TileData::DType` must be one of: `half`, `float` (floating-point types only). + - Tile layout must be row-major (`TileData::isRowMajor`). +- **Common constraints**: + - Tile location must be vector (`TileData::Loc == TileType::Vec`). + - Static valid bounds: `TileData::ValidRow <= TileData::Rows` and `TileData::ValidCol <= TileData::Cols`. + - Runtime: `dst` and `src` must have the same valid row/col. + - Slope scalar type must match the Tile data type. +- **Valid region**: + - The op uses `dst.GetValidRow()` / `dst.GetValidCol()` as the iteration domain. + +## Examples + +```cpp +#include + +using namespace pto; + +void example() { + using TileT = Tile; + TileT x, out; + TLRELU(out, x, 0.1f); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.tlrelu %src, %scalar : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tlrelu %src, %scalar : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = tlrelu %src, %slope : !pto.tile<...>, f32 +# AS Level 2 (DPS) +pto.tlrelu ins(%src, %scalar : !pto.tile_buf<...>, dtype) outs(%dst : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/TLRELU_zh.md b/designs/outerCube/PTOISA/TLRELU_zh.md new file mode 100644 index 00000000..7fc11ff7 --- /dev/null +++ b/designs/outerCube/PTOISA/TLRELU_zh.md @@ -0,0 +1,104 @@ +# TLRELU + +## 指令示意图 + +![TLRELU tile operation](../figures/isa/TLRELU.svg) + +## 简介 + +带标量斜率的 Leaky ReLU。 + +## 数学语义 + +对每个元素 `(i, j)` 在有效区域内： + +$$ \mathrm{dst}_{i,j} = (\mathrm{src}_{i,j} > 0) ? \mathrm{src}_{i,j} : (\mathrm{src}_{i,j} \cdot \mathrm{slope}) $$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS 规范](../assembly/PTO-AS_zh.md)。 + +同步形式： + +```text +%dst = tlrelu %src, %slope : !pto.tile<...>, f32 +``` + +### AS Level 1（SSA） + +```text +%dst = pto.tlrelu %src, %scalar : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.tlrelu ins(%src, %scalar : !pto.tile_buf<...>, dtype) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`： + +```cpp +template +PTO_INST RecordEvent TLRELU(TileDataDst& dst, TileDataSrc& src, typename TileDataSrc::DType scalar, WaitEvents&... events); +``` + +## 约束 + +- **实现检查 (A2A3)**: + - `TileData::DType` 必须是以下之一：`half`、`float16_t`、`float`、`float32_t`（仅浮点类型）。 + - Tile 布局必须是行主序（`TileData::isRowMajor`）。 +- **实现检查 (A5)**: + - `TileData::DType` 必须是以下之一：`half`、`float`（仅浮点类型）。 + - Tile 布局必须是行主序（`TileData::isRowMajor`）。 +- **通用约束**: + - Tile 位置必须是向量（`TileData::Loc == TileType::Vec`）。 + - 静态有效边界：`TileData::ValidRow <= TileData::Rows` 且 `TileData::ValidCol <= TileData::Cols`。 + - 运行时：`dst` 和 `src` 的有效行列数必须相同。 + - 斜率标量类型必须与 Tile 数据类型一致。 +- **有效区域**: + - 该操作使用 `dst.GetValidRow()` / `dst.GetValidCol()` 作为迭代域。 + +## 示例 + +```cpp +#include + +using namespace pto; + +void example() { + using TileT = Tile; + TileT x, out; + TLRELU(out, x, 0.1f); +} +``` + +## 汇编示例（ASM） + +### 自动模式 + +```text +# 自动模式：由编译器/运行时负责资源放置与调度。 +%dst = pto.tlrelu %src, %scalar : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### 手动模式 + +```text +# 手动模式：先显式绑定资源，再发射指令。 +# 可选（当该指令包含 tile 操作数时）： +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tlrelu %src, %scalar : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### PTO 汇编形式 + +```text +%dst = tlrelu %src, %slope : !pto.tile<...>, f32 +# AS Level 2 (DPS) +pto.tlrelu ins(%src, %scalar : !pto.tile_buf<...>, dtype) outs(%dst : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/TMATMUL.md b/designs/outerCube/PTOISA/TMATMUL.md new file mode 100644 index 00000000..3d79405b --- /dev/null +++ b/designs/outerCube/PTOISA/TMATMUL.md @@ -0,0 +1,159 @@ +# TMATMUL + + +## Tile Operation Diagram + +![TMATMUL tile operation](../figures/isa/TMATMUL.svg) + +## Introduction + +Matrix multiply (GEMM) producing an accumulator/output tile. + +## Math Interpretation + +Let: + +- `M = aMatrix.GetValidRow()` +- `K = aMatrix.GetValidCol()` +- `N = bMatrix.GetValidCol()` + +For `0 <= i < M` and `0 <= j < N` (output elements in the effective matmul domain): + +$$ \mathrm{C}_{i,j} = \sum_{k=0}^{K-1} \mathrm{A}_{i,k} \cdot \mathrm{B}_{k,j} $$ + +Exact accumulator behavior and datatype promotion are target/implementation-defined. + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%acc = tmatmul %a, %b : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%c = pto.tmatmul %a, %b : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tmatmul ins(%a, %b : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%c : !pto.tile_buf<...>) +``` + +### IR Level 1 (SSA) + +```text +%c = pto.tmatmul %a, %b : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### IR Level 2 (DPS) + +```text +pto.tmatmul ins(%a, %b : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%c : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TMATMUL(TileRes &cMatrix, TileLeft &aMatrix, TileRight &bMatrix, WaitEvents &... events); + +template +PTO_INST RecordEvent TMATMUL(TileRes &cMatrix, TileLeft &aMatrix, TileRight &bMatrix, WaitEvents &... events); +``` + +## Constraints + +- **Implementation checks (A2A3)**: + - Supported `(CType, AType, BType)` triples: + - `(int32_t, int8_t, int8_t)` + - `(float, half, half)` + - `(float, float, float)` + - `(float, bfloat16_t, bfloat16_t)` + - Static shape constraints: `TileLeft::Rows == TileRes::Rows`, `TileLeft::Cols == TileRight::Rows`, `TileRight::Cols == TileRes::Cols`. + - Tile locations: `TileLeft::Loc == Left`, `TileRight::Loc == Right`, `TileRes::Loc == Acc`. + - Runtime: `m/k/n` (taken from `aMatrix.GetValidRow()`, `aMatrix.GetValidCol()`, `bMatrix.GetValidCol()`) must be in `[1, 4095]`. +- **Implementation checks (A5)**: + - Accumulator type must be `int32_t` or `float`. + - If `int32_t`: `AType == int8_t` and `BType == int8_t`. + - If `float`: supports `half/bfloat16_t/float` and selected fp8 pairs (target-defined). + - Static shape constraints: `TileLeft::Rows == TileRes::Rows`, `TileLeft::Cols == TileRight::Rows`, `TileRight::Cols == TileRes::Cols`. + - Fractal/layout constraints are enforced: + - Left: `Loc == Left`, `!isRowMajor`, `SFractal == RowMajor` + - Right: `Loc == Right`, `isRowMajor`, `SFractal == ColMajor` + - Acc: `Loc == Acc`, `!isRowMajor`, `SFractal == RowMajor` + - Runtime: `m/k/n` (taken from `aMatrix.GetValidRow()`, `aMatrix.GetValidCol()`, `bMatrix.GetValidCol()`) must be in `[1, 4095]`. + +## Examples + +### Auto + +```cpp +#include + +using namespace pto; + +void example_auto() { + using A = TileLeft; + using B = TileRight; + using C = TileAcc; + A a; + B b; + C c; + TMATMUL(c, a, b); +} +``` + +### Manual + +```cpp +#include + +using namespace pto; + +void example_manual() { + using A = TileLeft; + using B = TileRight; + using C = TileAcc; + A a; + B b; + C c; + TASSIGN(a, 0x1000); + TASSIGN(b, 0x2000); + TASSIGN(c, 0x3000); + TMATMUL(c, a, b); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%c = pto.tmatmul %a, %b : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%c = pto.tmatmul %a, %b : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%acc = tmatmul %a, %b : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +# AS Level 2 (DPS) +pto.tmatmul ins(%a, %b : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%c : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TMATMUL_ACC.md b/designs/outerCube/PTOISA/TMATMUL_ACC.md new file mode 100644 index 00000000..e16b45c6 --- /dev/null +++ b/designs/outerCube/PTOISA/TMATMUL_ACC.md @@ -0,0 +1,147 @@ +# TMATMUL_ACC + + +## Tile Operation Diagram + +![TMATMUL_ACC tile operation](../figures/isa/TMATMUL_ACC.svg) + +## Introduction + +Matrix multiply with accumulator input (fused accumulate). + +## Math Interpretation + +Let: + +- `M = aMatrix.GetValidRow()` +- `K = aMatrix.GetValidCol()` +- `N = bMatrix.GetValidCol()` + +For `0 <= i < M` and `0 <= j < N`: + +$$ \mathrm{C1}_{i,j} = \mathrm{C0}_{i,j} + \sum_{k=0}^{K-1} \mathrm{A}_{i,k} \cdot \mathrm{B}_{k,j} $$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%acc1 = tmatmul.acc %acc0, %a, %b : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%c_out = pto.tmatmul.acc %c_in, %a, %b : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tmatmul.acc ins(%c_in, %a, %b : !pto.tile_buf<...>, !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%c_out : !pto.tile_buf<...>) +``` + +### IR Level 1 (SSA) + +```text +%c_out = pto.tmatmul.acc %c_in, %a, %b : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### IR Level 2 (DPS) + +```text +pto.tmatmul.acc ins(%c_in, %a, %b : !pto.tile_buf<...>, !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%c_out : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TMATMUL_ACC(TileRes &cOutMatrix, TileRes &cInMatrix, TileLeft &aMatrix, TileRight &bMatrix, WaitEvents &... events); + +template +PTO_INST RecordEvent TMATMUL_ACC(TileRes &cOutMatrix, TileRes &cInMatrix, TileLeft &aMatrix, TileRight &bMatrix, WaitEvents &... events); + +template +PTO_INST RecordEvent TMATMUL_ACC(TileRes &cMatrix, TileLeft &aMatrix, TileRight &bMatrix, WaitEvents &... events); +``` + +## Constraints + +- All constraints from `TMATMUL` apply to the `(cOutMatrix, aMatrix, bMatrix)` triple. +- **Implementation notes (A2A3/A5)**: + - `TMATMUL_ACC_IMPL` uses `aMatrix.GetValidRow()`, `aMatrix.GetValidCol()`, and `bMatrix.GetValidCol()` for `m/k/n`. + - `cInMatrix` is not validated by explicit assertions in the current implementations (target-defined behavior). + +## Examples + +### Auto + +```cpp +#include + +using namespace pto; + +void example_auto() { + using A = TileLeft; + using B = TileRight; + using C = TileAcc; + A a; + B b; + C c0, c1; + TMATMUL_ACC(c1, c0, a, b); +} +``` + +### Manual + +```cpp +#include + +using namespace pto; + +void example_manual() { + using A = TileLeft; + using B = TileRight; + using C = TileAcc; + A a; + B b; + C c0, c1; + TASSIGN(a, 0x1000); + TASSIGN(b, 0x2000); + TASSIGN(c0, 0x3000); + TASSIGN(c1, 0x4000); + TMATMUL_ACC(c1, c0, a, b); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%c_out = pto.tmatmul.acc %c_in, %a, %b : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%c_out = pto.tmatmul.acc %c_in, %a, %b : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%acc1 = tmatmul.acc %acc0, %a, %b : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +# AS Level 2 (DPS) +pto.tmatmul.acc ins(%c_in, %a, %b : !pto.tile_buf<...>, !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%c_out : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TMATMUL_ACC_zh.md b/designs/outerCube/PTOISA/TMATMUL_ACC_zh.md new file mode 100644 index 00000000..a7868230 --- /dev/null +++ b/designs/outerCube/PTOISA/TMATMUL_ACC_zh.md @@ -0,0 +1,120 @@ +# TMATMUL_ACC + +## 指令示意图 + +![TMATMUL_ACC tile operation](../figures/isa/TMATMUL_ACC.svg) + +## 简介 + +带累加器输入的矩阵乘法（融合累加）。 + +## 数学语义 + +Let: + +- `M = aMatrix.GetValidRow()` +- `K = aMatrix.GetValidCol()` +- `N = bMatrix.GetValidCol()` + +For `0 <= i < M` and `0 <= j < N`: + +$$ \mathrm{C1}_{i,j} = \mathrm{C0}_{i,j} + \sum_{k=0}^{K-1} \mathrm{A}_{i,k} \cdot \mathrm{B}_{k,j} $$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS Specification](../assembly/PTO-AS.md). + +同步形式： + +```text +%acc1 = tmatmul.acc %acc0, %a, %b : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%c_out = pto.tmatmul.acc %c_in, %a, %b : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tmatmul.acc ins(%c_in, %a, %b : !pto.tile_buf<...>, !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%c_out : !pto.tile_buf<...>) +``` + +### AS Level 1（SSA） + +```text +%c_out = pto.tmatmul.acc %c_in, %a, %b : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.tmatmul.acc ins(%c_in, %a, %b : !pto.tile_buf<...>, !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%c_out : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TMATMUL_ACC(TileRes &cOutMatrix, TileRes &cInMatrix, TileLeft &aMatrix, TileRight &bMatrix, WaitEvents &... events); + +template +PTO_INST RecordEvent TMATMUL_ACC(TileRes &cOutMatrix, TileRes &cInMatrix, TileLeft &aMatrix, TileRight &bMatrix, WaitEvents &... events); + +template +PTO_INST RecordEvent TMATMUL_ACC(TileRes &cMatrix, TileLeft &aMatrix, TileRight &bMatrix, WaitEvents &... events); +``` + +## 约束 + +- All constraints from `TMATMUL` apply to the `(cOutMatrix, aMatrix, bMatrix)` triple. +- **Implementation notes (A2A3/A5)**: + - `TMATMUL_ACC_IMPL` uses `aMatrix.GetValidRow()`, `aMatrix.GetValidCol()`, and `bMatrix.GetValidCol()` for `m/k/n`. + - `cInMatrix` is not validated by explicit assertions in the current implementations (target-defined behavior). + +## 示例 + +### 自动（Auto） + +```cpp +#include + +using namespace pto; + +void example_auto() { + using A = TileLeft; + using B = TileRight; + using C = TileAcc; + A a; + B b; + C c0, c1; + TMATMUL_ACC(c1, c0, a, b); +} +``` + +### 手动（Manual） + +```cpp +#include + +using namespace pto; + +void example_manual() { + using A = TileLeft; + using B = TileRight; + using C = TileAcc; + A a; + B b; + C c0, c1; + TASSIGN(a, 0x1000); + TASSIGN(b, 0x2000); + TASSIGN(c0, 0x3000); + TASSIGN(c1, 0x4000); + TMATMUL_ACC(c1, c0, a, b); +} +``` diff --git a/designs/outerCube/PTOISA/TMATMUL_BIAS.md b/designs/outerCube/PTOISA/TMATMUL_BIAS.md new file mode 100644 index 00000000..e3326e46 --- /dev/null +++ b/designs/outerCube/PTOISA/TMATMUL_BIAS.md @@ -0,0 +1,153 @@ +# TMATMUL_BIAS + + +## Tile Operation Diagram + +![TMATMUL_BIAS tile operation](../figures/isa/TMATMUL_BIAS.svg) + +## Introduction + +Matrix multiply with bias add. + +## Math Interpretation + +Let: + +- `M = aMatrix.GetValidRow()` +- `K = aMatrix.GetValidCol()` +- `N = bMatrix.GetValidCol()` + +For `0 <= i < M` and `0 <= j < N`: + +$$ \mathrm{C}_{i,j} = \sum_{k=0}^{K-1} \mathrm{A}_{i,k} \cdot \mathrm{B}_{k,j} + \mathrm{Bias}_{0,j} $$ + +Bias broadcasting behavior is implementation-defined. + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%acc = tmatmul.bias %a, %b, %bias : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%c = pto.tmatmul.bias %a, %b, %bias : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tmatmul.bias ins(%a, %b, %bias : !pto.tile_buf<...>, !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%c : !pto.tile_buf<...>) +``` + +### IR Level 1 (SSA) + +```text +%c = pto.tmatmul.bias %a, %b, %bias : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### IR Level 2 (DPS) + +```text +pto.tmatmul.bias ins(%a, %b, %bias : !pto.tile_buf<...>, !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%c : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TMATMUL_BIAS(TileRes &cMatrix, TileLeft &aMatrix, TileRight &bMatrix, TileBias &biasData, WaitEvents &... events); + +template +PTO_INST RecordEvent TMATMUL_BIAS(TileRes &cMatrix, TileLeft &aMatrix, TileRight &bMatrix, TileBias &biasData, WaitEvents &... events); +``` + +## Constraints + +- All constraints from `TMATMUL` apply to the `(cMatrix, aMatrix, bMatrix)` triple. +- **Bias constraints (A2A3)**: + - `TileBias::DType` must match `TileRes::DType`. + - `TileBias::Loc == TileType::Bias` and `TileBias::Rows == 1`. +- **Bias constraints (A5)**: + - `TileBias::DType` must match `TileRes::DType`. + - `TileBias::Loc == TileType::Bias`, `TileBias::Rows == 1`, and `TileBias::isRowMajor`. + +## Examples + +### Auto + +```cpp +#include + +using namespace pto; + +void example_auto() { + using A = TileLeft; + using B = TileRight; + using Bias = Tile; + using C = TileAcc; + A a; + B b; + Bias bias; + C c; + TMATMUL_BIAS(c, a, b, bias); +} +``` + +### Manual + +```cpp +#include + +using namespace pto; + +void example_manual() { + using A = TileLeft; + using B = TileRight; + using Bias = Tile; + using C = TileAcc; + A a; + B b; + Bias bias; + C c; + TASSIGN(a, 0x1000); + TASSIGN(b, 0x2000); + TASSIGN(bias, 0x3000); + TASSIGN(c, 0x4000); + TMATMUL_BIAS(c, a, b, bias); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%c = pto.tmatmul.bias %a, %b, %bias : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%c = pto.tmatmul.bias %a, %b, %bias : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%acc = tmatmul.bias %a, %b, %bias : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +# AS Level 2 (DPS) +pto.tmatmul.bias ins(%a, %b, %bias : !pto.tile_buf<...>, !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%c : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TMATMUL_BIAS_zh.md b/designs/outerCube/PTOISA/TMATMUL_BIAS_zh.md new file mode 100644 index 00000000..daa5bad0 --- /dev/null +++ b/designs/outerCube/PTOISA/TMATMUL_BIAS_zh.md @@ -0,0 +1,126 @@ +# TMATMUL_BIAS + +## 指令示意图 + +![TMATMUL_BIAS tile operation](../figures/isa/TMATMUL_BIAS.svg) + +## 简介 + +带偏置加法的矩阵乘法。 + +## 数学语义 + +Let: + +- `M = aMatrix.GetValidRow()` +- `K = aMatrix.GetValidCol()` +- `N = bMatrix.GetValidCol()` + +For `0 <= i < M` and `0 <= j < N`: + +$$ \mathrm{C}_{i,j} = \sum_{k=0}^{K-1} \mathrm{A}_{i,k} \cdot \mathrm{B}_{k,j} + \mathrm{Bias}_{0,j} $$ + +Bias broadcasting behavior is implementation-defined. + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS Specification](../assembly/PTO-AS.md). + +同步形式： + +```text +%acc = tmatmul.bias %a, %b, %bias : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%c = pto.tmatmul.bias %a, %b, %bias : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tmatmul.bias ins(%a, %b, %bias : !pto.tile_buf<...>, !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%c : !pto.tile_buf<...>) +``` + +### AS Level 1（SSA） + +```text +%c = pto.tmatmul.bias %a, %b, %bias : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.tmatmul.bias ins(%a, %b, %bias : !pto.tile_buf<...>, !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%c : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TMATMUL_BIAS(TileRes &cMatrix, TileLeft &aMatrix, TileRight &bMatrix, TileBias &biasData, WaitEvents &... events); + +template +PTO_INST RecordEvent TMATMUL_BIAS(TileRes &cMatrix, TileLeft &aMatrix, TileRight &bMatrix, TileBias &biasData, WaitEvents &... events); +``` + +## 约束 + +- All constraints from `TMATMUL` apply to the `(cMatrix, aMatrix, bMatrix)` triple. +- **Bias constraints (A2A3)**: + - `TileBias::DType` must match `TileRes::DType`. + - `TileBias::Loc == TileType::Bias` and `TileBias::Rows == 1`. +- **Bias constraints (A5)**: + - `TileBias::DType` must match `TileRes::DType`. + - `TileBias::Loc == TileType::Bias`, `TileBias::Rows == 1`, and `TileBias::isRowMajor`. + +## 示例 + +### 自动（Auto） + +```cpp +#include + +using namespace pto; + +void example_auto() { + using A = TileLeft; + using B = TileRight; + using Bias = Tile; + using C = TileAcc; + A a; + B b; + Bias bias; + C c; + TMATMUL_BIAS(c, a, b, bias); +} +``` + +### 手动（Manual） + +```cpp +#include + +using namespace pto; + +void example_manual() { + using A = TileLeft; + using B = TileRight; + using Bias = Tile; + using C = TileAcc; + A a; + B b; + Bias bias; + C c; + TASSIGN(a, 0x1000); + TASSIGN(b, 0x2000); + TASSIGN(bias, 0x3000); + TASSIGN(c, 0x4000); + TMATMUL_BIAS(c, a, b, bias); +} +``` diff --git a/designs/outerCube/PTOISA/TMATMUL_MX.md b/designs/outerCube/PTOISA/TMATMUL_MX.md new file mode 100644 index 00000000..935d4c1e --- /dev/null +++ b/designs/outerCube/PTOISA/TMATMUL_MX.md @@ -0,0 +1,202 @@ +# TMATMUL_MX + + +## Tile Operation Diagram + +![TMATMUL_MX tile operation](../figures/isa/TMATMUL_MX.svg) + +## Introduction + +Matrix multiply (GEMM) with additional scaling tiles for mixed-precision / quantized matmul on supported targets. + +This instruction is currently implemented on A5 (see `include/pto/npu/a5/TMatmul.hpp`). + +## Math Interpretation + +Let: + +- `M = aMatrix.GetValidRow()` +- `K = aMatrix.GetValidCol()` +- `N = bMatrix.GetValidCol()` + +Conceptually, the result corresponds to a matrix multiply over the effective matmul domain (`0 <= i < M`, `0 <= j < N`), with the scaling tiles `aScaleMatrix` / `bScaleMatrix` configuring implementation-defined mixed-precision behavior: + +$$ \mathrm{C}_{i,j} = \sum_{k=0}^{K-1} \mathrm{A}_{i,k} \cdot \mathrm{B}_{k,j} $$ + +The exact role of `aScaleMatrix` / `bScaleMatrix` (and any dequant/quant semantics) is target-defined. + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous forms (conceptual): + +```text +%c = tmatmul.mx %a, %a_scale, %b, %b_scale : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +%c_out = tmatmul.mx.acc %c_in, %a, %a_scale, %b, %b_scale : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +%c = tmatmul.mx.bias %a, %a_scale, %b, %b_scale, %bias : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%c = pto.tmatmul.mx %a, %a_scale, %b, %b_scale : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>, !pto.tile<...>) +-> !pto.tile<...> +%c_out = pto.tmatmul.mx.acc %c_in, %a, %a_scale, %b, %b_scale : (!pto.tile<...>, !pto.tile<...>, +!pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +%c = pto.tmatmul.mx.bias %a, %a_scale, %b, %b_scale, %bias : (!pto.tile<...>, !pto.tile<...>, +!pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tmatmul.mx ins(%a, %a_scale, %b, %b_scale : !pto.tile_buf<...>, !pto.tile_buf<...>, !pto.tile_buf<...>, !pto.tile_buf<...>) +outs(%c : !pto.tile_buf<...>) +pto.tmatmul.mx.acc ins(%c_in, %a, %a_scale, %b, %b_scale : !pto.tile_buf<...>, !pto.tile_buf<...>, !pto.tile_buf<...>, +!pto.tile_buf<...>, !pto.tile_buf<...>) outs(%c_out : !pto.tile_buf<...>) +pto.tmatmul.mx.bias ins(%a, %a_scale, %b, %b_scale, %bias : !pto.tile_buf<...>, !pto.tile_buf<...>, !pto.tile_buf<...>, +!pto.tile_buf<...>, !pto.tile_buf<...>) outs(%c : !pto.tile_buf<...>) +``` + +### IR Level 1 (SSA) + +```text +%c = pto.tmatmul.mx %a, %a_scale, %b, %b_scale : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>, !pto.tile<...>) +-> !pto.tile<...> +%c_out = pto.tmatmul.mx.acc %c_in, %a, %a_scale, %b, %b_scale : (!pto.tile<...>, !pto.tile<...>, +!pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +%c = pto.tmatmul.mx.bias %a, %a_scale, %b, %b_scale, %bias : (!pto.tile<...>, !pto.tile<...>, +!pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### IR Level 2 (DPS) + +```text +pto.tmatmul.mx ins(%a, %a_scale, %b, %b_scale : !pto.tile_buf<...>, !pto.tile_buf<...>, !pto.tile_buf<...>, !pto.tile_buf<...>) +outs(%c : !pto.tile_buf<...>) +pto.tmatmul.mx.acc ins(%c_in, %a, %a_scale, %b, %b_scale : !pto.tile_buf<...>, !pto.tile_buf<...>, !pto.tile_buf<...>, +!pto.tile_buf<...>, !pto.tile_buf<...>) outs(%c_out : !pto.tile_buf<...>) +pto.tmatmul.mx.bias ins(%a, %a_scale, %b, %b_scale, %bias : !pto.tile_buf<...>, !pto.tile_buf<...>, !pto.tile_buf<...>, +!pto.tile_buf<...>, !pto.tile_buf<...>) outs(%c : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TMATMUL_MX(TileRes &cMatrix, TileLeft &aMatrix, TileLeftScale &aScaleMatrix, TileRight &bMatrix, TileRightScale &bScaleMatrix, WaitEvents &... events); + +template +PTO_INST RecordEvent TMATMUL_MX(TileRes &cMatrix, TileLeft &aMatrix, TileLeftScale &aScaleMatrix, TileRight &bMatrix, TileRightScale &bScaleMatrix, WaitEvents &... events); + +template +PTO_INST RecordEvent TMATMUL_MX(TileRes &cOutMatrix, TileRes &cInMatrix, TileLeft &aMatrix, TileLeftScale &aScaleMatrix, TileRight &bMatrix, TileRightScale &bScaleMatrix, WaitEvents &... events); + +template +PTO_INST RecordEvent TMATMUL_MX(TileRes &cOutMatrix, TileRes &cInMatrix, TileLeft &aMatrix, TileLeftScale &aScaleMatrix, TileRight &bMatrix, TileRightScale &bScaleMatrix, WaitEvents &... events); + +template +PTO_INST RecordEvent TMATMUL_MX(TileRes &cMatrix, TileLeft &aMatrix, TileLeftScale &aScaleMatrix, TileRight &bMatrix, TileRightScale &bScaleMatrix, TileBias &biasData, WaitEvents &... events); + +template +PTO_INST RecordEvent TMATMUL_MX(TileRes &cMatrix, TileLeft &aMatrix, TileLeftScale &aScaleMatrix, TileRight &bMatrix, TileRightScale &bScaleMatrix, TileBias &biasData, WaitEvents &... events); +``` + +## Constraints + +- **Implementation checks (A5)**: + - `m/k/n` are taken from `aMatrix.GetValidRow()`, `aMatrix.GetValidCol()`, `bMatrix.GetValidCol()`. + - Static legality checks are enforced via `CheckMadMxValid<...>()` (types, shapes, fractals, and scaling tile legality). +- **Bias form**: + - `TileBias::DType` must be `float` and `TileBias::Loc == TileType::Bias` with `TileBias::Rows == 1` (A5 checks via `static_assert`). + +## Examples + +### Auto + +```cpp +#include + +using namespace pto; + +void example_auto() { + using A = TileLeft; + using B = TileRight; + using ScaleA = TileLeftScale; + using ScaleB = TileRightScale; + using Bias = Tile; + using C = TileAcc; + A a; + B b; + ScaleA scaleA; + ScaleB scaleB; + Bias bias; + C c; + TMATMUL_MX(c, a, scaleA, b, scaleB, bias); +} +``` + +### Manual + +```cpp +#include + +using namespace pto; + +void example_manual() { + using A = TileLeft; + using B = TileRight; + using ScaleA = TileLeftScale; + using ScaleB = TileRightScale; + using Bias = Tile; + using C = TileAcc; + A a; + B b; + ScaleA scaleA; + ScaleB scaleB; + Bias bias; + C c; + TASSIGN(a, 0x1000); + TASSIGN(b, 0x2000); + TASSIGN(scaleA, GetScaleAddr(a.data())); + TASSIGN(scaleB, GetScaleAddr(b.data())); + TASSIGN(bias, 0x3000); + TASSIGN(c, 0x4000); + TMATMUL_MX(c, a, scaleA, b, scaleB, bias); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%c = pto.tmatmul.mx %a, %a_scale, %b, %b_scale : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>, !pto.tile<...>) +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%c = pto.tmatmul.mx %a, %a_scale, %b, %b_scale : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>, !pto.tile<...>) +``` + +### PTO Assembly Form + +```text +%c = pto.tmatmul.mx %a, %a_scale, %b, %b_scale : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>, !pto.tile<...>) +# AS Level 2 (DPS) +pto.tmatmul.mx ins(%a, %a_scale, %b, %b_scale : !pto.tile_buf<...>, !pto.tile_buf<...>, !pto.tile_buf<...>, !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TMATMUL_MX_zh.md b/designs/outerCube/PTOISA/TMATMUL_MX_zh.md new file mode 100644 index 00000000..738035e6 --- /dev/null +++ b/designs/outerCube/PTOISA/TMATMUL_MX_zh.md @@ -0,0 +1,173 @@ +# TMATMUL_MX + +## 指令示意图 + +![TMATMUL_MX tile operation](../figures/isa/TMATMUL_MX.svg) + +## 简介 + +带额外缩放 Tile 的矩阵乘法 (GEMM)，用于支持目标上的混合精度/量化矩阵乘法。 + +## 数学语义 + +Let: + +- `M = aMatrix.GetValidRow()` +- `K = aMatrix.GetValidCol()` +- `N = bMatrix.GetValidCol()` + +Conceptually, the result corresponds to a matrix multiply over the effective matmul domain (`0 <= i < M`, `0 <= j < N`), with the scaling tiles `aScaleMatrix` / `bScaleMatrix` configuring implementation-defined mixed-precision behavior: + +$$ \mathrm{C}_{i,j} = \sum_{k=0}^{K-1} \mathrm{A}_{i,k} \cdot \mathrm{B}_{k,j} $$ + +The exact role of `aScaleMatrix` / `bScaleMatrix` (and any dequant/quant semantics) is target-defined. + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous forms (conceptual): + +```text +%c = tmatmul.mx %a, %a_scale, %b, %b_scale : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +%c_out = tmatmul.mx.acc %c_in, %a, %a_scale, %b, %b_scale : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +%c = tmatmul.mx.bias %a, %a_scale, %b, %b_scale, %bias : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%c = pto.tmatmul.mx %a, %a_scale, %b, %b_scale : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>, !pto.tile<...>) +-> !pto.tile<...> +%c_out = pto.tmatmul.mx.acc %c_in, %a, %a_scale, %b, %b_scale : (!pto.tile<...>, !pto.tile<...>, +!pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +%c = pto.tmatmul.mx.bias %a, %a_scale, %b, %b_scale, %bias : (!pto.tile<...>, !pto.tile<...>, +!pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tmatmul.mx ins(%a, %a_scale, %b, %b_scale : !pto.tile_buf<...>, !pto.tile_buf<...>, !pto.tile_buf<...>, !pto.tile_buf<...>) +outs(%c : !pto.tile_buf<...>) +pto.tmatmul.mx.acc ins(%c_in, %a, %a_scale, %b, %b_scale : !pto.tile_buf<...>, !pto.tile_buf<...>, !pto.tile_buf<...>, +!pto.tile_buf<...>, !pto.tile_buf<...>) outs(%c_out : !pto.tile_buf<...>) +pto.tmatmul.mx.bias ins(%a, %a_scale, %b, %b_scale, %bias : !pto.tile_buf<...>, !pto.tile_buf<...>, !pto.tile_buf<...>, +!pto.tile_buf<...>, !pto.tile_buf<...>) outs(%c : !pto.tile_buf<...>) +``` + +### AS Level 1（SSA） + +```text +%c = pto.tmatmul.mx %a, %a_scale, %b, %b_scale : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>, !pto.tile<...>) +-> !pto.tile<...> +%c_out = pto.tmatmul.mx.acc %c_in, %a, %a_scale, %b, %b_scale : (!pto.tile<...>, !pto.tile<...>, +!pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +%c = pto.tmatmul.mx.bias %a, %a_scale, %b, %b_scale, %bias : (!pto.tile<...>, !pto.tile<...>, +!pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.tmatmul.mx ins(%a, %a_scale, %b, %b_scale : !pto.tile_buf<...>, !pto.tile_buf<...>, !pto.tile_buf<...>, !pto.tile_buf<...>) +outs(%c : !pto.tile_buf<...>) +pto.tmatmul.mx.acc ins(%c_in, %a, %a_scale, %b, %b_scale : !pto.tile_buf<...>, !pto.tile_buf<...>, !pto.tile_buf<...>, +!pto.tile_buf<...>, !pto.tile_buf<...>) outs(%c_out : !pto.tile_buf<...>) +pto.tmatmul.mx.bias ins(%a, %a_scale, %b, %b_scale, %bias : !pto.tile_buf<...>, !pto.tile_buf<...>, !pto.tile_buf<...>, +!pto.tile_buf<...>, !pto.tile_buf<...>) outs(%c : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TMATMUL_MX(TileRes &cMatrix, TileLeft &aMatrix, TileLeftScale &aScaleMatrix, TileRight &bMatrix, TileRightScale &bScaleMatrix, WaitEvents &... events); + +template +PTO_INST RecordEvent TMATMUL_MX(TileRes &cMatrix, TileLeft &aMatrix, TileLeftScale &aScaleMatrix, TileRight &bMatrix, TileRightScale &bScaleMatrix, WaitEvents &... events); + +template +PTO_INST RecordEvent TMATMUL_MX(TileRes &cOutMatrix, TileRes &cInMatrix, TileLeft &aMatrix, TileLeftScale &aScaleMatrix, TileRight &bMatrix, TileRightScale &bScaleMatrix, WaitEvents &... events); + +template +PTO_INST RecordEvent TMATMUL_MX(TileRes &cOutMatrix, TileRes &cInMatrix, TileLeft &aMatrix, TileLeftScale &aScaleMatrix, TileRight &bMatrix, TileRightScale &bScaleMatrix, WaitEvents &... events); + +template +PTO_INST RecordEvent TMATMUL_MX(TileRes &cMatrix, TileLeft &aMatrix, TileLeftScale &aScaleMatrix, TileRight &bMatrix, TileRightScale &bScaleMatrix, TileBias &biasData, WaitEvents &... events); + +template +PTO_INST RecordEvent TMATMUL_MX(TileRes &cMatrix, TileLeft &aMatrix, TileLeftScale &aScaleMatrix, TileRight &bMatrix, TileRightScale &bScaleMatrix, TileBias &biasData, WaitEvents &... events); +``` + +## 约束 + +- **实现检查 (A5)**: + - `m/k/n` are taken from `aMatrix.GetValidRow()`, `aMatrix.GetValidCol()`, `bMatrix.GetValidCol()`. + - Static legality checks are enforced via `CheckMadMxValid<...>()` (types, shapes, fractals, and scaling tile legality). +- **Bias form**: + - `TileBias::DType` must be `float` and `TileBias::Loc == TileType::Bias` with `TileBias::Rows == 1` (A5 checks via `static_assert`). + +## 示例 + +### 自动（Auto） + +```cpp +#include + +using namespace pto; + +void example_auto() { + using A = TileLeft; + using B = TileRight; + using ScaleA = TileLeftScale; + using ScaleB = TileRightScale; + using Bias = Tile; + using C = TileAcc; + A a; + B b; + ScaleA scaleA; + ScaleB scaleB; + Bias bias; + C c; + TMATMUL_MX(c, a, scaleA, b, scaleB, bias); +} +``` + +### 手动（Manual） + +```cpp +#include + +using namespace pto; + +void example_manual() { + using A = TileLeft; + using B = TileRight; + using ScaleA = TileLeftScale; + using ScaleB = TileRightScale; + using Bias = Tile; + using C = TileAcc; + A a; + B b; + ScaleA scaleA; + ScaleB scaleB; + Bias bias; + C c; + TASSIGN(a, 0x1000); + TASSIGN(b, 0x2000); + TASSIGN(scaleA, GetScaleAddr(a.data())); + TASSIGN(scaleB, GetScaleAddr(b.data())); + TASSIGN(bias, 0x3000); + TASSIGN(c, 0x4000); + TMATMUL_MX(c, a, scaleA, b, scaleB, bias); +} +``` diff --git a/designs/outerCube/PTOISA/TMATMUL_zh.md b/designs/outerCube/PTOISA/TMATMUL_zh.md new file mode 100644 index 00000000..dbe425a8 --- /dev/null +++ b/designs/outerCube/PTOISA/TMATMUL_zh.md @@ -0,0 +1,132 @@ +# TMATMUL + +## 指令示意图 + +![TMATMUL tile operation](../figures/isa/TMATMUL.svg) + +## 简介 + +矩阵乘法 (GEMM)，生成累加器/输出 Tile。 + +## 数学语义 + +Let: + +- `M = aMatrix.GetValidRow()` +- `K = aMatrix.GetValidCol()` +- `N = bMatrix.GetValidCol()` + +For `0 <= i < M` and `0 <= j < N` (output elements in the effective matmul domain): + +$$ \mathrm{C}_{i,j} = \sum_{k=0}^{K-1} \mathrm{A}_{i,k} \cdot \mathrm{B}_{k,j} $$ + +Exact accumulator behavior and datatype promotion are target/implementation-defined. + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS Specification](../assembly/PTO-AS.md). + +同步形式： + +```text +%acc = tmatmul %a, %b : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%c = pto.tmatmul %a, %b : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tmatmul ins(%a, %b : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%c : !pto.tile_buf<...>) +``` + +### AS Level 1（SSA） + +```text +%c = pto.tmatmul %a, %b : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.tmatmul ins(%a, %b : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%c : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TMATMUL(TileRes &cMatrix, TileLeft &aMatrix, TileRight &bMatrix, WaitEvents &... events); + +template +PTO_INST RecordEvent TMATMUL(TileRes &cMatrix, TileLeft &aMatrix, TileRight &bMatrix, WaitEvents &... events); +``` + +## 约束 + +- **实现检查 (A2A3)**: + - Supported `(CType, AType, BType)` triples: + - `(int32_t, int8_t, int8_t)` + - `(float, half, half)` + - `(float, float, float)` + - `(float, bfloat16_t, bfloat16_t)` + - Static shape constraints: `TileLeft::Rows == TileRes::Rows`, `TileLeft::Cols == TileRight::Rows`, `TileRight::Cols == TileRes::Cols`. + - Tile locations: `TileLeft::Loc == Left`, `TileRight::Loc == Right`, `TileRes::Loc == Acc`. + - Runtime: `m/k/n` (taken from `aMatrix.GetValidRow()`, `aMatrix.GetValidCol()`, `bMatrix.GetValidCol()`) must be in `[1, 4095]`. +- **实现检查 (A5)**: + - Accumulator type must be `int32_t` or `float`. + - If `int32_t`: `AType == int8_t` and `BType == int8_t`. + - If `float`: supports `half/bfloat16_t/float` and selected fp8 pairs (target-defined). + - Static shape constraints: `TileLeft::Rows == TileRes::Rows`, `TileLeft::Cols == TileRight::Rows`, `TileRight::Cols == TileRes::Cols`. + - Fractal/layout constraints are enforced: + - Left: `Loc == Left`, `!isRowMajor`, `SFractal == RowMajor` + - Right: `Loc == Right`, `isRowMajor`, `SFractal == ColMajor` + - Acc: `Loc == Acc`, `!isRowMajor`, `SFractal == RowMajor` + - Runtime: `m/k/n` (taken from `aMatrix.GetValidRow()`, `aMatrix.GetValidCol()`, `bMatrix.GetValidCol()`) must be in `[1, 4095]`. + +## 示例 + +### 自动（Auto） + +```cpp +#include + +using namespace pto; + +void example_auto() { + using A = TileLeft; + using B = TileRight; + using C = TileAcc; + A a; + B b; + C c; + TMATMUL(c, a, b); +} +``` + +### 手动（Manual） + +```cpp +#include + +using namespace pto; + +void example_manual() { + using A = TileLeft; + using B = TileRight; + using C = TileAcc; + A a; + B b; + C c; + TASSIGN(a, 0x1000); + TASSIGN(b, 0x2000); + TASSIGN(c, 0x3000); + TMATMUL(c, a, b); +} +``` diff --git a/designs/outerCube/PTOISA/TMAX.md b/designs/outerCube/PTOISA/TMAX.md new file mode 100644 index 00000000..b46691b1 --- /dev/null +++ b/designs/outerCube/PTOISA/TMAX.md @@ -0,0 +1,135 @@ +# TMAX + + +## Tile Operation Diagram + +![TMAX tile operation](../figures/isa/TMAX.svg) + +## Introduction + +Elementwise maximum of two tiles. + +## Math Interpretation + +For each element `(i, j)` in the valid region: + +$$ \mathrm{dst}_{i,j} = \max(\mathrm{src0}_{i,j}, \mathrm{src1}_{i,j}) $$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = tmax %src0, %src1 : !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tmax %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tmax ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### IR Level 1 (SSA) + +```text +%dst = pto.tmax %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### IR Level 2 (DPS) + +```text +pto.tmax ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TMAX(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, WaitEvents &... events); +``` + +## Constraints + +- **Implementation checks (A2A3)**: + - `TileData::DType` must be one of: `int32_t`, `int16_t`, `half`, `float`. + - Tile layout must be row-major (`TileData::isRowMajor`). + - Tile location must be vector (`TileData::Loc == TileType::Vec`). + - Static valid bounds: `TileData::ValidRow <= TileData::Rows` and `TileData::ValidCol <= TileData::Cols`. + - Runtime: `src0`, `src1` and `dst` tiles should have the same `validRow/validCol`. +- **Implementation checks (A5)**: + - `TileData::DType` must be one of: `uint32_t`, `int32_t`, `uint16_t`, `int16_t`, `uint8_t`, `int8_t`, `float`, `half`. + - Tile layout must be row-major (`TileData::isRowMajor`). + - Tile location must be vector (`TileData::Loc == TileType::Vec`). + - Static valid bounds: `TileData::ValidRow <= TileData::Rows` and `TileData::ValidCol <= TileData::Cols`. + - Runtime: `src0`, `src1` and `dst` tiles should have the same `validRow/validCol`. +- **Valid region**: + - The op uses `dst.GetValidRow()` / `dst.GetValidCol()` as the iteration domain; `src0/src1` are assumed to be compatible (not validated by explicit runtime checks in this op). + +## Examples + +### Auto + +```cpp +#include + +using namespace pto; + +void example_auto() { + using TileT = Tile; + TileT src0, src1, dst; + TMAX(dst, src0, src1); +} +``` + +### Manual + +```cpp +#include + +using namespace pto; + +void example_manual() { + using TileT = Tile; + TileT src0, src1, dst; + TASSIGN(src0, 0x1000); + TASSIGN(src1, 0x2000); + TASSIGN(dst, 0x3000); + TMAX(dst, src0, src1); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.tmax %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tmax %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = tmax %src0, %src1 : !pto.tile<...> +# AS Level 2 (DPS) +pto.tmax ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TMAXS.md b/designs/outerCube/PTOISA/TMAXS.md new file mode 100644 index 00000000..268aa2ff --- /dev/null +++ b/designs/outerCube/PTOISA/TMAXS.md @@ -0,0 +1,104 @@ +# TMAXS + + +## Tile Operation Diagram + +![TMAXS tile operation](../figures/isa/TMAXS.svg) + +## Introduction + +Elementwise max of a tile and a scalar: `max(src, scalar)`. + +## Math Interpretation + +For each element `(i, j)` in the valid region: + +$$ \mathrm{dst}_{i,j} = \max(\mathrm{src}_{i,j}, \mathrm{scalar}) $$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = tmaxs %src, %scalar : !pto.tile<...>, f32 +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tmaxs %src, %scalar : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tmaxs ins(%src, %scalar : !pto.tile_buf<...>, dtype) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TMAXS(TileDataDst& dst, TileDataSrc& src, typename TileDataSrc::DType scalar, WaitEvents&... events); +``` + +## Constraints + +- **Implementation checks (A2A3)**: + - `TileData::DType` must be one of: `int32_t`, `int16_t`, `half`, `float`. + - Tile layout must be row-major (`TileData::isRowMajor`). +- **Implementation checks (A5)**: + - `TileData::DType` must be one of: `int32_t`, `uint32_t`, `float`, `int16_t`, `uint16_t`, `half`, `bfloat16_t`, `uint8_t`, `int8_t`. + - Tile layout must be row-major (`TileData::isRowMajor`). +- **Common constraints**: + - Tile location must be vector (`TileData::Loc == TileType::Vec`). + - Static valid bounds: `TileData::ValidRow <= TileData::Rows` and `TileData::ValidCol <= TileData::Cols`. + - Runtime: `dst` and `src` must have the same valid row/col. + - Scalar type must match the Tile data type. +- **Valid region**: + - The op uses `dst.GetValidRow()` / `dst.GetValidCol()` as the iteration domain. + +## Examples + +```cpp +#include + +using namespace pto; + +void example() { + using TileT = Tile; + TileT x, out; + TMAXS(out, x, 0.0f); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.tmaxs %src, %scalar : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tmaxs %src, %scalar : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = tmaxs %src, %scalar : !pto.tile<...>, f32 +# AS Level 2 (DPS) +pto.tmaxs ins(%src, %scalar : !pto.tile_buf<...>, dtype) outs(%dst : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/TMAXS_zh.md b/designs/outerCube/PTOISA/TMAXS_zh.md new file mode 100644 index 00000000..a77d73c8 --- /dev/null +++ b/designs/outerCube/PTOISA/TMAXS_zh.md @@ -0,0 +1,104 @@ +# TMAXS + +## 指令示意图 + +![TMAXS tile operation](../figures/isa/TMAXS.svg) + +## 简介 + +Tile 与标量的逐元素最大值：`max(src, scalar)`。 + +## 数学语义 + +对每个元素 `(i, j)` 在有效区域内： + +$$ \mathrm{dst}_{i,j} = \max(\mathrm{src}_{i,j}, \mathrm{scalar}) $$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS 规范](../assembly/PTO-AS_zh.md)。 + +同步形式： + +```text +%dst = tmaxs %src, %scalar : !pto.tile<...>, f32 +``` + +### AS Level 1（SSA） + +```text +%dst = pto.tmaxs %src, %scalar : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.tmaxs ins(%src, %scalar : !pto.tile_buf<...>, dtype) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`： + +```cpp +template +PTO_INST RecordEvent TMAXS(TileDataDst& dst, TileDataSrc& src, typename TileDataSrc::DType scalar, WaitEvents&... events); +``` + +## 约束 + +- **实现检查 (A2A3)**: + - `TileData::DType` 必须是以下之一：`int32_t`、`int16_t`、`half`、`float`。 + - Tile 布局必须是行主序（`TileData::isRowMajor`）。 +- **实现检查 (A5)**: + - `TileData::DType` 必须是以下之一：`int32_t`、`uint32_t`、`float`、`int16_t`、`uint16_t`、`half`、`bfloat16_t`、`uint8_t`、`int8_t`。 + - Tile 布局必须是行主序（`TileData::isRowMajor`）。 +- **通用约束**: + - Tile 位置必须是向量（`TileData::Loc == TileType::Vec`）。 + - 静态有效边界：`TileData::ValidRow <= TileData::Rows` 且 `TileData::ValidCol <= TileData::Cols`。 + - 运行时：`dst` 和 `src` 的有效行列数必须相同。 + - 标量类型必须与 Tile 数据类型一致。 +- **有效区域**: + - 该操作使用 `dst.GetValidRow()` / `dst.GetValidCol()` 作为迭代域。 + +## 示例 + +```cpp +#include + +using namespace pto; + +void example() { + using TileT = Tile; + TileT x, out; + TMAXS(out, x, 0.0f); +} +``` + +## 汇编示例（ASM） + +### 自动模式 + +```text +# 自动模式：由编译器/运行时负责资源放置与调度。 +%dst = pto.tmaxs %src, %scalar : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### 手动模式 + +```text +# 手动模式：先显式绑定资源，再发射指令。 +# 可选（当该指令包含 tile 操作数时）： +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tmaxs %src, %scalar : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### PTO 汇编形式 + +```text +%dst = tmaxs %src, %scalar : !pto.tile<...>, f32 +# AS Level 2 (DPS) +pto.tmaxs ins(%src, %scalar : !pto.tile_buf<...>, dtype) outs(%dst : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/TMAX_zh.md b/designs/outerCube/PTOISA/TMAX_zh.md new file mode 100644 index 00000000..ee11f117 --- /dev/null +++ b/designs/outerCube/PTOISA/TMAX_zh.md @@ -0,0 +1,108 @@ +# TMAX + +## 指令示意图 + +![TMAX tile operation](../figures/isa/TMAX.svg) + +## 简介 + +两个 Tile 的逐元素最大值。 + +## 数学语义 + +对每个元素 `(i, j)` 在有效区域内： + +$$ \mathrm{dst}_{i,j} = \max(\mathrm{src0}_{i,j}, \mathrm{src1}_{i,j}) $$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS Specification](../assembly/PTO-AS.md). + +同步形式： + +```text +%dst = tmax %src0, %src1 : !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tmax %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tmax ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### AS Level 1（SSA） + +```text +%dst = pto.tmax %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.tmax ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TMAX(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, WaitEvents &... events); +``` + +## 约束 + +- **实现检查 (A2A3)**: + - `TileData::DType` must be one of: `int32_t`, `int16_t`, `half`, `float`. + - Tile 布局 must be row-major (`TileData::isRowMajor`). + - Tile location must be vector (`TileData::Loc == TileType::Vec`). + - Static valid bounds: `TileData::ValidRow <= TileData::Rows` and `TileData::ValidCol <= TileData::Cols`. + - Runtime: `src0`, `src1` and `dst` tiles should have the same `validRow/validCol`. +- **实现检查 (A5)**: + - `TileData::DType` must be one of: `uint32_t`, `int32_t`, `uint16_t`, `int16_t`, `uint8_t`, `int8_t`, `float`, `half`. + - Tile 布局 must be row-major (`TileData::isRowMajor`). + - Tile location must be vector (`TileData::Loc == TileType::Vec`). + - Static valid bounds: `TileData::ValidRow <= TileData::Rows` and `TileData::ValidCol <= TileData::Cols`. + - Runtime: `src0`, `src1` and `dst` tiles should have the same `validRow/validCol`. +- **有效区域**: + - The op uses `dst.GetValidRow()` / `dst.GetValidCol()` as the iteration domain; `src0/src1` are assumed to be compatible (not validated by explicit runtime checks in this op). + +## 示例 + +### 自动（Auto） + +```cpp +#include + +using namespace pto; + +void example_auto() { + using TileT = Tile; + TileT src0, src1, dst; + TMAX(dst, src0, src1); +} +``` + +### 手动（Manual） + +```cpp +#include + +using namespace pto; + +void example_manual() { + using TileT = Tile; + TileT src0, src1, dst; + TASSIGN(src0, 0x1000); + TASSIGN(src1, 0x2000); + TASSIGN(dst, 0x3000); + TMAX(dst, src0, src1); +} +``` diff --git a/designs/outerCube/PTOISA/TMIN.md b/designs/outerCube/PTOISA/TMIN.md new file mode 100644 index 00000000..5feca244 --- /dev/null +++ b/designs/outerCube/PTOISA/TMIN.md @@ -0,0 +1,135 @@ +# TMIN + + +## Tile Operation Diagram + +![TMIN tile operation](../figures/isa/TMIN.svg) + +## Introduction + +Elementwise minimum of two tiles. + +## Math Interpretation + +For each element `(i, j)` in the valid region: + +$$ \mathrm{dst}_{i,j} = \min(\mathrm{src0}_{i,j}, \mathrm{src1}_{i,j}) $$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = tmin %src0, %src1 : !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tmin %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tmin ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### IR Level 1 (SSA) + +```text +%dst = pto.tmin %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### IR Level 2 (DPS) + +```text +pto.tmin ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TMIN(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, WaitEvents &... events); +``` + +## Constraints + +- **Implementation checks (A2A3)**: + - `TileData::DType` must be one of: `int32_t`, `int16_t`, `half`, `float`. + - Tile layout must be row-major (`TileData::isRowMajor`). + - Tile location must be vector (`TileData::Loc == TileType::Vec`). + - Static valid bounds: `TileData::ValidRow <= TileData::Rows` and `TileData::ValidCol <= TileData::Cols`. + - Runtime: `src0`, `src1` and `dst` tiles should have the same `validRow/validCol`. +- **Implementation checks (A5)**: + - `TileData::DType` must be one of: `uint32_t`, `int32_t`, `uint16_t`, `int16_t`, `uint8_t`, `int8_t`, `float`, `half`. + - Tile layout must be row-major (`TileData::isRowMajor`). + - Tile location must be vector (`TileData::Loc == TileType::Vec`). + - Static valid bounds: `TileData::ValidRow <= TileData::Rows` and `TileData::ValidCol <= TileData::Cols`. + - Runtime: `src0`, `src1` and `dst` tiles should have the same `validRow/validCol`. +- **Valid region**: + - The op uses `dst.GetValidRow()` / `dst.GetValidCol()` as the iteration domain; `src0/src1` are assumed to be compatible (not validated by explicit runtime checks in this op). + +## Examples + +### Auto + +```cpp +#include + +using namespace pto; + +void example_auto() { + using TileT = Tile; + TileT src0, src1, dst; + TMIN(dst, src0, src1); +} +``` + +### Manual + +```cpp +#include + +using namespace pto; + +void example_manual() { + using TileT = Tile; + TileT src0, src1, dst; + TASSIGN(src0, 0x1000); + TASSIGN(src1, 0x2000); + TASSIGN(dst, 0x3000); + TMIN(dst, src0, src1); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.tmin %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tmin %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = tmin %src0, %src1 : !pto.tile<...> +# AS Level 2 (DPS) +pto.tmin ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TMINS.md b/designs/outerCube/PTOISA/TMINS.md new file mode 100644 index 00000000..0ded1cc5 --- /dev/null +++ b/designs/outerCube/PTOISA/TMINS.md @@ -0,0 +1,121 @@ +# TMINS + + +## Tile Operation Diagram + +![TMINS tile operation](../figures/isa/TMINS.svg) + +## Introduction + +Elementwise minimum of a tile and a scalar. + +## Math Interpretation + +For each element `(i, j)` in the valid region: + +$$ \mathrm{dst}_{i,j} = \min(\mathrm{src}_{i,j}, \mathrm{scalar}) $$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = tmins %src, %scalar : !pto.tile<...>, f32 +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tmins %src, %scalar : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tmins ins(%src, %scalar : !pto.tile_buf<...>, dtype) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TMINS(TileDataDst &dst, TileDataSrc &src, typename TileDataSrc::DType scalar, WaitEvents &... events); +``` + +## Constraints + +- **Implementation checks (A2A3)**: + - `TileData::DType` must be one of: `int32_t`, `int`, `int16_t`, `half`, `float16_t`, `float`, `float32_t`. + - Runtime: `src.GetValidRow() == dst.GetValidRow()` and `src.GetValidCol() == dst.GetValidCol()`. +- **Implementation checks (A5)**: + - `TileData::DType` must be one of: `uint8_t`, `int8_t`, `uint16_t`, `int16_t`, `uint32_t`, `int32_t`, `half`, `float`, `bfloat16_t`. + - Runtime: `src.GetValidCol() == dst.GetValidCol()`. +- **Common constraints**: + - `dst` and `src` must use the same element type. + - Scalar type must match the tile data type. + - Tile location must be vector (`TileData::Loc == TileType::Vec`). +- **Valid region**: + - The op uses `dst.GetValidRow()` / `dst.GetValidCol()` as the iteration domain. + +## Examples + +### Auto + +```cpp +#include + +using namespace pto; + +void example_auto() { + using TileT = Tile; + TileT src, dst; + TMINS(dst, src, 0.0f); +} +``` + +### Manual + +```cpp +#include + +using namespace pto; + +void example_manual() { + using TileT = Tile; + TileT src, dst; + TASSIGN(src, 0x1000); + TASSIGN(dst, 0x2000); + TMINS(dst, src, 0.0f); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.tmins %src, %scalar : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tmins %src, %scalar : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = tmins %src, %scalar : !pto.tile<...>, f32 +# AS Level 2 (DPS) +pto.tmins ins(%src, %scalar : !pto.tile_buf<...>, dtype) outs(%dst : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/TMINS_zh.md b/designs/outerCube/PTOISA/TMINS_zh.md new file mode 100644 index 00000000..c53c5ddb --- /dev/null +++ b/designs/outerCube/PTOISA/TMINS_zh.md @@ -0,0 +1,121 @@ +# TMINS + +## 指令示意图 + +![TMINS tile operation](../figures/isa/TMINS.svg) + +## 简介 + +Tile 与标量的逐元素最小值。 + +## 数学语义 + +对每个元素 `(i, j)` 在有效区域内： + +$$ \mathrm{dst}_{i,j} = \min(\mathrm{src}_{i,j}, \mathrm{scalar}) $$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS 规范](../assembly/PTO-AS_zh.md)。 + +同步形式： + +```text +%dst = tmins %src, %scalar : !pto.tile<...>, f32 +``` + +### AS Level 1（SSA） + +```text +%dst = pto.tmins %src, %scalar : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.tmins ins(%src, %scalar : !pto.tile_buf<...>, dtype) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`： + +```cpp +template +PTO_INST RecordEvent TMINS(TileDataDst &dst, TileDataSrc &src, typename TileDataSrc::DType scalar, WaitEvents &... events); +``` + +## 约束 + +- **实现检查 (A2A3)**: + - `TileData::DType` 必须是以下之一：`int32_t`、`int`、`int16_t`、`half`、`float16_t`、`float`、`float32_t`。 + - 运行时：`src.GetValidRow() == dst.GetValidRow()` 且 `src.GetValidCol() == dst.GetValidCol()`。 +- **实现检查 (A5)**: + - `TileData::DType` 必须是以下之一：`uint8_t`、`int8_t`、`uint16_t`、`int16_t`、`uint32_t`、`int32_t`、`half`、`float`、`bfloat16_t`。 + - 运行时：`src.GetValidCol() == dst.GetValidCol()`。 +- **通用约束**: + - `dst` 和 `src` 必须使用相同的元素类型。 + - 标量类型必须与 Tile 数据类型一致。 + - Tile 位置必须是向量（`TileData::Loc == TileType::Vec`）。 +- **有效区域**: + - 该操作使用 `dst.GetValidRow()` / `dst.GetValidCol()` 作为迭代域。 + +## 示例 + +### 自动（Auto） + +```cpp +#include + +using namespace pto; + +void example_auto() { + using TileT = Tile; + TileT src, dst; + TMINS(dst, src, 0.0f); +} +``` + +### 手动（Manual） + +```cpp +#include + +using namespace pto; + +void example_manual() { + using TileT = Tile; + TileT src, dst; + TASSIGN(src, 0x1000); + TASSIGN(dst, 0x2000); + TMINS(dst, src, 0.0f); +} +``` + +## 汇编示例（ASM） + +### 自动模式 + +```text +# 自动模式：由编译器/运行时负责资源放置与调度。 +%dst = pto.tmins %src, %scalar : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### 手动模式 + +```text +# 手动模式：先显式绑定资源，再发射指令。 +# 可选（当该指令包含 tile 操作数时）： +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tmins %src, %scalar : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### PTO 汇编形式 + +```text +%dst = tmins %src, %scalar : !pto.tile<...>, f32 +# AS Level 2 (DPS) +pto.tmins ins(%src, %scalar : !pto.tile_buf<...>, dtype) outs(%dst : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/TMIN_zh.md b/designs/outerCube/PTOISA/TMIN_zh.md new file mode 100644 index 00000000..33ecee2e --- /dev/null +++ b/designs/outerCube/PTOISA/TMIN_zh.md @@ -0,0 +1,108 @@ +# TMIN + +## 指令示意图 + +![TMIN tile operation](../figures/isa/TMIN.svg) + +## 简介 + +两个 Tile 的逐元素最小值。 + +## 数学语义 + +对每个元素 `(i, j)` 在有效区域内： + +$$ \mathrm{dst}_{i,j} = \min(\mathrm{src0}_{i,j}, \mathrm{src1}_{i,j}) $$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS Specification](../assembly/PTO-AS.md). + +同步形式： + +```text +%dst = tmin %src0, %src1 : !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tmin %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tmin ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### AS Level 1（SSA） + +```text +%dst = pto.tmin %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.tmin ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TMIN(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, WaitEvents &... events); +``` + +## 约束 + +- **实现检查 (A2A3)**: + - `TileData::DType` must be one of: `int32_t`, `int16_t`, `half`, `float`. + - Tile 布局 must be row-major (`TileData::isRowMajor`). + - Tile location must be vector (`TileData::Loc == TileType::Vec`). + - Static valid bounds: `TileData::ValidRow <= TileData::Rows` and `TileData::ValidCol <= TileData::Cols`. + - Runtime: `src0`, `src1` and `dst` tiles should have the same `validRow/validCol`. +- **实现检查 (A5)**: + - `TileData::DType` must be one of: `uint32_t`, `int32_t`, `uint16_t`, `int16_t`, `uint8_t`, `int8_t`, `float`, `half`. + - Tile 布局 must be row-major (`TileData::isRowMajor`). + - Tile location must be vector (`TileData::Loc == TileType::Vec`). + - Static valid bounds: `TileData::ValidRow <= TileData::Rows` and `TileData::ValidCol <= TileData::Cols`. + - Runtime: `src0`, `src1` and `dst` tiles should have the same `validRow/validCol`. +- **有效区域**: + - The op uses `dst.GetValidRow()` / `dst.GetValidCol()` as the iteration domain; `src0/src1` are assumed to be compatible (not validated by explicit runtime checks in this op). + +## 示例 + +### 自动（Auto） + +```cpp +#include + +using namespace pto; + +void example_auto() { + using TileT = Tile; + TileT src0, src1, dst; + TMIN(dst, src0, src1); +} +``` + +### 手动（Manual） + +```cpp +#include + +using namespace pto; + +void example_manual() { + using TileT = Tile; + TileT src0, src1, dst; + TASSIGN(src0, 0x1000); + TASSIGN(src1, 0x2000); + TASSIGN(dst, 0x3000); + TMIN(dst, src0, src1); +} +``` diff --git a/designs/outerCube/PTOISA/TMOV.md b/designs/outerCube/PTOISA/TMOV.md new file mode 100644 index 00000000..6fa16879 --- /dev/null +++ b/designs/outerCube/PTOISA/TMOV.md @@ -0,0 +1,161 @@ +# TMOV + + +## Tile Operation Diagram + +![TMOV tile operation](../figures/isa/TMOV.svg) + +## Introduction + +Move/copy between tiles, optionally applying implementation-defined conversion modes selected by template parameters and overloads. + +`TMOV` is used for: + +- Vec -> Vec moves +- Mat -> Left/Right/Bias/Scaling/Scale(Microscaling) moves (target-dependent) +- Acc -> Vec moves (target-dependent) + +## Math Interpretation + +Conceptually copies or transforms elements from `src` into `dst` over the valid region. Exact transformation depends on the selected mode and target. + +For the pure copy case: + +$$ \mathrm{dst}_{i,j} = \mathrm{src}_{i,j} $$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +The PTO AS design recommends splitting `TMOV` into a family of ops: + +```text +%left = tmov.m2l %mat : !pto.tile<...> -> !pto.tile<...> +%right = tmov.m2r %mat : !pto.tile<...> -> !pto.tile<...> +%bias = tmov.m2b %mat : !pto.tile<...> -> !pto.tile<...> +%scale = tmov.m2s %mat : !pto.tile<...> -> !pto.tile<...> +%vec = tmov.a2v %acc : !pto.tile<...> -> !pto.tile<...> +%v1 = tmov.v2v %v0 : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tmov.s2d %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tmov ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp` and `include/pto/common/constants.hpp`: + +```cpp +template +PTO_INST RecordEvent TMOV(DstTileData &dst, SrcTileData &src, WaitEvents &... events); + +template +PTO_INST RecordEvent TMOV(DstTileData &dst, SrcTileData &src, WaitEvents &... events); + +template +PTO_INST RecordEvent TMOV(DstTileData &dst, SrcTileData &src, WaitEvents &... events); + +template +PTO_INST RecordEvent TMOV(DstTileData &dst, SrcTileData &src, FpTileData &fp, WaitEvents &... events); + +template +PTO_INST RecordEvent TMOV(DstTileData &dst, SrcTileData &src, uint64_t preQuantScalar, WaitEvents &... events); + +template +PTO_INST RecordEvent TMOV(DstTileData &dst, SrcTileData &src, uint64_t preQuantScalar, WaitEvents &... events); +``` + +## Constraints + +- **Implementation checks (A2A3)**: + - Shape rules: + - Shapes must match: `SrcTileData::Rows == DstTileData::Rows` and `SrcTileData::Cols == DstTileData::Cols`. + - Supported location pairs (compile-time checked): + - `Mat -> Left/Right/Bias/Scaling` + - `Vec -> Vec` + - `Acc -> Mat` + - Additional checks by path: + - `Acc -> Mat`: additional fractal and dtype constraints are enforced (for example, `Acc` uses an NZ-like fractal, `Mat` uses a 512B fractal, and only specific dtype conversions are allowed). +- **Implementation checks (A5)**: + - Shape rules: + - For `Mat -> Left/Right/Bias/Scaling/Scale`, shapes must match. + - For `Vec -> Vec` and `Vec -> Mat`, the effective copy region may be determined by the valid rows/cols of source and destination. + - Supported location pairs include (target-dependent): + - `Mat -> Left/Right/Bias/Scaling/Scale` + - `Vec -> Vec/Mat` + - `Acc -> Vec/Mat` + - `Acc -> Vec` supports additional `AccToVecMode` forms; some forms also take `FpTileData` or `preQuantScalar`. + +## Examples + +### Auto + +```cpp +#include + +using namespace pto; + +void example_auto() { + using TileT = Tile; + TileT src, dst; + TMOV(dst, src); +} +``` + +### Manual + +```cpp +#include + +using namespace pto; + +void example_manual() { + using SrcT = Tile; + using DstT = TileLeft; + SrcT mat; + DstT left; + TASSIGN(mat, 0x1000); + TASSIGN(left, 0x2000); + TMOV(left, mat); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.tmov.s2d %src : !pto.tile<...> -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tmov.s2d %src : !pto.tile<...> -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = pto.tmov.s2d %src : !pto.tile<...> -> !pto.tile<...> +# AS Level 2 (DPS) +pto.tmov ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/TMOV_FP.md b/designs/outerCube/PTOISA/TMOV_FP.md new file mode 100644 index 00000000..620431ff --- /dev/null +++ b/designs/outerCube/PTOISA/TMOV_FP.md @@ -0,0 +1,141 @@ +# TMOV_FP + + +## Tile Operation Diagram + +![TMOV_FP tile operation](../figures/isa/TMOV_FP.svg) + +## Introduction + +Move/convert from an accumulator tile into a destination tile, using a scaling (`fp`) tile for vector quantization parameters. + +`TMOV_FP` is a named wrapper around the `TMOV_IMPL(..., fp)` path and is part of the `TMOV` family (see `docs/isa/TMOV.md`). + +## Math Interpretation + +Conceptually converts each element using an implementation-defined quantization/dequantization configuration derived from `fp`: + +$$ \mathrm{dst}_{i,j} = \mathrm{Convert}\!\left(\mathrm{src}_{i,j};\ \mathrm{fp}\right) $$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = tmov.fp %src, %fp : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tmov.fp %src, %fp : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tmov.fp ins(%src, %fp : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### IR Level 1 (SSA) + +```text +%dst = pto.tmov.fp %src, %fp : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### IR Level 2 (DPS) + +```text +pto.tmov.fp ins(%src, %fp : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp` and `include/pto/common/constants.hpp`: + +```cpp +template +PTO_INST RecordEvent TMOV_FP(DstTileData &dst, SrcTileData &src, FpTileData &fp, WaitEvents &... events); +``` + +## Constraints + +- **Implementation checks (A2A3)**: + - The fp path is only supported for accumulator conversion and is validated by internal compile-time checks in `TMOV_IMPL(dst, src, fp)`. + - `FpTileData::Loc` must be `TileType::Scaling` (`static_assert`). +- **Implementation checks (A5)**: + - Validated by `CheckTMovAccValid(...)` and related compile-time checks in `TMOV_IMPL(dst, src, fp)`. + - `FpTileData::Loc` must be `TileType::Scaling` (`static_assert`). + - Destination location is target-dependent (`Vec` or `Mat` are supported in the fp path). + +## Examples + +### Auto + +```cpp +#include + +using namespace pto; + +void example_auto() { + using AccT = TileAcc; + using DstT = Tile; + using FpT = Tile; + + AccT acc; + DstT dst; + FpT fp; + TMOV_FP(dst, acc, fp); +} +``` + +### Manual + +```cpp +#include + +using namespace pto; + +void example_manual() { + using AccT = TileAcc; + using DstT = Tile; + using FpT = Tile; + + AccT acc; + DstT dst; + FpT fp; + TASSIGN(acc, 0x1000); + TASSIGN(dst, 0x2000); + TASSIGN(fp, 0x3000); + TMOV_FP(dst, acc, fp); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.tmov.fp %src, %fp : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tmov.fp %src, %fp : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = tmov.fp %src, %fp : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +# AS Level 2 (DPS) +pto.tmov.fp ins(%src, %fp : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TMOV_FP_zh.md b/designs/outerCube/PTOISA/TMOV_FP_zh.md new file mode 100644 index 00000000..28ed5751 --- /dev/null +++ b/designs/outerCube/PTOISA/TMOV_FP_zh.md @@ -0,0 +1,112 @@ +# TMOV_FP + +## 指令示意图 + +![TMOV_FP tile operation](../figures/isa/TMOV_FP.svg) + +## 简介 + +使用缩放 (`fp`) Tile 作为向量量化参数，将累加器 Tile 移动/转换到目标 Tile。 + +## 数学语义 + +Conceptually converts each element using an implementation-defined quantization/dequantization configuration derived from `fp`: + +$$ \mathrm{dst}_{i,j} = \mathrm{Convert}\!\left(\mathrm{src}_{i,j};\ \mathrm{fp}\right) $$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS Specification](../assembly/PTO-AS.md). + +同步形式： + +```text +%dst = tmov.fp %src, %fp : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tmov.fp %src, %fp : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tmov.fp ins(%src, %fp : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### AS Level 1（SSA） + +```text +%dst = pto.tmov.fp %src, %fp : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.tmov.fp ins(%src, %fp : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp` and `include/pto/common/constants.hpp`: + +```cpp +template +PTO_INST RecordEvent TMOV_FP(DstTileData &dst, SrcTileData &src, FpTileData &fp, WaitEvents &... events); +``` + +## 约束 + +- **实现检查 (A2A3)**: + - The fp path is only supported for accumulator conversion and is validated by internal compile-time checks in `TMOV_IMPL(dst, src, fp)`. + - `FpTileData::Loc` must be `TileType::Scaling` (`static_assert`). +- **实现检查 (A5)**: + - Validated by `CheckTMovAccValid(...)` and related compile-time checks in `TMOV_IMPL(dst, src, fp)`. + - `FpTileData::Loc` must be `TileType::Scaling` (`static_assert`). + - Destination location is target-dependent (`Vec` or `Mat` are supported in the fp path). + +## 示例 + +### 自动（Auto） + +```cpp +#include + +using namespace pto; + +void example_auto() { + using AccT = TileAcc; + using DstT = Tile; + using FpT = Tile; + + AccT acc; + DstT dst; + FpT fp; + TMOV_FP(dst, acc, fp); +} +``` + +### 手动（Manual） + +```cpp +#include + +using namespace pto; + +void example_manual() { + using AccT = TileAcc; + using DstT = Tile; + using FpT = Tile; + + AccT acc; + DstT dst; + FpT fp; + TASSIGN(acc, 0x1000); + TASSIGN(dst, 0x2000); + TASSIGN(fp, 0x3000); + TMOV_FP(dst, acc, fp); +} +``` diff --git a/designs/outerCube/PTOISA/TMOV_zh.md b/designs/outerCube/PTOISA/TMOV_zh.md new file mode 100644 index 00000000..92f4edd2 --- /dev/null +++ b/designs/outerCube/PTOISA/TMOV_zh.md @@ -0,0 +1,161 @@ +# TMOV + +## 指令示意图 + +![TMOV tile operation](../figures/isa/TMOV.svg) + +## 简介 + +在 Tile 之间移动/复制，可选通过模板参数和重载选择实现定义的转换模式。 + +`TMOV` 用于： + +- Vec -> Vec 移动 +- Mat -> Left/Right/Bias/Scaling/Scale（微缩放）移动（取决于目标） +- Acc -> Vec 移动（取决于目标） + +## 数学语义 + +概念上在有效区域上将元素从 `src` 复制或转换到 `dst`。确切的转换取决于所选模式和目标。 + +对于纯复制情况： + +$$ \mathrm{dst}_{i,j} = \mathrm{src}_{i,j} $$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS 规范](../assembly/PTO-AS_zh.md)。 + +PTO AS 设计建议将 `TMOV` 拆分为一系列操作： + +```text +%left = tmov.m2l %mat : !pto.tile<...> -> !pto.tile<...> +%right = tmov.m2r %mat : !pto.tile<...> -> !pto.tile<...> +%bias = tmov.m2b %mat : !pto.tile<...> -> !pto.tile<...> +%scale = tmov.m2s %mat : !pto.tile<...> -> !pto.tile<...> +%vec = tmov.a2v %acc : !pto.tile<...> -> !pto.tile<...> +%v1 = tmov.v2v %v0 : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 1（SSA） + +```text +%dst = pto.tmov.s2d %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.tmov ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp` 和 `include/pto/common/constants.hpp`： + +```cpp +template +PTO_INST RecordEvent TMOV(DstTileData &dst, SrcTileData &src, WaitEvents &... events); + +template +PTO_INST RecordEvent TMOV(DstTileData &dst, SrcTileData &src, WaitEvents &... events); + +template +PTO_INST RecordEvent TMOV(DstTileData &dst, SrcTileData &src, WaitEvents &... events); + +template +PTO_INST RecordEvent TMOV(DstTileData &dst, SrcTileData &src, FpTileData &fp, WaitEvents &... events); + +template +PTO_INST RecordEvent TMOV(DstTileData &dst, SrcTileData &src, uint64_t preQuantScalar, WaitEvents &... events); + +template +PTO_INST RecordEvent TMOV(DstTileData &dst, SrcTileData &src, uint64_t preQuantScalar, WaitEvents &... events); +``` + +## 约束 + +- **实现检查 (A2A3)**: + - 形状规则： + - 形状必须匹配：`SrcTileData::Rows == DstTileData::Rows` 且 `SrcTileData::Cols == DstTileData::Cols`。 + - 支持的位置对（编译时检查）： + - `Mat -> Left/Right/Bias/Scaling` + - `Vec -> Vec` + - `Acc -> Mat` + - 按路径附加检查如下： + - `Acc -> Mat`：会额外检查分形与数据类型约束（例如 `Acc` 使用类 NZ 分形，`Mat` 使用 512B 分形，且仅允许特定的数据类型转换）。 +- **实现检查 (A5)**: + - 形状规则： + - 对于 `Mat -> Left/Right/Bias/Scaling/Scale`，形状必须匹配。 + - 对于 `Vec -> Vec` 和 `Vec -> Mat`，实际复制区域可能由源和目的的有效行/列共同决定。 + - 支持的位置对包括（取决于目标）： + - `Mat -> Left/Right/Bias/Scaling/Scale` + - `Vec -> Vec/Mat` + - `Acc -> Vec/Mat` + - `Acc -> Vec` 还支持额外的 `AccToVecMode` 形式；其中部分形式还会结合 `FpTileData` 或 `preQuantScalar` 使用。 + +## 示例 + +### 自动（Auto） + +```cpp +#include + +using namespace pto; + +void example_auto() { + using TileT = Tile; + TileT src, dst; + TMOV(dst, src); +} +``` + +### 手动（Manual） + +```cpp +#include + +using namespace pto; + +void example_manual() { + using SrcT = Tile; + using DstT = TileLeft; + SrcT mat; + DstT left; + TASSIGN(mat, 0x1000); + TASSIGN(left, 0x2000); + TMOV(left, mat); +} +``` + +## 汇编示例（ASM） + +### 自动模式 + +```text +# 自动模式：由编译器/运行时负责资源放置与调度。 +%dst = pto.tmov.s2d %src : !pto.tile<...> -> !pto.tile<...> +``` + +### 手动模式 + +```text +# 手动模式：先显式绑定资源，再发射指令。 +# 可选（当该指令包含 tile 操作数时）： +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tmov.s2d %src : !pto.tile<...> -> !pto.tile<...> +``` + +### PTO 汇编形式 + +```text +%dst = pto.tmov.s2d %src : !pto.tile<...> -> !pto.tile<...> +# AS Level 2 (DPS) +pto.tmov ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/TMRGSORT.md b/designs/outerCube/PTOISA/TMRGSORT.md new file mode 100644 index 00000000..f76f1889 --- /dev/null +++ b/designs/outerCube/PTOISA/TMRGSORT.md @@ -0,0 +1,155 @@ +# TMRGSORT + + +## Tile Operation Diagram + +![TMRGSORT tile operation](../figures/isa/TMRGSORT.svg) + +## Introduction + +Merge sort for multiple sorted lists (implementation-defined element format and layout). + +## Math Interpretation + +Merges sorted input lists into `dst`. Ordering, element format (e.g., value/index pairs), and the meaning of executed counts depend on the implementation. + +$$ \mathrm{dst} = \mathrm{merge}(\mathrm{src}_0, \mathrm{src}_1, \ldots) $$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form (conceptual): + +```text +%dst, %executed = tmrgsort %src0, %src1 {exhausted = false} + : !pto.tile<...>, !pto.tile<...> -> (!pto.tile<...>, vector<4xi16>) +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tmrgsort %src, %blockLen : (!pto.tile<...>, dtype) -> !pto.tile<...> +%dst, %executed = pto.tmrgsort %src0, %src1, %src2, %src3 {exhausted = false} + : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> (!pto.tile<...>, vector<4xi16>) +``` + +### AS Level 2 (DPS) + +```text +pto.tmrgsort ins(%src, %blockLen : !pto.tile_buf<...>, dtype) outs(%dst : !pto.tile_buf<...>) +pto.tmrgsort ins(%src0, %src1, %src2, %src3 {exhausted = false} : !pto.tile_buf<...>, !pto.tile_buf<...>, !pto.tile_buf<...>, !pto.tile_buf<...>) +outs(%dst, %executed : !pto.tile_buf<...>, vector<4xi16>) +``` + +### IR Level 1 (SSA) + +```text +%dst = pto.tmrgsort %src, %blockLen : (!pto.tile<...>, dtype) -> !pto.tile<...> +%dst, %executed = pto.tmrgsort %src0, %src1, %src2, %src3 {exhausted = false} + : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> (!pto.tile<...>, vector<4xi16>) +``` + +### IR Level 2 (DPS) + +```text +pto.tmrgsort ins(%src, %blockLen : !pto.tile_buf<...>, dtype) outs(%dst : !pto.tile_buf<...>) +pto.tmrgsort ins(%src0, %src1, %src2, %src3 {exhausted = false} : !pto.tile_buf<...>, !pto.tile_buf<...>, !pto.tile_buf<...>, !pto.tile_buf<...>) +outs(%dst, %executed : !pto.tile_buf<...>, vector<4xi16>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TMRGSORT(DstTileData &dst, MrgSortExecutedNumList &executedNumList, TmpTileData &tmp, Src0TileData &src0, Src1TileData &src1, Src2TileData &src2, Src3TileData &src3, WaitEvents &... events); + +template +PTO_INST RecordEvent TMRGSORT(DstTileData &dst, MrgSortExecutedNumList &executedNumList, TmpTileData &tmp, Src0TileData &src0, Src1TileData &src1, Src2TileData &src2, WaitEvents &... events); + +template +PTO_INST RecordEvent TMRGSORT(DstTileData &dst, MrgSortExecutedNumList &executedNumList, TmpTileData &tmp, Src0TileData &src0, Src1TileData &src1, WaitEvents &... events); + +template +PTO_INST RecordEvent TMRGSORT(DstTileData &dst, SrcTileData &src, uint32_t blockLen, WaitEvents &... events); +``` + +## Constraints + +- **Implementation checks (A2A3/A5)**: + - Element type must be `half` or `float` and must match across `dst/tmp/src*` tiles. + - All tiles must be `TileType::Vec`, row-major, and have `Rows == 1` (list stored in a single row). + - UB memory usage is checked (compile-time and runtime) against target limits (single `Cols` across inputs plus `tmp`/`dst`). +- **Single-list variant (`TMRGSORT(dst, src, blockLen)`)**: + - `blockLen` must be a multiple of 64 (as checked by the implementation). + - `src.GetValidCol()` must be an integer multiple of `blockLen * 4`. + - `repeatTimes = src.GetValidCol() / (blockLen * 4)` must be in `[1, 255]`. +- **Multi-list variants**: + - `tmp` is required and `executedNumList` is written by the implementation; supported list counts and exact semantics are target-defined. + +## Examples + +### Auto + +```cpp +#include + +using namespace pto; + +void example_auto() { + using SrcT = Tile; + using DstT = Tile; + SrcT src; + DstT dst; + TMRGSORT(dst, src, /*blockLen=*/64); +} +``` + +### Manual + +```cpp +#include + +using namespace pto; + +void example_manual() { + using SrcT = Tile; + using DstT = Tile; + SrcT src; + DstT dst; + TASSIGN(src, 0x1000); + TASSIGN(dst, 0x2000); + TMRGSORT(dst, src, /*blockLen=*/64); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.tmrgsort %src, %blockLen : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tmrgsort %src, %blockLen : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = pto.tmrgsort %src, %blockLen : (!pto.tile<...>, dtype) -> !pto.tile<...> +# AS Level 2 (DPS) +pto.tmrgsort ins(%src, %blockLen : !pto.tile_buf<...>, dtype) outs(%dst : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TMRGSORT_zh.md b/designs/outerCube/PTOISA/TMRGSORT_zh.md new file mode 100644 index 00000000..1b3dcc36 --- /dev/null +++ b/designs/outerCube/PTOISA/TMRGSORT_zh.md @@ -0,0 +1,128 @@ +# TMRGSORT + +## 指令示意图 + +![TMRGSORT tile operation](../figures/isa/TMRGSORT.svg) + +## 简介 + +用于多个已排序列表的归并排序（实现定义的元素格式和布局）。 + +## 数学语义 + +Merges sorted input lists into `dst`. Ordering, element format (e.g., value/index pairs), and the meaning of executed counts depend on the implementation. + +$$ \mathrm{dst} = \mathrm{merge}(\mathrm{src}_0, \mathrm{src}_1, \ldots) $$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form (conceptual): + +```text +%dst, %executed = tmrgsort %src0, %src1 {exhausted = false} + : !pto.tile<...>, !pto.tile<...> -> (!pto.tile<...>, vector<4xi16>) +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tmrgsort %src, %blockLen : (!pto.tile<...>, dtype) -> !pto.tile<...> +%dst, %executed = pto.tmrgsort %src0, %src1, %src2, %src3 {exhausted = false} + : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> (!pto.tile<...>, vector<4xi16>) +``` + +### AS Level 2 (DPS) + +```text +pto.tmrgsort ins(%src, %blockLen : !pto.tile_buf<...>, dtype) outs(%dst : !pto.tile_buf<...>) +pto.tmrgsort ins(%src0, %src1, %src2, %src3 {exhausted = false} : !pto.tile_buf<...>, !pto.tile_buf<...>, !pto.tile_buf<...>, !pto.tile_buf<...>) +outs(%dst, %executed : !pto.tile_buf<...>, vector<4xi16>) +``` + +### AS Level 1（SSA） + +```text +%dst = pto.tmrgsort %src, %blockLen : (!pto.tile<...>, dtype) -> !pto.tile<...> +%dst, %executed = pto.tmrgsort %src0, %src1, %src2, %src3 {exhausted = false} + : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> (!pto.tile<...>, vector<4xi16>) +``` + +### AS Level 2（DPS） + +```text +pto.tmrgsort ins(%src, %blockLen : !pto.tile_buf<...>, dtype) outs(%dst : !pto.tile_buf<...>) +pto.tmrgsort ins(%src0, %src1, %src2, %src3 {exhausted = false} : !pto.tile_buf<...>, !pto.tile_buf<...>, !pto.tile_buf<...>, !pto.tile_buf<...>) +outs(%dst, %executed : !pto.tile_buf<...>, vector<4xi16>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TMRGSORT(DstTileData &dst, MrgSortExecutedNumList &executedNumList, TmpTileData &tmp, Src0TileData &src0, Src1TileData &src1, Src2TileData &src2, Src3TileData &src3, WaitEvents &... events); + +template +PTO_INST RecordEvent TMRGSORT(DstTileData &dst, MrgSortExecutedNumList &executedNumList, TmpTileData &tmp, Src0TileData &src0, Src1TileData &src1, Src2TileData &src2, WaitEvents &... events); + +template +PTO_INST RecordEvent TMRGSORT(DstTileData &dst, MrgSortExecutedNumList &executedNumList, TmpTileData &tmp, Src0TileData &src0, Src1TileData &src1, WaitEvents &... events); + +template +PTO_INST RecordEvent TMRGSORT(DstTileData &dst, SrcTileData &src, uint32_t blockLen, WaitEvents &... events); +``` + +## 约束 + +- **实现检查 (A2A3/A5)**: + - Element type must be `half` or `float` and must match across `dst/tmp/src*` tiles. + - All tiles must be `TileType::Vec`, row-major, and have `Rows == 1` (list stored in a single row). + - UB memory usage is checked (compile-time and runtime) against target limits (single `Cols` across inputs plus `tmp`/`dst`). +- **Single-list variant (`TMRGSORT(dst, src, blockLen)`)**: + - `blockLen` must be a multiple of 64 (as checked by the implementation). + - `src.GetValidCol()` must be an integer multiple of `blockLen * 4`. + - `repeatTimes = src.GetValidCol() / (blockLen * 4)` must be in `[1, 255]`. +- **Multi-list variants**: + - `tmp` is required and `executedNumList` is written by the implementation; supported list counts and exact semantics are target-defined. + +## 示例 + +### 自动（Auto） + +```cpp +#include + +using namespace pto; + +void example_auto() { + using SrcT = Tile; + using DstT = Tile; + SrcT src; + DstT dst; + TMRGSORT(dst, src, /*blockLen=*/64); +} +``` + +### 手动（Manual） + +```cpp +#include + +using namespace pto; + +void example_manual() { + using SrcT = Tile; + using DstT = Tile; + SrcT src; + DstT dst; + TASSIGN(src, 0x1000); + TASSIGN(dst, 0x2000); + TMRGSORT(dst, src, /*blockLen=*/64); +} +``` diff --git a/designs/outerCube/PTOISA/TMUL.md b/designs/outerCube/PTOISA/TMUL.md new file mode 100644 index 00000000..b4cfc637 --- /dev/null +++ b/designs/outerCube/PTOISA/TMUL.md @@ -0,0 +1,135 @@ +# TMUL + + +## Tile Operation Diagram + +![TMUL tile operation](../figures/isa/TMUL.svg) + +## Introduction + +Elementwise multiply of two tiles. + +## Math Interpretation + +For each element `(i, j)` in the valid region: + +$$ \mathrm{dst}_{i,j} = \mathrm{src0}_{i,j} \cdot \mathrm{src1}_{i,j} $$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = tmul %src0, %src1 : !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tmul %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tmul ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### IR Level 1 (SSA) + +```text +%dst = pto.tmul %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### IR Level 2 (DPS) + +```text +pto.tmul ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TMUL(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, WaitEvents &... events); +``` + +## Constraints + +- **Implementation checks (A2A3)**: + - `TileData::DType` must be one of: `int32_t`, `int16_t`, `half`, `float`. + - Tile location must be vector (`TileData::Loc == TileType::Vec`). + - Static valid bounds: `TileData::ValidRow <= TileData::Rows` and `TileData::ValidCol <= TileData::Cols`. + - Tile layout must be row-major (`TileData::isRowMajor`). + - Runtime: `src0`, `src1` and `dst` tiles should have the same `validRow/validCol`. +- **Implementation checks (A5)**: + - `TileData::DType` must be one of: `int32_t`, `uint32_t`, `float`, `int16_t`, `uint16_t`, `half`. + - Tile location must be vector (`TileData::Loc == TileType::Vec`). + - Static valid bounds: `TileData::ValidRow <= TileData::Rows` and `TileData::ValidCol <= TileData::Cols`. + - Tile layout must be row-major (`TileData::isRowMajor`). + - Runtime: `src0`, `src1` and `dst` tiles should have the same `validRow/validCol`. +- **Valid region**: + - The op uses `dst.GetValidRow()` / `dst.GetValidCol()` as the iteration domain; . + +## Examples + +### Auto + +```cpp +#include + +using namespace pto; + +void example_auto() { + using TileT = Tile; + TileT src0, src1, dst; + TMUL(dst, src0, src1); +} +``` + +### Manual + +```cpp +#include + +using namespace pto; + +void example_manual() { + using TileT = Tile; + TileT src0, src1, dst; + TASSIGN(src0, 0x1000); + TASSIGN(src1, 0x2000); + TASSIGN(dst, 0x3000); + TMUL(dst, src0, src1); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.tmul %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tmul %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = tmul %src0, %src1 : !pto.tile<...> +# AS Level 2 (DPS) +pto.tmul ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TMULS.md b/designs/outerCube/PTOISA/TMULS.md new file mode 100644 index 00000000..c163afb3 --- /dev/null +++ b/designs/outerCube/PTOISA/TMULS.md @@ -0,0 +1,134 @@ +# TMULS + + +## Tile Operation Diagram + +![TMULS tile operation](../figures/isa/TMULS.svg) + +## Introduction + +Elementwise multiply a tile by a scalar. + +## Math Interpretation + +For each element `(i, j)` in the valid region: + +$$ \mathrm{dst}_{i,j} = \mathrm{src}_{i,j} \cdot \mathrm{scalar} $$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = tmuls %src, %scalar : !pto.tile<...>, f32 +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tmuls %src, %scalar : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tmuls ins(%src, %scalar : !pto.tile_buf<...>, dtype) outs(%dst : !pto.tile_buf<...>) +``` + +### IR Level 1 (SSA) + +```text +%dst = pto.tmuls %src, %scalar : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### IR Level 2 (DPS) + +```text +pto.tmuls ins(%src, %scalar : !pto.tile_buf<...>, dtype) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TMULS(TileDataDst &dst, TileDataSrc &src0, typename TileDataSrc::DType scalar, WaitEvents &... events); +``` + +## Constraints + +- **Implementation checks (A2A3)**: + - `TileData::DType` must be one of: `int32_t`, `int`, `int16_t`, `half`, `float16_t`, `float`, `float32_t`. + - Tile location must be vector (`TileData::Loc == TileType::Vec`). + - Static valid bounds: `TileData::ValidRow <= TileData::Rows` and `TileData::ValidCol <= TileData::Cols`. + - Runtime: `src0.GetValidRow() == dst.GetValidRow()` and `src0.GetValidCol() == dst.GetValidCol()`. + - Tile layout must be row-major (`TileData::isRowMajor`). +- **Implementation checks (A5)**: + - `TileData::DType` must be one of: `uint8_t`, `int8_t`, `uint16_t`, `int16_t`, `uint32_t`, `int32_t`, `half`, `float`, `bfloat16_t`. + - Tile location must be vector (`TileData::Loc == TileType::Vec`). + - Static valid bounds: `TileData::ValidRow <= TileData::Rows` and `TileData::ValidCol <= TileData::Cols`. + - Runtime: `src0.GetValidCol() == dst.GetValidCol()`. + - Tile layout must be row-major (`TileData::isRowMajor`). +- **Valid region**: + - The op uses `dst.GetValidRow()` / `dst.GetValidCol()` as the iteration domain. + +## Examples + +### Auto + +```cpp +#include + +using namespace pto; + +void example_auto() { + using TileT = Tile; + TileT src, dst; + TMULS(dst, src, 2.0f); +} +``` + +### Manual + +```cpp +#include + +using namespace pto; + +void example_manual() { + using TileT = Tile; + TileT src, dst; + TASSIGN(src, 0x1000); + TASSIGN(dst, 0x2000); + TMULS(dst, src, 2.0f); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.tmuls %src, %scalar : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tmuls %src, %scalar : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = tmuls %src, %scalar : !pto.tile<...>, f32 +# AS Level 2 (DPS) +pto.tmuls ins(%src, %scalar : !pto.tile_buf<...>, dtype) outs(%dst : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TMULS_zh.md b/designs/outerCube/PTOISA/TMULS_zh.md new file mode 100644 index 00000000..20425d19 --- /dev/null +++ b/designs/outerCube/PTOISA/TMULS_zh.md @@ -0,0 +1,107 @@ +# TMULS + +## 指令示意图 + +![TMULS tile operation](../figures/isa/TMULS.svg) + +## 简介 + +Tile 与标量的逐元素乘法。 + +## 数学语义 + +对每个元素 `(i, j)` 在有效区域内： + +$$ \mathrm{dst}_{i,j} = \mathrm{src}_{i,j} \cdot \mathrm{scalar} $$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS Specification](../assembly/PTO-AS.md). + +同步形式： + +```text +%dst = tmuls %src, %scalar : !pto.tile<...>, f32 +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tmuls %src, %scalar : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tmuls ins(%src, %scalar : !pto.tile_buf<...>, dtype) outs(%dst : !pto.tile_buf<...>) +``` + +### AS Level 1（SSA） + +```text +%dst = pto.tmuls %src, %scalar : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.tmuls ins(%src, %scalar : !pto.tile_buf<...>, dtype) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TMULS(TileDataDst &dst, TileDataSrc &src0, typename TileDataSrc::DType scalar, WaitEvents &... events); +``` + +## 约束 + +- **实现检查 (A2A3)**: + - `TileData::DType` must be one of: `int32_t`, `int`, `int16_t`, `half`, `float16_t`, `float`, `float32_t`. + - Tile location must be vector (`TileData::Loc == TileType::Vec`). + - Static valid bounds: `TileData::ValidRow <= TileData::Rows` and `TileData::ValidCol <= TileData::Cols`. + - Runtime: `src0.GetValidRow() == dst.GetValidRow()` and `src0.GetValidCol() == dst.GetValidCol()`. + - Tile 布局 must be row-major (`TileData::isRowMajor`). +- **实现检查 (A5)**: + - `TileData::DType` must be one of: `uint8_t`, `int8_t`, `uint16_t`, `int16_t`, `uint32_t`, `int32_t`, `half`, `float`, `bfloat16_t`. + - Tile location must be vector (`TileData::Loc == TileType::Vec`). + - Static valid bounds: `TileData::ValidRow <= TileData::Rows` and `TileData::ValidCol <= TileData::Cols`. + - Runtime: `src0.GetValidCol() == dst.GetValidCol()`. + - Tile 布局 must be row-major (`TileData::isRowMajor`). +- **有效区域**: + - The op uses `dst.GetValidRow()` / `dst.GetValidCol()` as the iteration domain. + +## 示例 + +### 自动（Auto） + +```cpp +#include + +using namespace pto; + +void example_auto() { + using TileT = Tile; + TileT src, dst; + TMULS(dst, src, 2.0f); +} +``` + +### 手动（Manual） + +```cpp +#include + +using namespace pto; + +void example_manual() { + using TileT = Tile; + TileT src, dst; + TASSIGN(src, 0x1000); + TASSIGN(dst, 0x2000); + TMULS(dst, src, 2.0f); +} +``` diff --git a/designs/outerCube/PTOISA/TMUL_zh.md b/designs/outerCube/PTOISA/TMUL_zh.md new file mode 100644 index 00000000..14b6351a --- /dev/null +++ b/designs/outerCube/PTOISA/TMUL_zh.md @@ -0,0 +1,108 @@ +# TMUL + +## 指令示意图 + +![TMUL tile operation](../figures/isa/TMUL.svg) + +## 简介 + +两个 Tile 的逐元素乘法。 + +## 数学语义 + +对每个元素 `(i, j)` 在有效区域内： + +$$ \mathrm{dst}_{i,j} = \mathrm{src0}_{i,j} \cdot \mathrm{src1}_{i,j} $$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS Specification](../assembly/PTO-AS.md). + +同步形式： + +```text +%dst = tmul %src0, %src1 : !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tmul %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tmul ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### AS Level 1（SSA） + +```text +%dst = pto.tmul %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.tmul ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TMUL(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, WaitEvents &... events); +``` + +## 约束 + +- **实现检查 (A2A3)**: + - `TileData::DType` must be one of: `int32_t`, `int16_t`, `half`, `float`. + - Tile location must be vector (`TileData::Loc == TileType::Vec`). + - Static valid bounds: `TileData::ValidRow <= TileData::Rows` and `TileData::ValidCol <= TileData::Cols`. + - Tile 布局 must be row-major (`TileData::isRowMajor`). + - Runtime: `src0`, `src1` and `dst` tiles should have the same `validRow/validCol`. +- **实现检查 (A5)**: + - `TileData::DType` must be one of: `int32_t`, `uint32_t`, `float`, `int16_t`, `uint16_t`, `half`. + - Tile location must be vector (`TileData::Loc == TileType::Vec`). + - Static valid bounds: `TileData::ValidRow <= TileData::Rows` and `TileData::ValidCol <= TileData::Cols`. + - Tile 布局 must be row-major (`TileData::isRowMajor`). + - Runtime: `src0`, `src1` and `dst` tiles should have the same `validRow/validCol`. +- **有效区域**: + - The op uses `dst.GetValidRow()` / `dst.GetValidCol()` as the iteration domain; . + +## 示例 + +### 自动（Auto） + +```cpp +#include + +using namespace pto; + +void example_auto() { + using TileT = Tile; + TileT src0, src1, dst; + TMUL(dst, src0, src1); +} +``` + +### 手动（Manual） + +```cpp +#include + +using namespace pto; + +void example_manual() { + using TileT = Tile; + TileT src0, src1, dst; + TASSIGN(src0, 0x1000); + TASSIGN(src1, 0x2000); + TASSIGN(dst, 0x3000); + TMUL(dst, src0, src1); +} +``` diff --git a/designs/outerCube/PTOISA/TNEG.md b/designs/outerCube/PTOISA/TNEG.md new file mode 100644 index 00000000..c29ae21b --- /dev/null +++ b/designs/outerCube/PTOISA/TNEG.md @@ -0,0 +1,103 @@ +# TNEG + + +## Tile Operation Diagram + +![TNEG tile operation](../figures/isa/TNEG.svg) + +## Introduction + +Elementwise negation of a tile. + +## Math Interpretation + +For each element `(i, j)` in the valid region: + +$$ \mathrm{dst}_{i,j} = -\mathrm{src}_{i,j} $$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = tneg %src : !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tneg %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tneg ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### IR Level 1 (SSA) + +```text +%dst = pto.tneg %src : !pto.tile<...> -> !pto.tile<...> +``` + +### IR Level 2 (DPS) + +```text +pto.tneg ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TNEG(TileDataDst &dst, TileDataSrc &src, WaitEvents &... events); +``` + +## Constraints + +- The op iterates over `dst.GetValidRow()` / `dst.GetValidCol()`. + +## Examples + +```cpp +#include + +using namespace pto; + +void example() { + using TileT = Tile; + TileT x, out; + TNEG(out, x); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.tneg %src : !pto.tile<...> -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tneg %src : !pto.tile<...> -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = tneg %src : !pto.tile<...> +# AS Level 2 (DPS) +pto.tneg ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TNEG_zh.md b/designs/outerCube/PTOISA/TNEG_zh.md new file mode 100644 index 00000000..ae533466 --- /dev/null +++ b/designs/outerCube/PTOISA/TNEG_zh.md @@ -0,0 +1,76 @@ +# TNEG + +## 指令示意图 + +![TNEG tile operation](../figures/isa/TNEG.svg) + +## 简介 + +Tile 的逐元素取负。 + +## 数学语义 + +对每个元素 `(i, j)` 在有效区域内： + +$$ \mathrm{dst}_{i,j} = -\mathrm{src}_{i,j} $$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS Specification](../assembly/PTO-AS.md). + +同步形式： + +```text +%dst = tneg %src : !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tneg %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tneg ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### AS Level 1（SSA） + +```text +%dst = pto.tneg %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.tneg ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TNEG(TileDataDst &dst, TileDataSrc &src, WaitEvents &... events); +``` + +## 约束 + +- The op iterates over `dst.GetValidRow()` / `dst.GetValidCol()`. + +## 示例 + +```cpp +#include + +using namespace pto; + +void example() { + using TileT = Tile; + TileT x, out; + TNEG(out, x); +} +``` diff --git a/designs/outerCube/PTOISA/TNOT.md b/designs/outerCube/PTOISA/TNOT.md new file mode 100644 index 00000000..84c439fd --- /dev/null +++ b/designs/outerCube/PTOISA/TNOT.md @@ -0,0 +1,119 @@ +# TNOT + + +## Tile Operation Diagram + +![TNOT tile operation](../figures/isa/TNOT.svg) + +## Introduction + +Elementwise bitwise NOT of a tile. + +## Math Interpretation + +For each element `(i, j)` in the valid region: + +$$ \mathrm{dst}_{i,j} = \sim\mathrm{src}_{i,j} $$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = tnot %src : !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tnot %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tnot ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### IR Level 1 (SSA) + +```text +%dst = pto.tnot %src : !pto.tile<...> -> !pto.tile<...> +``` + +### IR Level 2 (DPS) + +```text +pto.tnot ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TNOT(TileDataDst &dst, TileDataSrc &src, WaitEvents &... events); +``` + +## Constraints + +## Constraints + +- **Implementation checks (A2A3)**: + - `TileData::DType` must be one of: `int16_t`, `uint16_t`. + - Tile layout must be row-major (`TileData::isRowMajor`). + - Tile location must be vector (`TileData::Loc == TileType::Vec`). + - Static valid bounds: `TileData::ValidRow <= TileData::Rows` and `TileData::ValidCol <= TileData::Cols`. + - Runtime: `src` and `dst` tiles should have the same `validRow/validCol`. +- **Implementation checks (A5)**: + - `TileData::DType` must be one of: `uint32_t`, `int32_t`, `uint16_t`, `int16_t`, `uint8_t`, `int8_t`. + - Tile layout must be row-major (`TileData::isRowMajor`). + - Tile location must be vector (`TileData::Loc == TileType::Vec`). + - Static valid bounds: `TileData::ValidRow <= TileData::Rows` and `TileData::ValidCol <= TileData::Cols`. + - Runtime: `src` and `dst` tiles should have the same `validRow/validCol`. +- **Valid region**: + - The op uses `dst.GetValidRow()` / `dst.GetValidCol()` as the iteration domain; `src/dst` are assumed to be compatible (not validated by explicit runtime checks in this op). + + +## Examples + +```cpp +#include + +using namespace pto; + +void example() { + using TileT = Tile; + TileT x, out; + TNOT(out, x); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.tnot %src : !pto.tile<...> -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tnot %src : !pto.tile<...> -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = tnot %src : !pto.tile<...> +# AS Level 2 (DPS) +pto.tnot ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TNOT_zh.md b/designs/outerCube/PTOISA/TNOT_zh.md new file mode 100644 index 00000000..3c88eabb --- /dev/null +++ b/designs/outerCube/PTOISA/TNOT_zh.md @@ -0,0 +1,89 @@ +# TNOT + +## 指令示意图 + +![TNOT tile operation](../figures/isa/TNOT.svg) + +## 简介 + +Tile 的逐元素按位取反。 + +## 数学语义 + +对每个元素 `(i, j)` 在有效区域内： + +$$ \mathrm{dst}_{i,j} = \sim\mathrm{src}_{i,j} $$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS Specification](../assembly/PTO-AS.md). + +同步形式： + +```text +%dst = tnot %src : !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tnot %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tnot ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### AS Level 1（SSA） + +```text +%dst = pto.tnot %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.tnot ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TNOT(TileDataDst &dst, TileDataSrc &src, WaitEvents &... events); +``` + +## 约束 + +- **实现检查 (A2A3)**: + - `TileData::DType` must be one of: `int16_t`, `uint16_t`. + - Tile 布局 must be row-major (`TileData::isRowMajor`). + - Tile location must be vector (`TileData::Loc == TileType::Vec`). + - Static valid bounds: `TileData::ValidRow <= TileData::Rows` and `TileData::ValidCol <= TileData::Cols`. + - Runtime: `src` and `dst` tiles should have the same `validRow/validCol`. +- **实现检查 (A5)**: + - `TileData::DType` must be one of: `uint32_t`, `int32_t`, `uint16_t`, `int16_t`, `uint8_t`, `int8_t`. + - Tile 布局 must be row-major (`TileData::isRowMajor`). + - Tile location must be vector (`TileData::Loc == TileType::Vec`). + - Static valid bounds: `TileData::ValidRow <= TileData::Rows` and `TileData::ValidCol <= TileData::Cols`. + - Runtime: `src` and `dst` tiles should have the same `validRow/validCol`. +- **有效区域**: + - The op uses `dst.GetValidRow()` / `dst.GetValidCol()` as the iteration domain; `src/dst` are assumed to be compatible (not validated by explicit runtime checks in this op). + +## 示例 + +```cpp +#include + +using namespace pto; + +void example() { + using TileT = Tile; + TileT x, out; + TNOT(out, x); +} +``` diff --git a/designs/outerCube/PTOISA/TOR.md b/designs/outerCube/PTOISA/TOR.md new file mode 100644 index 00000000..ece1123c --- /dev/null +++ b/designs/outerCube/PTOISA/TOR.md @@ -0,0 +1,103 @@ +# TOR + + +## Tile Operation Diagram + +![TOR tile operation](../figures/isa/TOR.svg) + +## Introduction + +Elementwise bitwise OR of two tiles. + +## Math Interpretation + +For each element `(i, j)` in the valid region: + +$$ \mathrm{dst}_{i,j} = \mathrm{src0}_{i,j} \;|\; \mathrm{src1}_{i,j} $$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = tor %src0, %src1 : !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tor %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tor ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TOR(TileData &dst, TileData &src0, TileData &src1, WaitEvents &... events); +``` + +## Constraints + +- **Implementation checks (A2A3)**: + - Supported element types are 1-byte or 2-byte integral types. + - `dst`, `src0`, and `src1` must use the same element type. + - `dst`, `src0`, and `src1` must be row-major. + - Runtime: `src0.GetValidRow()/GetValidCol()` and `src1.GetValidRow()/GetValidCol()` must match `dst`. +- **Implementation checks (A5)**: + - Supported element types are `uint8_t`, `int8_t`, `uint16_t`, `int16_t`, `uint32_t`, and `int32_t`. + - `dst`, `src0`, and `src1` must use the same element type. + - `dst`, `src0`, and `src1` must be row-major. + - Runtime: `src0.GetValidRow()/GetValidCol()` and `src1.GetValidRow()/GetValidCol()` must match `dst`. +- **Valid region**: + - The op uses `dst.GetValidRow()` / `dst.GetValidCol()` as the iteration domain. + +## Examples + +```cpp +#include + +using namespace pto; + +void example() { + using TileT = Tile; + TileT a, b, out; + TOR(out, a, b); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.tor %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tor %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = tor %src0, %src1 : !pto.tile<...> +# AS Level 2 (DPS) +pto.tor ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/TORS.md b/designs/outerCube/PTOISA/TORS.md new file mode 100644 index 00000000..8bd53389 --- /dev/null +++ b/designs/outerCube/PTOISA/TORS.md @@ -0,0 +1,106 @@ +# TORS + + +## Tile Operation Diagram + +![TORS tile operation](../figures/isa/TORS.svg) + +## Introduction + +Elementwise bitwise OR of a tile and a scalar. + +## Math Interpretation + +For each element `(i, j)` in the valid region: + +$$ \mathrm{dst}_{i,j} = \mathrm{src}_{i,j} \;|\; \mathrm{scalar} $$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = tors %src, %scalar : !pto.tile<...>, i32 +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tors %src, %scalar : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tors ins(%src, %scalar : !pto.tile_buf<...>, dtype) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TORS(TileDataDst &dst, TileDataSrc &src, typename TileDataDst::DType scalar, WaitEvents &... events); +``` + +## Constraints + +- **Implementation checks (A2A3)**: + - Intended for integral element types. + - `dst` and `src` must use the same element type. + - `dst` and `src` must be vector tiles. + - Runtime: `src.GetValidRow() == dst.GetValidRow()` and `src.GetValidCol() == dst.GetValidCol()`. + - In manual mode, setting the source tile and destination tile to the same memory is unsupported. +- **Implementation checks (A5)**: + - Intended for integral element types supported by `TEXPANDS` and `TOR`. + - `dst` and `src` must use the same element type. + - `dst` and `src` must be vector tiles. + - In manual mode, setting the source tile and destination tile to the same memory is unsupported. +- **Valid region**: + - The op uses `dst.GetValidRow()` / `dst.GetValidCol()` as the iteration domain. + +## Examples + +```cpp +#include + +using namespace pto; + +void example() { + using TileDst = Tile; + using TileSrc = Tile; + TileDst dst; + TileSrc src; + TORS(dst, src, 0xffu); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.tors %src, %scalar : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tors %src, %scalar : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = tors %src, %scalar : !pto.tile<...>, i32 +# AS Level 2 (DPS) +pto.tors ins(%src, %scalar : !pto.tile_buf<...>, dtype) outs(%dst : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/TORS_zh.md b/designs/outerCube/PTOISA/TORS_zh.md new file mode 100644 index 00000000..65c938fb --- /dev/null +++ b/designs/outerCube/PTOISA/TORS_zh.md @@ -0,0 +1,106 @@ +# TORS + +## 指令示意图 + +![TORS tile operation](../figures/isa/TORS.svg) + +## 简介 + +Tile 与标量的逐元素按位或。 + +## 数学语义 + +对每个元素 `(i, j)` 在有效区域内： + +$$ \mathrm{dst}_{i,j} = \mathrm{src}_{i,j} \;|\; \mathrm{scalar} $$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS 规范](../assembly/PTO-AS_zh.md)。 + +同步形式： + +```text +%dst = tors %src, %scalar : !pto.tile<...>, i32 +``` + +### AS Level 1（SSA） + +```text +%dst = pto.tors %src, %scalar : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.tors ins(%src, %scalar : !pto.tile_buf<...>, dtype) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`： + +```cpp +template +PTO_INST RecordEvent TORS(TileDataDst &dst, TileDataSrc &src, typename TileDataDst::DType scalar, WaitEvents &... events); +``` + +## 约束 + +- **实现检查 (A2A3)**: + - 适用于整数元素类型。 + - `dst` 和 `src` 必须使用相同的元素类型。 + - `dst` 和 `src` 必须是向量 Tile。 + - 运行时：`src.GetValidRow() == dst.GetValidRow()` 且 `src.GetValidCol() == dst.GetValidCol()`。 + - 在手动模式下，不支持将源 Tile 和目标 Tile 设置为相同的内存。 +- **实现检查 (A5)**: + - 适用于 `TEXPANDS` 和 `TOR` 支持的整数元素类型。 + - `dst` 和 `src` 必须使用相同的元素类型。 + - `dst` 和 `src` 必须是向量 Tile。 + - 在手动模式下，不支持将源 Tile 和目标 Tile 设置为相同的内存。 +- **有效区域**: + - 该操作使用 `dst.GetValidRow()` / `dst.GetValidCol()` 作为迭代域。 + +## 示例 + +```cpp +#include + +using namespace pto; + +void example() { + using TileDst = Tile; + using TileSrc = Tile; + TileDst dst; + TileSrc src; + TORS(dst, src, 0xffu); +} +``` + +## 汇编示例（ASM） + +### 自动模式 + +```text +# 自动模式：由编译器/运行时负责资源放置与调度。 +%dst = pto.tors %src, %scalar : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### 手动模式 + +```text +# 手动模式：先显式绑定资源，再发射指令。 +# 可选（当该指令包含 tile 操作数时）： +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tors %src, %scalar : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### PTO 汇编形式 + +```text +%dst = tors %src, %scalar : !pto.tile<...>, i32 +# AS Level 2 (DPS) +pto.tors ins(%src, %scalar : !pto.tile_buf<...>, dtype) outs(%dst : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/TOR_zh.md b/designs/outerCube/PTOISA/TOR_zh.md new file mode 100644 index 00000000..8ad38d80 --- /dev/null +++ b/designs/outerCube/PTOISA/TOR_zh.md @@ -0,0 +1,103 @@ +# TOR + +## 指令示意图 + +![TOR tile operation](../figures/isa/TOR.svg) + +## 简介 + +两个 Tile 的逐元素按位或。 + +## 数学语义 + +对每个元素 `(i, j)` 在有效区域内： + +$$ \mathrm{dst}_{i,j} = \mathrm{src0}_{i,j} \;|\; \mathrm{src1}_{i,j} $$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS 规范](../assembly/PTO-AS_zh.md)。 + +同步形式： + +```text +%dst = tor %src0, %src1 : !pto.tile<...> +``` + +### AS Level 1（SSA） + +```text +%dst = pto.tor %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.tor ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`： + +```cpp +template +PTO_INST RecordEvent TOR(TileData &dst, TileData &src0, TileData &src1, WaitEvents &... events); +``` + +## 约束 + +- **实现检查 (A2A3)**: + - 支持的元素类型为 1 字节或 2 字节整数类型。 + - `dst`、`src0` 和 `src1` 必须使用相同的元素类型。 + - `dst`、`src0` 和 `src1` 必须是行主序。 + - 运行时：`src0.GetValidRow()/GetValidCol()` 和 `src1.GetValidRow()/GetValidCol()` 必须与 `dst` 一致。 +- **实现检查 (A5)**: + - 支持的元素类型为 `uint8_t`、`int8_t`、`uint16_t`、`int16_t`、`uint32_t` 和 `int32_t`。 + - `dst`、`src0` 和 `src1` 必须使用相同的元素类型。 + - `dst`、`src0` 和 `src1` 必须是行主序。 + - 运行时：`src0.GetValidRow()/GetValidCol()` 和 `src1.GetValidRow()/GetValidCol()` 必须与 `dst` 一致。 +- **有效区域**: + - 该操作使用 `dst.GetValidRow()` / `dst.GetValidCol()` 作为迭代域。 + +## 示例 + +```cpp +#include + +using namespace pto; + +void example() { + using TileT = Tile; + TileT a, b, out; + TOR(out, a, b); +} +``` + +## 汇编示例（ASM） + +### 自动模式 + +```text +# 自动模式：由编译器/运行时负责资源放置与调度。 +%dst = pto.tor %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### 手动模式 + +```text +# 手动模式：先显式绑定资源，再发射指令。 +# 可选（当该指令包含 tile 操作数时）： +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tor %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### PTO 汇编形式 + +```text +%dst = tor %src0, %src1 : !pto.tile<...> +# AS Level 2 (DPS) +pto.tor ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/TPACK.md b/designs/outerCube/PTOISA/TPACK.md new file mode 100644 index 00000000..b96033de --- /dev/null +++ b/designs/outerCube/PTOISA/TPACK.md @@ -0,0 +1,40 @@ +# TPACK + +## Tile Operation Diagram + +![TPACK tile operation](../figures/isa/TPACK.svg) + +## Introduction + +Pack or convert tile elements into a narrower destination representation. + +## Math Interpretation + +Semantics are instruction-specific. Unless stated otherwise, behavior is defined over the destination valid region. + +## Assembly Syntax + +PTO-AS form: see `docs/assembly/PTO-AS.md`. + +### IR Level 1 (SSA) + +```text +%dst = pto.tpack ... +``` + +### IR Level 2 (DPS) + +```text +pto.tpack ins(...) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`. + +## Constraints + +Refer to backend-specific legality checks for data type/layout/location/shape constraints. + +## Examples + +See related instruction pages in `docs/isa/` for concrete Auto/Manual usage patterns. diff --git a/designs/outerCube/PTOISA/TPACK_zh.md b/designs/outerCube/PTOISA/TPACK_zh.md new file mode 100644 index 00000000..71a90d2c --- /dev/null +++ b/designs/outerCube/PTOISA/TPACK_zh.md @@ -0,0 +1,41 @@ +# TPACK + +## 指令示意图 + +![TPACK tile operation](../figures/isa/TPACK.svg) + +## 简介 + +将 Tile 元素打包或转换为更窄的目标表示。 + +## 数学语义 + +语义随指令而变化。 Unless stated otherwise, behavior is defined over the destination valid region. + +## 汇编语法 + +PTO-AS 形式：参见 `docs/assembly/PTO-AS.md`. + +### AS Level 1（SSA） + +```text +%dst = pto.tpack ... +``` + +### AS Level 2（DPS） + +```text +pto.tpack ins(...) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`. + +## 约束 + +Refer to backend-specific legality checks for data type/layout/location/shape constraints. + +## 示例 + +See related instruction pages in `docs/isa/` for concrete Auto/Manual usage patterns. diff --git a/designs/outerCube/PTOISA/TPARTADD.md b/designs/outerCube/PTOISA/TPARTADD.md new file mode 100644 index 00000000..8409953f --- /dev/null +++ b/designs/outerCube/PTOISA/TPARTADD.md @@ -0,0 +1,137 @@ +# TPARTADD + + +## Tile Operation Diagram + +![TPARTADD tile operation](../figures/isa/TPARTADD.svg) + +## Introduction + +Partial elementwise add with implementation-defined handling of mismatched valid regions. + +## Math Interpretation + +For each element `(i, j)` in the destination valid region: + +$$ +\mathrm{dst}_{i,j} = +\begin{cases} +\mathrm{src0}_{i,j} + \mathrm{src1}_{i,j} & \text{if both inputs are defined at } (i,j) \\ +\mathrm{src0}_{i,j} & \text{if only src0 is defined at } (i,j) \\ +\mathrm{src1}_{i,j} & \text{if only src1 is defined at } (i,j) +\end{cases} +$$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = tpartadd %src0, %src1 : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tpartadd %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tpartadd ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### IR Level 1 (SSA) + +```text +%dst = pto.tpartadd %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### IR Level 2 (DPS) + +```text +pto.tpartadd ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TPARTADD(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, WaitEvents &... events); +``` + +## Constraints + +- **Implementation checks (A2A3)**: + - `dst/src0/src1` element types must be identical, and must be one of: `int32_t`, `int16_t`, `half`, `float`. + - All three tiles must be row-major (`isRowMajor`). + - Runtime: if `dst.GetValidRow() == 0` or `dst.GetValidCol() == 0`, the op returns early. + - Runtime: the implementation requires at least one input's valid region to match `dst`'s valid region, and the other's valid region not greater than `dst`'s valid region (otherwise it asserts). +- **Implementation checks (A5)**: + - `dst/src0/src1` element types must be identical, and must be one of: `uint8_t`, `int8_t`, `uint16_t`, `int16_t`, `uint32_t`, `int32_t`, `half`, `float`, `bfloat16_t`. + - Runtime: if `dst` has a zero valid region, the op returns early. + - Only certain partial-validity patterns are handled (e.g., one source equal to `dst` while the other is smaller by valid-rows or valid-cols); other patterns are not supported (target-defined behavior). + +## Examples + +### Auto + +```cpp +#include + +using namespace pto; + +void example_auto() { + using TileT = Tile; + TileT src0, src1, dst; + TPARTADD(dst, src0, src1); +} +``` + +### Manual + +```cpp +#include + +using namespace pto; + +void example_manual() { + using TileT = Tile; + TileT src0, src1, dst; + TASSIGN(src0, 0x1000); + TASSIGN(src1, 0x2000); + TASSIGN(dst, 0x3000); + TPARTADD(dst, src0, src1); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.tpartadd %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tpartadd %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = tpartadd %src0, %src1 : !pto.tile<...> -> !pto.tile<...> +# AS Level 2 (DPS) +pto.tpartadd ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TPARTADD_zh.md b/designs/outerCube/PTOISA/TPARTADD_zh.md new file mode 100644 index 00000000..dc0569b5 --- /dev/null +++ b/designs/outerCube/PTOISA/TPARTADD_zh.md @@ -0,0 +1,110 @@ +# TPARTADD + +## 指令示意图 + +![TPARTADD tile operation](../figures/isa/TPARTADD.svg) + +## 简介 + +部分逐元素加法，对不匹配的有效区域具有实现定义的处理方式。 + +## 数学语义 + +对每个元素 `(i, j)` in the destination valid region: + +$$ +\mathrm{dst}_{i,j} = +\begin{cases} +\mathrm{src0}_{i,j} + \mathrm{src1}_{i,j} & \text{if both inputs are defined at } (i,j) \\ +\mathrm{src0}_{i,j} & \text{if only src0 is defined at } (i,j) \\ +\mathrm{src1}_{i,j} & \text{if only src1 is defined at } (i,j) +\end{cases} +$$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS Specification](../assembly/PTO-AS.md). + +同步形式： + +```text +%dst = tpartadd %src0, %src1 : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tpartadd %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tpartadd ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### AS Level 1（SSA） + +```text +%dst = pto.tpartadd %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.tpartadd ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TPARTADD(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, WaitEvents &... events); +``` + +## 约束 + +- **实现检查 (A2A3)**: + - `dst/src0/src1` element types must be identical, and must be one of: `int32_t`, `int16_t`, `half`, `float`. + - All three tiles must be row-major (`isRowMajor`). + - Runtime: if `dst.GetValidRow() == 0` or `dst.GetValidCol() == 0`, the op returns early. + - Runtime: the implementation requires at least one input's valid region to match `dst`'s valid region, and the other's valid region not greater than `dst`'s valid region (otherwise it asserts). +- **实现检查 (A5)**: + - `dst/src0/src1` element types must be identical, and must be one of: `uint8_t`, `int8_t`, `uint16_t`, `int16_t`, `uint32_t`, `int32_t`, `half`, `float`, `bfloat16_t`. + - Runtime: if `dst` has a zero valid region, the op returns early. + - Only certain partial-validity patterns are handled (e.g., one source equal to `dst` while the other is smaller by valid-rows or valid-cols); other patterns are not supported (target-defined behavior). + +## 示例 + +### 自动（Auto） + +```cpp +#include + +using namespace pto; + +void example_auto() { + using TileT = Tile; + TileT src0, src1, dst; + TPARTADD(dst, src0, src1); +} +``` + +### 手动（Manual） + +```cpp +#include + +using namespace pto; + +void example_manual() { + using TileT = Tile; + TileT src0, src1, dst; + TASSIGN(src0, 0x1000); + TASSIGN(src1, 0x2000); + TASSIGN(dst, 0x3000); + TPARTADD(dst, src0, src1); +} +``` diff --git a/designs/outerCube/PTOISA/TPARTMAX.md b/designs/outerCube/PTOISA/TPARTMAX.md new file mode 100644 index 00000000..a0762900 --- /dev/null +++ b/designs/outerCube/PTOISA/TPARTMAX.md @@ -0,0 +1,137 @@ +# TPARTMAX + + +## Tile Operation Diagram + +![TPARTMAX tile operation](../figures/isa/TPARTMAX.svg) + +## Introduction + +Partial elementwise max with implementation-defined handling of mismatched valid regions. + +## Math Interpretation + +For each element `(i, j)` in the destination valid region: + +$$ +\mathrm{dst}_{i,j} = +\begin{cases} +\max(\mathrm{src0}_{i,j}, \mathrm{src1}_{i,j}) & \text{if both inputs are defined at } (i,j) \\ +\mathrm{src0}_{i,j} & \text{if only src0 is defined at } (i,j) \\ +\mathrm{src1}_{i,j} & \text{if only src1 is defined at } (i,j) +\end{cases} +$$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = tpartmax %src0, %src1 : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tpartmax %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tpartmax ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### IR Level 1 (SSA) + +```text +%dst = pto.tpartmax %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### IR Level 2 (DPS) + +```text +pto.tpartmax ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TPARTMAX(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, WaitEvents &... events); +``` + +## Constraints + +- **Implementation checks (A2A3)**: + - `dst/src0/src1` element types must be identical, and must be one of: `int32_t`, `int16_t`, `half`, `float`. + - All three tiles must be row-major (`isRowMajor`). + - Runtime: if `dst.GetValidRow() == 0` or `dst.GetValidCol() == 0`, the op returns early. + - Runtime: the implementation requires at least one input's valid region to match `dst`'s valid region, and the onther's valid region not greater than `dst`'s valid region (otherwise it asserts). +- **Implementation checks (A5)**: + - `dst/src0/src1` element types must be identical and must be one of: `int8_t`, `uint8_t`, `int16_t`, `uint16_t`, `int32_t`, `uint32_t`, `half`, `bfloat16_t`, `float`. + - Runtime: if any of `src0/src1/dst` has a zero valid region, the op returns early. + - Requires `src0` and `src1` valid region to be `<= dst` valid region in both dimensions; other patterns are not supported (target-defined behavior). + +## Examples + +### Auto + +```cpp +#include + +using namespace pto; + +void example_auto() { + using TileT = Tile; + TileT src0, src1, dst; + TPARTMAX(dst, src0, src1); +} +``` + +### Manual + +```cpp +#include + +using namespace pto; + +void example_manual() { + using TileT = Tile; + TileT src0, src1, dst; + TASSIGN(src0, 0x1000); + TASSIGN(src1, 0x2000); + TASSIGN(dst, 0x3000); + TPARTMAX(dst, src0, src1); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.tpartmax %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tpartmax %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = tpartmax %src0, %src1 : !pto.tile<...> -> !pto.tile<...> +# AS Level 2 (DPS) +pto.tpartmax ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TPARTMAX_zh.md b/designs/outerCube/PTOISA/TPARTMAX_zh.md new file mode 100644 index 00000000..a2916a9f --- /dev/null +++ b/designs/outerCube/PTOISA/TPARTMAX_zh.md @@ -0,0 +1,110 @@ +# TPARTMAX + +## 指令示意图 + +![TPARTMAX tile operation](../figures/isa/TPARTMAX.svg) + +## 简介 + +部分逐元素最大值，对不匹配的有效区域具有实现定义的处理方式。 + +## 数学语义 + +对每个元素 `(i, j)` in the destination valid region: + +$$ +\mathrm{dst}_{i,j} = +\begin{cases} +\max(\mathrm{src0}_{i,j}, \mathrm{src1}_{i,j}) & \text{if both inputs are defined at } (i,j) \\ +\mathrm{src0}_{i,j} & \text{if only src0 is defined at } (i,j) \\ +\mathrm{src1}_{i,j} & \text{if only src1 is defined at } (i,j) +\end{cases} +$$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS Specification](../assembly/PTO-AS.md). + +同步形式： + +```text +%dst = tpartmax %src0, %src1 : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tpartmax %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tpartmax ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### AS Level 1（SSA） + +```text +%dst = pto.tpartmax %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.tpartmax ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TPARTMAX(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, WaitEvents &... events); +``` + +## 约束 + +- **实现检查 (A2A3)**: + - `dst/src0/src1` element types must be identical, and must be one of: `int32_t`, `int16_t`, `half`, `float`. + - All three tiles must be row-major (`isRowMajor`). + - Runtime: if `dst.GetValidRow() == 0` or `dst.GetValidCol() == 0`, the op returns early. + - Runtime: the implementation requires at least one input's valid region to match `dst`'s valid region, and the onther's valid region not greater than `dst`'s valid region (otherwise it asserts). +- **实现检查 (A5)**: + - `dst/src0/src1` element types must be identical and must be one of: `int8_t`, `uint8_t`, `int16_t`, `uint16_t`, `int32_t`, `uint32_t`, `half`, `bfloat16_t`, `float`. + - Runtime: if any of `src0/src1/dst` has a zero valid region, the op returns early. + - Requires `src0` and `src1` valid region to be `<= dst` valid region in both dimensions; other patterns are not supported (target-defined behavior). + +## 示例 + +### 自动（Auto） + +```cpp +#include + +using namespace pto; + +void example_auto() { + using TileT = Tile; + TileT src0, src1, dst; + TPARTMAX(dst, src0, src1); +} +``` + +### 手动（Manual） + +```cpp +#include + +using namespace pto; + +void example_manual() { + using TileT = Tile; + TileT src0, src1, dst; + TASSIGN(src0, 0x1000); + TASSIGN(src1, 0x2000); + TASSIGN(dst, 0x3000); + TPARTMAX(dst, src0, src1); +} +``` diff --git a/designs/outerCube/PTOISA/TPARTMIN.md b/designs/outerCube/PTOISA/TPARTMIN.md new file mode 100644 index 00000000..fd9a8502 --- /dev/null +++ b/designs/outerCube/PTOISA/TPARTMIN.md @@ -0,0 +1,137 @@ +# TPARTMIN + + +## Tile Operation Diagram + +![TPARTMIN tile operation](../figures/isa/TPARTMIN.svg) + +## Introduction + +Partial elementwise min with implementation-defined handling of mismatched valid regions. + +## Math Interpretation + +For each element `(i, j)` in the destination valid region: + +$$ +\mathrm{dst}_{i,j} = +\begin{cases} +\min(\mathrm{src0}_{i,j}, \mathrm{src1}_{i,j}) & \text{if both inputs are defined at } (i,j) \\ +\mathrm{src0}_{i,j} & \text{if only src0 is defined at } (i,j) \\ +\mathrm{src1}_{i,j} & \text{if only src1 is defined at } (i,j) +\end{cases} +$$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = tpartmin %src0, %src1 : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tpartmin %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tpartmin ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### IR Level 1 (SSA) + +```text +%dst = pto.tpartmin %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### IR Level 2 (DPS) + +```text +pto.tpartmin ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TPARTMIN(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, WaitEvents &... events); +``` + +## Constraints + +- **Implementation checks (A2A3)**: + - `dst/src0/src1` element types must be identical, and must be one of: `int32_t`, `int16_t`, `half`, `float`. + - All three tiles must be row-major (`isRowMajor`). + - Runtime: if `dst.GetValidRow() == 0` or `dst.GetValidCol() == 0`, the op returns early. + - Runtime: the implementation requires at least one input's valid region to match `dst`'s valid region, and the onther's valid region not greater than `dst`'s valid region (otherwise it asserts). +- **Implementation checks (A5)**: + - `dst/src0/src1` element types must be identical and must be one of: `int8_t`, `uint8_t`, `int16_t`, `uint16_t`, `int32_t`, `uint32_t`, `half`, `bfloat16_t`, `float`. + - Runtime: if any of `src0/src1/dst` has a zero valid region, the op returns early. + - Requires `src0` and `src1` valid region to be `<= dst` valid region in both dimensions; other patterns are not supported (target-defined behavior). + +## Examples + +### Auto + +```cpp +#include + +using namespace pto; + +void example_auto() { + using TileT = Tile; + TileT src0, src1, dst; + TPARTMIN(dst, src0, src1); +} +``` + +### Manual + +```cpp +#include + +using namespace pto; + +void example_manual() { + using TileT = Tile; + TileT src0, src1, dst; + TASSIGN(src0, 0x1000); + TASSIGN(src1, 0x2000); + TASSIGN(dst, 0x3000); + TPARTMIN(dst, src0, src1); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.tpartmin %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tpartmin %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = tpartmin %src0, %src1 : !pto.tile<...> -> !pto.tile<...> +# AS Level 2 (DPS) +pto.tpartmin ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TPARTMIN_zh.md b/designs/outerCube/PTOISA/TPARTMIN_zh.md new file mode 100644 index 00000000..89b0603a --- /dev/null +++ b/designs/outerCube/PTOISA/TPARTMIN_zh.md @@ -0,0 +1,110 @@ +# TPARTMIN + +## 指令示意图 + +![TPARTMIN tile operation](../figures/isa/TPARTMIN.svg) + +## 简介 + +部分逐元素最小值，对不匹配的有效区域具有实现定义的处理方式。 + +## 数学语义 + +对每个元素 `(i, j)` in the destination valid region: + +$$ +\mathrm{dst}_{i,j} = +\begin{cases} +\min(\mathrm{src0}_{i,j}, \mathrm{src1}_{i,j}) & \text{if both inputs are defined at } (i,j) \\ +\mathrm{src0}_{i,j} & \text{if only src0 is defined at } (i,j) \\ +\mathrm{src1}_{i,j} & \text{if only src1 is defined at } (i,j) +\end{cases} +$$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS Specification](../assembly/PTO-AS.md). + +同步形式： + +```text +%dst = tpartmin %src0, %src1 : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tpartmin %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tpartmin ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### AS Level 1（SSA） + +```text +%dst = pto.tpartmin %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.tpartmin ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TPARTMIN(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, WaitEvents &... events); +``` + +## 约束 + +- **实现检查 (A2A3)**: + - `dst/src0/src1` element types must be identical, and must be one of: `int32_t`, `int16_t`, `half`, `float`. + - All three tiles must be row-major (`isRowMajor`). + - Runtime: if `dst.GetValidRow() == 0` or `dst.GetValidCol() == 0`, the op returns early. + - Runtime: the implementation requires at least one input's valid region to match `dst`'s valid region, and the onther's valid region not greater than `dst`'s valid region (otherwise it asserts). +- **实现检查 (A5)**: + - `dst/src0/src1` element types must be identical and must be one of: `int8_t`, `uint8_t`, `int16_t`, `uint16_t`, `int32_t`, `uint32_t`, `half`, `bfloat16_t`, `float`. + - Runtime: if any of `src0/src1/dst` has a zero valid region, the op returns early. + - Requires `src0` and `src1` valid region to be `<= dst` valid region in both dimensions; other patterns are not supported (target-defined behavior). + +## 示例 + +### 自动（Auto） + +```cpp +#include + +using namespace pto; + +void example_auto() { + using TileT = Tile; + TileT src0, src1, dst; + TPARTMIN(dst, src0, src1); +} +``` + +### 手动（Manual） + +```cpp +#include + +using namespace pto; + +void example_manual() { + using TileT = Tile; + TileT src0, src1, dst; + TASSIGN(src0, 0x1000); + TASSIGN(src1, 0x2000); + TASSIGN(dst, 0x3000); + TPARTMIN(dst, src0, src1); +} +``` diff --git a/designs/outerCube/PTOISA/TPARTMUL.md b/designs/outerCube/PTOISA/TPARTMUL.md new file mode 100644 index 00000000..d0da3546 --- /dev/null +++ b/designs/outerCube/PTOISA/TPARTMUL.md @@ -0,0 +1,129 @@ +# TPARTMUL + + +## Tile Operation Diagram + +![TPARTMUL tile operation](../figures/isa/TPARTMUL.svg) + +## Introduction + +Partial elementwise multiply with implementation-defined handling of mismatched valid regions. + +## Math Interpretation + +For each element `(i, j)` in the destination valid region: + +$$ +\mathrm{dst}_{i,j} = +egin{cases} +\mathrm{src0}_{i,j} \cdot \mathrm{src1}_{i,j} & ext{if both inputs are defined at } (i,j) \ +\mathrm{src0}_{i,j} & ext{if only src0 is defined at } (i,j) \ +\mathrm{src1}_{i,j} & ext{if only src1 is defined at } (i,j) +\end{cases} +$$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = tpartmul %src0, %src1 : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tpartmul %src0, %src1 : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tpartmul ins(%src0, %src1 : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### IR Level 1 (SSA) + +```text +%dst = pto.tpartmul %src0, %src1 : !pto.tile<...> -> !pto.tile<...> +``` + +### IR Level 2 (DPS) + +```text +pto.tpartmul ins(%src0, %src1 : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TPARTMUL(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, WaitEvents &... events); +``` + +## Constraints + +- Element type/layout legality follows backend checks and is analogous to `TPARTADD` / `TPARTMAX` / `TPARTMIN`. +- Destination valid region defines the result domain. +- Partial-validity handling is implementation-defined for unsupported shape combinations. + +## Examples + +### Auto + +```cpp +#include +using namespace pto; + +void example_auto() { + using TileT = Tile; + TileT src0, src1, dst; + TPARTMUL(dst, src0, src1); +} +``` + +### Manual + +```cpp +#include +using namespace pto; + +void example_manual() { + using TileT = Tile; + TileT src0, src1, dst; + TASSIGN(src0, 0x1000); + TASSIGN(src1, 0x2000); + TASSIGN(dst, 0x3000); + TPARTMUL(dst, src0, src1); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.tpartmul %src0, %src1 : !pto.tile<...> -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tpartmul %src0, %src1 : !pto.tile<...> -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = tpartmul %src0, %src1 : !pto.tile<...> -> !pto.tile<...> +# AS Level 2 (DPS) +pto.tpartmul ins(%src0, %src1 : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TPARTMUL_zh.md b/designs/outerCube/PTOISA/TPARTMUL_zh.md new file mode 100644 index 00000000..ca6c30c5 --- /dev/null +++ b/designs/outerCube/PTOISA/TPARTMUL_zh.md @@ -0,0 +1,102 @@ +# TPARTMUL + +## 指令示意图 + +![TPARTMUL tile operation](../figures/isa/TPARTMUL.svg) + +## 简介 + +部分逐元素乘法，对有效区域不一致的处理为实现定义。 + +## 数学语义 + +对每个元素 `(i, j)` in the destination valid region: + +$$ +\mathrm{dst}_{i,j} = +egin{cases} +\mathrm{src0}_{i,j} \cdot \mathrm{src1}_{i,j} & ext{if both inputs are defined at } (i,j) \ +\mathrm{src0}_{i,j} & ext{if only src0 is defined at } (i,j) \ +\mathrm{src1}_{i,j} & ext{if only src1 is defined at } (i,j) +\end{cases} +$$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS Specification](../assembly/PTO-AS.md). + +同步形式： + +```text +%dst = tpartmul %src0, %src1 : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tpartmul %src0, %src1 : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tpartmul ins(%src0, %src1 : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### AS Level 1（SSA） + +```text +%dst = pto.tpartmul %src0, %src1 : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.tpartmul ins(%src0, %src1 : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TPARTMUL(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, WaitEvents &... events); +``` + +## 约束 + +- Element type/layout legality follows backend checks and is analogous to `TPARTADD` / `TPARTMAX` / `TPARTMIN`. +- Destination valid region defines the result domain. +- Partial-validity handling is implementation-defined for unsupported shape combinations. + +## 示例 + +### 自动（Auto） + +```cpp +#include +using namespace pto; + +void example_auto() { + using TileT = Tile; + TileT src0, src1, dst; + TPARTMUL(dst, src0, src1); +} +``` + +### 手动（Manual） + +```cpp +#include +using namespace pto; + +void example_manual() { + using TileT = Tile; + TileT src0, src1, dst; + TASSIGN(src0, 0x1000); + TASSIGN(src1, 0x2000); + TASSIGN(dst, 0x3000); + TPARTMUL(dst, src0, src1); +} +``` diff --git a/designs/outerCube/PTOISA/TPOP.md b/designs/outerCube/PTOISA/TPOP.md new file mode 100644 index 00000000..1d49b220 --- /dev/null +++ b/designs/outerCube/PTOISA/TPOP.md @@ -0,0 +1,40 @@ +# TPOP + +## Tile Operation Diagram + +![TPOP tile operation](../figures/isa/TPOP.svg) + +## Introduction + +Pop a tile from a pipe or FIFO consumer endpoint. + +## Math Interpretation + +Semantics are instruction-specific. Unless stated otherwise, behavior is defined over the destination valid region. + +## Assembly Syntax + +PTO-AS form: see `docs/assembly/PTO-AS.md`. + +### IR Level 1 (SSA) + +```text +%dst = pto.tpop ... +``` + +### IR Level 2 (DPS) + +```text +pto.tpop ins(...) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`. + +## Constraints + +Refer to backend-specific legality checks for data type/layout/location/shape constraints. + +## Examples + +See related instruction pages in `docs/isa/` for concrete Auto/Manual usage patterns. diff --git a/designs/outerCube/PTOISA/TPOP_zh.md b/designs/outerCube/PTOISA/TPOP_zh.md new file mode 100644 index 00000000..1c6909d2 --- /dev/null +++ b/designs/outerCube/PTOISA/TPOP_zh.md @@ -0,0 +1,41 @@ +# TPOP + +## 指令示意图 + +![TPOP tile operation](../figures/isa/TPOP.svg) + +## 简介 + +从 pipe 或 FIFO 的消费者端弹出一个 Tile。 + +## 数学语义 + +语义随指令而变化。 Unless stated otherwise, behavior is defined over the destination valid region. + +## 汇编语法 + +PTO-AS 形式：参见 `docs/assembly/PTO-AS.md`. + +### AS Level 1（SSA） + +```text +%dst = pto.tpop ... +``` + +### AS Level 2（DPS） + +```text +pto.tpop ins(...) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`. + +## 约束 + +Refer to backend-specific legality checks for data type/layout/location/shape constraints. + +## 示例 + +See related instruction pages in `docs/isa/` for concrete Auto/Manual usage patterns. diff --git a/designs/outerCube/PTOISA/TPREFETCH.md b/designs/outerCube/PTOISA/TPREFETCH.md new file mode 100644 index 00000000..ab7fc128 --- /dev/null +++ b/designs/outerCube/PTOISA/TPREFETCH.md @@ -0,0 +1,94 @@ +# TPREFETCH + + +## Tile Operation Diagram + +![TPREFETCH tile operation](../figures/isa/TPREFETCH.svg) + +## Introduction + +Prefetch data from global memory into a tile-local cache/buffer (implementation-defined). This is typically used to reduce latency before a subsequent `TLOAD`. + +Note: unlike most PTO instructions, `TPREFETCH` does **not** implicitly call `TSYNC(events...)` in the C++ wrapper. + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = tprefetch %src : !pto.global<...> -> !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tprefetch %src : !pto.global<...> -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tprefetch ins(%src : !pto.global<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### IR Level 1 (SSA) + +```text +%dst = pto.tprefetch %src : !pto.global<...> -> !pto.tile<...> +``` + +### IR Level 2 (DPS) + +```text +pto.tprefetch ins(%src : !pto.global<...>) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TPREFETCH(TileData &dst, GlobalData &src); +``` + +## Constraints + +- Semantics and caching behavior are target/implementation-defined. +- Some targets may ignore prefetches or treat them as hints. + +## Math Interpretation + +Unless otherwise specified, semantics are defined over the valid region and target-dependent behavior is marked as implementation-defined. + +## Examples + +See related examples in `docs/isa/` and `docs/coding/tutorials/`. + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.tprefetch %src : !pto.global<...> -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tprefetch %src : !pto.global<...> -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = tprefetch %src : !pto.global<...> -> !pto.tile<...> +# AS Level 2 (DPS) +pto.tprefetch ins(%src : !pto.global<...>) outs(%dst : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TPREFETCH_zh.md b/designs/outerCube/PTOISA/TPREFETCH_zh.md new file mode 100644 index 00000000..2e22e6ff --- /dev/null +++ b/designs/outerCube/PTOISA/TPREFETCH_zh.md @@ -0,0 +1,65 @@ +# TPREFETCH + +## 指令示意图 + +![TPREFETCH tile operation](../figures/isa/TPREFETCH.svg) + +## 简介 + +将数据从全局内存预取到 Tile 本地缓存/缓冲区（提示）。 + +## 数学语义 + +除非另有说明, semantics are defined over the valid region and target-dependent behavior is marked as implementation-defined. + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS Specification](../assembly/PTO-AS.md). + +同步形式： + +```text +%dst = tprefetch %src : !pto.global<...> -> !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tprefetch %src : !pto.global<...> -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tprefetch ins(%src : !pto.global<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### AS Level 1（SSA） + +```text +%dst = pto.tprefetch %src : !pto.global<...> -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.tprefetch ins(%src : !pto.global<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TPREFETCH(TileData &dst, GlobalData &src); +``` + +## 约束 + +- Semantics and caching behavior are target/implementation-defined. +- Some targets may ignore prefetches or treat them as hints. + +## 示例 + +See related examples in `docs/isa/` and `docs/coding/tutorials/`. diff --git a/designs/outerCube/PTOISA/TPRELU.md b/designs/outerCube/PTOISA/TPRELU.md new file mode 100644 index 00000000..74c5ef05 --- /dev/null +++ b/designs/outerCube/PTOISA/TPRELU.md @@ -0,0 +1,106 @@ +# TPRELU + + +## Tile Operation Diagram + +![TPRELU tile operation](../figures/isa/TPRELU.svg) + +## Introduction + +Elementwise PReLU (parametric ReLU) with a per-element slope tile. + +## Math Interpretation + +For each element `(i, j)` in the valid region: + +$$ \mathrm{dst}_{i,j} = (\mathrm{src0}_{i,j} > 0) ? \mathrm{src0}_{i,j} : (\mathrm{src0}_{i,j} \cdot \mathrm{src1}_{i,j}) $$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = tprelu %src0, %src1 : !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tprelu %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tprelu ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### IR Level 1 (SSA) + +```text +%dst = pto.tprelu %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### IR Level 2 (DPS) + +```text +pto.tprelu ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TPRELU(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, TileDataTmp &tmp, WaitEvents &... events); +``` + +## Constraints + +- The op iterates over `dst.GetValidRow()` / `dst.GetValidCol()`. +- Temporary space is required by A3 for calculation, while not used by A5. +- For A3, 2 source Tile, destination Tile, temporary space must in different memory range without overlapping. + +## Examples + +```cpp +#include + +using namespace pto; + +void example() { + using TileT = Tile; + TileT x, slope, out, tmp; + TPRELU(out, x, slope, tmp); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.tprelu %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tprelu %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = tprelu %src0, %src1 : !pto.tile<...> +# AS Level 2 (DPS) +pto.tprelu ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TPRELU_zh.md b/designs/outerCube/PTOISA/TPRELU_zh.md new file mode 100644 index 00000000..1f5b2a8a --- /dev/null +++ b/designs/outerCube/PTOISA/TPRELU_zh.md @@ -0,0 +1,79 @@ +# TPRELU + +## 指令示意图 + +![TPRELU tile operation](../figures/isa/TPRELU.svg) + +## 简介 + +带逐元素斜率 Tile 的逐元素参数化 ReLU (PReLU)。 + +## 数学语义 + +对每个元素 `(i, j)` 在有效区域内： + +$$ \mathrm{dst}_{i,j} = (\mathrm{src0}_{i,j} > 0) ? \mathrm{src0}_{i,j} : (\mathrm{src0}_{i,j} \cdot \mathrm{src1}_{i,j}) $$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS Specification](../assembly/PTO-AS.md). + +同步形式： + +```text +%dst = tprelu %src0, %src1 : !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tprelu %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tprelu ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### AS Level 1（SSA） + +```text +%dst = pto.tprelu %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.tprelu ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TPRELU(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, TileDataTmp &tmp, WaitEvents &... events); +``` + +## 约束 + +- The op iterates over `dst.GetValidRow()` / `dst.GetValidCol()`. +- Temporary space is required by A3 for calculation, while not used by A5. +- For A3, 2 source Tile, destination Tile, temporary space must in different memory range without overlapping. + +## 示例 + +```cpp +#include + +using namespace pto; + +void example() { + using TileT = Tile; + TileT x, slope, out, tmp; + TPRELU(out, x, slope, tmp); +} +``` diff --git a/designs/outerCube/PTOISA/TPRINT.md b/designs/outerCube/PTOISA/TPRINT.md new file mode 100644 index 00000000..b92db8fe --- /dev/null +++ b/designs/outerCube/PTOISA/TPRINT.md @@ -0,0 +1,157 @@ +# TPRINT + + +## Tile Operation Diagram + +![TPRINT tile operation](../figures/isa/TPRINT.svg) + +## Introduction + +Print the contents of a Tile or GlobalTensor for debugging purposes directly from device code. + +The `TPRINT` instruction outputs the logical view of data stored in a Tile or GlobalTensor. It supports common data types (e.g., `float`, `half`, `int8`, `uint32`) and multiple memory layouts (`ND`, `DN`, `NZ` for GlobalTensor; vector tiles for on-chip buffers). + +> **Important**: +> - This instruction is **for development and debugging ONLY**. +> - It incurs **significant runtime overhead** and **must not be used in production kernels**. +> - Output may be **truncated** if it exceeds the internal print buffer. +> - **Requires CCE compilation option `-D_DEBUG --cce-enable-print`** (see [Behavior](#behavior)). + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +```text +tprint %src : !pto.tile<...> | !pto.global<...> +``` + +### AS Level 1 (SSA) + +```text +pto.tprint %src : !pto.tile<...> | !pto.partition_tensor_view -> () +``` + +### AS Level 2 (DPS) + +```text +pto.tprint ins(%src : !pto.tile_buf<...> | !pto.partition_tensor_view) +``` + +### IR Level 1 (SSA) + +```text +pto.tprint %src : !pto.tile<...> | !pto.partition_tensor_view -> () +``` + +### IR Level 2 (DPS) + +```text +pto.tprint ins(%src : !pto.tile_buf<...> | !pto.partition_tensor_view) +``` +## C++ Intrinsic +Declared in `include/pto/common/pto_instr.hpp`: +```cpp +template +PTO_INST RecordEvent TPRINT(TileData &src, WaitEvents &... events); +``` + +### Supported Types for T +- **Tile**: Must be a vector tile (`TileType::Vec`) with supported element type. +- **GlobalTensor**: Must use layout `ND`, `DN`, or `NZ`, and have a supported element type. + +## Constraints + +- **Supported element type**: + - Floating-point: `float`, `half` + - Signed integers: `int8_t`, `int16_t`, `int32_t` + - Unsigned integers: `uint8_t`, `uint16_t`, `uint32_t` +- **For Tiles**: `TileData::Loc == TileType::Vec` (only vector tiles are printable). +- **For GlobalTensor**: Layout must be one of `Layout::ND`, `Layout::DN`, or `Layout::NZ`. + +## Behavior +- **Mandatory Compilation Flag**: + + On A2/A3/A5 devices, `TPRINT` uses `cce::printf` to emit output via the device-to-host debug channel. **You must enable the CCE option `-D_DEBUG --cce-enable-print`**. + +- **Buffer Limitation:** + + The internal print buffer of `cce::printf` is limited in size. If the output exceeds this buffer, a warning message such as `"Warning: out of bound! try best to print"` may appear, and **only partial data will be printed**. + +- **Synchronization**: + + Automatically inserts a `pipe_barrier(PIPE_ALL)` before printing to ensure all prior operations complete and data is consistent. + +- **Formatting**: + + - Floating-point values: printed as `%6.2f` + - Integer values: printed as `%6d` + - For `GlobalTensor`, due to data size and buffer limitations, only elements within its logical shape (defined by `Shape`) are printed. + - For `Tile`, invalid regions (beyond `validRows`/`validCols`) are still printed but marked with a `|` separator when partial validity is specified. + +## Examples + +### Print a Tile + +```cpp +#include + +PTO_INTERNAL void DebugTile(__gm__ float *src) { + using ValidSrcShape = TileShape2D; + using NDSrcShape = BaseShape2D; + using GlobalDataSrc = GlobalTensor; + GlobalDataSrc srcGlobal(src); + + using srcTileData = Tile; + srcTileData srcTile; + TASSIGN(srcTile, 0x0); + + TLOAD(srcTile, srcGlobal); + TPRINT(srcTile); +} +``` + +### Print a GlobalTensor + +```cpp +#include + +PTO_INTERNAL void DebugGlobalTensor(__gm__ float *src) { + using ValidSrcShape = TileShape2D; + using NDSrcShape = BaseShape2D; + using GlobalDataSrc = GlobalTensor; + GlobalDataSrc srcGlobal(src); + + TPRINT(srcGlobal); +} +``` + +## Math Interpretation + +Unless otherwise specified, semantics are defined over the valid region and target-dependent behavior is marked as implementation-defined. + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +pto.tprint %src : !pto.tile<...> | !pto.partition_tensor_view -> () +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +pto.tprint %src : !pto.tile<...> | !pto.partition_tensor_view -> () +``` + +### PTO Assembly Form + +```text +pto.tprint %src : !pto.tile<...> | !pto.partition_tensor_view -> () +# AS Level 2 (DPS) +pto.tprint ins(%src : !pto.tile_buf<...> | !pto.partition_tensor_view) +``` diff --git a/designs/outerCube/PTOISA/TPRINT_zh.md b/designs/outerCube/PTOISA/TPRINT_zh.md new file mode 100644 index 00000000..1dbacc50 --- /dev/null +++ b/designs/outerCube/PTOISA/TPRINT_zh.md @@ -0,0 +1,113 @@ +# TPRINT + +## 指令示意图 + +![TPRINT tile operation](../figures/isa/TPRINT.svg) + +## 简介 + +调试/打印 Tile 中的元素（实现定义）。 + +Print the contents of a Tile or GlobalTensor for debugging purposes directly from device code. + +The `TPRINT` instruction outputs the logical view of data stored in a Tile or GlobalTensor. It supports common data types (e.g., `float`, `half`, `int8`, `uint32`) and multiple memory layouts (`ND`, `DN`, `NZ` for GlobalTensor; vector tiles for on-chip buffers). + +> **Important**: +> - This instruction is **for development and debugging ONLY**. +> - It incurs **significant runtime overhead** and **must not be used in production kernels**. +> - Output may be **truncated** if it exceeds the internal print buffer. +> - **Requires CCE compilation option `-D_DEBUG --cce-enable-print`** (see [Behavior](#behavior)). + +## 数学语义 + +除非另有说明, semantics are defined over the valid region and target-dependent behavior is marked as implementation-defined. + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS Specification](../assembly/PTO-AS.md). + +```text +tprint %src : !pto.tile<...> | !pto.global<...> +``` + +### AS Level 1 (SSA) + +```text +pto.tprint %src : !pto.tile<...> | !pto.partition_tensor_view -> () +``` + +### AS Level 2 (DPS) + +```text +pto.tprint ins(%src : !pto.tile_buf<...> | !pto.partition_tensor_view) +``` + +### AS Level 1（SSA） + +```text +pto.tprint %src : !pto.tile<...> | !pto.partition_tensor_view -> () +``` + +### AS Level 2（DPS） + +```text +pto.tprint ins(%src : !pto.tile_buf<...> | !pto.partition_tensor_view) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`: +```cpp +template +PTO_INST RecordEvent TPRINT(TileData &src, WaitEvents &... events); +``` + +### Supported Types for T +- **Tile**: Must be a vector tile (`TileType::Vec`) with supported element type. +- **GlobalTensor**: Must use layout `ND`, `DN`, or `NZ`, and have a supported element type. + +## 约束 + +- **Supported element type**: + - Floating-point: `float`, `half` + - Signed integers: `int8_t`, `int16_t`, `int32_t` + - Unsigned integers: `uint8_t`, `uint16_t`, `uint32_t` +- **For Tiles**: `TileData::Loc == TileType::Vec` (only vector tiles are printable). +- **For GlobalTensor**: Layout must be one of `Layout::ND`, `Layout::DN`, or `Layout::NZ`. + +## 示例 + +### Print a Tile + +```cpp +#include + +PTO_INTERNAL void DebugTile(__gm__ float *src) { + using ValidSrcShape = TileShape2D; + using NDSrcShape = BaseShape2D; + using GlobalDataSrc = GlobalTensor; + GlobalDataSrc srcGlobal(src); + + using srcTileData = Tile; + srcTileData srcTile; + TASSIGN(srcTile, 0x0); + + TLOAD(srcTile, srcGlobal); + TPRINT(srcTile); +} +``` + +### Print a GlobalTensor + +```cpp +#include + +PTO_INTERNAL void DebugGlobalTensor(__gm__ float *src) { + using ValidSrcShape = TileShape2D; + using NDSrcShape = BaseShape2D; + using GlobalDataSrc = GlobalTensor; + GlobalDataSrc srcGlobal(src); + + TPRINT(srcGlobal); +} +``` diff --git a/designs/outerCube/PTOISA/TPUSH.md b/designs/outerCube/PTOISA/TPUSH.md new file mode 100644 index 00000000..1a1b8c4c --- /dev/null +++ b/designs/outerCube/PTOISA/TPUSH.md @@ -0,0 +1,40 @@ +# TPUSH + +## Tile Operation Diagram + +![TPUSH tile operation](../figures/isa/TPUSH.svg) + +## Introduction + +Push a tile into a pipe or FIFO producer endpoint. + +## Math Interpretation + +Semantics are instruction-specific. Unless stated otherwise, behavior is defined over the destination valid region. + +## Assembly Syntax + +PTO-AS form: see `docs/assembly/PTO-AS.md`. + +### IR Level 1 (SSA) + +```text +%dst = pto.tpush ... +``` + +### IR Level 2 (DPS) + +```text +pto.tpush ins(...) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`. + +## Constraints + +Refer to backend-specific legality checks for data type/layout/location/shape constraints. + +## Examples + +See related instruction pages in `docs/isa/` for concrete Auto/Manual usage patterns. diff --git a/designs/outerCube/PTOISA/TPUSH_zh.md b/designs/outerCube/PTOISA/TPUSH_zh.md new file mode 100644 index 00000000..f6ebfadc --- /dev/null +++ b/designs/outerCube/PTOISA/TPUSH_zh.md @@ -0,0 +1,41 @@ +# TPUSH + +## 指令示意图 + +![TPUSH tile operation](../figures/isa/TPUSH.svg) + +## 简介 + +将 Tile 推入 pipe 或 FIFO 的生产者端。 + +## 数学语义 + +语义随指令而变化。 Unless stated otherwise, behavior is defined over the destination valid region. + +## 汇编语法 + +PTO-AS 形式：参见 `docs/assembly/PTO-AS.md`. + +### AS Level 1（SSA） + +```text +%dst = pto.tpush ... +``` + +### AS Level 2（DPS） + +```text +pto.tpush ins(...) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`. + +## 约束 + +Refer to backend-specific legality checks for data type/layout/location/shape constraints. + +## 示例 + +See related instruction pages in `docs/isa/` for concrete Auto/Manual usage patterns. diff --git a/designs/outerCube/PTOISA/TQUANT.md b/designs/outerCube/PTOISA/TQUANT.md new file mode 100644 index 00000000..945abb5e --- /dev/null +++ b/designs/outerCube/PTOISA/TQUANT.md @@ -0,0 +1,94 @@ +# TQUANT + + +## Tile Operation Diagram + +![TQUANT tile operation](../figures/isa/TQUANT.svg) + +## Introduction + +Quantize an FP32 tile into a lower-precision format (e.g. FP8), producing auxiliary exponent/scaling/max tiles. The quantization mode is a compile-time template parameter (`mode`). + +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TQUANT(TileDataOut &dst, TileDataSrc &src, TileDataExp *exp, TileDataMax *max, TileDataSrc *scaling, WaitEvents &... events); + +template +PTO_INST RecordEvent TQUANT(TileDataOut &dst, TileDataSrc &src, TileDataExp *exp, TileDataMax *max, TileDataSrc *scaling, TileDataExp *exp_zz, TileDataIdx *vgather_idx, WaitEvents &... events); + +template +PTO_INST RecordEvent TQUANT(TileDataOut &dst, TileDataSrc &src, TileDataPara &scale, TileDataPara *offset = nullptr, WaitEvents &... events); +``` + +## Constraints + +- This instruction is currently implemented for specific targets (see `include/pto/npu/*/TQuant.hpp`). +- Input type requirements and output tile types are mode/target-dependent. + +## Math Interpretation + +Unless otherwise specified, semantics are defined over the valid region and target-dependent behavior is marked as implementation-defined. + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +### AS Level 1 (SSA) + +```text +%dst = pto.tquant %src, %qp : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tquant ins(%src, %qp : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### IR Level 1 (SSA) + +```text +%dst = pto.tquant %src, %qp : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### IR Level 2 (DPS) + +```text +pto.tquant ins(%src, %qp : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## Examples + +See related examples in `docs/isa/` and `docs/coding/tutorials/`. + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.tquant %src, %qp : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tquant %src, %qp : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = pto.tquant %src, %qp : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +# AS Level 2 (DPS) +pto.tquant ins(%src, %qp : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TQUANT_zh.md b/designs/outerCube/PTOISA/TQUANT_zh.md new file mode 100644 index 00000000..85d6d359 --- /dev/null +++ b/designs/outerCube/PTOISA/TQUANT_zh.md @@ -0,0 +1,67 @@ +# TQUANT + +## 指令示意图 + +![TQUANT tile operation](../figures/isa/TQUANT.svg) + +## 简介 + +量化 Tile（例如 FP32 到 FP8），生成指数/缩放/最大值输出。 + +## 数学语义 + +除非另有说明, semantics are defined over the valid region and target-dependent behavior is marked as implementation-defined. + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS Specification](../assembly/PTO-AS.md). + +### AS Level 1 (SSA) + +```text +%dst = pto.tquant %src, %qp : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tquant ins(%src, %qp : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### AS Level 1（SSA） + +```text +%dst = pto.tquant %src, %qp : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.tquant ins(%src, %qp : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TQUANT(TileDataOut &dst, TileDataSrc &src, TileDataExp *exp, TileDataMax *max, TileDataSrc *scaling, WaitEvents &... events); + +template +PTO_INST RecordEvent TQUANT(TileDataOut &dst, TileDataSrc &src, TileDataExp *exp, TileDataMax *max, TileDataSrc *scaling, TileDataExp *exp_zz, TileDataIdx *vgather_idx, WaitEvents &... events); + +template +PTO_INST RecordEvent TQUANT(TileDataOut &dst, TileDataSrc &src, TileDataPara &scale, TileDataPara *offset = nullptr, WaitEvents &... events); +``` + +## 约束 + +- This instruction is currently implemented for specific targets (see `include/pto/npu/*/TQuant.hpp`). +- Input type requirements and output tile types are mode/target-dependent. + +## 示例 + +See related examples in `docs/isa/` and `docs/coding/tutorials/`. diff --git a/designs/outerCube/PTOISA/TRANDOM.md b/designs/outerCube/PTOISA/TRANDOM.md new file mode 100644 index 00000000..f7aa18a6 --- /dev/null +++ b/designs/outerCube/PTOISA/TRANDOM.md @@ -0,0 +1,122 @@ +# TRANDOM + +## Tile Operation Diagram + +![TRANDOM tile operation](../figures/isa/TRANDOM.svg) + +## Introduction + +Generates random numbers in the destination tile using a counter-based cipher algorithm. + +## Math Interpretation + +This instruction implements a counter-based random number generator. For each element in the valid region, it generates +pseudo-random values based on a key and counter state using a cipher-like transformation with configurable rounds. + +The algorithm uses: + +- 128-bit state (4 × 32-bit counters) +- 64-bit key (2 × 32-bit words) +- ChaCha-like quarter-round operations with vector instructions + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +trandom %dst, %key, %counter : !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.trandom %key, %counter : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.trandom ins(%key, %counter : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ Intrinsic + +Declared in `include/pto/npu/a5/TRandom.hpp`: + +```cpp +template +PTO_INST void TRANDOM_IMPL(DstTile &dst, TRandomKey &key, TRandomCounter &counter); +``` + +## Constraints + +- **Implementation checks (A5)**: + - `DstTile::DType` must be one of: `int32_t`, `uint32_t`. + - Tile layout must be row-major (`DstTile::isRowMajor`). + - `Rounds` must be either 7 or 10 (default: 10). + - `key` and `counter` must not be null. +- **Valid region**: + - The op uses `dst.GetValidRow()` / `dst.GetValidCol()` as the iteration domain. + +## Examples + +### Auto + +```cpp +#include + +using namespace pto; + +void example_auto() { + using TileT = Tile; + TileT dst; + TRandomKey key = {0x01234, 0x56789}; + TRandomCounter counter = {0, 0, 0, 0}; + TRANDOM_IMPL(dst, key, counter); +} +``` + +### Manual + +```cpp +#include + +using namespace pto; + +void example_manual() { + using TileT = Tile; + TileT dst; + TRandomKey key = {0x01234, 0x56789}; + TRandomCounter counter = {0, 0, 0, 0}; + TASSIGN(dst, 0x0); + TRANDOM_IMPL<10>(dst, key, counter); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.trandom %key, %counter : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x3000) +%dst = pto.trandom %key, %counter : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +trandom %dst, %key, %counter : !pto.tile<...> +# AS Level 2 (DPS) +pto.trandom ins(%key, %counter : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TRANDOM_zh.md b/designs/outerCube/PTOISA/TRANDOM_zh.md new file mode 100644 index 00000000..d6dfc933 --- /dev/null +++ b/designs/outerCube/PTOISA/TRANDOM_zh.md @@ -0,0 +1,122 @@ +# TRANDOM + +## Tile Operation Diagram + +![TRANDOM tile operation](../figures/isa/TRANDOM.svg) + +## 简介 + +使用基于计数器的密码算法在目标 Tile 中生成随机数。 + +## 数学解释 + +该指令实现了一个基于计数器的随机数生成器。对于有效区域中的每个元素，它基于密钥和计数器状态，使用可配置轮数的密码类变换生成 +伪随机值。 + +该算法使用： + +- 128 位状态（4 × 32 位计数器） +- 64 位密钥（2 × 32 位字） +- 类似 ChaCha 的四分之一轮操作，使用向量指令 + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS 规范](../assembly/PTO-AS.md)。 + +同步形式： + +```text +trandom %dst, %key, %counter : !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.trandom %key, %counter : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.trandom ins(%key, %counter : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内置函数 + +声明于 `include/pto/npu/a5/TRandom.hpp`： + +```cpp +template +PTO_INST void TRANDOM_IMPL(DstTile &dst, TRandomKey &key, TRandomCounter &counter); +``` + +## 约束条件 + +- **实现检查（A5）**： + - `DstTile::DType` 必须为以下类型之一：`int32_t`、`uint32_t`。 + - Tile 布局必须为行主序（`DstTile::isRowMajor`）。 + - `Rounds` 必须为 7 或 10（默认为 10）。 + - `key` 和 `counter` 不能为空。 +- **有效区域**： + - 该操作使用 `dst.GetValidRow()` / `dst.GetValidCol()` 作为迭代域。 + +## 示例 + +### Auto 模式 + +```cpp +#include + +using namespace pto; + +void example_auto() { + using TileT = Tile; + TileT dst; + TRandomKey key = {0x01234, 0x56789}; + TRandomCounter counter = {0, 0, 0, 0}; + TRANDOM_IMPL(dst, key, counter); +} +``` + +### Manual 模式 + +```cpp +#include + +using namespace pto; + +void example_manual() { + using TileT = Tile; + TileT dst; + TRandomKey key = {0x01234, 0x56789}; + TRandomCounter counter = {0, 0, 0, 0}; + TASSIGN(dst, 0x0); + TRANDOM_IMPL<10>(dst, key, counter); +} +``` + +## 汇编形式示例 + +### Auto 模式 + +```text +# Auto 模式：编译器/运行时管理的布局和调度。 +%dst = pto.trandom %key, %counter : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### Manual 模式 + +```text +# Manual 模式：在发出指令之前显式绑定资源。 +# Tile 操作数可选： +# pto.tassign %arg0, @tile(0x3000) +%dst = pto.trandom %key, %counter : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### PTO 汇编形式 + +```text +trandom %dst, %key, %counter : !pto.tile<...> +# AS Level 2 (DPS) +pto.trandom ins(%key, %counter : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TRECIP.md b/designs/outerCube/PTOISA/TRECIP.md new file mode 100644 index 00000000..4b592b63 --- /dev/null +++ b/designs/outerCube/PTOISA/TRECIP.md @@ -0,0 +1,113 @@ +# TRECIP + + +## Tile Operation Diagram + +![TRECIP tile operation](../figures/isa/TRECIP.svg) + +## Introduction + +Elementwise reciprocal of a tile. + +## Math Interpretation + +For each element `(i, j)` in the valid region: + +$$ \mathrm{dst}_{i,j} = \frac{1}{\mathrm{src}_{i,j}} $$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = trecip %src : !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.trecip %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.trecip ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### IR Level 1 (SSA) + +```text +%dst = pto.trecip %src : !pto.tile<...> -> !pto.tile<...> +``` + +### IR Level 2 (DPS) + +```text +pto.trecip ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TRECIP(TileDataDst &dst, TileDataSrc &src, WaitEvents &... events); +``` + +## Constraints + +- **Implementation checks (NPU)**: + - `TileData::DType` must be one of: `float` or `half`; + - Tile location must be vector (`TileData::Loc == TileType::Vec`); + - Static valid bounds: `TileData::ValidRow <= TileData::Rows` and `TileData::ValidCol <= TileData::Cols`; + - Runtime: `src.GetValidRow() == dst.GetValidRow()` and `src.GetValidCol() == dst.GetValidCol()`; + - Tile layout must be row-major (`TileData::isRowMajor`). + - A3's TRECIP instruction does not support setting the source Tile and destination Tile to the same memory. +- **Valid region**: + - The op uses `dst.GetValidRow()` / `dst.GetValidCol()` as the iteration domain. +- **Domain / NaN**: + - Division-by-zero behavior is target-defined; the CPU simulator asserts in debug builds. + +## Examples + +```cpp +#include + +using namespace pto; + +void example() { + using TileT = Tile; + TileT x, out; + TRECIP(out, x); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.trecip %src : !pto.tile<...> -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.trecip %src : !pto.tile<...> -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = trecip %src : !pto.tile<...> +# AS Level 2 (DPS) +pto.trecip ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TRECIP_zh.md b/designs/outerCube/PTOISA/TRECIP_zh.md new file mode 100644 index 00000000..f93f9086 --- /dev/null +++ b/designs/outerCube/PTOISA/TRECIP_zh.md @@ -0,0 +1,86 @@ +# TRECIP + +## 指令示意图 + +![TRECIP tile operation](../figures/isa/TRECIP.svg) + +## 简介 + +Tile 的逐元素倒数。 + +## 数学语义 + +对每个元素 `(i, j)` 在有效区域内： + +$$ \mathrm{dst}_{i,j} = \frac{1}{\mathrm{src}_{i,j}} $$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS Specification](../assembly/PTO-AS.md). + +同步形式： + +```text +%dst = trecip %src : !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.trecip %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.trecip ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### AS Level 1（SSA） + +```text +%dst = pto.trecip %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.trecip ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TRECIP(TileDataDst &dst, TileDataSrc &src, WaitEvents &... events); +``` + +## 约束 + +- **实现检查 (NPU)**: + - `TileData::DType` must be one of: `float` or `half`; + - Tile location must be vector (`TileData::Loc == TileType::Vec`); + - Static valid bounds: `TileData::ValidRow <= TileData::Rows` and `TileData::ValidCol <= TileData::Cols`; + - Runtime: `src.GetValidRow() == dst.GetValidRow()` and `src.GetValidCol() == dst.GetValidCol()`; + - Tile 布局 must be row-major (`TileData::isRowMajor`). + - A3's TRECIP instruction does not support setting the source Tile and destination Tile to the same memory. +- **有效区域**: + - The op uses `dst.GetValidRow()` / `dst.GetValidCol()` as the iteration domain. +- **Domain / NaN**: + - Division-by-zero behavior is target-defined; the CPU simulator asserts in debug builds. + +## 示例 + +```cpp +#include + +using namespace pto; + +void example() { + using TileT = Tile; + TileT x, out; + TRECIP(out, x); +} +``` diff --git a/designs/outerCube/PTOISA/TRELU.md b/designs/outerCube/PTOISA/TRELU.md new file mode 100644 index 00000000..0a85211e --- /dev/null +++ b/designs/outerCube/PTOISA/TRELU.md @@ -0,0 +1,116 @@ +# TRELU + + +## Tile Operation Diagram + +![TRELU tile operation](../figures/isa/TRELU.svg) + +## Introduction + +Elementwise ReLU of a tile. + +## Math Interpretation + +For each element `(i, j)` in the valid region: + +$$ \mathrm{dst}_{i,j} = \max(\mathrm{src}_{i,j}, 0) $$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = trelu %src : !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.trelu %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.trelu ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### IR Level 1 (SSA) + +```text +%dst = pto.trelu %src : !pto.tile<...> -> !pto.tile<...> +``` + +### IR Level 2 (DPS) + +```text +pto.trelu ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TRELU(TileDataDst &dst, TileDataSrc &src, WaitEvents &... events); +``` + +## Constraints + +- **Implementation checks (A2A3)**: + - `TileData::DType` must be one of: `half`, `float`, `int32_t`. + - Tile layout must be row-major (`TileData::isRowMajor`). + - Tile location must be vector (`TileData::Loc == TileType::Vec`). + - Static valid bounds: `TileData::ValidRow <= TileData::Rows` and `TileData::ValidCol <= TileData::Cols`. + - Runtime: `src` and `dst` tiles should have the same `validRow/validCol`. +- **Implementation checks (A5)**: + - `TileData::DType` must be one of: `half`, `float`, `int32_t`. + - Tile layout must be row-major (`TileData::isRowMajor`). + - Tile location must be vector (`TileData::Loc == TileType::Vec`). + - Static valid bounds: `TileData::ValidRow <= TileData::Rows` and `TileData::ValidCol <= TileData::Cols`. + - Runtime: `src` and `dst` tiles should have the same `validRow/validCol`. +- **Valid region**: + - The op uses `dst.GetValidRow()` / `dst.GetValidCol()` as the iteration domain; `src/dst` are assumed to be compatible (not validated by explicit runtime checks in this op). + +## Examples + +```cpp +#include + +using namespace pto; + +void example() { + using TileT = Tile; + TileT x, out; + TRELU(out, x); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.trelu %src : !pto.tile<...> -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.trelu %src : !pto.tile<...> -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = trelu %src : !pto.tile<...> +# AS Level 2 (DPS) +pto.trelu ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TRELU_zh.md b/designs/outerCube/PTOISA/TRELU_zh.md new file mode 100644 index 00000000..7024ffd7 --- /dev/null +++ b/designs/outerCube/PTOISA/TRELU_zh.md @@ -0,0 +1,89 @@ +# TRELU + +## 指令示意图 + +![TRELU tile operation](../figures/isa/TRELU.svg) + +## 简介 + +Tile 的逐元素 ReLU。 + +## 数学语义 + +对每个元素 `(i, j)` 在有效区域内： + +$$ \mathrm{dst}_{i,j} = \max(\mathrm{src}_{i,j}, 0) $$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS Specification](../assembly/PTO-AS.md). + +同步形式： + +```text +%dst = trelu %src : !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.trelu %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.trelu ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### AS Level 1（SSA） + +```text +%dst = pto.trelu %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.trelu ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TRELU(TileDataDst &dst, TileDataSrc &src, WaitEvents &... events); +``` + +## 约束 + +- **实现检查 (A2A3)**: + - `TileData::DType` must be one of: `half`, `float`, `int32_t`. + - Tile 布局 must be row-major (`TileData::isRowMajor`). + - Tile location must be vector (`TileData::Loc == TileType::Vec`). + - Static valid bounds: `TileData::ValidRow <= TileData::Rows` and `TileData::ValidCol <= TileData::Cols`. + - Runtime: `src` and `dst` tiles should have the same `validRow/validCol`. +- **实现检查 (A5)**: + - `TileData::DType` must be one of: `half`, `float`, `int32_t`. + - Tile 布局 must be row-major (`TileData::isRowMajor`). + - Tile location must be vector (`TileData::Loc == TileType::Vec`). + - Static valid bounds: `TileData::ValidRow <= TileData::Rows` and `TileData::ValidCol <= TileData::Cols`. + - Runtime: `src` and `dst` tiles should have the same `validRow/validCol`. +- **有效区域**: + - The op uses `dst.GetValidRow()` / `dst.GetValidCol()` as the iteration domain; `src/dst` are assumed to be compatible (not validated by explicit runtime checks in this op). + +## 示例 + +```cpp +#include + +using namespace pto; + +void example() { + using TileT = Tile; + TileT x, out; + TRELU(out, x); +} +``` diff --git a/designs/outerCube/PTOISA/TREM.md b/designs/outerCube/PTOISA/TREM.md new file mode 100644 index 00000000..88968044 --- /dev/null +++ b/designs/outerCube/PTOISA/TREM.md @@ -0,0 +1,115 @@ +# TREM + + +## Tile Operation Diagram + +![TREM tile operation](../figures/isa/TREM.svg) + +## Introduction + +Elementwise remainder of two tiles. The result has the same sign as the divider. + +## Math Interpretation + +For each element `(i, j)` in the valid region: + +$$\mathrm{dst}_{i,j} = \mathrm{src0}_{i,j} \bmod \mathrm{src1}_{i,j}$$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = trem %src0, %src1 : !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.trem %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.trem ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TREM(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, TileDataTmp &tmp, WaitEvents &... events); +``` + +## Constraints + +- **Implementation Checks (A2A3)**: + - `dst`, `src0`, and `src1` must use the same element type. + - Supported element types: `float` and `int32_t`. + - `dst`, `src0`, and `src1` must be vector tiles. + - `dst`, `src0`, and `src1` must be row-major. + - Runtime: `dst.GetValidRow() == src0.GetValidRow() == src1.GetValidRow() > 0` and `dst.GetValidCol() == src0.GetValidCol() == src1.GetValidCol() > 0`. + - **tmp Buffer Requirements**: + - `tmp.GetValidCol() >= dst.GetValidCol()` (at least as many columns as dst) + - `tmp.GetValidRow() >= 1` (at least 1 row) + - Data type must match `TileDataDst::DType`. +- **Implementation Checks (A5)**: + - `dst`, `src0`, and `src1` must use the same element type. + - Supported element types: `float`, `int32_t`, `uint32_t`, `half`, `int16_t`, and `uint16_t`. + - `dst`, `src0`, and `src1` must be vector tiles. + - Static valid bounds: `ValidRow <= Rows` and `ValidCol <= Cols` for all tiles. + - Runtime: `dst.GetValidRow() == src0.GetValidRow() == src1.GetValidRow()` and `dst.GetValidCol() == src0.GetValidCol() == src1.GetValidCol()`. + - Note: tmp parameter is accepted but not validated or used on A5. +- **Division by Zero**: + - Behavior is target-defined; the CPU simulator asserts in debug builds. +- **Valid Region**: + - The op uses `dst.GetValidRow()` / `dst.GetValidCol()` as the iteration domain. +- **For `int32_t` Inputs (A2A3 Only)**: Both `src0` and `src1` elements must be in the range `[-2^24, 2^24]` (i.e., `[-16777216, 16777216]`) to ensure exact conversion to float32 during computation. + +## Examples + +```cpp +#include + +using namespace pto; + +void example() { + using TileT = Tile; + TileT out, a, b; + Tile tmp; + TREM(out, a, b, tmp); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.trem %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.trem %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = trem %src0, %src1 : !pto.tile<...> +# AS Level 2 (DPS) +pto.trem ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/TREMS.md b/designs/outerCube/PTOISA/TREMS.md new file mode 100644 index 00000000..03c323be --- /dev/null +++ b/designs/outerCube/PTOISA/TREMS.md @@ -0,0 +1,115 @@ +# TREMS + + +## Tile Operation Diagram + +![TREMS tile operation](../figures/isa/TREMS.svg) + +## Introduction + +Elementwise remainder with a scalar: `%`. + +## Math Interpretation + +For each element `(i, j)` in the valid region: + +$$\mathrm{dst}_{i,j} = \mathrm{src}_{i,j} \bmod \mathrm{scalar}$$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = trems %src, %scalar : !pto.tile<...>, f32 +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.trems %src, %scalar : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.trems ins(%src, %scalar : !pto.tile_buf<...>, dtype) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TREMS(TileDataDst &dst, TileDataSrc &src, typename TileDataSrc::DType scalar, + TileDataTmp &tmp, WaitEvents &... events); +``` + +## Constraints + +- **Implementation Checks (A2A3)**: + - `dst` and `src` must use the same element type. + - Supported element types: `float` and `int32_t`. + - `dst` and `src` must be vector tiles. + - `dst` and `src` must be row-major. + - Runtime: `dst.GetValidRow() == src.GetValidRow() > 0` and `dst.GetValidCol() == src.GetValidCol() > 0`. + - **tmp Buffer Requirements**: + - `tmp.GetValidCol() >= dst.GetValidCol()` (at least as many columns as dst) + - `tmp.GetValidRow() >= 1` (at least 1 row) + - Data type must match `TileDataDst::DType`. +- **Implementation Checks (A5)**: + - `dst` and `src` must use the same element type. + - Supported element types: `float`, `int32_t`, `uint32_t`, `half`, `int16_t`, and `uint16_t`. + - `dst` and `src` must be vector tiles. + - Static valid bounds: `ValidRow <= Rows` and `ValidCol <= Cols` for both tiles. + - Runtime: `dst.GetValidRow() == src.GetValidRow()` and `dst.GetValidCol() == src.GetValidCol()`. + - Note: tmp parameter is accepted but not validated or used on A5. +- **Division by Zero**: + - Behavior is target-defined; the CPU simulator asserts in debug builds. +- **Valid Region**: + - The op uses `dst.GetValidRow()` / `dst.GetValidCol()` as the iteration domain. +- **For `int32_t` Inputs (A2A3 Only)**: Both `src` elements and `scalar` must be in the range `[-2^24, 2^24]` (i.e., `[-16777216, 16777216]`) to ensure exact conversion to float32 during computation. + +## Examples + +```cpp +#include + +using namespace pto; + +void example() { + using TileT = Tile; + TileT x, out; + Tile tmp; + TREMS(out, x, 3.0f, tmp); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.trems %src, %scalar : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.trems %src, %scalar : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = trems %src, %scalar : !pto.tile<...>, f32 +# AS Level 2 (DPS) +pto.trems ins(%src, %scalar : !pto.tile_buf<...>, dtype) outs(%dst : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/TREMS_zh.md b/designs/outerCube/PTOISA/TREMS_zh.md new file mode 100644 index 00000000..b3e3bb51 --- /dev/null +++ b/designs/outerCube/PTOISA/TREMS_zh.md @@ -0,0 +1,115 @@ +# TREMS + +## 指令示意图 + +![TREMS tile operation](../figures/isa/TREMS.svg) + +## 简介 + +与标量的逐元素余数：`remainder(src, scalar)`。 + +## 数学语义 + +对每个元素 `(i, j)` 在有效区域内： + +$$\mathrm{dst}_{i,j} = \mathrm{src}_{i,j} \bmod \mathrm{scalar}$$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS 规范](../assembly/PTO-AS_zh.md)。 + +同步形式： + +```text +%dst = trems %src, %scalar : !pto.tile<...>, f32 +``` + +### AS Level 1（SSA） + +```text +%dst = pto.trems %src, %scalar : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.trems ins(%src, %scalar : !pto.tile_buf<...>, dtype) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`： + +```cpp +template +PTO_INST RecordEvent TREMS(TileDataDst &dst, TileDataSrc &src, typename TileDataSrc::DType scalar, + TileDataTmp &tmp, WaitEvents &... events); +``` + +## 约束 + +- **实现检查 (A2A3)**: + - `dst` 和 `src` 必须使用相同的元素类型。 + - 支持的元素类型：`float` 和 `int32_t`。 + - `dst` 和 `src` 必须是向量 Tile。 + - `dst` 和 `src` 必须是行主序。 + - 运行时：`dst.GetValidRow() == src.GetValidRow() > 0` 且 `dst.GetValidCol() == src.GetValidCol() > 0`。 + - **tmp 缓冲区要求**： + - `tmp.GetValidCol() >= dst.GetValidCol()`（至少与 dst 相同的列数） + - `tmp.GetValidRow() >= 1`（至少 1 行） + - 数据类型必须与 `TileDataDst::DType` 匹配。 +- **实现检查 (A5)**: + - `dst` 和 `src` 必须使用相同的元素类型。 + - 支持的元素类型：`float`、`int32_t`、`uint32_t`、`half`、`int16_t` 和 `uint16_t`。 + - `dst` 和 `src` 必须是向量 Tile。 + - 两个 Tile 的静态有效边界都必须满足 `ValidRow <= Rows` 且 `ValidCol <= Cols`。 + - 运行时：`dst.GetValidRow() == src.GetValidRow()` 且 `dst.GetValidCol() == src.GetValidCol()`。 + - 注意：tmp 参数在 A5 上被接受但不进行验证或使用。 +- **除零**: + - 行为由目标定义；CPU 模拟器在调试构建中会断言。 +- **有效区域**: + - 该操作使用 `dst.GetValidRow()` / `dst.GetValidCol()` 作为迭代域。 +- **对于 `int32_t` 输入（仅 A2A3）**：`src` 的元素和 `scalar` 必须在 `[-2^24, 2^24]` 范围内（即 `[-16777216, 16777216]`），以确保在计算过程中能精确转换为 float32。 + +## 示例 + +```cpp +#include + +using namespace pto; + +void example() { + using TileT = Tile; + TileT x, out; + Tile tmp; + TREMS(out, x, 3.0f, tmp); +} +``` + +## 汇编示例（ASM） + +### 自动模式 + +```text +# 自动模式：由编译器/运行时负责资源放置与调度。 +%dst = pto.trems %src, %scalar : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### 手动模式 + +```text +# 手动模式：先显式绑定资源，再发射指令。 +# 可选（当该指令包含 tile 操作数时）： +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.trems %src, %scalar : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### PTO 汇编形式 + +```text +%dst = trems %src, %scalar : !pto.tile<...>, f32 +# AS Level 2 (DPS) +pto.trems ins(%src, %scalar : !pto.tile_buf<...>, dtype) outs(%dst : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/TREM_zh.md b/designs/outerCube/PTOISA/TREM_zh.md new file mode 100644 index 00000000..5011131c --- /dev/null +++ b/designs/outerCube/PTOISA/TREM_zh.md @@ -0,0 +1,113 @@ +# TREM + +## 指令示意图 + +![TREM tile operation](../figures/isa/TREM.svg) + +## 简介 + +两个 Tile 的逐元素余数运算。结果符号与除数相同。 + +## 数学语义 + +对每个元素 `(i, j)` 在有效区域内： + +$$\mathrm{dst}_{i,j} = \mathrm{src0}_{i,j} \bmod \mathrm{src1}_{i,j}$$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS 规范](../assembly/PTO-AS_zh.md)。 + +同步形式： + +```text +%dst = trem %src0, %src1 : !pto.tile<...> +``` + +### AS Level 1（SSA） + +```text +%dst = pto.trem %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.trem ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`： + +```cpp +template +PTO_INST RecordEvent TREM(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, TileDataTmp &tmp, WaitEvents &... events); +``` + +## 约束 + +- **实现检查 (A2A3)**: + - `dst`、`src0` 和 `src1` 必须使用相同的元素类型。 + - 支持的元素类型：`float` 和 `int32_t`。 + - `dst`、`src0` 和 `src1` 必须是向量 Tile。 + - `dst`、`src0` 和 `src1` 必须是行主序。 + - 运行时：`dst.GetValidRow() == src0.GetValidRow() == src1.GetValidRow() > 0` 且 `dst.GetValidCol() == src0.GetValidCol() == src1.GetValidCol() > 0`。 + - **tmp 缓冲区要求**： + - `tmp.GetValidCol() >= dst.GetValidCol()`（至少与 dst 相同的列数） + - `tmp.GetValidRow() >= 1`（至少 1 行） + - 数据类型必须与 `TileDataDst::DType` 匹配。 +- **实现检查 (A5)**: + - `dst`、`src0` 和 `src1` 必须使用相同的元素类型。 + - 支持的元素类型：`float`、`int32_t`、`uint32_t`、`half`、`int16_t` 和 `uint16_t`。 + - `dst`、`src0` 和 `src1` 必须是向量 Tile。 + - 静态有效边界：所有 Tile 都必须满足 `ValidRow <= Rows` 且 `ValidCol <= Cols`。 + - 运行时：`dst.GetValidRow() == src0.GetValidRow() == src1.GetValidRow()` 且 `dst.GetValidCol() == src0.GetValidCol() == src1.GetValidCol()`。 + - 注意：tmp 参数在 A5 上被接受但不进行验证或使用。 +- **除零**: + - 行为由目标定义；CPU 模拟器在调试构建中会断言。 +- **有效区域**: + - 该操作使用 `dst.GetValidRow()` / `dst.GetValidCol()` 作为迭代域。 +- **对于 `int32_t` 输入（仅 A2A3）**：`src0` 和 `src1` 的所有元素必须在 `[-2^24, 2^24]` 范围内（即 `[-16777216, 16777216]`），以确保在计算过程中能精确转换为 float32。 + +## 示例 + +```cpp +#include + +using namespace pto; + +void example() { + using TileT = Tile; + TileT out, a, b; + Tile tmp; + TREM(out, a, b, tmp); +} +``` + +## 汇编示例（ASM） + +### 自动模式 + +```text +# 自动模式：由编译器/运行时负责资源放置与调度。 +%dst = pto.trem %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### 手动模式 + +```text +# 手动模式：先显式绑定资源，再发射指令。 +# 可选（当该指令包含 tile 操作数时）： +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.trem %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### PTO 汇编形式 + +```text +%dst = trem %src0, %src1 : !pto.tile<...> +# AS Level 2 (DPS) +pto.trem ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TRESHAPE.md b/designs/outerCube/PTOISA/TRESHAPE.md new file mode 100644 index 00000000..ef5ca45d --- /dev/null +++ b/designs/outerCube/PTOISA/TRESHAPE.md @@ -0,0 +1,115 @@ +# TRESHAPE + + +## Tile Operation Diagram + +![TRESHAPE tile operation](../figures/isa/TRESHAPE.svg) + +## Introduction + +Reinterpret a tile as another tile type/shape while preserving the underlying bytes. + +This is a *bitwise* reshape: it does not change values, it only changes how the same byte buffer is viewed. + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +```text +%dst = treshape %src : !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.treshape %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.treshape ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### IR Level 1 (SSA) + +```text +%dst = pto.treshape %src : !pto.tile<...> -> !pto.tile<...> +``` + +### IR Level 2 (DPS) + +```text +pto.treshape ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TRESHAPE(TileDataOut &dst, TileDataIn &src, WaitEvents &... events); +``` + +## Constraints + +Enforced by `TRESHAPE_IMPL`: + +- **Tile type must match**: `TileDataIn::Loc == TileDataOut::Loc`. +- **Total byte size must match**: `sizeof(InElem) * InNumel == sizeof(OutElem) * OutNumel`. +- **No boxed/non-boxed conversion**: + - cannot reshape between `SLayout::NoneBox` and boxed layouts. + +## Notes + +- **CPU simulation**: implemented as a byte-for-byte copy into `dst`. +- **A2/A3**: implemented as an alias (`TASSIGN_IMPL(dst, src.data())`), so `dst` and `src` refer to the same underlying storage. + +## Examples + +```cpp +#include + +using namespace pto; + +void example() { + using Src = Tile; + using Dst = Tile; + static_assert(Src::Numel == Dst::Numel); + + Src src; + Dst dst; + TRESHAPE(dst, src); +} +``` + +## Math Interpretation + +Unless otherwise specified, semantics are defined over the valid region and target-dependent behavior is marked as implementation-defined. + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.treshape %src : !pto.tile<...> -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.treshape %src : !pto.tile<...> -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = pto.treshape %src : !pto.tile<...> -> !pto.tile<...> +# AS Level 2 (DPS) +pto.treshape ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TRESHAPE_zh.md b/designs/outerCube/PTOISA/TRESHAPE_zh.md new file mode 100644 index 00000000..616c08b8 --- /dev/null +++ b/designs/outerCube/PTOISA/TRESHAPE_zh.md @@ -0,0 +1,81 @@ +# TRESHAPE + +## 指令示意图 + +![TRESHAPE tile operation](../figures/isa/TRESHAPE.svg) + +## 简介 + +将 Tile 重新解释为另一种 Tile 类型/形状，同时保留底层字节。 + +## 数学语义 + +除非另有说明, semantics are defined over the valid region and target-dependent behavior is marked as implementation-defined. + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS Specification](../assembly/PTO-AS.md). + +```text +%dst = treshape %src : !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.treshape %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.treshape ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### AS Level 1（SSA） + +```text +%dst = pto.treshape %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.treshape ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TRESHAPE(TileDataOut &dst, TileDataIn &src, WaitEvents &... events); +``` + +## 约束 + +Enforced by `TRESHAPE_IMPL`: + +- **Tile type must match**: `TileDataIn::Loc == TileDataOut::Loc`. +- **Total byte size must match**: `sizeof(InElem) * InNumel == sizeof(OutElem) * OutNumel`. +- **No boxed/non-boxed conversion**: + - cannot reshape between `SLayout::NoneBox` and boxed layouts. + +## 示例 + +```cpp +#include + +using namespace pto; + +void example() { + using Src = Tile; + using Dst = Tile; + static_assert(Src::Numel == Dst::Numel); + + Src src; + Dst dst; + TRESHAPE(dst, src); +} +``` diff --git a/designs/outerCube/PTOISA/TROWARGMAX.md b/designs/outerCube/PTOISA/TROWARGMAX.md new file mode 100644 index 00000000..470e0bda --- /dev/null +++ b/designs/outerCube/PTOISA/TROWARGMAX.md @@ -0,0 +1,148 @@ +# TROWARGMAX + + +## Tile Operation Diagram + +![TROWARGMAX tile operation](../figures/isa/TROWARGMAX.svg) + +## Introduction + +Get the column index of the maximum element for each row. + +## Math Interpretation + +Let `R = src.GetValidRow()` and `C = src.GetValidCol()`. For `0 <= i < R`: + +$$ \mathrm{dst}_{i,0} = \max_{0 \le j < C} j_{i} $$ + +## Assembly Syntax + +PTO-AS form: see `docs/grammar/PTO-AS.md`. + +Synchronous form: + +```text +%dst = trowargmax %src : !pto.tile<...> -> !pto.tile<...> +``` +Lowering may introduce internal scratch tiles; the C++ intrinsic requires an explicit `tmp` operand. + +### IR Level 1 (SSA) + +```text +%dst = pto.trowargmax %src, %tmp : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### IR Level 2 (DPS) + +```text +pto.trowargmax ins(%src, %tmp : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TROWARGMAX(TileDataOut& dst, TileDataIn& src, TileDataTmp& tmp, WaitEvents&... events); +``` + +## Constraints + +Implementation checks (NPU): + +- A2A3: + - Tile location: `dst` and `src` must be `TileType::Vec`. + - Tile layout of `src`: ND fractal (`isRowMajor` and `SLayout::NoneBox`). + - Tile layout of `dst`: + - **Compact Mode**: DN layout Tile of 1D, e.g., `Tile`, ROWS must be 32b aligned. + - **Traditional Mode**: ND layout Tile of 2D, e.g., `Tile`. + - Source data types: `half` or `float`. + - Destination data types: `uint32_t` or `int32_t`. + - Runtime valid checks: + - `srcValidCol != 0` and `srcValidRow != 0`. +- A5: + - Source data types: `half` or `float`. + - Destination data types: `uint32_t` or `int32_t`. + - No explicit runtime assertions on `validRow/validCol` in the implementation; the loops use `src.GetValidRow()` and `src.GetValidCol()`. + - `tmp` temporary tile is not used, only for compatibility use. + +### About temporary tile `tmp` for A3 + +* Temporary tile is not used when `srcValidCol <= ElementPerRepeat`, used when `srcValidCol > ElementPerRepeat`. +* `tmp` tile's rows is the same as `src`. +* Simply set `tmp` tile size the same as `src` when `src` is small. +* `tmp` tile's stride can be calculated out based on `src`'s `validCol` using the following formula: + +```text +repeats = ceil(validCol / elementPerRepeat) +stride = ceil(repeats * 2 / elementPerBlock) * elementPerBlock + ceil(repeats / elementPerBlock) * elementPerBlock +``` + +## Examples + +### Auto + +```cpp +#include + +using namespace pto; + +void example_auto() { + using SrcT = Tile; + using DstT = Tile; + using TmpT = Tile; + SrcT src; + DstT dst; + TmpT tmp; + TROWARGMAX(dst, src, tmp); +} +``` + +### Manual + +```cpp +#include + +using namespace pto; + +void example_manual() { + using SrcT = Tile; + using DstT = Tile; + using TmpT = Tile; + SrcT src; + DstT dst; + TmpT tmp; + TASSIGN(src, 0x1000); + TASSIGN(dst, 0x2000); + TASSIGN(tmp, 0x3000); + TROWARGMAX(dst, src, tmp); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.trowmax %src, %tmp : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.trowmax %src, %tmp : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = trowmax %src : !pto.tile<...> -> !pto.tile<...> +# IR Level 2 (DPS) +pto.trowmax ins(%src, %tmp : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/TROWARGMAX_zh.md b/designs/outerCube/PTOISA/TROWARGMAX_zh.md new file mode 100644 index 00000000..01da87a4 --- /dev/null +++ b/designs/outerCube/PTOISA/TROWARGMAX_zh.md @@ -0,0 +1,147 @@ +# TROWARGMAX + +## 指令示意图 + +![TROWARGMAX tile operation](../figures/isa/TROWARGMAX.svg) + +## 简介 + +获取每行最大值对应列索引。 + +## 数学语义 + +Let `R = src.GetValidRow()` and `C = src.GetValidCol()`. For `0 <= i < R`: + +$$ \mathrm{dst}_{i,0} = \max_{0 \le j < C} j_{i} $$ + +## 汇编语法 + +PTO-AS 形式：参见 `docs/grammar/PTO-AS.md`. + +同步形式： + +```text +%dst = trowargmax %src : !pto.tile<...> -> !pto.tile<...> +``` +Lowering may introduce internal scratch tiles; the C++ intrinsic requires an explicit `tmp` operand. + +### IR Level 1（SSA） + +```text +%dst = pto.trowargmax %src, %tmp : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### IR Level 2（DPS） + +```text +pto.trowargmax ins(%src, %tmp : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TROWARGMAX(TileDataOut& dst, TileDataIn& src, TileDataTmp& tmp, WaitEvents&... events); +``` + +## 约束 + +实现检查 (NPU): + +- A2A3: + - Tile location: `dst` and `src` must be `TileType::Vec`. + - Tile 布局 of `src`: ND fractal (`isRowMajor` and `SLayout::NoneBox`). + - Tile 布局 of `dst`: + - **紧凑模式**：DN 布局的一维 Tile，例如 `Tile`，此时ROWS要做到32b对齐。 + - **传统模式**：ND 布局的二维 Tile，例如 `Tile`。 + - 源数据类型: `half` or `float`. + - 目标数据类型：`uint32_t` or `int32_t`. + - 运行期有效区域检查: + - `srcValidCol != 0` and `srcValidRow != 0`. +- A5: + - 源数据类型: `half` or `float`. + - 目标数据类型：`uint32_t` or `int32_t`. + - No explicit runtime assertions on `validRow/validCol` in the implementation; the loops use `src.GetValidRow()` and `src.GetValidCol()`. + - `tmp`临时Tile不使用，仅做兼容。 + +### A3 `tmp`临时Tile相关说明 + +* `tmp`临时Tile在`srcValidCol <= ElementPerRepeat`时不使用，`srcValidCol > ElementPerRepeat`时需要使用。 +* `tmp` tile的行数和`src` tile的行数相同。 +* 按以下公式根据`src` tile的`validCol`算出`tmp` tile所需stride： + +```text +repeats = ceil(validCol / elementPerRepeat) +stride = ceil(repeats * 2 / elementPerBlock) * elementPerBlock + ceil(repeats / elementPerBlock) * elementPerBlock +``` + +## 示例 + +### 自动（Auto） + +```cpp +#include + +using namespace pto; + +void example_auto() { + using SrcT = Tile; + using DstT = Tile; + using TmpT = Tile; + SrcT src; + DstT dst; + TmpT tmp; + TROWARGMAX(dst, src, tmp); +} +``` + +### 手动（Manual） + +```cpp +#include + +using namespace pto; + +void example_manual() { + using SrcT = Tile; + using DstT = Tile; + using TmpT = Tile; + SrcT src; + DstT dst; + TmpT tmp; + TASSIGN(src, 0x1000); + TASSIGN(dst, 0x2000); + TASSIGN(tmp, 0x3000); + TROWARGMAX(dst, src, tmp); +} +``` + +## 汇编示例（ASM） + +### 自动模式 + +```text +# 自动模式：由编译器/运行时负责资源放置与调度。 +%dst = pto.trowargmax %src, %tmp : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### 手动模式 + +```text +# 手动模式：先显式绑定资源，再发射指令。 +# 可选（当该指令包含 tile 操作数时）： +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.trowargmax %src, %tmp : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### PTO 汇编形式 + +```text +%dst = trowargmax %src : !pto.tile<...> -> !pto.tile<...> +# IR Level 2 (DPS) +pto.trowargmax ins(%src, %tmp : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/TROWARGMIN.md b/designs/outerCube/PTOISA/TROWARGMIN.md new file mode 100644 index 00000000..e1d99930 --- /dev/null +++ b/designs/outerCube/PTOISA/TROWARGMIN.md @@ -0,0 +1,148 @@ +# TROWARGMIN + + +## Tile Operation Diagram + +![TROWARGMIN tile operation](../figures/isa/TROWARGMIN.svg) + +## Introduction + +Get the column index of the minimum element for each row. + +## Math Interpretation + +Let `R = src.GetValidRow()` and `C = src.GetValidCol()`. For `0 <= i < R`: + +$$ \mathrm{dst}_{i,0} = \min_{0 \le j < C} j_{i} $$ + +## Assembly Syntax + +PTO-AS form: see `docs/grammar/PTO-AS.md`. + +Synchronous form: + +```text +%dst = trowargmin %src : !pto.tile<...> -> !pto.tile<...> +``` +Lowering may introduce internal scratch tiles; the C++ intrinsic requires an explicit `tmp` operand. + +### IR Level 1 (SSA) + +```text +%dst = pto.trowargmin %src, %tmp : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### IR Level 2 (DPS) + +```text +pto.trowargmin ins(%src, %tmp : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TROWARGMIN(TileDataOut& dst, TileDataIn& src, TileDataTmp& tmp, WaitEvents&... events); +``` + +## Constraints + +Implementation checks (NPU): + +- A2A3: + - Tile location: `dst` and `src` must be `TileType::Vec`. + - Tile layout of `src`: ND fractal (`isRowMajor` and `SLayout::NoneBox`). + - Tile layout of `dst`: + - **Compact Mode**: DN layout Tile of 1D, e.g., `Tile`, ROWS must be 32b aligned. + - **Traditional Mode**: ND layout Tile of 2D, e.g., `Tile`. + - Source data types: `half` or `float`. + - Destination data types: `uint32_t` or `int32_t`. + - Runtime valid checks: + - `srcValidCol != 0` and `srcValidRow != 0`. +- A5: + - Source data types: `half` or `float`. + - Destination data types: `uint32_t` or `int32_t`. + - No explicit runtime assertions on `validRow/validCol` in the implementation; the loops use `src.GetValidRow()` and `src.GetValidCol()`. + - `tmp` temporary tile is not used, only for compatibility use. + +### About temporary tile `tmp` for A3 + +* Temporary tile is not used when `srcValidCol <= ElementPerRepeat`, used when `srcValidCol > ElementPerRepeat`. +* `tmp` tile's rows is the same as `src`. +* Simply set `tmp` tile size the same as `src` when `src` is small. +* `tmp` tile's stride can be calculated out based on `src`'s `validCol` using the following formula: + +```text +repeats = ceil(validCol / elementPerRepeat) +stride = ceil(repeats * 2 / elementPerBlock) * elementPerBlock + ceil(repeats / elementPerBlock) * elementPerBlock +``` + +## Examples + +### Auto + +```cpp +#include + +using namespace pto; + +void example_auto() { + using SrcT = Tile; + using DstT = Tile; + using TmpT = Tile; + SrcT src; + DstT dst; + TmpT tmp; + TROWARGMIN(dst, src, tmp); +} +``` + +### Manual + +```cpp +#include + +using namespace pto; + +void example_manual() { + using SrcT = Tile; + using DstT = Tile; + using TmpT = Tile; + SrcT src; + DstT dst; + TmpT tmp; + TASSIGN(src, 0x1000); + TASSIGN(dst, 0x2000); + TASSIGN(tmp, 0x3000); + TROWARGMIN(dst, src, tmp); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.trowargmin %src, %tmp : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.trowargmin %src, %tmp : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = trowargmin %src : !pto.tile<...> -> !pto.tile<...> +# IR Level 2 (DPS) +pto.trowargmin ins(%src, %tmp : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/TROWARGMIN_zh.md b/designs/outerCube/PTOISA/TROWARGMIN_zh.md new file mode 100644 index 00000000..4dae67f1 --- /dev/null +++ b/designs/outerCube/PTOISA/TROWARGMIN_zh.md @@ -0,0 +1,147 @@ +# TROWARGMIN + +## 指令示意图 + +![TROWARGMIN tile operation](../figures/isa/TROWARGMIN.svg) + +## 简介 + +获取每行最小值对应列索引。 + +## 数学语义 + +Let `R = src.GetValidRow()` and `C = src.GetValidCol()`. For `0 <= i < R`: + +$$ \mathrm{dst}_{i,0} = \min_{0 \le j < C} j_{i} $$ + +## 汇编语法 + +PTO-AS 形式：参见 `docs/grammar/PTO-AS.md`. + +同步形式： + +```text +%dst = trowargmin %src : !pto.tile<...> -> !pto.tile<...> +``` +Lowering may introduce internal scratch tiles; the C++ intrinsic requires an explicit `tmp` operand. + +### IR Level 1（SSA） + +```text +%dst = pto.trowargmin %src, %tmp : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### IR Level 2（DPS） + +```text +pto.trowargmin ins(%src, %tmp : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TROWARGMIN(TileDataOut& dst, TileDataIn& src, TileDataTmp& tmp, WaitEvents&... events); +``` + +## 约束 + +实现检查 (NPU): + +- A2A3: + - Tile location: `dst` and `src` must be `TileType::Vec`. + - Tile 布局 of `src`: ND fractal (`isRowMajor` and `SLayout::NoneBox`). + - Tile 布局 of `dst`: + - **紧凑模式**：DN 布局的一维 Tile，例如 `Tile`，此时ROWS要做到32b对齐。 + - **传统模式**：ND 布局的二维 Tile，例如 `Tile`。 + - 源数据类型: `half` or `float`. + - 目标数据类型：`uint32_t` or `int32_t`. + - 运行期有效区域检查: + - `srcValidCol != 0` and `srcValidRow != 0`. +- A5: + - 源数据类型: `half` or `float`. + - 目标数据类型：`uint32_t` or `int32_t`. + - No explicit runtime assertions on `validRow/validCol` in the implementation; the loops use `src.GetValidRow()` and `src.GetValidCol()`. + - `tmp`临时Tile不使用，仅做兼容。 + +### A3 `tmp`临时Tile相关说明 + +* `tmp`临时Tile在`srcValidCol <= ElementPerRepeat`时不使用，`srcValidCol > ElementPerRepeat`时需要使用。 +* `tmp` tile的行数和`src` tile的行数相同。 +* 按以下公式根据`src` tile的`validCol`算出`tmp` tile所需stride： + +```text +repeats = ceil(validCol / elementPerRepeat) +stride = ceil(repeats * 2 / elementPerBlock) * elementPerBlock + ceil(repeats / elementPerBlock) * elementPerBlock +``` + +## 示例 + +### 自动（Auto） + +```cpp +#include + +using namespace pto; + +void example_auto() { + using SrcT = Tile; + using DstT = Tile; + using TmpT = Tile; + SrcT src; + DstT dst; + TmpT tmp; + TROWARGMIN(dst, src, tmp); +} +``` + +### 手动（Manual） + +```cpp +#include + +using namespace pto; + +void example_manual() { + using SrcT = Tile; + using DstT = Tile; + using TmpT = Tile; + SrcT src; + DstT dst; + TmpT tmp; + TASSIGN(src, 0x1000); + TASSIGN(dst, 0x2000); + TASSIGN(tmp, 0x3000); + TROWARGMIN(dst, src, tmp); +} +``` + +## 汇编示例（ASM） + +### 自动模式 + +```text +# 自动模式：由编译器/运行时负责资源放置与调度。 +%dst = pto.trowargmin %src, %tmp : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### 手动模式 + +```text +# 手动模式：先显式绑定资源，再发射指令。 +# 可选（当该指令包含 tile 操作数时）： +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.trowargmin %src, %tmp : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### PTO 汇编形式 + +```text +%dst = trowargmin %src : !pto.tile<...> -> !pto.tile<...> +# IR Level 2 (DPS) +pto.trowargmin ins(%src, %tmp : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/TROWEXPAND.md b/designs/outerCube/PTOISA/TROWEXPAND.md new file mode 100644 index 00000000..55d385d1 --- /dev/null +++ b/designs/outerCube/PTOISA/TROWEXPAND.md @@ -0,0 +1,132 @@ +# TROWEXPAND + + +## Tile Operation Diagram + +![TROWEXPAND tile operation](../figures/isa/TROWEXPAND.svg) + +## Introduction + +Broadcast the first element of each source row across the destination row. + +## Math Interpretation + +Let `R = dst.GetValidRow()` and `C = dst.GetValidCol()`. For `0 <= i < R` and `0 <= j < C`: + +$$ \mathrm{dst}_{i,j} = \mathrm{src}_{i,0} $$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = trowexpand %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.trowexpand %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.trowexpand ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### IR Level 1 (SSA) + +```text +%dst = pto.trowexpand %src : !pto.tile<...> -> !pto.tile<...> +``` + +### IR Level 2 (DPS) + +```text +pto.trowexpand ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TROWEXPAND(TileDataDst &dst, TileDataSrc &src, WaitEvents &... events); +``` + +## Constraints + +Implementation checks (NPU): + +- Tile Type: `dst` and `src` must be `TileType::Vec`. +- Tile layout: ND fractal (`isRowMajor` and `SLayout::NoneBox`) for both `src` and `dst`. +- Data type: A2A3/A5 element types must be one of: `int8_t` or `uint8_t` or `int16_t` or `uint16_t` or `int32_t` or `uint32_t` or `half` or `bfloat16_t` or `float`. +- Runtime valid checks: + - A2A3: returns early if any of `dstValidRow`, `dstValidCol`, `srcValidRow`, `srcValidCol` is zero. + - A5: asserts `srcValidRow == dstValidRow` and asserts `srcValidRow != 0 && srcValidCol != 0`. + +## Examples + +### Auto + +```cpp +#include + +using namespace pto; + +void example_auto() { + using SrcT = Tile; + using DstT = Tile; + SrcT src; + DstT dst; + TROWEXPAND(dst, src); +} +``` + +### Manual + +```cpp +#include + +using namespace pto; + +void example_manual() { + using SrcT = Tile; + using DstT = Tile; + SrcT src; + DstT dst; + TASSIGN(src, 0x1000); + TASSIGN(dst, 0x2000); + TROWEXPAND(dst, src); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.trowexpand %src : !pto.tile<...> -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.trowexpand %src : !pto.tile<...> -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = trowexpand %src : !pto.tile<...> -> !pto.tile<...> +# AS Level 2 (DPS) +pto.trowexpand ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TROWEXPANDADD.md b/designs/outerCube/PTOISA/TROWEXPANDADD.md new file mode 100644 index 00000000..8f8b334f --- /dev/null +++ b/designs/outerCube/PTOISA/TROWEXPANDADD.md @@ -0,0 +1,106 @@ +# TROWEXPANDADD + + +## Tile Operation Diagram + +![TROWEXPANDADD tile operation](../figures/isa/TROWEXPANDADD.svg) + +## Introduction + +Row-wise broadcast add: add a per-row scalar vector `src1` to each row of `src0`. + +## Math Interpretation + +Let `R = dst.GetValidRow()` and `C = dst.GetValidCol()`. Let `s_i` be the per-row scalar taken from `src1` (one value per row). + +For `0 <= i < R` and `0 <= j < C`: + +$$ +\mathrm{dst}_{i,j} = \mathrm{src0}_{i,j} + s_i +$$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = trowexpandadd %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.trowexpandadd %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.trowexpandadd ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### IR Level 1 (SSA) + +```text +%dst = pto.trowexpandadd %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### IR Level 2 (DPS) + +```text +pto.trowexpandadd ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TROWEXPANDADD(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, WaitEvents &... events); + +template +PTO_INST RecordEvent TROWEXPANDADD(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, TileDataTmp &tmp, WaitEvents &... events); +``` + +## Constraints + +- `TileDataDst::DType == TileDataSrc0::DType == TileDataSrc1::DType` +- `TileDataDst::DType`, `TileDataSrc0::DType`, `TileDataSrc1::DType` must be one of: `half`, `float`. +- Tile shape/layout constraint (compile-time): `TileDataDst::isRowMajor`. +- Mode 1: `src1` is expected to provide **one scalar per row** (i.e., its valid shape must cover `R` values). +- Mode 2: `src1` is expected to provide **32 bytes data per row**. +- Exact layout/fractal constraints are target-specific; see backend headers under `include/pto/npu/*/TRowExpand*.hpp`. + +## Examples + +See related examples in `docs/isa/` and `docs/coding/tutorials/`. + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.trowexpandadd %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.trowexpandadd %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = trowexpandadd %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +# AS Level 2 (DPS) +pto.trowexpandadd ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TROWEXPANDADD_zh.md b/designs/outerCube/PTOISA/TROWEXPANDADD_zh.md new file mode 100644 index 00000000..6170b26b --- /dev/null +++ b/designs/outerCube/PTOISA/TROWEXPANDADD_zh.md @@ -0,0 +1,79 @@ +# TROWEXPANDADD + +## 指令示意图 + +![TROWEXPANDADD tile operation](../figures/isa/TROWEXPANDADD.svg) + +## 简介 + +行广播加法：加上一个每行标量向量。 + +## 数学语义 + +Let `R = dst.GetValidRow()` and `C = dst.GetValidCol()`. Let `s_i` be the per-row scalar taken from `src1` (one value per row). + +For `0 <= i < R` and `0 <= j < C`: + +$$ +\mathrm{dst}_{i,j} = \mathrm{src0}_{i,j} + s_i +$$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS Specification](../assembly/PTO-AS.md). + +同步形式： + +```text +%dst = trowexpandadd %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.trowexpandadd %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.trowexpandadd ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### AS Level 1（SSA） + +```text +%dst = pto.trowexpandadd %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.trowexpandadd ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TROWEXPANDADD(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, WaitEvents &... events); + +template +PTO_INST RecordEvent TROWEXPANDADD(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, TileDataTmp &tmp, WaitEvents &... events); +``` + +## 约束 + +- `TileDataDst::DType == TileDataSrc0::DType == TileDataSrc1::DType` +- `TileDataDst::DType`, `TileDataSrc0::DType`, `TileDataSrc1::DType` must be one of: `half`, `float`. +- Tile 形状/布局约束 (compile-time): `TileDataDst::isRowMajor`. +- Mode 1: `src1` is expected to provide **one scalar per row** (i.e., its valid shape must cover `R` values). +- Mode 2: `src1` is expected to provide **32 bytes data per row**. +- Exact layout/fractal constraints are target-specific; see backend headers under `include/pto/npu/*/TRowExpand*.hpp`. + +## 示例 + +See related examples in `docs/isa/` and `docs/coding/tutorials/`. diff --git a/designs/outerCube/PTOISA/TROWEXPANDDIV.md b/designs/outerCube/PTOISA/TROWEXPANDDIV.md new file mode 100644 index 00000000..5a116155 --- /dev/null +++ b/designs/outerCube/PTOISA/TROWEXPANDDIV.md @@ -0,0 +1,126 @@ +# TROWEXPANDDIV + + +## Tile Operation Diagram + +![TROWEXPANDDIV tile operation](../figures/isa/TROWEXPANDDIV.svg) + +## Introduction + +Row-wise broadcast divide: divide each row of `src0` by a per-row scalar vector `src1`. + +## Math Interpretation + +For each element `(i, j)` in the valid region: + +$$ \mathrm{dst}_{i,j} = \frac{\mathrm{src0}_{i,j}}{\mathrm{src1}_{0,i}} $$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = trowexpanddiv %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.trowexpanddiv %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.trowexpanddiv ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TROWEXPANDDIV(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, WaitEvents &... events); + +template +PTO_INST RecordEvent TROWEXPANDDIV(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, TileDataTmp &tmp, WaitEvents &... events); +``` + +## Constraints + +- **Implementation checks**: + - `TileDataDst::DType == TileDataSrc0::DType == TileDataSrc1::DType` (compile-time). + - `TileDataDst::DType`, `TileDataSrc0::DType`, `TileDataSrc1::DType` must be one of: `half`, `float`. + - Tile shape/layout constraint (compile-time): `TileDataDst::isRowMajor`. + - Mode 1: `src1` is expected to provide **one scalar per row** (i.e., its valid shape must cover `R` values). + - Mode 2: `src1` is expected to provide **32 bytes data per row**. + +## Examples + +### Auto + +```cpp +#include + +using namespace pto; + +void example_auto() { + using TileT = Tile; + using RowVecT = Tile; + + TileT src0, dst; + RowVecT src1(16); + TROWEXPANDDIV(dst, src0, src1); +} +``` + +### Manual + +```cpp +#include + +using namespace pto; + +void example_manual() { + using TileT = Tile; + using RowVecT = Tile; + + TileT src0, dst; + RowVecT src1(16); + TASSIGN(src0, 0x1000); + TASSIGN(dst, 0x2000); + TASSIGN(src1, 0x3000); + TROWEXPANDDIV(dst, src0, src1); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.trowexpanddiv %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.trowexpanddiv %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = trowexpanddiv %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +# AS Level 2 (DPS) +pto.trowexpanddiv ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/TROWEXPANDDIV_zh.md b/designs/outerCube/PTOISA/TROWEXPANDDIV_zh.md new file mode 100644 index 00000000..0f5523ea --- /dev/null +++ b/designs/outerCube/PTOISA/TROWEXPANDDIV_zh.md @@ -0,0 +1,126 @@ +# TROWEXPANDDIV + +## 指令示意图 + +![TROWEXPANDDIV tile operation](../figures/isa/TROWEXPANDDIV.svg) + +## 简介 + +行广播除法：将 `src0` 的每一行除以一个每行标量向量 `src1`。 + +## 数学语义 + +对每个元素 `(i, j)` 在有效区域内： + +$$ \mathrm{dst}_{i,j} = \frac{\mathrm{src0}_{i,j}}{\mathrm{src1}_{0,i}} $$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS 规范](../assembly/PTO-AS_zh.md)。 + +同步形式： + +```text +%dst = trowexpanddiv %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 1（SSA） + +```text +%dst = pto.trowexpanddiv %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.trowexpanddiv ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`： + +```cpp +template +PTO_INST RecordEvent TROWEXPANDDIV(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, WaitEvents &... events); + +template +PTO_INST RecordEvent TROWEXPANDDIV(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, TileDataTmp &tmp, WaitEvents &... events); +``` + +## 约束 + +- **实现检查**: + - `TileDataDst::DType == TileDataSrc0::DType == TileDataSrc1::DType`（编译时）。 + - `TileDataDst::DType`、`TileDataSrc0::DType`、`TileDataSrc1::DType` 必须是以下之一：`half`、`float`。 + - Tile 形状/布局约束（编译时）：`TileDataDst::isRowMajor`。 + - 模式 1：`src1` 预期提供**每行一个标量**（即，其有效形状必须覆盖 `R` 个值）。 + - 模式 2：`src1` 预期提供**每行 32 字节数据**。 + +## 示例 + +### 自动（Auto） + +```cpp +#include + +using namespace pto; + +void example_auto() { + using TileT = Tile; + using RowVecT = Tile; + + TileT src0, dst; + RowVecT src1(16); + TROWEXPANDDIV(dst, src0, src1); +} +``` + +### 手动（Manual） + +```cpp +#include + +using namespace pto; + +void example_manual() { + using TileT = Tile; + using RowVecT = Tile; + + TileT src0, dst; + RowVecT src1(16); + TASSIGN(src0, 0x1000); + TASSIGN(dst, 0x2000); + TASSIGN(src1, 0x3000); + TROWEXPANDDIV(dst, src0, src1); +} +``` + +## 汇编示例（ASM） + +### 自动模式 + +```text +# 自动模式：由编译器/运行时负责资源放置与调度。 +%dst = pto.trowexpanddiv %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### 手动模式 + +```text +# 手动模式：先显式绑定资源，再发射指令。 +# 可选（当该指令包含 tile 操作数时）： +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.trowexpanddiv %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### PTO 汇编形式 + +```text +%dst = trowexpanddiv %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +# AS Level 2 (DPS) +pto.trowexpanddiv ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/TROWEXPANDEXPDIF.md b/designs/outerCube/PTOISA/TROWEXPANDEXPDIF.md new file mode 100644 index 00000000..d5551a18 --- /dev/null +++ b/designs/outerCube/PTOISA/TROWEXPANDEXPDIF.md @@ -0,0 +1,106 @@ +# TROWEXPANDEXPDIF + + +## Tile Operation Diagram + +![TROWEXPANDEXPDIF tile operation](../figures/isa/TROWEXPANDEXPDIF.svg) + +## Introduction + +Row-wise exp-diff: compute `exp(src0 - src1)` where `src1` provides one scalar per row. + +## Math Interpretation + +Let `R = dst.GetValidRow()` and `C = dst.GetValidCol()`. Let `s_i` be the per-row scalar taken from `src1` (one value per row). + +For `0 <= i < R` and `0 <= j < C`: + +$$ +\mathrm{dst}_{i,j} = \exp(\mathrm{src0}_{i,j} - s_i) +$$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = trowexpandexpdif %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.trowexpandexpdif %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.trowexpandexpdif ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### IR Level 1 (SSA) + +```text +%dst = pto.trowexpandexpdif %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### IR Level 2 (DPS) + +```text +pto.trowexpandexpdif ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TROWEXPANDEXPDIF(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, WaitEvents &... events); + +template +PTO_INST RecordEvent TROWEXPANDEXPDIF(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, TileDataTmp &tmp, WaitEvents &... events); +``` + +## Constraints + +- `TileDataDst::DType == TileDataSrc0::DType == TileDataSrc1::DType` +- `TileDataDst::DType`, `TileDataSrc0::DType`, `TileDataSrc1::DType` must be one of: `half`, `float`. +- Tile shape/layout constraint (compile-time): `TileDataDst::isRowMajor`. +- Mode 1: `src1` is expected to provide **one scalar per row** (i.e., its valid shape must cover `R` values). +- Mode 2: `src1` is expected to provide **32 bytes data per row**. +- Exact layout/fractal constraints are target-specific; see backend headers under `include/pto/npu/*/TRowExpand*.hpp`. + +## Examples + +See related examples in `docs/isa/` and `docs/coding/tutorials/`. + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.trowexpandexpdif %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.trowexpandexpdif %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = trowexpandexpdif %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +# AS Level 2 (DPS) +pto.trowexpandexpdif ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TROWEXPANDEXPDIF_zh.md b/designs/outerCube/PTOISA/TROWEXPANDEXPDIF_zh.md new file mode 100644 index 00000000..7a98cd6f --- /dev/null +++ b/designs/outerCube/PTOISA/TROWEXPANDEXPDIF_zh.md @@ -0,0 +1,79 @@ +# TROWEXPANDEXPDIF + +## 指令示意图 + +![TROWEXPANDEXPDIF tile operation](../figures/isa/TROWEXPANDEXPDIF.svg) + +## 简介 + +行指数差运算：计算 exp(src0 - src1)，其中 src1 为每行标量。 + +## 数学语义 + +Let `R = dst.GetValidRow()` and `C = dst.GetValidCol()`. Let `s_i` be the per-row scalar taken from `src1` (one value per row). + +For `0 <= i < R` and `0 <= j < C`: + +$$ +\mathrm{dst}_{i,j} = \exp(\mathrm{src0}_{i,j} - s_i) +$$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS Specification](../assembly/PTO-AS.md). + +同步形式： + +```text +%dst = trowexpandexpdif %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.trowexpandexpdif %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.trowexpandexpdif ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### AS Level 1（SSA） + +```text +%dst = pto.trowexpandexpdif %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.trowexpandexpdif ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TROWEXPANDEXPDIF(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, WaitEvents &... events); + +template +PTO_INST RecordEvent TROWEXPANDEXPDIF(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, TileDataTmp &tmp, WaitEvents &... events); +``` + +## 约束 + +- `TileDataDst::DType == TileDataSrc0::DType == TileDataSrc1::DType` +- `TileDataDst::DType`, `TileDataSrc0::DType`, `TileDataSrc1::DType` must be one of: `half`, `float`. +- Tile 形状/布局约束 (compile-time): `TileDataDst::isRowMajor`. +- Mode 1: `src1` is expected to provide **one scalar per row** (i.e., its valid shape must cover `R` values). +- Mode 2: `src1` is expected to provide **32 bytes data per row**. +- Exact layout/fractal constraints are target-specific; see backend headers under `include/pto/npu/*/TRowExpand*.hpp`. + +## 示例 + +See related examples in `docs/isa/` and `docs/coding/tutorials/`. diff --git a/designs/outerCube/PTOISA/TROWEXPANDMAX.md b/designs/outerCube/PTOISA/TROWEXPANDMAX.md new file mode 100644 index 00000000..88ddf649 --- /dev/null +++ b/designs/outerCube/PTOISA/TROWEXPANDMAX.md @@ -0,0 +1,106 @@ +# TROWEXPANDMAX + + +## Tile Operation Diagram + +![TROWEXPANDMAX tile operation](../figures/isa/TROWEXPANDMAX.svg) + +## Introduction + +Row-wise broadcast max: take `max(src0, src1)` where `src1` provides one scalar per row. + +## Math Interpretation + +Let `R = dst.GetValidRow()` and `C = dst.GetValidCol()`. Let `s_i` be the per-row scalar taken from `src1` (one value per row). + +For `0 <= i < R` and `0 <= j < C`: + +$$ +\mathrm{dst}_{i,j} = \max(\mathrm{src0}_{i,j}, s_i) +$$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = trowexpandmax %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.trowexpandmax %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.trowexpandmax ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### IR Level 1 (SSA) + +```text +%dst = pto.trowexpandmax %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### IR Level 2 (DPS) + +```text +pto.trowexpandmax ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TROWEXPANDMAX(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, WaitEvents &... events); + +template +PTO_INST RecordEvent TROWEXPANDMAX(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, TileDataTmp &tmp, WaitEvents &... events); +``` + +## Constraints + +- `TileDataDst::DType == TileDataSrc0::DType == TileDataSrc1::DType` +- `TileDataDst::DType`, `TileDataSrc0::DType`, `TileDataSrc1::DType` must be one of: `half`, `float`. +- Tile shape/layout constraint (compile-time): `TileDataDst::isRowMajor`. +- Mode 1: `src1` is expected to provide **one scalar per row** (i.e., its valid shape must cover `R` values). +- Mode 2: `src1` is expected to provide **32 bytes data per row**. +- Exact layout/fractal constraints are target-specific; see backend headers under `include/pto/npu/*/TRowExpand*.hpp`. + +## Examples + +See related examples in `docs/isa/` and `docs/coding/tutorials/`. + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.trowexpandmax %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.trowexpandmax %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = trowexpandmax %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +# AS Level 2 (DPS) +pto.trowexpandmax ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TROWEXPANDMAX_zh.md b/designs/outerCube/PTOISA/TROWEXPANDMAX_zh.md new file mode 100644 index 00000000..f763dfa3 --- /dev/null +++ b/designs/outerCube/PTOISA/TROWEXPANDMAX_zh.md @@ -0,0 +1,79 @@ +# TROWEXPANDMAX + +## 指令示意图 + +![TROWEXPANDMAX tile operation](../figures/isa/TROWEXPANDMAX.svg) + +## 简介 + +行广播最大值：与每行标量向量取最大值。 + +## 数学语义 + +Let `R = dst.GetValidRow()` and `C = dst.GetValidCol()`. Let `s_i` be the per-row scalar taken from `src1` (one value per row). + +For `0 <= i < R` and `0 <= j < C`: + +$$ +\mathrm{dst}_{i,j} = \max(\mathrm{src0}_{i,j}, s_i) +$$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS Specification](../assembly/PTO-AS.md). + +同步形式： + +```text +%dst = trowexpandmax %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.trowexpandmax %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.trowexpandmax ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### AS Level 1（SSA） + +```text +%dst = pto.trowexpandmax %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.trowexpandmax ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TROWEXPANDMAX(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, WaitEvents &... events); + +template +PTO_INST RecordEvent TROWEXPANDMAX(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, TileDataTmp &tmp, WaitEvents &... events); +``` + +## 约束 + +- `TileDataDst::DType == TileDataSrc0::DType == TileDataSrc1::DType` +- `TileDataDst::DType`, `TileDataSrc0::DType`, `TileDataSrc1::DType` must be one of: `half`, `float`. +- Tile 形状/布局约束 (compile-time): `TileDataDst::isRowMajor`. +- Mode 1: `src1` is expected to provide **one scalar per row** (i.e., its valid shape must cover `R` values). +- Mode 2: `src1` is expected to provide **32 bytes data per row**. +- Exact layout/fractal constraints are target-specific; see backend headers under `include/pto/npu/*/TRowExpand*.hpp`. + +## 示例 + +See related examples in `docs/isa/` and `docs/coding/tutorials/`. diff --git a/designs/outerCube/PTOISA/TROWEXPANDMIN.md b/designs/outerCube/PTOISA/TROWEXPANDMIN.md new file mode 100644 index 00000000..e981807c --- /dev/null +++ b/designs/outerCube/PTOISA/TROWEXPANDMIN.md @@ -0,0 +1,106 @@ +# TROWEXPANDMIN + + +## Tile Operation Diagram + +![TROWEXPANDMIN tile operation](../figures/isa/TROWEXPANDMIN.svg) + +## Introduction + +Row-wise broadcast min: take `min(src0, src1)` where `src1` provides one scalar per row. + +## Math Interpretation + +Let `R = dst.GetValidRow()` and `C = dst.GetValidCol()`. Let `s_i` be the per-row scalar taken from `src1` (one value per row). + +For `0 <= i < R` and `0 <= j < C`: + +$$ +\mathrm{dst}_{i,j} = \min(\mathrm{src0}_{i,j}, s_i) +$$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = trowexpandmin %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.trowexpandmin %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.trowexpandmin ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### IR Level 1 (SSA) + +```text +%dst = pto.trowexpandmin %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### IR Level 2 (DPS) + +```text +pto.trowexpandmin ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TROWEXPANDMIN(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, WaitEvents &... events); + +template +PTO_INST RecordEvent TROWEXPANDMIN(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, TileDataTmp &tmp, WaitEvents &... events); +``` + +## Constraints + +- `TileDataDst::DType == TileDataSrc0::DType == TileDataSrc1::DType` +- `TileDataDst::DType`, `TileDataSrc0::DType`, `TileDataSrc1::DType` must be one of: `half`, `float`. +- Tile shape/layout constraint (compile-time): `TileDataDst::isRowMajor`. +- Mode 1: `src1` is expected to provide **one scalar per row** (i.e., its valid shape must cover `R` values). +- Mode 2: `src1` is expected to provide **32 bytes data per row**. +- Exact layout/fractal constraints are target-specific; see backend headers under `include/pto/npu/*/TRowExpand*.hpp`. + +## Examples + +See related examples in `docs/isa/` and `docs/coding/tutorials/`. + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.trowexpandmin %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.trowexpandmin %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = trowexpandmin %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +# AS Level 2 (DPS) +pto.trowexpandmin ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TROWEXPANDMIN_zh.md b/designs/outerCube/PTOISA/TROWEXPANDMIN_zh.md new file mode 100644 index 00000000..e3895fd9 --- /dev/null +++ b/designs/outerCube/PTOISA/TROWEXPANDMIN_zh.md @@ -0,0 +1,79 @@ +# TROWEXPANDMIN + +## 指令示意图 + +![TROWEXPANDMIN tile operation](../figures/isa/TROWEXPANDMIN.svg) + +## 简介 + +行广播最小值：与每行标量向量取最小值。 + +## 数学语义 + +Let `R = dst.GetValidRow()` and `C = dst.GetValidCol()`. Let `s_i` be the per-row scalar taken from `src1` (one value per row). + +For `0 <= i < R` and `0 <= j < C`: + +$$ +\mathrm{dst}_{i,j} = \min(\mathrm{src0}_{i,j}, s_i) +$$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS Specification](../assembly/PTO-AS.md). + +同步形式： + +```text +%dst = trowexpandmin %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.trowexpandmin %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.trowexpandmin ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### AS Level 1（SSA） + +```text +%dst = pto.trowexpandmin %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.trowexpandmin ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TROWEXPANDMIN(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, WaitEvents &... events); + +template +PTO_INST RecordEvent TROWEXPANDMIN(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, TileDataTmp &tmp, WaitEvents &... events); +``` + +## 约束 + +- `TileDataDst::DType == TileDataSrc0::DType == TileDataSrc1::DType` +- `TileDataDst::DType`, `TileDataSrc0::DType`, `TileDataSrc1::DType` must be one of: `half`, `float`. +- Tile 形状/布局约束 (compile-time): `TileDataDst::isRowMajor`. +- Mode 1: `src1` is expected to provide **one scalar per row** (i.e., its valid shape must cover `R` values). +- Mode 2: `src1` is expected to provide **32 bytes data per row**. +- Exact layout/fractal constraints are target-specific; see backend headers under `include/pto/npu/*/TRowExpand*.hpp`. + +## 示例 + +See related examples in `docs/isa/` and `docs/coding/tutorials/`. diff --git a/designs/outerCube/PTOISA/TROWEXPANDMUL.md b/designs/outerCube/PTOISA/TROWEXPANDMUL.md new file mode 100644 index 00000000..76a11fb4 --- /dev/null +++ b/designs/outerCube/PTOISA/TROWEXPANDMUL.md @@ -0,0 +1,126 @@ +# TROWEXPANDMUL + + +## Tile Operation Diagram + +![TROWEXPANDMUL tile operation](../figures/isa/TROWEXPANDMUL.svg) + +## Introduction + +Row-wise broadcast multiply: multiply each row of `src0` by a per-row scalar vector `src1`. + +## Math Interpretation + +For each element `(i, j)` in the valid region: + +$$ \mathrm{dst}_{i,j} = \mathrm{src0}_{i,j} \cdot \mathrm{src1}_{0,i} $$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = trowexpandmul %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.trowexpandmul %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.trowexpandmul ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TROWEXPANDMUL(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, WaitEvents &... events); + +template +PTO_INST RecordEvent TROWEXPANDMUL(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, TileDataTmp &tmp, WaitEvents &... events); +``` + +## Constraints + +- **Implementation checks**: + - `TileDataDst::DType == TileDataSrc0::DType == TileDataSrc1::DType` (compile-time). + - `TileDataDst::DType`, `TileDataSrc0::DType`, `TileDataSrc1::DType` must be one of: `half`, `float`. + - Tile shape/layout constraint (compile-time): `TileDataDst::isRowMajor`. + - Mode 1: `src1` is expected to provide **one scalar per row** (i.e., its valid shape must cover `R` values). + - Mode 2: `src1` is expected to provide **32 bytes data per row**. + +## Examples + +### Auto + +```cpp +#include + +using namespace pto; + +void example_auto() { + using TileT = Tile; + using RowVecT = Tile; + + TileT src0, dst; + RowVecT src1(16); + TROWEXPANDMUL(dst, src0, src1); +} +``` + +### Manual + +```cpp +#include + +using namespace pto; + +void example_manual() { + using TileT = Tile; + using RowVecT = Tile; + + TileT src0, dst; + RowVecT src1(16); + TASSIGN(src0, 0x1000); + TASSIGN(dst, 0x2000); + TASSIGN(src1, 0x3000); + TROWEXPANDMUL(dst, src0, src1); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.trowexpandmul %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.trowexpandmul %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = trowexpandmul %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +# AS Level 2 (DPS) +pto.trowexpandmul ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/TROWEXPANDMUL_zh.md b/designs/outerCube/PTOISA/TROWEXPANDMUL_zh.md new file mode 100644 index 00000000..f27d717f --- /dev/null +++ b/designs/outerCube/PTOISA/TROWEXPANDMUL_zh.md @@ -0,0 +1,126 @@ +# TROWEXPANDMUL + +## 指令示意图 + +![TROWEXPANDMUL tile operation](../figures/isa/TROWEXPANDMUL.svg) + +## 简介 + +行广播乘法：将 `src0` 的每一行乘以一个每行标量向量 `src1`。 + +## 数学语义 + +对每个元素 `(i, j)` 在有效区域内： + +$$ \mathrm{dst}_{i,j} = \mathrm{src0}_{i,j} \cdot \mathrm{src1}_{0,i} $$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS 规范](../assembly/PTO-AS_zh.md)。 + +同步形式： + +```text +%dst = trowexpandmul %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 1（SSA） + +```text +%dst = pto.trowexpandmul %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.trowexpandmul ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`： + +```cpp +template +PTO_INST RecordEvent TROWEXPANDMUL(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, WaitEvents &... events); + +template +PTO_INST RecordEvent TROWEXPANDMUL(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, TileDataTmp &tmp, WaitEvents &... events); +``` + +## 约束 + +- **实现检查**: + - `TileDataDst::DType == TileDataSrc0::DType == TileDataSrc1::DType`（编译时）。 + - `TileDataDst::DType`、`TileDataSrc0::DType`、`TileDataSrc1::DType` 必须是以下之一：`half`、`float`。 + - Tile 形状/布局约束（编译时）：`TileDataDst::isRowMajor`。 + - 模式 1：`src1` 预期提供**每行一个标量**（即，其有效形状必须覆盖 `R` 个值）。 + - 模式 2：`src1` 预期提供**每行 32 字节数据**。 + +## 示例 + +### 自动（Auto） + +```cpp +#include + +using namespace pto; + +void example_auto() { + using TileT = Tile; + using RowVecT = Tile; + + TileT src0, dst; + RowVecT src1(16); + TROWEXPANDMUL(dst, src0, src1); +} +``` + +### 手动（Manual） + +```cpp +#include + +using namespace pto; + +void example_manual() { + using TileT = Tile; + using RowVecT = Tile; + + TileT src0, dst; + RowVecT src1(16); + TASSIGN(src0, 0x1000); + TASSIGN(dst, 0x2000); + TASSIGN(src1, 0x3000); + TROWEXPANDMUL(dst, src0, src1); +} +``` + +## 汇编示例（ASM） + +### 自动模式 + +```text +# 自动模式：由编译器/运行时负责资源放置与调度。 +%dst = pto.trowexpandmul %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### 手动模式 + +```text +# 手动模式：先显式绑定资源，再发射指令。 +# 可选（当该指令包含 tile 操作数时）： +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.trowexpandmul %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### PTO 汇编形式 + +```text +%dst = trowexpandmul %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +# AS Level 2 (DPS) +pto.trowexpandmul ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/TROWEXPANDSUB.md b/designs/outerCube/PTOISA/TROWEXPANDSUB.md new file mode 100644 index 00000000..15f38477 --- /dev/null +++ b/designs/outerCube/PTOISA/TROWEXPANDSUB.md @@ -0,0 +1,126 @@ +# TROWEXPANDSUB + + +## Tile Operation Diagram + +![TROWEXPANDSUB tile operation](../figures/isa/TROWEXPANDSUB.svg) + +## Introduction + +Row-wise broadcast subtract: subtract a per-row scalar vector `src1` from each row of `src0`. + +## Math Interpretation + +For each element `(i, j)` in the valid region: + +$$ \mathrm{dst}_{i,j} = \mathrm{src0}_{i,j} - \mathrm{src1}_{0,i} $$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = trowexpandsub %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.trowexpandsub %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.trowexpandsub ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TROWEXPANDSUB(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, WaitEvents &... events); + +template +PTO_INST RecordEvent TROWEXPANDSUB(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, TileDataTmp &tmp, WaitEvents &... events); +``` + +## Constraints + +- **Implementation checks**: + - `TileDataDst::DType == TileDataSrc0::DType == TileDataSrc1::DType` (compile-time). + - `TileDataDst::DType`, `TileDataSrc0::DType`, `TileDataSrc1::DType` must be one of: `half`, `float`. + - Tile shape/layout constraint (compile-time): `TileDataDst::isRowMajor`. + - Mode 1: `src1` is expected to provide **one scalar per row** (i.e., its valid shape must cover `R` values). + - Mode 2: `src1` is expected to provide **32 bytes data per row**. + +## Examples + +### Auto + +```cpp +#include + +using namespace pto; + +void example_auto() { + using TileT = Tile; + using RowVecT = Tile; + + TileT src0, dst; + RowVecT src1(16); + TROWEXPANDSUB(dst, src0, src1); +} +``` + +### Manual + +```cpp +#include + +using namespace pto; + +void example_manual() { + using TileT = Tile; + using RowVecT = Tile; + + TileT src0, dst; + RowVecT src1(16); + TASSIGN(src0, 0x1000); + TASSIGN(dst, 0x2000); + TASSIGN(src1, 0x3000); + TROWEXPANDSUB(dst, src0, src1); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.trowexpandsub %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.trowexpandsub %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = trowexpandsub %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +# AS Level 2 (DPS) +pto.trowexpandsub ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/TROWEXPANDSUB_zh.md b/designs/outerCube/PTOISA/TROWEXPANDSUB_zh.md new file mode 100644 index 00000000..d1dad849 --- /dev/null +++ b/designs/outerCube/PTOISA/TROWEXPANDSUB_zh.md @@ -0,0 +1,126 @@ +# TROWEXPANDSUB + +## 指令示意图 + +![TROWEXPANDSUB tile operation](../figures/isa/TROWEXPANDSUB.svg) + +## 简介 + +行广播减法：从 `src0` 的每一行中减去一个每行标量向量 `src1`。 + +## 数学语义 + +对每个元素 `(i, j)` 在有效区域内： + +$$ \mathrm{dst}_{i,j} = \mathrm{src0}_{i,j} - \mathrm{src1}_{0,i} $$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS 规范](../assembly/PTO-AS_zh.md)。 + +同步形式： + +```text +%dst = trowexpandsub %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 1（SSA） + +```text +%dst = pto.trowexpandsub %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.trowexpandsub ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`： + +```cpp +template +PTO_INST RecordEvent TROWEXPANDSUB(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, WaitEvents &... events); + +template +PTO_INST RecordEvent TROWEXPANDSUB(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, TileDataTmp &tmp, WaitEvents &... events); +``` + +## 约束 + +- **实现检查**: + - `TileDataDst::DType == TileDataSrc0::DType == TileDataSrc1::DType`（编译时）。 + - `TileDataDst::DType`、`TileDataSrc0::DType`、`TileDataSrc1::DType` 必须是以下之一：`half`、`float`。 + - Tile 形状/布局约束（编译时）：`TileDataDst::isRowMajor`。 + - 模式 1：`src1` 预期提供**每行一个标量**（即，其有效形状必须覆盖 `R` 个值）。 + - 模式 2：`src1` 预期提供**每行 32 字节数据**。 + +## 示例 + +### 自动（Auto） + +```cpp +#include + +using namespace pto; + +void example_auto() { + using TileT = Tile; + using RowVecT = Tile; + + TileT src0, dst; + RowVecT src1(16); + TROWEXPANDSUB(dst, src0, src1); +} +``` + +### 手动（Manual） + +```cpp +#include + +using namespace pto; + +void example_manual() { + using TileT = Tile; + using RowVecT = Tile; + + TileT src0, dst; + RowVecT src1(16); + TASSIGN(src0, 0x1000); + TASSIGN(dst, 0x2000); + TASSIGN(src1, 0x3000); + TROWEXPANDSUB(dst, src0, src1); +} +``` + +## 汇编示例（ASM） + +### 自动模式 + +```text +# 自动模式：由编译器/运行时负责资源放置与调度。 +%dst = pto.trowexpandsub %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### 手动模式 + +```text +# 手动模式：先显式绑定资源，再发射指令。 +# 可选（当该指令包含 tile 操作数时）： +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.trowexpandsub %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### PTO 汇编形式 + +```text +%dst = trowexpandsub %src0, %src1 : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +# AS Level 2 (DPS) +pto.trowexpandsub ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/TROWEXPAND_zh.md b/designs/outerCube/PTOISA/TROWEXPAND_zh.md new file mode 100644 index 00000000..d0dd216d --- /dev/null +++ b/designs/outerCube/PTOISA/TROWEXPAND_zh.md @@ -0,0 +1,105 @@ +# TROWEXPAND + +## 指令示意图 + +![TROWEXPAND tile operation](../figures/isa/TROWEXPAND.svg) + +## 简介 + +将每个源行的第一个元素广播到目标行中。 + +## 数学语义 + +Let `R = dst.GetValidRow()` and `C = dst.GetValidCol()`. For `0 <= i < R` and `0 <= j < C`: + +$$ \mathrm{dst}_{i,j} = \mathrm{src}_{i,0} $$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS Specification](../assembly/PTO-AS.md). + +同步形式： + +```text +%dst = trowexpand %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.trowexpand %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.trowexpand ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### AS Level 1（SSA） + +```text +%dst = pto.trowexpand %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.trowexpand ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TROWEXPAND(TileDataDst &dst, TileDataSrc &src, WaitEvents &... events); +``` + +## 约束 + +实现检查 (NPU): + +- Tile Type: `dst` and `src` must be `TileType::Vec`. +- Tile 布局: ND fractal (`isRowMajor` and `SLayout::NoneBox`) for both `src` and `dst`. +- Data type: A2A3/A5 element types must be one of: `int8_t` or `uint8_t` or `int16_t` or `uint16_t` or `int32_t` or `uint32_t` or `half` or `bfloat16_t` or `float`. +- 运行期有效区域检查: + - A2A3: returns early if any of `dstValidRow`, `dstValidCol`, `srcValidRow`, `srcValidCol` is zero. + - A5: asserts `srcValidRow == dstValidRow` and asserts `srcValidRow != 0 && srcValidCol != 0`. + +## 示例 + +### 自动（Auto） + +```cpp +#include + +using namespace pto; + +void example_auto() { + using SrcT = Tile; + using DstT = Tile; + SrcT src; + DstT dst; + TROWEXPAND(dst, src); +} +``` + +### 手动（Manual） + +```cpp +#include + +using namespace pto; + +void example_manual() { + using SrcT = Tile; + using DstT = Tile; + SrcT src; + DstT dst; + TASSIGN(src, 0x1000); + TASSIGN(dst, 0x2000); + TROWEXPAND(dst, src); +} +``` diff --git a/designs/outerCube/PTOISA/TROWMAX.md b/designs/outerCube/PTOISA/TROWMAX.md new file mode 100644 index 00000000..67c2254c --- /dev/null +++ b/designs/outerCube/PTOISA/TROWMAX.md @@ -0,0 +1,135 @@ +# TROWMAX + + +## Tile Operation Diagram + +![TROWMAX tile operation](../figures/isa/TROWMAX.svg) + +## Introduction + +Reduce each row by taking the maximum across columns. + +## Math Interpretation + +Let `R = src.GetValidRow()` and `C = src.GetValidCol()`. For `0 <= i < R`: + +$$ \mathrm{dst}_{i,0} = \max_{0 \le j < C} \mathrm{src}_{i,j} $$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = trowmax %src : !pto.tile<...> -> !pto.tile<...> +``` +Lowering may introduce internal scratch tiles; the C++ intrinsic requires an explicit `tmp` operand. + +### AS Level 1 (SSA) + +```text +%dst = pto.trowmax %src, %tmp : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.trowmax ins(%src, %tmp : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TROWMAX(TileDataOut &dst, TileDataIn &src, TileDataTmp &tmp, WaitEvents &... events); +``` + +## Constraints + +Implementation checks (NPU): + +- A2A3: + - Tile location: `dst` and `src` must be `TileType::Vec`. + - Tile layout of `src`: ND fractal (`isRowMajor` and `SLayout::NoneBox`). + - Tile layout of `dst`: + - **Compact Mode**: DN layout Tile of 1D, e.g., `Tile`, ROWS must be 32b aligned. + - **Traditional Mode**: ND layout Tile of 2D, e.g., `Tile`. + - Data types: `half` or `float`. + - DType consistency: `dst.DType == src.DType`. + - Runtime valid checks: + - `srcValidCol != 0` and `srcValidRow != 0`. + - `srcValidRow == dstValidRow` (the output valid row must match the input valid row). +- A5: + - Data types: `half` or `float`. + - DType consistency: `dst.DType == src.DType`. + - No explicit runtime assertions on `validRow/validCol` in the implementation; the loops use `src.GetValidRow()` and `src.GetValidCol()`. + +## Examples + +### Auto + +```cpp +#include + +using namespace pto; + +void example_auto() { + using SrcT = Tile; + using DstT = Tile; + using TmpT = Tile; + SrcT src; + DstT dst; + TmpT tmp; + TROWMAX(dst, src, tmp); +} +``` + +### Manual + +```cpp +#include + +using namespace pto; + +void example_manual() { + using SrcT = Tile; + using DstT = Tile; + using TmpT = Tile; + SrcT src; + DstT dst; + TmpT tmp; + TASSIGN(src, 0x1000); + TASSIGN(dst, 0x2000); + TASSIGN(tmp, 0x3000); + TROWMAX(dst, src, tmp); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.trowmax %src, %tmp : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.trowmax %src, %tmp : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = trowmax %src : !pto.tile<...> -> !pto.tile<...> +# AS Level 2 (DPS) +pto.trowmax ins(%src, %tmp : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TROWMAX_zh.md b/designs/outerCube/PTOISA/TROWMAX_zh.md new file mode 100644 index 00000000..1795309c --- /dev/null +++ b/designs/outerCube/PTOISA/TROWMAX_zh.md @@ -0,0 +1,135 @@ +# TROWMAX + +## 指令示意图 + +![TROWMAX tile operation](../figures/isa/TROWMAX.svg) + +## 简介 + +通过取列间最大值来归约每一行。 + +## 数学语义 + +设 `R = src.GetValidRow()`，`C = src.GetValidCol()`。对 `0 <= i < R`： + +$$ \mathrm{dst}_{i,0} = \max_{0 \le j < C} \mathrm{src}_{i,j} $$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS 规范](../assembly/PTO-AS_zh.md)。 + +同步形式： + +```text +%dst = trowmax %src : !pto.tile<...> -> !pto.tile<...> +``` +降低时可能引入内部临时 Tile；C++ 内建接口需要显式传入 `tmp` 操作数。 + +### AS Level 1（SSA） + +```text +%dst = pto.trowmax %src, %tmp : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.trowmax ins(%src, %tmp : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`： + +```cpp +template +PTO_INST RecordEvent TROWMAX(TileDataOut &dst, TileDataIn &src, TileDataTmp &tmp, WaitEvents &... events); +``` + +## 约束 + +实现检查 (NPU): + +- A2A3: + - Tile 位置：`dst` 和 `src` 必须是 `TileType::Vec`。 + - `src` 的 Tile 布局：ND 分形（`isRowMajor` 且 `SLayout::NoneBox`）。 + - `dst` 的 Tile 布局： + - **紧凑模式**：DN 布局的一维 Tile，例如 `Tile`，此时ROWS要做到32b对齐。 + - **传统模式**：ND 布局的二维 Tile，例如 `Tile`。 + - 数据类型：`half` 或 `float`。 + - 数据类型一致性：`dst.DType == src.DType`。 + - 运行期有效区域检查： + - `srcValidCol != 0` 且 `srcValidRow != 0`。 + - `srcValidRow == dstValidRow`（输出有效行数必须与输入有效行数匹配）。 +- A5: + - 数据类型：`half` 或 `float`。 + - 数据类型一致性：`dst.DType == src.DType`。 + - 实现中对 `validRow/validCol` 无显式运行时断言；循环使用 `src.GetValidRow()` 和 `src.GetValidCol()`。 + +## 示例 + +### 自动（Auto） + +```cpp +#include + +using namespace pto; + +void example_auto() { + using SrcT = Tile; + using DstT = Tile; + using TmpT = Tile; + SrcT src; + DstT dst; + TmpT tmp; + TROWMAX(dst, src, tmp); +} +``` + +### 手动（Manual） + +```cpp +#include + +using namespace pto; + +void example_manual() { + using SrcT = Tile; + using DstT = Tile; + using TmpT = Tile; + SrcT src; + DstT dst; + TmpT tmp; + TASSIGN(src, 0x1000); + TASSIGN(dst, 0x2000); + TASSIGN(tmp, 0x3000); + TROWMAX(dst, src, tmp); +} +``` + +## 汇编示例（ASM） + +### 自动模式 + +```text +# 自动模式：由编译器/运行时负责资源放置与调度。 +%dst = pto.trowmax %src, %tmp : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### 手动模式 + +```text +# 手动模式：先显式绑定资源，再发射指令。 +# 可选（当该指令包含 tile 操作数时）： +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.trowmax %src, %tmp : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### PTO 汇编形式 + +```text +%dst = trowmax %src : !pto.tile<...> -> !pto.tile<...> +# AS Level 2 (DPS) +pto.trowmax ins(%src, %tmp : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TROWMIN.md b/designs/outerCube/PTOISA/TROWMIN.md new file mode 100644 index 00000000..ab60bbe7 --- /dev/null +++ b/designs/outerCube/PTOISA/TROWMIN.md @@ -0,0 +1,135 @@ +# TROWMIN + + +## Tile Operation Diagram + +![TROWMIN tile operation](../figures/isa/TROWMIN.svg) + +## Introduction + +Reduce each row by taking the minimum across columns. + +## Math Interpretation + +Let `R = src.GetValidRow()` and `C = src.GetValidCol()`. For `0 <= i < R`: + +$$ \mathrm{dst}_{i,0} = \min_{0 \le j < C} \mathrm{src}_{i,j} $$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = trowmin %src : !pto.tile<...> -> !pto.tile<...> +``` +Lowering may introduce internal scratch tiles; the C++ intrinsic requires an explicit `tmp` operand. + +### AS Level 1 (SSA) + +```text +%dst = pto.trowmin %src, %tmp : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.trowmin ins(%src, %tmp : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TROWMIN(TileDataOut &dst, TileDataIn &src, TileDataTmp &tmp, WaitEvents &... events); +``` + +## Constraints + +Implementation checks (NPU): + +- A2A3: + - Tile location: `dst` and `src` must be `TileType::Vec`. + - Tile layout of `src`: ND fractal (`isRowMajor` and `SLayout::NoneBox`). + - Tile layout of `dst`: + - **Compact Mode**: DN layout Tile of 1D, e.g., `Tile`, ROWS must be 32b aligned. + - **Traditional Mode**: ND layout Tile of 2D, e.g., `Tile`. + - Data types: `half` or `float`. + - DType consistency: `dst.DType == src.DType`. + - Runtime valid checks: + - `srcValidCol != 0` and `srcValidRow != 0`. + - `srcValidRow == dstValidRow` (the output valid row must match the input valid row). +- A5: + - Data types: `half` or `float`. + - DType consistency: `dst.DType == src.DType`. + - No explicit runtime assertions on `validRow/validCol` in the implementation; the loops use `src.GetValidRow()` and `src.GetValidCol()`. + +## Examples + +### Auto + +```cpp +#include + +using namespace pto; + +void example_auto() { + using SrcT = Tile; + using DstT = Tile; + using TmpT = Tile; + SrcT src; + DstT dst; + TmpT tmp; + TROWMIN(dst, src, tmp); +} +``` + +### Manual + +```cpp +#include + +using namespace pto; + +void example_manual() { + using SrcT = Tile; + using DstT = Tile; + using TmpT = Tile; + SrcT src; + DstT dst; + TmpT tmp; + TASSIGN(src, 0x1000); + TASSIGN(dst, 0x2000); + TASSIGN(tmp, 0x3000); + TROWMIN(dst, src, tmp); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.trowmin %src, %tmp : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.trowmin %src, %tmp : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = trowmin %src : !pto.tile<...> -> !pto.tile<...> +# AS Level 2 (DPS) +pto.trowmin ins(%src, %tmp : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TROWMIN_zh.md b/designs/outerCube/PTOISA/TROWMIN_zh.md new file mode 100644 index 00000000..8cd11fc2 --- /dev/null +++ b/designs/outerCube/PTOISA/TROWMIN_zh.md @@ -0,0 +1,135 @@ +# TROWMIN + +## 指令示意图 + +![TROWMIN tile operation](../figures/isa/TROWMIN.svg) + +## 简介 + +通过取列间最小值来归约每一行。 + +## 数学语义 + +设 `R = src.GetValidRow()`，`C = src.GetValidCol()`。对 `0 <= i < R`： + +$$ \mathrm{dst}_{i,0} = \min_{0 \le j < C} \mathrm{src}_{i,j} $$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS 规范](../assembly/PTO-AS_zh.md)。 + +同步形式： + +```text +%dst = trowmin %src : !pto.tile<...> -> !pto.tile<...> +``` +降低时可能引入内部临时 Tile；C++ 内建接口需要显式传入 `tmp` 操作数。 + +### AS Level 1（SSA） + +```text +%dst = pto.trowmin %src, %tmp : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.trowmin ins(%src, %tmp : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`： + +```cpp +template +PTO_INST RecordEvent TROWMIN(TileDataOut &dst, TileDataIn &src, TileDataTmp &tmp, WaitEvents &... events); +``` + +## 约束 + +实现检查 (NPU): + +- A2A3: + - Tile 位置：`dst` 和 `src` 必须是 `TileType::Vec`。 + - `src` 的 Tile 布局：ND 分形（`isRowMajor` 且 `SLayout::NoneBox`）。 + - `dst` 的 Tile 布局： + - **紧凑模式**：DN 布局的一维 Tile，例如 `Tile`，此时ROWS要做到32b对齐。 + - **传统模式**：ND 布局的二维 Tile，例如 `Tile`。 + - 数据类型：`half` 或 `float`。 + - 数据类型一致性：`dst.DType == src.DType`。 + - 运行期有效区域检查： + - `srcValidCol != 0` 且 `srcValidRow != 0`。 + - `srcValidRow == dstValidRow`（输出有效行数必须与输入有效行数匹配）。 +- A5: + - 数据类型：`half` 或 `float`。 + - 数据类型一致性：`dst.DType == src.DType`。 + - 实现中对 `validRow/validCol` 无显式运行时断言；循环使用 `src.GetValidRow()` 和 `src.GetValidCol()`。 + +## 示例 + +### 自动（Auto） + +```cpp +#include + +using namespace pto; + +void example_auto() { + using SrcT = Tile; + using DstT = Tile; + using TmpT = Tile; + SrcT src; + DstT dst; + TmpT tmp; + TROWMIN(dst, src, tmp); +} +``` + +### 手动（Manual） + +```cpp +#include + +using namespace pto; + +void example_manual() { + using SrcT = Tile; + using DstT = Tile; + using TmpT = Tile; + SrcT src; + DstT dst; + TmpT tmp; + TASSIGN(src, 0x1000); + TASSIGN(dst, 0x2000); + TASSIGN(tmp, 0x3000); + TROWMIN(dst, src, tmp); +} +``` + +## 汇编示例（ASM） + +### 自动模式 + +```text +# 自动模式：由编译器/运行时负责资源放置与调度。 +%dst = pto.trowmin %src, %tmp : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### 手动模式 + +```text +# 手动模式：先显式绑定资源，再发射指令。 +# 可选（当该指令包含 tile 操作数时）： +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.trowmin %src, %tmp : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### PTO 汇编形式 + +```text +%dst = trowmin %src : !pto.tile<...> -> !pto.tile<...> +# AS Level 2 (DPS) +pto.trowmin ins(%src, %tmp : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TROWPROD.md b/designs/outerCube/PTOISA/TROWPROD.md new file mode 100644 index 00000000..dfd49a18 --- /dev/null +++ b/designs/outerCube/PTOISA/TROWPROD.md @@ -0,0 +1,150 @@ +# TROWPROD + + +## Tile Operation Diagram + +![TROWPROD tile operation](../figures/isa/TROWPROD.svg) + +## Introduction + +Reduce each row by multiplying across columns. + +## Math Interpretation + +Let `R = src.GetValidRow()` and `C = src.GetValidCol()`. For `0 <= i < R`: + +$$ \mathrm{dst}_{i,0} = \prod_{j=0}^{C-1} \mathrm{src}_{i,j} $$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = trowprod %src : !pto.tile<...> -> !pto.tile<...> +``` +Lowering may introduce internal scratch tiles; the C++ intrinsic requires an explicit `tmp` operand. + +### AS Level 1 (SSA) + +```text +%dst = pto.trowprod %src, %tmp : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.trowprod ins(%src, %tmp : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### IR Level 1 (SSA) + +```text +%dst = pto.trowprod %src : !pto.tile<...> -> !pto.tile<...> +``` + +### IR Level 2 (DPS) + +```text +pto.trowprod ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TROWPROD(TileDataOut &dst, TileDataIn &src, TileDataTmp &tmp, WaitEvents &... events); +``` + +## Constraints + +Implementation checks (NPU): + +- A2A3: + - Tile location: `dst` and `src` must be `TileType::Vec`. + - Tile layout of `src`: ND fractal (`isRowMajor` and `SLayout::NoneBox`). + - Tile layout of `dst`: DN layout Tile of 1D, e.g., `Tile` + - Data types: `half`, `float`. + - DType consistency: `dst.DType == src.DType`. + - Runtime valid checks: + - `srcValidCol != 0` and `srcValidRow != 0`. + - `srcValidRow == dstValidRow` (the output valid row must match the input valid row). + - `tmp` must have the same shape as `src`. + +## Implementation Notes + +Unlike TROWSUM which uses `vcadd`/`vcgadd` instructions, TROWPROD uses binary reduction with `vmul` since there is no `vcmul` instruction available on A2A3. The implementation: + +1. Multiplies adjacent repeat pairs and stores results in `tmp` +2. Iteratively performs binary multiplication reduction on `tmp` +3. Continues until each row has only one element + +## Examples + +### Auto + +```cpp +#include + +using namespace pto; + +void example_auto() { + using SrcT = Tile; + using DstT = Tile; + using TmpT = Tile; + SrcT src; + DstT dst; + TmpT tmp; + TROWPROD(dst, src, tmp); +} +``` + +### Manual + +```cpp +#include + +using namespace pto; + +void example_manual() { + using SrcT = Tile; + using DstT = Tile; + using TmpT = Tile; + SrcT src; + DstT dst; + TmpT tmp; + TASSIGN(src, 0x1000); + TASSIGN(dst, 0x2000); + TASSIGN(tmp, 0x3000); + TROWPROD(dst, src, tmp); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.trowprod %src, %tmp : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.trowprod %src, %tmp : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = trowprod %src : !pto.tile<...> -> !pto.tile<...> +# AS Level 2 (DPS) +pto.trowprod ins(%src, %tmp : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TROWPROD_zh.md b/designs/outerCube/PTOISA/TROWPROD_zh.md new file mode 100644 index 00000000..7863b14d --- /dev/null +++ b/designs/outerCube/PTOISA/TROWPROD_zh.md @@ -0,0 +1,115 @@ +# TROWPROD + +## 指令示意图 + +![TROWPROD tile operation](../figures/isa/TROWPROD.svg) + +## 简介 + +对每一行沿列方向连乘归约。 + +## 数学语义 + +Let `R = src.GetValidRow()` and `C = src.GetValidCol()`. For `0 <= i < R`: + +$$ \mathrm{dst}_{i,0} = \prod_{j=0}^{C-1} \mathrm{src}_{i,j} $$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS Specification](../assembly/PTO-AS.md). + +同步形式： + +```text +%dst = trowprod %src : !pto.tile<...> -> !pto.tile<...> +``` +Lowering may introduce internal scratch tiles; the C++ intrinsic requires an explicit `tmp` operand. + +### AS Level 1 (SSA) + +```text +%dst = pto.trowprod %src, %tmp : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.trowprod ins(%src, %tmp : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### AS Level 1（SSA） + +```text +%dst = pto.trowprod %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.trowprod ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TROWPROD(TileDataOut &dst, TileDataIn &src, TileDataTmp &tmp, WaitEvents &... events); +``` + +## 约束 + +实现检查 (NPU): + +- A2A3: + - Tile location: `dst` and `src` must be `TileType::Vec`. + - Tile 布局 of `src`: ND fractal (`isRowMajor` and `SLayout::NoneBox`). + - Tile 布局 of `dst`: DN layout Tile of 1D, e.g., `Tile` + - 数据类型: `half`, `float`. + - 数据类型一致性: `dst.DType == src.DType`. + - 运行期有效区域检查: + - `srcValidCol != 0` and `srcValidRow != 0`. + - `srcValidRow == dstValidRow` (the output valid row must match the input valid row). + - `tmp` must have the same shape as `src`. + +## 示例 + +### 自动（Auto） + +```cpp +#include + +using namespace pto; + +void example_auto() { + using SrcT = Tile; + using DstT = Tile; + using TmpT = Tile; + SrcT src; + DstT dst; + TmpT tmp; + TROWPROD(dst, src, tmp); +} +``` + +### 手动（Manual） + +```cpp +#include + +using namespace pto; + +void example_manual() { + using SrcT = Tile; + using DstT = Tile; + using TmpT = Tile; + SrcT src; + DstT dst; + TmpT tmp; + TASSIGN(src, 0x1000); + TASSIGN(dst, 0x2000); + TASSIGN(tmp, 0x3000); + TROWPROD(dst, src, tmp); +} +``` diff --git a/designs/outerCube/PTOISA/TROWSUM.md b/designs/outerCube/PTOISA/TROWSUM.md new file mode 100644 index 00000000..44944d24 --- /dev/null +++ b/designs/outerCube/PTOISA/TROWSUM.md @@ -0,0 +1,147 @@ +# TROWSUM + + +## Tile Operation Diagram + +![TROWSUM tile operation](../figures/isa/TROWSUM.svg) + +## Introduction + +Reduce each row by summing across columns. + +## Math Interpretation + +Let `R = src.GetValidRow()` and `C = src.GetValidCol()`. For `0 <= i < R`: + +$$ \mathrm{dst}_{i,0} = \sum_{j=0}^{C-1} \mathrm{src}_{i,j} $$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = trowsum %src : !pto.tile<...> -> !pto.tile<...> +``` +Lowering may introduce internal scratch tiles; the C++ intrinsic requires an explicit `tmp` operand. + +### AS Level 1 (SSA) + +```text +%dst = pto.trowsum %src, %tmp : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.trowsum ins(%src, %tmp : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### IR Level 1 (SSA) + +```text +%dst = pto.trowsum %src, %tmp : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### IR Level 2 (DPS) + +```text +pto.trowsum ins(%src, %tmp : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TROWSUM(TileDataOut &dst, TileDataIn &src, TileDataTmp &tmp, WaitEvents &... events); +``` + +## Constraints + +Implementation checks (NPU): + +- A2A3: + - Tile location: `dst` and `src` must be `TileType::Vec`. + - Tile layout of `src`: ND fractal (`isRowMajor` and `SLayout::NoneBox`). + - Tile layout of `dst`: + - **Recommended**: DN layout Tile of 1D, e.g., `Tile` + - **To be removed**: ND layout Tile of 2D, e.g., `Tile` + - Data types: `half` or `float`. + - DType consistency: `dst.DType == src.DType`. + - Runtime valid checks: + - `srcValidCol != 0` and `srcValidRow != 0`. + - `srcValidRow == dstValidRow` (the output valid row must match the input valid row). +- A5: + - Data types: `half` or `float`. + - DType consistency: `dst.DType == src.DType`. + - No explicit runtime assertions on `validRow/validCol` in the implementation; the loops use `src.GetValidRow()` and `src.GetValidCol()`. + +## Examples + +### Auto + +```cpp +#include + +using namespace pto; + +void example_auto() { + using SrcT = Tile; + using DstT = Tile; + using TmpT = Tile; + SrcT src; + DstT dst; + TmpT tmp; + TROWSUM(dst, src, tmp); +} +``` + +### Manual + +```cpp +#include + +using namespace pto; + +void example_manual() { + using SrcT = Tile; + using DstT = Tile; + using TmpT = Tile; + SrcT src; + DstT dst; + TmpT tmp; + TASSIGN(src, 0x1000); + TASSIGN(dst, 0x2000); + TASSIGN(tmp, 0x3000); + TROWSUM(dst, src, tmp); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.trowsum %src, %tmp : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.trowsum %src, %tmp : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = trowsum %src : !pto.tile<...> -> !pto.tile<...> +# AS Level 2 (DPS) +pto.trowsum ins(%src, %tmp : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TROWSUM_zh.md b/designs/outerCube/PTOISA/TROWSUM_zh.md new file mode 100644 index 00000000..527f4e02 --- /dev/null +++ b/designs/outerCube/PTOISA/TROWSUM_zh.md @@ -0,0 +1,120 @@ +# TROWSUM + +## 指令示意图 + +![TROWSUM tile operation](../figures/isa/TROWSUM.svg) + +## 简介 + +通过对列求和来归约每一行。 + +## 数学语义 + +Let `R = src.GetValidRow()` and `C = src.GetValidCol()`. For `0 <= i < R`: + +$$ \mathrm{dst}_{i,0} = \sum_{j=0}^{C-1} \mathrm{src}_{i,j} $$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS Specification](../assembly/PTO-AS.md). + +同步形式： + +```text +%dst = trowsum %src : !pto.tile<...> -> !pto.tile<...> +``` +Lowering may introduce internal scratch tiles; the C++ intrinsic requires an explicit `tmp` operand. + +### AS Level 1 (SSA) + +```text +%dst = pto.trowsum %src, %tmp : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.trowsum ins(%src, %tmp : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### AS Level 1（SSA） + +```text +%dst = pto.trowsum %src, %tmp : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.trowsum ins(%src, %tmp : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TROWSUM(TileDataOut &dst, TileDataIn &src, TileDataTmp &tmp, WaitEvents &... events); +``` + +## 约束 + +实现检查 (NPU): + +- A2A3: + - Tile location: `dst` and `src` must be `TileType::Vec`. + - Tile 布局 of `src`: ND fractal (`isRowMajor` and `SLayout::NoneBox`). + - Tile 布局 of `dst`: + - **推荐**: DN layout Tile of 1D, e.g., `Tile` + - **将移除**: ND layout Tile of 2D, e.g., `Tile` + - 数据类型: `half` or `float`. + - 数据类型一致性: `dst.DType == src.DType`. + - 运行期有效区域检查: + - `srcValidCol != 0` and `srcValidRow != 0`. + - `srcValidRow == dstValidRow` (the output valid row must match the input valid row). +- A5: + - 数据类型: `half` or `float`. + - 数据类型一致性: `dst.DType == src.DType`. + - No explicit runtime assertions on `validRow/validCol` in the implementation; the loops use `src.GetValidRow()` and `src.GetValidCol()`. + +## 示例 + +### 自动（Auto） + +```cpp +#include + +using namespace pto; + +void example_auto() { + using SrcT = Tile; + using DstT = Tile; + using TmpT = Tile; + SrcT src; + DstT dst; + TmpT tmp; + TROWSUM(dst, src, tmp); +} +``` + +### 手动（Manual） + +```cpp +#include + +using namespace pto; + +void example_manual() { + using SrcT = Tile; + using DstT = Tile; + using TmpT = Tile; + SrcT src; + DstT dst; + TmpT tmp; + TASSIGN(src, 0x1000); + TASSIGN(dst, 0x2000); + TASSIGN(tmp, 0x3000); + TROWSUM(dst, src, tmp); +} +``` diff --git a/designs/outerCube/PTOISA/TRSQRT.md b/designs/outerCube/PTOISA/TRSQRT.md new file mode 100644 index 00000000..10e58013 --- /dev/null +++ b/designs/outerCube/PTOISA/TRSQRT.md @@ -0,0 +1,134 @@ +# TRSQRT + + +## Tile Operation Diagram + +![TRSQRT tile operation](../figures/isa/TRSQRT.svg) + +## Introduction + +Elementwise reciprocal square root. + +## Math Interpretation + +For each element `(i, j)` in the valid region: + +$$ \mathrm{dst}_{i,j} = \frac{1}{\sqrt{\mathrm{src}_{i,j}}} $$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = trsqrt %src : !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.trsqrt %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.trsqrt ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### IR Level 1 (SSA) + +```text +%dst = pto.trsqrt %src : !pto.tile<...> -> !pto.tile<...> +``` + +### IR Level 2 (DPS) + +```text +pto.trsqrt ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TRSQRT(TileDataDst &dst, TileDataSrc &src, WaitEvents &... events); + +template +PTO_INST RecordEvent TRSQRT(TileDataDst &dst, TileDataSrc &src, TileDataTmp &tmp, WaitEvents &... events); +``` + +## Constraints + +- **Implementation checks (NPU)**: + - The `tmp` buffer must be at least 32 bytes. When tmp is provided, the high-precision version is executed. + - `TileData::DType` must be one of: `float` or `half`; + - Tile location must be vector (`TileData::Loc == TileType::Vec`); + - Static valid bounds: `TileData::ValidRow <= TileData::Rows` and `TileData::ValidCol <= TileData::Cols`; + - Runtime: `src.GetValidRow() == dst.GetValidRow()` and `src.GetValidCol() == dst.GetValidCol()`; + - Tile layout must be row-major (`TileData::isRowMajor`). +- **Valid region**: + - The op uses `dst.GetValidRow()` / `dst.GetValidCol()` as the iteration domain. +- **Domain / NaN**: + - Behavior is target-defined (e.g., for `src == 0` or negative inputs). + +## Examples + +### Auto + +```cpp +#include + +using namespace pto; + +void example_auto() { + using TileT = Tile; + TileT src, dst; + TRSQRT(dst, src); +} +``` + +### Manual + +```cpp +#include + +using namespace pto; + +void example_manual() { + using TileT = Tile; + TileT src, dst; + TASSIGN(src, 0x1000); + TASSIGN(dst, 0x2000); + TRSQRT(dst, src); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.trsqrt %src : !pto.tile<...> -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.trsqrt %src : !pto.tile<...> -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = trsqrt %src : !pto.tile<...> +# AS Level 2 (DPS) +pto.trsqrt ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TRSQRT_zh.md b/designs/outerCube/PTOISA/TRSQRT_zh.md new file mode 100644 index 00000000..9b942dee --- /dev/null +++ b/designs/outerCube/PTOISA/TRSQRT_zh.md @@ -0,0 +1,107 @@ +# TRSQRT + +## 指令示意图 + +![TRSQRT tile operation](../figures/isa/TRSQRT.svg) + +## 简介 + +逐元素倒数平方根。 + +## 数学语义 + +对每个元素 `(i, j)` 在有效区域内： + +$$ \mathrm{dst}_{i,j} = \frac{1}{\sqrt{\mathrm{src}_{i,j}}} $$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS Specification](../assembly/PTO-AS.md). + +同步形式： + +```text +%dst = trsqrt %src : !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.trsqrt %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.trsqrt ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### AS Level 1（SSA） + +```text +%dst = pto.trsqrt %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.trsqrt ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TRSQRT(TileDataDst &dst, TileDataSrc &src, WaitEvents &... events); + +template +PTO_INST RecordEvent TRSQRT(TileDataDst &dst, TileDataSrc &src, TileDataTmp &tmp, WaitEvents &... events); +``` + +## 约束 + +- **实现检查 (NPU)**: + - The `tmp` buffer must be at least 32 bytes. When tmp is provided, the high-precision version is executed. + - `TileData::DType` must be one of: `float` or `half`; + - Tile location must be vector (`TileData::Loc == TileType::Vec`); + - Static valid bounds: `TileData::ValidRow <= TileData::Rows` and `TileData::ValidCol <= TileData::Cols`; + - Runtime: `src.GetValidRow() == dst.GetValidRow()` and `src.GetValidCol() == dst.GetValidCol()`; + - Tile 布局 must be row-major (`TileData::isRowMajor`). +- **有效区域**: + - The op uses `dst.GetValidRow()` / `dst.GetValidCol()` as the iteration domain. +- **Domain / NaN**: + - Behavior is target-defined (e.g., for `src == 0` or negative inputs). + +## 示例 + +### 自动（Auto） + +```cpp +#include + +using namespace pto; + +void example_auto() { + using TileT = Tile; + TileT src, dst; + TRSQRT(dst, src); +} +``` + +### 手动（Manual） + +```cpp +#include + +using namespace pto; + +void example_manual() { + using TileT = Tile; + TileT src, dst; + TASSIGN(src, 0x1000); + TASSIGN(dst, 0x2000); + TRSQRT(dst, src); +} +``` diff --git a/designs/outerCube/PTOISA/TSCATTER.md b/designs/outerCube/PTOISA/TSCATTER.md new file mode 100644 index 00000000..05d0dd23 --- /dev/null +++ b/designs/outerCube/PTOISA/TSCATTER.md @@ -0,0 +1,139 @@ +# TSCATTER + + +## Tile Operation Diagram + +![TSCATTER tile operation](../figures/isa/TSCATTER.svg) + +## Introduction + +Scatter source elements into a destination tile using per-element flattened destination offsets. + +## Math Interpretation + +For each source element `(i, j)`, let `k = idx[i,j]` and write: + +$$ \mathrm{dst\_flat}_{k} = \mathrm{src}_{i,j} $$ + +Here `dst_flat` denotes the destination tile viewed as a single linear storage sequence. `TSCATTER` does **not** interpret `idx[i,j]` as a destination row selector. On the standard row-major tile layout, this is equivalent to writing the `k`-th flattened destination element. + +If multiple elements map to the same destination location, the final value is implementation-defined (last writer wins in the current implementation). + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = tscatter %src, %idx : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### IR Level 1 (SSA) + +```text +%dst = pto.tscatter %src, %idx : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### IR Level 2 (DPS) + +```text +pto.tscatter ins(%src, %idx : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TSCATTER(TileDataD &dst, TileDataS &src, TileDataI &indexes, WaitEvents &... events); +``` + +## Constraints + +- **Implementation checks (A2A3)**: + - `TileDataD::Loc`, `TileDataS::Loc`, `TileDataI::Loc` must be `TileType::Vec`. + - `TileDataD::DType`, `TileDataS::DType` must be one of: `int32_t`, `int16_t`, `int8_t`, `half`, `float32_t`, `uint32_t`, `uint16_t`, `uint8_t`, `bfloat16_t`. + - `TileDataI::DType` must be one of: `int16_t`, `int32_t`, `uint16_t` or `uint32_t`. + - `indexes` values are interpreted as flattened destination element offsets in destination tile storage order. + - No bounds checks are enforced on `indexes` values. + - Static valid bounds: `TileDataD::ValidRow <= TileDataD::Rows`, `TileDataD::ValidCol <= TileDataD::Cols`, `TileDataS::ValidRow <= TileDataS::Rows`, `TileDataS::ValidCol <= TileDataS::Cols`, `TileDataI::ValidRow <= TileDataI::Rows`, `TileDataI::ValidCol <= TileDataI::Cols`. + - `TileDataD::DType` and `TileDataS::DType` must be the same. + - When size of `TileDataD::DType` is 4 bytes, the size of `TileDataI::DType` must be 4 bytes. + - When size of `TileDataD::DType` is 2 bytes, the size of `TileDataI::DType` must be 2 bytes. + - When size of `TileDataD::DType` is 1 bytes, the size of `TileDataI::DType` must be 2 bytes. +- **Implementation checks (A5)**: + - `TileDataD::Loc`, `TileDataS::Loc`, `TileDataI::Loc` must be `TileType::Vec`. + - `TileDataD::DType`, `TileDataS::DType` must be one of: `int32_t`, `int16_t`, `int8_t`, `half`, `float32_t`, `uint32_t`, `uint16_t`, `uint8_t`, `bfloat16_t`. + - `TileDataI::DType` must be one of: `int16_t`, `int32_t`, `uint16_t` or `uint32_t`. + - `indexes` values are interpreted as flattened destination element offsets in destination tile storage order. + - No bounds checks are enforced on `indexes` values. + - Static valid bounds: `TileDataD::ValidRow <= TileDataD::Rows`, `TileDataD::ValidCol <= TileDataD::Cols`, `TileDataS::ValidRow <= TileDataS::Rows`, `TileDataS::ValidCol <= TileDataS::Cols`, `TileDataI::ValidRow <= TileDataI::Rows`, `TileDataI::ValidCol <= TileDataI::Cols`. + - `TileDataD::DType` and `TileDataS::DType` must be the same. + - When size of `TileDataD::DType` is 4 bytes, the size of `TileDataI::DType` must be 4 bytes. + - When size of `TileDataD::DType` is 2 bytes, the size of `TileDataI::DType` must be 2 bytes. + - When size of `TileDataD::DType` is 1 bytes, the size of `TileDataI::DType` must be 2 bytes. + +## Examples + +### Auto + +```cpp +#include + +using namespace pto; + +void example_auto() { + using TileT = Tile; + using IdxT = Tile; + TileT src, dst; + IdxT idx; + TSCATTER(dst, src, idx); +} +``` + +### Manual + +```cpp +#include + +using namespace pto; + +void example_manual() { + using TileT = Tile; + using IdxT = Tile; + TileT src, dst; + IdxT idx; + TASSIGN(src, 0x1000); + TASSIGN(dst, 0x2000); + TASSIGN(idx, 0x3000); + TSCATTER(dst, src, idx); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.tscatter %src, %idx : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tscatter %src, %idx : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = tscatter %src, %idx : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +# IR Level 2 (DPS) +pto.tscatter ins(%src, %idx : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TSCATTER_zh.md b/designs/outerCube/PTOISA/TSCATTER_zh.md new file mode 100644 index 00000000..30b828ac --- /dev/null +++ b/designs/outerCube/PTOISA/TSCATTER_zh.md @@ -0,0 +1,112 @@ +# TSCATTER + +## 指令示意图 + +![TSCATTER tile operation](../figures/isa/TSCATTER.svg) + +## 简介 + +使用逐元素行索引将源 Tile 的行散播到目标 Tile 中。 + +## 数学语义 + +对每个源元素 `(i, j)`, let `k = idx[i,j]` and write: + +$$ \mathrm{dst\_flat}_{k} = \mathrm{src}_{i,j} $$ + +Here `dst_flat` denotes the destination tile viewed as a single linear storage sequence. `TSCATTER` does **not** interpret `idx[i,j]` as a destination row selector. On the standard row-major tile layout, this is equivalent to writing the `k`-th flattened destination element. + +If multiple elements map to the same destination location, the final value is implementation-defined (last writer wins in the current implementation). + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS Specification](../assembly/PTO-AS.md). + +同步形式： + +```text +%dst = tscatter %src, %idx : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 1（SSA） + +```text +%dst = pto.tscatter %src, %idx : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.tscatter ins(%src, %idx : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TSCATTER(TileDataD &dst, TileDataS &src, TileDataI &indexes, WaitEvents &... events); +``` + +## 约束 + +- **实现检查 (A2A3)**: + - `TileDataD::Loc`, `TileDataS::Loc`, `TileDataI::Loc` must be `TileType::Vec`. + - `TileDataD::DType`, `TileDataS::DType` must be one of: `int32_t`, `int16_t`, `int8_t`, `half`, `float32_t`, `uint32_t`, `uint16_t`, `uint8_t`, `bfloat16_t`. + - `TileDataI::DType` must be one of: `int16_t`, `int32_t`, `uint16_t` or `uint32_t`. + - `indexes` values are interpreted as flattened destination element offsets in destination tile storage order. + - No bounds checks are enforced on `indexes` values. + - Static valid bounds: `TileDataD::ValidRow <= TileDataD::Rows`, `TileDataD::ValidCol <= TileDataD::Cols`, `TileDataS::ValidRow <= TileDataS::Rows`, `TileDataS::ValidCol <= TileDataS::Cols`, `TileDataI::ValidRow <= TileDataI::Rows`, `TileDataI::ValidCol <= TileDataI::Cols`. + - `TileDataD::DType` and `TileDataS::DType` must be the same. + - When size of `TileDataD::DType` is 4 bytes, the size of `TileDataI::DType` must be 4 bytes. + - When size of `TileDataD::DType` is 2 bytes, the size of `TileDataI::DType` must be 2 bytes. + - When size of `TileDataD::DType` is 1 bytes, the size of `TileDataI::DType` must be 2 bytes. +- **实现检查 (A5)**: + - `TileDataD::Loc`, `TileDataS::Loc`, `TileDataI::Loc` must be `TileType::Vec`. + - `TileDataD::DType`, `TileDataS::DType` must be one of: `int32_t`, `int16_t`, `int8_t`, `half`, `float32_t`, `uint32_t`, `uint16_t`, `uint8_t`, `bfloat16_t`. + - `TileDataI::DType` must be one of: `int16_t`, `int32_t`, `uint16_t` or `uint32_t`. + - `indexes` values are interpreted as flattened destination element offsets in destination tile storage order. + - No bounds checks are enforced on `indexes` values. + - Static valid bounds: `TileDataD::ValidRow <= TileDataD::Rows`, `TileDataD::ValidCol <= TileDataD::Cols`, `TileDataS::ValidRow <= TileDataS::Rows`, `TileDataS::ValidCol <= TileDataS::Cols`, `TileDataI::ValidRow <= TileDataI::Rows`, `TileDataI::ValidCol <= TileDataI::Cols`. + - `TileDataD::DType` and `TileDataS::DType` must be the same. + - When size of `TileDataD::DType` is 4 bytes, the size of `TileDataI::DType` must be 4 bytes. + - When size of `TileDataD::DType` is 2 bytes, the size of `TileDataI::DType` must be 2 bytes. + - When size of `TileDataD::DType` is 1 bytes, the size of `TileDataI::DType` must be 2 bytes. + +## 示例 + +### 自动（Auto） + +```cpp +#include + +using namespace pto; + +void example_auto() { + using TileT = Tile; + using IdxT = Tile; + TileT src, dst; + IdxT idx; + TSCATTER(dst, src, idx); +} +``` + +### 手动（Manual） + +```cpp +#include + +using namespace pto; + +void example_manual() { + using TileT = Tile; + using IdxT = Tile; + TileT src, dst; + IdxT idx; + TASSIGN(src, 0x1000); + TASSIGN(dst, 0x2000); + TASSIGN(idx, 0x3000); + TSCATTER(dst, src, idx); +} +``` diff --git a/designs/outerCube/PTOISA/TSEL.md b/designs/outerCube/PTOISA/TSEL.md new file mode 100644 index 00000000..c1090b2a --- /dev/null +++ b/designs/outerCube/PTOISA/TSEL.md @@ -0,0 +1,140 @@ +# TSEL + + +## Tile Operation Diagram + +![TSEL tile operation](../figures/isa/TSEL.svg) + +## Introduction + +Select between two tiles using a mask tile (per-element selection). + +## Math Interpretation + +For each element `(i, j)` in the valid region: + +$$ +\mathrm{dst}_{i,j} = +\begin{cases} +\mathrm{src0}_{i,j} & \text{if } \mathrm{mask}_{i,j}\ \text{is true} \\ +\mathrm{src1}_{i,j} & \text{otherwise} +\end{cases} +$$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = tsel %mask, %src0, %src1 : !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tsel %mask, %src0, %src1 : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tsel ins(%mask, %src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TSEL(TileData &dst, MaskTile &selMask, TileData &src0, TileData &src1, TmpTile &tmp, WaitEvents &... events); +``` + +## Constraints + +- **Implementation checks (A2A3)**: + - `sizeof(TileData::DType)` must be `2` or `4` bytes. + - `TileData::DType` must be `int16_t` or `uint16_t` or `int32_t` or `uint32_t` or `half` or `bfloat16_t` or `float`. + - `dst`, `src0`, and `src1` must use the same element type. + - `dst`, `src0`, and `src1` must be row-major. + - The selection domain is `dst.GetValidRow()` / `dst.GetValidCol()`. +- **Implementation checks (A5)**: + - `sizeof(TileData::DType)` must be `2` or `4` bytes. + - `TileData::DType` must be `int16_t` or `uint16_t` or `int32_t` or `uint32_t` or `half` or `bfloat16_t` or `float`. + - `dst`, `src0`, and `src1` must use the same element type. + - `dst`, `src0`, and `src1` must be row-major. + - The selection domain is `dst.GetValidRow()` / `dst.GetValidCol()`. +- **Mask encoding**: + - The mask tile is interpreted as packed predicate bits in a target-defined layout. + +## Examples + +### Auto + +```cpp +#include + +using namespace pto; + +void example_auto() { + using TileT = Tile; + using MaskT = Tile; + using TmpT = Tile; + TileT src0, src1, dst; + MaskT mask(16, 2); + TmpT tmp; + TSEL(dst, mask, src0, src1, tmp); +} +``` + +### Manual + +```cpp +#include + +using namespace pto; + +void example_manual() { + using TileT = Tile; + using MaskT = Tile; + using TmpT = Tile; + TileT src0, src1, dst; + MaskT mask(16, 2); + TmpT tmp; + TASSIGN(src0, 0x1000); + TASSIGN(src1, 0x2000); + TASSIGN(dst, 0x3000); + TASSIGN(mask, 0x4000); + TASSIGN(tmp, 0x5000); + TSEL(dst, mask, src0, src1, tmp); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.tsel %mask, %src0, %src1 : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tsel %mask, %src0, %src1 : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = tsel %mask, %src0, %src1 : !pto.tile<...> +# AS Level 2 (DPS) +pto.tsel ins(%mask, %src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/TSELS.md b/designs/outerCube/PTOISA/TSELS.md new file mode 100644 index 00000000..a68226f3 --- /dev/null +++ b/designs/outerCube/PTOISA/TSELS.md @@ -0,0 +1,157 @@ +# TSELS + +## Tile Operation Diagram + +![TSELS tile operation](../figures/isa/TSELS.svg) + +## Introduction + +Select between source tile and scalar using a mask tile (per-element selection for source tile). + +## Math Interpretation + +For each element `(i, j)` in the valid region: + +$$ +\mathrm{dst}_{i,j} = +\begin{cases} +\mathrm{src}_{i,j} & \text{if } \mathrm{mask}_{i,j}\ \text{is true} \\ +\mathrm{scalar} & \text{otherwise} +\end{cases} +$$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = tsels %mask, %src, %scalar : !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tsels %mask, %src, %scalar : (!pto.tile<...>, !pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tsels ins(%mask, %src, %scalar : !pto.tile_buf<...>, !pto.tile_buf<...>, dtype) outs(%dst : !pto.tile_buf<...>) +``` + +### IR Level 1 (SSA) + +```text +%dst = pto.tsels %src0, %src1, %scalar : (!pto.tile<...>, !pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### IR Level 2 (DPS) + +```text +pto.tsels ins(%src0, %src1, %scalar : !pto.tile_buf<...>, !pto.tile_buf<...>, dtype) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TSELS(TileDataDst &dst, TileDataMask &mask, TileDataSrc &src, TileDataTmp &tmp, typename TileDataSrc::DType scalar, WaitEvents &... events); +``` + +## Constraints + +- **Implementation checks (A2A3)**: + - `sizeof(TileDataDst::DType)` must be `2` or `4` bytes. + - Supported data types are `half`, `float16_t`, `float`, and `float32_t`. + - `dst` and `src` must use the same element type. + - `dst` and `src` must be row-major. + - Runtime: `src.GetValidRow()/GetValidCol()` must match `dst.GetValidRow()/GetValidCol()`. +- **Implementation checks (A5)**: + - `sizeof(TileDataDst::DType)` may be `1`, `2`, or `4` bytes. + - Supported data types are `int8_t`, `uint8_t`, `int16_t`, `uint16_t`, `int32_t`, `uint32_t`, `half`, and `float`. + - `dst` and `src` must use the same element type. + - `dst`, `mask`, and `src` must be row-major. + - Runtime: `src.GetValidRow()/GetValidCol()` must match `dst.GetValidRow()/GetValidCol()`. +- **Valid region**: + - The op uses `dst.GetValidRow()` / `dst.GetValidCol()` as the iteration domain. +- **Mask encoding**: + - The mask tile is interpreted as packed predicate bits in a target-defined layout. + +## Examples + +### Auto + +```cpp +#include + +using namespace pto; + +void example_auto() { + using TileDst = Tile; + using TileSrc = Tile; + using TileTmp = Tile; + using TileMask = Tile; + TileDst dst; + TileSrc src; + TileTmp tmp; + TileMask mask(16, 2); + float scalar = 0.0f; + TSELS(dst, mask, src, tmp, scalar); +} +``` + +### Manual + +```cpp +#include + +using namespace pto; + +void example_manual() { + using TileDst = Tile; + using TileSrc = Tile; + using TileTmp = Tile; + using TileMask = Tile; + TileDst dst; + TileSrc src; + TileTmp tmp; + TileMask mask(16, 2); + float scalar = 0.0f; + TASSIGN(src, 0x1000); + TASSIGN(tmp, 0x2000); + TASSIGN(dst, 0x3000); + TASSIGN(mask, 0x4000); + TSELS(dst, mask, src, tmp, scalar); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.tsels %mask, %src, %scalar : (!pto.tile<...>, !pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tsels %mask, %src, %scalar : (!pto.tile<...>, !pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = tsels %mask, %src, %scalar : !pto.tile<...> +# AS Level 2 (DPS) +pto.tsels ins(%mask, %src, %scalar : !pto.tile_buf<...>, !pto.tile_buf<...>, dtype) outs(%dst : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TSELS_zh.md b/designs/outerCube/PTOISA/TSELS_zh.md new file mode 100644 index 00000000..31d6d7e2 --- /dev/null +++ b/designs/outerCube/PTOISA/TSELS_zh.md @@ -0,0 +1,147 @@ +# TSELS + +## 指令示意图 + +![TSELS tile operation](../figures/isa/TSELS.svg) + +## 简介 + +使用 mask tile 在源 Tile 和标量之间进行逐元素选择。 + +## 数学语义 + +对每个元素 `(i, j)` 在有效区域内： + +$$ +\mathrm{dst}_{i,j} = +\begin{cases} +\mathrm{src}_{i,j} & \text{if } \mathrm{mask}_{i,j}\ \text{为真} \\ +\mathrm{scalar} & \text{否则} +\end{cases} +$$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS 规范](../assembly/PTO-AS_zh.md)。 + +同步形式： + +```text +%dst = tsels %mask, %src, %scalar : !pto.tile<...> +``` + +### AS Level 1（SSA） + +```text +%dst = pto.tsels %mask, %src, %scalar : (!pto.tile<...>, !pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.tsels ins(%mask, %src, %scalar : !pto.tile_buf<...>, !pto.tile_buf<...>, dtype) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`： + +```cpp +template +PTO_INST RecordEvent TSELS(TileDataDst &dst, TileDataMask &mask, TileDataSrc &src, TileDataTmp &tmp, typename TileDataSrc::DType scalar, WaitEvents &... events); +``` + +## 约束 + +- **实现检查 (A2A3)**: + - `sizeof(TileDataDst::DType)` 必须是 `2` 或 `4` 字节。 + - 支持的数据类型为 `half`、`float16_t`、`float` 和 `float32_t`。 + - `dst` 和 `src` 必须使用相同的元素类型。 + - `dst` 和 `src` 必须是行主序。 + - 运行时：`src.GetValidRow()/GetValidCol()` 必须与 `dst.GetValidRow()/GetValidCol()` 一致。 +- **实现检查 (A5)**: + - `sizeof(TileDataDst::DType)` 可以是 `1`、`2` 或 `4` 字节。 + - 支持的数据类型为 `int8_t`、`uint8_t`、`int16_t`、`uint16_t`、`int32_t`、`uint32_t`、`half` 和 `float`。 + - `dst` 和 `src` 必须使用相同的元素类型。 + - `dst`、`mask` 和 `src` 必须是行主序。 + - 运行时：`src.GetValidRow()/GetValidCol()` 必须与 `dst.GetValidRow()/GetValidCol()` 一致。 +- **有效区域**: + - 该操作使用 `dst.GetValidRow()` / `dst.GetValidCol()` 作为迭代域。 +- **掩码编码**: + - 掩码 Tile 被解释为目标定义布局中的打包谓词位。 + +## 示例 + +### 自动（Auto） + +```cpp +#include + +using namespace pto; + +void example_auto() { + using TileDst = Tile; + using TileSrc = Tile; + using TileTmp = Tile; + using TileMask = Tile; + TileDst dst; + TileSrc src; + TileTmp tmp; + TileMask mask(16, 2); + float scalar = 0.0f; + TSELS(dst, mask, src, tmp, scalar); +} +``` + +### 手动（Manual） + +```cpp +#include + +using namespace pto; + +void example_manual() { + using TileDst = Tile; + using TileSrc = Tile; + using TileTmp = Tile; + using TileMask = Tile; + TileDst dst; + TileSrc src; + TileTmp tmp; + TileMask mask(16, 2); + float scalar = 0.0f; + TASSIGN(src, 0x1000); + TASSIGN(tmp, 0x2000); + TASSIGN(dst, 0x3000); + TASSIGN(mask, 0x4000); + TSELS(dst, mask, src, tmp, scalar); +} +``` + +## 汇编示例（ASM） + +### 自动模式 + +```text +# 自动模式：由编译器/运行时负责资源放置与调度。 +%dst = pto.tsels %mask, %src, %scalar : (!pto.tile<...>, !pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### 手动模式 + +```text +# 手动模式：先显式绑定资源，再发射指令。 +# 可选（当该指令包含 tile 操作数时）： +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tsels %mask, %src, %scalar : (!pto.tile<...>, !pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### PTO 汇编形式 + +```text +%dst = tsels %mask, %src, %scalar : !pto.tile<...> +# AS Level 2 (DPS) +pto.tsels ins(%mask, %src, %scalar : !pto.tile_buf<...>, !pto.tile_buf<...>, dtype) outs(%dst : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/TSEL_zh.md b/designs/outerCube/PTOISA/TSEL_zh.md new file mode 100644 index 00000000..fac4e34b --- /dev/null +++ b/designs/outerCube/PTOISA/TSEL_zh.md @@ -0,0 +1,140 @@ +# TSEL + +## 指令示意图 + +![TSEL tile operation](../figures/isa/TSEL.svg) + +## 简介 + +使用掩码 Tile 在两个 Tile 之间进行选择（逐元素选择）。 + +## 数学语义 + +对每个元素 `(i, j)` 在有效区域内： + +$$ +\mathrm{dst}_{i,j} = +\begin{cases} +\mathrm{src0}_{i,j} & \text{if } \mathrm{mask}_{i,j}\ \text{is true} \\ +\mathrm{src1}_{i,j} & \text{otherwise} +\end{cases} +$$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS 规范](../assembly/PTO-AS_zh.md)。 + +同步形式： + +```text +%dst = tsel %mask, %src0, %src1 : !pto.tile<...> +``` + +### AS Level 1（SSA） + +```text +%dst = pto.tsel %mask, %src0, %src1 : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.tsel ins(%mask, %src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`： + +```cpp +template +PTO_INST RecordEvent TSEL(TileData &dst, MaskTile &selMask, TileData &src0, TileData &src1, TmpTile &tmp, WaitEvents &... events); +``` + +## 约束 + +- **实现检查 (A2A3)**: + - `sizeof(TileData::DType)` 必须是 `2` 或 `4` 字节。 + - `TileData::DType` 必须是 `int16_t` 或 `uint16_t` 或 `int32_t` 或 `uint32_t` 或 `half` 或 `bfloat16_t` 或 `float`。 + - `dst`、`src0` 和 `src1` 必须使用相同的元素类型。 + - `dst`、`src0` 和 `src1` 必须是行主序。 + - 选择域由 `dst.GetValidRow()` / `dst.GetValidCol()` 决定。 +- **实现检查 (A5)**: + - `sizeof(TileData::DType)` 必须是 `2` 或 `4` 字节。 + - `TileData::DType` 必须是 `int16_t` 或 `uint16_t` 或 `int32_t` 或 `uint32_t` 或 `half` 或 `bfloat16_t` 或 `float`。 + - `dst`、`src0` 和 `src1` 必须使用相同的元素类型。 + - `dst`、`src0` 和 `src1` 必须是行主序。 + - 选择域由 `dst.GetValidRow()` / `dst.GetValidCol()` 决定。 +- **掩码编码**: + - 掩码 tile 被解释为目标定义布局中的打包谓词位。 + +## 示例 + +### 自动（Auto） + +```cpp +#include + +using namespace pto; + +void example_auto() { + using TileT = Tile; + using MaskT = Tile; + using TmpT = Tile; + TileT src0, src1, dst; + MaskT mask(16, 2); + TmpT tmp; + TSEL(dst, mask, src0, src1, tmp); +} +``` + +### 手动（Manual） + +```cpp +#include + +using namespace pto; + +void example_manual() { + using TileT = Tile; + using MaskT = Tile; + using TmpT = Tile; + TileT src0, src1, dst; + MaskT mask(16, 2); + TmpT tmp; + TASSIGN(src0, 0x1000); + TASSIGN(src1, 0x2000); + TASSIGN(dst, 0x3000); + TASSIGN(mask, 0x4000); + TASSIGN(tmp, 0x5000); + TSEL(dst, mask, src0, src1, tmp); +} +``` + +## 汇编示例（ASM） + +### 自动模式 + +```text +# 自动模式：由编译器/运行时负责资源放置与调度。 +%dst = pto.tsel %mask, %src0, %src1 : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### 手动模式 + +```text +# 手动模式：先显式绑定资源，再发射指令。 +# 可选（当该指令包含 tile 操作数时）： +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tsel %mask, %src0, %src1 : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### PTO 汇编形式 + +```text +%dst = tsel %mask, %src0, %src1 : !pto.tile<...> +# AS Level 2 (DPS) +pto.tsel ins(%mask, %src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/TSETFMATRIX.md b/designs/outerCube/PTOISA/TSETFMATRIX.md new file mode 100644 index 00000000..a7679c4e --- /dev/null +++ b/designs/outerCube/PTOISA/TSETFMATRIX.md @@ -0,0 +1,89 @@ +# TSETFMATRIX + + +## Tile Operation Diagram + +![TSETFMATRIX tile operation](../figures/isa/TSETFMATRIX.svg) + +## Introduction + +Set the FMATRIX register(s) used by IMG2COL-like operations from an `Img2colTileConfig` (target/implementation-defined). + +## See also + +- IMG2COL instruction: `docs/isa/TIMG2COL.md`. + +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TSETFMATRIX(ConvTileData &src, WaitEvents&... events); +``` + +## Math Interpretation + +Unless otherwise specified, semantics are defined over the valid region and target-dependent behavior is marked as implementation-defined. + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +### AS Level 1 (SSA) + +```text +pto.tsetfmatrix %cfg : !pto.fmatrix_config -> () +``` + +### AS Level 2 (DPS) + +```text +pto.tsetfmatrix ins(%cfg : !pto.fmatrix_config) outs() +``` + +### IR Level 1 (SSA) + +```text +pto.tsetfmatrix %cfg : !pto.fmatrix_config -> () +``` + +### IR Level 2 (DPS) + +```text +pto.tsetfmatrix ins(%cfg : !pto.fmatrix_config) outs() +``` +## Constraints + +Type/layout/location/shape legality is backend-dependent; treat implementation-specific notes as normative for that backend. + +## Examples + +See related examples in `docs/isa/` and `docs/coding/tutorials/`. + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +pto.tsetfmatrix %cfg : !pto.fmatrix_config -> () +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +pto.tsetfmatrix %cfg : !pto.fmatrix_config -> () +``` + +### PTO Assembly Form + +```text +pto.tsetfmatrix %cfg : !pto.fmatrix_config -> () +# AS Level 2 (DPS) +pto.tsetfmatrix ins(%cfg : !pto.fmatrix_config) outs() +``` diff --git a/designs/outerCube/PTOISA/TSETFMATRIX_zh.md b/designs/outerCube/PTOISA/TSETFMATRIX_zh.md new file mode 100644 index 00000000..ee314082 --- /dev/null +++ b/designs/outerCube/PTOISA/TSETFMATRIX_zh.md @@ -0,0 +1,58 @@ +# TSETFMATRIX + +## 指令示意图 + +![TSETFMATRIX tile operation](../figures/isa/TSETFMATRIX.svg) + +## 简介 + +为类 IMG2COL 操作设置 FMATRIX 寄存器。 + +## 数学语义 + +除非另有说明, semantics are defined over the valid region and target-dependent behavior is marked as implementation-defined. + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS Specification](../assembly/PTO-AS.md). + +### AS Level 1 (SSA) + +```text +pto.tsetfmatrix %cfg : !pto.fmatrix_config -> () +``` + +### AS Level 2 (DPS) + +```text +pto.tsetfmatrix ins(%cfg : !pto.fmatrix_config) outs() +``` + +### AS Level 1（SSA） + +```text +pto.tsetfmatrix %cfg : !pto.fmatrix_config -> () +``` + +### AS Level 2（DPS） + +```text +pto.tsetfmatrix ins(%cfg : !pto.fmatrix_config) outs() +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TSETFMATRIX(ConvTileData &src, WaitEvents&... events); +``` + +## 约束 + +Type/layout/location/shape legality is backend-dependent; treat implementation-specific notes as normative for that backend. + +## 示例 + +See related examples in `docs/isa/` and `docs/coding/tutorials/`. diff --git a/designs/outerCube/PTOISA/TSETHF32MODE.md b/designs/outerCube/PTOISA/TSETHF32MODE.md new file mode 100644 index 00000000..9d27bd40 --- /dev/null +++ b/designs/outerCube/PTOISA/TSETHF32MODE.md @@ -0,0 +1,62 @@ +# TSETHF32MODE + +## Tile Operation Diagram + +![TSETHF32MODE tile operation](../figures/isa/TSETHF32MODE.svg) + +## Introduction + +Configure HF32 transform mode (implementation-defined). + +This instruction controls backend-specific HF32 transformation behavior used by supported compute paths. + +## Math Interpretation + +No direct tensor arithmetic is produced by this instruction. It updates target mode state used by subsequent instructions. + +## Assembly Syntax + +PTO-AS form: see `docs/assembly/PTO-AS.md`. + +Schematic form: + +```text +tsethf32mode {enable = true, mode = ...} +``` + +### IR Level 1 (SSA) + +```text +pto.tsethf32mode {enable = true, mode = ...} +``` + +### IR Level 2 (DPS) + +```text +pto.tsethf32mode ins({enable = true, mode = ...}) outs() +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TSETHF32MODE(WaitEvents &... events); +``` + +## Constraints + +- Available only when the corresponding backend capability macro is enabled. +- Exact mode values and hardware behavior are target-defined. +- This instruction has control-state side effects and should be ordered appropriately relative to dependent compute instructions. + +## Examples + +```cpp +#include +using namespace pto; + +void example_enable_hf32() { + TSETHF32MODE(); +} +``` diff --git a/designs/outerCube/PTOISA/TSETHF32MODE_zh.md b/designs/outerCube/PTOISA/TSETHF32MODE_zh.md new file mode 100644 index 00000000..674bbedb --- /dev/null +++ b/designs/outerCube/PTOISA/TSETHF32MODE_zh.md @@ -0,0 +1,61 @@ +# TSETHF32MODE + +## 指令示意图 + +![TSETHF32MODE tile operation](../figures/isa/TSETHF32MODE.svg) + +## 简介 + +设置 HF32 变换模式（实现定义）。 + +## 数学语义 + +No direct tensor arithmetic is produced by this instruction. It updates target mode state used by subsequent instructions. + +## 汇编语法 + +PTO-AS 形式：参见 `docs/assembly/PTO-AS.md`. + +Schematic form: + +```text +tsethf32mode {enable = true, mode = ...} +``` + +### AS Level 1（SSA） + +```text +pto.tsethf32mode {enable = true, mode = ...} +``` + +### AS Level 2（DPS） + +```text +pto.tsethf32mode ins({enable = true, mode = ...}) outs() +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TSETHF32MODE(WaitEvents &... events); +``` + +## 约束 + +- Available only when the corresponding backend capability macro is enabled. +- Exact mode values and hardware behavior are target-defined. +- This instruction has control-state side effects and should be ordered appropriately relative to dependent compute instructions. + +## 示例 + +```cpp +#include +using namespace pto; + +void example_enable_hf32() { + TSETHF32MODE(); +} +``` diff --git a/designs/outerCube/PTOISA/TSETTF32MODE.md b/designs/outerCube/PTOISA/TSETTF32MODE.md new file mode 100644 index 00000000..b366e0d2 --- /dev/null +++ b/designs/outerCube/PTOISA/TSETTF32MODE.md @@ -0,0 +1,62 @@ +# TSETTF32MODE + +## Tile Operation Diagram + +![TSETTF32MODE tile operation](../figures/isa/TSETTF32MODE.svg) + +## Introduction + +Configure TF32 transform mode (implementation-defined). + +This instruction controls backend-specific TF32 transformation behavior used by supported compute paths. + +## Math Interpretation + +No direct tensor arithmetic is produced by this instruction. It updates target mode state used by subsequent instructions. + +## Assembly Syntax + +PTO-AS form: see `docs/assembly/PTO-AS.md`. + +Schematic form: + +```text +tsettf32mode {enable = true, mode = ...} +``` + +### IR Level 1 (SSA) + +```text +pto.tsettf32mode {enable = true, mode = ...} +``` + +### IR Level 2 (DPS) + +```text +pto.tsettf32mode ins({enable = true, mode = ...}) outs() +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TSETTF32MODE(WaitEvents &... events); +``` + +## Constraints + +- Available only when the corresponding backend capability macro is enabled. +- Exact mode values and hardware behavior are target-defined. +- This instruction has control-state side effects and should be ordered appropriately relative to dependent compute instructions. + +## Examples + +```cpp +#include +using namespace pto; + +void example_enable_tf32() { + TSETTF32MODE(); +} +``` diff --git a/designs/outerCube/PTOISA/TSETTF32MODE_zh.md b/designs/outerCube/PTOISA/TSETTF32MODE_zh.md new file mode 100644 index 00000000..3bb8aaac --- /dev/null +++ b/designs/outerCube/PTOISA/TSETTF32MODE_zh.md @@ -0,0 +1,61 @@ +# TSETTF32MODE + +## 指令示意图 + +![TSETTF32MODE tile operation](../figures/isa/TSETTF32MODE.svg) + +## 简介 + +设置 TF32 变换模式（实现定义）。 + +## 数学语义 + +No direct tensor arithmetic is produced by this instruction. It updates target mode state used by subsequent instructions. + +## 汇编语法 + +PTO-AS 形式：参见 `docs/assembly/PTO-AS.md`. + +Schematic form: + +```text +tsettf32mode {enable = true, mode = ...} +``` + +### AS Level 1（SSA） + +```text +pto.tsettf32mode {enable = true, mode = ...} +``` + +### AS Level 2（DPS） + +```text +pto.tsettf32mode ins({enable = true, mode = ...}) outs() +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TSETTF32MODE(WaitEvents &... events); +``` + +## 约束 + +- Available only when the corresponding backend capability macro is enabled. +- Exact mode values and hardware behavior are target-defined. +- This instruction has control-state side effects and should be ordered appropriately relative to dependent compute instructions. + +## 示例 + +```cpp +#include +using namespace pto; + +void example_enable_tf32() { + TSETTF32MODE(); +} +``` diff --git a/designs/outerCube/PTOISA/TSET_IMG2COL_PADDING.md b/designs/outerCube/PTOISA/TSET_IMG2COL_PADDING.md new file mode 100644 index 00000000..7f3b513a --- /dev/null +++ b/designs/outerCube/PTOISA/TSET_IMG2COL_PADDING.md @@ -0,0 +1,106 @@ +# TSET_IMG2COL_PADDING + +## Tile Operation Diagram + +![TSET_IMG2COL_PADDING tile operation](../figures/isa/TSET_IMG2COL_PADDING.svg) + +## Introduction + +Set IMG2COL padding metadata from an IMG2COL configuration tile (implementation-defined). + +## Math Interpretation + +No direct tensor arithmetic is produced by this instruction. It updates IMG2COL padding control state consumed by subsequent data-movement operations. + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Schematic form: + +```text +tset_img2col_padding %cfg +``` + +### AS Level 1 (SSA) + +```text +pto.tset_img2col_padding %cfg : !pto.fmatrix_config -> () +``` + +### AS Level 2 (DPS) + +```text +pto.tset_img2col_padding ins(%cfg : !pto.fmatrix_config) outs() +``` + +### IR Level 1 (SSA) + +```text +pto.tset_img2col_padding %cfg +``` + +### IR Level 2 (DPS) + +```text +pto.tset_img2col_padding ins(%cfg) outs() +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TSET_IMG2COL_PADDING(ConvTileData &src, WaitEvents &... events); + +template +PTO_INST RecordEvent TSET_IMG2COL_PADDING(ConvTileData &src, WaitEvents &... events); +``` + +For `MEMORY_BASE` targets, an overload without `SetFmatrixMode` is also provided. + +## Constraints + +- This instruction is backend-specific and available only for backends that expose IMG2COL configuration state. +- `src` must be a valid IMG2COL configuration tile type accepted by the backend implementation. +- The exact padding fields updated by this instruction are implementation-defined. +- Use this instruction before dependent `TIMG2COL` operations in the same execution stream. + +## Examples + +```cpp +#include + +using namespace pto; + +void example_set_img2col_padding(Img2colTileConfig& cfg) { + TSET_IMG2COL_PADDING(cfg); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +pto.tset_img2col_padding %cfg : !pto.fmatrix_config -> () +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +pto.tset_img2col_padding %cfg : !pto.fmatrix_config -> () +``` + +### PTO Assembly Form + +```text +pto.tset_img2col_padding %cfg : !pto.fmatrix_config -> () +# AS Level 2 (DPS) +pto.tset_img2col_padding ins(%cfg : !pto.fmatrix_config) outs() +``` diff --git a/designs/outerCube/PTOISA/TSET_IMG2COL_PADDING_zh.md b/designs/outerCube/PTOISA/TSET_IMG2COL_PADDING_zh.md new file mode 100644 index 00000000..5d4c2e1d --- /dev/null +++ b/designs/outerCube/PTOISA/TSET_IMG2COL_PADDING_zh.md @@ -0,0 +1,80 @@ +# TSET_IMG2COL_PADDING + +## 指令示意图 + +![TSET_IMG2COL_PADDING tile operation](../figures/isa/TSET_IMG2COL_PADDING.svg) + +## 简介 + +从 IMG2COL 配置 Tile 设置 IMG2COL 填充元数据。 + +## 数学语义 + +No direct tensor arithmetic is produced by this instruction. It updates IMG2COL padding control state consumed by subsequent data-movement operations. + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS Specification](../assembly/PTO-AS.md). + +Schematic form: + +```text +tset_img2col_padding %cfg +``` + +### AS Level 1 (SSA) + +```text +pto.tset_img2col_padding %cfg : !pto.fmatrix_config -> () +``` + +### AS Level 2 (DPS) + +```text +pto.tset_img2col_padding ins(%cfg : !pto.fmatrix_config) outs() +``` + +### AS Level 1（SSA） + +```text +pto.tset_img2col_padding %cfg +``` + +### AS Level 2（DPS） + +```text +pto.tset_img2col_padding ins(%cfg) outs() +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TSET_IMG2COL_PADDING(ConvTileData &src, WaitEvents &... events); + +template +PTO_INST RecordEvent TSET_IMG2COL_PADDING(ConvTileData &src, WaitEvents &... events); +``` + +For `MEMORY_BASE` targets, an overload without `SetFmatrixMode` is also provided. + +## 约束 + +- This instruction is backend-specific and available only for backends that expose IMG2COL configuration state. +- `src` must be a valid IMG2COL configuration tile type accepted by the backend implementation. +- The exact padding fields updated by this instruction are implementation-defined. +- Use this instruction before dependent `TIMG2COL` operations in the same execution stream. + +## 示例 + +```cpp +#include + +using namespace pto; + +void example_set_img2col_padding(Img2colTileConfig& cfg) { + TSET_IMG2COL_PADDING(cfg); +} +``` diff --git a/designs/outerCube/PTOISA/TSET_IMG2COL_RPT.md b/designs/outerCube/PTOISA/TSET_IMG2COL_RPT.md new file mode 100644 index 00000000..6911e358 --- /dev/null +++ b/designs/outerCube/PTOISA/TSET_IMG2COL_RPT.md @@ -0,0 +1,106 @@ +# TSET_IMG2COL_RPT + +## Tile Operation Diagram + +![TSET_IMG2COL_RPT tile operation](../figures/isa/TSET_IMG2COL_RPT.svg) + +## Introduction + +Set IMG2COL repeat metadata from an IMG2COL configuration tile (implementation-defined). + +## Math Interpretation + +No direct tensor arithmetic is produced by this instruction. It updates IMG2COL control state used by subsequent data-movement operations. + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Schematic form: + +```text +tset_img2col_rpt %cfg +``` + +### AS Level 1 (SSA) + +```text +pto.tset_img2col_rpt %cfg : !pto.fmatrix_config -> () +``` + +### AS Level 2 (DPS) + +```text +pto.tset_img2col_rpt ins(%cfg : !pto.fmatrix_config) outs() +``` + +### IR Level 1 (SSA) + +```text +pto.tset_img2col_rpt %cfg +``` + +### IR Level 2 (DPS) + +```text +pto.tset_img2col_rpt ins(%cfg) outs() +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TSET_IMG2COL_RPT(ConvTileData &src, WaitEvents &... events); + +template +PTO_INST RecordEvent TSET_IMG2COL_RPT(ConvTileData &src, WaitEvents &... events); +``` + +For `MEMORY_BASE` targets, an overload without `SetFmatrixMode` is also provided. + +## Constraints + +- This instruction is backend-specific and available only for backends that expose IMG2COL configuration state. +- `src` must be a valid IMG2COL configuration tile type accepted by the backend implementation. +- The exact register/metadata fields updated by this instruction are implementation-defined. +- Use this instruction before dependent `TIMG2COL` operations in the same execution stream. + +## Examples + +```cpp +#include + +using namespace pto; + +void example_set_img2col_rpt(Img2colTileConfig& cfg) { + TSET_IMG2COL_RPT(cfg); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +pto.tset_img2col_rpt %cfg : !pto.fmatrix_config -> () +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +pto.tset_img2col_rpt %cfg : !pto.fmatrix_config -> () +``` + +### PTO Assembly Form + +```text +pto.tset_img2col_rpt %cfg : !pto.fmatrix_config -> () +# AS Level 2 (DPS) +pto.tset_img2col_rpt ins(%cfg : !pto.fmatrix_config) outs() +``` diff --git a/designs/outerCube/PTOISA/TSET_IMG2COL_RPT_zh.md b/designs/outerCube/PTOISA/TSET_IMG2COL_RPT_zh.md new file mode 100644 index 00000000..059534d0 --- /dev/null +++ b/designs/outerCube/PTOISA/TSET_IMG2COL_RPT_zh.md @@ -0,0 +1,80 @@ +# TSET_IMG2COL_RPT + +## 指令示意图 + +![TSET_IMG2COL_RPT tile operation](../figures/isa/TSET_IMG2COL_RPT.svg) + +## 简介 + +从 IMG2COL 配置 Tile 设置 IMG2COL 重复次数元数据。 + +## 数学语义 + +No direct tensor arithmetic is produced by this instruction. It updates IMG2COL control state used by subsequent data-movement operations. + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS Specification](../assembly/PTO-AS.md). + +Schematic form: + +```text +tset_img2col_rpt %cfg +``` + +### AS Level 1 (SSA) + +```text +pto.tset_img2col_rpt %cfg : !pto.fmatrix_config -> () +``` + +### AS Level 2 (DPS) + +```text +pto.tset_img2col_rpt ins(%cfg : !pto.fmatrix_config) outs() +``` + +### AS Level 1（SSA） + +```text +pto.tset_img2col_rpt %cfg +``` + +### AS Level 2（DPS） + +```text +pto.tset_img2col_rpt ins(%cfg) outs() +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TSET_IMG2COL_RPT(ConvTileData &src, WaitEvents &... events); + +template +PTO_INST RecordEvent TSET_IMG2COL_RPT(ConvTileData &src, WaitEvents &... events); +``` + +For `MEMORY_BASE` targets, an overload without `SetFmatrixMode` is also provided. + +## 约束 + +- This instruction is backend-specific and available only for backends that expose IMG2COL configuration state. +- `src` must be a valid IMG2COL configuration tile type accepted by the backend implementation. +- The exact register/metadata fields updated by this instruction are implementation-defined. +- Use this instruction before dependent `TIMG2COL` operations in the same execution stream. + +## 示例 + +```cpp +#include + +using namespace pto; + +void example_set_img2col_rpt(Img2colTileConfig& cfg) { + TSET_IMG2COL_RPT(cfg); +} +``` diff --git a/designs/outerCube/PTOISA/TSHL.md b/designs/outerCube/PTOISA/TSHL.md new file mode 100644 index 00000000..8f3cb121 --- /dev/null +++ b/designs/outerCube/PTOISA/TSHL.md @@ -0,0 +1,103 @@ +# TSHL + + +## Tile Operation Diagram + +![TSHL tile operation](../figures/isa/TSHL.svg) + +## Introduction + +Elementwise shift-left of two tiles. + +## Math Interpretation + +For each element `(i, j)` in the valid region: + +$$ \mathrm{dst}_{i,j} = \mathrm{src0}_{i,j} \ll \mathrm{src1}_{i,j} $$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = tshl %src0, %src1 : !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tshl %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tshl ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TSHL(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, WaitEvents &... events); +``` + +## Constraints + +- **Implementation checks (A2A3)**: + - Supported element types are `uint8_t`, `int8_t`, `uint16_t`, `int16_t`, `uint32_t`, and `int32_t`. + - `dst`, `src0`, and `src1` must use the same element type. + - `dst`, `src0`, and `src1` must be row-major. + - Runtime: `src0.GetValidRow()/GetValidCol()` and `src1.GetValidRow()/GetValidCol()` must match `dst`. +- **Implementation checks (A5)**: + - Supported element types are `uint8_t`, `int8_t`, `uint16_t`, `int16_t`, `uint32_t`, and `int32_t`. + - `dst`, `src0`, and `src1` must use the same element type. + - `dst`, `src0`, and `src1` must be row-major. + - Runtime: `src0.GetValidRow()/GetValidCol()` and `src1.GetValidRow()/GetValidCol()` must match `dst`. +- **Valid region**: + - The op uses `dst.GetValidRow()` / `dst.GetValidCol()` as the iteration domain. + +## Examples + +```cpp +#include + +using namespace pto; + +void example() { + using TileT = Tile; + TileT x, sh, out; + TSHL(out, x, sh); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.tshl %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tshl %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = tshl %src0, %src1 : !pto.tile<...> +# AS Level 2 (DPS) +pto.tshl ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/TSHLS.md b/designs/outerCube/PTOISA/TSHLS.md new file mode 100644 index 00000000..d792f7cc --- /dev/null +++ b/designs/outerCube/PTOISA/TSHLS.md @@ -0,0 +1,108 @@ +# TSHLS + + +## Tile Operation Diagram + +![TSHLS tile operation](../figures/isa/TSHLS.svg) + +## Introduction + +Elementwise shift-left of a tile, shift bits given by scalar. + +## Math Interpretation + +For each element `(i, j)` in the valid region: + +$$ \mathrm{dst}_{i,j} = \mathrm{src}_{i,j} \ll \mathrm{scalar} $$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = tshls %src, %scalar : !pto.tile<...>, i32 +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tshls %src, %scalar : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tshls ins(%src, %scalar : !pto.tile_buf<...>, dtype) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TSHLS(TileDataDst &dst, TileDataSrc &src, typename TileDataDst::DType scalar, WaitEvents &... events); +``` + +## Constraints + +- **Implementation checks (A2A3)**: + - Supported element types are `int32_t`, `int`, `int16_t`, `uint32_t`, `unsigned int`, and `uint16_t`. + - `dst` and `src` must use the same element type. + - `dst` and `src` must be vector tiles. + - Runtime: `src.GetValidRow() == dst.GetValidRow()` and `src.GetValidCol() == dst.GetValidCol()`. + - Scalar only supports zero and positive values. +- **Implementation checks (A5)**: + - Supported element types are `int32_t`, `int16_t`, `int8_t`, `uint32_t`, `uint16_t`, and `uint8_t`. + - `dst` and `src` must use the same element type. + - `dst` and `src` must be vector tiles. + - Static valid bounds must satisfy `ValidRow <= Rows` and `ValidCol <= Cols` for both tiles. + - Runtime: `src.GetValidRow() == dst.GetValidRow()` and `src.GetValidCol() == dst.GetValidCol()`. + - Scalar only supports zero and positive values. +- **Valid region**: + - The op uses `dst.GetValidRow()` / `dst.GetValidCol()` as the iteration domain. + +## Examples + +```cpp +#include + +using namespace pto; + +void example() { + using TileDst = Tile; + using TileSrc = Tile; + TileDst dst; + TileSrc src; + TSHLS(dst, src, 0x2); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.tshls %src, %scalar : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tshls %src, %scalar : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = tshls %src, %scalar : !pto.tile<...>, i32 +# AS Level 2 (DPS) +pto.tshls ins(%src, %scalar : !pto.tile_buf<...>, dtype) outs(%dst : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/TSHLS_zh.md b/designs/outerCube/PTOISA/TSHLS_zh.md new file mode 100644 index 00000000..12e456e7 --- /dev/null +++ b/designs/outerCube/PTOISA/TSHLS_zh.md @@ -0,0 +1,108 @@ +# TSHLS + +## 指令示意图 + +![TSHLS tile operation](../figures/isa/TSHLS.svg) + +## 简介 + +Tile 按标量逐元素左移。 + +## 数学语义 + +对每个元素 `(i, j)` 在有效区域内： + +$$ \mathrm{dst}_{i,j} = \mathrm{src}_{i,j} \ll \mathrm{scalar} $$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS 规范](../assembly/PTO-AS_zh.md)。 + +同步形式： + +```text +%dst = tshls %src, %scalar : !pto.tile<...>, i32 +``` + +### AS Level 1（SSA） + +```text +%dst = pto.tshls %src, %scalar : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.tshls ins(%src, %scalar : !pto.tile_buf<...>, dtype) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`： + +```cpp +template +PTO_INST RecordEvent TSHLS(TileDataDst &dst, TileDataSrc &src, typename TileDataDst::DType scalar, WaitEvents &... events); +``` + +## 约束 + +- **实现检查 (A2A3)**: + - 支持的元素类型为 `int32_t`、`int`、`int16_t`、`uint32_t`、`unsigned int` 和 `uint16_t`。 + - `dst` 和 `src` 必须使用相同的元素类型。 + - `dst` 和 `src` 必须是向量 Tile。 + - 运行时：`src.GetValidRow() == dst.GetValidRow()` 且 `src.GetValidCol() == dst.GetValidCol()`。 + - 标量仅支持零和正值。 +- **实现检查 (A5)**: + - 支持的元素类型为 `int32_t`、`int16_t`、`int8_t`、`uint32_t`、`uint16_t` 和 `uint8_t`。 + - `dst` 和 `src` 必须使用相同的元素类型。 + - `dst` 和 `src` 必须是向量 Tile。 + - 两个 Tile 的静态有效边界都必须满足 `ValidRow <= Rows` 且 `ValidCol <= Cols`。 + - 运行时：`src.GetValidRow() == dst.GetValidRow()` 且 `src.GetValidCol() == dst.GetValidCol()`。 + - 标量仅支持零和正值。 +- **有效区域**: + - 该操作使用 `dst.GetValidRow()` / `dst.GetValidCol()` 作为迭代域。 + +## 示例 + +```cpp +#include + +using namespace pto; + +void example() { + using TileDst = Tile; + using TileSrc = Tile; + TileDst dst; + TileSrc src; + TSHLS(dst, src, 0x2); +} +``` + +## 汇编示例（ASM） + +### 自动模式 + +```text +# 自动模式：由编译器/运行时负责资源放置与调度。 +%dst = pto.tshls %src, %scalar : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### 手动模式 + +```text +# 手动模式：先显式绑定资源，再发射指令。 +# 可选（当该指令包含 tile 操作数时）： +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tshls %src, %scalar : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### PTO 汇编形式 + +```text +%dst = tshls %src, %scalar : !pto.tile<...>, i32 +# AS Level 2 (DPS) +pto.tshls ins(%src, %scalar : !pto.tile_buf<...>, dtype) outs(%dst : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/TSHL_zh.md b/designs/outerCube/PTOISA/TSHL_zh.md new file mode 100644 index 00000000..02fb6bc5 --- /dev/null +++ b/designs/outerCube/PTOISA/TSHL_zh.md @@ -0,0 +1,103 @@ +# TSHL + +## 指令示意图 + +![TSHL tile operation](../figures/isa/TSHL.svg) + +## 简介 + +两个 Tile 的逐元素左移。 + +## 数学语义 + +对每个元素 `(i, j)` 在有效区域内： + +$$ \mathrm{dst}_{i,j} = \mathrm{src0}_{i,j} \ll \mathrm{src1}_{i,j} $$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS 规范](../assembly/PTO-AS_zh.md)。 + +同步形式： + +```text +%dst = tshl %src0, %src1 : !pto.tile<...> +``` + +### AS Level 1（SSA） + +```text +%dst = pto.tshl %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.tshl ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`： + +```cpp +template +PTO_INST RecordEvent TSHL(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, WaitEvents &... events); +``` + +## 约束 + +- **实现检查 (A2A3)**: + - 支持的元素类型为 `uint8_t`、`int8_t`、`uint16_t`、`int16_t`、`uint32_t` 和 `int32_t`。 + - `dst`、`src0` 和 `src1` 必须使用相同的元素类型。 + - `dst`、`src0` 和 `src1` 必须是行主序。 + - 运行时：`src0.GetValidRow()/GetValidCol()` 和 `src1.GetValidRow()/GetValidCol()` 必须与 `dst` 一致。 +- **实现检查 (A5)**: + - 支持的元素类型为 `uint8_t`、`int8_t`、`uint16_t`、`int16_t`、`uint32_t` 和 `int32_t`。 + - `dst`、`src0` 和 `src1` 必须使用相同的元素类型。 + - `dst`、`src0` 和 `src1` 必须是行主序。 + - 运行时：`src0.GetValidRow()/GetValidCol()` 和 `src1.GetValidRow()/GetValidCol()` 必须与 `dst` 一致。 +- **有效区域**: + - 该操作使用 `dst.GetValidRow()` / `dst.GetValidCol()` 作为迭代域。 + +## 示例 + +```cpp +#include + +using namespace pto; + +void example() { + using TileT = Tile; + TileT x, sh, out; + TSHL(out, x, sh); +} +``` + +## 汇编示例（ASM） + +### 自动模式 + +```text +# 自动模式：由编译器/运行时负责资源放置与调度。 +%dst = pto.tshl %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### 手动模式 + +```text +# 手动模式：先显式绑定资源，再发射指令。 +# 可选（当该指令包含 tile 操作数时）： +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tshl %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### PTO 汇编形式 + +```text +%dst = tshl %src0, %src1 : !pto.tile<...> +# AS Level 2 (DPS) +pto.tshl ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/TSHR.md b/designs/outerCube/PTOISA/TSHR.md new file mode 100644 index 00000000..0ddd9b4f --- /dev/null +++ b/designs/outerCube/PTOISA/TSHR.md @@ -0,0 +1,103 @@ +# TSHR + + +## Tile Operation Diagram + +![TSHR tile operation](../figures/isa/TSHR.svg) + +## Introduction + +Elementwise shift-right of two tiles. + +## Math Interpretation + +For each element `(i, j)` in the valid region: + +$$ \mathrm{dst}_{i,j} = \mathrm{src0}_{i,j} \gg \mathrm{src1}_{i,j} $$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = tshr %src0, %src1 : !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tshr %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tshr ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TSHR(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, WaitEvents &... events); +``` + +## Constraints + +- **Implementation checks (A2A3)**: + - Supported element types are `uint8_t`, `int8_t`, `uint16_t`, `int16_t`, `uint32_t`, and `int32_t`. + - `dst`, `src0`, and `src1` must use the same element type. + - `dst`, `src0`, and `src1` must be row-major. + - Runtime: `src0.GetValidRow()/GetValidCol()` and `src1.GetValidRow()/GetValidCol()` must match `dst`. +- **Implementation checks (A5)**: + - Supported element types are `uint8_t`, `int8_t`, `uint16_t`, `int16_t`, `uint32_t`, and `int32_t`. + - `dst`, `src0`, and `src1` must use the same element type. + - `dst`, `src0`, and `src1` must be row-major. + - Runtime: `src0.GetValidRow()/GetValidCol()` and `src1.GetValidRow()/GetValidCol()` must match `dst`. +- **Valid region**: + - The op uses `dst.GetValidRow()` / `dst.GetValidCol()` as the iteration domain. + +## Examples + +```cpp +#include + +using namespace pto; + +void example() { + using TileT = Tile; + TileT x, sh, out; + TSHR(out, x, sh); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.tshr %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tshr %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = tshr %src0, %src1 : !pto.tile<...> +# AS Level 2 (DPS) +pto.tshr ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/TSHRS.md b/designs/outerCube/PTOISA/TSHRS.md new file mode 100644 index 00000000..bf8fa11b --- /dev/null +++ b/designs/outerCube/PTOISA/TSHRS.md @@ -0,0 +1,108 @@ +# TSHRS + + +## Tile Operation Diagram + +![TSHRS tile operation](../figures/isa/TSHRS.svg) + +## Introduction + +Elementwise shift-right of a tile, shift bits given by scalar. + +## Math Interpretation + +For each element `(i, j)` in the valid region: + +$$ \mathrm{dst}_{i,j} = \mathrm{src}_{i,j} \gg \mathrm{scalar} $$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = tshrs %src, %scalar : !pto.tile<...>, i32 +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tshrs %src, %scalar : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tshrs ins(%src, %scalar : !pto.tile_buf<...>, dtype) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TSHRS(TileDataDst &dst, TileDataSrc &src, typename TileDataDst::DType scalar, WaitEvents &... events); +``` + +## Constraints + +- **Implementation checks (A2A3)**: + - Supported element types are `int32_t`, `int`, `int16_t`, `uint32_t`, `unsigned int`, and `uint16_t`. + - `dst` and `src` must use the same element type. + - `dst` and `src` must be vector tiles. + - Runtime: `src.GetValidRow() == dst.GetValidRow()` and `src.GetValidCol() == dst.GetValidCol()`. + - Scalar only supports zero and positive values. +- **Implementation checks (A5)**: + - Supported element types are `int32_t`, `int16_t`, `int8_t`, `uint32_t`, `uint16_t`, and `uint8_t`. + - `dst` and `src` must use the same element type. + - `dst` and `src` must be vector tiles. + - Static valid bounds must satisfy `ValidRow <= Rows` and `ValidCol <= Cols` for both tiles. + - Runtime: `src.GetValidRow() == dst.GetValidRow()` and `src.GetValidCol() == dst.GetValidCol()`. + - Scalar only supports zero and positive values. +- **Valid region**: + - The op uses `dst.GetValidRow()` / `dst.GetValidCol()` as the iteration domain. + +## Examples + +```cpp +#include + +using namespace pto; + +void example() { + using TileDst = Tile; + using TileSrc = Tile; + TileDst dst; + TileSrc src; + TSHRS(dst, src, 0x2); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.tshrs %src, %scalar : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tshrs %src, %scalar : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = tshrs %src, %scalar : !pto.tile<...>, i32 +# AS Level 2 (DPS) +pto.tshrs ins(%src, %scalar : !pto.tile_buf<...>, dtype) outs(%dst : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/TSHRS_zh.md b/designs/outerCube/PTOISA/TSHRS_zh.md new file mode 100644 index 00000000..12330812 --- /dev/null +++ b/designs/outerCube/PTOISA/TSHRS_zh.md @@ -0,0 +1,108 @@ +# TSHRS + +## 指令示意图 + +![TSHRS tile operation](../figures/isa/TSHRS.svg) + +## 简介 + +Tile 按标量逐元素右移。 + +## 数学语义 + +对每个元素 `(i, j)` 在有效区域内： + +$$ \mathrm{dst}_{i,j} = \mathrm{src}_{i,j} \gg \mathrm{scalar} $$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS 规范](../assembly/PTO-AS_zh.md)。 + +同步形式： + +```text +%dst = tshrs %src, %scalar : !pto.tile<...>, i32 +``` + +### AS Level 1（SSA） + +```text +%dst = pto.tshrs %src, %scalar : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.tshrs ins(%src, %scalar : !pto.tile_buf<...>, dtype) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`： + +```cpp +template +PTO_INST RecordEvent TSHRS(TileDataDst &dst, TileDataSrc &src, typename TileDataDst::DType scalar, WaitEvents &... events); +``` + +## 约束 + +- **实现检查 (A2A3)**: + - 支持的元素类型为 `int32_t`、`int`、`int16_t`、`uint32_t`、`unsigned int` 和 `uint16_t`。 + - `dst` 和 `src` 必须使用相同的元素类型。 + - `dst` 和 `src` 必须是向量 Tile。 + - 运行时：`src.GetValidRow() == dst.GetValidRow()` 且 `src.GetValidCol() == dst.GetValidCol()`。 + - 标量仅支持零和正值。 +- **实现检查 (A5)**: + - 支持的元素类型为 `int32_t`、`int16_t`、`int8_t`、`uint32_t`、`uint16_t` 和 `uint8_t`。 + - `dst` 和 `src` 必须使用相同的元素类型。 + - `dst` 和 `src` 必须是向量 Tile。 + - 两个 Tile 的静态有效边界都必须满足 `ValidRow <= Rows` 且 `ValidCol <= Cols`。 + - 运行时：`src.GetValidRow() == dst.GetValidRow()` 且 `src.GetValidCol() == dst.GetValidCol()`。 + - 标量仅支持零和正值。 +- **有效区域**: + - 该操作使用 `dst.GetValidRow()` / `dst.GetValidCol()` 作为迭代域。 + +## 示例 + +```cpp +#include + +using namespace pto; + +void example() { + using TileDst = Tile; + using TileSrc = Tile; + TileDst dst; + TileSrc src; + TSHRS(dst, src, 0x2); +} +``` + +## 汇编示例（ASM） + +### 自动模式 + +```text +# 自动模式：由编译器/运行时负责资源放置与调度。 +%dst = pto.tshrs %src, %scalar : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### 手动模式 + +```text +# 手动模式：先显式绑定资源，再发射指令。 +# 可选（当该指令包含 tile 操作数时）： +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tshrs %src, %scalar : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### PTO 汇编形式 + +```text +%dst = tshrs %src, %scalar : !pto.tile<...>, i32 +# AS Level 2 (DPS) +pto.tshrs ins(%src, %scalar : !pto.tile_buf<...>, dtype) outs(%dst : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/TSHR_zh.md b/designs/outerCube/PTOISA/TSHR_zh.md new file mode 100644 index 00000000..2a170903 --- /dev/null +++ b/designs/outerCube/PTOISA/TSHR_zh.md @@ -0,0 +1,103 @@ +# TSHR + +## 指令示意图 + +![TSHR tile operation](../figures/isa/TSHR.svg) + +## 简介 + +两个 Tile 的逐元素右移。 + +## 数学语义 + +对每个元素 `(i, j)` 在有效区域内： + +$$ \mathrm{dst}_{i,j} = \mathrm{src0}_{i,j} \gg \mathrm{src1}_{i,j} $$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS 规范](../assembly/PTO-AS_zh.md)。 + +同步形式： + +```text +%dst = tshr %src0, %src1 : !pto.tile<...> +``` + +### AS Level 1（SSA） + +```text +%dst = pto.tshr %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.tshr ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`： + +```cpp +template +PTO_INST RecordEvent TSHR(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, WaitEvents &... events); +``` + +## 约束 + +- **实现检查 (A2A3)**: + - 支持的元素类型为 `uint8_t`、`int8_t`、`uint16_t`、`int16_t`、`uint32_t` 和 `int32_t`。 + - `dst`、`src0` 和 `src1` 必须使用相同的元素类型。 + - `dst`、`src0` 和 `src1` 必须是行主序。 + - 运行时：`src0.GetValidRow()/GetValidCol()` 和 `src1.GetValidRow()/GetValidCol()` 必须与 `dst` 一致。 +- **实现检查 (A5)**: + - 支持的元素类型为 `uint8_t`、`int8_t`、`uint16_t`、`int16_t`、`uint32_t` 和 `int32_t`。 + - `dst`、`src0` 和 `src1` 必须使用相同的元素类型。 + - `dst`、`src0` 和 `src1` 必须是行主序。 + - 运行时：`src0.GetValidRow()/GetValidCol()` 和 `src1.GetValidRow()/GetValidCol()` 必须与 `dst` 一致。 +- **有效区域**: + - 该操作使用 `dst.GetValidRow()` / `dst.GetValidCol()` 作为迭代域。 + +## 示例 + +```cpp +#include + +using namespace pto; + +void example() { + using TileT = Tile; + TileT x, sh, out; + TSHR(out, x, sh); +} +``` + +## 汇编示例（ASM） + +### 自动模式 + +```text +# 自动模式：由编译器/运行时负责资源放置与调度。 +%dst = pto.tshr %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### 手动模式 + +```text +# 手动模式：先显式绑定资源，再发射指令。 +# 可选（当该指令包含 tile 操作数时）： +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tshr %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### PTO 汇编形式 + +```text +%dst = tshr %src0, %src1 : !pto.tile<...> +# AS Level 2 (DPS) +pto.tshr ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/TSORT32.md b/designs/outerCube/PTOISA/TSORT32.md new file mode 100644 index 00000000..08948410 --- /dev/null +++ b/designs/outerCube/PTOISA/TSORT32.md @@ -0,0 +1,150 @@ +# TSORT32 + +## Tile Operation Diagram + +![TSORT32 tile operation](../figures/isa/TSORT32.svg) + +## Introduction + +Sort each 32-element block of `src` together with the corresponding indices from `idx`, and write the sorted value-index pairs into `dst`. + +## Math Interpretation + +For each row, `TSORT32` processes `src` in independent 32-element blocks. Let block `b` cover columns `32b ... 32b+31`, and let `n_b = min(32, C - 32b)` be the valid element count of that block. + +For each valid element in the block, form a pair + +$$ +(v_k, i_k) = (\mathrm{src}_{r,32b+k}, \mathrm{idx}_{r,32b+k}), \quad 0 \le k < n_b +$$ + +Then sort the pairs by value and write the sorted value-index pairs to `dst`. The exact packing layout in `dst` is target-defined, but semantically the output of each block is the reordered sequence + +$$ +[(v_{\pi(0)}, i_{\pi(0)}), (v_{\pi(1)}, i_{\pi(1)}), \ldots, (v_{\pi(n_b-1)}, i_{\pi(n_b-1)})] +$$ + +where `π` is the permutation produced by the implementation for that 32-element block. + +Notes: + +- `idx` is an input tile, not an output tile. +- `dst` stores sorted value-index pairs, not just sorted values. +- The CPU simulation sorts in descending order by value, and for equal values keeps smaller indices first. + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = tsort32 %src, %idx : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tsort32 %src, %idx : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tsort32 ins(%src, %idx : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TSORT32(DstTileData &dst, SrcTileData &src, IdxTileData &idx); + +template +PTO_INST RecordEvent TSORT32(DstTileData &dst, SrcTileData &src, IdxTileData &idx, TmpTileData &tmp); +``` + +## Constraints + +- `TSORT32` does not take `WaitEvents&...` and does not call `TSYNC(...)` internally; synchronize explicitly if needed. +- `idx` is a required input operand in both overloads; it provides the indices that are permuted together with `src`. +- **Implementation checks (A2A3/A5)**: + - `DstTileData::DType` must be `half` or `float`. + - `SrcTileData::DType` must match `DstTileData::DType`. + - `IdxTileData::DType` must be `uint32_t`. + - `dst/src/idx` tile location must be `TileType::Vec`, and all must be row-major (`isRowMajor`). +- **Valid region**: + - The implementation uses `dst.GetValidRow()` as the row count. + - The implementation uses `src.GetValidCol()` to determine how many elements participate in sorting in each row. + - Sorting is performed independently per 32-element block; the 4-argument overload additionally supports non-32-aligned tails with `tmp`. + +## Examples + +### Auto + +```cpp +#include + +using namespace pto; + +void example_auto() { + using SrcT = Tile; + using IdxT = Tile; + using DstT = Tile; + SrcT src; + IdxT idx; + DstT dst; + TSORT32(dst, src, idx); +} +``` + +### Manual + +```cpp +#include + +using namespace pto; + +void example_manual() { + using SrcT = Tile; + using IdxT = Tile; + using DstT = Tile; + SrcT src; + IdxT idx; + DstT dst; + TASSIGN(src, 0x1000); + TASSIGN(idx, 0x2000); + TASSIGN(dst, 0x3000); + TSORT32(dst, src, idx); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.tsort32 %src, %idx : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +# pto.tassign %arg2, @tile(0x3000) +%dst = pto.tsort32 %src, %idx : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = tsort32 %src, %idx : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +# AS Level 2 (DPS) +pto.tsort32 ins(%src, %idx : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/TSORT32_zh.md b/designs/outerCube/PTOISA/TSORT32_zh.md new file mode 100644 index 00000000..2229f183 --- /dev/null +++ b/designs/outerCube/PTOISA/TSORT32_zh.md @@ -0,0 +1,150 @@ +# TSORT32 + +## 指令示意图 + +![TSORT32 tile operation](../figures/isa/TSORT32.svg) + +## 简介 + +对 `src` 的每个 32 元素块，与 `idx` 中对应的索引一起进行排序，并将排序后的值-索引对写入 `dst`。 + +## 数学语义 + +对每一行，`TSORT32` 会按独立的 32 元素块处理 `src`。设第 `b` 个块覆盖列 `32b ... 32b+31`，该块的有效元素数为 `n_b = min(32, C - 32b)`。 + +对于块中的每个有效元素，先构造一个二元组： + +$$ +(v_k, i_k) = (\mathrm{src}_{r,32b+k}, \mathrm{idx}_{r,32b+k}), \quad 0 \le k < n_b +$$ + +然后按值对这些二元组排序，并将排序后的值-索引对写入 `dst`。`dst` 中的具体打包布局由目标实现定义，但从语义上看，每个块的输出可表示为： + +$$ +[(v_{\pi(0)}, i_{\pi(0)}), (v_{\pi(1)}, i_{\pi(1)}), \ldots, (v_{\pi(n_b-1)}, i_{\pi(n_b-1)})] +$$ + +其中 `π` 是该 32 元素块对应的排序置换。 + +说明： + +- `idx` 是输入 Tile，不是输出 Tile。 +- `dst` 保存的是排序后的值-索引对，而不只是排序后的值。 +- 在 CPU 仿真实现中，按值降序排序；当值相同时，索引较小者优先。 + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS 规范](../assembly/PTO-AS_zh.md)。 + +同步形式： + +```text +%dst = tsort32 %src, %idx : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 1（SSA） + +```text +%dst = pto.tsort32 %src, %idx : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.tsort32 ins(%src, %idx : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`： + +```cpp +template +PTO_INST RecordEvent TSORT32(DstTileData &dst, SrcTileData &src, IdxTileData &idx); + +template +PTO_INST RecordEvent TSORT32(DstTileData &dst, SrcTileData &src, IdxTileData &idx, TmpTileData &tmp); +``` + +## 约束 + +- `TSORT32` 不接受 `WaitEvents&...` 参数，也不在内部调用 `TSYNC(...)`；如有需要请显式同步。 +- `idx` 在两个重载中都是必需的输入操作数；它提供与 `src` 一起参与重排的索引。 +- **实现检查 (A2A3/A5)**: + - `DstTileData::DType` 必须是 `half` 或 `float`。 + - `SrcTileData::DType` 必须与 `DstTileData::DType` 匹配。 + - `IdxTileData::DType` 必须是 `uint32_t`。 + - `dst`/`src`/`idx` Tile 位置必须是 `TileType::Vec`，且都必须是行主序（`isRowMajor`）。 +- **有效区域**: + - 实现使用 `dst.GetValidRow()` 作为行数。 + - 实现使用 `src.GetValidCol()` 确定每行参与排序的元素数量。 + - 排序按独立的 32 元素块进行；4 参数重载额外通过 `tmp` 支持非 32 对齐尾块。 + +## 示例 + +### 自动（Auto） + +```cpp +#include + +using namespace pto; + +void example_auto() { + using SrcT = Tile; + using IdxT = Tile; + using DstT = Tile; + SrcT src; + IdxT idx; + DstT dst; + TSORT32(dst, src, idx); +} +``` + +### 手动（Manual） + +```cpp +#include + +using namespace pto; + +void example_manual() { + using SrcT = Tile; + using IdxT = Tile; + using DstT = Tile; + SrcT src; + IdxT idx; + DstT dst; + TASSIGN(src, 0x1000); + TASSIGN(idx, 0x2000); + TASSIGN(dst, 0x3000); + TSORT32(dst, src, idx); +} +``` + +## 汇编示例（ASM） + +### 自动模式 + +```text +# 自动模式：由编译器/运行时负责资源放置与调度。 +%dst = pto.tsort32 %src, %idx : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### 手动模式 + +```text +# 手动模式：先显式绑定资源，再发射指令。 +# 可选（当该指令包含 tile 操作数时）： +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +# pto.tassign %arg2, @tile(0x3000) +%dst = pto.tsort32 %src, %idx : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +``` + +### PTO 汇编形式 + +```text +%dst = tsort32 %src, %idx : !pto.tile<...>, !pto.tile<...> -> !pto.tile<...> +# AS Level 2 (DPS) +pto.tsort32 ins(%src, %idx : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TSQRT.md b/designs/outerCube/PTOISA/TSQRT.md new file mode 100644 index 00000000..881fb3ec --- /dev/null +++ b/designs/outerCube/PTOISA/TSQRT.md @@ -0,0 +1,130 @@ +# TSQRT + + +## Tile Operation Diagram + +![TSQRT tile operation](../figures/isa/TSQRT.svg) + +## Introduction + +Elementwise square root. + +## Math Interpretation + +For each element `(i, j)` in the valid region: + +$$ \mathrm{dst}_{i,j} = \sqrt{\mathrm{src}_{i,j}} $$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = tsqrt %src : !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tsqrt %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tsqrt ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### IR Level 1 (SSA) + +```text +%dst = pto.tsqrt %src : !pto.tile<...> -> !pto.tile<...> +``` + +### IR Level 2 (DPS) + +```text +pto.tsqrt ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TSQRT(TileDataDst &dst, TileDataSrc &src, WaitEvents &... events); +``` + +## Constraints + +- **Implementation checks (NPU)**: + - `TileData::DType` must be one of: `float` or `half`; + - Tile location must be vector (`TileData::Loc == TileType::Vec`); + - Static valid bounds: `TileData::ValidRow <= TileData::Rows` and `TileData::ValidCol <= TileData::Cols`; + - Runtime: `src.GetValidRow() == dst.GetValidRow()` and `src.GetValidCol() == dst.GetValidCol()`; + - Tile layout must be row-major (`TileData::isRowMajor`). +- **Valid region**: + - The op uses `dst.GetValidRow()` / `dst.GetValidCol()` as the iteration domain. +- **Domain / NaN**: + - Behavior is target-defined (e.g., for negative inputs). + +## Examples + +### Auto + +```cpp +#include + +using namespace pto; + +void example_auto() { + using TileT = Tile; + TileT src, dst; + TSQRT(dst, src); +} +``` + +### Manual + +```cpp +#include + +using namespace pto; + +void example_manual() { + using TileT = Tile; + TileT src, dst; + TASSIGN(src, 0x1000); + TASSIGN(dst, 0x2000); + TSQRT(dst, src); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.tsqrt %src : !pto.tile<...> -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tsqrt %src : !pto.tile<...> -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = tsqrt %src : !pto.tile<...> +# AS Level 2 (DPS) +pto.tsqrt ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TSQRT_zh.md b/designs/outerCube/PTOISA/TSQRT_zh.md new file mode 100644 index 00000000..555c0308 --- /dev/null +++ b/designs/outerCube/PTOISA/TSQRT_zh.md @@ -0,0 +1,103 @@ +# TSQRT + +## 指令示意图 + +![TSQRT tile operation](../figures/isa/TSQRT.svg) + +## 简介 + +逐元素平方根。 + +## 数学语义 + +对每个元素 `(i, j)` 在有效区域内： + +$$ \mathrm{dst}_{i,j} = \sqrt{\mathrm{src}_{i,j}} $$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS Specification](../assembly/PTO-AS.md). + +同步形式： + +```text +%dst = tsqrt %src : !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tsqrt %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tsqrt ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### AS Level 1（SSA） + +```text +%dst = pto.tsqrt %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.tsqrt ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TSQRT(TileDataDst &dst, TileDataSrc &src, WaitEvents &... events); +``` + +## 约束 + +- **实现检查 (NPU)**: + - `TileData::DType` must be one of: `float` or `half`; + - Tile location must be vector (`TileData::Loc == TileType::Vec`); + - Static valid bounds: `TileData::ValidRow <= TileData::Rows` and `TileData::ValidCol <= TileData::Cols`; + - Runtime: `src.GetValidRow() == dst.GetValidRow()` and `src.GetValidCol() == dst.GetValidCol()`; + - Tile 布局 must be row-major (`TileData::isRowMajor`). +- **有效区域**: + - The op uses `dst.GetValidRow()` / `dst.GetValidCol()` as the iteration domain. +- **Domain / NaN**: + - Behavior is target-defined (e.g., for negative inputs). + +## 示例 + +### 自动（Auto） + +```cpp +#include + +using namespace pto; + +void example_auto() { + using TileT = Tile; + TileT src, dst; + TSQRT(dst, src); +} +``` + +### 手动（Manual） + +```cpp +#include + +using namespace pto; + +void example_manual() { + using TileT = Tile; + TileT src, dst; + TASSIGN(src, 0x1000); + TASSIGN(dst, 0x2000); + TSQRT(dst, src); +} +``` diff --git a/designs/outerCube/PTOISA/TSTORE.md b/designs/outerCube/PTOISA/TSTORE.md new file mode 100644 index 00000000..e6e017c7 --- /dev/null +++ b/designs/outerCube/PTOISA/TSTORE.md @@ -0,0 +1,158 @@ +# TSTORE + + +## Tile Operation Diagram + +![TSTORE tile operation](../figures/isa/TSTORE.svg) + +## Introduction + +Store data from a Tile into a GlobalTensor (GM), optionally using atomic write or quantization parameters. + +## Math Interpretation + +Notation depends on the `GlobalTensor` shape/stride and the `Tile` layout. Conceptually (2D view, with a base offset): + +$$ \mathrm{dst}_{r_0 + i,\; c_0 + j} = \mathrm{src}_{i,j} $$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +tstore %t1, %sv_out[%c0, %c0] +``` + +### IR Level 1 (SSA) + +```text +pto.tstore %src, %mem : (!pto.tile<...>, !pto.partition_tensor_view) -> () +``` + +### IR Level 2 (DPS) + +```text +pto.tstore ins(%src : !pto.tile_buf<...>) outs(%mem : !pto.partition_tensor_view) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp` and `include/pto/common/constants.hpp`: + +```cpp +template +PTO_INST RecordEvent TSTORE(GlobalData &dst, TileData &src, WaitEvents &... events); + +template +PTO_INST RecordEvent TSTORE(GlobalData &dst, TileData &src, uint64_t preQuantScalar, WaitEvents &... events); + +template +PTO_INST RecordEvent TSTORE_FP(GlobalData &dst, TileData &src, FpTileData &fp, WaitEvents &... events); +``` + +The `preQuantScalar` and `TSTORE_FP` quantized-store overloads are only legal for `TileType::Acc` on current A2/A3 and A5 backends. They do not provide a native vec-tile quantized store contract. + +## Constraints + +- **Implementation checks (A2A3)**: + - Source tile location must be one of: `TileType::Vec`, `TileType::Mat`, `TileType::Acc`. + - Runtime: all `dst.GetShape(dim)` values and `src.GetValidRow()/GetValidCol()` must be `> 0`. + - For `TileType::Vec` / `TileType::Mat`: + - `TileData::DType` must be one of: `int8_t`, `uint8_t`, `int16_t`, `uint16_t`, `int32_t`, `uint32_t`, `int64_t`, `uint64_t`, `half`, `bfloat16_t`, `float`. + - `sizeof(TileData::DType) == sizeof(GlobalData::DType)`. + - Layouts must match ND/DN/NZ (or a special case where `TileData::Rows == 1` or `TileData::Cols == 1`). + - For `int64_t/uint64_t`, only ND->ND or DN->DN are supported. + - A2/A3 does not expose a native vec quantized-store path. Frontends that need `vec -> GM` dtype conversion or quantization MUST first materialize the converted vec tile (for example via `TCVT`) and then issue a same-dtype `TSTORE`. + - For `TileType::Acc` (including quantized/atomic variants): + - Destination layout must be ND or NZ. + - Source dtype must be `int32_t` or `float`. + - When not using quantization, destination dtype must be `__gm__ int32_t/float/half/bfloat16_t`. + - Static shape constraints: `1 <= TileData::Cols <= 4095`; if ND then `1 <= TileData::Rows <= 8192`; if NZ then `1 <= TileData::Rows <= 65535` and `TileData::Cols % 16 == 0`. + - Runtime: `1 <= src.GetValidCol() <= 4095`. +- **Implementation checks (A5)**: + - Source tile location must be `TileType::Vec` or `TileType::Acc` (no `Mat` store on this target). + - For `TileType::Vec`: + - `sizeof(TileData::DType) == sizeof(GlobalData::DType)`. + - `TileData::DType` must be one of: `int8_t`, `uint8_t`, `int16_t`, `uint16_t`, `int32_t`, `uint32_t`, `int64_t`, `uint64_t`, `half`, `bfloat16_t`, `float`, `float8_e4m3_t`, `float8_e5m2_t`, `hifloat8_t`, `float4_e1m2x2_t`, `float4_e2m1x2_t`. + - Layouts must match ND/DN/NZ (or a special case where `TileData::Rows == 1` or `TileData::Cols == 1`). + - Additional alignment constraints are enforced (e.g., for ND the row-major width in bytes must be a multiple of 32; for DN the column-major height in bytes must be a multiple of 32, with special-case exceptions). + - For `TileType::Acc`: + - Destination layout must be ND or NZ; source dtype must be `int32_t` or `float`. + - When not using quantization, destination dtype must be `__gm__ int32_t/float/half/bfloat16_t`. + - Static shape constraints match A2A3 for rows/cols; `AtomicAdd` additionally restricts destination dtype to supported atomic types. +- **Valid region**: + - The implementation uses `src.GetValidRow()` / `src.GetValidCol()` as the transfer size. + +## Examples + +### Auto + +```cpp +#include + +using namespace pto; + +template +void example_auto(__gm__ T* out) { + using TileT = Tile; + using GShape = Shape<1, 1, 1, 16, 16>; + using GStride = BaseShape2D; + using GTensor = GlobalTensor; + + GTensor gout(out); + TileT t; + TSTORE(gout, t); +} +``` + +### Manual + +```cpp +#include + +using namespace pto; + +template +void example_manual(__gm__ T* out) { + using TileT = Tile; + using GShape = Shape<1, 1, 1, 16, 16>; + using GStride = BaseShape2D; + using GTensor = GlobalTensor; + + GTensor gout(out); + TileT t; + TASSIGN(t, 0x1000); + TSTORE(gout, t); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +pto.tstore %src, %mem : (!pto.tile<...>, !pto.partition_tensor_view) -> () +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +pto.tstore %src, %mem : (!pto.tile<...>, !pto.partition_tensor_view) -> () +``` + +### PTO Assembly Form + +```text +tstore %t1, %sv_out[%c0, %c0] +# IR Level 2 (DPS) +pto.tstore ins(%src : !pto.tile_buf<...>) outs(%mem : !pto.partition_tensor_view) +``` diff --git a/designs/outerCube/PTOISA/TSTORE_FP.md b/designs/outerCube/PTOISA/TSTORE_FP.md new file mode 100644 index 00000000..942e1abe --- /dev/null +++ b/designs/outerCube/PTOISA/TSTORE_FP.md @@ -0,0 +1,147 @@ +# TSTORE_FP + + +## Tile Operation Diagram + +![TSTORE_FP tile operation](../figures/isa/TSTORE_FP.svg) + +## Introduction + +Store an accumulator tile into global memory using a scaling (`fp`) tile for vector quantization parameters. + +`TSTORE_FP` is the fp-quantization overload of `TSTORE` (see `docs/isa/TSTORE.md`). + +## Math Interpretation + +Let `R = src.GetValidRow()` and `C = src.GetValidCol()`. Conceptually (2D view, with a base offset), for `0 <= i < R` and `0 <= j < C`: + +$$ \mathrm{dst}_{r_0 + i,\; c_0 + j} = \mathrm{Convert}\!\left(\mathrm{src}_{i,j};\ \mathrm{fp}\right) $$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +tstore.fp %src, %fp, %sv_out[%c0, %c0] +``` + +### AS Level 1 (SSA) + +```text +pto.tstore.fp %src, %fp, %mem : (!pto.tile<...>, !pto.tile<...>, !pto.partition_tensor_view) -> () +``` + +### AS Level 2 (DPS) + +```text +pto.tstore.fp ins(%src, %fp : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%mem : !pto.partition_tensor_view) +``` + +### IR Level 1 (SSA) + +```text +pto.tstore.fp %src, %fp, %mem : (!pto.tile<...>, !pto.tile<...>, !pto.partition_tensor_view) -> () +``` + +### IR Level 2 (DPS) + +```text +pto.tstore.fp ins(%src, %fp : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%mem : !pto.partition_tensor_view) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp` and `include/pto/common/constants.hpp`: + +```cpp +template +PTO_INST RecordEvent TSTORE_FP(GlobalData &dst, TileData &src, FpTileData &fp, WaitEvents &... events); +``` + +## Constraints + +- **Implementation checks (A2A3)**: + - The fp store path is implemented via `TSTORE_IMPL(dst, src, fp)` and uses the same accumulator-to-GM legality checks as quantized accumulator stores: + - Destination layout must be ND or NZ. + - Source dtype must be `int32_t` or `float`. + - Static shape constraints: `1 <= TileData::Cols <= 4095`; if ND then `1 <= TileData::Rows <= 8192`; if NZ then `1 <= TileData::Rows <= 65535` and `TileData::Cols % 16 == 0`. + - Runtime: `1 <= src.GetValidCol() <= 4095`. + - No explicit `static_assert` is enforced on `FpTileData` (the implementation uses `fp` to set FPC state). +- **Implementation checks (A5)**: + - Implemented via `TSTORE_IMPL(dst, src, fp)` and validated by `CheckStaticAcc<..., true>()` for the accumulator path (ND/NZ only, `int32_t/float` source dtype, rows/cols ranges). + - No explicit `static_assert` is enforced on `FpTileData` (the implementation uses `fp` to set FPC state). + +## Examples + +### Auto + +```cpp +#include + +using namespace pto; + +void example_auto(__gm__ int8_t* out) { + using AccT = TileAcc; + using FpT = Tile; + using GShape = Shape<1, 1, 1, 16, 16>; + using GStride = BaseShape2D; + using GT = GlobalTensor; + + GT gout(out); + AccT acc; + FpT fp(16); + TSTORE_FP(gout, acc, fp); +} +``` + +### Manual + +```cpp +#include + +using namespace pto; + +void example_manual(__gm__ int8_t* out) { + using AccT = TileAcc; + using FpT = Tile; + using GShape = Shape<1, 1, 1, 16, 16>; + using GStride = BaseShape2D; + using GT = GlobalTensor; + + GT gout(out); + AccT acc; + FpT fp(16); + TASSIGN(acc, 0x1000); + TASSIGN(fp, 0x2000); + TSTORE_FP(gout, acc, fp); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +pto.tstore.fp %src, %fp, %mem : (!pto.tile<...>, !pto.tile<...>, !pto.partition_tensor_view) -> () +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +pto.tstore.fp %src, %fp, %mem : (!pto.tile<...>, !pto.tile<...>, !pto.partition_tensor_view) -> () +``` + +### PTO Assembly Form + +```text +tstore.fp %src, %fp, %sv_out[%c0, %c0] +# AS Level 2 (DPS) +pto.tstore.fp ins(%src, %fp : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%mem : !pto.partition_tensor_view) +``` diff --git a/designs/outerCube/PTOISA/TSTORE_FP_zh.md b/designs/outerCube/PTOISA/TSTORE_FP_zh.md new file mode 100644 index 00000000..53e9a64e --- /dev/null +++ b/designs/outerCube/PTOISA/TSTORE_FP_zh.md @@ -0,0 +1,118 @@ +# TSTORE_FP + +## 指令示意图 + +![TSTORE_FP tile operation](../figures/isa/TSTORE_FP.svg) + +## 简介 + +使用缩放 (`fp`) Tile 作为向量量化参数，将累加器 Tile 存储到全局内存。 + +## 数学语义 + +Let `R = src.GetValidRow()` and `C = src.GetValidCol()`. Conceptually (2D view, with a base offset), for `0 <= i < R` and `0 <= j < C`: + +$$ \mathrm{dst}_{r_0 + i,\; c_0 + j} = \mathrm{Convert}\!\left(\mathrm{src}_{i,j};\ \mathrm{fp}\right) $$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS Specification](../assembly/PTO-AS.md). + +同步形式： + +```text +tstore.fp %src, %fp, %sv_out[%c0, %c0] +``` + +### AS Level 1 (SSA) + +```text +pto.tstore.fp %src, %fp, %mem : (!pto.tile<...>, !pto.tile<...>, !pto.partition_tensor_view) -> () +``` + +### AS Level 2 (DPS) + +```text +pto.tstore.fp ins(%src, %fp : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%mem : !pto.partition_tensor_view) +``` + +### AS Level 1（SSA） + +```text +pto.tstore.fp %src, %fp, %mem : (!pto.tile<...>, !pto.tile<...>, !pto.partition_tensor_view) -> () +``` + +### AS Level 2（DPS） + +```text +pto.tstore.fp ins(%src, %fp : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%mem : !pto.partition_tensor_view) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp` and `include/pto/common/constants.hpp`: + +```cpp +template +PTO_INST RecordEvent TSTORE_FP(GlobalData &dst, TileData &src, FpTileData &fp, WaitEvents &... events); +``` + +## 约束 + +- **实现检查 (A2A3)**: + - The fp store path is implemented via `TSTORE_IMPL(dst, src, fp)` and uses the same accumulator-to-GM legality checks as quantized accumulator stores: + - Destination layout must be ND or NZ. + - Source dtype must be `int32_t` or `float`. + - Static shape constraints: `1 <= TileData::Cols <= 4095`; if ND then `1 <= TileData::Rows <= 8192`; if NZ then `1 <= TileData::Rows <= 65535` and `TileData::Cols % 16 == 0`. + - Runtime: `1 <= src.GetValidCol() <= 4095`. + - No explicit `static_assert` is enforced on `FpTileData` (the implementation uses `fp` to set FPC state). +- **实现检查 (A5)**: + - Implemented via `TSTORE_IMPL(dst, src, fp)` and validated by `CheckStaticAcc<..., true>()` for the accumulator path (ND/NZ only, `int32_t/float` source dtype, rows/cols ranges). + - No explicit `static_assert` is enforced on `FpTileData` (the implementation uses `fp` to set FPC state). + +## 示例 + +### 自动（Auto） + +```cpp +#include + +using namespace pto; + +void example_auto(__gm__ int8_t* out) { + using AccT = TileAcc; + using FpT = Tile; + using GShape = Shape<1, 1, 1, 16, 16>; + using GStride = BaseShape2D; + using GT = GlobalTensor; + + GT gout(out); + AccT acc; + FpT fp(16); + TSTORE_FP(gout, acc, fp); +} +``` + +### 手动（Manual） + +```cpp +#include + +using namespace pto; + +void example_manual(__gm__ int8_t* out) { + using AccT = TileAcc; + using FpT = Tile; + using GShape = Shape<1, 1, 1, 16, 16>; + using GStride = BaseShape2D; + using GT = GlobalTensor; + + GT gout(out); + AccT acc; + FpT fp(16); + TASSIGN(acc, 0x1000); + TASSIGN(fp, 0x2000); + TSTORE_FP(gout, acc, fp); +} +``` diff --git a/designs/outerCube/PTOISA/TSTORE_zh.md b/designs/outerCube/PTOISA/TSTORE_zh.md new file mode 100644 index 00000000..1ae44856 --- /dev/null +++ b/designs/outerCube/PTOISA/TSTORE_zh.md @@ -0,0 +1,131 @@ +# TSTORE + +## 指令示意图 + +![TSTORE tile operation](../figures/isa/TSTORE.svg) + +## 简介 + +将 Tile 中的数据存储到 GlobalTensor (GM)，可选使用原子写入或量化参数。 + +## 数学语义 + +Notation depends on the `GlobalTensor` shape/stride and the `Tile` layout. Conceptually (2D view, with a base offset): + +$$ \mathrm{dst}_{r_0 + i,\; c_0 + j} = \mathrm{src}_{i,j} $$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS Specification](../assembly/PTO-AS.md). + +同步形式： + +```text +tstore %t1, %sv_out[%c0, %c0] +``` + +### AS Level 1（SSA） + +```text +pto.tstore %src, %mem : (!pto.tile<...>, !pto.partition_tensor_view) -> () +``` + +### AS Level 2（DPS） + +```text +pto.tstore ins(%src : !pto.tile_buf<...>) outs(%mem : !pto.partition_tensor_view) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp` and `include/pto/common/constants.hpp`: + +```cpp +template +PTO_INST RecordEvent TSTORE(GlobalData &dst, TileData &src, WaitEvents &... events); + +template +PTO_INST RecordEvent TSTORE(GlobalData &dst, TileData &src, uint64_t preQuantScalar, WaitEvents &... events); + +template +PTO_INST RecordEvent TSTORE_FP(GlobalData &dst, TileData &src, FpTileData &fp, WaitEvents &... events); +``` + +The `preQuantScalar` and `TSTORE_FP` quantized-store overloads are only legal for `TileType::Acc` on current A2/A3 and A5 backends. They do not provide a native vec-tile quantized store contract. + +## 约束 + +- **实现检查 (A2A3)**: + - Source tile location must be one of: `TileType::Vec`, `TileType::Mat`, `TileType::Acc`. + - Runtime: all `dst.GetShape(dim)` values and `src.GetValidRow()/GetValidCol()` must be `> 0`. + - For `TileType::Vec` / `TileType::Mat`: + - `TileData::DType` must be one of: `int8_t`, `uint8_t`, `int16_t`, `uint16_t`, `int32_t`, `uint32_t`, `int64_t`, `uint64_t`, `half`, `bfloat16_t`, `float`. + - `sizeof(TileData::DType) == sizeof(GlobalData::DType)`. + - Layouts must match ND/DN/NZ (or a special case where `TileData::Rows == 1` or `TileData::Cols == 1`). + - For `int64_t/uint64_t`, only ND->ND or DN->DN are supported. + - A2/A3 does not expose a native vec quantized-store path. Frontends that need `vec -> GM` dtype conversion or quantization MUST first materialize the converted vec tile (for example via `TCVT`) and then issue a same-dtype `TSTORE`. + - For `TileType::Acc` (including quantized/atomic variants): + - Destination layout must be ND or NZ. + - Source dtype must be `int32_t` or `float`. + - When not using quantization, destination dtype must be `__gm__ int32_t/float/half/bfloat16_t`. + - Static shape constraints: `1 <= TileData::Cols <= 4095`; if ND then `1 <= TileData::Rows <= 8192`; if NZ then `1 <= TileData::Rows <= 65535` and `TileData::Cols % 16 == 0`. + - Runtime: `1 <= src.GetValidCol() <= 4095`. +- **实现检查 (A5)**: + - Source tile location must be `TileType::Vec` or `TileType::Acc` (no `Mat` store on this target). + - For `TileType::Vec`: + - `sizeof(TileData::DType) == sizeof(GlobalData::DType)`. + - `TileData::DType` must be one of: `int8_t`, `uint8_t`, `int16_t`, `uint16_t`, `int32_t`, `uint32_t`, `int64_t`, `uint64_t`, `half`, `bfloat16_t`, `float`, `float8_e4m3_t`, `float8_e5m2_t`, `hifloat8_t`, `float4_e1m2x2_t`, `float4_e2m1x2_t`. + - Layouts must match ND/DN/NZ (or a special case where `TileData::Rows == 1` or `TileData::Cols == 1`). + - Additional alignment constraints are enforced (e.g., for ND the row-major width in bytes must be a multiple of 32; for DN the column-major height in bytes must be a multiple of 32, with special-case exceptions). + - For `TileType::Acc`: + - Destination layout must be ND or NZ; source dtype must be `int32_t` or `float`. + - When not using quantization, destination dtype must be `__gm__ int32_t/float/half/bfloat16_t`. + - Static shape constraints match A2A3 for rows/cols; `AtomicAdd` additionally restricts destination dtype to supported atomic types. +- **有效区域**: + - The implementation uses `src.GetValidRow()` / `src.GetValidCol()` as the transfer size. + +## 示例 + +### 自动（Auto） + +```cpp +#include + +using namespace pto; + +template +void example_auto(__gm__ T* out) { + using TileT = Tile; + using GShape = Shape<1, 1, 1, 16, 16>; + using GStride = BaseShape2D; + using GTensor = GlobalTensor; + + GTensor gout(out); + TileT t; + TSTORE(gout, t); +} +``` + +### 手动（Manual） + +```cpp +#include + +using namespace pto; + +template +void example_manual(__gm__ T* out) { + using TileT = Tile; + using GShape = Shape<1, 1, 1, 16, 16>; + using GStride = BaseShape2D; + using GTensor = GlobalTensor; + + GTensor gout(out); + TileT t; + TASSIGN(t, 0x1000); + TSTORE(gout, t); +} +``` diff --git a/designs/outerCube/PTOISA/TSUB.md b/designs/outerCube/PTOISA/TSUB.md new file mode 100644 index 00000000..5f20459b --- /dev/null +++ b/designs/outerCube/PTOISA/TSUB.md @@ -0,0 +1,135 @@ +# TSUB + + +## Tile Operation Diagram + +![TSUB tile operation](../figures/isa/TSUB.svg) + +## Introduction + +Elementwise subtract of two tiles. + +## Math Interpretation + +For each element `(i, j)` in the valid region: + +$$ \mathrm{dst}_{i,j} = \mathrm{src0}_{i,j} - \mathrm{src1}_{i,j} $$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = tsub %src0, %src1 : !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tsub %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tsub ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### IR Level 1 (SSA) + +```text +%dst = pto.tsub %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### IR Level 2 (DPS) + +```text +pto.tsub ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TSUB(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, WaitEvents &... events); +``` + +## Constraints + +- **Implementation checks (A2A3)**: + - `TileData::DType` must be one of: `int32_t`, `int16_t`, `half`, `float`. + - Tile layout must be row-major (`TileData::isRowMajor`). + - Tile location must be vector (`TileData::Loc == TileType::Vec`). + - Static valid bounds: `TileData::ValidRow <= TileData::Rows` and `TileData::ValidCol <= TileData::Cols`. + - Runtime: `src0`, `src1` and `dst` tiles should have the same `validRow/validCol`. +- **Implementation checks (A5)**: + - `TileData::DType` must be one of: `uint32_t`, `int32_t`, `uint16_t`, `int16_t`, `uint8_t`, `int8_t`, `float`, `half`. + - Tile layout must be row-major (`TileData::isRowMajor`). + - Tile location must be vector (`TileData::Loc == TileType::Vec`). + - Static valid bounds: `TileData::ValidRow <= TileData::Rows` and `TileData::ValidCol <= TileData::Cols`. + - Runtime: `src0`, `src1` and `dst` tiles should have the same `validRow/validCol`. +- **Valid region**: + - The op uses `dst.GetValidRow()` / `dst.GetValidCol()` as the iteration domain; `src0/src1` are assumed to be compatible (not validated by explicit runtime checks in this op). + +## Examples + +### Auto + +```cpp +#include + +using namespace pto; + +void example_auto() { + using TileT = Tile; + TileT src0, src1, dst; + TSUB(dst, src0, src1); +} +``` + +### Manual + +```cpp +#include + +using namespace pto; + +void example_manual() { + using TileT = Tile; + TileT src0, src1, dst; + TASSIGN(src0, 0x1000); + TASSIGN(src1, 0x2000); + TASSIGN(dst, 0x3000); + TSUB(dst, src0, src1); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.tsub %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tsub %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = tsub %src0, %src1 : !pto.tile<...> +# AS Level 2 (DPS) +pto.tsub ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TSUBC.md b/designs/outerCube/PTOISA/TSUBC.md new file mode 100644 index 00000000..aa0ef697 --- /dev/null +++ b/designs/outerCube/PTOISA/TSUBC.md @@ -0,0 +1,103 @@ +# TSUBC + + +## Tile Operation Diagram + +![TSUBC tile operation](../figures/isa/TSUBC.svg) + +## Introduction + +Elementwise ternary op: `src0 - src1 + src2`. + +## Math Interpretation + +For each element `(i, j)` in the valid region: + +$$ \mathrm{dst}_{i,j} = \mathrm{src0}_{i,j} - \mathrm{src1}_{i,j} + \mathrm{src2}_{i,j} $$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = tsubc %src0, %src1, %src2 : !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tsubc %src0, %src1, %src2 : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tsubc ins(%src0, %src1, %src2 : !pto.tile_buf<...>, !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### IR Level 1 (SSA) + +```text +%dst = pto.tsubc %src0, %src1, %src2 : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### IR Level 2 (DPS) + +```text +pto.tsubc ins(%src0, %src1, %src2 : !pto.tile_buf<...>, !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TSUBC(TileData &dst, TileData &src0, TileData &src1, TileData &src2, WaitEvents &... events); +``` + +## Constraints + +- The op iterates over `dst.GetValidRow()` / `dst.GetValidCol()`. + +## Examples + +```cpp +#include + +using namespace pto; + +void example() { + using TileT = Tile; + TileT a, b, c, out; + TSUBC(out, a, b, c); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.tsubc %src0, %src1, %src2 : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tsubc %src0, %src1, %src2 : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = tsubc %src0, %src1, %src2 : !pto.tile<...> +# AS Level 2 (DPS) +pto.tsubc ins(%src0, %src1, %src2 : !pto.tile_buf<...>, !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TSUBC_zh.md b/designs/outerCube/PTOISA/TSUBC_zh.md new file mode 100644 index 00000000..100e1832 --- /dev/null +++ b/designs/outerCube/PTOISA/TSUBC_zh.md @@ -0,0 +1,76 @@ +# TSUBC + +## 指令示意图 + +![TSUBC tile operation](../figures/isa/TSUBC.svg) + +## 简介 + +三元逐元素运算：`src0 - src1 + src2`。 + +## 数学语义 + +对每个元素 `(i, j)` 在有效区域内： + +$$ \mathrm{dst}_{i,j} = \mathrm{src0}_{i,j} - \mathrm{src1}_{i,j} + \mathrm{src2}_{i,j} $$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS Specification](../assembly/PTO-AS.md). + +同步形式： + +```text +%dst = tsubc %src0, %src1, %src2 : !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tsubc %src0, %src1, %src2 : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tsubc ins(%src0, %src1, %src2 : !pto.tile_buf<...>, !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### AS Level 1（SSA） + +```text +%dst = pto.tsubc %src0, %src1, %src2 : (!pto.tile<...>, !pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.tsubc ins(%src0, %src1, %src2 : !pto.tile_buf<...>, !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TSUBC(TileData &dst, TileData &src0, TileData &src1, TileData &src2, WaitEvents &... events); +``` + +## 约束 + +- The op iterates over `dst.GetValidRow()` / `dst.GetValidCol()`. + +## 示例 + +```cpp +#include + +using namespace pto; + +void example() { + using TileT = Tile; + TileT a, b, c, out; + TSUBC(out, a, b, c); +} +``` diff --git a/designs/outerCube/PTOISA/TSUBS.md b/designs/outerCube/PTOISA/TSUBS.md new file mode 100644 index 00000000..4ce309b9 --- /dev/null +++ b/designs/outerCube/PTOISA/TSUBS.md @@ -0,0 +1,105 @@ +# TSUBS + + +## Tile Operation Diagram + +![TSUBS tile operation](../figures/isa/TSUBS.svg) + +## Introduction + +Elementwise subtract a scalar from a tile. + +## Math Interpretation + +For each element `(i, j)` in the valid region: + +$$ \mathrm{dst}_{i,j} = \mathrm{src}_{i,j} - \mathrm{scalar} $$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = tsubs %src, %scalar : !pto.tile<...>, f32 +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tsubs %src, %scalar : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tsubs ins(%src, %scalar : !pto.tile_buf<...>, dtype) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TSUBS(TileDataDst &dst, TileDataSrc &src0, typename TileDataSrc::DType scalar, WaitEvents &... events); +``` + +## Constraints + +- **Implementation checks (A2A3)**: + - `TileData::DType` must be one of: `int32_t`, `int`, `int16_t`, `half`, `float16_t`, `float`, `float32_t`. + - Tile location must be vector (`TileData::Loc == TileType::Vec`). + - Runtime: `src0.GetValidRow() == dst.GetValidRow()` and `src0.GetValidCol() == dst.GetValidCol()`. +- **Implementation checks (A5)**: + - `TileData::DType` must be one of: `int32_t`, `int`, `int16_t`, `half`, `float16_t`, `float`, `float32_t`. + - Tile location must be vector (`TileDataDst::Loc == TileType::Vec` and `TileDataSrc::Loc == TileType::Vec`). + - Static valid bounds: `TileDataDst::ValidRow <= TileDataDst::Rows`, `TileDataDst::ValidCol <= TileDataDst::Cols`, `TileDataSrc::ValidRow <= TileDataSrc::Rows`, and `TileDataSrc::ValidCol <= TileDataSrc::Cols`. + - Runtime: `src0.GetValidRow() == dst.GetValidRow()` and `src0.GetValidCol() == dst.GetValidCol()`. +- **Common constraints**: + - `dst` and `src0` must use the same element type. + - Scalar type must match `TileDataSrc::DType`. +- **Valid region**: + - The op uses `dst.GetValidRow()` / `dst.GetValidCol()` as the iteration domain. + +## Examples + +```cpp +#include + +using namespace pto; + +void example() { + using TileT = Tile; + TileT x, out; + TSUBS(out, x, 1.0f); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.tsubs %src, %scalar : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tsubs %src, %scalar : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = tsubs %src, %scalar : !pto.tile<...>, f32 +# AS Level 2 (DPS) +pto.tsubs ins(%src, %scalar : !pto.tile_buf<...>, dtype) outs(%dst : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/TSUBSC.md b/designs/outerCube/PTOISA/TSUBSC.md new file mode 100644 index 00000000..c04cf390 --- /dev/null +++ b/designs/outerCube/PTOISA/TSUBSC.md @@ -0,0 +1,116 @@ +# TSUBSC + + +## Tile Operation Diagram + +![TSUBSC tile operation](../figures/isa/TSUBSC.svg) + +## Introduction + +Elementwise fused op: `src0 - scalar + src1`. + +## Math Interpretation + +For each element `(i, j)` in the valid region: + +$$ \mathrm{dst}_{i,j} = \mathrm{src0}_{i,j} - \mathrm{scalar} + \mathrm{src1}_{i,j} $$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = tsubsc %src0, %scalar, %src1 : !pto.tile<...>, f32, !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tsubsc %src0, %scalar, %src1 : (!pto.tile<...>, dtype, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tsubsc ins(%src0, %scalar, %src1 : !pto.tile_buf<...>, dtype, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### IR Level 1 (SSA) + +```text +%dst = pto.tsubsc %src0, %scalar, %src1 : (!pto.tile<...>, dtype, !pto.tile<...>) -> !pto.tile<...> +``` + +### IR Level 2 (DPS) + +```text +pto.tsubsc ins(%src0, %scalar, %src1 : !pto.tile_buf<...>, dtype, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TSUBSC(TileData& dst, TileData& src0, typename TileData::DType scalar, TileData& src1, + WaitEvents&... events); +``` + +## Constraints + +- **Implementation checks (A2A3)**: + - `TileData::DType` must be one of: `int32_t`, `int16_t`, `half`, `float`. + - Tile layout must be row-major (`TileData::isRowMajor`). +- **Implementation checks (A5)**: + - `TileData::DType` must be one of: `int32_t`, `int16_t`, `half`, `float`. + - Tile layout must be row-major (`TileData::isRowMajor`). +- **Common constraints**: + - Tile location must be vector (`TileData::Loc == TileType::Vec`). + - Static valid bounds: `TileData::ValidRow <= TileData::Rows` and `TileData::ValidCol <= TileData::Cols`. + - Runtime: `dst`, `src0` and `src1` must have the same valid row/col. + - Scalar type must match the Tile data type. +- **Valid region**: + - The op uses `dst.GetValidRow()` / `dst.GetValidCol()` as the iteration domain. + +## Examples + +```cpp +#include + +using namespace pto; + +void example() { + using TileT = Tile; + TileT a, b, out; + TSUBSC(out, a, 2.0f, b); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.tsubsc %src0, %scalar, %src1 : (!pto.tile<...>, dtype, !pto.tile<...>) -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tsubsc %src0, %scalar, %src1 : (!pto.tile<...>, dtype, !pto.tile<...>) -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = tsubsc %src0, %scalar, %src1 : !pto.tile<...>, f32, !pto.tile<...> +# AS Level 2 (DPS) +pto.tsubsc ins(%src0, %scalar, %src1 : !pto.tile_buf<...>, dtype, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TSUBSC_zh.md b/designs/outerCube/PTOISA/TSUBSC_zh.md new file mode 100644 index 00000000..3b34e713 --- /dev/null +++ b/designs/outerCube/PTOISA/TSUBSC_zh.md @@ -0,0 +1,89 @@ +# TSUBSC + +## 指令示意图 + +![TSUBSC tile operation](../figures/isa/TSUBSC.svg) + +## 简介 + +融合逐元素运算：`src0 - scalar + src1`。 + +## 数学语义 + +对每个元素 `(i, j)` 在有效区域内： + +$$ \mathrm{dst}_{i,j} = \mathrm{src0}_{i,j} - \mathrm{scalar} + \mathrm{src1}_{i,j} $$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS Specification](../assembly/PTO-AS.md). + +同步形式： + +```text +%dst = tsubsc %src0, %scalar, %src1 : !pto.tile<...>, f32, !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tsubsc %src0, %scalar, %src1 : (!pto.tile<...>, dtype, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tsubsc ins(%src0, %scalar, %src1 : !pto.tile_buf<...>, dtype, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### AS Level 1（SSA） + +```text +%dst = pto.tsubsc %src0, %scalar, %src1 : (!pto.tile<...>, dtype, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.tsubsc ins(%src0, %scalar, %src1 : !pto.tile_buf<...>, dtype, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TSUBSC(TileData& dst, TileData& src0, typename TileData::DType scalar, TileData& src1, + WaitEvents&... events); +``` + +## 约束 + +- **实现检查 (A2A3)**: + - `TileData::DType` must be one of: `int32_t`, `int16_t`, `half`, `float`. + - Tile 布局 must be row-major (`TileData::isRowMajor`). +- **实现检查 (A5)**: + - `TileData::DType` must be one of: `int32_t`, `int16_t`, `half`, `float`. + - Tile 布局 must be row-major (`TileData::isRowMajor`). +- **Common constraints**: + - Tile location must be vector (`TileData::Loc == TileType::Vec`). + - Static valid bounds: `TileData::ValidRow <= TileData::Rows` and `TileData::ValidCol <= TileData::Cols`. + - Runtime: `dst`, `src0` and `src1` must have the same valid row/col. + - Scalar type must match the Tile data type. +- **有效区域**: + - The op uses `dst.GetValidRow()` / `dst.GetValidCol()` as the iteration domain. + +## 示例 + +```cpp +#include + +using namespace pto; + +void example() { + using TileT = Tile; + TileT a, b, out; + TSUBSC(out, a, 2.0f, b); +} +``` diff --git a/designs/outerCube/PTOISA/TSUBS_zh.md b/designs/outerCube/PTOISA/TSUBS_zh.md new file mode 100644 index 00000000..5441db2b --- /dev/null +++ b/designs/outerCube/PTOISA/TSUBS_zh.md @@ -0,0 +1,105 @@ +# TSUBS + +## 指令示意图 + +![TSUBS tile operation](../figures/isa/TSUBS.svg) + +## 简介 + +从 Tile 中逐元素减去一个标量。 + +## 数学语义 + +对每个元素 `(i, j)` 在有效区域内： + +$$ \mathrm{dst}_{i,j} = \mathrm{src}_{i,j} - \mathrm{scalar} $$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS 规范](../assembly/PTO-AS_zh.md)。 + +同步形式： + +```text +%dst = tsubs %src, %scalar : !pto.tile<...>, f32 +``` + +### AS Level 1（SSA） + +```text +%dst = pto.tsubs %src, %scalar : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.tsubs ins(%src, %scalar : !pto.tile_buf<...>, dtype) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`： + +```cpp +template +PTO_INST RecordEvent TSUBS(TileDataDst &dst, TileDataSrc &src0, typename TileDataSrc::DType scalar, WaitEvents &... events); +``` + +## 约束 + +- **实现检查 (A2A3)**: + - `TileData::DType` 必须是以下之一：`int32_t`、`int`、`int16_t`、`half`、`float16_t`、`float`、`float32_t`。 + - Tile 位置必须是向量（`TileData::Loc == TileType::Vec`）。 + - 运行时：`src0.GetValidRow() == dst.GetValidRow()` 且 `src0.GetValidCol() == dst.GetValidCol()`。 +- **实现检查 (A5)**: + - `TileData::DType` 必须是以下之一：`int32_t`、`int`、`int16_t`、`half`、`float16_t`、`float`、`float32_t`。 + - Tile 位置必须是向量（`TileDataDst::Loc == TileType::Vec` 且 `TileDataSrc::Loc == TileType::Vec`）。 + - 静态有效边界：`TileDataDst::ValidRow <= TileDataDst::Rows`、`TileDataDst::ValidCol <= TileDataDst::Cols`、`TileDataSrc::ValidRow <= TileDataSrc::Rows`，且 `TileDataSrc::ValidCol <= TileDataSrc::Cols`。 + - 运行时：`src0.GetValidRow() == dst.GetValidRow()` 且 `src0.GetValidCol() == dst.GetValidCol()`。 +- **通用约束**: + - `dst` 和 `src0` 必须使用相同的元素类型。 + - 标量类型必须与 `TileDataSrc::DType` 一致。 +- **有效区域**: + - 该操作使用 `dst.GetValidRow()` / `dst.GetValidCol()` 作为迭代域。 + +## 示例 + +```cpp +#include + +using namespace pto; + +void example() { + using TileT = Tile; + TileT x, out; + TSUBS(out, x, 1.0f); +} +``` + +## 汇编示例（ASM） + +### 自动模式 + +```text +# 自动模式：由编译器/运行时负责资源放置与调度。 +%dst = pto.tsubs %src, %scalar : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### 手动模式 + +```text +# 手动模式：先显式绑定资源，再发射指令。 +# 可选（当该指令包含 tile 操作数时）： +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.tsubs %src, %scalar : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### PTO 汇编形式 + +```text +%dst = tsubs %src, %scalar : !pto.tile<...>, f32 +# AS Level 2 (DPS) +pto.tsubs ins(%src, %scalar : !pto.tile_buf<...>, dtype) outs(%dst : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/TSUBVIEW.md b/designs/outerCube/PTOISA/TSUBVIEW.md new file mode 100644 index 00000000..c423eb63 --- /dev/null +++ b/designs/outerCube/PTOISA/TSUBVIEW.md @@ -0,0 +1,89 @@ +# TSUBVIEW + + +## Tile Operation Diagram + +![TSUBVIEW tile operation](../figures/isa/TSUBVIEW.svg) + +## Introduction + +Reinterpret a tile as a subtile of another tile. + +## Math Interpretation + +- `rowIdx`: in the valid region of `src`, the starting row index of the `dst` subtile. +- `colIdx`: in the valid region of `src`, the starting column index of the `dst` subtile. + +For each element `(i, j)` in the valid region of `dst`: + +$$ \mathrm{dst}_{i,j} = \mathrm{src}_{\mathrm{rowIdx} + i,\mathrm{colIdx} + j} $$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + + +### IR Level 1 (SSA) +TODO + +### IR Level 2 (DPS) +TODO + + +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TSUBVIEW(TileDataDst &dst, TileDataSrc &src, uint16_t rowIdx, uint16_t colIdx, WaitEvents&... events); +``` + +## Constraints + +Enforced by `TSUBVIEW_IMPL`: + +- **Tile type must match**: `TileDataSrc::Loc == TileDataDst::Loc`. +- **Both tiles must have the same static capacity**: `TileDataSrc::Rows == TileDataDst::Rows` and `TileDataSrc::Cols == TileDataDst::Cols`. +- **Both tiles must have the same BLayout**: `TileDataSrc::BFractal == TileDataDst::BFractal`. +- **The source tile's validRow (validCol) is at least as big as the destination tile's validRow (validCol)** + +## Examples + +```cpp +#include + +using namespace pto; + +void example() { + using Src = Tile; + using Dst = Tile; + + Src src; + Dst dst0; + Dst dst1; + Dst dst2; + Dst dst3; + + // e.g. split into four 2x32 subtiles + TSUBVIEW(dst0, src, 0, 0); + TSUBVIEW(dst1, src, 0, 32); + TSUBVIEW(dst2, src, 2, 0); + TSUBVIEW(dst3, src, 2, 32); +} +``` + +## ASM Form Examples + +### Auto Mode + +TODO + +### Manual Mode + +TODO + +### PTO Assembly Form + +TODO + diff --git a/designs/outerCube/PTOISA/TSUBVIEW_zh.md b/designs/outerCube/PTOISA/TSUBVIEW_zh.md new file mode 100644 index 00000000..42f56e89 --- /dev/null +++ b/designs/outerCube/PTOISA/TSUBVIEW_zh.md @@ -0,0 +1,87 @@ +# TSUBVIEW + +## Tile操作图例 + +![TSUBVIEW tile operation](../figures/isa/TSUBVIEW.svg) + +## 简介 + +表达一个Tile是另一个Tile的subview。 + +## 数学表达 + +- `rowIdx`: 在`src`的有效区域内的起始行的索引。 +- `colIdx`: 在`src`的有效区域内的起始列的索引。 + +对于`dst`中有效区域内的每一个元素`(i, j)`： + +$$ \mathrm{dst}_{i,j} = \mathrm{src}_{\mathrm{rowIdx} + i,\mathrm{colIdx} + j} $$ + +## 汇编语法 + +PTO-AS form: 详见 [PTO-AS Specification](../assembly/PTO-AS.md). + +### IR Level 1 (SSA) + +TODO + +### IR Level 2 (DPS) + +TODO + +## C++ Intrinsic + +定义在 `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TSUBVIEW(TileDataDst &dst, TileDataSrc &src, uint16_t rowIdx, uint16_t colIdx, WaitEvents&... events); +``` + +## 限制 + +规定在`TSUBVIEW_IMPL`中: + +- **Tile类型必须相同**: `TileDataSrc::Loc == TileDataDst::Loc`. +- **输入和输出Tile的静态shape必须相同**: `TileDataSrc::Rows == TileDataDst::Rows` and `TileDataSrc::Cols == TileDataDst::Cols`. +- **输入和输出Tile的BLayout必须相同**: `TileDataSrc::BFractal == TileDataDst::BFractal`. +- **src的validRow和validCol必须大于等于dst的validRow和validCol** + +## 示例 + +```cpp +#include + +using namespace pto; + +void example() { + using Src = Tile; + using Dst = Tile; + + Src src; + Dst dst0; + Dst dst1; + Dst dst2; + Dst dst3; + + // e.g. split into four 2x32 subtiles + TSUBVIEW(dst0, src, 0, 0); + TSUBVIEW(dst1, src, 0, 32); + TSUBVIEW(dst2, src, 2, 0); + TSUBVIEW(dst3, src, 2, 32); +} +``` + +## ASM示例 + +### Auto模式 + +TODO + +### Manual模式 + +TODO + +### PTO汇编格式 + +TODO diff --git a/designs/outerCube/PTOISA/TSUB_zh.md b/designs/outerCube/PTOISA/TSUB_zh.md new file mode 100644 index 00000000..4a69783c --- /dev/null +++ b/designs/outerCube/PTOISA/TSUB_zh.md @@ -0,0 +1,108 @@ +# TSUB + +## 指令示意图 + +![TSUB tile operation](../figures/isa/TSUB.svg) + +## 简介 + +两个 Tile 的逐元素减法。 + +## 数学语义 + +对每个元素 `(i, j)` 在有效区域内： + +$$ \mathrm{dst}_{i,j} = \mathrm{src0}_{i,j} - \mathrm{src1}_{i,j} $$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS Specification](../assembly/PTO-AS.md). + +同步形式： + +```text +%dst = tsub %src0, %src1 : !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.tsub %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.tsub ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### AS Level 1（SSA） + +```text +%dst = pto.tsub %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.tsub ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TSUB(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, WaitEvents &... events); +``` + +## 约束 + +- **实现检查 (A2A3)**: + - `TileData::DType` must be one of: `int32_t`, `int16_t`, `half`, `float`. + - Tile 布局 must be row-major (`TileData::isRowMajor`). + - Tile location must be vector (`TileData::Loc == TileType::Vec`). + - Static valid bounds: `TileData::ValidRow <= TileData::Rows` and `TileData::ValidCol <= TileData::Cols`. + - Runtime: `src0`, `src1` and `dst` tiles should have the same `validRow/validCol`. +- **实现检查 (A5)**: + - `TileData::DType` must be one of: `uint32_t`, `int32_t`, `uint16_t`, `int16_t`, `uint8_t`, `int8_t`, `float`, `half`. + - Tile 布局 must be row-major (`TileData::isRowMajor`). + - Tile location must be vector (`TileData::Loc == TileType::Vec`). + - Static valid bounds: `TileData::ValidRow <= TileData::Rows` and `TileData::ValidCol <= TileData::Cols`. + - Runtime: `src0`, `src1` and `dst` tiles should have the same `validRow/validCol`. +- **有效区域**: + - The op uses `dst.GetValidRow()` / `dst.GetValidCol()` as the iteration domain; `src0/src1` are assumed to be compatible (not validated by explicit runtime checks in this op). + +## 示例 + +### 自动（Auto） + +```cpp +#include + +using namespace pto; + +void example_auto() { + using TileT = Tile; + TileT src0, src1, dst; + TSUB(dst, src0, src1); +} +``` + +### 手动（Manual） + +```cpp +#include + +using namespace pto; + +void example_manual() { + using TileT = Tile; + TileT src0, src1, dst; + TASSIGN(src0, 0x1000); + TASSIGN(src1, 0x2000); + TASSIGN(dst, 0x3000); + TSUB(dst, src0, src1); +} +``` diff --git a/designs/outerCube/PTOISA/TSYNC.md b/designs/outerCube/PTOISA/TSYNC.md new file mode 100644 index 00000000..7764c600 --- /dev/null +++ b/designs/outerCube/PTOISA/TSYNC.md @@ -0,0 +1,143 @@ +# TSYNC + + +## Tile Operation Diagram + +![TSYNC tile operation](../figures/isa/TSYNC.svg) + +## Introduction + +Synchronize PTO execution: + +- `TSYNC(events...)` waits on a set of explicit event tokens. +- `TSYNC()` inserts a pipeline barrier for a single vector op class. + +Many intrinsics in `include/pto/common/pto_instr.hpp` call `TSYNC(events...)` internally before issuing the instruction. + +## Math Interpretation + +Not applicable. + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Event operand form: + +```text +tsync %e0, %e1 : !pto.event<...>, !pto.event<...> +``` + +Single-op barrier form: + +```text +tsync.op #pto.op +``` + +### AS Level 1 (SSA) + +```text +// Level 1 (SSA) does not support explicit synchronization primitives. +``` + +### AS Level 2 (DPS) + +```text +pto.record_event[src_op, dst_op, eventID] +// 支持的op：TLOAD，TSTORE_ACC，TSTORE_VEC，TMOV_M2L，TMOV_M2S，TMOV_M2B，TMOV_M2V，TMOV_V2M，TMATMUL，TVEC +pto.wait_event[src_op, dst_op, eventID] +// 支持的op：TLOAD，TSTORE_ACC，TSTORE_VEC，TMOV_M2L，TMOV_M2S，TMOV_M2B，TMOV_M2V，TMOV_V2M，TMATMUL，TVEC +pto.barrier(op) +// 支持的op：TVEC,TMATMUL +``` + +In the current PTO-DSL front-end flow, `record_event` and `wait_event` should +be treated as low-level TSYNC forms. Front-end kernels SHOULD normally stay free +of explicit event wiring and rely on `ptoas --enable-insert-sync`. + +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST void TSYNC(); + +template +PTO_INST void TSYNC(WaitEvents &... events); +``` + +## Constraints + +- **Implementation checks (`TSYNC()`)**: + - `TSYNC_IMPL()` only supports vector-pipeline ops (`static_assert(pipe == PIPE_V)` in `include/pto/common/event.hpp`). +- **`TSYNC(events...)` semantics**: + - `TSYNC(events...)` calls `WaitAllEvents(events...)`, which invokes `events.Wait()` on each event token. In auto mode, this is no-op. + +## Examples + +### Auto + +```cpp +#include + +using namespace pto; + +void example_auto(__gm__ float* in) { + using TileT = Tile; + using GShape = Shape<1, 1, 1, 16, 16>; + using GStride = BaseShape2D; + using GT = GlobalTensor; + + GT gin(in); + TileT t; + Event e; + e = TLOAD(t, gin); + TSYNC(e); +} +``` + +### Manual + +```cpp +#include + +using namespace pto; + +void example_manual() { + using TileT = Tile; + TileT a, b, c; + Event e; + e = TADD(c, a, b); + TSYNC(); + TSYNC(e); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%result = pto.tsync ... +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%result = pto.tsync ... +``` + +### PTO Assembly Form + +```text +tsync %e0, %e1 : !pto.event<...>, !pto.event<...> +# AS Level 2 (DPS) +pto.record_event[src_op, dst_op, eventID] +``` + diff --git a/designs/outerCube/PTOISA/TSYNC_zh.md b/designs/outerCube/PTOISA/TSYNC_zh.md new file mode 100644 index 00000000..2d686d55 --- /dev/null +++ b/designs/outerCube/PTOISA/TSYNC_zh.md @@ -0,0 +1,141 @@ +# TSYNC + +## 指令示意图 + +![TSYNC tile operation](../figures/isa/TSYNC.svg) + +## 简介 + +同步 PTO 执行（等待事件或插入每操作流水线屏障）。 + +- `TSYNC(events...)` 等待一组显式事件令牌。 +- `TSYNC()` 为单个向量操作类插入流水线屏障。 + +`include/pto/common/pto_instr.hpp` 中的许多内建函数在发射指令前会在内部调用 `TSYNC(events...)`。 + +## 数学语义 + +不适用。 + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS 规范](../assembly/PTO-AS_zh.md)。 + +Event operand form: + +```text +tsync %e0, %e1 : !pto.event<...>, !pto.event<...> +``` + +Single-op barrier form: + +```text +tsync.op #pto.op +``` + +### AS Level 1（SSA） + +```text +// Level 1 (SSA) does not support explicit synchronization primitives. +``` + +### AS Level 2（DPS） + +```text +pto.record_event[src_op, dst_op, eventID] +// 支持的op：TLOAD， TSTORE_ACC，TSTORE_VEC，TMOV_M2L，TMOV_M2S，TMOV_M2B，TMOV_M2V，TMOV_V2M，TMATMUL，TVEC +pto.wait_event[src_op, dst_op, eventID] +// 支持的op：TLOAD， TSTORE_ACC，TSTORE_VEC，TMOV_M2L，TMOV_M2S，TMOV_M2B，TMOV_M2V，TMOV_V2M，TMATMUL，TVEC +pto.barrier(op) +// 支持的op：TVEC,TMATMUL +``` + +在当前 PTO-DSL 前端流程中，`record_event` 和 `wait_event` 应视为 TSYNC 的低层形式。 +前端 kernel 通常不应手工编写事件连线，而应依赖 `ptoas --enable-insert-sync` +自动插入同步。 + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`： + +```cpp +template +PTO_INST void TSYNC(); + +template +PTO_INST void TSYNC(WaitEvents &... events); +``` + +## 约束 + +- **实现检查（`TSYNC()`）**: + - `TSYNC_IMPL()` 仅支持向量流水线操作（`include/pto/common/event.hpp` 中通过 `static_assert(pipe == PIPE_V)` 强制执行）。 +- **`TSYNC(events...)` 语义**: + - `TSYNC(events...)` 调用 `WaitAllEvents(events...)`，后者对每个事件令牌调用 `events.Wait()`。在auto模式下是no-op。 + +## 示例 + +### 自动（Auto） + +```cpp +#include + +using namespace pto; + +void example_auto(__gm__ float* in) { + using TileT = Tile; + using GShape = Shape<1, 1, 1, 16, 16>; + using GStride = BaseShape2D; + using GT = GlobalTensor; + + GT gin(in); + TileT t; + Event e; + e = TLOAD(t, gin); + TSYNC(e); +} +``` + +### 手动（Manual） + +```cpp +#include + +using namespace pto; + +void example_manual() { + using TileT = Tile; + TileT a, b, c; + Event e; + e = TADD(c, a, b); + TSYNC(); + TSYNC(e); +} +``` + +## 汇编示例（ASM） + +### 自动模式 + +```text +# 自动模式：由编译器/运行时负责资源放置与调度。 +%result = pto.tsync ... +``` + +### 手动模式 + +```text +# 手动模式：先显式绑定资源，再发射指令。 +# 可选（当该指令包含 tile 操作数时）： +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%result = pto.tsync ... +``` + +### PTO 汇编形式 + +```text +tsync %e0, %e1 : !pto.event<...>, !pto.event<...> +# AS Level 2 (DPS) +pto.record_event[src_op, dst_op, eventID] +``` diff --git a/designs/outerCube/PTOISA/TTRANS.md b/designs/outerCube/PTOISA/TTRANS.md new file mode 100644 index 00000000..f2738063 --- /dev/null +++ b/designs/outerCube/PTOISA/TTRANS.md @@ -0,0 +1,144 @@ +# TTRANS + + +## Tile Operation Diagram + +![TTRANS tile operation](../figures/isa/TTRANS.svg) + +## Introduction + +Transpose with an implementation-defined temporary tile. + +## Math Interpretation + +For a 2D tile, over the effective transpose domain: + +$$ \mathrm{dst}_{i,j} = \mathrm{src}_{j,i} $$ + +Exact shape/layout and the transpose domain depend on the target (see Constraints). + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = ttrans %src : !pto.tile<...> -> !pto.tile<...> +``` +Lowering may introduce internal scratch tiles; the C++ intrinsic requires an explicit `tmp` operand. + +### AS Level 1 (SSA) + +```text +%dst = pto.ttrans %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.ttrans ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TTRANS(TileDataDst &dst, TileDataSrc &src, TileDataTmp &tmp, WaitEvents &... events); +``` + +## Constraints + +- **Implementation checks (A2A3)**: + - `sizeof(TileDataSrc::DType) == sizeof(TileDataDst::DType)`. + - Source layout must be row-major (`TileDataSrc::isRowMajor`). + - Element size must be `1`, `2`, or `4` bytes. + - Supported element types are restricted per element width: + - 4 bytes: `uint32_t`, `int32_t`, `float` + - 2 bytes: `uint16_t`, `int16_t`, `half`, `bfloat16_t` + - 1 byte: `uint8_t`, `int8_t` + - The transpose size is taken from `src.GetValidRow()` / `src.GetValidCol()`. +- **Implementation checks (A5)**: + - `sizeof(TileDataSrc::DType) == sizeof(TileDataDst::DType)`. + - 32-byte alignment constraints are enforced on the major dimension of both input and output (row-major checks `Cols * sizeof(T) % 32 == 0`, col-major checks `Rows * sizeof(T) % 32 == 0`). + - Supported element types are restricted per element width: + - 4 bytes: `uint32_t`, `int32_t`, `float` + - 2 bytes: `uint16_t`, `int16_t`, `half`, `bfloat16_t` + - 1 byte: `uint8_t`, `int8_t` + - The implementation operates over the static tile shape (`TileDataSrc::Rows/Cols`) and does not consult `GetValidRow/GetValidCol`. +- **Temporary tile**: + - The C++ API requires `tmp`, but some implementations may not use it. +- **ConvTile**: + - Transpose of ConvTile for `TileType::Vec` is supported。 Element size must be `1`、`2` or `4` bytes. Supported element types are `uint32_t`、`int32_t`、`float`、`uint16_t`、`int16_t`、`half`、`bfloat16_t`、`uint8_t`、`int8_t`. + - Format transformation from `NCHW` to `NC1HWC0` is supported, while `C1 == (C + C0 - 1)/C0`，HW matches alignment constraint，which means `H*W*sizeof(T)==0`. C0 means `c0_size`, which `C0 * sizeof(T) == 32`。C0 can also be 4. + - Format transformation from `NC1HWC0` to `FRACTAL_Z` is supported， while `N1 == (N + N0 - 1)/N0`。N0 should be 16. + +## Examples + +### Auto + +```cpp +#include + +using namespace pto; + +void example_auto() { + using SrcT = Tile; + using DstT = Tile; + using TmpT = Tile; + SrcT src; + DstT dst; + TmpT tmp; + TTRANS(dst, src, tmp); +} +``` + +### Manual + +```cpp +#include + +using namespace pto; + +void example_manual() { + using SrcT = Tile; + using DstT = Tile; + using TmpT = Tile; + SrcT src; + DstT dst; + TmpT tmp; + TASSIGN(src, 0x1000); + TASSIGN(dst, 0x2000); + TASSIGN(tmp, 0x3000); + TTRANS(dst, src, tmp); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.ttrans %src : !pto.tile<...> -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.ttrans %src : !pto.tile<...> -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = ttrans %src : !pto.tile<...> -> !pto.tile<...> +# AS Level 2 (DPS) +pto.ttrans ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/TTRANS_zh.md b/designs/outerCube/PTOISA/TTRANS_zh.md new file mode 100644 index 00000000..370e6082 --- /dev/null +++ b/designs/outerCube/PTOISA/TTRANS_zh.md @@ -0,0 +1,144 @@ +# TTRANS + +## 指令示意图 + +![TTRANS tile operation](../figures/isa/TTRANS.svg) + +## 简介 + +使用实现定义的临时 Tile 进行转置。 + +## 数学语义 + +对于二维 Tile，在有效转置域上： + +$$ \mathrm{dst}_{i,j} = \mathrm{src}_{j,i} $$ + +确切的形状/布局及转置域取决于目标硬件（参见约束）。 + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS 规范](../assembly/PTO-AS_zh.md)。 + +同步形式： + +```text +%dst = ttrans %src : !pto.tile<...> -> !pto.tile<...> +``` +降低时可能引入内部临时 Tile；C++ 内建接口需要显式传入 `tmp` 操作数。 + +### AS Level 1（SSA） + +```text +%dst = pto.ttrans %src : !pto.tile<...> -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.ttrans ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`： + +```cpp +template +PTO_INST RecordEvent TTRANS(TileDataDst &dst, TileDataSrc &src, TileDataTmp &tmp, WaitEvents &... events); +``` + +## 约束 + +- **实现检查 (A2A3)**: + - `sizeof(TileDataSrc::DType) == sizeof(TileDataDst::DType)`。 + - 源布局必须是行主序（`TileDataSrc::isRowMajor`）。 + - 元素大小必须是 `1`、`2` 或 `4` 字节。 + - 支持的元素类型按元素宽度限制如下： + - 4 字节：`uint32_t`、`int32_t`、`float` + - 2 字节：`uint16_t`、`int16_t`、`half`、`bfloat16_t` + - 1 字节：`uint8_t`、`int8_t` + - 转置大小取自 `src.GetValidRow()` / `src.GetValidCol()`。 +- **实现检查 (A5)**: + - `sizeof(TileDataSrc::DType) == sizeof(TileDataDst::DType)`。 + - 对输入和输出的主维度强制执行 32 字节对齐约束（行主序检查 `Cols * sizeof(T) % 32 == 0`，列主序检查 `Rows * sizeof(T) % 32 == 0`）。 + - 支持的元素类型按元素宽度限制如下： + - 4 字节：`uint32_t`、`int32_t`、`float` + - 2 字节：`uint16_t`、`int16_t`、`half`、`bfloat16_t` + - 1 字节：`uint8_t`、`int8_t` + - 实现在静态 Tile 形状（`TileDataSrc::Rows/Cols`）上运算，不参考 `GetValidRow/GetValidCol`。 +- **临时 Tile**: + - C++ API 需要 `tmp`，但某些实现可能不使用它。 +- **ConvTile**: + - 支持在`TileType::Vec`上的ConvTile的格式转换。其元素大小必须是 `1`、`2` 或 `4` 字节。元素类型限制为`uint32_t`、`int32_t`、`float`、`uint16_t`、`int16_t`、`half`、`bfloat16_t`、`uint8_t`、`int8_t`。 + - 支持ConvTile从`NCHW`到`NC1HWC0`的变换，其中`C1 == (C + C0 - 1)/C0`，HW满足对齐要求，即`H*W*sizeof(T)==0`. C0对应`c0_size`, 即`C0 * sizeof(T) == 32`。C0也可以为4。 + - 支持ConvTile从`NC1HWC0`到`FRACTAL_Z`的变换, 其中`N1 == (N + N0 - 1)/N0`。N0为16。 + +## 示例 + +### 自动（Auto） + +```cpp +#include + +using namespace pto; + +void example_auto() { + using SrcT = Tile; + using DstT = Tile; + using TmpT = Tile; + SrcT src; + DstT dst; + TmpT tmp; + TTRANS(dst, src, tmp); +} +``` + +### 手动（Manual） + +```cpp +#include + +using namespace pto; + +void example_manual() { + using SrcT = Tile; + using DstT = Tile; + using TmpT = Tile; + SrcT src; + DstT dst; + TmpT tmp; + TASSIGN(src, 0x1000); + TASSIGN(dst, 0x2000); + TASSIGN(tmp, 0x3000); + TTRANS(dst, src, tmp); +} +``` + +## 汇编示例（ASM） + +### 自动模式 + +```text +# 自动模式：由编译器/运行时负责资源放置与调度。 +%dst = pto.ttrans %src : !pto.tile<...> -> !pto.tile<...> +``` + +### 手动模式 + +```text +# 手动模式：先显式绑定资源，再发射指令。 +# 可选（当该指令包含 tile 操作数时）： +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.ttrans %src : !pto.tile<...> -> !pto.tile<...> +``` + +### PTO 汇编形式 + +```text +%dst = ttrans %src : !pto.tile<...> -> !pto.tile<...> +# AS Level 2 (DPS) +pto.ttrans ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/TTRI.md b/designs/outerCube/PTOISA/TTRI.md new file mode 100644 index 00000000..d1b01b3e --- /dev/null +++ b/designs/outerCube/PTOISA/TTRI.md @@ -0,0 +1,98 @@ +# TTRI + + +## Tile Operation Diagram + +![TTRI tile operation](../figures/isa/TTRI.svg) + +## Introduction + +Generate a (lower/upper) triangular mask tile with ones and zeros. The triangular orientation is controlled by the compile-time template parameter `isUpperOrLower` (0 = lower, 1 = upper). + +## Math Interpretation + +Let `R = dst.GetValidRow()` and `C = dst.GetValidCol()`. Let `d = diagonal`. + +Lower-triangular (`isUpperOrLower=0`) conceptually produces: + +$$ +\mathrm{dst}_{i,j} = \begin{cases}1 & j \le i + d \\\\ 0 & \text{otherwise}\end{cases} +$$ + +Upper-triangular (`isUpperOrLower=1`) conceptually produces: + +$$ +\mathrm{dst}_{i,j} = \begin{cases}0 & j < i + d \\\\ 1 & \text{otherwise}\end{cases} +$$ + +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TTRI(TileData &dst, int diagonal, WaitEvents &... events); +``` + +## Constraints + +- `isUpperOrLower` must be `0` (lower) or `1` (upper). +- Destination tile must be row-major on some targets (see `include/pto/npu/*/TTri.hpp`). + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +### AS Level 1 (SSA) + +```text +%dst = pto.ttri %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.ttri ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### IR Level 1 (SSA) + +```text +%dst = pto.ttri %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### IR Level 2 (DPS) + +```text +pto.ttri ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## Examples + +See related examples in `docs/isa/` and `docs/coding/tutorials/`. + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.ttri %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.ttri %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = pto.ttri %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +# AS Level 2 (DPS) +pto.ttri ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` diff --git a/designs/outerCube/PTOISA/TTRI_zh.md b/designs/outerCube/PTOISA/TTRI_zh.md new file mode 100644 index 00000000..cf82b414 --- /dev/null +++ b/designs/outerCube/PTOISA/TTRI_zh.md @@ -0,0 +1,71 @@ +# TTRI + +## 指令示意图 + +![TTRI tile operation](../figures/isa/TTRI.svg) + +## 简介 + +生成三角（下/上）掩码 Tile。 + +## 数学语义 + +Let `R = dst.GetValidRow()` and `C = dst.GetValidCol()`. Let `d = diagonal`. + +Lower-triangular (`isUpperOrLower=0`) conceptually produces: + +$$ +\mathrm{dst}_{i,j} = \begin{cases}1 & j \le i + d \\\\ 0 & \text{otherwise}\end{cases} +$$ + +Upper-triangular (`isUpperOrLower=1`) conceptually produces: + +$$ +\mathrm{dst}_{i,j} = \begin{cases}0 & j < i + d \\\\ 1 & \text{otherwise}\end{cases} +$$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS Specification](../assembly/PTO-AS.md). + +### AS Level 1 (SSA) + +```text +%dst = pto.ttri %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.ttri ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +### AS Level 1（SSA） + +```text +%dst = pto.ttri %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.ttri ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TTRI(TileData &dst, int diagonal, WaitEvents &... events); +``` + +## 约束 + +- `isUpperOrLower` must be `0` (lower) or `1` (upper). +- Destination tile must be row-major on some targets (see `include/pto/npu/*/TTri.hpp`). + +## 示例 + +See related examples in `docs/isa/` and `docs/coding/tutorials/`. diff --git a/designs/outerCube/PTOISA/TXOR.md b/designs/outerCube/PTOISA/TXOR.md new file mode 100644 index 00000000..ab22c828 --- /dev/null +++ b/designs/outerCube/PTOISA/TXOR.md @@ -0,0 +1,110 @@ +# TXOR + + +## Tile Operation Diagram + +![TXOR tile operation](../figures/isa/TXOR.svg) + +## Introduction + +Elementwise bitwise XOR of two tiles. + +## Math Interpretation + +For each element `(i, j)` in the valid region: + +$$ \mathrm{dst}_{i,j} = \mathrm{src0}_{i,j} \oplus \mathrm{src1}_{i,j} $$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = txor %src0, %src1 : !pto.tile<...> +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.txor %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.txor ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TXOR(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, TileDataTmp &tmp, WaitEvents &... events); +``` + +## Constraints + +- The op iterates over `dst.GetValidRow()` / `dst.GetValidCol()`. +- **Implementation checks (A5)**: + - `dst`, `src0`, and `src1` element types must match. + - Supported element types are `uint8_t`, `int8_t`, `uint16_t`, `int16_t`, `uint32_t`, and `int32_t`. + - `dst`, `src0`, and `src1` must be row-major. + - `src0.GetValidRow()/GetValidCol()` and `src1.GetValidRow()/GetValidCol()` must match `dst`. +- **Implementation checks (A2A3)**: + - `dst`, `src0`, `src1`, and `tmp` element types must match. + - Supported element types are `uint8_t`, `int8_t`, `uint16_t`, and `int16_t`. + - `dst`, `src0`, `src1`, and `tmp` must be row-major. + - `src0`, `src1`, and `tmp` valid shapes must match `dst`. + - In manual mode, `dst`, `src0`, `src1`, and `tmp` must not overlap in memory. + +## Examples + +```cpp +#include + +using namespace pto; + +void example() { + using TileDst = Tile; + using TileSrc0 = Tile; + using TileSrc1 = Tile; + using TileTmp = Tile; + TileDst dst; + TileSrc0 src0; + TileSrc1 src1; + TileTmp tmp; + TXOR(dst, src0, src1, tmp); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.txor %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.txor %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = txor %src0, %src1 : !pto.tile<...> +# AS Level 2 (DPS) +pto.txor ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/TXORS.md b/designs/outerCube/PTOISA/TXORS.md new file mode 100644 index 00000000..9caa91d4 --- /dev/null +++ b/designs/outerCube/PTOISA/TXORS.md @@ -0,0 +1,105 @@ +# TXORS + + +## Tile Operation Diagram + +![TXORS tile operation](../figures/isa/TXORS.svg) + +## Introduction + +Elementwise bitwise XOR of a tile and a scalar. + +## Math Interpretation + +For each element `(i, j)` in the valid region: + +$$ \mathrm{dst}_{i,j} = \mathrm{src}_{i,j} \oplus \mathrm{scalar} $$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../assembly/PTO-AS.md). + +Synchronous form: + +```text +%dst = txors %src, %scalar : !pto.tile<...>, i32 +``` + +### AS Level 1 (SSA) + +```text +%dst = pto.txors %src, %scalar : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### AS Level 2 (DPS) + +```text +pto.txors ins(%src, %scalar : !pto.tile_buf<...>, dtype) outs(%dst : !pto.tile_buf<...>) +``` +## C++ Intrinsic + +Declared in `include/pto/common/pto_instr.hpp`: + +```cpp +template +PTO_INST RecordEvent TXORS(TileDataDst &dst, TileDataSrc &src0, typename TileDataSrc::DType scalar, TileDataTmp &tmp, WaitEvents &... events); +``` + +## Constraints + +- **Implementation checks (A2A3)**: + - Supported element types are `uint8_t`, `int8_t`, `uint16_t`, and `int16_t`. + - `dst`, `src`, and `tmp` must use the same element type. + - In manual mode, source, destination, and temporary storage must not overlap in memory. +- **Implementation checks (A5)**: + - Supported element types are `uint8_t`, `int8_t`, `uint16_t`, `int16_t`, `uint32_t`, and `int32_t`. + - `dst` and `src` element types must match. + - `src.GetValidRow()/GetValidCol()` must match `dst`. +- **Valid region**: + - The op uses `dst.GetValidRow()` / `dst.GetValidCol()` as the iteration domain. + +## Examples + +```cpp +#include + +using namespace pto; + +void example() { + using TileDst = Tile; + using TileSrc = Tile; + using TileTmp = Tile; + TileDst dst; + TileSrc src; + TileTmp tmp; + TXORS(dst, src, 0x1u, tmp); +} +``` + +## ASM Form Examples + +### Auto Mode + +```text +# Auto mode: compiler/runtime-managed placement and scheduling. +%dst = pto.txors %src, %scalar : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### Manual Mode + +```text +# Manual mode: bind resources explicitly before issuing the instruction. +# Optional for tile operands: +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.txors %src, %scalar : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### PTO Assembly Form + +```text +%dst = txors %src, %scalar : !pto.tile<...>, i32 +# AS Level 2 (DPS) +pto.txors ins(%src, %scalar : !pto.tile_buf<...>, dtype) outs(%dst : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/TXORS_zh.md b/designs/outerCube/PTOISA/TXORS_zh.md new file mode 100644 index 00000000..ebc0ed69 --- /dev/null +++ b/designs/outerCube/PTOISA/TXORS_zh.md @@ -0,0 +1,105 @@ +# TXORS + +## 指令示意图 + +![TXORS tile operation](../figures/isa/TXORS.svg) + +## 简介 + +Tile 与标量的逐元素按位异或。 + +## 数学语义 + +对每个元素 `(i, j)` 在有效区域内： + +$$ \mathrm{dst}_{i,j} = \mathrm{src}_{i,j} \oplus \mathrm{scalar} $$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS 规范](../assembly/PTO-AS_zh.md)。 + +同步形式： + +```text +%dst = txors %src, %scalar : !pto.tile<...>, i32 +``` + +### AS Level 1（SSA） + +```text +%dst = pto.txors %src, %scalar : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.txors ins(%src, %scalar : !pto.tile_buf<...>, dtype) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`： + +```cpp +template +PTO_INST RecordEvent TXORS(TileDataDst &dst, TileDataSrc &src0, typename TileDataSrc::DType scalar, TileDataTmp &tmp, WaitEvents &... events); +``` + +## 约束 + +- **实现检查 (A2A3)**: + - 支持的元素类型为 `uint8_t`、`int8_t`、`uint16_t` 和 `int16_t`。 + - `dst`、`src` 和 `tmp` 必须使用相同的元素类型。 + - 在手动模式下，源、目标和临时存储的内存区域不得重叠。 +- **实现检查 (A5)**: + - 支持的元素类型为 `uint8_t`、`int8_t`、`uint16_t`、`int16_t`、`uint32_t` 和 `int32_t`。 + - `dst` 和 `src` 的元素类型必须一致。 + - `src.GetValidRow()/GetValidCol()` 必须与 `dst` 一致。 +- **有效区域**: + - 该操作使用 `dst.GetValidRow()` / `dst.GetValidCol()` 作为迭代域。 + +## 示例 + +```cpp +#include + +using namespace pto; + +void example() { + using TileDst = Tile; + using TileSrc = Tile; + using TileTmp = Tile; + TileDst dst; + TileSrc src; + TileTmp tmp; + TXORS(dst, src, 0x1u, tmp); +} +``` + +## 汇编示例（ASM） + +### 自动模式 + +```text +# 自动模式：由编译器/运行时负责资源放置与调度。 +%dst = pto.txors %src, %scalar : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### 手动模式 + +```text +# 手动模式：先显式绑定资源，再发射指令。 +# 可选（当该指令包含 tile 操作数时）： +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.txors %src, %scalar : (!pto.tile<...>, dtype) -> !pto.tile<...> +``` + +### PTO 汇编形式 + +```text +%dst = txors %src, %scalar : !pto.tile<...>, i32 +# AS Level 2 (DPS) +pto.txors ins(%src, %scalar : !pto.tile_buf<...>, dtype) outs(%dst : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/TXOR_zh.md b/designs/outerCube/PTOISA/TXOR_zh.md new file mode 100644 index 00000000..ee3126fc --- /dev/null +++ b/designs/outerCube/PTOISA/TXOR_zh.md @@ -0,0 +1,110 @@ +# TXOR + +## 指令示意图 + +![TXOR tile operation](../figures/isa/TXOR.svg) + +## 简介 + +两个 Tile 的逐元素按位异或。 + +## 数学语义 + +对每个元素 `(i, j)` 在有效区域内： + +$$ \mathrm{dst}_{i,j} = \mathrm{src0}_{i,j} \oplus \mathrm{src1}_{i,j} $$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS 规范](../assembly/PTO-AS_zh.md)。 + +同步形式： + +```text +%dst = txor %src0, %src1 : !pto.tile<...> +``` + +### AS Level 1（SSA） + +```text +%dst = pto.txor %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### AS Level 2（DPS） + +```text +pto.txor ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + +## C++ 内建接口 + +声明于 `include/pto/common/pto_instr.hpp`： + +```cpp +template +PTO_INST RecordEvent TXOR(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, TileDataTmp &tmp, WaitEvents &... events); +``` + +## 约束 + +- 该操作在 `dst.GetValidRow()` / `dst.GetValidCol()` 上迭代。 +- **实现检查 (A5)**: + - `dst`、`src0` 和 `src1` 的元素类型必须一致。 + - 支持的元素类型为 `uint8_t`、`int8_t`、`uint16_t`、`int16_t`、`uint32_t` 和 `int32_t`。 + - `dst`、`src0` 和 `src1` 必须是行主序。 + - `src0.GetValidRow()/GetValidCol()` 和 `src1.GetValidRow()/GetValidCol()` 必须与 `dst` 一致。 +- **实现检查 (A2A3)**: + - `dst`、`src0`、`src1` 和 `tmp` 的元素类型必须一致。 + - 支持的元素类型为 `uint8_t`、`int8_t`、`uint16_t` 和 `int16_t`。 + - `dst`、`src0`、`src1` 和 `tmp` 必须是行主序。 + - `src0`、`src1` 和 `tmp` 的有效形状必须与 `dst` 一致。 + - 在手动模式下，`dst`、`src0`、`src1` 和 `tmp` 的内存区域不得重叠。 + +## 示例 + +```cpp +#include + +using namespace pto; + +void example() { + using TileDst = Tile; + using TileSrc0 = Tile; + using TileSrc1 = Tile; + using TileTmp = Tile; + TileDst dst; + TileSrc0 src0; + TileSrc1 src1; + TileTmp tmp; + TXOR(dst, src0, src1, tmp); +} +``` + +## 汇编示例（ASM） + +### 自动模式 + +```text +# 自动模式：由编译器/运行时负责资源放置与调度。 +%dst = pto.txor %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### 手动模式 + +```text +# 手动模式：先显式绑定资源，再发射指令。 +# 可选（当该指令包含 tile 操作数时）： +# pto.tassign %arg0, @tile(0x1000) +# pto.tassign %arg1, @tile(0x2000) +%dst = pto.txor %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...> +``` + +### PTO 汇编形式 + +```text +%dst = txor %src0, %src1 : !pto.tile<...> +# AS Level 2 (DPS) +pto.txor ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>) +``` + diff --git a/designs/outerCube/PTOISA/comm/README.md b/designs/outerCube/PTOISA/comm/README.md new file mode 100644 index 00000000..01bba656 --- /dev/null +++ b/designs/outerCube/PTOISA/comm/README.md @@ -0,0 +1,130 @@ +# PTO Communication ISA Reference + +This directory contains the per-instruction reference for the PTO Communication ISA. + +- Source of truth (C++ intrinsics): `include/pto/comm/pto_comm_inst.hpp` +- Type definitions: `include/pto/comm/comm_types.hpp` + +## Point-to-Point Communication (Synchronous) +- [**TPUT**](TPUT.md): Remote write (GM → UB → GM) +- [**TGET**](TGET.md): Remote read (GM → UB → GM) + +## Point-to-Point Communication (Asynchronous) +- [**TPUT_ASYNC**](TPUT_ASYNC.md): Asynchronous remote write (GM → DMA engine → GM) +- [**TGET_ASYNC**](TGET_ASYNC.md): Asynchronous remote read (GM → DMA engine → GM) + +## Signal-Based Synchronization +- [**TNOTIFY**](TNOTIFY.md): Send notification to remote NPU +- [**TWAIT**](TWAIT.md): Blocking wait for signal condition +- [**TTEST**](TTEST.md): Non-blocking test signal condition + +## Collective Communication + +- [**TGATHER**](TGATHER.md): Gather data from all ranks +- [**TSCATTER**](TSCATTER.md): Scatter data to all ranks +- [**TREDUCE**](TREDUCE.md): Reduce data from all ranks to local +- [**TBROADCAST**](TBROADCAST.md): Broadcast from current NPU to all ranks + +## Type Definitions + +### NotifyOp + +Operation type for `TNOTIFY`: + +| Value | Description | +|-------|-------------| +| `NotifyOp::Set` | Direct set (`signal = value`) | +| `NotifyOp::AtomicAdd` | Atomic add (`signal += value`) | + +### WaitCmp + +Comparison operators for `TWAIT` and `TTEST`: + +| Value | Description | +|-------|-------------| +| `WaitCmp::EQ` | Equal (`==`) | +| `WaitCmp::NE` | Not equal (`!=`) | +| `WaitCmp::GT` | Greater than (`>`) | +| `WaitCmp::GE` | Greater or equal (`>=`) | +| `WaitCmp::LT` | Less than (`<`) | +| `WaitCmp::LE` | Less or equal (`<=`) | + +```cpp +// Usage (unified runtime parameter style): +comm::TNOTIFY(signal, 1, comm::NotifyOp::Set); +comm::TWAIT(signal, 1, comm::WaitCmp::EQ); +comm::TTEST(signal, 1, comm::WaitCmp::GE); +``` + +### ReduceOp + +Reduction operators for `TREDUCE`: + +| Value | Description | +|-------|-------------| +| `ReduceOp::Sum` | Element-wise sum | +| `ReduceOp::Max` | Element-wise maximum | +| `ReduceOp::Min` | Element-wise minimum | + +### AtomicType + +Atomic operation type for `TPUT` (defined in `include/pto/common/constants.hpp`): + +| Value | Description | +|-------|-------------| +| `AtomicType::AtomicNone` | No atomic operation (default) | +| `AtomicType::AtomicAdd` | Atomic add operation | + +### DmaEngine + +DMA backend selection for `TPUT_ASYNC` and `TGET_ASYNC`: + +| Value | Description | +|-------|-------------| +| `DmaEngine::SDMA` | SDMA engine (supports 2D transfer) | +| `DmaEngine::URMA` | URMA engine (supports 1D transfer, todo) | + +### AsyncEvent + +Returned by `TPUT_ASYNC` / `TGET_ASYNC`. Use to synchronize completion: + +```cpp +struct AsyncEvent { + uint64_t handle; + DmaEngine engine; + + bool valid() const; // true if handle != 0 + bool Wait(const AsyncSession &session) const; // block until transfer completes + bool Test(const AsyncSession &session) const; // non-blocking completion check +}; +``` + +### AsyncSession + +Engine-agnostic session for async DMA operations. Build once, pass to all async calls: + +```cpp +comm::AsyncSession session; +comm::BuildAsyncSession(scratchTile, workspace, session); +``` + +Defined in `include/pto/comm/async/async_types.hpp`. See [TPUT_ASYNC](TPUT_ASYNC.md) for construction details and parameters. + +### ParallelGroup + +Wrapper for collective communication across multiple NPUs: + +```cpp +template +struct ParallelGroup { + // Pointer to an array of `GlobalData` objects (each wraps a GM address). + // The array itself is local metadata; the wrapped addresses may refer to local or remote GM, + // depending on the collective instruction. + GlobalData *tensors; + int nranks; // Number of ranks + int rootIdx; // Root NPU's rank index + + // Factory function (recommended): build from an existing tensor array. + static ParallelGroup Create(GlobalData *tensorArray, int size, int rank_id); +}; +``` diff --git a/designs/outerCube/PTOISA/comm/README_zh.md b/designs/outerCube/PTOISA/comm/README_zh.md new file mode 100644 index 00000000..ee826e32 --- /dev/null +++ b/designs/outerCube/PTOISA/comm/README_zh.md @@ -0,0 +1,131 @@ +# PTO 通信 ISA 参考手册 + +本目录包含 PTO 通信 ISA 的逐指令参考文档。 + +- 权威来源（C++ 内建接口）：`include/pto/comm/pto_comm_inst.hpp` +- 类型定义：`include/pto/comm/comm_types.hpp` + +## 点对点通信（同步） +- [**TPUT**](TPUT_zh.md)：远程写（GM → UB → GM） +- [**TGET**](TGET_zh.md)：远程读（GM → UB → GM） + +## 点对点通信（异步） +- [**TPUT_ASYNC**](TPUT_ASYNC_zh.md)：异步远程写（GM → DMA 引擎 → GM） +- [**TGET_ASYNC**](TGET_ASYNC_zh.md)：异步远程读（GM → DMA 引擎 → GM） + +## 基于信号的同步 +- [**TNOTIFY**](TNOTIFY_zh.md)：向远端 NPU 发送通知 +- [**TWAIT**](TWAIT_zh.md)：阻塞等待信号条件满足 +- [**TTEST**](TTEST_zh.md)：非阻塞检测信号条件 + +## 集合通信 + +- [**TGATHER**](TGATHER_zh.md)：从所有 rank 收集数据 +- [**TSCATTER**](TSCATTER_zh.md)：向所有 rank 分发数据 +- [**TREDUCE**](TREDUCE_zh.md)：从所有 rank 归约数据到本地 +- [**TBROADCAST**](TBROADCAST_zh.md)：从当前 NPU 广播数据到所有 rank + +## 类型定义 + +### NotifyOp + +`TNOTIFY` 的操作类型： + +| 值 | 说明 | +|-------|-------------| +| `NotifyOp::Set` | 直接赋值（`signal = value`）| +| `NotifyOp::AtomicAdd` | 原子加（`signal += value`）| + +### WaitCmp + +`TWAIT` 和 `TTEST` 的比较运算符： + +| 值 | 说明 | +|-------|-------------| +| `WaitCmp::EQ` | 等于（`==`）| +| `WaitCmp::NE` | 不等于（`!=`）| +| `WaitCmp::GT` | 大于（`>`）| +| `WaitCmp::GE` | 大于等于（`>=`）| +| `WaitCmp::LT` | 小于（`<`）| +| `WaitCmp::LE` | 小于等于（`<=`）| + +```cpp +// 用法示例（统一运行时参数风格）： +comm::TNOTIFY(signal, 1, comm::NotifyOp::Set); +comm::TWAIT(signal, 1, comm::WaitCmp::EQ); +comm::TTEST(signal, 1, comm::WaitCmp::GE); +``` + +### ReduceOp + +`TREDUCE` 的归约运算符： + +| 值 | 说明 | +|-------|-------------| +| `ReduceOp::Sum` | 逐元素求和 | +| `ReduceOp::Max` | 逐元素取最大值 | +| `ReduceOp::Min` | 逐元素取最小值 | + +### AtomicType + +`TPUT` 的原子操作类型（定义于 `include/pto/common/constants.hpp`）： + +| 值 | 说明 | +|-------|-------------| +| `AtomicType::AtomicNone` | 无原子操作（默认）| +| `AtomicType::AtomicAdd` | 原子加操作 | + +### DmaEngine + +`TPUT_ASYNC` 和 `TGET_ASYNC` 的 DMA 后端选择： + +| 值 | 说明 | +|-------|-------------| +| `DmaEngine::SDMA` | SDMA 引擎（支持二维传输）| +| `DmaEngine::URMA` | URMA 引擎（支持一维传输，待实现）| + +### AsyncEvent + +由 `TPUT_ASYNC` / `TGET_ASYNC` 返回，用于同步传输完成状态： + +```cpp +struct AsyncEvent { + uint64_t handle; + DmaEngine engine; + + bool valid() const; // handle != 0 时返回 true + bool Wait(const AsyncSession &session) const; // 阻塞直到传输完成 + bool Test(const AsyncSession &session) const; // 非阻塞完成检测 +}; +``` + +### AsyncSession + +用于异步 DMA 操作的引擎无关会话对象，构建一次后传递给所有异步调用： + +```cpp +comm::AsyncSession session; +comm::BuildAsyncSession(scratchTile, workspace, session); +``` + +定义于 `include/pto/comm/async/async_types.hpp`。构建参数详见 [TPUT_ASYNC](TPUT_ASYNC_zh.md)。 + +### ParallelGroup + +用于多 NPU 集合通信的包装器： + +```cpp +template +struct ParallelGroup { + // 指向 `GlobalData` 对象数组的指针（每个对象封装一个 GM 地址）。 + // 数组本身是本地元数据；封装的地址可以指向本地或远端 GM， + // 具体取决于集合通信指令的语义。 + GlobalData *tensors; + int nranks; // rank 总数 + int rootIdx; // 根 NPU 的 rank 索引 + + // 工厂函数（推荐）：从已有 tensor 数组构建。 + static ParallelGroup Create(GlobalData *tensorArray, int size, int rank_id); +}; +``` + diff --git a/designs/outerCube/PTOISA/comm/TBROADCAST.md b/designs/outerCube/PTOISA/comm/TBROADCAST.md new file mode 100644 index 00000000..1f0f613d --- /dev/null +++ b/designs/outerCube/PTOISA/comm/TBROADCAST.md @@ -0,0 +1,122 @@ +# TBROADCAST + +## Introduction + +Broadcast data from current NPU to all ranks in the parallel group. The calling NPU is the root and its data is copied to all other NPUs. + +Only the root needs to execute `TBROADCAST`. Non-root ranks only need to ensure their destination buffers are allocated and writable for the duration of the operation. Calling `TBROADCAST` on non-root ranks is undefined behavior. + +**Large Tile Support**: When the GlobalTensor exceeds the UB (Unified Buffer) tile capacity in rows and/or columns, the transfer is automatically chunked via 2D sliding. + +## Math Interpretation + +After the operation: + +$$ \mathrm{dst}^{(k)}_{i,j} = \mathrm{src}^{(\text{root})}_{i,j} \quad \forall k \in [0, N) $$ + +where $N$ is the number of ranks and `root` is the calling NPU. + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../../assembly/PTO-AS.md). + +Synchronous form: + +```text +tbroadcast %group, %src : (!pto.group<...>, !pto.memref<...>) +``` +Lowering introduces UB staging tile(s) for the GM→UB→GM data path; the C++ intrinsic requires explicit `stagingTileData` (or `pingTile` / `pongTile`) operand(s). + +## C++ Intrinsic + +Declared in `include/pto/comm/pto_comm_inst.hpp`: + +```cpp +// Basic broadcast (single staging tile) +template +PTO_INST RecordEvent TBROADCAST(ParallelGroupType ¶llelGroup, GlobalSrcData &srcGlobalData, + TileData &stagingTileData, WaitEvents&... events); + +// Ping-pong broadcast (double buffering with two staging tiles) +template +PTO_INST RecordEvent TBROADCAST(ParallelGroupType ¶llelGroup, GlobalSrcData &srcGlobalData, + TileData &pingTile, TileData &pongTile, WaitEvents&... events); +``` + +## Constraints + +- **Type constraints**: + - `ParallelGroup::value_type::RawDType` must equal `GlobalSrcData::RawDType`. + - `TileData::DType` must equal `GlobalSrcData::RawDType`. +- **Memory constraints**: + - `srcGlobalData` must point to local memory (current NPU). + - `stagingTileData` (or `pingTile` / `pongTile`) must be pre-allocated in UB. +- **ParallelGroup constraints**: + - `parallelGroup.tensors[k]` must refer to rank `k`'s destination buffer (remote GM as seen by the root). + - `parallelGroup.GetRootIdx()` identifies the calling NPU as the broadcast root. + - All destination tensors are assumed to have the same shape and strides. +- **Chunked mode constraints** (when data exceeds a single UB tile): + - If `TileData` has static `ValidRow`, `GetShape(DIM_3)` must be divisible by `ValidRow`. Use a Tile with `DYNAMIC` ValidRow for partial row support. + - If `TileData` has static `ValidCol`, `GetShape(DIM_4)` must be divisible by `ValidCol`. Use a Tile with `DYNAMIC` ValidCol for partial column support. + +## Examples + +### Basic Broadcast + +```cpp +#include + +using namespace pto; + +template +void broadcast(__gm__ T* group_addrs[NRANKS], __gm__ T* my_data, int my_rank) { + // Tile dimensions can differ from tensor dimensions. + // The 2D sliding chunked path automatically tiles both row and column. + using TileT = Tile; + using GTensor = GlobalTensor, + BaseShape2D, Layout::ND>; + + GTensor tensors[NRANKS]; + for (int i = 0; i < NRANKS; ++i) { + tensors[i] = GTensor(group_addrs[i]); + } + + comm::ParallelGroup group(tensors, NRANKS, my_rank); + GTensor srcG(my_data); + TileT stagingTile(TILE_ROWS, TILE_COLS); + + // Current NPU broadcasts its data to all others + comm::TBROADCAST(group, srcG, stagingTile); +} +``` + +### Ping-Pong Broadcast (Double Buffering) + +Uses two UB tiles to overlap TLOAD of the next chunk with TSTORE of the current chunk. + +```cpp +#include + +using namespace pto; + +template +void broadcast_pingpong(__gm__ T* group_addrs[NRANKS], __gm__ T* my_data, int my_rank) { + + using TileT = Tile; + using GPerRank = GlobalTensor, + BaseShape2D, Layout::ND>; + + GPerRank tensors[NRANKS]; + for (int i = 0; i < NRANKS; ++i) { + tensors[i] = GPerRank(group_addrs[i]); + } + + comm::ParallelGroup group(tensors, NRANKS, my_rank); + GPerRank srcG(my_data); + TileT pingTile(TILE_ROWS, TILE_COLS); + TileT pongTile(TILE_ROWS, TILE_COLS); + + // Ping-pong: overlaps TLOAD and TSTORE for better throughput + comm::TBROADCAST(group, srcG, pingTile, pongTile); +} +``` diff --git a/designs/outerCube/PTOISA/comm/TBROADCAST_zh.md b/designs/outerCube/PTOISA/comm/TBROADCAST_zh.md new file mode 100644 index 00000000..a82808a5 --- /dev/null +++ b/designs/outerCube/PTOISA/comm/TBROADCAST_zh.md @@ -0,0 +1,123 @@ +# TBROADCAST + +## 简介 + +将当前 NPU 的数据广播到并行组中所有 rank。调用方 NPU 为根节点，其数据将被复制到所有其他 NPU。 + +只有根节点需要执行 `TBROADCAST`。非根节点只需确保在操作期间其目标缓冲区已分配且可写。在非根节点上调用 `TBROADCAST` 属于未定义行为。 + +**大 Tile 支持**：当 GlobalTensor 在行和/或列方向超出 UB（统一缓冲区）Tile 容量时，传输将通过二维滑动自动分块。 + +## 数学语义 + +操作完成后： + +$$ \mathrm{dst}^{(k)}_{i,j} = \mathrm{src}^{(\text{root})}_{i,j} \quad \forall k \in [0, N) $$ + +其中 $N$ 为 rank 总数，`root` 为调用方 NPU。 + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS 规范](../../assembly/PTO-AS_zh.md)。 + +同步形式： + +```text +tbroadcast %group, %src : (!pto.group<...>, !pto.memref<...>) +``` + +降级时会为 GM→UB→GM 数据路径引入 UB 暂存 Tile；C++ 内建接口需要显式传入 `stagingTileData`（或 `pingTile` / `pongTile`）操作数。 + +## C++ 内建接口 + +声明于 `include/pto/comm/pto_comm_inst.hpp`： + +```cpp +// 基础广播（单暂存 Tile） +template +PTO_INST RecordEvent TBROADCAST(ParallelGroupType ¶llelGroup, GlobalSrcData &srcGlobalData, + TileData &stagingTileData, WaitEvents&... events); + +// 乒乓广播（使用两个暂存 Tile 实现双缓冲） +template +PTO_INST RecordEvent TBROADCAST(ParallelGroupType ¶llelGroup, GlobalSrcData &srcGlobalData, + TileData &pingTile, TileData &pongTile, WaitEvents&... events); +``` + +## 约束 + +- **类型约束**： + - `ParallelGroup::value_type::RawDType` 必须等于 `GlobalSrcData::RawDType`。 + - `TileData::DType` 必须等于 `GlobalSrcData::RawDType`。 +- **内存约束**： + - `srcGlobalData` 必须指向本地内存（当前 NPU）。 + - `stagingTileData`（或 `pingTile` / `pongTile`）必须预先在 UB 中分配。 +- **ParallelGroup 约束**： + - `parallelGroup.tensors[k]` 必须指向 rank `k` 的目标缓冲区（从根节点视角看到的远端 GM）。 + - `parallelGroup.GetRootIdx()` 标识调用方 NPU 为广播根节点。 + - 所有目标 tensor 假定具有相同的形状和步幅。 +- **分块模式约束**（数据超出单个 UB Tile 时）： + - 若 `TileData` 具有静态 `ValidRow`，则 `GetShape(DIM_3)` 必须能被 `ValidRow` 整除。如需支持不足一行的情况，请使用 `DYNAMIC` ValidRow 的 Tile。 + - 若 `TileData` 具有静态 `ValidCol`，则 `GetShape(DIM_4)` 必须能被 `ValidCol` 整除。如需支持不足一列的情况，请使用 `DYNAMIC` ValidCol 的 Tile。 + +## 示例 + +### 基础广播 + +```cpp +#include + +using namespace pto; + +template +void broadcast(__gm__ T* group_addrs[NRANKS], __gm__ T* my_data, int my_rank) { + // Tile 维度可以与 tensor 维度不同。 + // 二维滑动分块路径会自动在行和列两个方向进行分块。 + using TileT = Tile; + using GTensor = GlobalTensor, + BaseShape2D, Layout::ND>; + + GTensor tensors[NRANKS]; + for (int i = 0; i < NRANKS; ++i) { + tensors[i] = GTensor(group_addrs[i]); + } + + comm::ParallelGroup group(tensors, NRANKS, my_rank); + GTensor srcG(my_data); + TileT stagingTile(TILE_ROWS, TILE_COLS); + + // 当前 NPU 将自身数据广播到所有其他 NPU + comm::TBROADCAST(group, srcG, stagingTile); +} +``` + +### 乒乓广播（双缓冲） + +使用两个 UB Tile，将下一块的 TLOAD 与当前块的 TSTORE 重叠执行。 + +```cpp +#include + +using namespace pto; + +template +void broadcast_pingpong(__gm__ T* group_addrs[NRANKS], __gm__ T* my_data, int my_rank) { + + using TileT = Tile; + using GPerRank = GlobalTensor, + BaseShape2D, Layout::ND>; + + GPerRank tensors[NRANKS]; + for (int i = 0; i < NRANKS; ++i) { + tensors[i] = GPerRank(group_addrs[i]); + } + + comm::ParallelGroup group(tensors, NRANKS, my_rank); + GPerRank srcG(my_data); + TileT pingTile(TILE_ROWS, TILE_COLS); + TileT pongTile(TILE_ROWS, TILE_COLS); + + // 乒乓模式：将 TLOAD 与 TSTORE 重叠执行以提升吞吐量 + comm::TBROADCAST(group, srcG, pingTile, pongTile); +} +``` diff --git a/designs/outerCube/PTOISA/comm/TGATHER.md b/designs/outerCube/PTOISA/comm/TGATHER.md new file mode 100644 index 00000000..a5d3b35e --- /dev/null +++ b/designs/outerCube/PTOISA/comm/TGATHER.md @@ -0,0 +1,128 @@ +# TGATHER + +## Introduction + +Gather operation: the calling NPU (root) collects data from all ranks in the parallel group and concatenates the results along **DIM_3** (row dimension) into a local output buffer. + + +Only the root needs to execute `TGATHER`. Non-root ranks only need to ensure their source buffers are ready and remain valid for the duration of the operation. Calling `TGATHER` on non-root ranks is undefined behavior. + +**Large Tile Support**: When the GlobalTensor exceeds the UB tile capacity in rows and/or columns, the transfer is automatically chunked via 2D sliding — the same mechanism used by other PTO-COMM instructions. + +## Math Interpretation + +Each rank $r$ has source data of shape $(D_0, D_1, D_2, H, W)$. The gather concatenates all $N$ ranks along DIM_3: + +$$\mathrm{dst}_{d_0, d_1, d_2,\; r \cdot H + i,\; j} = \mathrm{src}^{(r)}_{d_0, d_1, d_2,\; i,\; j} \quad \forall\, r \in [0, N),\; i \in [0, H),\; j \in [0, W)$$ + +The destination tensor has shape $(D_0, D_1, D_2, N \times H, W)$. + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../../assembly/PTO-AS.md). + +Synchronous form: + +```text +tgather %group, %dst : (!pto.group<...>, !pto.memref<...>) +``` +Lowering introduces UB staging tile(s) for the GM→UB→GM data path; the C++ intrinsic requires explicit `stagingTileData` (or `pingTile` / `pongTile`) operand(s). + +## C++ Intrinsic + +Declared in `include/pto/comm/pto_comm_inst.hpp`: + +```cpp +// Basic gather (single staging tile) +template +PTO_INST RecordEvent TGATHER(ParallelGroupType ¶llelGroup, GlobalDstData &dstGlobalData, + TileData &stagingTileData, WaitEvents&... events); + +// Ping-pong gather (double buffering with two staging tiles) +template +PTO_INST RecordEvent TGATHER(ParallelGroupType ¶llelGroup, GlobalDstData &dstGlobalData, + TileData &pingTile, TileData &pongTile, WaitEvents&... events); +``` + +## Constraints + +- **Type constraints**: + - `ParallelGroup::value_type::RawDType` must equal `GlobalDstData::RawDType`. + - `TileData::DType` must equal `GlobalDstData::RawDType`. +- **Memory constraints**: + - `dstGlobalData` must point to local memory (current NPU) and be large enough to hold the concatenated result from all ranks. Specifically, `dstGlobalData.GetShape(DIM_3)` must be $\geq N \times H$ where $H$ is each rank's `GetShape(DIM_3)`. + - If `dstGlobalData.GetShape(DIM_3) > N × H`, only the first `N × H` rows are written; remaining rows are left unchanged. + - `stagingTileData` (or `pingTile` / `pongTile`) must be pre-allocated in UB. +- **ParallelGroup constraints**: + - `parallelGroup.tensors[r]` must refer to rank `r`'s source buffer (remote GM as seen by the root). + - `parallelGroup.GetRootIdx()` identifies the calling NPU as the gather root. + - All source tensors are assumed to have the same shape and strides; behavior is undefined if they differ. +- **Chunked mode constraints** (when source data exceeds a single UB tile): + - If `TileData` has static `ValidRow`, `GetShape(DIM_3)` of each rank's source must be divisible by `ValidRow`. Use a Tile with `DYNAMIC` ValidRow for partial row support. + - If `TileData` has static `ValidCol`, `GetShape(DIM_4)` must be divisible by `ValidCol`. Use a Tile with `DYNAMIC` ValidCol for partial column support. + +## Examples + +### Basic Gather (Single Staging Tile) + +Each rank contributes `ROWS × COLS` data. The root collects them into `NRANKS * ROWS` rows. +The tile size (`TILE_ROWS × TILE_COLS`) can be smaller than the per-rank data — when it is, the implementation automatically chunks the transfer along both DIM_3 and DIM_4 via 2D sliding. + +```cpp +#include + +using namespace pto; + +template +void gather(__gm__ T* group_addrs[NRANKS], __gm__ T* result, int my_rank) { + using TileT = Tile; + using GPerRank = GlobalTensor, + BaseShape2D, Layout::ND>; + using GResult = GlobalTensor, + BaseShape2D, Layout::ND>; + + GPerRank tensors[NRANKS]; + for (int i = 0; i < NRANKS; ++i) { + tensors[i] = GPerRank(group_addrs[i]); + } + + comm::ParallelGroup group(tensors, NRANKS, my_rank); + GResult dstG(result); + TileT stagingTile(TILE_ROWS, TILE_COLS); + + comm::TGATHER(group, dstG, stagingTile); +} +``` + +### Ping-Pong Gather (Double Buffering) + +Uses two UB tiles to overlap TLOAD of the next chunk (MTE2) with TSTORE of the current chunk (MTE3). + +```cpp +#include + +using namespace pto; + +template +void gather_pingpong(__gm__ T* group_addrs[NRANKS], __gm__ T* result, int my_rank) { + // Tile can be smaller than the data in both dimensions + using TileT = Tile; + using GPerRank = GlobalTensor, + BaseShape2D, Layout::ND>; + using GResult = GlobalTensor, + BaseShape2D, Layout::ND>; + + GPerRank tensors[NRANKS]; + for (int i = 0; i < NRANKS; ++i) { + tensors[i] = GPerRank(group_addrs[i]); + } + + comm::ParallelGroup group(tensors, NRANKS, my_rank); + GResult dstG(result); + TileT pingTile(TILE_ROWS, TILE_COLS); + TileT pongTile(TILE_ROWS, TILE_COLS); + + // Ping-pong: overlaps TLOAD and TSTORE for better throughput + comm::TGATHER(group, dstG, pingTile, pongTile); +} +``` diff --git a/designs/outerCube/PTOISA/comm/TGATHER_zh.md b/designs/outerCube/PTOISA/comm/TGATHER_zh.md new file mode 100644 index 00000000..699e50b1 --- /dev/null +++ b/designs/outerCube/PTOISA/comm/TGATHER_zh.md @@ -0,0 +1,121 @@ +# TGATHER + +## 简介 + +Gather 操作：调用方 NPU（根节点）从并行组中所有 rank 收集数据，并沿 **DIM_3**（行维度）拼接到本地输出缓冲区。 + +只有根节点需要执行 `TGATHER`。非根节点只需确保在操作期间其源缓冲区已就绪且保持有效。在非根节点上调用 `TGATHER` 属于未定义行为。 + +**大 Tile 支持**：当 GlobalTensor 在行和/或列方向超出 UB Tile 容量时，传输将通过二维滑动自动分块——与其他 PTO-COMM 指令采用相同机制。 + +## 数学语义 + +每个 rank $r$ 的源数据形状为 $(D_0, D_1, D_2, H, W)$。gather 沿 DIM_3 拼接所有 $N$ 个 rank 的数据： + +$$\mathrm{dst}_{d_0, d_1, d_2,\; r \cdot H + i,\; j} = \mathrm{src}^{(r)}_{d_0, d_1, d_2,\; i,\; j} \quad \forall\, r \in [0, N),\; i \in [0, H),\; j \in [0, W)$$ + +目标 tensor 的形状为 $(D_0, D_1, D_2, N \times H, W)$。 + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS 规范](../../assembly/PTO-AS_zh.md)。 + +同步形式： + +```text +tgather %group, %dst : (!pto.group<...>, !pto.memref<...>) +``` + +降级时会为 GM→UB→GM 数据路径引入 UB 暂存 Tile；C++ 内建接口需要显式传入 `stagingTileData`（或 `pingTile` / `pongTile`）操作数。 + +## C++ 内建接口 + +声明于 `include/pto/comm/pto_comm_inst.hpp`： + +```cpp +// 基础 gather（单暂存 Tile） +template +PTO_INST RecordEvent TGATHER(ParallelGroupType ¶llelGroup, GlobalDstData &dstGlobalData, + TileData &stagingTileData, WaitEvents&... events); + +// 乒乓 gather（使用两个暂存 Tile 实现双缓冲） +template +PTO_INST RecordEvent TGATHER(ParallelGroupType ¶llelGroup, GlobalDstData &dstGlobalData, + TileData &pingTile, TileData &pongTile, WaitEvents&... events); +``` + +## 约束 + +- **类型约束**： + - `ParallelGroup::value_type::RawDType` 必须等于 `GlobalDstData::RawDType`。 + - `TileData::DType` 必须等于 `GlobalDstData::RawDType`。 +- **内存约束**： + - `dstGlobalData` 必须指向本地内存（当前 NPU），且足够容纳所有 rank 拼接后的结果。具体要求：`dstGlobalData.GetShape(DIM_3)` 必须 $\geq N \times H$，其中 $H$ 为每个 rank 的 `GetShape(DIM_3)`。 + - 若 `dstGlobalData.GetShape(DIM_3) > N × H`，则只写入前 `N × H` 行，其余行保持不变。 + - `stagingTileData`（或 `pingTile` / `pongTile`）必须预先在 UB 中分配。 +- **ParallelGroup 约束**： + - `parallelGroup.tensors[r]` 必须指向 rank `r` 的源缓冲区（从根节点视角看到的远端 GM）。 + - `parallelGroup.GetRootIdx()` 标识调用方 NPU 为 gather 根节点。 + - 所有源 tensor 假定具有相同的形状和步幅；否则行为未定义。 +- **分块模式约束**（源数据超出单个 UB Tile 时）： + - 若 `TileData` 具有静态 `ValidRow`，则每个 rank 源数据的 `GetShape(DIM_3)` 必须能被 `ValidRow` 整除。如需支持不足一行的情况，请使用 `DYNAMIC` ValidRow 的 Tile。 + - 若 `TileData` 具有静态 `ValidCol`，则 `GetShape(DIM_4)` 必须能被 `ValidCol` 整除。如需支持不足一列的情况，请使用 `DYNAMIC` ValidCol 的 Tile。 + +## 示例 + +### 基础 Gather（单暂存 Tile） + +每个 rank 提供 `ROWS × COLS` 的数据，根节点将其收集到 `NRANKS * ROWS` 行中。 +Tile 大小（`TILE_ROWS × TILE_COLS`）可小于每 rank 的数据——此时实现会自动沿 DIM_3 和 DIM_4 通过二维滑动进行分块传输。 + +```cpp +#include + +using namespace pto; + +template +void gather(__gm__ T* group_addrs[NRANKS], __gm__ T* result, int my_rank) { + using TileT = Tile; + using GPerRank = GlobalTensor, + BaseShape2D, Layout::ND>; + using GResult = GlobalTensor, + BaseShape2D, Layout::ND>; + + GPerRank tensors[NRANKS]; + for (int i = 0; i < NRANKS; ++i) tensors[i] = GPerRank(group_addrs[i]); + + comm::ParallelGroup group(tensors, NRANKS, my_rank); + GResult dstG(result); + TileT stagingTile(TILE_ROWS, TILE_COLS); + comm::TGATHER(group, dstG, stagingTile); +} +``` + +### 乒乓 Gather（双缓冲） + +使用两个 UB Tile，将下一块的 TLOAD（MTE2）与当前块的 TSTORE（MTE3）重叠执行。 + +```cpp +#include + +using namespace pto; + +template +void gather_pingpong(__gm__ T* group_addrs[NRANKS], __gm__ T* result, int my_rank) { + using TileT = Tile; + using GPerRank = GlobalTensor, + BaseShape2D, Layout::ND>; + using GResult = GlobalTensor, + BaseShape2D, Layout::ND>; + + GPerRank tensors[NRANKS]; + for (int i = 0; i < NRANKS; ++i) tensors[i] = GPerRank(group_addrs[i]); + + comm::ParallelGroup group(tensors, NRANKS, my_rank); + GResult dstG(result); + TileT pingTile(TILE_ROWS, TILE_COLS); + TileT pongTile(TILE_ROWS, TILE_COLS); + // 乒乓模式：将 TLOAD 与 TSTORE 重叠执行以提升吞吐量 + comm::TGATHER(group, dstG, pingTile, pongTile); +} +``` diff --git a/designs/outerCube/PTOISA/comm/TGET.md b/designs/outerCube/PTOISA/comm/TGET.md new file mode 100644 index 00000000..0e000561 --- /dev/null +++ b/designs/outerCube/PTOISA/comm/TGET.md @@ -0,0 +1,109 @@ +# TGET + +## Introduction + +Remote read operation: read remote NPU's data to local memory. Data is transferred via a UB tile as intermediate staging buffer. + +When the GlobalTensor exceeds the UB tile capacity, TGET automatically performs **2D sliding** �?chunking rows (DIM_3) and columns (DIM_4) to fit each chunk into the tile, iterating over all outer dimensions (DIM_0, DIM_1, DIM_2). + +## Math Interpretation + +For each element `(i, j)` in the valid region: + +$$ \mathrm{dst}^{\mathrm{local}}_{i,j} = \mathrm{src}^{\mathrm{remote}}_{i,j} $$ + +Data flow: `srcGlobalData (remote GM)` �?`stagingTileData (UB)` �?`dstGlobalData (local GM)` + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../../assembly/PTO-AS.md). + +Synchronous form: + +```text +tget %dst_local, %src_remote : (!pto.memref<...>, !pto.memref<...>) +``` +Lowering introduces UB staging tile(s) for the GM→UB→GM data path; the C++ intrinsic requires explicit `stagingTileData` (or `pingTile` / `pongTile`) operand(s). + +## C++ Intrinsic + +Declared in `include/pto/comm/pto_comm_inst.hpp` + +### Single-tile (auto-chunking) + +```cpp +template +PTO_INST RecordEvent TGET(GlobalDstData &dstGlobalData, GlobalSrcData &srcGlobalData, + TileData &stagingTileData, WaitEvents&... events); +``` + +### Ping-pong double buffering + +Uses two staging tiles to overlap TLOAD and TSTORE for adjacent chunks, hiding one DMA transfer behind the other. + +```cpp +template +PTO_INST RecordEvent TGET(GlobalDstData &dstGlobalData, GlobalSrcData &srcGlobalData, + TileData &pingTile, TileData &pongTile, WaitEvents&... events); +``` + +## Constraints + +- **Type constraints**: + - `GlobalSrcData::RawDType` must equal `GlobalDstData::RawDType`. + - `TileData::DType` must equal `GlobalSrcData::RawDType`. + - `GlobalSrcData::layout` must equal `GlobalDstData::layout`. +- **Memory constraints**: + - `srcGlobalData` must point to remote address (on source NPU). + - `dstGlobalData` must point to local address (on current NPU). + - `stagingTileData` / `pingTile` / `pongTile` must be pre-allocated in Unified Buffer. +- **Valid region**: + - Transfer size is determined by `GlobalTensor` shape (auto-chunked to fit tile). +- **Ping-pong**: + - `pingTile` and `pongTile` must have the same type and dimensions. + - Must reside at non-overlapping UB offsets. + +## Examples + +### Basic Usage + +```cpp +#include +#include + +using namespace pto; + +template +void example_tget(__gm__ T* local_data, __gm__ T* remote_addr) { + using TileT = Tile; + using GShape = Shape<1, 1, 1, 16, 16>; + using GStride = BaseShape2D; + /* + If the globalTensor is larger than UB Tile, TGET will perform 2D sliding automatically. + using GShape = Shape<1, 1, 1, 4096, 4096>; + using GStride = BaseShape2D; + */ + using GTensor = GlobalTensor; + + GTensor srcG(remote_addr); + GTensor dstG(local_data); + TileT stagingTile; + TASSIGN(stagingTile, 0); + + // Basic remote read + comm::TGET(dstG, srcG, stagingTile); +} +``` + +### Ping-pong Double Buffering + +```cpp +constexpr size_t tileUBBytes = ((64 * 64 * sizeof(float) + 1023) / 1024) * 1024; +TileT pingTile(64, 64); +TileT pongTile(64, 64); +TASSIGN(pingTile, 0); +TASSIGN(pongTile, tileUBBytes); // Non-overlapping UB region + +// Overlaps TLOAD[i+1] with TSTORE[i] for better pipeline utilization +comm::TGET(dstG, srcG, pingTile, pongTile); +``` diff --git a/designs/outerCube/PTOISA/comm/TGET_ASYNC.md b/designs/outerCube/PTOISA/comm/TGET_ASYNC.md new file mode 100644 index 00000000..9a576051 --- /dev/null +++ b/designs/outerCube/PTOISA/comm/TGET_ASYNC.md @@ -0,0 +1,130 @@ +# TGET_ASYNC + +## Introduction + +`TGET_ASYNC` is an asynchronous remote read primitive. It starts a transfer from remote GM to local GM and returns an `AsyncEvent` immediately. + +Data flow: + +`srcGlobalData (remote GM) -> DMA engine -> dstGlobalData (local GM)` + +## Template Parameter + +- `engine`: + - `DmaEngine::SDMA` (default) + - `DmaEngine::URMA` (todo) + +> **Important (SDMA path)** +> `TGET_ASYNC` with `DmaEngine::SDMA` currently supports **only flat contiguous logical 1D tensors**. +> Non-1D or non-contiguous layouts are not supported by the current SDMA async implementation. + +## C++ Intrinsic + +Declared in `include/pto/comm/pto_comm_inst.hpp`. + +```cpp +template +PTO_INST AsyncEvent TGET_ASYNC(GlobalDstData &dstGlobalData, GlobalSrcData &srcGlobalData, + const AsyncSession &session, WaitEvents &... events); +``` + +`AsyncSession` is an engine-agnostic session object. Build once with +`BuildAsyncSession()`, then pass to all async calls and event waits. +The template `engine` parameter selects the DMA backend at compile time, making the +code forward-compatible with future engines (URMA, CCU, etc.). + +## AsyncSession Construction + +Use `BuildAsyncSession` from `include/pto/comm/async/async_event_impl.hpp`: + +```cpp +template +PTO_INTERNAL bool BuildAsyncSession(ScratchTile &scratchTile, + __gm__ uint8_t *workspace, + AsyncSession &session, + uint32_t syncId = 0, + const sdma::SdmaBaseConfig &baseConfig = {32 * 1024, 0, 1}, + uint32_t channelGroupIdx = sdma::kAutoChannelGroupIdx); +``` + +The engine template parameter selects the backend (currently only SDMA). + +Parameters with defaults: + +| Parameter | Default | Description | +|---|---|---| +| `syncId` | `0` | MTE3/MTE2 pipe sync event id (0-7). Override if kernel uses other pipe barriers on the same id. | +| `baseConfig` | `{32*1024, 0, 1}` | `{block_bytes, comm_block_offset, queue_num}`. Suitable for most single-queue transfers. | +| `channelGroupIdx` | `kAutoChannelGroupIdx` | SDMA channel group index. Default uses `get_block_idx()` internally, mapping to current AI core. Override for multi-block or custom channel mapping scenarios. | + +## Constraints + +- `GlobalSrcData::RawDType == GlobalDstData::RawDType` +- `GlobalSrcData::layout == GlobalDstData::layout` +- SDMA path requires source tensor to be **flat contiguous logical 1D only** +- workspace must be a valid GM pointer allocated by host-side `SdmaWorkspaceManager` + +If the 1D contiguous requirement is not met, current implementation returns an invalid async event (`handle == 0`). + +## scratchTile Role + +`scratchTile` is **not** used to hold transferred payload data. +It is converted to `TmpBuffer` and used as temporary UB workspace for: + +- writing/reading SDMA control words (flag, sq_tail, channel_info) +- polling event completion flags +- committing queue tail during completion + +The real payload path remains remote GM -> DMA engine -> local GM; `scratchTile` is only for control/synchronization metadata. + +## scratchTile Type and Size Constraints + +- must be a `pto::Tile` type +- must be UB/Vec tile (`ScratchTile::Loc == TileType::Vec`) +- available bytes must be at least `sizeof(uint64_t)` (8 bytes) + +Recommended: `Tile` (256B). + +## Completion Semantics + +Use `AsyncEvent` to synchronize: + +- `event.Wait(session)` — blocks until the transfer is complete + +After wait succeeds, reads into `dstGlobalData` are complete. + +## Example + +```cpp +#include +#include + +using namespace pto; + +template +__global__ AICORE void SimpleGet(__gm__ T *localDst, __gm__ T *remoteSrc, + __gm__ uint8_t *sdmaWorkspace) +{ + using ShapeDyn = Shape; + using StrideDyn = Stride; + using GT = GlobalTensor; + using ScratchTile = Tile; + + ShapeDyn shape(1, 1, 1, 1, 1024); + StrideDyn stride(1024, 1024, 1024, 1024, 1); + GT dstG(localDst, shape, stride); + GT srcG(remoteSrc, shape, stride); + + ScratchTile scratchTile; + TASSIGN(scratchTile, 0x0); + + comm::AsyncSession session; + if (!comm::BuildAsyncSession(scratchTile, sdmaWorkspace, session)) { + return; + } + + auto event = comm::TGET_ASYNC(dstG, srcG, session); + (void)event.Wait(session); +} +``` diff --git a/designs/outerCube/PTOISA/comm/TGET_ASYNC_zh.md b/designs/outerCube/PTOISA/comm/TGET_ASYNC_zh.md new file mode 100644 index 00000000..8f9a6383 --- /dev/null +++ b/designs/outerCube/PTOISA/comm/TGET_ASYNC_zh.md @@ -0,0 +1,126 @@ +# TGET_ASYNC + +## 简介 + +`TGET_ASYNC` 是异步远程读原语。它启动一次从远端 GM 到本地 GM 的传输，并立即返回 `AsyncEvent`。 + +数据流： + +`srcGlobalData（远端 GM）` → DMA 引擎 → `dstGlobalData（本地 GM）` + +## 模板参数 + +- `engine`： + - `DmaEngine::SDMA`（默认） + - `DmaEngine::URMA`（待实现） + +> **注意（SDMA 路径）** +> `TGET_ASYNC` 配合 `DmaEngine::SDMA` 目前**仅支持扁平连续的逻辑一维 tensor**。 +> 当前 SDMA 异步实现不支持非一维或非连续布局。 + +## C++ 内建接口 + +声明于 `include/pto/comm/pto_comm_inst.hpp`： + +```cpp +template +PTO_INST AsyncEvent TGET_ASYNC(GlobalDstData &dstGlobalData, GlobalSrcData &srcGlobalData, + const AsyncSession &session, WaitEvents &... events); +``` + +`AsyncSession` 是引擎无关的会话对象。使用 `BuildAsyncSession()` 构建一次后，传递给所有异步调用和事件等待。模板参数 `engine` 在编译期选择 DMA 后端，使代码对未来引擎（URMA、CCU 等）保持前向兼容。 + +## AsyncSession 构建 + +使用 `include/pto/comm/async/async_event_impl.hpp` 中的 `BuildAsyncSession`： + +```cpp +template +PTO_INTERNAL bool BuildAsyncSession(ScratchTile &scratchTile, + __gm__ uint8_t *workspace, + AsyncSession &session, + uint32_t syncId = 0, + const sdma::SdmaBaseConfig &baseConfig = {32 * 1024, 0, 1}, + uint32_t channelGroupIdx = sdma::kAutoChannelGroupIdx); +``` + +带默认值的参数说明： + +| 参数 | 默认值 | 说明 | +|---|---|---| +| `syncId` | `0` | MTE3/MTE2 管道同步事件 ID（0-7）。若 kernel 在相同 ID 上使用了其他管道屏障，则需覆盖此值。| +| `baseConfig` | `{32*1024, 0, 1}` | `{block_bytes, comm_block_offset, queue_num}`。适用于大多数单队列传输场景。| +| `channelGroupIdx` | `kAutoChannelGroupIdx` | SDMA 通道组索引。默认内部使用 `get_block_idx()` 映射到当前 AI Core。多 block 或自定义通道映射场景下需覆盖此值。| + +## 约束 + +- `GlobalSrcData::RawDType == GlobalDstData::RawDType` +- `GlobalSrcData::layout == GlobalDstData::layout` +- SDMA 路径要求源 tensor 为**扁平连续的逻辑一维** +- workspace 必须是由主机侧 `SdmaWorkspaceManager` 分配的有效 GM 指针 + +若不满足一维连续要求，当前实现返回无效 async event（`handle == 0`）。 + +## scratchTile 的作用 + +`scratchTile` **不是**用于传输数据负载的暂存缓冲区。 +它被转换为 `TmpBuffer`，用作临时 UB 工作区，用于： + +- 写入/读取 SDMA 控制字（flag、sq_tail、channel_info） +- 轮询事件完成标志 +- 完成时提交队列尾部 + +实际数据路径为远端 GM → DMA 引擎 → 本地 GM；`scratchTile` 仅用于控制和同步元数据。 + +## scratchTile 类型与大小约束 + +- 必须是 `pto::Tile` 类型 +- 必须是 UB/Vec tile（`ScratchTile::Loc == TileType::Vec`） +- 可用字节数至少为 `sizeof(uint64_t)`（8 字节） + +推荐使用：`Tile`（256B）。 + +## 完成语义 + +使用 `AsyncEvent` 同步： + +- `event.Wait(session)` — 阻塞直到传输完成 + +wait 成功后，读入 `dstGlobalData` 的数据已全部就绪。 + +## 示例 + +```cpp +#include +#include + +using namespace pto; + +template +__global__ AICORE void SimpleGet(__gm__ T *localDst, __gm__ T *remoteSrc, + __gm__ uint8_t *sdmaWorkspace) +{ + using ShapeDyn = Shape; + using StrideDyn = Stride; + using GT = GlobalTensor; + using ScratchTile = Tile; + + ShapeDyn shape(1, 1, 1, 1, 1024); + StrideDyn stride(1024, 1024, 1024, 1024, 1); + GT dstG(localDst, shape, stride); + GT srcG(remoteSrc, shape, stride); + + ScratchTile scratchTile; + TASSIGN(scratchTile, 0x0); + + comm::AsyncSession session; + if (!comm::BuildAsyncSession(scratchTile, sdmaWorkspace, session)) { + return; + } + + auto event = comm::TGET_ASYNC(dstG, srcG, session); + (void)event.Wait(session); +} +``` + diff --git a/designs/outerCube/PTOISA/comm/TGET_zh.md b/designs/outerCube/PTOISA/comm/TGET_zh.md new file mode 100644 index 00000000..2c39826f --- /dev/null +++ b/designs/outerCube/PTOISA/comm/TGET_zh.md @@ -0,0 +1,106 @@ +# TGET + +## 简介 + +远程读操作：将远端 NPU 的数据读取到本地内存。数据通过 UB Tile 作为中间暂存缓冲区进行传输。 + +当 GlobalTensor 超出 UB Tile 容量时，TGET 将自动执行**二维滑动**——沿行（DIM_3）和列（DIM_4）分块以适配 Tile，并遍历所有外层维度（DIM_0、DIM_1、DIM_2）。 + +## 数学语义 + +对有效区域内每个元素 `(i, j)`： + +$$\mathrm{dst}^{\mathrm{local}}_{i,j} = \mathrm{src}^{\mathrm{remote}}_{i,j}$$ + +数据流：`srcGlobalData（远端 GM）` → `stagingTileData（UB）` → `dstGlobalData（本地 GM）` + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS 规范](../../assembly/PTO-AS_zh.md)。 + +同步形式： + +```text +tget %dst_local, %src_remote : (!pto.memref<...>, !pto.memref<...>) +``` + +降级时会为 GM→UB→GM 数据路径引入 UB 暂存 Tile；C++ 内建接口需要显式传入 `stagingTileData`（或 `pingTile` / `pongTile`）操作数。 + +## C++ 内建接口 + +声明于 `include/pto/comm/pto_comm_inst.hpp` + +### 单 Tile（自动分块） + +```cpp +template +PTO_INST RecordEvent TGET(GlobalDstData &dstGlobalData, GlobalSrcData &srcGlobalData, + TileData &stagingTileData, WaitEvents&... events); +``` + +### 乒乓双缓冲 + +使用两个暂存 Tile，将相邻块的 TLOAD 与 TSTORE 重叠执行，隐藏 DMA 传输延迟。 + +```cpp +template +PTO_INST RecordEvent TGET(GlobalDstData &dstGlobalData, GlobalSrcData &srcGlobalData, + TileData &pingTile, TileData &pongTile, WaitEvents&... events); +``` + +## 约束 + +- **类型约束**： + - `GlobalSrcData::RawDType` 必须等于 `GlobalDstData::RawDType`。 + - `TileData::DType` 必须等于 `GlobalSrcData::RawDType`。 + - `GlobalSrcData::layout` 必须等于 `GlobalDstData::layout`。 +- **内存约束**： + - `srcGlobalData` 必须指向远端地址（源 NPU）。 + - `dstGlobalData` 必须指向本地地址（当前 NPU）。 + - `stagingTileData` / `pingTile` / `pongTile` 必须预先在统一缓冲区中分配。 +- **有效区域**： + - 传输大小由 `GlobalTensor` 的形状决定（自动分块以适配 Tile）。 +- **乒乓约束**： + - `pingTile` 和 `pongTile` 必须具有相同的类型和维度。 + - 必须位于不重叠的 UB 偏移处。 + +## 示例 + +### 基础用法 + +```cpp +#include +#include + +using namespace pto; + +template +void example_tget(__gm__ T* local_data, __gm__ T* remote_addr) { + using TileT = Tile; + using GShape = Shape<1, 1, 1, 16, 16>; + using GStride = BaseShape2D; + using GTensor = GlobalTensor; + + GTensor srcG(remote_addr); + GTensor dstG(local_data); + TileT stagingTile; + TASSIGN(stagingTile, 0); + + // 基础远程读 + comm::TGET(dstG, srcG, stagingTile); +} +``` + +### 乒乓双缓冲 + +```cpp +constexpr size_t tileUBBytes = ((64 * 64 * sizeof(float) + 1023) / 1024) * 1024; +TileT pingTile(64, 64); +TileT pongTile(64, 64); +TASSIGN(pingTile, 0); +TASSIGN(pongTile, tileUBBytes); // 不重叠的 UB 区域 + +// 将 TLOAD[i+1] 与 TSTORE[i] 重叠执行以提升流水线利用率 +comm::TGET(dstG, srcG, pingTile, pongTile); +``` + diff --git a/designs/outerCube/PTOISA/comm/TNOTIFY.md b/designs/outerCube/PTOISA/comm/TNOTIFY.md new file mode 100644 index 00000000..6bb80aa4 --- /dev/null +++ b/designs/outerCube/PTOISA/comm/TNOTIFY.md @@ -0,0 +1,100 @@ +# TNOTIFY + +## Introduction + +Send flag notification to remote NPU. Used for lightweight synchronization between NPUs without transferring bulk data. + +## Math Interpretation + +For `NotifyOp::Set`: + +$$ \mathrm{signal}^{\mathrm{remote}} = \mathrm{value} $$ + +For `NotifyOp::AtomicAdd`: + +$$ \mathrm{signal}^{\mathrm{remote}} \mathrel{+}= \mathrm{value} \quad (\text{atomic}) $$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../../assembly/PTO-AS.md). + +```text +tnotify %signal_remote, %value {op = #pto.notify_op} : (!pto.memref, i32) +tnotify %signal_remote, %value {op = #pto.notify_op} : (!pto.memref, i32) +``` + +## C++ Intrinsic + +Declared in `include/pto/comm/pto_comm_inst.hpp`: + +```cpp +template +PTO_INST void TNOTIFY(GlobalSignalData &dstSignalData, int32_t value, NotifyOp op, WaitEvents&... events); +``` + +## Constraints + +- **Type constraints**: + - `GlobalSignalData::DType` must be `int32_t` (32-bit signal). +- **Memory constraints**: + - `dstSignalData` must point to remote address (on target NPU). + - `dstSignalData` should be 4-byte aligned. +- **Operation semantics**: + - `NotifyOp::Set`: Direct store to remote memory. + - `NotifyOp::AtomicAdd`: Hardware atomic add using `st_atomic` instruction. + +## Examples + +### Basic Set Notification + +```cpp +#include + +using namespace pto; + +void notify_set(__gm__ int32_t* remote_signal) { + comm::Signal sig(remote_signal); + + // Set remote signal to 1 + comm::TNOTIFY(sig, 1, comm::NotifyOp::Set); +} +``` + +### Atomic Counter Increment + +```cpp +#include + +using namespace pto; + +void atomic_increment(__gm__ int32_t* remote_counter) { + comm::Signal counter(remote_counter); + + // Atomically add 1 to remote counter + comm::TNOTIFY(counter, 1, comm::NotifyOp::AtomicAdd); +} +``` + +### Producer-Consumer Pattern + +```cpp +#include + +using namespace pto; + +// Producer: notify when data is ready +void producer(__gm__ int32_t* remote_flag) { + // ... produce data ... + + comm::Signal flag(remote_flag); + comm::TNOTIFY(flag, 1, comm::NotifyOp::Set); +} + +// Consumer: wait for data +void consumer(__gm__ int32_t* local_flag) { + comm::Signal flag(local_flag); + comm::TWAIT(flag, 1, comm::WaitCmp::EQ); + + // ... consume data ... +} +``` diff --git a/designs/outerCube/PTOISA/comm/TNOTIFY_zh.md b/designs/outerCube/PTOISA/comm/TNOTIFY_zh.md new file mode 100644 index 00000000..d484bcfe --- /dev/null +++ b/designs/outerCube/PTOISA/comm/TNOTIFY_zh.md @@ -0,0 +1,101 @@ +# TNOTIFY + +## 简介 + +向远端 NPU 发送标志通知。用于 NPU 之间的轻量级同步，无需传输大量数据。 + +## 数学语义 + +`NotifyOp::Set` 时： + +$$\mathrm{signal}^{\mathrm{remote}} = \mathrm{value}$$ + +`NotifyOp::AtomicAdd` 时： + +$$\mathrm{signal}^{\mathrm{remote}} \mathrel{+}= \mathrm{value} \quad (\text{原子操作})$$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS 规范](../../assembly/PTO-AS_zh.md)。 + +```text +tnotify %signal_remote, %value {op = #pto.notify_op} : (!pto.memref, i32) +tnotify %signal_remote, %value {op = #pto.notify_op} : (!pto.memref, i32) +``` + +## C++ 内建接口 + +声明于 `include/pto/comm/pto_comm_inst.hpp`： + +```cpp +template +PTO_INST void TNOTIFY(GlobalSignalData &dstSignalData, int32_t value, NotifyOp op, WaitEvents&... events); +``` + +## 约束 + +- **类型约束**： + - `GlobalSignalData::DType` 必须为 `int32_t`（32 位信号）。 +- **内存约束**： + - `dstSignalData` 必须指向远端地址（目标 NPU）。 + - `dstSignalData` 应 4 字节对齐。 +- **操作语义**： + - `NotifyOp::Set`：直接存储到远端内存。 + - `NotifyOp::AtomicAdd`：使用 `st_atomic` 指令执行硬件原子加。 + +## 示例 + +### 基础 Set 通知 + +```cpp +#include + +using namespace pto; + +void notify_set(__gm__ int32_t* remote_signal) { + comm::Signal sig(remote_signal); + + // 将远端信号置为 1 + comm::TNOTIFY(sig, 1, comm::NotifyOp::Set); +} +``` + +### 原子计数器自增 + +```cpp +#include + +using namespace pto; + +void atomic_increment(__gm__ int32_t* remote_counter) { + comm::Signal counter(remote_counter); + + // 对远端计数器原子加 1 + comm::TNOTIFY(counter, 1, comm::NotifyOp::AtomicAdd); +} +``` + +### 生产者-消费者模式 + +```cpp +#include + +using namespace pto; + +// 生产者：数据就绪后发送通知 +void producer(__gm__ int32_t* remote_flag) { + // ... 生产数据 ... + + comm::Signal flag(remote_flag); + comm::TNOTIFY(flag, 1, comm::NotifyOp::Set); +} + +// 消费者：等待数据就绪 +void consumer(__gm__ int32_t* local_flag) { + comm::Signal flag(local_flag); + comm::TWAIT(flag, 1, comm::WaitCmp::EQ); + + // ... 消费数据 ... +} +``` + diff --git a/designs/outerCube/PTOISA/comm/TPUT.md b/designs/outerCube/PTOISA/comm/TPUT.md new file mode 100644 index 00000000..0c16a735 --- /dev/null +++ b/designs/outerCube/PTOISA/comm/TPUT.md @@ -0,0 +1,131 @@ +# TPUT + +## Introduction + +Remote write operation: write local data to remote NPU's memory. Data is transferred via a UB tile as intermediate staging buffer. + +When the GlobalTensor exceeds the UB tile capacity, TPUT automatically performs **2D sliding** — chunking rows (DIM_3) and columns (DIM_4) to fit each chunk into the tile, iterating over all outer dimensions (DIM_0, DIM_1, DIM_2). + +## Math Interpretation + +For each element `(i, j)` in the valid region: + +$$ \mathrm{dst}^{\mathrm{remote}}_{i,j} = \mathrm{src}^{\mathrm{local}}_{i,j} $$ + +Data flow: `srcGlobalData (local GM)` → `stagingTileData (UB)` → `dstGlobalData (remote GM)` + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../../assembly/PTO-AS.md). + +Synchronous form: + +```text +tput %dst_remote, %src_local : (!pto.memref<...>, !pto.memref<...>) +``` +Lowering introduces UB staging tile(s) for the GM→UB→GM data path; the C++ intrinsic requires explicit `stagingTileData` (or `pingTile` / `pongTile`) operand(s). + +## C++ Intrinsic + +Declared in `include/pto/comm/pto_comm_inst.hpp` + +### Single-tile (auto-chunking) + +```cpp +template +PTO_INST RecordEvent TPUT(GlobalDstData &dstGlobalData, GlobalSrcData &srcGlobalData, + TileData &stagingTileData, WaitEvents&... events); +``` + +### Ping-pong double buffering + +Uses two staging tiles to overlap TLOAD and TSTORE for adjacent chunks, hiding one DMA transfer behind the other. + +```cpp +template +PTO_INST RecordEvent TPUT(GlobalDstData &dstGlobalData, GlobalSrcData &srcGlobalData, + TileData &pingTile, TileData &pongTile, WaitEvents&... events); +``` + +### Runtime atomic type + +```cpp +template +PTO_INST RecordEvent TPUT(GlobalDstData &dstGlobalData, GlobalSrcData &srcGlobalData, + TileData &stagingTileData, AtomicType atomicType, WaitEvents&... events); +``` + +## Constraints + +- **Type constraints**: + - `GlobalSrcData::RawDType` must equal `GlobalDstData::RawDType`. + - `TileData::DType` must equal `GlobalSrcData::RawDType`. + - `GlobalSrcData::layout` must equal `GlobalDstData::layout`. +- **Memory constraints**: + - `dstGlobalData` must point to remote address (on target NPU). + - `srcGlobalData` must point to local address (on current NPU). + - `stagingTileData` / `pingTile` / `pongTile` must be pre-allocated in Unified Buffer. +- **Valid region**: + - Transfer size is determined by `GlobalTensor` shape (auto-chunked to fit tile). +- **Atomic operation**: + - `atomicType` supports `AtomicNone` and `AtomicAdd`. +- **Ping-pong**: + - `pingTile` and `pongTile` must have the same type and dimensions. + - Must reside at non-overlapping UB offsets. + +## Examples + +### Basic Usage + +```cpp +#include +#include + +using namespace pto; + +template +void example_tput(__gm__ T* local_data, __gm__ T* remote_addr) { + using TileT = Tile; + using GShape = Shape<1, 1, 1, 16, 16>; + using GStride = BaseShape2D; + /* + If the globalTensor is larger than UB Tile, TPUT will perform 2D sliding automatically. + using GShape = Shape<1, 1, 1, 4096, 4096>; + using GStride = BaseShape2D; + */ + using GTensor = GlobalTensor; + + GTensor srcG(local_data); + GTensor dstG(remote_addr); + TileT stagingTile; + TASSIGN(stagingTile, 0); + + // Basic remote write + comm::TPUT(dstG, srcG, stagingTile); + + // Remote write with atomic add + comm::TPUT(dstG, srcG, stagingTile); +} +``` + +### Ping-pong Double Buffering + +```cpp +constexpr size_t tileUBBytes = ((64 * 64 * sizeof(float) + 1023) / 1024) * 1024; +TileT pingTile(64, 64); +TileT pongTile(64, 64); +TASSIGN(pingTile, 0); +TASSIGN(pongTile, tileUBBytes); // Non-overlapping UB region + +// Overlaps TLOAD[i+1] with TSTORE[i] for better pipeline utilization +comm::TPUT(dstG, srcG, pingTile, pongTile); +``` + +### Runtime Atomic Type + +```cpp +// Select atomic type at runtime instead of compile-time template parameter +comm::TPUT(dstG, srcG, stagingTile, AtomicType::AtomicAdd); +``` \ No newline at end of file diff --git a/designs/outerCube/PTOISA/comm/TPUT_ASYNC.md b/designs/outerCube/PTOISA/comm/TPUT_ASYNC.md new file mode 100644 index 00000000..3d8a16aa --- /dev/null +++ b/designs/outerCube/PTOISA/comm/TPUT_ASYNC.md @@ -0,0 +1,132 @@ +# TPUT_ASYNC + +## Introduction + +`TPUT_ASYNC` is an asynchronous remote write primitive. It starts a transfer from local GM to remote GM and returns an `AsyncEvent` immediately. + +Data flow: + +`srcGlobalData (local GM) -> DMA engine -> dstGlobalData (remote GM)` + + +## Template Parameter + +- `engine`: + - `DmaEngine::SDMA` (default) + - `DmaEngine::URMA` (todo) + +> **Important (SDMA path)** +> `TPUT_ASYNC` with `DmaEngine::SDMA` currently supports **only flat contiguous logical 1D tensors**. +> Non-1D or non-contiguous layouts are not supported by the current SDMA async implementation. + + +## C++ Intrinsic + +Declared in `include/pto/comm/pto_comm_inst.hpp`. + +```cpp +template +PTO_INST AsyncEvent TPUT_ASYNC(GlobalDstData &dstGlobalData, GlobalSrcData &srcGlobalData, + const AsyncSession &session, WaitEvents &... events); +``` + +`AsyncSession` is an engine-agnostic session object. Build once with +`BuildAsyncSession()`, then pass to all async calls and event waits. +The template `engine` parameter selects the DMA backend at compile time, making the +code forward-compatible with future engines (URMA, CCU, etc.). + +## AsyncSession Construction + +Use `BuildAsyncSession` from `include/pto/comm/async/async_event_impl.hpp`: + +```cpp +template +PTO_INTERNAL bool BuildAsyncSession(ScratchTile &scratchTile, + __gm__ uint8_t *workspace, + AsyncSession &session, + uint32_t syncId = 0, + const sdma::SdmaBaseConfig &baseConfig = {32 * 1024, 0, 1}, + uint32_t channelGroupIdx = sdma::kAutoChannelGroupIdx); +``` + +The engine template parameter selects the backend (currently only SDMA). + +Parameters with defaults: + +| Parameter | Default | Description | +|---|---|---| +| `syncId` | `0` | MTE3/MTE2 pipe sync event id (0-7). Override if kernel uses other pipe barriers on the same id. | +| `baseConfig` | `{32*1024, 0, 1}` | `{block_bytes, comm_block_offset, queue_num}`. Suitable for most single-queue transfers. | +| `channelGroupIdx` | `kAutoChannelGroupIdx` | SDMA channel group index. Default uses `get_block_idx()` internally, mapping to current AI core. Override for multi-block or custom channel mapping scenarios. | + +## Constraints + +- `GlobalSrcData::RawDType == GlobalDstData::RawDType` +- `GlobalSrcData::layout == GlobalDstData::layout` +- SDMA path requires source tensor to be **flat contiguous logical 1D only** +- workspace must be a valid GM pointer allocated by host-side `SdmaWorkspaceManager` + +If the 1D contiguous requirement is not met, current implementation returns an invalid async event (`handle == 0`). + +## scratchTile Role + +`scratchTile` is **not** the payload staging buffer for user data. +It is converted to `TmpBuffer` and used as temporary UB workspace for: + +- writing/reading SDMA control words (flag, sq_tail, channel_info) +- polling event completion flags +- committing queue tail during completion + +Data payload moves between GM buffers directly; `scratchTile` only supports control and synchronization metadata. + +## scratchTile Type and Size Constraints + +- must be a `pto::Tile` type +- must be UB/Vec tile (`ScratchTile::Loc == TileType::Vec`) +- available bytes must be at least `sizeof(uint64_t)` (8 bytes) + +Recommended: `Tile` (256B). + +## Completion Semantics + +Use `AsyncEvent` to synchronize: + +- `event.Wait(session)` — blocks until the transfer is complete + +After wait succeeds, writes to `dstGlobalData` are complete. + +## Example + +```cpp +#include +#include + +using namespace pto; + +template +__global__ AICORE void SimplePut(__gm__ T *remoteDst, __gm__ T *localSrc, + __gm__ uint8_t *sdmaWorkspace) +{ + using ShapeDyn = Shape; + using StrideDyn = Stride; + using GT = GlobalTensor; + using ScratchTile = Tile; + + ShapeDyn shape(1, 1, 1, 1, 1024); + StrideDyn stride(1024, 1024, 1024, 1024, 1); + GT dstG(remoteDst, shape, stride); + GT srcG(localSrc, shape, stride); + + ScratchTile scratchTile; + TASSIGN(scratchTile, 0x0); + + comm::AsyncSession session; + if (!comm::BuildAsyncSession(scratchTile, sdmaWorkspace, session)) { + return; + } + + auto event = comm::TPUT_ASYNC(dstG, srcG, session); + (void)event.Wait(session); +} +``` diff --git a/designs/outerCube/PTOISA/comm/TPUT_ASYNC_zh.md b/designs/outerCube/PTOISA/comm/TPUT_ASYNC_zh.md new file mode 100644 index 00000000..ceb83763 --- /dev/null +++ b/designs/outerCube/PTOISA/comm/TPUT_ASYNC_zh.md @@ -0,0 +1,126 @@ +# TPUT_ASYNC + +## 简介 + +`TPUT_ASYNC` 是异步远程写原语。它启动一次从本地 GM 到远端 GM 的传输，并立即返回 `AsyncEvent`。 + +数据流： + +`srcGlobalData（本地 GM）` → DMA 引擎 → `dstGlobalData（远端 GM）` + +## 模板参数 + +- `engine`： + - `DmaEngine::SDMA`（默认） + - `DmaEngine::URMA`（待实现） + +> **注意（SDMA 路径）** +> `TPUT_ASYNC` 配合 `DmaEngine::SDMA` 目前**仅支持扁平连续的逻辑一维 tensor**。 +> 当前 SDMA 异步实现不支持非一维或非连续布局。 + +## C++ 内建接口 + +声明于 `include/pto/comm/pto_comm_inst.hpp`： + +```cpp +template +PTO_INST AsyncEvent TPUT_ASYNC(GlobalDstData &dstGlobalData, GlobalSrcData &srcGlobalData, + const AsyncSession &session, WaitEvents &... events); +``` + +`AsyncSession` 是引擎无关的会话对象。使用 `BuildAsyncSession()` 构建一次后，传递给所有异步调用和事件等待。模板参数 `engine` 在编译期选择 DMA 后端，使代码对未来引擎（URMA、CCU 等）保持前向兼容。 + +## AsyncSession 构建 + +使用 `include/pto/comm/async/async_event_impl.hpp` 中的 `BuildAsyncSession`： + +```cpp +template +PTO_INTERNAL bool BuildAsyncSession(ScratchTile &scratchTile, + __gm__ uint8_t *workspace, + AsyncSession &session, + uint32_t syncId = 0, + const sdma::SdmaBaseConfig &baseConfig = {32 * 1024, 0, 1}, + uint32_t channelGroupIdx = sdma::kAutoChannelGroupIdx); +``` + +带默认值的参数说明： + +| 参数 | 默认值 | 说明 | +|---|---|---| +| `syncId` | `0` | MTE3/MTE2 管道同步事件 ID（0-7）。若 kernel 在相同 ID 上使用了其他管道屏障，则需覆盖此值。| +| `baseConfig` | `{32*1024, 0, 1}` | `{block_bytes, comm_block_offset, queue_num}`。适用于大多数单队列传输场景。| +| `channelGroupIdx` | `kAutoChannelGroupIdx` | SDMA 通道组索引。默认内部使用 `get_block_idx()` 映射到当前 AI Core。多 block 或自定义通道映射场景下需覆盖此值。| + +## 约束 + +- `GlobalSrcData::RawDType == GlobalDstData::RawDType` +- `GlobalSrcData::layout == GlobalDstData::layout` +- SDMA 路径要求源 tensor 为**扁平连续的逻辑一维** +- workspace 必须是由主机侧 `SdmaWorkspaceManager` 分配的有效 GM 指针 + +若不满足一维连续要求，当前实现返回无效 async event（`handle == 0`）。 + +## scratchTile 的作用 + +`scratchTile` **不是**用于存放用户数据负载的暂存缓冲区。 +它被转换为 `TmpBuffer`，用作临时 UB 工作区，用于： + +- 写入/读取 SDMA 控制字（flag、sq_tail、channel_info） +- 轮询事件完成标志 +- 完成时提交队列尾部 + +实际数据负载直接在 GM 缓冲区之间传输；`scratchTile` 仅用于控制和同步元数据。 + +## scratchTile 类型与大小约束 + +- 必须是 `pto::Tile` 类型 +- 必须是 UB/Vec tile（`ScratchTile::Loc == TileType::Vec`） +- 可用字节数至少为 `sizeof(uint64_t)`（8 字节） + +推荐使用：`Tile`（256B）。 + +## 完成语义 + +使用 `AsyncEvent` 同步： + +- `event.Wait(session)` — 阻塞直到传输完成 + +wait 成功后，对 `dstGlobalData` 的写入已全部完成。 + +## 示例 + +```cpp +#include +#include + +using namespace pto; + +template +__global__ AICORE void SimplePut(__gm__ T *remoteDst, __gm__ T *localSrc, + __gm__ uint8_t *sdmaWorkspace) +{ + using ShapeDyn = Shape; + using StrideDyn = Stride; + using GT = GlobalTensor; + using ScratchTile = Tile; + + ShapeDyn shape(1, 1, 1, 1, 1024); + StrideDyn stride(1024, 1024, 1024, 1024, 1); + GT dstG(remoteDst, shape, stride); + GT srcG(localSrc, shape, stride); + + ScratchTile scratchTile; + TASSIGN(scratchTile, 0x0); + + comm::AsyncSession session; + if (!comm::BuildAsyncSession(scratchTile, sdmaWorkspace, session)) { + return; + } + + auto event = comm::TPUT_ASYNC(dstG, srcG, session); + (void)event.Wait(session); +} +``` + diff --git a/designs/outerCube/PTOISA/comm/TPUT_zh.md b/designs/outerCube/PTOISA/comm/TPUT_zh.md new file mode 100644 index 00000000..ad4a2da7 --- /dev/null +++ b/designs/outerCube/PTOISA/comm/TPUT_zh.md @@ -0,0 +1,128 @@ +# TPUT + +## 简介 + +远程写操作：将本地数据写入远端 NPU 的内存。数据通过 UB Tile 作为中间暂存缓冲区进行传输。 + +当 GlobalTensor 超出 UB Tile 容量时，TPUT 将自动执行**二维滑动**——沿行（DIM_3）和列（DIM_4）分块以适配 Tile，并遍历所有外层维度（DIM_0、DIM_1、DIM_2）。 + +## 数学语义 + +对有效区域内每个元素 `(i, j)`： + +$$\mathrm{dst}^{\mathrm{remote}}_{i,j} = \mathrm{src}^{\mathrm{local}}_{i,j}$$ + +数据流：`srcGlobalData（本地 GM）` → `stagingTileData（UB）` → `dstGlobalData（远端 GM）` + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS 规范](../../assembly/PTO-AS_zh.md)。 + +同步形式： + +```text +tput %dst_remote, %src_local : (!pto.memref<...>, !pto.memref<...>) +``` + +降级时会为 GM→UB→GM 数据路径引入 UB 暂存 Tile；C++ 内建接口需要显式传入 `stagingTileData`（或 `pingTile` / `pongTile`）操作数。 + +## C++ 内建接口 + +声明于 `include/pto/comm/pto_comm_inst.hpp` + +### 单 Tile（自动分块） + +```cpp +template +PTO_INST RecordEvent TPUT(GlobalDstData &dstGlobalData, GlobalSrcData &srcGlobalData, + TileData &stagingTileData, WaitEvents&... events); +``` + +### 乒乓双缓冲 + +使用两个暂存 Tile，将相邻块的 TLOAD 与 TSTORE 重叠执行，隐藏 DMA 传输延迟。 + +```cpp +template +PTO_INST RecordEvent TPUT(GlobalDstData &dstGlobalData, GlobalSrcData &srcGlobalData, + TileData &pingTile, TileData &pongTile, WaitEvents&... events); +``` + +### 运行时原子类型 + +```cpp +template +PTO_INST RecordEvent TPUT(GlobalDstData &dstGlobalData, GlobalSrcData &srcGlobalData, + TileData &stagingTileData, AtomicType atomicType, WaitEvents&... events); +``` + +## 约束 + +- **类型约束**： + - `GlobalSrcData::RawDType` 必须等于 `GlobalDstData::RawDType`。 + - `TileData::DType` 必须等于 `GlobalSrcData::RawDType`。 + - `GlobalSrcData::layout` 必须等于 `GlobalDstData::layout`。 +- **内存约束**： + - `dstGlobalData` 必须指向远端地址（目标 NPU）。 + - `srcGlobalData` 必须指向本地地址（当前 NPU）。 + - `stagingTileData` / `pingTile` / `pongTile` 必须预先在统一缓冲区中分配。 +- **有效区域**： + - 传输大小由 `GlobalTensor` 的形状决定（自动分块以适配 Tile）。 +- **原子操作**： + - `atomicType` 支持 `AtomicNone` 和 `AtomicAdd`。 +- **乒乓约束**： + - `pingTile` 和 `pongTile` 必须具有相同的类型和维度。 + - 必须位于不重叠的 UB 偏移处。 + +## 示例 + +### 基础用法 + +```cpp +#include +#include + +using namespace pto; + +template +void example_tput(__gm__ T* local_data, __gm__ T* remote_addr) { + using TileT = Tile; + using GShape = Shape<1, 1, 1, 16, 16>; + using GStride = BaseShape2D; + using GTensor = GlobalTensor; + + GTensor srcG(local_data); + GTensor dstG(remote_addr); + TileT stagingTile; + TASSIGN(stagingTile, 0); + + // 基础远程写 + comm::TPUT(dstG, srcG, stagingTile); + + // 带原子加的远程写 + comm::TPUT(dstG, srcG, stagingTile); +} +``` + +### 乒乓双缓冲 + +```cpp +constexpr size_t tileUBBytes = ((64 * 64 * sizeof(float) + 1023) / 1024) * 1024; +TileT pingTile(64, 64); +TileT pongTile(64, 64); +TASSIGN(pingTile, 0); +TASSIGN(pongTile, tileUBBytes); // 不重叠的 UB 区域 + +// 将 TLOAD[i+1] 与 TSTORE[i] 重叠执行以提升流水线利用率 +comm::TPUT(dstG, srcG, pingTile, pongTile); +``` + +### 运行时原子类型 + +```cpp +// 在运行时而非编译期模板参数中选择原子类型 +comm::TPUT(dstG, srcG, stagingTile, AtomicType::AtomicAdd); +``` + diff --git a/designs/outerCube/PTOISA/comm/TREDUCE.md b/designs/outerCube/PTOISA/comm/TREDUCE.md new file mode 100644 index 00000000..1a2e2c7e --- /dev/null +++ b/designs/outerCube/PTOISA/comm/TREDUCE.md @@ -0,0 +1,118 @@ +# TREDUCE + +## Introduction + +Reduce operation: gather data from multiple remote NPUs and perform element-wise reduction locally. + + +Only the root needs to execute `TREDUCE`. Non-root ranks only need to ensure their source buffers are ready and remain valid for the duration of the operation. Calling `TREDUCE` on non-root ranks is undefined behavior. + +**Large Tile Support**: When the GlobalTensor exceeds the UB tile capacity in rows and/or columns, the reduction is automatically chunked via 2D sliding. + +## Math Interpretation + +For each element `(i, j)` in the valid region: + +$$ \mathrm{dst}^{\mathrm{local}}_{i,j} = \bigoplus_{r=0}^{N-1} \mathrm{src}^{(r)}_{i,j} $$ + +where $N$ is the number of ranks and $\oplus$ is the reduction operation (sum, max, min, etc.). + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../../assembly/PTO-AS.md). + +Synchronous form: + +```text +treduce %group, %dst {op = #pto.reduce_op} : (!pto.group<...>, !pto.memref<...>) +treduce %group, %dst {op = #pto.reduce_op} : (!pto.group<...>, !pto.memref<...>) +``` +Lowering introduces internal accumulator and receive tiles for the reduce pipeline; the C++ intrinsic requires explicit `accTileData`, `recvTileData` (or `accTileData`, `pingTileData`, `pongTileData`) operand(s). + +## C++ Intrinsic + +Declared in `include/pto/comm/pto_comm_inst.hpp`: + +```cpp +// Basic reduce (accumulator + receive tile) +template +PTO_INST RecordEvent TREDUCE(ParallelGroupType ¶llelGroup, GlobalDstData &dstGlobalData, + TileData &accTileData, TileData &recvTileData, ReduceOp op, WaitEvents&... events); + +// Ping-pong reduce (accumulator + ping + pong tiles for double buffering) +template +PTO_INST RecordEvent TREDUCE(ParallelGroupType ¶llelGroup, GlobalDstData &dstGlobalData, + TileData &accTileData, TileData &pingTileData, TileData &pongTileData, + ReduceOp op, WaitEvents&... events); +``` + +## Constraints + +- **Type constraints**: + - `ParallelGroup::value_type::RawDType` must equal `GlobalDstData::RawDType`. + - `TileData::DType` must equal `GlobalDstData::RawDType`. +- **Memory constraints**: + - `dstGlobalData` must point to local address (on current NPU). + - `accTileData`, `recvTileData` (or `accTileData`, `pingTileData`, `pongTileData`) must be pre-allocated UB tiles. +- **ParallelGroup constraints**: + - `parallelGroup.tensors[r]` must refer to rank `r`'s source buffer (remote GM as seen by the root). + - `parallelGroup.GetRootIdx()` identifies the calling NPU as the reduce root. + - All source tensors are assumed to have the same shape and strides. +- **Chunked mode constraints** (when data exceeds a single UB tile): + - If `TileData` has static `ValidRow`, `GetShape(DIM_3)` must be divisible by `ValidRow`. Use a Tile with `DYNAMIC` ValidRow for partial row support. + - If `TileData` has static `ValidCol`, `GetShape(DIM_4)` must be divisible by `ValidCol`. Use a Tile with `DYNAMIC` ValidCol for partial column support. + +## Examples + +### Basic Reduce Sum + +```cpp +#include + +using namespace pto; + +template +void reduce_sum(__gm__ T* group_addrs[NRANKS], __gm__ T* result, int my_rank) { + using TileT = Tile; + using GTensor = GlobalTensor, + BaseShape2D, Layout::ND>; + + // Stack-allocated tensors + GTensor tensors[NRANKS]; + for (int i = 0; i < NRANKS; ++i) { + tensors[i] = GTensor(group_addrs[i]); + } + + comm::ParallelGroup group(tensors, NRANKS, my_rank); + GTensor dstG(result); + TileT accTile, recvTile; + + comm::TREDUCE(group, dstG, accTile, recvTile, comm::ReduceOp::Sum); +} +``` + +### Max Reduce + +```cpp +#include + +using namespace pto; + +template +void reduce_max(__gm__ T* group_addrs[NRANKS], __gm__ T* result, int my_rank) { + using TileT = Tile; + using GTensor = GlobalTensor, + BaseShape2D, Layout::ND>; + + GTensor tensors[NRANKS]; + for (int i = 0; i < NRANKS; ++i) { + tensors[i] = GTensor(group_addrs[i]); + } + + comm::ParallelGroup group(tensors, NRANKS, my_rank); + GTensor dstG(result); + TileT accTile, recvTile; + + comm::TREDUCE(group, dstG, accTile, recvTile, comm::ReduceOp::Max); +} +``` diff --git a/designs/outerCube/PTOISA/comm/TREDUCE_zh.md b/designs/outerCube/PTOISA/comm/TREDUCE_zh.md new file mode 100644 index 00000000..5f165efe --- /dev/null +++ b/designs/outerCube/PTOISA/comm/TREDUCE_zh.md @@ -0,0 +1,112 @@ +# TREDUCE + +## 简介 + +Reduce 操作：从多个远端 NPU 收集数据并在本地执行逐元素归约。 + +只有根节点需要执行 `TREDUCE`。非根节点只需确保在操作期间其源缓冲区已就绪且保持有效。在非根节点上调用 `TREDUCE` 属于未定义行为。 + +**大 Tile 支持**：当 GlobalTensor 在行和/或列方向超出 UB Tile 容量时，归约操作将通过二维滑动自动分块。 + +## 数学语义 + +对有效区域内每个元素 `(i, j)`： + +$$\mathrm{dst}^{\mathrm{local}}_{i,j} = \bigoplus_{r=0}^{N-1} \mathrm{src}^{(r)}_{i,j}$$ + +其中 $N$ 为 rank 总数，$\oplus$ 为归约运算（求和、取最大值、取最小值等）。 + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS 规范](../../assembly/PTO-AS_zh.md)。 + +同步形式： + +```text +treduce %group, %dst {op = #pto.reduce_op} : (!pto.group<...>, !pto.memref<...>) +treduce %group, %dst {op = #pto.reduce_op} : (!pto.group<...>, !pto.memref<...>) +``` + +降级时会为 reduce 流水线引入内部累加 Tile 和接收 Tile；C++ 内建接口需要显式传入 `accTileData`、`recvTileData`（或 `accTileData`、`pingTileData`、`pongTileData`）操作数。 + +## C++ 内建接口 + +声明于 `include/pto/comm/pto_comm_inst.hpp`： + +```cpp +// 基础 reduce（累加 Tile + 接收 Tile） +template +PTO_INST RecordEvent TREDUCE(ParallelGroupType ¶llelGroup, GlobalDstData &dstGlobalData, + TileData &accTileData, TileData &recvTileData, ReduceOp op, WaitEvents&... events); + +// 乒乓 reduce（累加 Tile + ping/pong Tile 实现双缓冲） +template +PTO_INST RecordEvent TREDUCE(ParallelGroupType ¶llelGroup, GlobalDstData &dstGlobalData, + TileData &accTileData, TileData &pingTileData, TileData &pongTileData, + ReduceOp op, WaitEvents&... events); +``` + +## 约束 + +- **类型约束**： + - `ParallelGroup::value_type::RawDType` 必须等于 `GlobalDstData::RawDType`。 + - `TileData::DType` 必须等于 `GlobalDstData::RawDType`。 +- **内存约束**： + - `dstGlobalData` 必须指向本地内存（当前 NPU）。 + - `accTileData`、`recvTileData`（或 `accTileData`、`pingTileData`、`pongTileData`）必须为预先分配的 UB Tile。 +- **ParallelGroup 约束**： + - `parallelGroup.tensors[r]` 必须指向 rank `r` 的源缓冲区（从根节点视角看到的远端 GM）。 + - `parallelGroup.GetRootIdx()` 标识调用方 NPU 为 reduce 根节点。 + - 所有源 tensor 假定具有相同的形状和步幅。 +- **分块模式约束**（数据超出单个 UB Tile 时）： + - 若 `TileData` 具有静态 `ValidRow`，则 `GetShape(DIM_3)` 必须能被 `ValidRow` 整除。如需支持不足一行的情况，请使用 `DYNAMIC` ValidRow 的 Tile。 + - 若 `TileData` 具有静态 `ValidCol`，则 `GetShape(DIM_4)` 必须能被 `ValidCol` 整除。如需支持不足一列的情况，请使用 `DYNAMIC` ValidCol 的 Tile。 + +## 示例 + +### 基础求和归约 + +```cpp +#include + +using namespace pto; + +template +void reduce_sum(__gm__ T* group_addrs[NRANKS], __gm__ T* result, int my_rank) { + using TileT = Tile; + using GTensor = GlobalTensor, + BaseShape2D, Layout::ND>; + + GTensor tensors[NRANKS]; + for (int i = 0; i < NRANKS; ++i) tensors[i] = GTensor(group_addrs[i]); + + comm::ParallelGroup group(tensors, NRANKS, my_rank); + GTensor dstG(result); + TileT accTile, recvTile; + comm::TREDUCE(group, dstG, accTile, recvTile, comm::ReduceOp::Sum); +} +``` + +### 最大值归约 + +```cpp +#include + +using namespace pto; + +template +void reduce_max(__gm__ T* group_addrs[NRANKS], __gm__ T* result, int my_rank) { + using TileT = Tile; + using GTensor = GlobalTensor, + BaseShape2D, Layout::ND>; + + GTensor tensors[NRANKS]; + for (int i = 0; i < NRANKS; ++i) tensors[i] = GTensor(group_addrs[i]); + + comm::ParallelGroup group(tensors, NRANKS, my_rank); + GTensor dstG(result); + TileT accTile, recvTile; + comm::TREDUCE(group, dstG, accTile, recvTile, comm::ReduceOp::Max); +} +``` + diff --git a/designs/outerCube/PTOISA/comm/TSCATTER.md b/designs/outerCube/PTOISA/comm/TSCATTER.md new file mode 100644 index 00000000..66e00ca3 --- /dev/null +++ b/designs/outerCube/PTOISA/comm/TSCATTER.md @@ -0,0 +1,126 @@ +# TSCATTER + +## Introduction + +Scatter operation: the calling NPU (root) distributes data to all ranks in the parallel group by splitting the local source tensor along **DIM_3** (row dimension). This is the inverse of `TGATHER`. + + +Only the root needs to execute `TSCATTER`. Non-root ranks only need to ensure their destination buffers are allocated and writable for the duration of the operation. Calling `TSCATTER` on non-root ranks is undefined behavior. + +**Large Tile Support**: When the per-rank data exceeds the UB tile capacity in rows and/or columns, the transfer is automatically chunked via 2D sliding. + +## Math Interpretation + +The local source tensor has shape $(D_0, D_1, D_2, N \times H, W)$, where $N$ is the number of ranks and each rank receives $H$ rows. After the operation: + +$$\mathrm{dst}^{(r)}_{d_0, d_1, d_2,\; i,\; j} = \mathrm{src}^{\mathrm{local}}_{d_0, d_1, d_2,\; r \cdot H + i,\; j} \quad \forall\, r \in [0, N),\; i \in [0, H),\; j \in [0, W)$$ + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../../assembly/PTO-AS.md). + +Synchronous form: + +```text +tscatter %group, %src : (!pto.group<...>, !pto.memref<...>) +``` +Lowering introduces UB staging tile(s) for the GM→UB→GM data path; the C++ intrinsic requires explicit `stagingTileData` (or `pingTile` / `pongTile`) operand(s). + +## C++ Intrinsic + +Declared in `include/pto/comm/pto_comm_inst.hpp`: + +```cpp +// Basic scatter (single staging tile) +template +PTO_INST RecordEvent TSCATTER(ParallelGroupType ¶llelGroup, GlobalSrcData &srcGlobalData, + TileData &stagingTileData, WaitEvents&... events); + +// Ping-pong scatter (double buffering with two staging tiles) +template +PTO_INST RecordEvent TSCATTER(ParallelGroupType ¶llelGroup, GlobalSrcData &srcGlobalData, + TileData &pingTile, TileData &pongTile, WaitEvents&... events); +``` + +## Constraints + +- **Type constraints**: + - `ParallelGroup::value_type::RawDType` must equal `GlobalSrcData::RawDType`. + - `TileData::DType` must equal `GlobalSrcData::RawDType`. +- **Memory constraints**: + - `srcGlobalData` must point to local memory (current NPU) and be large enough to hold data for all ranks. Specifically, `srcGlobalData.GetShape(DIM_3)` must be $\geq N \times H$ where $H$ is each rank's `GetShape(DIM_3)`. + - If `srcGlobalData.GetShape(DIM_3) > N × H`, only the first `N × H` rows are read; remaining rows are ignored. + - `stagingTileData` (or `pingTile` / `pongTile`) must be pre-allocated in UB. +- **ParallelGroup constraints**: + - `parallelGroup.tensors[r]` must refer to rank `r`'s destination buffer (remote GM as seen by the root). + - `parallelGroup.GetRootIdx()` identifies the calling NPU as the scatter root. + - All destination tensors are assumed to have the same shape and strides; behavior is undefined if they differ. +- **Chunked mode constraints** (when per-rank data exceeds a single UB tile): + - If `TileData` has static `ValidRow`, `GetShape(DIM_3)` of each rank's destination must be divisible by `ValidRow`. Use a Tile with `DYNAMIC` ValidRow for partial row support. + - If `TileData` has static `ValidCol`, `GetShape(DIM_4)` must be divisible by `ValidCol`. Use a Tile with `DYNAMIC` ValidCol for partial column support. + +## Examples + +### Basic Scatter (Single Staging Tile) + +Root has `NRANKS * ROWS` rows of width `COLS`. Each rank receives `ROWS × COLS`, split along DIM_3. +The tile size (`TILE_ROWS × TILE_COLS`) can be smaller than the per-rank data — when it is, the implementation automatically chunks the transfer along both DIM_3 and DIM_4 via 2D sliding. + +```cpp +#include + +using namespace pto; + +template +void scatter(__gm__ T* local_data, __gm__ T* group_addrs[NRANKS], int my_rank) { + using TileT = Tile; + using GPerRank = GlobalTensor, + BaseShape2D, Layout::ND>; + using GSource = GlobalTensor, + BaseShape2D, Layout::ND>; + + GPerRank tensors[NRANKS]; + for (int i = 0; i < NRANKS; ++i) { + tensors[i] = GPerRank(group_addrs[i]); + } + + comm::ParallelGroup group(tensors, NRANKS, my_rank); + GSource srcG(local_data); + TileT stagingTile(TILE_ROWS, TILE_COLS); + + comm::TSCATTER(group, srcG, stagingTile); +} +``` + +### Ping-Pong Scatter (Double Buffering) + +Uses two UB tiles to overlap TLOAD of the next chunk (MTE2) with TSTORE of the current chunk (MTE3). + +```cpp +#include + +using namespace pto; + +template +void scatter_pingpong(__gm__ T* local_data, __gm__ T* group_addrs[NRANKS], int my_rank) { + // Tile can be smaller than the data in both dimensions + using TileT = Tile; + using GPerRank = GlobalTensor, + BaseShape2D, Layout::ND>; + using GSource = GlobalTensor, + BaseShape2D, Layout::ND>; + + GPerRank tensors[NRANKS]; + for (int i = 0; i < NRANKS; ++i) { + tensors[i] = GPerRank(group_addrs[i]); + } + + comm::ParallelGroup group(tensors, NRANKS, my_rank); + GSource srcG(local_data); + TileT pingTile(TILE_ROWS, TILE_COLS); + TileT pongTile(TILE_ROWS, TILE_COLS); + + // Ping-pong: overlaps TLOAD and TSTORE for better throughput + comm::TSCATTER(group, srcG, pingTile, pongTile); +} +``` diff --git a/designs/outerCube/PTOISA/comm/TSCATTER_zh.md b/designs/outerCube/PTOISA/comm/TSCATTER_zh.md new file mode 100644 index 00000000..c353beab --- /dev/null +++ b/designs/outerCube/PTOISA/comm/TSCATTER_zh.md @@ -0,0 +1,120 @@ +# TSCATTER + +## 简介 + +Scatter 操作：调用方 NPU（根节点）将本地源 tensor 沿 **DIM_3**（行维度）拆分后分发到并行组中所有 rank。该操作是 `TGATHER` 的逆操作。 + +只有根节点需要执行 `TSCATTER`。非根节点只需确保在操作期间其目标缓冲区已分配且可写。在非根节点上调用 `TSCATTER` 属于未定义行为。 + +**大 Tile 支持**：当每 rank 的数据在行和/或列方向超出 UB Tile 容量时，传输将通过二维滑动自动分块。 + +## 数学语义 + +本地源 tensor 的形状为 $(D_0, D_1, D_2, N \times H, W)$，其中 $N$ 为 rank 总数，每个 rank 接收 $H$ 行。操作完成后： + +$$\mathrm{dst}^{(r)}_{d_0, d_1, d_2,\; i,\; j} = \mathrm{src}^{\mathrm{local}}_{d_0, d_1, d_2,\; r \cdot H + i,\; j} \quad \forall\, r \in [0, N),\; i \in [0, H),\; j \in [0, W)$$ + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS 规范](../../assembly/PTO-AS_zh.md)。 + +同步形式： + +```text +tscatter %group, %src : (!pto.group<...>, !pto.memref<...>) +``` + +降级时会为 GM→UB→GM 数据路径引入 UB 暂存 Tile；C++ 内建接口需要显式传入 `stagingTileData`（或 `pingTile` / `pongTile`）操作数。 + +## C++ 内建接口 + +声明于 `include/pto/comm/pto_comm_inst.hpp`： + +```cpp +// 基础 scatter（单暂存 Tile） +template +PTO_INST RecordEvent TSCATTER(ParallelGroupType ¶llelGroup, GlobalSrcData &srcGlobalData, + TileData &stagingTileData, WaitEvents&... events); + +// 乒乓 scatter（使用两个暂存 Tile 实现双缓冲） +template +PTO_INST RecordEvent TSCATTER(ParallelGroupType ¶llelGroup, GlobalSrcData &srcGlobalData, + TileData &pingTile, TileData &pongTile, WaitEvents&... events); +``` + +## 约束 + +- **类型约束**： + - `ParallelGroup::value_type::RawDType` 必须等于 `GlobalSrcData::RawDType`。 + - `TileData::DType` 必须等于 `GlobalSrcData::RawDType`。 +- **内存约束**： + - `srcGlobalData` 必须指向本地内存（当前 NPU），且足够容纳所有 rank 的数据。具体要求：`srcGlobalData.GetShape(DIM_3)` 必须 $\geq N \times H$，其中 $H$ 为每个 rank 的 `GetShape(DIM_3)`。 + - 若 `srcGlobalData.GetShape(DIM_3) > N × H`，则只读取前 `N × H` 行，其余行被忽略。 + - `stagingTileData`（或 `pingTile` / `pongTile`）必须预先在 UB 中分配。 +- **ParallelGroup 约束**： + - `parallelGroup.tensors[r]` 必须指向 rank `r` 的目标缓冲区（从根节点视角看到的远端 GM）。 + - `parallelGroup.GetRootIdx()` 标识调用方 NPU 为 scatter 根节点。 + - 所有目标 tensor 假定具有相同的形状和步幅；否则行为未定义。 +- **分块模式约束**（每 rank 数据超出单个 UB Tile 时）： + - 若 `TileData` 具有静态 `ValidRow`，则每个 rank 目标数据的 `GetShape(DIM_3)` 必须能被 `ValidRow` 整除。如需支持不足一行的情况，请使用 `DYNAMIC` ValidRow 的 Tile。 + - 若 `TileData` 具有静态 `ValidCol`，则 `GetShape(DIM_4)` 必须能被 `ValidCol` 整除。如需支持不足一列的情况，请使用 `DYNAMIC` ValidCol 的 Tile。 + +## 示例 + +### 基础 Scatter（单暂存 Tile） + +根节点拥有 `NRANKS * ROWS` 行、宽度为 `COLS` 的数据，每个 rank 接收 `ROWS × COLS`，沿 DIM_3 拆分。 +Tile 大小可小于每 rank 的数据——此时实现会自动通过二维滑动进行分块传输。 + +```cpp +#include + +using namespace pto; + +template +void scatter(__gm__ T* local_data, __gm__ T* group_addrs[NRANKS], int my_rank) { + using TileT = Tile; + using GPerRank = GlobalTensor, + BaseShape2D, Layout::ND>; + using GSource = GlobalTensor, + BaseShape2D, Layout::ND>; + + GPerRank tensors[NRANKS]; + for (int i = 0; i < NRANKS; ++i) tensors[i] = GPerRank(group_addrs[i]); + + comm::ParallelGroup group(tensors, NRANKS, my_rank); + GSource srcG(local_data); + TileT stagingTile(TILE_ROWS, TILE_COLS); + comm::TSCATTER(group, srcG, stagingTile); +} +``` + +### 乒乓 Scatter（双缓冲） + +使用两个 UB Tile，将下一块的 TLOAD（MTE2）与当前块的 TSTORE（MTE3）重叠执行。 + +```cpp +#include + +using namespace pto; + +template +void scatter_pingpong(__gm__ T* local_data, __gm__ T* group_addrs[NRANKS], int my_rank) { + using TileT = Tile; + using GPerRank = GlobalTensor, + BaseShape2D, Layout::ND>; + using GSource = GlobalTensor, + BaseShape2D, Layout::ND>; + + GPerRank tensors[NRANKS]; + for (int i = 0; i < NRANKS; ++i) tensors[i] = GPerRank(group_addrs[i]); + + comm::ParallelGroup group(tensors, NRANKS, my_rank); + GSource srcG(local_data); + TileT pingTile(TILE_ROWS, TILE_COLS); + TileT pongTile(TILE_ROWS, TILE_COLS); + // 乒乓模式：将 TLOAD 与 TSTORE 重叠执行以提升吞吐量 + comm::TSCATTER(group, srcG, pingTile, pongTile); +} +``` + diff --git a/designs/outerCube/PTOISA/comm/TTEST.md b/designs/outerCube/PTOISA/comm/TTEST.md new file mode 100644 index 00000000..184f1f43 --- /dev/null +++ b/designs/outerCube/PTOISA/comm/TTEST.md @@ -0,0 +1,150 @@ +# TTEST + +## Introduction + +Non-blocking test if signal(s) meet comparison condition. Returns `true` if condition is satisfied, `false` otherwise. Used for polling-based synchronization with timeout or interleaved work. + +Supports single signal or multi-dimensional signal tensor (up to 5-D, shape derived from GlobalTensor). For tensor, returns `true` only if ALL signals meet the condition. + +## Math Interpretation + +Test and return result: + +Single signal: + +$$ \mathrm{result} = (\mathrm{signal} \;\mathtt{cmp}\; \mathrm{cmpValue}) $$ + +Signal tensor (all must satisfy): + +$$ \mathrm{result} = \bigwedge_{d_0, d_1, d_2, d_3, d_4} (\mathrm{signal}_{d_0, d_1, d_2, d_3, d_4} \;\mathtt{cmp}\; \mathrm{cmpValue}) $$ + +where `cmp` ∈ {`EQ`, `NE`, `GT`, `GE`, `LT`, `LE`} + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../../assembly/PTO-AS.md). + +```text +%result = ttest %signal, %cmp_value {cmp = #pto.cmp} : (!pto.memref, i32) -> i1 +%result = ttest %signal_matrix, %cmp_value {cmp = #pto.cmp} : (!pto.memref, i32) -> i1 +``` + +## C++ Intrinsic + +Declared in `include/pto/comm/pto_comm_inst.hpp`: + +```cpp +template +PTO_INST bool TTEST(GlobalSignalData &signalData, int32_t cmpValue, WaitCmp cmp, WaitEvents&... events); +``` + +## Constraints + +- **Type constraints**: + - `GlobalSignalData::DType` must be `int32_t` (32-bit signal). +- **Memory constraints**: + - `signalData` must point to local address (on current NPU). +- **Return value**: + - Returns `true` if condition is satisfied, `false` otherwise. + - For signal tensor, returns `true` only if ALL signals satisfy the condition. +- **Shape semantics**: + - For single signal: Shape is `<1,1,1,1,1>`. + - For signal tensor: Shape determines the multi-dimensional region (up to 5-D) to test. +- **Comparison operators** (WaitCmp): + | Value | Condition | + |-------|-----------| + | `EQ` | `signal == cmpValue` | + | `NE` | `signal != cmpValue` | + | `GT` | `signal > cmpValue` | + | `GE` | `signal >= cmpValue` | + | `LT` | `signal < cmpValue` | + | `LE` | `signal <= cmpValue` | + +## Examples + +### Basic Test + +```cpp +#include + +using namespace pto; + +bool check_ready(__gm__ int32_t* local_signal) { + comm::Signal sig(local_signal); + + // Check if signal == 1 + return comm::TTEST(sig, 1, comm::WaitCmp::EQ); +} +``` + +### Test Signal Matrix + +```cpp +#include + +using namespace pto; + +// Test if all signals from a 4x8 dense grid of workers are ready +bool check_worker_grid(__gm__ int32_t* signal_matrix) { + comm::Signal2D<4, 8> grid(signal_matrix); + + // Returns true only if all 32 signals == 1 + return comm::TTEST(grid, 1, comm::WaitCmp::EQ); +} +``` + +### Polling with Timeout + +```cpp +#include + +using namespace pto; + +bool poll_with_timeout(__gm__ int32_t* local_signal, int max_iterations) { + comm::Signal sig(local_signal); + + for (int i = 0; i < max_iterations; ++i) { + if (comm::TTEST(sig, 1, comm::WaitCmp::EQ)) { + return true; // Signal received + } + // Could do other work here between polls + } + return false; // Timeout +} +``` + +### Progress-Based Polling + +```cpp +#include + +using namespace pto; + +void process_with_progress(__gm__ int32_t* local_counter, int expected_count) { + comm::Signal counter(local_counter); + + while (!comm::TTEST(counter, expected_count, comm::WaitCmp::GE)) { + // Do some useful work while waiting + // ... + } + // All expected signals received +} +``` + +### Compare TWAIT vs TTEST + +```cpp +#include + +using namespace pto; + +void compare_wait_test(__gm__ int32_t* local_signal) { + comm::Signal sig(local_signal); + + // Blocking: spins until signal == 1 + comm::TWAIT(sig, 1, comm::WaitCmp::EQ); + + // Non-blocking: returns immediately with result + bool ready = comm::TTEST(sig, 1, comm::WaitCmp::EQ); +} +``` diff --git a/designs/outerCube/PTOISA/comm/TTEST_zh.md b/designs/outerCube/PTOISA/comm/TTEST_zh.md new file mode 100644 index 00000000..1b71740a --- /dev/null +++ b/designs/outerCube/PTOISA/comm/TTEST_zh.md @@ -0,0 +1,151 @@ +# TTEST + +## 简介 + +非阻塞检测信号是否满足比较条件。满足则返回 `true`，否则返回 `false`。适用于基于轮询的同步（含超时）或与其他工作交错执行的场景。 + +支持单个信号或多维信号 tensor（最高 5 维，形状由 GlobalTensor 决定）。对于 tensor，仅当**所有**信号均满足条件时才返回 `true`。 + +## 数学语义 + +检测并返回结果： + +单个信号： + +$$\mathrm{result} = (\mathrm{signal} \;\mathtt{cmp}\; \mathrm{cmpValue})$$ + +信号 tensor（所有元素均须满足）： + +$$\mathrm{result} = \bigwedge_{d_0, d_1, d_2, d_3, d_4} (\mathrm{signal}_{d_0, d_1, d_2, d_3, d_4} \;\mathtt{cmp}\; \mathrm{cmpValue})$$ + +其中 `cmp` ∈ {`EQ`, `NE`, `GT`, `GE`, `LT`, `LE`} + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS 规范](../../assembly/PTO-AS_zh.md)。 + +```text +%result = ttest %signal, %cmp_value {cmp = #pto.cmp} : (!pto.memref, i32) -> i1 +%result = ttest %signal_matrix, %cmp_value {cmp = #pto.cmp} : (!pto.memref, i32) -> i1 +``` + +## C++ 内建接口 + +声明于 `include/pto/comm/pto_comm_inst.hpp`： + +```cpp +template +PTO_INST bool TTEST(GlobalSignalData &signalData, int32_t cmpValue, WaitCmp cmp, WaitEvents&... events); +``` + +## 约束 + +- **类型约束**： + - `GlobalSignalData::DType` 必须为 `int32_t`（32 位信号）。 +- **内存约束**： + - `signalData` 必须指向本地地址（当前 NPU）。 +- **返回值**： + - 条件满足时返回 `true`，否则返回 `false`。 + - 对于信号 tensor，仅当所有信号均满足条件时才返回 `true`。 +- **形状语义**： + - 单个信号：形状为 `<1,1,1,1,1>`。 + - 信号 tensor：形状决定要检测的多维区域（最高 5 维）。 +- **比较运算符**（WaitCmp）： + | 值 | 条件 | + |-------|--------| + | `EQ` | `signal == cmpValue` | + | `NE` | `signal != cmpValue` | + | `GT` | `signal > cmpValue` | + | `GE` | `signal >= cmpValue` | + | `LT` | `signal < cmpValue` | + | `LE` | `signal <= cmpValue` | + +## 示例 + +### 基础检测 + +```cpp +#include + +using namespace pto; + +bool check_ready(__gm__ int32_t* local_signal) { + comm::Signal sig(local_signal); + + // 检测 signal == 1 + return comm::TTEST(sig, 1, comm::WaitCmp::EQ); +} +``` + +### 检测信号矩阵 + +```cpp +#include + +using namespace pto; + +// 检测 4x8 网格中所有 worker 的信号是否就绪 +bool check_worker_grid(__gm__ int32_t* signal_matrix) { + comm::Signal2D<4, 8> grid(signal_matrix); + + // 仅当所有 32 个信号均为 1 时返回 true + return comm::TTEST(grid, 1, comm::WaitCmp::EQ); +} +``` + +### 带超时的轮询 + +```cpp +#include + +using namespace pto; + +bool poll_with_timeout(__gm__ int32_t* local_signal, int max_iterations) { + comm::Signal sig(local_signal); + + for (int i = 0; i < max_iterations; ++i) { + if (comm::TTEST(sig, 1, comm::WaitCmp::EQ)) { + return true; // 收到信号 + } + // 两次轮询之间可执行其他工作 + } + return false; // 超时 +} +``` + +### 基于进度的轮询 + +```cpp +#include + +using namespace pto; + +void process_with_progress(__gm__ int32_t* local_counter, int expected_count) { + comm::Signal counter(local_counter); + + while (!comm::TTEST(counter, expected_count, comm::WaitCmp::GE)) { + // 等待期间执行其他有用工作 + // ... + } + // 所有预期信号均已收到 +} +``` + +### TWAIT 与 TTEST 对比 + +```cpp +#include + +using namespace pto; + +void compare_wait_test(__gm__ int32_t* local_signal) { + comm::Signal sig(local_signal); + + // 阻塞：自旋直到 signal == 1 + comm::TWAIT(sig, 1, comm::WaitCmp::EQ); + + // 非阻塞：立即返回结果 + bool ready = comm::TTEST(sig, 1, comm::WaitCmp::EQ); +} +``` + diff --git a/designs/outerCube/PTOISA/comm/TWAIT.md b/designs/outerCube/PTOISA/comm/TWAIT.md new file mode 100644 index 00000000..4d9af8d8 --- /dev/null +++ b/designs/outerCube/PTOISA/comm/TWAIT.md @@ -0,0 +1,131 @@ +# TWAIT + +## Introduction + +Blocking wait until signal(s) meet comparison condition. Used in conjunction with `TNOTIFY` for flag-based synchronization. + +Supports single signal or multi-dimensional signal tensor (up to 5-D, shape derived from GlobalTensor). + + +## Math Interpretation + +Wait (spin) until the following condition is satisfied: + +Single signal: + +$$ \mathrm{signal} \;\mathtt{cmp}\; \mathrm{cmpValue} $$ + +Signal tensor (all elements must satisfy): + +$$ \forall d_0, d_1, d_2, d_3, d_4: \mathrm{signal}_{d_0, d_1, d_2, d_3, d_4} \;\mathtt{cmp}\; \mathrm{cmpValue} $$ + +where `cmp` ∈ {`EQ`, `NE`, `GT`, `GE`, `LT`, `LE`} + +## Assembly Syntax + +PTO-AS form: see [PTO-AS Specification](../../assembly/PTO-AS.md). + +```text +twait %signal, %cmp_value {cmp = #pto.cmp} : (!pto.memref, i32) +twait %signal_matrix, %cmp_value {cmp = #pto.cmp} : (!pto.memref, i32) +``` + +## C++ Intrinsic + +Declared in `include/pto/comm/pto_comm_inst.hpp`: + +```cpp +template +PTO_INST void TWAIT(GlobalSignalData &signalData, int32_t cmpValue, WaitCmp cmp, WaitEvents&... events); +``` + +## Constraints + +- **Type constraints**: + - `GlobalSignalData::DType` must be `int32_t` (32-bit signal). +- **Memory constraints**: + - `signalData` must point to local address (on current NPU). +- **Shape semantics**: + - For single signal: Shape is `<1,1,1,1,1>`. + - For signal tensor: Shape determines the multi-dimensional region (up to 5-D) to wait on. All signals in the tensor must satisfy the condition. +- **Comparison operators** (WaitCmp): + | Value | Condition | + |-------|-----------| + | `EQ` | `signal == cmpValue` | + | `NE` | `signal != cmpValue` | + | `GT` | `signal > cmpValue` | + | `GE` | `signal >= cmpValue` | + | `LT` | `signal < cmpValue` | + | `LE` | `signal <= cmpValue` | + +## Examples + +### Wait for Single Signal + +```cpp +#include + +using namespace pto; + +void wait_for_ready(__gm__ int32_t* local_signal) { + comm::Signal sig(local_signal); + + // Wait until signal == 1 + comm::TWAIT(sig, 1, comm::WaitCmp::EQ); +} +``` + +### Wait for Signal Matrix + +```cpp +#include + +using namespace pto; + +// Wait for signals from a 4x8 dense grid of workers +void wait_worker_grid(__gm__ int32_t* signal_matrix) { + comm::Signal2D<4, 8> grid(signal_matrix); + + // Wait until all 32 signals == 1 + comm::TWAIT(grid, 1, comm::WaitCmp::EQ); +} +``` + +### Wait for Counter Threshold + +```cpp +#include + +using namespace pto; + +void wait_for_count(__gm__ int32_t* local_counter, int expected_count) { + comm::Signal counter(local_counter); + + // Wait until counter >= expected_count + comm::TWAIT(counter, expected_count, comm::WaitCmp::GE); +} +``` + +### Producer-Consumer Pattern + +```cpp +#include + +using namespace pto; + +// Producer: notify when data is ready +void producer(__gm__ int32_t* remote_flag) { + // ... produce data ... + + comm::Signal flag(remote_flag); + comm::TNOTIFY(flag, 1, comm::NotifyOp::Set); +} + +// Consumer: wait for data +void consumer(__gm__ int32_t* local_flag) { + comm::Signal flag(local_flag); + comm::TWAIT(flag, 1, comm::WaitCmp::EQ); + + // ... consume data ... +} +``` \ No newline at end of file diff --git a/designs/outerCube/PTOISA/comm/TWAIT_zh.md b/designs/outerCube/PTOISA/comm/TWAIT_zh.md new file mode 100644 index 00000000..0ed76431 --- /dev/null +++ b/designs/outerCube/PTOISA/comm/TWAIT_zh.md @@ -0,0 +1,131 @@ +# TWAIT + +## 简介 + +阻塞等待，直到信号满足比较条件。与 `TNOTIFY` 配合使用，实现基于标志的同步。 + +支持单个信号或多维信号 tensor（最高 5 维，形状由 GlobalTensor 决定）。 + +## 数学语义 + +自旋等待，直到以下条件满足： + +单个信号： + +$$\mathrm{signal} \;\mathtt{cmp}\; \mathrm{cmpValue}$$ + +信号 tensor（所有元素均须满足）： + +$$\forall d_0, d_1, d_2, d_3, d_4: \mathrm{signal}_{d_0, d_1, d_2, d_3, d_4} \;\mathtt{cmp}\; \mathrm{cmpValue}$$ + +其中 `cmp` ∈ {`EQ`, `NE`, `GT`, `GE`, `LT`, `LE`} + +## 汇编语法 + +PTO-AS 形式：参见 [PTO-AS 规范](../../assembly/PTO-AS_zh.md)。 + +```text +twait %signal, %cmp_value {cmp = #pto.cmp} : (!pto.memref, i32) +twait %signal_matrix, %cmp_value {cmp = #pto.cmp} : (!pto.memref, i32) +``` + +## C++ 内建接口 + +声明于 `include/pto/comm/pto_comm_inst.hpp`： + +```cpp +template +PTO_INST void TWAIT(GlobalSignalData &signalData, int32_t cmpValue, WaitCmp cmp, WaitEvents&... events); +``` + +## 约束 + +- **类型约束**： + - `GlobalSignalData::DType` 必须为 `int32_t`（32 位信号）。 +- **内存约束**： + - `signalData` 必须指向本地地址（当前 NPU）。 +- **形状语义**： + - 单个信号：形状为 `<1,1,1,1,1>`。 + - 信号 tensor：形状决定要等待的多维区域（最高 5 维）。tensor 中所有信号必须满足条件。 +- **比较运算符**（WaitCmp）： + | 值 | 条件 | + |-------|--------| + | `EQ` | `signal == cmpValue` | + | `NE` | `signal != cmpValue` | + | `GT` | `signal > cmpValue` | + | `GE` | `signal >= cmpValue` | + | `LT` | `signal < cmpValue` | + | `LE` | `signal <= cmpValue` | + +## 示例 + +### 等待单个信号 + +```cpp +#include + +using namespace pto; + +void wait_for_ready(__gm__ int32_t* local_signal) { + comm::Signal sig(local_signal); + + // 等待 signal == 1 + comm::TWAIT(sig, 1, comm::WaitCmp::EQ); +} +``` + +### 等待信号矩阵 + +```cpp +#include + +using namespace pto; + +// 等待 4x8 网格中所有 worker 的信号就绪 +void wait_worker_grid(__gm__ int32_t* signal_matrix) { + comm::Signal2D<4, 8> grid(signal_matrix); + + // 等待所有 32 个信号均为 1 + comm::TWAIT(grid, 1, comm::WaitCmp::EQ); +} +``` + +### 等待计数器阈值 + +```cpp +#include + +using namespace pto; + +void wait_for_count(__gm__ int32_t* local_counter, int expected_count) { + comm::Signal counter(local_counter); + + // 等待 counter >= expected_count + comm::TWAIT(counter, expected_count, comm::WaitCmp::GE); +} +``` + +### 生产者-消费者模式 + +```cpp +#include + +using namespace pto; + +// 生产者：数据就绪后发送通知 +void producer(__gm__ int32_t* remote_flag) { + // ... 生产数据 ... + + comm::Signal flag(remote_flag); + comm::TNOTIFY(flag, 1, comm::NotifyOp::Set); +} + +// 消费者：等待数据就绪 +void consumer(__gm__ int32_t* local_flag) { + comm::Signal flag(local_flag); + comm::TWAIT(flag, 1, comm::WaitCmp::EQ); + + // ... 消费数据 ... +} +``` + diff --git a/designs/outerCube/PTOISA/conventions.md b/designs/outerCube/PTOISA/conventions.md new file mode 100644 index 00000000..c1d9dd82 --- /dev/null +++ b/designs/outerCube/PTOISA/conventions.md @@ -0,0 +1,41 @@ +# PTO ISA Conventions + +This page defines shared conventions used by the per-instruction ISA reference pages in `docs/isa/` and the corresponding C++ intrinsics in `include/pto/common/pto_instr.hpp`. + +## Notation + +- **Tile**: A fixed-size on-chip tile object (e.g., `pto::Tile<...>`). Many instructions operate on tiles and use the tile’s valid region (`GetValidRow()`, `GetValidCol()`). +- **GM (global memory)**: Off-chip memory accessed via `pto::GlobalTensor<...>`. +- **Scalar / immediate**: A host-side scalar value or an encoded immediate used by `*S` / `*C` variants. + +For the detailed C++ programming model behind these terms, see: + +- Tiles: `docs/coding/Tile.md` +- GlobalTensor: `docs/coding/GlobalTensor.md` +- Scalars and enums: `docs/coding/Scalar.md` + +## Shapes and layouts + +- **Row-major vs. column-major**: Unless stated otherwise, CPU simulator kernels assume row-major tiles. Instructions that support multiple layouts will state supported layouts explicitly. +- **Valid region**: The runtime compute region of a tile, expressed as `(valid_row, valid_col)` and queried via `GetValidRow()` / `GetValidCol()`. + +### Valid Region Semantics + +For instruction pages, when we say “for each element `(i, j)` in the valid region”, we mean: + +- `valid_row = dst.GetValidRow()` and `valid_col = dst.GetValidCol()` unless the instruction explicitly defines a different domain (e.g., some ops may use the source tile’s valid region). +- The math interpretation defines `dst[i, j]` only for indices where `0 <= i < valid_row` and `0 <= j < valid_col`. +- Elements outside the valid region are **unspecified** unless the instruction explicitly states otherwise (do not assume they are zeroed or preserved). + +For multi-operand instructions (e.g., `src0`, `src1`), the docs assume the input tiles are compatible with the iteration domain unless the constraints section states stricter requirements. + +## Types + +- The instruction page lists supported data types (e.g., `fp16`, `fp32`, `int8`, `int16`, `int32`, `uint8`, `uint16`, `uint32`). CPU simulator support may be a subset and is documented in `include/README.md`. + +## Events and synchronization + +- Instructions may require ordering between memory and vector pipelines. When examples show events (e.g., `set_flag(...)` / `wait_flag(...)`), they indicate the required ordering constraints on the target backend. +- `TSYNC` is used for explicit synchronization when needed by a sequence of instructions. + +See `docs/coding/Event.md` for the event model used by PTO Tile Lib. diff --git a/designs/outerCube/PTOISA/conventions_zh.md b/designs/outerCube/PTOISA/conventions_zh.md new file mode 100644 index 00000000..e7a292e4 --- /dev/null +++ b/designs/outerCube/PTOISA/conventions_zh.md @@ -0,0 +1,42 @@ +# PTO ISA 通用约定 + +本页定义 `docs/isa/` 指令参考文档中使用的通用术语与写法，并与 `include/pto/common/pto_instr.hpp` 中的 C++ 内建接口保持一致。 + +## 记号 + +- **Tile**：片上二维操作数对象（例如 `pto::Tile<...>`）。大量指令以 Tile 作为输入/输出，并通过 `GetValidRow()` / `GetValidCol()` 使用 Tile 的有效区域（valid region）。 +- **GM（全局内存）**：通过 `pto::GlobalTensor<...>` 访问的片外内存视图。 +- **标量 / 立即数**：主机侧标量值，或在 `*S` / `*C` 等变体中编码的立即数参数。 + +关于这些对象的 C++ 编程模型（类型、布局、枚举、约束等），可参考： + +- Tile：`docs/coding/Tile_zh.md` +- GlobalTensor：`docs/coding/GlobalTensor_zh.md` +- 标量与枚举：`docs/coding/Scalar_zh.md` + +## 形状与布局 + +- **行主序 / 列主序**：除非指令页明确声明支持多种布局，否则示例与参考实现默认假设为行主序 Tile。支持多布局的指令会在约束小节中列出具体要求。 +- **有效区域（valid region）**：Tile 运行时计算域，通常写作 `(valid_row, valid_col)`，并通过 `GetValidRow()` / `GetValidCol()` 查询。 + +### 有效区域语义 + +在指令页中，当我们写“对有效区域内的每个元素 `(i, j)`”，含义为： + +- 除非指令显式定义不同的迭代域，否则默认使用 `valid_row = dst.GetValidRow()`、`valid_col = dst.GetValidCol()`。 +- 数学语义仅对 `0 <= i < valid_row` 且 `0 <= j < valid_col` 的 `dst[i, j]` 做出定义。 +- 有效区域之外元素的值为**未指定**，除非指令页明确说明（不要假设一定清零或保持不变）。 + +对多输入指令（例如 `src0`、`src1`），除非约束小节有更严格的要求，文档默认输入 Tile 与迭代域在形状/有效区域上是兼容的。 + +## 数据类型 + +每条指令页会列出支持的数据类型（例如 `fp16`、`fp32`、`int8`、`int16`、`int32`、`uint8`、`uint16`、`uint32` 等）。 +不同后端/目标对数据类型与布局支持可能不同，具体以对应实现与编译期检查为准。 + +## 事件与同步 + +- 某些指令序列需要建立内存与向量流水线之间的顺序关系。示例中出现的事件（例如 `set_flag(...)` / `wait_flag(...)`）用于表达后端需要满足的顺序约束。 +- 在需要显式同步的场景，使用 `TSYNC` 建立阶段间的顺序关系。 + +事件模型可参考：`docs/coding/Event_zh.md`。 diff --git a/designs/outerCube/vector4k.md b/designs/outerCube/vector4k.md new file mode 100644 index 00000000..6b3fb228 --- /dev/null +++ b/designs/outerCube/vector4k.md @@ -0,0 +1,962 @@ +# VEC-4K: Vector Unit for 4 KB PTO Tiles (PTO ISA Subset) + +## 1. Purpose and Scope + +This document specifies a **vector execution unit (VEC-4K)** that implements a **software-visible subset** of the PTO Tile Lib ISA ([`PTOISA/README.md`](PTOISA/README.md)): elementwise tile–tile ops, tile–scalar ops, axis reduce/expand, and selected **complex** instructions (e.g. **TMRGSORT**, **TSORT32**, **TGATHER**, **TCI**). The unit is paired with a **tile register file (TRegFile)** holding **4 KB** tiles. + +**Non-goals (this document):** matrix multiply (**TMATMUL** / **TGEMV** family), global-memory **TLOAD/TSTORE** (treated as separate DMA-like paths), and **comm** collective ISA—only the on-tile vector datapath is analyzed here. + +--- + +## 2. Tile and Format Model + +### 2.1 Storage Invariant + +Each logical tile occupies exactly **4096 bytes** in the TRegFile. The logical shape is **R × C** with: + +- **R** and **C** are powers of two (implementation may also require R·C to match the element count implied by the format). +- **Row-major** layout: address increases along columns within a row, then along rows. + +Let **E** be the **storage bytes per logical element** in the chosen encoding: + +| Logical format | Typical storage `E` (bytes / element) | Elements per 4 KB tile (N = 4096 / E) | +|----------------|----------------------------------------|----------------------------------------| +| FP32 | 4 | 1024 | +| FP16 / BF16 | 2 | 2048 | +| FP8 (E4M3/E5M2)| 1 | 4096 | +| MXFP4 / HiFP4 | ½ (packed nibble pair in byte) | 8192 | + +For **sub-byte** types, hardware views memory as **byte lanes**; unpack/pack stages map nibbles to wider internal operands (e.g. FP16/FP32) for ALU operations, then pack back on write. + +**Valid shape examples** (illustrative): + +- FP32: 32×32, 16×64, 64×16, … (R·C = 1024). +- FP16: 64×32, 32×64, 128×16, … (R·C = 2048). +- FP8: 64×64, 128×32, … (R·C = 4096). +- FP4: 128×64, 256×32, … (R·C = 8192). + +### 2.2 Metadata + +Each issued vector op carries **format**, **R**, **C**, and **opcode**. Microcode (or a small FSM per op) derives: + +- `strip_count = 4096 / 512 = 8` **physical strips** per tile (fixed by §3). +- `elem_per_strip = 512 / E` (must be integer; hardware asserts this from format). + +--- + +## 3. TRegFile Interface and Striping + +### 3.1 Ports (Design Assumption) + +| Direction | Width | Count | Aggregate | +|-----------|-------|-------|-----------| +| Read | 512 B | 2 | **1024 B/cycle** | +| Write | 512 B | 2 | **1024 B/cycle** | + +Ports may target **independent tile bases** (e.g. `src0` and `src1`) or **the same tile** at different offsets (double-pump one operand into two buffers). + +When VEC is attached to [`tregfile4k.md`](tregfile4k.md), a concrete dual-read binding is **Rd0 → R0** (**Port A**, phase **0**) and **Rd1 → R4** (**Port B**, phase **4**) so **same `tile_idx`** yields strip pair **`(G,e)`** and **`(G+4,e)`** at epoch phase **e** (**§4.4**). + +**Read semantics:** TRegFile read ports present **only** full **512 B** bank-group strips per [`tregfile4k.md`](tregfile4k.md) — **no gather** (no sub-strip element indexing inside the RF). **`TCOL*`** therefore **replays** the same `reg_idx` over **multiple cycles** / **epochs** as needed; **column extraction** is done in **VEC** from **strip buffers A/B** after each read (**§5.3.2**, **§4.4 Example H**). + +### 3.2 Physical Strip + +A **strip** is a contiguous **512-byte** chunk at offset `s·512` for `s ∈ {0,…,7}` within the 4 KB tile. This matches one port transaction per strip. + +**Minimum streaming latency (full tile), ignoring bank conflicts:** + +- **Unary** (both read ports read **the same logical tile** at consecutive strip offsets): **2 strips/cycle** × **512 B** = **1024 B/cycle** → **4096 / 1024 = 4 cycles** to read one full tile. +- **Binary elementwise** (typical: **Rd0 → src0** strip `s`, **Rd1 → src1** strip `s`): **1 strip per operand per cycle** → **8 strips/operand** → **8 cycles** to ingest **both** full tiles. Software/hardware can **reuse** a buffered operand (e.g. **op reuse buffer**) to hide half of the reads on back-to-back dependent ops. + +The micro-architecture below assumes **8 strip indices** per 4 KB tile and schedules **cross-strip** work where reductions, expands, or gathers require it. + +### 3.3 On-Chip Buffers + +- **A strip buffer** and **B strip buffer** (512 B each, **Rd0/Rd1**), optionally **double-buffered** to overlap TRegFile read with compute; **§4.1** **crossbar** ingests **1024 B/cycle** from the two ports. +- **Acc** — **256 × 32 b × 2** ping-pong (**`N_run = 512`**, **§4.1**, **§9.3.2**); optional **strip / staging** for multi-pass sorts; **§4.3** schedules **Rd0/Rd1** vs **`fiber_id`** / **Acc** updates. +- **Scalar broadcast register** (tile–scalar immediates or a single-element tile). + +--- + +## 4. Vector Datapath Overview + +### 4.1 Block Diagram (dataflow level) + +**Reference micro-architecture** (counts for **scheduling** / **§5.3.2** **`N_tree`**): + +```text + ┌────────────────────────────────────────────────────────────────────┐ + │ TRegFile (4 KB tiles) │ + │ Rd0 (512 B) Rd1 (512 B) │ + └──────────────────┬──────────────────────────┬──────────────────────┘ + │ │ + └──────────┬───────────────┘ + │ 1024 B aggregate / cycle (2×512 B) + ▼ + ┌────────────────────────────────────────────────────────────────────┐ + │ Instruction opcode + shape (format, R, C, …) ──► CONTROL │ + └────────────────────────────────────────────────────────────────────┘ + │ + ▼ + ┌─────────────────────────────────────┐ + │ CROSSBAR │ + │ 1024 B in → distribute to compute │ + └─────────────────┬───────────────────┘ + │ + ┌─────────────────▼───────────────────────────────────────────┐ + │ (A) ALIGN / UNPACK / PERMUTE (control-selected) │ + │ IN: 1024 B / cycle from crossbar │ + │ OUT: 128 slices (slice i width = W_prep,i bits) │ + └─────────────────┬───────────────────────────────────────────┘ + │ 128 parallel slice buses + ▼ + ┌─────────────────▼───────────────────────────────────────────┐ + │ (B) N_group = 128 INDEPENDENT COMPUTE GROUPS i = 0…127 │ + │ ┌─────────────────────────────────────────────────────┐ │ + │ │ Group i (representative): │ │ + │ │ IN: W_prep,i (from A) │ │ + │ │ ┌──────────────────┐ ┌────────────────────┐ │ │ + │ │ │ Elementwise ALU │ ───► │ Reduction tree │ │ │ + │ │ │ OUT: W_ALU,i │ │ OUT: W_tree,i │ │ │ + │ │ └──────────────────┘ └─────────┬──────────┘ │ │ + │ │ Constraint: W_ALU,i ≥ W_tree,i (allowed; tree │ │ + │ │ narrows / retires partials; ALU may be wide SIMD) │ │ + │ │ Elementwise bypass: ALU OUT can skip deep tree │ │ + │ │ (W_tree,i = W_ALU,i, or tree depth 0) when opcode │ │ + │ │ does not need cross-lane combine on that group. │ │ + │ └─────────────────────────────────────────────────────┘ │ + │ Typical: W_tree,i = 32 b (FP32-shaped partial → Acc) │ + └─────────────────┬───────────────────────────────────────────┘ + │ 128 × W_tree,i (subset to Acc per beat) + ▼ + ┌─────────────────────────────────────┐ + │ ACCUMULATOR (DFF, ping-pong) │ + │ 256 × 32 b × 2 halves ≈ 2048 B │ + │ per slot: DFF + optional combine │ + │ • RMW: adder (new ⊕ feedback DFF) │ + │ • BYPASS: new → DFF (no combine) │ + │ N_run = 512 logical slots (§9.3.2) │ + └─────────────────┬───────────────────┘ + │ mux: one 256-word half + ▼ + ┌─────────────────────────────────────┐ + │ Pack (wide → FP8/FP4 / narrow dst) │ + └─────────────────┬───────────────────┘ + │ + ┌───────────▼───────────┐ + │ Wr0 (512 B) Wr1 (512 B) │ + │ = 1024 B retire / phase │ + └───────────────────────────┘ +``` + +**Flow:** **Rd0+Rd1** → **crossbar** (**1024 B/cycle**). **Control** drives **crossbar** routing, **(A)** unpack/permute **masks**, **(B)** per-group **ALU** opcode and **tree** depth (or **bypass**), and **Acc** addressing. **(A)** outputs **128** parallel **slices** of width **`W_prep,i`** (depends on **format** / **opcode** / **implementation**). **(B)** is **`N_group = 128`** identical **structures**: each slice feeds an **elementwise ALU** whose output has width **`W_ALU,i`**, then a **reduction tree** that may **narrow** to **`W_tree,i`**. **Allow `W_ALU,i ≥ W_tree,i`** (wide **SIMD** **ALU** **before** a **smaller** **tree** **footprint**). **Typical** partial to **Acc:** **`W_tree,i = 32` b** (FP32-shaped). **Pure elementwise** may use **tree depth 0** or **bypass** so **`W_tree,i = W_ALU,i`** for the path toward **Pack**. **Accumulator:** besides **RMW** (**partial ⊕** **stored** via **adder** **+** **DFF** **feedback**), **control** may **bypass** the **combine** **adder** and **write** **tree/ALU** **data** **straight** **into** the **Acc** **DFF** (**load** / **overwrite** / **non-accumulating** **retire**). **Acc** ping-pong, **Wr** half-select, **`fiber_id` / `ρ` / Acc waves:** **§5.3.2**, **§9.3.2**; **§4.3** calendars. + +### 4.2 “Lanes” vs “Strips” + +- **SIMD lane**: one parallel datapath processing **one logical element** after unpack (width depends on op; internal **FP32** is a reasonable unified width for expensive ops). +- **Strip**: 512 B of **spatially contiguous** storage; SIMD width = `elem_per_strip`. +- **Cross-lane** (within strip): reductions along a dimension that fits in one strip (partial row/col). +- **Cross-strip**: **control-programmed** **crossbar** + **trees** (**§4.1**) combine strip `s` and `s′` contributions, or **multi-cycle accumulation** into **Acc** ping-pong (**§9.3.2**) / **staging**. + +### 4.3 Fiber ID and strip read calendar + +**`fiber_id`** is the **logical index along the axis** that **reduce** and **expand/broadcast** class ops treat as a **fiber**—one **output slot** per fiber after a reduce, or one **scalar source** per fiber when expanding along that axis: + +| Opcode family | `fiber_id` | Range | +|---------------|------------|--------| +| **`TROW*`** (row reduce) | row index **`r`** | `0 … R−1` | +| **`TCOL*`** (column reduce) | column index **`c`** | `0 … C−1` | +| **`TROWEXPAND*`** | **`r`** (splat target row) | `0 … R−1` | +| **`TCOLEXPAND*`** | **`c`** (splat target column) | `0 … C−1` | + +**Elementwise** tile–tile ops do **not** use a single global **`fiber_id`**; they are scheduled **strip-by-strip** only. **Gather/sort/merge** use their own index streams; where they write **per-row/col** state, that state can still be keyed like **`fiber_id`** for buffer allocation. + +**From strip bytes to `(r, c)` and `fiber_id`:** For strip index **`s ∈ {0,…,7}`** and lane/byte offset inside the **512 B** chunk, **row-major** layout fixes a linear element order; decode **`(r, c)`** from **`(R, C, E)`**. Then **`fiber_id = r`** or **`c`** according to the opcode’s **axis**. **Control** drives the **crossbar** (**§4.1**) so **unpack**, **permutation**, and **tree/ALU** inputs see the correct segment for each **`fiber_id`** touched in that strip. + +**Strip read calendar:** A **calendar** is the **cycle-by-cycle** schedule that binds **what arrives on Rd0/Rd1** to **what the datapath does**—in particular, **which operands feed each lane** and **which `fiber_id`(s)** touch **Acc** or **per-fiber `v` buffers** that cycle. + +- **Port row (per cycle `t`):** specifies **`s(t)`** (which **512 B** chunk), **which logical tile** each port reads (**`src0`**, **`src1`**, narrow **`v`** tile, scalar tile, **ping-pong scratch** for merges/sorts, or **idle**), and optional **second-pass** phases. **`TCOL*`** does **not** use a **transpose scratchpad** — only **normal** `reg_idx` tiles in **row-major** strip order (**§5.3.2**). TRegFile ports **cannot gather** (**§3.1**); **`TCOL*`** may **repeat** the **same** `reg_idx` over **multiple TRegFile epochs** when **`#W = max(⌈C/N_acc⌉, ⌈C/(N_tree·f)⌉, ⌈C/N_run⌉) > 1`** (**§5.3.2**, **§4.4 Example H**; **`#W`** **reduces** to **two** **terms** **when** **`N_acc ≤ N_run`**). +- **Operand sources (`TROW*` reduce):** **Tile elements** arrive strip-serially from **read ports**; after **unpack → within-strip tree → cross-strip combine**, the reducer performs **RMW** on **Acc** at **`fiber_id = r`**. Physical slot **`ρ`** is **`fiber_id` remapped** into **`[0, N_run)`** for the current **Acc wave** (§9.3.2: **`bank = ρ mod 8`**, **`word = ρ >> 3`**, **0…63**). One strip can touch **many** distinct **`fiber_id`**s when **`row_B < 512`** or **`col_B < 512`** (many thin fibers per strip). +- **Operand sources (`TCOL*` reduce):** Ports still deliver **full rows** inside each **512 B** strip; **VEC** **selects** **`(r,c)`** for the scheduled **column band** from **strip buffers** (**no RF gather**). **Acc[`c`]** **+=** partial sums across strip-beats and, if needed, across **re-scans** of the tile. +- **Operand sources (expand):** **`v[fiber_id]`** is supplied from a **narrow per-fiber vector** streamed on a read port, from **Acc / staging** after an in-place reduce, or from a **small buffer** filled in a **prefetch** phase; **`src`** elements still arrive **strip-major** like §5.1. The calendar interleaves **`v`** strip reads with **`src`** strips so each cycle’s SIMD sees a consistent **`(fiber_id, lane)`** map. + +**Templates:** Opcode decode picks a **calendar template** from **`(format, R, C, opcode)`**. The §9 metrics **`rS`, `rW`, `rK`, …** / **`cS`, `cW`, …** fix how many **within-strip** rounds and how **8-strip** walks align with **cross-strip** merge. The **47** distinct scheduling recipes in **§9.5.1** are **calendar families** over the same datapath, not separate RTL blocks. **Epoch-aligned worked tables** vs [`tregfile4k.md`](tregfile4k.md): **§4.4**. + +**Illustrative calendar row** (one cycle of a row-reduce pass; details vary by shape): + +| Field | Content | +|-------|---------| +| **`t`** | Cycle index in the micro-sequence | +| **Rd0 / Rd1** | e.g. **`src` strip `s`**, second operand or **`idle`** | +| **`s`** | Current **strip index** `0…7` (or remapped pass) | +| **Lane → `(r,c)`** | From **§2.1** row-major map | +| **`fiber_id`s updated** | Subset of **`r`** appearing in this strip’s segment | +| **Acc** | **RMW** at decoded **bank/word** for each retiring partial | + +### 4.4 Epoch-aligned fiber calendars vs `tregfile4k.md` (four worked examples) + +Full **(format, shape)** enumeration would need **76** row-axis templates alone (§9); this subsection fixes **VEC ↔ TRegFile-4K** timing and shows **eight** representative **`fiber_id`** calendars (**Examples A–H**; **E–H** emphasize **FP8** and **MXFP4**). See [`tregfile4k.md`](tregfile4k.md): global **`e = cy[2:0]`** (phase within an **8-cycle** epoch); read port **Rp** presents bank-group **`G = (p + e) mod 8`** (**512 B** = one **strip** **Gs**). + +**Port binding for the tables:** + +| Logical name | TRegFile read port | Phase `p` | Strip delivered at phase `e` | +|--------------|-------------------|-----------|--------------------------------| +| **Port A** | **R0** | 0 | **`G_A = e`** | +| **Port B** | **R4** | 4 | **`G_B = (4 + e) mod 8`** | + +**Epoch start:** **`t = 0`** is an **epoch boundary** (**e = 0**): the **`reg_idx`** for each port is **active** for the next 8 cycles (pending→active promotion, `tregfile4k.md` §4). + +**Dual-port same `tile_idx` on A+B:** in cycles **`t = 0…3`** (**e = 0…3**), the pair **`(G_A, G_B)`** visits **`(0,4), (1,5), (2,6), (3,7)`** — every strip **Gs ∈ {0,…,7}** appears **exactly once** as **one** of the two 512 B beats. Cycles **`t = 4…7`** repeat the **same** strip schedule (second lap with the **same** latched tile on both ports); microcode **suppresses duplicate Acc** or reuses beats for **another operand** / **write path**. **Benefit:** **4 cycles** to see all **8** strips **once** with **two** 512 B reads/cycle vs **8 cycles** with **Port A only** (Port B **idle**). + +**Row-major element index** in a strip: byte offset **`512·Gs + δ`** with **`δ`** increasing along **columns** within the row segment; **`fiber_id = r`** for **`TROW*`** labels which **row**’s **C** elements are being reduced or expanded. + +**Column shorthand in tables:** + +| Column | Meaning | +|--------|---------| +| **`t`**, **`e`** | Core cycle from op **epoch start**; **`e = t mod 8`**. | +| **Port A / B** | **`T@Gs`** = tile **`reg_idx` T** and physical strip **Gs** (512 B). **`—`** = port unused this cycle. | +| **Fibers (this beat)** | **`fiber_id`** values whose **row data** (reduce) or **row op** (expand) is anchored on **that port’s** strip in this cycle. | +| **First elem @ port** | Logical **element** at **byte 0** of that port’s 512 B chunk for the listed fiber (start of the row segment in that strip). | +| **`#elem`** | **Logical elements along the row** (along **C**) taken from **that port** this cycle toward **`TROW*`** / expand **`src`**. | +| **Reduce / expand** | **`TROWSUM`:** cross-lane tree over **`#elem`** → **one** partial per **`fiber_id = r`** → **Acc RMW**. **`TCOL*`** (**§5.3.2**): **`fiber_id = c`**; **strip replay** + **VEC column mux** + **`Acc[c]`** **RMW**; **`P_beat = min(N_tree, N_acc)`**; **`#W = max(⌈C/N_acc⌉, ⌈C/(N_tree·f)⌉, ⌈C/N_run⌉)`** (**`f`**, **`N_run`**, **§5.3.2**; **`#W`** ≡ **`#waves`** **when** **`⌈C/N_run⌉ ≤ ⌈C/N_acc⌉`**) — **§4.4 Example H**. **`TROWEXPANDADD`:** for each **`fiber_id`**, combine **`#elem`** **`src`** lanes with **`v[fiber_id]`** (from **`v`** tile or latch). | + +*End-to-end latency* may add **tree pipeline stages** after the last ingest cycle; tables list **operand arrival** and **per-fiber arithmetic scope** per cycle. + +--- + +#### Example A — `TROWSUM`, **FP32**, **8×128** (`C = 128`, **one row = one strip**) + +**Geometry:** **`row_B = 512 B`**, strip **Gs** holds **exactly row `r = Gs`**. **Dual-port** same **`src`** tile on **A+B** gives **two rows/cycle** for **`t = 0…3`**; **`t = 4…7`** are duplicate strip delivery (masked). + +| `t` | `e` | Port A | Port B | Fibers (A) | First elem @ A | `#elem` | Fibers (B) | First elem @ B | `#elem` | Reduce note | +|----:|----:|--------|--------|------------|----------------|--------:|------------|----------------|--------:|-------------| +| 0 | 0 | `src@G0` | `src@G4` | `r=0` | elem `(0,0)` | 128 | `r=4` | elem `(4,0)` | 128 | 2× `TROWSUM` lane-tree → **Acc** `r=0`, `r=4` | +| 1 | 1 | `src@G1` | `src@G5` | `r=1` | `(1,0)` | 128 | `r=5` | `(5,0)` | 128 | **Acc** `r=1`, `r=5` | +| 2 | 2 | `src@G2` | `src@G6` | `r=2` | `(2,0)` | 128 | `r=6` | `(6,0)` | 128 | **Acc** `r=2`, `r=6` | +| 3 | 3 | `src@G3` | `src@G7` | `r=3` | `(3,0)` | 128 | `r=7` | `(7,0)` | 128 | **Acc** `r=3`, `r=7` | + +**Unique ingest complete at `t = 3`** (8 fibers, each **128** elements). **Single-port (A only):** stretch to **`t = 0…7`**, one row/cycle, **no** dual-port gain. + +--- + +#### Example B — `TROWSUM`, **FP32**, **32×32** (`C = 32`, **4 rows / strip**) + +**Geometry:** **`row_B = 128 B`**, **`512 / 128 = 4`** rows per strip. **Single Port A** is enough (dual port does **not** shorten **unique** row coverage unless compute is strip-bound and overlapped differently); **Port B idle**. + +| `t` | `e` | Port A | Port B | Fibers (A) | First elem @ A (each fiber) | `#elem` each | Reduce note | +|----:|----:|--------|--------|------------|-----------------------------|----------------|-------------| +| 0 | 0 | `src@G0` | — | `0,1,2,3` | `(0,0)`, `(1,0)`, `(2,0)`, `(3,0)` | 32 | 4× lane-tree (`K=32`) → **Acc** `r=0…3` | +| 1 | 1 | `src@G1` | — | `4,5,6,7` | `(4,0)`…`(7,0)` | 32 | **Acc** `r=4…7` | +| 2 | 2 | `src@G2` | — | `8,9,10,11` | … | 32 | **Acc** | +| 3 | 3 | `src@G3` | — | `12…15` | … | 32 | **Acc** | +| 4 | 4 | `src@G4` | — | `16…19` | … | 32 | **Acc** | +| 5 | 5 | `src@G5` | — | `20…23` | … | 32 | **Acc** | +| 6 | 6 | `src@G6` | — | `24…27` | … | 32 | **Acc** | +| 7 | 7 | `src@G7` | — | `28…31` | … | 32 | **Acc** | + +**32** fibers, each **`#elem = C = 32`** from **Port A** only; **8 cycles** = one epoch, **one** `reg_idx` on **R0**. + +--- + +#### Example C — `TROWEXPANDADD`, **FP32**, **8×128** (`v[r]` + `src`) + +**`v` tile:** **8** row scalars as **FP32** = **32 B** at **byte offset 0** of strip **G0** (tile **`v`**; remaining bytes **don’t-care**). + +**Why prefetch `v`:** If **`v@G0`** were on **Port B** while **`src`** streams on **Port A** only, **dual-port** cannot also deliver **`src@G4`** in the **same** cycle. **High bandwidth schedule:** (1) **Pre-epoch** or **`t_pre`:** **Port B** reads **`v@G0`** once; latch **`v[0]…v[7]`** (bytes **0–3**, **4–7**, …, **28–31**). (2) **`t = 0…3`:** **Port A** and **Port B** both carry **`src`** with **same** `reg_idx` as Example **A** — **two rows/cycle**. + +| `t` | `e` | Port A | Port B | Fibers (`src`) | First elem @ A | First elem @ B | `#elem` / fiber | **`v[fiber_id]`** | Expand | +|----:|----:|--------|--------|----------------|----------------|----------------|-----------------|-------------------|--------| +| 0 | 0 | `src@G0` | `src@G4` | `r=0`, `r=4` | `(0,0)` | `(4,0)` | 128 | **latched** **`v[0]`**, **`v[4]`** | **128** lanes/fiber: **`src` + v** | +| 1 | 1 | `src@G1` | `src@G5` | `r=1`, `r=5` | `(1,0)` | `(5,0)` | 128 | **latched** **`v[1]`**, **`v[5]`** | … | +| 2 | 2 | `src@G2` | `src@G6` | `r=2`, `r=6` | … | … | 128 | **latched** **`v[2]`**, **`v[6]`** | … | +| 3 | 3 | `src@G3` | `src@G7` | `r=3`, `r=7` | … | … | 128 | **latched** **`v[3]`**, **`v[7]`** | … | + +**`t_pre` (one beat, e.g. previous epoch):** **Port B** = **`v@G0`**, **Port A** = **—** or next **`src`** prefetch; **first element of `v[0]`** = **byte 0** of **B**’s 512 B chunk. + +--- + +#### Example D — `TROWSUM`, **HiFP4**, **256×32** (`C = 32`, **`E = ½`**, **32 rows / strip**) + +**Geometry:** **`row_B = 16 B`** = **32** logical elements/row; **`512 / 16 = 32`** distinct **`fiber_id`** values per strip. **Dual-port** same **`src`**: **`t = 0…3`** covers **256** rows (all fibers) with **64** partial trees/cycle (32 fibers × 2 ports). + +| `t` | `e` | Port A | Port B | Fiber IDs (A) | First elem @ A | `#elem` | Fiber IDs (B) | First elem @ B | `#elem` | Reduce note | +|----:|----:|--------|--------|---------------|----------------|--------:|---------------|----------------|--------:|-------------| +| 0 | 0 | `src@G0` | `src@G4` | `r=0…31` | row `r` starts at byte **`16r`** mod strip | 32 each | `r=128…159` | byte **`16(r−128)`** in **G4** strip | 32 each | **64** lane-trees → **64** **Acc** RMW (**watch bank** = `r mod 8`) | +| 1 | 1 | `src@G1` | `src@G5` | `32…63` | … | 32 | `160…191` | … | 32 | **64** **Acc** | +| 2 | 2 | `src@G2` | `src@G6` | `64…95` | … | 32 | `192…223` | … | 32 | **64** **Acc** | +| 3 | 3 | `src@G3` | `src@G7` | `96…127` | … | 32 | `224…255` | … | 32 | **64** **Acc** | + +**`t = 4…7`:** duplicate **`src`** strips (suppress **Acc** idempotent re-reduce) unless **`reg_idx`** advances to a **second** tile / phase. + +--- + +#### Example E — `TROWSUM`, **FP8** (`E = 1`), **64×64** (`C = 64`, **8 rows / strip**) + +**Geometry:** **`row_B = 64 B`** = **64** **`UINT8`/FP8** elements along the row; **`512 / 64 = 8`** distinct **`fiber_id`** values per strip. **Dual-port** same **`src`**: **`t = 0…3`** ingests all **64** rows (**16** partial trees/cycle). + +| `t` | `e` | Port A | Port B | Fiber IDs (A) | First elem @ A | `#elem` | Fiber IDs (B) | First elem @ B | `#elem` | Reduce note | +|----:|----:|--------|--------|---------------|----------------|--------:|---------------|----------------|--------:|-------------| +| 0 | 0 | `src@G0` | `src@G4` | `r=0…7` | row `r` at byte **`64r`** in **G0** | 64 | `r=32…39` | byte **`64(r−32)`** in **G4** *(base row **32**)* | 64 | **16** lane-trees → **Acc** (unpack **FP8→FP32** internal) | +| 1 | 1 | `src@G1` | `src@G5` | `8…15` | … | 64 | `40…47` | … | 64 | **16** **Acc** | +| 2 | 2 | `src@G2` | `src@G6` | `16…23` | … | 64 | `48…55` | … | 64 | **16** **Acc** | +| 3 | 3 | `src@G3` | `src@G7` | `24…31` | … | 64 | `56…63` | … | 64 | **16** **Acc** | + +--- + +#### Example F — `TROWSUM`, **FP8** (`E = 1`), **16×256** (`C = 256`, **2 rows / strip**) + +**Geometry:** **`row_B = 256 B`**; **`512 / 256 = 2`** rows per strip. **Dual-port** same **`src`**: **4** cycles × **4** fibers/cycle = **16** rows. + +| `t` | `e` | Port A | Port B | Fibers (A) | First elem @ A | `#elem` | Fibers (B) | First elem @ B | `#elem` | Reduce note | +|----:|----:|--------|--------|------------|----------------|--------:|-----------|----------------|--------:|-------------| +| 0 | 0 | `src@G0` | `src@G4` | `r=0`, `1` | `(0,0)`, `(1,0)` | 256 each | `r=8`, `9` | strip **G4** row **8** at byte **0**, row **9** at byte **256** | 256 | **4** trees (`K=256`, **`D_lane = 8`**) | +| 1 | 1 | `src@G1` | `src@G5` | `2`, `3` | … | 256 | `10`, `11` | … | 256 | **4** **Acc** | +| 2 | 2 | `src@G2` | `src@G6` | `4`, `5` | … | 256 | `12`, `13` | … | 256 | **4** **Acc** | +| 3 | 3 | `src@G3` | `src@G7` | `6`, `7` | … | 256 | `14`, `15` | … | 256 | **4** **Acc** | + +*(Row **8** in **G4:** byte offset **`512·4 = 2048`** = **`8 × 256`**.)* + +--- + +#### Example G — `TROWSUM`, **MXFP4** (`E = ½`, packed nibble), **512×16** (`C = 16`, **64 rows / strip**) + +**Geometry:** **`row_B = 8 B`** = **16** logical FP4 elements/row; **`512 / 8 = 64`** **`fiber_id`**s per strip. **Dual-port** same **`src`**: **`t = 0…3`** covers **512** rows (**128** lane-trees/cycle). **Unpack** maps **nibble lanes** to **wide** compare/add operands before **Acc**. + +| `t` | `e` | Port A | Port B | Fiber IDs (A) | First elem @ A | `#elem` | Fiber IDs (B) | First elem @ B | `#elem` | Reduce note | +|----:|----:|--------|--------|---------------|----------------|--------:|---------------|----------------|--------:|-------------| +| 0 | 0 | `src@G0` | `src@G4` | `r=0…63` | row `r` at byte **`8r`** in **G0** | 16 | `r=256…319` | byte **`8(r−256)`** in **G4** | 16 | **128** trees → **128** **Acc** RMW | +| 1 | 1 | `src@G1` | `src@G5` | `64…127` | … | 16 | `320…383` | … | 16 | **128** **Acc** | +| 2 | 2 | `src@G2` | `src@G6` | `128…191` | … | 16 | `384…447` | … | 16 | **128** **Acc** | +| 3 | 3 | `src@G3` | `src@G7` | `192…255` | … | 16 | `448…511` | … | 16 | **128** **Acc** | + +--- + +#### Example H — `TCOLSUM`, **MXFP4** (`E = ½`), **32×256** (`R = 32`, **`C = 256`**, **native row-major**) + +**TRegFile:** Read ports emit **only** full **512 B** strips (**[`tregfile4k.md`](tregfile4k.md)**); **there is no gather** inside the tile RF. **`TCOLSUM`** cannot request “column **`c`** only” from the file — it must **accept whole strips** on **Port A / Port B**, then **select** the needed **`(r,c)`** in **VEC** (strip buffers → unpack → **column mux** / shifter network). + +**Policy:** **No transpose scratchpad** (**§5.3.2**). Operand remains **one** `reg_idx`, **§2.1** row-major. **Acc[`c`]**: **read–modify–write** associative **add** so partials from each strip-beat **accumulate** until all **R = 32** row contributions for column **`c`** are seen. + +**Hardware parallelism (§5.3.2):** Let **`N_tree`** = parallel **adder / reduce trees** per beat; **`N_acc`** = parallel **Acc** **RMW** slots per cycle (**`N_acc ≤ N_run`**, **§9.3.2**); **`f`** = **effective `Acc[c]` commits per tree per full tile scan** (one **dual-ingest** pass over **all** strips — includes **sub-cycles** / **pipeline**). **Same-cycle** combine+retire is capped by **`P_beat = min(N_tree, N_acc)`**. + +**Wave count (both limits):** + +**`#W = max(⌈C / N_acc⌉, ⌈C / (N_tree · f)⌉, ⌈C / N_run⌉)`** (**`#W`** **tile-epoch** **count**; **synonym** **`#waves`** **below** **when** **`N_acc ≤ N_run`** **⇒** **`⌈C/N_run⌉ ≤ ⌈C/N_acc⌉`**) + +- **`#waves_acc = ⌈C / N_acc⌉`**: **Acc-band** partitioning (**≤ `N_acc`** columns **finished** per **wave** if **trees** keep up). +- **`#waves_tree = ⌈C / (N_tree · f)⌉`**: when **`N_tree ≪ N_acc`**, **tree throughput** may require **more** **full scans** than **`#waves_acc`** predicts. +- **`#waves_Nrun = ⌈C / N_run⌉`**: **DFF** **capacity** (**§5.3.2**); **redundant** **vs** **`#waves_acc`** **when** **`N_acc ≤ N_run`**. + +When **`N_acc > N_tree`**, **trees** are **time-multiplexed** over **sub-cycles**; **`f`** must be **measured** from **RTL**/**micro-arch** (Example: **`S = 4`** strip-pair beats × **`f_micro`** commits per beat per tree). + +**Illustrative numbers:** **`C = 256`**, **`N_acc = 64`**, **`N_run = 512`** → **`#waves_acc = 4`**, **`⌈C/N_run⌉ = 1`**. With **`N_tree = 8`**, **`f = 8`** (e.g. **8** **`Acc[c]`** commits per tree over one **4-beat** scan × **2** **micro** rounds): **`N_tree · f = 64`**, **`#waves_tree = 4`**, **`#W = max(4, 4, 1) = 4`**. With **`N_tree = 4`**, **`f = 8`**: **`N_tree · f = 32`**, **`#waves_tree = 8`**, **`#W = max(4, 8, 1) = 8`** — **tree**-limited; **strip calendar** is unchanged, but **microcode** runs **more** **tile** **epochs** and may **shrink** the **column band** per wave below **`N_acc`**. + +**Acc-limited schedule (`#W = ⌈C / N_acc⌉`):** **`c_base = N_acc · k`** as in the tables below. **`N_tree = 32`**, **`N_acc = 64`** may still need **two** **tree** **phases** per **`t`** — **micro-cycles** expand **`f`**; re-check **`#waves_tree`**. + +**Geometry:** **`row_B = 128 B`** (**256** FP4 elements/row); **4** rows per **512 B** strip. **Dual** read (**R0+R4**, **§3.1**): **`t = 0…3`** (**`e = 0…3`**) delivers **unique** strip pairs **`(0,4)…(3,7)`** and visits **all 32** rows **once per full scan**. Cycles **`t = 4…7`** of the **same** TRegFile **epoch** repeat the **same** strips (second lap with identical `reg_idx`); **disable Acc updates** on **`t = 4…7`** unless **overlapped** with another **column band** (implementation choice). + +**If `N_acc ≥ C`:** **one** wave (**one** scan, **`t = 0…3`**) suffices for all columns. + +**Per-strip-beat (one wave):** From **A**/**B** buffers, **column mux** pulls **`(r,c)`** for **`c`** in the active band only; **8** row samples per **`c`** per **`t`** (4 rows × 2 ports) → **`Acc[c] +=`** partial (after **`K = 8`** interim reduce via **`N_tree`** lanes). After **`t = 3`** for that wave, each **`c`** in the band has **32** row terms accumulated → **done** for **`TCOLSUM`** (modulo tree **pipeline**). + +**Strip calendar (identical each wave; `c_base = N_acc · k`):** + +| `t` | `e` | Port A | Port B | Rows in A / B | **`fiber_id` band** | Per-**`c`** row samples this `t` | **Acc** | +|----:|----:|--------|--------|---------------|---------------------|----------------------------------|---------| +| 0 | 0 | `src@G0` | `src@G4` | **0–3** / **16–19** | **`c ∈ [c_base, c_base + N_acc − 1]`** | **8** | **`Acc[c] +=`** partial from **8** **`(r,c)`** (mux from **A/B**) | +| 1 | 1 | `src@G1` | `src@G5` | **4–7** / **20–23** | same band | **8** | **+=** … | +| 2 | 2 | `src@G2` | `src@G6` | **8–11** / **24–27** | same band | **8** | **+=** … | +| 3 | 3 | `src@G3` | `src@G7` | **12–15** / **28–31** | same band | **8** | **32** terms integrated per **`c`** in band | + +**`(r,c)` byte** in a strip with base row **`r₀`**: **`(r − r₀)·row_B + ⌊c·E⌋`** plus **nibble** select (**`E = ½`**). **Multi-epoch summary** (**Acc-limited** **`#W = 4`**, i.e. **`#waves_tree ≤ #waves_acc`**; **`N_acc = 64`**, **`N_run = 512`**): + +| Wave `k` | Tile read policy | Active columns | Strip beats used | +|----------|------------------|----------------|------------------| +| 0 | Same `reg_idx`, epoch **E0** | **`c = 0…63`** | **`t = 0…3`** as above | +| 1 | **Re-read** same tile, epoch **E1** | **`c = 64…127`** | repeat calendar | +| 2 | epoch **E2** | **`c = 128…191`** | repeat | +| 3 | epoch **E3** | **`c = 192…255`** | repeat | + +If **`#waves_tree > #waves_acc`**, add **waves** **`k = 4 … #W − 1`** with **overlapping** or **narrower** **column** **bands** — **implementation**-specific. + +**Cycle lower bound (illustrative):** **`#W × 4`** strip-pair cycles (**`#W`** from **§5.3.2** **`max(⌈C/N_acc⌉, ⌈C/(N_tree·f)⌉, ⌈C/N_run⌉)`**), **plus** **epoch** turnarounds — **implementation-dependent**. **Single-port A only** doubles strip cycles per scan (**`t = 0…7`** unique). + +**§9 `c*`** metrics still bound **tree / strip** complexity; they **exclude** **transpose scratch**, **`#W`** **tile replays**, **`f`**, **`N_run`**, **TRegFile** **non-gather** replay — add explicitly in schedules (**§5.3.2**). + +--- + +## 5. Instruction Categories and Cycle Sketches + +The following uses **R**/**C** notation, **S = 8** strips, and **read_pair** = one cycle with both 512 B read ports used. **Write_pair** = both write ports used (same or different tiles depending on retire policy). + +### 5.1 Elementwise (Tile–Tile) + +**Representative:** `TADD`, `TMUL`, `TAND`, `TCMP`, `TCVT` (unary ops such as `TABS`/`TRELU` omit one read port per strip). + +**Dataflow (non-pipelined sketch):** + +1. For each strip index `s = 0…7`: `read_pair` loads `src0[s]` and `src1[s]` → unpack → SIMD op → pack into `dst[s]` staging. +2. Retire `dst[s]` with `write_pair` (same cycle as next strip’s read if the pipeline supports **read–compute–write** overlap). + +**Latency:** **8 cycles** minimum to **read** both operand tiles strip-by-strip; with **pipelining** (overlap read `s+1` with write `s−1`), end-to-end often **~10–12 cycles** for a full `dst` tile (implementation-dependent buffering). + +**Cross-lane:** **none** for pure elementwise; SIMD lanes are independent within the strip. + +**Special:** `TCVT` may widen/narrow; internal path uses **wider SIMD** or **two-pass** if pack/unpack asymmetry exceeds one cycle. + +```mermaid +flowchart LR + subgraph per_strip [Per strip s] + R0[Read src0 512B] --> U0[Unpack] + R1[Read src1 512B] --> U1[Unpack] + U0 --> ALU[Elementwise ALU] + U1 --> ALU + ALU --> P[Pack] + P --> W[Write dst 512B] + end +``` + +--- + +### 5.2 Tile–Scalar / Tile–Immediate + +**Representative:** `TADDS`, `TMULS`, `TCMPS`, `TEXPANDS`, `TADDSC`. + +**Scalar path:** + +- Immediate or **single-element tile** loaded once into **scalar broadcast reg** (optional **1-cycle** read of a dedicated scalar slot). +- Each strip: SIMD op **lane_i = f(tile[s]_i, scalar)**. + +**Cycles:** same order of magnitude as §5.1; **one fewer** long-latency operand read if scalar is in a control register. + +**Cross-lane:** none (unless scalar differs per row/col via side table—then becomes expand-like). + +--- + +### 5.3 Axis Reduce + +**Row-reduce examples:** `TROWSUM`, `TROWMAX`, `TROWARGMAX` (reduce across **columns** within each row). +**Column-reduce examples:** `TCOLSUM`, `TCOLMAX`, `TCOLARGMAX`. + +**Key geometric fact:** a **512 B strip** spans a **contiguous run** of row-major storage; for **large C**, one row may span **multiple strips**; for **small C**, one strip may hold **multiple partial rows**. The control FSM computes `(row, col)` range per strip from `(R, C, E)`. + +**Scheduling:** Reduce passes are driven by a **strip read calendar** keyed by **`fiber_id = r`** or **`c`** (**§4.3**): each cycle’s **Rd0/Rd1** transactions determine **operand sources**; partials retire to **Acc** on the matching **`fiber_id`**. **`TCOL*`** obeys **§5.3.2** (**no transpose scratchpad**; TRegFile **no gather** — **strip replay** + **VEC column select** + **Acc RMW**). + +#### 5.3.1 Row-wise reduce (e.g. `TROWSUM`) + +For each **row r**, compute `acc[r] = reduce_{c} M[r,c]`. + +**Phase A – partial reduce within strip:** + +- For strips that contain **multiple columns of the same row segment**, use **horizontal SIMD tree** within the strip (cross-lane inside SIMD). + +**Phase B – cross-strip combine for rows spanning strips:** + +- Strips contributing to the same row feed a **segmented reduction network** or write **partial sums** to **Acc** (logical index `r`, physical slot **`ρ`** when **`N_run < R`**, **§9.3.2**), then **second pass** reads back when row complete. **Logical** depth (**rAccB** / **rStgUB**) is in **§9.3.1**; **legal shapes** in **§9.7**; **running** silicon = **`N_run`** DFF entries. + +**Cycle sketch (conceptual):** + +| Phase | Action | +|-------|--------| +| 1 | For each strip `s` in 0…7: read tile strip, compute **strip-partial** per affected row segment → **Acc** RMW (atomic add/max/…) | +| 2 | If all columns of row seen, **finalize** row result to narrow format | +| 3 | For `TROWEXPAND`-style output of scalar-per-row, stream writes; for true reduce producing **R×1** or packed vector tile, **write compact tile** over multiple cycles | + +**`TROWARGMAX` / `TROWARGMIN`:** each strip produces **(value, col_index)** pairs; cross-strip compare selects winner; **cross-lane compare tree** + **index mux**. + +```text + Strip0 partial ──┐ + Strip1 partial ──┼──▶ Per-row combine (max/sum) ──▶ Row result tile + ... │ + Strip7 partial ──┘ + ▲ + └── updates keyed by row id (cross-strip) +``` + +#### 5.3.2 Column-wise reduce (e.g. `TCOLSUM`, `TCOLMAX`) + +**Architectural rule (VEC-4K):** **`TCOL*`** **must** be implemented on the **operand tile’s native row-major** layout as seen through **normal TRegFile** `reg_idx` / **512 B strip** reads. **No transpose scratchpad tile** — software and microcode **shall not** rely on materializing a **C×R** row-major **copy** of the operand in a separate tile **for the sole purpose of column reduction**. + +**Parallelism — `N_tree` vs `N_acc` (hardware):** + +| Symbol | Meaning | +|--------|---------| +| **`N_tree`** | Parallel **adder / reduce** (or **elementwise**) **paths** after the **crossbar** (**§4.1**). **Reference implementation:** **`N_tree = 128`**. Scheduling **examples** below may use **smaller** **illustrative** values. | +| **`N_acc`** | **Distinct** **`Acc[·]`** **RMW** (or **commit**) slots **in the same cycle** — limited by **`N_tree`**, **adder feedback** **ports**, and **`N_run`** (**§9.3.2**): **`N_acc ≤ N_run`** (**512**); **one ping-pong half** holds **256** slots (**1024 B**). | + +**Coupling:** On a **single** beat, **at most `min(N_tree, N_acc)`** columns can **both** **combine** fresh partials **and** **retire** to **Acc** in the **same** cycle if **tree output** must **pair** **1:1** with an **accumulator write**. + +**When `N_acc > N_tree`:** **Trees** are the **scarce** resource; microcode may **time-multiplex** **`N_tree`** trees across **sub-cycles** while **keeping `N_acc`** **accumulators** **live** (pipeline registers + **Acc**). Once **pipelined**, the **schedule** can still **advance up to `N_acc` column accumulations per cycle** by **feeding** accumulators from **staggered** tree outputs. + +**Accumulator-centric wave count** (column **bands** sized by **Acc** retire slots): + +**`#waves_acc = ⌈C / N_acc⌉`** + +(i.e. **`num_col / num_acc`**, rounded up): each **wave** is one **complete** **row-major** scan of the operand tile, updating a **disjoint band** of **at most `N_acc`** columns’ **`Acc[c]`** toward the final **R**-way reduce. + +**Tree-limited wave count (`N_tree ≪ N_acc`):** Define **`f`** as the **effective number of distinct `Acc[c]` commits** each **single** **adder tree** can **sustain per full operand tile scan** (one **dual-port** ingest of **all** strips, e.g. **`t = 0…3`** in Example H), **after** **pipelining** and **sub-cycle** multiplex (**`f`** counts **tree→Acc** **throughput** over the **whole** scan — product of **commits per strip-beat** × **number of beats**, **bypass**, and **stage depth**). If **trees** cannot **produce** partials fast enough to **match** **`#waves_acc`**, **more** **tile replays** are needed: + +**`#waves_tree = ⌈C / (N_tree · f)⌉`** + +**DFF capacity wave count (`N_run`):** + +**`#waves_Nrun = ⌈C / N_run⌉`** + +**Combined (conservative, full-tile replays for `TCOL*`):** + +**`#W = max(⌈C / N_acc⌉, ⌈C / (N_tree · f)⌉, ⌈C / N_run⌉)`** + +Treat **`#W`** as the **tile-scan / epoch** **count** **lower bound** for **correct** **`TCOL*`** (**`#waves`** is an **alias** when **unambiguous**). **`K_outer`** (**§8**, **write staging**) counts **outer** **fiber-offset** **campaigns**; it **need not** equal **`#W`** — **avoid** **double-counting** **tile** **replays** **unless** the **micro-op** **nest** (**outer** × **inner** strip loop) is **specified**. + +**Redundancy:** **`N_acc ≤ N_run`** (**§9.3.2**) ⇒ **`C / N_acc ≥ C / N_run`** ⇒ **`⌈C / N_acc⌉ ≥ ⌈C / N_run⌉`** for **`C > 0`**, so **`#waves_Nrun`** **never exceeds** **`#waves_acc`** **in that regime** — the **third** **`max`** **term** is **for** **generality** (alternate **schedules**, **tooling**, or **future** **caps**) and **matches** **`#waves_acc`** **when** **`N_acc = N_run`**. + +When **`N_tree · f ≥ N_acc`**, **`#waves_tree ≤ #waves_acc`** and **`#W = max(⌈C / N_acc⌉, ⌈C / N_run⌉) = ⌈C / N_acc⌉`** (still **Acc-band** **long pole** if **`N_acc ≤ N_run`**). + +**Fiber-capacity rounds (`N_run`):** if **more output fibers** are **live** than **`N_run`** DFF slots allow in one **in-core** pass, or an **extreme `(R,C)`** forces **narrow bands** per **outer** iteration, **opcode decode** expands **one** architectural **`TROW*` / `TCOL*`** into **`K_outer` hardware loops** (nested **outside** the **strip** walk). Each **outer** iteration carries a **fiber base / offset** (`c_base`, `r_base`, …) so **only** **`≤ N_run`** **logical** fibers map to **physical `ρ`** in **Acc** at a time; the **inner** loop is still the **usual** **row-major** strip calendar (**§4.3**). **Correctness** is preserved by **trading latency for capacity**. + +**Write-side staging across outer loops:** **Wr0 / Wr1** (and **Pack** ahead of them) may hold **wide staging registers** — **per-strip** or **per-output-slice** — where **partial result tiles** or **completed fiber bands** from **earlier** outer iterations **accumulate** or **merge** until the **full** **`R`×`C`** (or **per-fiber vector**) output is **complete**. For **associative** reduces (**sum** / **max** / **min**), **merge** order must match **ISA numerics** (e.g. **sum** associativity vs **rounding**); **arg** ops need **value∥index** staging consistent across rounds (**§9.3.2**). This is **invisible** at **single-instruction retire** if the **VEC** does **not** commit **`dst`** until the **last** outer loop. + +**When `N_acc ≤ N_tree`:** **Acc** is the **bottleneck** for **parallel column retires**; **`#waves_acc`** **still** applies; **`min(N_tree, N_acc) = N_acc`** caps **simultaneous** combine+retire per beat unless **pipelining** exposes extra **tree** throughput. **Also** evaluate **`#waves_tree`** if **`f`** is **small**. + +**Design shorthand:** **`P_beat = min(N_tree, N_acc)`** for **strict** same-cycle **tree→Acc** pairing; **tile-replay** uses **`#W`** above — see **§4.4 Example H**. + +**`TROW*` mirror (row-axis output fibers, `fiber_id = r`):** same **symbols** **`N_tree`**, **`N_acc`**, **`N_run`**, **`f`** (**`f`** = **effective `Acc[r]` commits per tree per full operand scan** on the **row-reduce** calendar). **Replace `C` → `R`:** + +**`#W_trow = max(⌈R / N_acc⌉, ⌈R / (N_tree · f)⌉, ⌈R / N_run⌉)`** + +**§5.3.1** **Phase B** **strip** **walk** **replays** apply. **`⌈R / N_run⌉`** is **redundant** **vs** **`⌈R / N_acc⌉`** **when** **`N_acc ≤ N_run`** — **same** **as** **`TCOL*`**. + +For each **column c**, reduce across **rows** (**R** elements). In **row-major** storage, a column is **not** one contiguous byte range unless **`C = 1`**. **Implementation:** TRegFile delivers **only** full **512 B** strips (**§3.1** — **no gather**). Hardware **re-reads** the operand tile’s strips in **Gs** order (possibly **many TRegFile epochs** with the **same** `reg_idx`); after each read, **strip buffers A/B** hold **row-contiguous** data; **unpack** + **column mux** (VEC-side, **not** in the RF) extracts **`(r,c)`** for the **column band** scheduled that beat; **Acc[`c`] read–modify–write** accumulates partial sums until all **R** rows are covered. If **`N_acc < C`**, **repeat** the **full strip walk** for the next column band (**§4.4 Example H**). **Blocked partials** and **multi-cycle** calendars (**§4.3**) apply. + +**Metrics parity (§9):** Closed-form **`c*`** symbols match the **mathematical** **`TROW*`-on-`C×R`** substitution (**transpose-equivalent indices only**). That **algebra** does **not** imply a **physical** transpose buffer — it sizes **trees**, **`cS`**, **`cW`**, and **SRAM**; **wall-clock** must add **strip replay** and **`#W = max(⌈C / N_acc⌉, ⌈C / (N_tree · f)⌉, ⌈C / N_run⌉)`** **full-tile** **epochs** (**`f`**, **`N_run`** per **§5.3.2** / **§9.3.2**). + +**Cross-strip / cross-lane:** still heavy when **`col_B`** is small (many columns’ samples packed per strip); see **`c*`** in **§9.3** and **§9.6** (§9.7 lists **shapes** only). + +--- + +### 5.4 Axis Expand / Broadcast + +**Representative:** `TROWEXPAND*`, `TCOLEXPAND*`. + +**Scheduling:** Expands use the same **`fiber_id`** convention (**§4.3**): **`r`** or **`c`** selects **`v[fiber_id]`**; the **calendar** interleaves reads of the **narrow `v` tile** (or **Acc**-backed **`v`**) with **`src`** strips so each **512 B** write sees correct **splat** metadata per lane. + +**Row expand** (broadcast scalar along row): after computing or loading **per-row scalar** `v[r]`, for each strip determine row segments and **broadcast** `v[r]` across lane positions (SIMD **splat**). + +**Column expand:** same **no-transpose-scratch** rule as **`TCOL*`** (**§5.3.2**): **row-major** strip walk + **multi-pass splat** / **lane scatter** with **column address generation**; **no** **`C×R`** scratch tile **only** for expand. + +**Cycles:** often **1× read** of narrow **per-row/col vector tile** + **1× read** of `src` + **streamed write** of `dst` → similar to **8–16** cycles depending on whether `src` and `v` fit strip schedule without extra passes. + +```mermaid +flowchart TB + subgraph row_expand [TROWEXPANDADD sketch] + V[Per-row scalars v[r] in buffer] + S[src tile strips] + V --> SPLAT[Splat per row segment] + S --> ADD[Add/mul/max...] + SPLAT --> ADD + ADD --> D[dst strips] + end +``` + +--- + +### 5.5 Complex Instructions + +#### 5.5.1 `TSORT32` + +Spec: sort **each 32-element block** of `src` with paired indices from `idx`. + +- **Within-strip:** if `32·E ≤ 512 B`, multiple blocks per strip; process blocks **in parallel SIMD sort networks** (bitonic / odd-even) of depth O(log² 32) comparators **pipelined**. +- **Cross-block:** independent per block → **minimal cross-strip** except when a 32-block spans strip boundary → **microcode** stitches **tail/head** in a **staging register**. + +**Cycles:** **many** (tens), dominated by comparator stages × number of blocks `N/32`. + +#### 5.5.2 `TMRGSORT` (merge sort of multiple sorted lists) + +Typically **multi-list merge** with **k-way** comparator tree: + +1. **Load** list headers / pointers (implementation-defined in ISA). +2. **Stream** strips from each list into **merge front buffers** (read ports time-multiplexed across lists). +3. **Repeat:** compare **k** front elements, pick winner, push to **output strip**, refill from corresponding list. +4. **Write** output strips via write ports. + +**Cross-lane / cross-strip:** **heavy**; merge **global** across lists, not SIMD-embarrassingly parallel. Expect **O(4096 / 1024) × (merge depth)** plus **compare tree** cycles—**hundreds** of cycles acceptable for a “complex” op. + +```text + List0 strips ──▶ ┐ + List1 strips ──▶ ├──▶ k-way merge tree ──▶ out strip buffer ──▶ Wr ports + ... │ + List(k-1) ────▶ ┘ +``` + +#### 5.5.3 `TGATHER` / `TGATHERB` / `TSCATTER` + +- **Index-driven** access: per element, **addr = base + f(index)`**; within VEC-4K, **on-tile** gather means **cross-strip byte mux** driven by **index SIMD** (indices may come from second tile). +- Realistic schedule: **batch** indices into **coalesced** groups that fall into **same or adjacent strips** to limit mux fanout. + +**Cycles:** **large variance**; worst case approaches **per-element** serialization if indices are random. + +#### 5.5.4 `TCI`, `TTRI`, `TPART*` + +- **`TCI`:** **strip-parallel** index generation `base + stride` → **no cross-lane** dependency beyond broadcast of parameters. +- **`TTRI`:** row/col counters compared to generate mask; **cross-lane** for diagonal boundary within strip only. +- **`TPART*`:** valid-region mask intersects elementwise regions; same as §5.1 with **predicate gating**. + +#### 5.5.5 `TQUANT` / `TDEQUANT` + +Often **two-phase**: compute **scale/exp** per tile or per row (reduce), then **elementwise** scale. Combines **§5.3** + **§5.1**. + +--- + +## 6. Cross-Lane and Cross-Strip Summary + +| Category | Cross-lane (within 512 B strip) | Cross-strip (among 8 strips) | +|----------|----------------------------------|------------------------------| +| Elementwise tile–tile | Independent lanes | None (strip order arbitrary) | +| Tile–scalar | Independent | None | +| Row reduce | Horizontal tree for row segment in strip | Combine partials for rows spanning strips | +| Column reduce | **Strip read** → **VEC column mux** from row data in buffer (RF **no gather**) | **Heavy** strip **replay** / **`Acc` RMW** / multi-epoch (**no transpose scratch**) | +| Row expand | Splat scalar across row segment | Repeat/broadcast metadata per strip | +| Column expand | Partial splat (**column-major intent**, row-major storage) | **Heavy** multi-pass (**no transpose scratch**) | +| `TSORT32` | Sort network per 32-block | Block spanning strip boundary | +| `TMRGSORT` | Per-element compare in tree | **Global** merge across streams | +| `TGATHER` | Mux selected elements | Arbitrary strip sources | + +--- + +## 7. Datapath Diagram — Row Reduce with Cross-Strip Combine + +**Read sequencing** follows a **strip calendar** (**§4.3**). **§4.1** **dataflow:** **Rd0+Rd1** → **crossbar** (**1024 B**) → **(A) align/unpack/permute** → **128 slices `W_prep,i`** → **(B) 128×(ALU `W_ALU,i` → tree `W_tree,i`)** → **Acc** ping-pong → **half-select** → **Wr0+Wr1** (**`W_ALU,i` may exceed `W_tree,i`**). + +```mermaid +flowchart TB + subgraph rf [TRegFile] + RD0[Rd0 512B] + RD1[Rd1 512B] + end + subgraph ctl [Control] + C[Opcode + shape] + end + subgraph xb [Crossbar] + XB[1024 B in] + end + subgraph modA ["(A) Align unpack permute"] + A["IN 1024 B OUT 128 x W_prep,i"] + end + subgraph modB ["(B) 128 groups N_group"] + G["Per i: slice W_prep,i to ALU to tree W_ALU,i then W_tree,i 32b typical"] + end + subgraph acc [Acc ping-pong] + ACCMEM["256x32bx2 RMW or bypass to DFF"] + end + subgraph out [Retire] + PACK[Pack] + WR[Wr0 Wr1 512B] + end + RD0 --> XB + RD1 --> XB + C --> XB + C --> A + C --> G + C --> ACCMEM + XB --> A + A --> G + G -->|W_tree to Acc rho| ACCMEM + ACCMEM -->|256 words| PACK --> WR +``` + +--- + +## 8. Implementation Notes + +1. **Opcode decode** produces **control** for the **§4.1** **crossbar**, **(A)** **align/unpack/permute** (**per-slice** **`W_prep,i`**), **(B)** **128** **groups** (**ALU** **`W_ALU,i`**, **tree** **`W_tree,i`**, **`W_ALU,i ≥ W_tree,i`** **allowed**), **Acc** ping-pong **addresses**, **per-slot** **RMW** **vs** **bypass-to-DFF** (**§9.3.2**), **Wr half-select**, and a **strip read calendar** (**§4.3**): per-cycle **Rd0/Rd1** targets, **strip index** phase, **`fiber_id`** / **Acc** side effects. Parameters include strip loop count, **`TCOL*`** **wave** / **`N_acc`** / **`N_tree`** / **`f`** (§5.3.2), **`N_run`** / **`ρ` remap**, **`K_outer`**, **write-side staging**, **splat** / merge **k**, §9 **`r*`** / **`c*`** template id (**47** families). **`TCOL*`** **replays** over **`#W = max(⌈C/N_acc⌉, ⌈C/(N_tree·f)⌉, ⌈C/N_run⌉)`** when **`#W > 1`**; **no transpose-scratch**; **no RF gather** (**§3.1**). +2. **Determinism:** PTO ops are expected to be **deterministic** at the tile level; multi-cycle internal scheduling is **invisible** if the instruction **retires atomically** from the programmer’s view (barriers via **`TSYNC`** as needed). +3. **Resource conflicts:** with only **two** read ports, **TMRGSORT** and **column-reduce** should **stall** other TRegFile clients or use **dedicated tiles** for **algorithmic** ping-pong (e.g. sort lists) — **not** for a **transpose scratchpad** forbidden by **§5.3.2**. +4. **Numerics:** FP4/FP8 ops may specify **internal FP16/FP32** evaluation; document **rounding** per `TCVT` / ISA rules. + +--- + +## 9. Legal `(format, R×C)` enumeration and axis-reduce complexity (`TROW*` / `TCOL*`) + +This section **enumerates every** combination of **logical format** and **tile shape** from §2.1 and, for each, gives **paired** metrics for **row-axis** reductions (`TROWSUM`, `TROWMAX`, `TROWARGMAX`, …) and **column-axis** reductions (`TCOLSUM`, `TCOLMAX`, `TCOLARGMAX`, …). It then explains how a **single reconfigurable reduction tree** morphs with those parameters, and counts how many distinct **control shapes** appear in the table. + +### 9.1 Enumeration rules + +- Tile storage: **4096 bytes**, row-major, **R** and **C** powers of two. +- **N = R·C = 4096 / E** with **E** bytes per logical element: + - **FP32:** `E = 4`, `N = 1024`, **11** shapes. + - **FP16** and **BF16:** `E = 2`, `N = 2048`, **12** shapes each (**24** table rows). + - **FP8:** `E = 1`, `N = 4096`, **13** shapes. + - **MXFP4** and **HiFP4:** `E = ½`, `N = 8192`, **14** shapes each (**28** table rows). + +**Master table rows:** **76**. **Unique `(E, R, C)` geometries:** **50**. + +`elem_per_strip = 512/E` (for `E = ½`, **1024** elements per 512 B). + +### 9.2 Row-axis metrics (`TROW*`) + +For each **row** fiber, reduce **C** elements. **Bytes per row** `row_B = 4096/R`. + +| Sym | Definition | +|-----|------------| +| **rS** | Strips per row `= ⌈row_B / 512⌉`. | +| **rK** | Elements in one cross-lane segment: `C` if `rS = 1`, else `512/E`. | +| **rDl** | Cross-lane depth `= max(0, ⌈log₂ rK⌉)`. | +| **rDc** | Cross-strip depth `= max(0, ⌈log₂ rS⌉)`. | +| **rW** | Per-strip serial work: `rDl` if `row_B ≥ 512`, else `(512/row_B)·rDl`. | +| **rLB** | `4 + rDl + rDc` (optimistic; §9.4). | +| **rUB** | `4 + 8·rW + R·rDc` (conservative serial tree; §9.4). | +| **rAccB** / **rStgUB** | Partial state (bytes): §9.3.1 — **`4·R`** logical running; **`4·R·rS`** staged upper bound; **physical running** **`N_run`** (**§9.3.2**). | + +### 9.3 Column-axis metrics (`TCOL*`) + +For each **column** fiber, reduce **R** elements. **Logical bytes per column** (if packed contiguously) `col_B = 4096/C = R·E`. + +**Formal substitution (metrics only — not a scratch layout):** Algebraically, `TCOL*` on **R×C** matches `TROW*` on a **fictitious C×R** row-major tile with the **same** **4096 B** element multiset. **VEC-4K does not allocate a physical C×R transpose scratchpad** for **`TCOL*`** (**§5.3.2**); the **`c*`** formulas still size **trees**, strip pressure, and **SRAM** for **strip replay + VEC column mux** (**TRegFile has no gather**, **§3.1**). The symbols are the **same** as §9.2 with **`(R,C) → (C,R)`** and **`C` ↔ `R`**: + +| Sym | Definition | +|-----|------------| +| **cS** | `⌈col_B / 512⌉` (= strips per column fiber in the **substitution-equivalent** striping model). | +| **cK** | `R` if `cS = 1`, else `512/E`. | +| **cDl** | `max(0, ⌈log₂ cK⌉)`. | +| **cDc** | `max(0, ⌈log₂ cS⌉)`. | +| **cW** | `cDl` if `col_B ≥ 512`, else `(512/col_B)·cDl`. | +| **cLB** | `4 + cDl + cDc`. | +| **cUB** | `4 + 8·cW + C·cDc` (note **`C`** column outputs, not `R`). | +| **cAccB** / **cStgUB** | Partial state (bytes): §9.3.1 — **`4·C`** logical running; **`4·C·cS`** staged upper bound; **physical running** **`N_run`** (**§9.3.2**). | + +**Row-major hardware path:** scheduling uses the **same numeric** `(cS, cK, cDl, cDc, cW)` for **strip-sequential reads**, **partial state**, **VEC column extraction**, and **cross-strip merge** on the **operand tile**; **cLB/cUB** **exclude** **TTRANS** / **transpose-scratch** (**§5.3.2**) and **exclude** **`#W = max(⌈C/N_acc⌉, ⌈C/(N_tree·f)⌉, ⌈C/N_run⌉)`** **tile replays**, **`f`**, and **`N_run`** (**§5.3.2**). **Multi-epoch** **`reg_idx`** replay (**§4.4 Example H**) may dominate wall-clock. + +### 9.3.1 Partial accumulator state (`TROW*` / `TCOL*`) + +Strips that contribute to the **same** row (or column) either **update a running partial** or **buffer strip-level partials** until the cross-strip merge completes. **§9.3.1** gives **logical** byte formulas; **§9.7** lists **(format, R×C)** rows only; **§9.3.2** caps **live** running entries in silicon. + +**Assumption A — associative reduce (max / min / sum):** each output fiber keeps **one** **FP32-shaped** running partial (widen narrow formats in the reducer). Index **r** for rows, **c** for columns. + +| Symbol | Formula | Meaning | +|--------|---------|---------| +| **rAccB** | **`4·R`** | **Logical** per-row state (bytes): `R` rows × **4 B** (FP32 partial / compare operand width). **Physical** running file holds **`min(R, N_run)`** slots at a time when **`N_run < R`** (**wave** remap, **§9.3.2**). | +| **cAccB** | **`4·C`** | **Logical** per-column state (bytes). **Physical** **`min(C, N_run)`** at a time when **`N_run < C`**. | + +**Implementation cap — `N_run = 512`:** the **VEC-4K** running-partial file is **512 × 32b DFF** (**2048 B**), **16×** smaller than the **§2.1** worst-case **8192** logical fibers (**8192 / 512 = 16**). When **`R > N_run`** or **`C > N_run`**, **decode** drives **`K_outer > 1` hardware loops** (**§5.3.2**): each **outer** step maps **at most `N_run`** fibers to **`ρ`** and runs the **full** inner **strip** schedule (or a **defined** subset); **completed** bands **retire** through **Pack → Wr0/Wr1**, often into **write-path staging registers** that **hold** or **combine** **partial `dst`** **slices** until **all** offsets are **done** — **functionally** equivalent to an unbounded Acc file, at **higher** cycle cost. + +**Same mechanism for `N_acc` / tree limits:** **outer loops** are **not** only for **`N_run`**; **banded `TCOL*`** (**`#W`** in **§5.3.2**) is the **same** pattern — **time** for **capacity**. **Write staging** is optional when each **wave** writes **disjoint** **`dst`** fibers directly; it is **required** when **outer** rounds must **merge** into **shared** output **strip** words or **one** **fiber** is **finished** only after **multiple** passes. + +**Assumption B — staged strip partials (upper bound):** microarchitecture retains **up to one FP32 partial per strip slot per fiber** before the **`⌈log₂ S⌉`** cross-strip tree drains them (worst case over all fibers simultaneously). + +| Symbol | Formula | Meaning | +|--------|---------|---------| +| **rStgUB** | **`4·R·rS`** | **Row-axis staging upper bound** (bytes). Never exceeds **32 768 B (32 KiB)** for any legal `(E,R,C)` in §2.1 (same peak as **rAccB** when `rS = 1`, or **4·1024·8** when `R = 1`, `rS = 8`, etc.). | +| **cStgUB** | **`4·C·cS`** | **Column-axis** analogue; peak **32 KiB**. | + +**`TROWARGMAX` / `TROWARGMIN` / `TCOLARG*`:** plan for **value + index** per fiber (e.g. **8 B** aligned entries). A simple scaling rule: **≈ `2 × rAccB`** / **`2 × cAccB`** (and **×2** on **rStgUB** / **cStgUB** if indices are kept per staged partial). + +**Dual-axis overlap:** a single physical **Acc** file can be **time-multiplexed** between row and column passes; **simultaneous** row+column reductions need enough **live** slots for both (**≤ `N_run`** each if **serialized** bands) **or** **serialized** op issue. **Transpose scratch** is **not** used to fold axes (**§5.3.2**). + +#### 9.3.2 Accumulator organization (ping-pong DFF, `N_run = 512`, §4.1) + +The **running partial** store matches **§4.1**: **two** **ping-pong** **halves** of **256 × 32 bit** each (**1024 B** / **half**, **2048 B** total). **Each** **slot** is a **DFF** **word** with **two** **write** **modes** selected by **control**: + +- **RMW accumulate:** **new** **partial** from **(B)** **feeds** an **adder**; **second** **operand** is **feedback** from the **same** **slot’s** **DFF** **output**; **sum** (or **max/min** **compare**) **writes** **back** **to** **that** **DFF** (**associative** **reduce** **path**). +- **Bypass combine (write-through):** **new** **data** **from** **(B)** **is** **muxed** **directly** **into** the **DFF**, **skipping** the **accumulate** **adder** — **overwrite** / **initialise** / **move** **style** **updates** **without** **old** **+** **new** **arithmetic**. + +**One** **half** **accepts** **writes** **while** **control** may **select** the **other** **half** for **Pack → Wr0+Wr1** (**512 B + 512 B** = **1024 B** = **256** words **per** **retire** **phase**). + +**Logical indexing:** **`ρ ∈ [0, N_run)`** with **`N_run = 512`**; e.g. **`ρ = h·256 + σ`** with **half** **`h ∈ {0,1}`** and **`σ ∈ [0,255]`**. **`fiber_id`** (**§4.3**) **remaps** to **`ρ`** across **Acc waves** when **`R` or `C > 512`**. + +**Capacity:** + +- **`N_run = 512`** **FP32-shaped** partials **across** **both** **halves**. **`N_acc ≤ N_run`** (**§5.3.2**); **at most 256** **distinct** **RMW** targets **per** **half** **per** **cycle** if **all** **writes** **land** **in** **one** **active** **accumulation** **half**. +- **Logical** **`max(R)`** / **`max(C)`** over §2.1 remains **8192** — **rAccB** / **cAccB** (**§9.3.1**, **§9.6**) are **algorithmic**. + +**Conflict decode (optional 8-way view):** **`bank_id = ρ mod 8`**, **`word = ρ >> 3`** still **useful** for **port** **scheduling** (same as **32** **words**/bank × **8** **banks** **within** **each** **256-word** **half**). + +**`TROWARG*` / `TCOLARG*` variant:** + +- **64-bit** **value∥index** **per** **slot** → **double** **width** **or** **sidecar** **index** **RAM** (**§4.1** **unchanged** **topology**). + +**Staged partials (`rStgUB` / `cStgUB`):** + +- **Separate** **small** **buffer** **or** **stretched** **schedule** (**§9.3.1** **Assumption B**) — **orthogonal** to **Acc** ping-pong. + +**Summary:** **§4.1** **256 × 32 b × 2** **ping-pong** **Acc**; **`N_run = 512`**; **per-slot** **RMW** **or** **bypass-to-DFF**; **Wr0+Wr1** **drain** **one** **half** (**256** **words**) **per** **selected** **phase**. **Acc waves** **remap** **`fiber_id → ρ`** when **logical** **fibers** **exceed** **512**. + +### 9.4 Cycle model (both axes) + +Both axes assume **§3.2** unary ingest: **4 cycles** minimum to read the full tile with **two** 512 B read ports. + +- **Lower bound (*LB*):** ideal overlap of read, **one** wide pipelined `⌈log₂ K⌉`-stage tree, and cross-strip merge; **ignores** time-multiplexing many thin fibers on **one** physical tree. +- **Upper bound (*UB*):** **8** strips each pay **W** tree-stage units on **one** shared tree, plus **one cross-strip phase per output fiber** (`R` outputs for `TROW*`, `C` outputs for `TCOL*`). + +### 9.5 Reconfigurable reduction tree — how the hardware “shape” follows the table + +The datapath is **one logical pipeline** reused by all table rows; its **effective shape** is selected by microcode from the **`r*`** or **`c*`** fields. + +1. **Unpack** maps a 512 B strip to up to **1024** logical lanes (FP4) / **512** (FP8) / … — **physical SIMD** may be narrower; the **logical** tree depth is still **⌈log₂ K⌉**. + +2. **Cross-lane tree (variable fan-in K):** implement as **`D_lane = ⌈log₂ K⌉`** stages of **pairwise** reduce ops. **K** jumps with `(format, R, C)`: + - **`rK`** (row) depends primarily on **`C`** when `rS=1`, else fixed **`512/E`**. + - **`cK`** (column) depends primarily on **`R`** when `cS=1`, else **`512/E`**. + - For **rectangular** tiles, **`rK ≠ cK`** in general → row and column ops need **different programmed depths** for the same stored tile. + +3. **Cross-strip merger (variable S):** after each strip contributes a **partial**, a **balanced tree** of depth **`⌈log₂ S⌉`** combines partials for the same fiber ID (`rS` or `cS`). **S ∈ {1,2,4,8}** in this enumeration → at most **3** compare stages after lane tree. + +4. **Temporal “stretch” (W):** when **`row_B < 512`** (or **`col_B < 512`**), **multiple complete fibers** land in one strip. A **single** lane tree of depth **`D_lane`** must run **`512/row_B`** (or **`512/col_B`**) times **per strip** unless duplicated in silicon → **`W`** scales **linearly** with packed fiber count. + +```mermaid +flowchart LR + subgraph strip [Per 512B strip] + U[Unpack] --> MUX[Mux K active lanes] + MUX --> LT[log2 K-stage lane tree] + LT --> P[Partial per fiber ID] + end + P --> CS[Depth log2 S cross-strip tree] + CS --> ACC[Acc ping-pong 256×32b×2 RMW §4.1] + ACC --> OUT[Reduced fiber value] +``` + +#### 9.5.1 How many distinct “shapes” are needed? + +| Counting notion | Value | Meaning | +|-----------------|------:|---------| +| **Physical datapaths** | **1** | One reducer suffices if it supports **max K = 1024**, **max `D_lane` = 10**, **max `S` = 8** (`D_cross ≤ 3`), with **per-stage bypass** and **programmable lane mask**. | +| **Unique `(D_lane, D_cross, W_strip)` tuples** | **47** | Distinct **time-scheduling recipes** for **either** axis, over all **50** geometries (same 47-set for row **or** column as multiset over shapes). | +| **Unique `(S, K, D_lane, D_cross)` quartets** | **23** | Coarser strip + tree fingerprint (per axis). | +| **Unique paired `(row tuple, column tuple)`** | **50** | One pair per **`(E,R,C)`**; **square** shapes have **identical** row and column metrics. | + +So: **one** parameterized **tree + cross-strip** unit covers the whole table; firmware/microcode must hold **47** **scheduling templates** (or equivalent parameterized loops) per axis, not **76** different RTL blocks. + +### 9.6 Summary by format (extrema over all legal shapes) + +Maxima over **both** axes are **identical** for each format family (swap **R↔C** maps extreme row cases to extreme column cases). + +| Format | N | # shapes | max **K** (either axis) | max **D_lane** | max **S** | max **D_cross** | min *LB* | max *LB* | max *UB* (r or c) | max **rAccB** / **cAccB** | max **rStgUB** / **cStgUB** | +|--------|---:|---:|---:|---:|---:|---:|---:|---:|---:|---:|---:| +| FP32 | 1024 | 11 | 128 | 7 | 8 | 3 | 4 | 14 | 516 | 4096 | 32768 | +| FP16 / BF16 | 2048 | 12 | 256 | 8 | 8 | 3 | 4 | 15 | 1028 | 8192 | 32768 | +| FP8 | 4096 | 13 | 512 | 9 | 8 | 3 | 4 | 16 | 2052 | 16384 | 32768 | +| MXFP4 / HiFP4 | 8192 | 14 | 1024 | 10 | 8 | 3 | 4 | 17 | 4100 | **32768** | **32768** | + +**Logical** peak **rAccB** / **cAccB** in the table is still **`4·R` / `4·C`** (up to **32 KiB** at **`R` or `C = 8192`**). **VEC-4K silicon** (**§9.3.2**): **running partials** = **`N_run = 512`** entries × **4 B** = **2048 B DFF**; **`R` or `C > 512`** uses **Acc waves** (**§9.3.1**). **rStgUB** / **cStgUB** remain **staging upper bounds** (still **≤ 32 KiB** per §2.1); **physical staging** may be a **small separate buffer** or **longer** microcode schedule. + +### 9.7 Legal `(format, R×C)` enumeration + +**76** rows — same **master-table** row count as **§9.1** (**50** distinct **`(E, R, C)`** geometries; **FP16** vs **BF16** duplicate shapes). **Per-axis metrics** (`r*`, `c*`, **LB/UB**, **rAccB**, **cAccB**, **rStgUB**, **cStgUB**) are defined in **§9.2–9.3**; **format extrema** in **§9.6**. + +| Format | E (B/elem) | N | R×C | +|--------|------------|---|-----| +| FP32 | 4 | 1024 | 1×1024 | +| FP32 | 4 | 1024 | 2×512 | +| FP32 | 4 | 1024 | 4×256 | +| FP32 | 4 | 1024 | 8×128 | +| FP32 | 4 | 1024 | 16×64 | +| FP32 | 4 | 1024 | 32×32 | +| FP32 | 4 | 1024 | 64×16 | +| FP32 | 4 | 1024 | 128×8 | +| FP32 | 4 | 1024 | 256×4 | +| FP32 | 4 | 1024 | 512×2 | +| FP32 | 4 | 1024 | 1024×1 | +| FP16 | 2 | 2048 | 1×2048 | +| FP16 | 2 | 2048 | 2×1024 | +| FP16 | 2 | 2048 | 4×512 | +| FP16 | 2 | 2048 | 8×256 | +| FP16 | 2 | 2048 | 16×128 | +| FP16 | 2 | 2048 | 32×64 | +| FP16 | 2 | 2048 | 64×32 | +| FP16 | 2 | 2048 | 128×16 | +| FP16 | 2 | 2048 | 256×8 | +| FP16 | 2 | 2048 | 512×4 | +| FP16 | 2 | 2048 | 1024×2 | +| FP16 | 2 | 2048 | 2048×1 | +| BF16 | 2 | 2048 | 1×2048 | +| BF16 | 2 | 2048 | 2×1024 | +| BF16 | 2 | 2048 | 4×512 | +| BF16 | 2 | 2048 | 8×256 | +| BF16 | 2 | 2048 | 16×128 | +| BF16 | 2 | 2048 | 32×64 | +| BF16 | 2 | 2048 | 64×32 | +| BF16 | 2 | 2048 | 128×16 | +| BF16 | 2 | 2048 | 256×8 | +| BF16 | 2 | 2048 | 512×4 | +| BF16 | 2 | 2048 | 1024×2 | +| BF16 | 2 | 2048 | 2048×1 | +| FP8 | 1 | 4096 | 1×4096 | +| FP8 | 1 | 4096 | 2×2048 | +| FP8 | 1 | 4096 | 4×1024 | +| FP8 | 1 | 4096 | 8×512 | +| FP8 | 1 | 4096 | 16×256 | +| FP8 | 1 | 4096 | 32×128 | +| FP8 | 1 | 4096 | 64×64 | +| FP8 | 1 | 4096 | 128×32 | +| FP8 | 1 | 4096 | 256×16 | +| FP8 | 1 | 4096 | 512×8 | +| FP8 | 1 | 4096 | 1024×4 | +| FP8 | 1 | 4096 | 2048×2 | +| FP8 | 1 | 4096 | 4096×1 | +| MXFP4 | 0.5 | 8192 | 1×8192 | +| MXFP4 | 0.5 | 8192 | 2×4096 | +| MXFP4 | 0.5 | 8192 | 4×2048 | +| MXFP4 | 0.5 | 8192 | 8×1024 | +| MXFP4 | 0.5 | 8192 | 16×512 | +| MXFP4 | 0.5 | 8192 | 32×256 | +| MXFP4 | 0.5 | 8192 | 64×128 | +| MXFP4 | 0.5 | 8192 | 128×64 | +| MXFP4 | 0.5 | 8192 | 256×32 | +| MXFP4 | 0.5 | 8192 | 512×16 | +| MXFP4 | 0.5 | 8192 | 1024×8 | +| MXFP4 | 0.5 | 8192 | 2048×4 | +| MXFP4 | 0.5 | 8192 | 4096×2 | +| MXFP4 | 0.5 | 8192 | 8192×1 | +| HiFP4 | 0.5 | 8192 | 1×8192 | +| HiFP4 | 0.5 | 8192 | 2×4096 | +| HiFP4 | 0.5 | 8192 | 4×2048 | +| HiFP4 | 0.5 | 8192 | 8×1024 | +| HiFP4 | 0.5 | 8192 | 16×512 | +| HiFP4 | 0.5 | 8192 | 32×256 | +| HiFP4 | 0.5 | 8192 | 64×128 | +| HiFP4 | 0.5 | 8192 | 128×64 | +| HiFP4 | 0.5 | 8192 | 256×32 | +| HiFP4 | 0.5 | 8192 | 512×16 | +| HiFP4 | 0.5 | 8192 | 1024×8 | +| HiFP4 | 0.5 | 8192 | 2048×4 | +| HiFP4 | 0.5 | 8192 | 4096×2 | +| HiFP4 | 0.5 | 8192 | 8192×1 | + +--- + +## 10. Related Documents + +- [`tregfile4k.md`](tregfile4k.md) — **8R/8W** tile RF, **8-cycle epoch**, **`G = (p+e) mod 8`** calendar; **§4.4** binds **R0/R4** to VEC **Port A/B**. +- [`outerCube.md`](outerCube.md) — MXU / outer product engine (different port count; **not** identical to VEC-4K’s 2R+2W model). +- [`PTOISA/README.md`](PTOISA/README.md) — authoritative ISA list and per-op references. + +--- + +## Document History + +| Version | Date | Notes | +|---------|------|-------| +| 0.1 | 2026-04-07 | Initial VEC-4K architecture sketch for 4 KB tiles, 2×512B R/W ports, PTO ISA vector subset | +| 0.2 | 2026-04-07 | §9: full `(format, R×C)` enumeration, `TROWMAX` tree complexity, `C_lb`/`C_ub` cycle models, master table | +| 0.3 | 2026-04-07 | Remove §5.3.1a examples; §9 unified row+column table; §9.5 tree morphing + shape counts (1 datapath, 47 recipes, 23 quartets, 50 pairs) | +| 0.4 | 2026-04-07 | §9.3.1 + table columns **rAccB**/**cAccB**/**rStgUB**/**cStgUB** (per-fiber partial SRAM sizing) | +| 0.5 | 2026-04-07 | §9.7: Markdown pipe table → compact **HTML** table (`font-size: 0.52em`, scroll wrapper) for preview rendering | +| 0.6 | 2026-04-07 | §9.3.2 multi-bank accumulator SRAM: **8×1024×32b** default, address map, ports, arg/staging variants | +| 0.7 | 2026-04-07 | §4.1 / §7 / §9.5 diagrams: **Acc 8-bank** in logical block diagram, row-reduce mermaid, reconfigurable-tree flow | +| 0.8 | 2026-04-07 | §4.3 **fiber_id** + **strip read calendar** (Rd0/Rd1 per cycle, operand sources, Acc RMW); ties to §5.3–5.4, §8, §9.3.2 / §9.5.1 templates | +| 0.9 | 2026-04-07 | §4.4 four **epoch-aligned** fiber calendars vs `tregfile4k.md` (**R0/R4**), dual/single-port ingest, **TROWSUM**/**TROWEXPANDADD** examples | +| 0.10 | 2026-04-07 | §4.4 **+4** examples (**E–H**): **FP8** `TROWSUM` **64×64**, **16×256**; **MXFP4** `TROWSUM` **512×16**; **MXFP4** **32×256** (superseded for **H** in **v0.11**) | +| 0.11 | 2026-04-07 | §4.4 Example **H** → **`TCOLSUM` MXFP4 32×256** (**`fiber_id = c`**); §4.3 legend **`TCOL*`** cross-ref | +| 0.12 | 2026-04-07 | **`TCOL*` / `TCOLEXPAND*`**: **no transpose scratchpad** — native row-major + gather/splat; §5.3.2, §6, §8–9, **Example H** rewritten; **`c*`** = metrics-only substitution | +| 0.13 | 2026-04-07 | **§3.1** TRegFile **no gather**; **`TCOL*`** = strip **replay** + VEC **column mux** + **Acc RMW**; **Example H** multi-epoch / **`P`** bands; §5.3.2, §6, §8–9 aligned | +| 0.14 | 2026-04-07 | **§5.3.2** **`N_tree`** / **`N_acc`**, **`P_beat=min`**, **`#waves=⌈C/N_acc⌉`**; **Example H** + §4.3/§8/§9 use **`N_acc`** (not lone **`P`**) | +| 0.15 | 2026-04-07 | **`f`** (commits/tree/full-scan); **`#waves=max(⌈C/N_acc⌉,⌈C/(N_tree·f)⌉)`**; §5.3.2, Example H, §4.3/§8/§9 | +| 0.16 | 2026-04-07 | §4.4 Example **H**: **illustrative** **`#waves_acc`/`#waves_tree`** split; **Acc-limited** multi-epoch table caption; **tree-limited** extra waves note | +| 0.17 | 2026-04-07 | **`N_run = 512`**: running partials **8×64×32b DFF** (~**2 KiB**), **16×** vs **8192** peak; **Acc waves** / **`ρ`** remap; §4.1/§4.3/§5.3.2/§8/§9.3–9.7 + mermaid | +| 0.18 | 2026-04-07 | **§5.3.2** / **§9.3.1** / **§8**: **`K_outer`** hardware loops, **fiber offset**, **Wr staging** to **merge** partial **`dst`** when Acc capacity **<** extreme shape | +| 0.19 | 2026-04-07 | **§5.3.2**: **`#waves_Nrun`**, **`#W`** **max** **formula**, **`#W_trow`** **`TROW*`**; **`K_outer`** **vs** **`#W`**; **§4.3** / **§4.4 H** / **§8** / **§9.3** **`#W`** **cross-refs**; **§5.3.1** **Acc** **wording** | +| 0.20 | 2026-04-07 | **§9.7**: drop wide **HTML** **r\*/c\*** **master** table → **Markdown** **4-column** **(Format, E, N, R×C)** only; **cross-refs** **§5.3.2** / **§9.3.1** | +| 0.21 | 2026-04-07 | **§4.1** **dataflow** diagram: **opcode+shape→control→crossbar** (**1024 B**), **`N_tree=128`**, **Acc** **256×32b×2** **ping-pong** **adder+fb**, **Wr half** → **Wr0+Wr1**; **§3.3** / **§4.2–4.3** / **§7–8** / **§9.3.2** / **§9.5** mermaid | +| 0.22 | 2026-04-07 | **§4.1** / **§7**: split **(A)** **align/unpack/permute** vs **(B)** **128** **groups**; **W_prep,i** / **W_ALU,i** / **W_tree,i**; **W_ALU ≥ W_tree** | +| 0.23 | 2026-04-07 | **Acc** **bypass**: **write-through** **to** **DFF** **without** **combine** **adder** (**§4.1**, **§9.3.2**, **§7–8**) | From c069c6fe3bc6048f01b9d4364cff1016ab189573 Mon Sep 17 00:00:00 2001 From: Mac Date: Mon, 20 Apr 2026 16:46:42 +0800 Subject: [PATCH 02/12] Add outerCube tile16 datapath plots and NVIDIA shuffle montage Made-with: Cursor --- designs/outerCube/nv_shuffle.py | 301 +++++++ .../outerCube/plot_tile16_vector_datapath.py | 756 ++++++++++++++++++ .../tile16_figures/elementwise_all.png | Bin 0 -> 480089 bytes .../outerCube/tile16_figures/expand_all.png | Bin 0 -> 342947 bytes .../tile16_figures/mergesort_all.png | Bin 0 -> 609277 bytes .../tile16_figures/nv_shuffle_all.png | Bin 0 -> 467588 bytes .../outerCube/tile16_figures/reduce_all.png | Bin 0 -> 292627 bytes 7 files changed, 1057 insertions(+) create mode 100644 designs/outerCube/nv_shuffle.py create mode 100644 designs/outerCube/plot_tile16_vector_datapath.py create mode 100644 designs/outerCube/tile16_figures/elementwise_all.png create mode 100644 designs/outerCube/tile16_figures/expand_all.png create mode 100644 designs/outerCube/tile16_figures/mergesort_all.png create mode 100644 designs/outerCube/tile16_figures/nv_shuffle_all.png create mode 100644 designs/outerCube/tile16_figures/reduce_all.png diff --git a/designs/outerCube/nv_shuffle.py b/designs/outerCube/nv_shuffle.py new file mode 100644 index 00000000..3e738d01 --- /dev/null +++ b/designs/outerCube/nv_shuffle.py @@ -0,0 +1,301 @@ +#!/usr/bin/env python3 +""" +NVIDIA warp shuffle schematic (16 B register tile). + +One PNG montage (4×4): rows = __shfl_sync (per-lane indexed read; here a fixed permutation), +__shfl_up_sync, +__shfl_down_sync, __shfl_xor_sync; columns = FP32 / FP16 / FP8 / FP4 (E = 4/2/1/0.5 B). + +Each pane: input lanes (▭ width ∝ E) on top, output lanes on bottom, curved wires +lane i ← lane src(i). Not cycle-accururate; illustration only. +""" + +from __future__ import annotations + +import argparse +import math +import os +from dataclasses import dataclass +from typing import List, Sequence, Tuple + +from matplotlib.axes import Axes +from matplotlib.patches import Circle, FancyArrowPatch, Rectangle + +import matplotlib.pyplot as plt + +TILE_BYTES = 16 +E_REF = 4.0 + + +@dataclass(frozen=True) +class FloatForm: + E: float # bytes per element + label: str + + @property + def n(self) -> int: + return int(round(TILE_BYTES / self.E)) + + +def formats() -> List[FloatForm]: + return [ + FloatForm(4.0, "FP32"), + FloatForm(2.0, "FP16"), + FloatForm(1.0, "FP8"), + FloatForm(0.5, "FP4"), + ] + + +def _rect(ax: Axes, cx: float, cy: float, w: float, h: float, **kwargs) -> Rectangle: + kwargs.setdefault("zorder", 2) + r = Rectangle((cx - w / 2, cy - h / 2), w, h, fill=True, **kwargs) + ax.add_patch(r) + return r + + +def _rect_top(cy: float, h: float) -> float: + return cy + h / 2 + + +def _rect_bottom(cy: float, h: float) -> float: + return cy - h / 2 + + +def _lane_layout(E: float, n: int, x0: float, x1: float) -> Tuple[float, float, List[float]]: + """Single contiguous row of n elements; rectangle width ∝ E (same spirit as tile16 script).""" + e = max(float(E), 0.5) + span = x1 - x0 + g_in = min(0.028, 0.11 * span / max(n, 2)) + gaps_inside = max(n - 1, 0) * g_in + slack = span - gaps_inside + if slack <= 0: + g_in *= 0.5 + gaps_inside = max(n - 1, 0) * g_in + slack = span - gaps_inside + K = slack / (n * E_REF) + w = max(0.0028, K * e) + if n * w + gaps_inside > span: + w = max(0.0028, (span - gaps_inside) / max(n, 1)) + h = min(0.038, 0.48 / max(n, 1)) + xs: List[float] = [] + x = x0 + for i in range(n): + xs.append(x + w / 2) + x += w + if i < n - 1: + x += g_in + return w, h, xs + + +def _shfl_linear_permutation_params(n: int) -> Tuple[int, int]: + """ + Coefficients (a, b) for src(dst) = (a * dst + b) % n with gcd(a, n) == 1 so each + destination reads from a distinct source (full permutation on lanes). + """ + if n <= 1: + return 1, 0 + a = 1 + for cand in range(2, n): + if math.gcd(cand, n) == 1: + a = cand + break + b = 1 if n > 1 else 0 + return a, b + + +def _shuffle_src( + op: str, n: int, dst: int, *, delta: int = 1, xor_mask: int = 4 +) -> int: + """Map destination lane -> source lane for schematic (CUDA-ish).""" + if n <= 0: + return 0 + if op == "shfl": + a, b = _shfl_linear_permutation_params(n) + return (a * dst + b) % n + if op == "shfl_up": + j = dst - delta + return j if j >= 0 else 0 + if op == "shfl_down": + j = dst + delta + return j if j < n else n - 1 + if op == "shfl_xor": + m = xor_mask % n + if m == 0: + m = 1 if n > 1 else 0 + return dst ^ m + return dst + + +def render_shuffle_pane( + ax: Axes, + op: str, + op_title: str, + cuda_name: str, + spec: FloatForm, + *, + title_fs: float = 8.0, + lane_fs: float = 5.0, +) -> None: + n = spec.n + ax.set_xlim(0, 1) + ax.set_ylim(0, 1) + ax.axis("off") + + E = float(spec.E) + x0, x1 = 0.05, 0.95 + w, h, xs = _lane_layout(E, n, x0, x1) + + y_in = 0.74 + y_out = 0.26 + ax.set_title( + f"{op_title}\n{cuda_name} — {spec.label} — E={E:g} B, N={n} ({TILE_BYTES} B tile)", + fontsize=title_fs, + pad=4, + ) + + for i in range(n): + _rect(ax, xs[i], y_in, w, h, facecolor="#cfe8ff", edgecolor="#1a4f8c", linewidth=0.9) + if n <= 16: + ax.text( + xs[i], + y_in + h / 2 + 0.022, + f"L{i}", + ha="center", + va="bottom", + fontsize=max(4.0, lane_fs), + color="#123", + ) + + for i in range(n): + _rect(ax, xs[i], y_out, w, h, facecolor="#dff5df", edgecolor="#1a6c2e", linewidth=0.9) + if n <= 16: + ax.text( + xs[i], + y_out - h / 2 - 0.018, + f"O{i}", + ha="center", + va="top", + fontsize=max(4.0, lane_fs), + color="#123", + ) + + # Legend for op-specific params (tiny) + if op == "shfl": + pa, pb = _shfl_linear_permutation_params(n) + note = f"per-lane srcLane: ( {pa}·i + {pb} ) mod {n} (each Oi reads a different Li)" + elif op == "shfl_up": + note = "delta=1 (from lower lane id)" + elif op == "shfl_down": + note = "delta=1 (from higher lane id)" + else: + m = 4 % n if n else 0 + if m == 0: + m = 1 if n > 1 else 0 + note = f"maskLane={m} (XOR index)" + + ax.text(0.5, 0.06, note, ha="center", va="center", fontsize=max(3.8, lane_fs - 0.8), color="#444") + + xor_mask = 4 + for dst in range(n): + src = _shuffle_src(op, n, dst, delta=1, xor_mask=xor_mask) + x0a, y0a = xs[src], _rect_bottom(y_in, h) + x1a, y1a = xs[dst], _rect_top(y_out, h) + dx = x1a - x0a + rad = 0.22 * (1.0 if dx >= 0 else -1.0) * (0.35 + min(abs(dx) * 1.8, 0.9)) + style = "arc3,rad=" + str(rad) + a = FancyArrowPatch( + (x0a, y0a), + (x1a, y1a), + arrowstyle="-|>", + linestyle="-", + linewidth=0.75, + color="#333", + connectionstyle=style, + mutation_scale=7, + zorder=3, + clip_on=False, + ) + ax.add_patch(a) + + # Optional small node at merge (purely decorative for dense N) + if n <= 8: + cr = min(0.014, 0.5 * h) + for dst in range(n): + xm = 0.5 * (xs[_shuffle_src(op, n, dst, xor_mask=xor_mask)] + xs[dst]) + ym = 0.5 * (y_in + y_out) + c = Circle((xm, ym), cr, facecolor="#f6f0ff", edgecolor="#555", linewidth=0.6, zorder=1) + ax.add_patch(c) + + +def _save_montage_4x4(out_path: str, *, dpi: int = 140) -> None: + forms = formats() + ops: List[Tuple[str, str, str]] = [ + ("shfl", "shfl (per-lane indexed)", "__shfl_sync"), + ("shfl_up", "shfl_up", "__shfl_up_sync"), + ("shfl_down", "shfl_down", "__shfl_down_sync"), + ("shfl_xor", "shfl_xor", "__shfl_xor_sync"), + ] + + fig, axes = plt.subplots(4, 4, figsize=(22, 22), dpi=dpi) + fig.suptitle( + f"NVIDIA warp shuffle — {TILE_BYTES} B tile, ▭ width ∝ element size (FP32/FP16/FP8/FP4)", + fontsize=13, + y=0.995, + ) + + for r, (op, short, cuda) in enumerate(ops): + for c, spec in enumerate(forms): + render_shuffle_pane(axes[r, c], op, short, cuda, spec, title_fs=7.6, lane_fs=5.0) + + for c, spec in enumerate(forms): + axes[0, c].text( + 0.5, + 1.02, + spec.label, + transform=axes[0, c].transAxes, + ha="center", + va="bottom", + fontsize=10, + fontweight="600", + color="#111", + ) + + fig.text( + 0.5, + 0.012, + ( + "Each column fixes E (bytes/element) with R×C×E = 16 B; rows are shuffle kinds. " + "Top row: each Oi uses its own srcLane(i) (here a linear permutation on lanes; " + "broadcast is the special case srcLane(i)=const). " + "Arrows: value at Oi from Lsrc (schematic; mask/warp participation omitted)." + ), + ha="center", + fontsize=8.5, + color="#222", + ) + fig.subplots_adjust(left=0.03, right=0.97, top=0.94, bottom=0.04, hspace=0.42, wspace=0.20) + fig.savefig(out_path, bbox_inches="tight") + plt.close(fig) + + +def main(argv: Sequence[str] | None = None) -> int: + p = argparse.ArgumentParser(description="Plot NVIDIA warp shuffle 4×4 montage (one PNG).") + p.add_argument( + "-o", + "--out", + default=os.path.join(os.path.dirname(__file__), "tile16_figures", "nv_shuffle_all.png"), + help="Output PNG path (directories created if missing).", + ) + p.add_argument("--dpi", type=int, default=140, help="Figure DPI.") + args = p.parse_args(list(argv) if argv is not None else None) + + out_dir = os.path.dirname(os.path.abspath(args.out)) + if out_dir: + os.makedirs(out_dir, exist_ok=True) + _save_montage_4x4(args.out, dpi=args.dpi) + print(f"Wrote {args.out}") + return 0 + + +if __name__ == "__main__": + raise SystemExit(main()) diff --git a/designs/outerCube/plot_tile16_vector_datapath.py b/designs/outerCube/plot_tile16_vector_datapath.py new file mode 100644 index 00000000..d6158af1 --- /dev/null +++ b/designs/outerCube/plot_tile16_vector_datapath.py @@ -0,0 +1,756 @@ +#!/usr/bin/env python3 +""" +Generate small-tile (16 B) vector datapath illustrations inspired by +`vector4k.md`: A and B holding registers as contiguous blocks (all A, then all +B), ▭ width ∝ E, circles = 2-input execution units, crossed wires. + +Writes 4 PNGs (one montage per operation type: 8 subplots each) to an output +directory (default: ./tile16_figures next to this script). Types 1–4: elementwise, +reduce, expand, mergesort (compare–swap levels). +""" + +from __future__ import annotations + +import argparse +import os +from dataclasses import dataclass +from typing import Callable, List, Sequence, Tuple + +from matplotlib.axes import Axes + +import matplotlib.pyplot as plt +from matplotlib.patches import Circle, FancyArrowPatch, Rectangle + +TILE_BYTES = 16 +# Reference element size (bytes) for rectangle width scaling in figures. +E_REF = 4.0 + + +@dataclass(frozen=True) +class TileShape: + idx: int + R: int + C: int + E: float # bytes per logical element (0.5 allowed for packed nibble) + label: str + + @property + def N(self) -> int: + assert abs(self.R * self.C * self.E - TILE_BYTES) < 1e-6, self + return int(round(TILE_BYTES / self.E)) + + def fmt_desc(self) -> str: + return f"R×C = {self.R}×{self.C}, E = {self.E} B/elem → N = {self.N}" + + +def canonical_shapes() -> List[TileShape]: + # Eight distinct (R, C, E) with R*C*E = 16 B; mix wide/narrow + formats. + return [ + TileShape(1, 1, 4, 4.0, "1×4 FP32 (wide row)"), + TileShape(2, 4, 1, 4.0, "4×1 FP32 (tall col)"), + TileShape(3, 2, 2, 4.0, "2×2 FP32"), + TileShape(4, 1, 8, 2.0, "1×8 FP16"), + TileShape(5, 8, 1, 2.0, "8×1 FP16"), + TileShape(6, 2, 4, 2.0, "2×4 FP16"), + TileShape(7, 4, 4, 1.0, "4×4 FP8"), + TileShape(8, 4, 8, 0.5, "4×8 MXFP4 (½ B/elem)"), + ] + + +def _rect(ax: Axes, cx: float, cy: float, w: float, h: float, **kwargs) -> Rectangle: + """Axis-aligned rectangle centered at (cx, cy).""" + kwargs.setdefault("zorder", 2) + r = Rectangle((cx - w / 2, cy - h / 2), w, h, fill=True, **kwargs) + ax.add_patch(r) + return r + + +def _rect_top(cy: float, h: float) -> float: + return cy + h / 2 + + +def _rect_bottom(cy: float, h: float) -> float: + return cy - h / 2 + + +def _circ_top(cy: float, r: float) -> float: + return cy + r + + +def _circ_bottom(cy: float, r: float) -> float: + return cy - r + + +def _ab_block_layout( + E: float, + n_a: int, + n_b: int, + x0: float, + x1: float, +) -> Tuple[float, float, float, float, List[float], List[float]]: + """ + All A operands contiguous, then a gap, then all B operands contiguous. + Same width w for every element rectangle (w ∝ E). Returns: + (w, h, gap_inside_block, gap_between_ab, xa_centers, xb_centers). + """ + e = max(float(E), 0.5) + span = x1 - x0 + gap_block = min(0.032, 0.09 * span) + g_in = min(0.009, 0.14 * span / max(n_a + n_b, 2)) + gaps_inside = max(n_a - 1, 0) * g_in + max(n_b - 1, 0) * g_in + coef = n_a + n_b + slack = span - gap_block - gaps_inside + if slack <= 0: + slack = 0.01 * span + gap_block *= 0.5 + g_in *= 0.5 + gaps_inside = max(n_a - 1, 0) * g_in + max(n_b - 1, 0) * g_in + slack = span - gap_block - gaps_inside + K = slack / (coef * E_REF) + w = max(0.0025, K * e) + if coef * w + gaps_inside + gap_block > span: + w = max(0.0025, (span - gap_block - gaps_inside) / max(coef, 1)) + h = min(0.032, 0.52 / max(n_a + n_b, 1)) + + xa: List[float] = [] + x = x0 + for i in range(n_a): + xa.append(x + w / 2) + x += w + if i < n_a - 1: + x += g_in + x += gap_block + xb: List[float] = [] + for i in range(n_b): + xb.append(x + w / 2) + x += w + if i < n_b - 1: + x += g_in + return w, h, g_in, gap_block, xa, xb + + +def _circle(ax, cx: float, cy: float, r: float, **kwargs) -> Circle: + kwargs.setdefault("zorder", 2) + c = Circle((cx, cy), r, fill=True, **kwargs) + ax.add_patch(c) + return c + + +def _wire_straight( + ax: Axes, + p0: Tuple[float, float], + p1: Tuple[float, float], + *, + color: str = "#444", + lw: float = 0.9, + zorder: float = 4, +) -> None: + """Straight segment (exact endpoints; draws above operand patches).""" + ax.plot( + [p0[0], p1[0]], + [p0[1], p1[1]], + color=color, + linewidth=lw, + solid_capstyle="round", + zorder=zorder, + clip_on=False, + ) + + +def _wire( + ax, + p0: Tuple[float, float], + p1: Tuple[float, float], + rad: float = 0.0, + color: str = "#444", + lw: float = 0.9, + zorder: float = 4, +) -> None: + if abs(rad) < 1e-9: + _wire_straight(ax, p0, p1, color=color, lw=lw, zorder=zorder) + return + style = "arc3,rad=" + str(rad) + a = FancyArrowPatch( + p0, + p1, + arrowstyle="-", + linestyle="-", + linewidth=lw, + color=color, + connectionstyle=style, + mutation_scale=1, + zorder=zorder, + clip_on=False, + ) + ax.add_patch(a) + + +def _odd_even_transposition_stages(n: int, max_stages: int) -> List[List[Tuple[int, int]]]: + """Disjoint compare–swap pairs per stage (odd / even offset), straight multistage network.""" + out: List[List[Tuple[int, int]]] = [] + for p in range(max_stages): + pairs: List[Tuple[int, int]] = [] + start = p % 2 + for i in range(start, n - 1, 2): + pairs.append((i, i + 1)) + out.append(pairs) + return out + + +def _title_block(ax: Axes, kind: str, spec: TileShape, *, fontsize: float = 11) -> None: + ax.set_title( + f"{kind} — {TILE_BYTES} B tile\n{spec.label} — {spec.fmt_desc()}", + fontsize=fontsize, + pad=6, + ) + + +def render_elementwise( + ax: Axes, + spec: TileShape, + *, + title_fontsize: float = 9, + label_fs: float = 6, + show_footer: bool = False, +) -> None: + N = spec.N + ax.set_xlim(0, 1) + ax.set_ylim(0, 1) + ax.axis("off") + _title_block(ax, "Element-wise (2-input / lane)", spec, fontsize=title_fontsize) + + # One row: all A contiguous, gap, all B contiguous; width ∝ E; ALU below each (A[i],B[i]) pair. + x0, x1 = 0.04, 0.96 + y_reg, y_u, y_o = 0.86, 0.50, 0.30 + w, h, _g_in, _gap_ab, xa_list, xb_list = _ab_block_layout(float(spec.E), N, N, x0, x1) + cr = min(0.022, 0.04 / max(N / 8, 1), 0.55 * h) + + ax.text(0.02, y_reg + h / 2 + 0.045, "A block | B block (width ∝ E)", fontsize=max(5.0, label_fs)) + + for i in range(N): + xa_c, xb_c = xa_list[i], xb_list[i] + x_mid = 0.5 * (xa_c + xb_c) + _rect(ax, xa_c, y_reg, w, h, facecolor="#cfe8ff", edgecolor="#1a4f8c", linewidth=1.0) + ax.text(xa_c, y_reg + h / 2 + 0.028, f"A{i}", ha="center", va="bottom", fontsize=label_fs) + _rect(ax, xb_c, y_reg, w, h, facecolor="#ffe8cf", edgecolor="#8c4f1a", linewidth=1.0) + ax.text(xb_c, y_reg + h / 2 + 0.028, f"B{i}", ha="center", va="bottom", fontsize=label_fs) + + _circle(ax, x_mid, y_u, cr, facecolor="#e8e8ff", edgecolor="#333", linewidth=1.0) + ax.text(x_mid, y_u, "⊕", ha="center", va="center", fontsize=max(5.0, label_fs), color="#222") + + rad_a = 0.18 * ((-1) ** i) + rad_b = -rad_a + _wire( + ax, + (xa_c, _rect_bottom(y_reg, h)), + (x_mid, _circ_top(y_u, cr)), + rad=rad_a, + ) + _wire( + ax, + (xb_c, _rect_bottom(y_reg, h)), + (x_mid, _circ_top(y_u, cr)), + rad=rad_b, + ) + + wo, ho = w * 0.92, h * 0.92 + _rect(ax, x_mid, y_o, wo, ho, facecolor="#dff5df", edgecolor="#1a6c2e", linewidth=0.9) + _wire_straight( + ax, + (x_mid, _circ_bottom(y_u, cr)), + (x_mid, _rect_top(y_o, ho)), + lw=0.7, + color="#555", + ) + + if show_footer: + ax.text( + 0.5, + 0.02, + "▭ = element (width ∝ E); ○ = 2-input ALU; opposite bends = crossed operand paths.", + ha="center", + va="bottom", + fontsize=6, + color="#333", + ) + + +def render_reduce( + ax: Axes, + spec: TileShape, + *, + title_fontsize: float = 9, + label_fs: float = 5.5, + show_footer: bool = False, +) -> None: + """Row-style reduce along C for fiber row 0; then binary reduction tree.""" + C = spec.C + ax.set_xlim(0, 1) + ax.set_ylim(0, 1) + ax.axis("off") + _title_block(ax, "Reduce (row 0, axis C)", spec, fontsize=title_fontsize) + + N = C + x0, x1 = 0.06, 0.94 + y_reg = 0.12 + y_leaf_circ = 0.30 + w, h, _g_in, _gap_ab, xa_list, xb_list = _ab_block_layout(float(spec.E), N, N, x0, x1) + cr = min(0.024, 0.05 / max(N / 8, 1), 0.55 * h) + + ax.text(0.02, 0.94, f"fiber row 0; R={spec.R}", fontsize=max(5.0, label_fs)) + ax.text(0.02, y_reg + h / 2 + 0.05, "A block | B block (width ∝ E)", fontsize=max(5.0, label_fs)) + + for i in range(N): + xa_c, xb_c = xa_list[i], xb_list[i] + x_mid = 0.5 * (xa_c + xb_c) + _rect(ax, xa_c, y_reg, w, h, facecolor="#cfe8ff", edgecolor="#1a4f8c", linewidth=1.0) + ax.text(xa_c, y_reg + h / 2 + 0.028, f"A0,{i}", ha="center", va="bottom", fontsize=label_fs) + _rect(ax, xb_c, y_reg, w, h, facecolor="#ffe8cf", edgecolor="#8c4f1a", linewidth=1.0) + ax.text(xb_c, y_reg + h / 2 + 0.028, f"B0,{i}", ha="center", va="bottom", fontsize=label_fs) + + leaf_out_x: List[float] = [] + for i in range(N): + xa_c, xb_c = xa_list[i], xb_list[i] + x_mid = 0.5 * (xa_c + xb_c) + _circle(ax, x_mid, y_leaf_circ, cr, facecolor="#e8e8ff", edgecolor="#333", linewidth=1.0) + rad_a = 0.12 * ((-1) ** i) + _wire( + ax, + (xa_c, _rect_top(y_reg, h)), + (x_mid, _circ_bottom(y_leaf_circ, cr)), + rad=rad_a, + ) + _wire( + ax, + (xb_c, _rect_top(y_reg, h)), + (x_mid, _circ_bottom(y_leaf_circ, cr)), + rad=-rad_a, + ) + leaf_out_x.append(x_mid) + + leaves = [(x, y_leaf_circ) for x in leaf_out_x] + cur = leaves + dy = 0.09 + r_tree = cr * 1.05 + y = y_leaf_circ + cr + dy * 0.55 + depth = 0 + while len(cur) > 1: + r_child = cr if depth == 0 else r_tree + nxt: List[Tuple[float, float]] = [] + for j in range(0, len(cur), 2): + if j + 1 < len(cur): + xm = 0.5 * (cur[j][0] + cur[j + 1][0]) + xL, xR = cur[j][0], cur[j + 1][0] + else: + xm = cur[j][0] + xL = xR = cur[j][0] + _circle(ax, xm, y, r_tree, facecolor="#f3e8ff", edgecolor="#333", linewidth=1.0) + _wire( + ax, + (xL, cur[j][1] + r_child), + (xm, _circ_bottom(y, r_tree)), + rad=0.05, + ) + if j + 1 < len(cur): + _wire( + ax, + (xR, cur[j + 1][1] + r_child), + (xm, _circ_bottom(y, r_tree)), + rad=-0.05, + ) + nxt.append((xm, y)) + cur = nxt + y += dy + depth += 1 + + root = cur[0] + w_acc = max(w * 1.25, 0.014) + y_acc_c = root[1] + 0.08 + _rect( + ax, + root[0], + y_acc_c, + w_acc, + h, + facecolor="#ffd7d7", + edgecolor="#8c1a1a", + linewidth=1.1, + ) + _wire_straight( + ax, + (root[0], _circ_top(root[1], r_tree)), + (root[0], _rect_bottom(y_acc_c, h)), + lw=0.85, + color="#333", + ) + ax.text(root[0], y_acc_c + h / 2 + 0.045, "Acc", ha="center", va="bottom", fontsize=max(5.0, label_fs + 1)) + + if show_footer: + ax.text( + 0.5, + 0.01, + "○ = 2-input combine; upper = reduction tree.", + ha="center", + fontsize=6, + ) + + +def _fanout_levels_top_down( + C: int, x0: float, x1: float, y_top: float, y_bottom: float +) -> List[List[Tuple[float, float]]]: + """Balanced pairing tree: index 0 is root, last level has C leaves (left-to-right x).""" + xs = [x0 + (x1 - x0) * i / max(C - 1, 1) for i in range(C)] + layers_bottom_up: List[List[Tuple[float, float]]] = [[(x, 0.0) for x in xs]] + while len(layers_bottom_up[-1]) > 1: + prev = layers_bottom_up[-1] + nxt: List[Tuple[float, float]] = [] + for j in range(0, len(prev), 2): + if j + 1 < len(prev): + xm = 0.5 * (prev[j][0] + prev[j + 1][0]) + else: + xm = prev[j][0] + nxt.append((xm, 0.0)) + layers_bottom_up.append(nxt) + layers = list(reversed(layers_bottom_up)) + nh = len(layers) + for i, lev in enumerate(layers): + if nh == 1: + yi = y_top + else: + yi = y_top - i * ((y_top - y_bottom) / (nh - 1)) + layers[i] = [(x, yi) for (x, _) in lev] + return layers + + +def _fanout_levels_from_leaf_xs( + leaf_xs: List[float], y_top: float, y_bottom: float +) -> List[List[Tuple[float, float]]]: + """Same pairing tree as `_fanout_levels_top_down`, but leaf x positions are explicit.""" + if not leaf_xs: + return [] + layers_bottom_up: List[List[Tuple[float, float]]] = [[(x, 0.0) for x in leaf_xs]] + while len(layers_bottom_up[-1]) > 1: + prev = layers_bottom_up[-1] + nxt: List[Tuple[float, float]] = [] + for j in range(0, len(prev), 2): + if j + 1 < len(prev): + xm = 0.5 * (prev[j][0] + prev[j + 1][0]) + else: + xm = prev[j][0] + nxt.append((xm, 0.0)) + layers_bottom_up.append(nxt) + layers = list(reversed(layers_bottom_up)) + nh = len(layers) + for i, lev in enumerate(layers): + if nh == 1: + yi = y_top + else: + yi = y_top - i * ((y_top - y_bottom) / (nh - 1)) + layers[i] = [(x, yi) for (x, _) in lev] + return layers + + +def render_expand( + ax: Axes, + spec: TileShape, + *, + title_fontsize: float = 9, + label_fs: float = 5.5, + show_footer: bool = False, +) -> None: + """Expand along C: v[r] in A fans out; B holds src row; leaf 2-input combines.""" + C = spec.C + ax.set_xlim(0, 1) + ax.set_ylim(0, 1) + ax.axis("off") + _title_block(ax, "Expand (row 0, fanout C)", spec, fontsize=title_fontsize) + + y_fan_top = 0.82 + y_fan_bot = 0.52 + y_leaf_circ = 0.34 + y_row = 0.12 + + x0, x1 = 0.05, 0.95 + w, h, _g_in, _gap_ab, xa_list, xb_list = _ab_block_layout(float(spec.E), 1, C, x0, x1) + cr = min(0.026, 0.05 / max(C / 8, 1), 0.55 * h) + xv = xa_list[0] + leaves_x = list(xb_list) + + levels = _fanout_levels_from_leaf_xs(leaves_x, y_top=y_fan_top, y_bottom=y_fan_bot) + root_fan_x, root_fan_y = levels[0][0] + + ax.text(0.02, 0.94, f"row 0; R={spec.R}", fontsize=max(5.0, label_fs)) + ax.text(0.02, y_row + h / 2 + 0.05, "A block (v) | B block (width ∝ E)", fontsize=max(5.0, label_fs)) + + _rect(ax, xv, y_row, w, h, facecolor="#cfe8ff", edgecolor="#1a4f8c", linewidth=1.0) + ax.text(xv, y_row + h / 2 + 0.03, "v[r]", ha="center", va="bottom", fontsize=max(5.0, label_fs + 0.5)) + for i, xb in enumerate(xb_list): + _rect(ax, xb, y_row, w, h, facecolor="#ffe8cf", edgecolor="#8c4f1a", linewidth=1.0) + ax.text(xb, y_row + h / 2 + 0.03, f"B0,{i}", ha="center", va="bottom", fontsize=label_fs) + + for lev in levels: + for (x, y) in lev: + _circle(ax, x, y, cr, facecolor="#eef8ff", edgecolor="#333", linewidth=1.0) + + _wire_straight( + ax, + (xv, _rect_top(y_row, h)), + (root_fan_x, _circ_bottom(root_fan_y, cr)), + lw=0.85, + color="#333", + ) + + for li in range(len(levels) - 1): + parents = levels[li] + children = levels[li + 1] + for pi, (xp, yp) in enumerate(parents): + for ci in (2 * pi, 2 * pi + 1): + if ci < len(children): + xc, yc = children[ci] + _wire( + ax, + (xp, _circ_bottom(yp, cr)), + (xc, _circ_top(yc, cr)), + rad=0.035 * ((-1) ** (ci + pi)), + ) + + y_fan_leaves = levels[-1][0][1] + for i, x_lane in enumerate(leaves_x): + xb = xb_list[i] + y_out_c = y_leaf_circ + 0.09 + wo, ho = w * 0.9, h * 0.9 + _circle(ax, x_lane, y_leaf_circ, cr, facecolor="#e8ffe8", edgecolor="#333", linewidth=1.0) + _wire_straight( + ax, + (x_lane, _circ_bottom(y_fan_leaves, cr)), + (x_lane, _circ_top(y_leaf_circ, cr)), + lw=0.9, + color="#444", + ) + _wire( + ax, + (xb, _rect_top(y_row, h)), + (x_lane, _circ_bottom(y_leaf_circ, cr)), + rad=0.14 * ((-1) ** i), + color="#8c4f1a", + lw=1.0, + ) + _rect(ax, x_lane, y_out_c, wo, ho, facecolor="#dff5df", edgecolor="#1a6c2e", linewidth=0.9) + _wire_straight( + ax, + (x_lane, _circ_bottom(y_leaf_circ, cr)), + (x_lane, _rect_top(y_out_c, ho)), + lw=0.75, + color="#555", + ) + + if show_footer: + ax.text( + 0.5, + 0.01, + "Fanout tree + leaf ○ with B lanes.", + ha="center", + fontsize=6, + ) + + +def render_mergesort( + ax: Axes, + spec: TileShape, + *, + title_fontsize: float = 9, + label_fs: float = 5.5, + show_footer: bool = False, +) -> None: + """ + Multi-level compare–swap (2-in / 2-out) only: straight wires from data to each ○, + straight wires between levels on fixed tracks; no shuffle bus / no horizontal rails. + """ + ax.set_xlim(0, 1) + ax.set_ylim(0, 1) + ax.axis("off") + _title_block(ax, "Mergesort (compare–swap)", spec, fontsize=title_fontsize) + + Ntile = spec.N + n_vis = min(Ntile, 8) + if n_vis < 2: + n_vis = 2 + if n_vis % 2 == 1: + n_vis -= 1 + m = n_vis // 2 + E = float(spec.E) + x0, x1 = 0.06, 0.94 + w, h, _g, _ggap, xa_list, xb_list = _ab_block_layout(E, m, m, x0, x1) + + y_reg = 0.84 + for i in range(m): + _rect(ax, xa_list[i], y_reg, w, h, facecolor="#cfe8ff", edgecolor="#1a4f8c", linewidth=0.9) + ax.text( + xa_list[i], + y_reg + h / 2 + 0.02, + f"A{i}", + ha="center", + va="bottom", + fontsize=max(4.5, label_fs - 0.5), + ) + for i in range(m): + _rect(ax, xb_list[i], y_reg, w, h, facecolor="#ffe8cf", edgecolor="#8c4f1a", linewidth=0.9) + ax.text( + xb_list[i], + y_reg + h / 2 + 0.02, + f"B{i}", + ha="center", + va="bottom", + fontsize=max(4.5, label_fs - 0.5), + ) + + note = f"n={n_vis} lanes" + (f" (tile N={Ntile})" if n_vis < Ntile else "") + ax.text(0.02, 0.97, note, fontsize=max(4.5, label_fs - 0.5)) + + n = 2 * m + xs_lane: List[float] = [] + for i in range(m): + xs_lane.append(xa_list[i]) + xs_lane.append(xb_list[i]) + y_rect_bot = _rect_bottom(y_reg, h) + cr = min(0.017, 0.32 / n, 0.45 * h) + leg = max(0.028, 0.05 - 0.002 * n) + max_stages = max(3, min(2 * n - 1, 10)) + stages = _odd_even_transposition_stages(n, max_stages) + + y_track = [y_rect_bot] * n + for pairs in stages: + y_in = min(y_track) + y_cs = y_in - leg - cr + y_next = y_cs - cr - 0.012 + paired: set[int] = set() + for (i, j) in pairs: + paired.add(i) + paired.add(j) + xm = 0.5 * (xs_lane[i] + xs_lane[j]) + _circle(ax, xm, y_cs, cr, facecolor="#f0e8ff", edgecolor="#333", linewidth=0.85) + ax.text( + xm, + y_cs, + "C&S", + ha="center", + va="center", + fontsize=max(4.0, label_fs - 1.0), + color="#222", + ) + _wire_straight(ax, (xs_lane[i], y_track[i]), (xm, _circ_top(y_cs, cr)), lw=0.75, color="#444") + _wire_straight(ax, (xs_lane[j], y_track[j]), (xm, _circ_top(y_cs, cr)), lw=0.75, color="#444") + dx = cr * 0.55 + _wire_straight(ax, (xm - dx, _circ_bottom(y_cs, cr)), (xs_lane[i], y_next), lw=0.75, color="#444") + _wire_straight(ax, (xm + dx, _circ_bottom(y_cs, cr)), (xs_lane[j], y_next), lw=0.75, color="#444") + y_track[i] = y_next + y_track[j] = y_next + for k in range(n): + if k not in paired: + _wire_straight(ax, (xs_lane[k], y_track[k]), (xs_lane[k], y_next), lw=0.65, color="#888") + y_track[k] = y_next + + y_cur = min(y_track) + y_out = max(0.07, y_cur - 0.025) + wo, ho = w * 0.82, h * 0.82 + for k in range(n): + _wire_straight( + ax, + (xs_lane[k], y_track[k]), + (xs_lane[k], _rect_top(y_out, ho)), + lw=0.55, + color="#666", + ) + for k in range(n): + _rect(ax, xs_lane[k], y_out, wo, ho, facecolor="#dff5df", edgecolor="#1a6c2e", linewidth=0.8) + ax.text(0.5, y_out - ho / 2 - 0.018, "merged lane values", ha="center", va="top", fontsize=5) + + if show_footer: + ax.text( + 0.5, + 0.015, + "▭ = key; ○ = compare–swap (2 in / 2 out); only straight segments, no shuffle / bus lines.", + ha="center", + fontsize=5, + color="#333", + ) + + +def _save_montage( + out_path: str, + shapes: List[TileShape], + render: Callable[..., None], + suptitle: str, + footnote: str, + *, + figsize: Tuple[float, float] = (28, 16), + dpi: int = 140, +) -> None: + fig, axes = plt.subplots(2, 4, figsize=figsize, dpi=dpi) + fig.suptitle(suptitle, fontsize=14, y=0.995) + for ax, spec in zip(axes.ravel(), shapes): + render(ax, spec, title_fontsize=8.5, label_fs=5.5, show_footer=False) + fig.text(0.5, 0.012, footnote, ha="center", fontsize=9, color="#222") + fig.subplots_adjust(left=0.03, right=0.97, top=0.93, bottom=0.06, hspace=0.38, wspace=0.22) + fig.savefig(out_path, bbox_inches="tight") + plt.close(fig) + + +def main(argv: Sequence[str] | None = None) -> int: + p = argparse.ArgumentParser(description="Plot 16 B tile vector datapath montages (4 PNGs).") + p.add_argument( + "-o", + "--out-dir", + default=os.path.join(os.path.dirname(__file__), "tile16_figures"), + help="Directory for PNG output (created if missing).", + ) + args = p.parse_args(list(argv) if argv is not None else None) + + os.makedirs(args.out_dir, exist_ok=True) + shapes = canonical_shapes() + + _save_montage( + os.path.join(args.out_dir, "elementwise_all.png"), + shapes, + render_elementwise, + suptitle=f"Element-wise — 8 tile shapes ({TILE_BYTES} B holding register each)", + footnote=( + "▭ = element (width ∝ E); all A contiguous, then all B; ○ = 2-input unit; " + "crossed bends on operand paths (cf. vector4k dual-port strip buffers)." + ), + ) + _save_montage( + os.path.join(args.out_dir, "reduce_all.png"), + shapes, + render_reduce, + suptitle=f"Reduce (representative row / fiber) — 8 tile shapes ({TILE_BYTES} B tile)", + footnote=( + "Per subplot: A block then B block (▭ width ∝ E); lane i pairing into ○, then reduction tree to Acc." + ), + ) + _save_montage( + os.path.join(args.out_dir, "expand_all.png"), + shapes, + render_expand, + suptitle=f"Expand / fanout — 8 tile shapes ({TILE_BYTES} B tile)", + footnote=( + "A block (v) then B block (▭ width ∝ E); v fans out; leaf ○ combines fanout with each B lane." + ), + ) + _save_montage( + os.path.join(args.out_dir, "mergesort_all.png"), + shapes, + render_mergesort, + suptitle=f"Mergesort (compare–swap) — 8 tile shapes ({TILE_BYTES} B tile)", + footnote=( + "Type 4: A|B keys (▭ ∝ E); multi-stage compare–swap (2-in/2-out ○); straight wires only, " + "odd–even transposition layers (schematic multistage C&S, not a full minimal merge depth proof)." + ), + ) + + print(f"Wrote 4 PNG montages to {args.out_dir}") + return 0 + + +if __name__ == "__main__": + raise SystemExit(main()) diff --git a/designs/outerCube/tile16_figures/elementwise_all.png b/designs/outerCube/tile16_figures/elementwise_all.png new file mode 100644 index 0000000000000000000000000000000000000000..2ad21101dcd4aaa76d9770554025619de6e3e6b8 GIT binary patch literal 480089 zcmeFZc~q14)-R5wjmH+nYO5d!RsFa? zQ$S_`sS1)X3L!E^#Slz@$Pi*k2zP&J&-=b--TUY7kKbMEy4F#k91@;qfA{`O`-wSk zYP|W|UEhj`h-^N6>KAhnku5hxME=$AFARL;)*JI)_(#Y8#3g?VZx{cdE53M!#~ArJstCUM{(IHm*w1y;V?g80+qq7Z&~w;Wc#(Sgz<$uIg;#6yW&n3d<8H5-+%I*Opd-e^xvPOkDfmf6Zz&pzBGLpbMrs{fBq7pM(}?B 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