compile_cycle_aware should support reset port naming/polarity customization

[HLEE80]

Issue Draft: reset_polarity / reset port customization in compile_cycle_aware

Title

compile_cycle_aware should support reset port naming/polarity customization (e.g. rst_n, active-low)

Background

In current PyCircuit v5 flow, compile_cycle_aware creates a clock domain through m.create_domain(...), and the default reset port behavior is effectively fixed to a top-level reset named rst (active-high assertion semantics internally).

For integration into existing RTL specs that require an active-low top-level reset interface (commonly rst_n), this causes interface mismatch at generated RTL boundaries.

Problem

At the moment, users can set domain_name, but cannot configure:

1. reset port name (rst vs rst_n)
2. reset polarity at top-level interface (active-high vs active-low)

This forces downstream projects to add post-processing wrappers/rewrites on generated RTL to match project interface contracts.

Reproduction

1. Build any cycle-aware design with:

compile_cycle_aware(build_fn, name="my_top", eager=True)

2. Emit RTL via pycc flow.
3. Observe generated top-level reset IO includes rst and assumes active-high reset integration semantics.

Expected Behavior

Users should be able to configure reset interface directly in frontend compile flow, for example:

• reset port name: rst_n
• reset polarity: active-low

without requiring manual RTL post-processing.

Proposed API Direction

Add optional reset interface controls in v5 compile/domain creation APIs, e.g.:

compile_cycle_aware(
    build_fn,
    name="my_top",
    domain_name="clk",
    reset_name="rst_n",
    reset_polarity="active_low",  # or enum/bool equivalent
    eager=True,
)

or expose equivalent knobs in create_domain(...) and pass through from compile_cycle_aware(...).

Compatibility Considerations

• Keep current defaults unchanged (rst, active-high) for backward compatibility.
• New arguments should be optional and non-breaking.
• Existing testbench helpers (tb.reset(...)) should work with custom reset port names.

Why This Matters

• Many IP/specs mandate active-low reset top-level interfaces.
• Avoids fragile post-generation RTL rewriting.
• Improves interoperability with existing RTL integration environments.

[zhoubot]

Implementation review for PR #62:

• Reviewed the reset API, frontend metadata, and C++/Verilog emitter changes.
• The public API direction matches the issue: compile_cycle_aware(...) and create_domain(...) now accept reset_name and reset_polarity, with defaults preserving the existing rst / active-high behavior.
• The frontend keeps the internal reset contract active-high by recording pyc.reset_polarities metadata, while the emitters introduce an internal active-high alias for active-low reset ports before sequential primitives consume reset.
• The compatibility path for the older reset_active_high boolean is retained, which is useful for migration.

Review verdict: implementation direction looks sound, but I would add one regression before calling this fully merge-ready: an emitter-level test or golden check that active-low rst_n produces the expected inversion in generated Verilog and C++ and that a register primitive consumes the internal active-high reset, not the external active-low port directly. The current tests assert the frontend MLIR metadata and reset_active op, but the user-visible promise in this issue includes backend C++/Verilog polarity conversion.