memory: A4000 motherboard expansion space + CPU-slot accelerator RAM

copperline.example.toml

@@ -191,9 +191,19 @@ slow = "512K"
 # probe rather than autoconfig. Needs a Ramsey memory controller (the
 # A3000/A4000 profiles fit one, and 4M of this RAM, by default) and a
 # 32-bit CPU. Must fill whole Ramsey banks: 1M-4M in 1M steps, or
-# 8M/12M/16M. Set to 0 to remove it.
+# 8M/12M/16M. On the A4000 (Ramsey-07), sizes beyond 16M fill the
+# $04000000-$06FFFFFF motherboard RAM expansion space in 4M steps up
+# to 64M. Set to 0 to remove it.
 # motherboard = "16M"
 
+# CPU-slot (accelerator) fast RAM: 32-bit local RAM starting at $08000000
+# and growing upward through the coprocessor-slot space, up to 128M
+# (ending at $10000000, where Zorro III space begins). Sized by
+# Kickstart's own probe rather than autoconfig; the big-box Kickstarts
+# scan for it, elsewhere guest software has to AddMem it. Needs a CPU
+# with a 32-bit address bus. Any whole number of megabytes.
+# accelerator = "64M"
+
 
 # Additional Zorro boards described by TOML metadata files, configured
 # in file order after the built-in [memory] fast/z3 boards. The metadata

docs/guide/configuration.md

@@ -43,7 +43,8 @@ range checks as the equivalent TOML fields:
 | `--chip SIZE` | `[memory] chip` | `512K`, `1M`, `2M`, ... |
 | `--fast SIZE` | `[memory] fast` | `0`, `1M`, `4M`, `8M`, ... |
 | `--slow SIZE` | `[memory] slow` | `0`, up to `512K` |
-| `--motherboard SIZE` | `[memory] motherboard` | Ramsey RAM (A3000/A4000): `0`, `1M`..`4M`, `8M`, `12M`, `16M` |
+| `--motherboard SIZE` | `[memory] motherboard` | Ramsey RAM (A3000/A4000): `0`, `1M`..`4M`, `8M`, `12M`, `16M`; A4000 up to `64M` |
+| `--accelerator SIZE` | `[memory] accelerator` | CPU-slot RAM at `$08000000` (32-bit CPUs): `0` to `128M` |
 | `--floppy-drives COUNT` | `[floppy] drives` | `1` to `4` wired drives (`DF0:` plus external drives) |
 | `--floppy-speed PERCENT` | `[floppy] speed` | `100` (real), `200`, `400`, `800`, or `0` (turbo) |
 | `--joystick MODE` | `[input] joystick` | `gamepad` (default), `keyboard` |
@@ -180,7 +181,10 @@ drives), and setting the flag explicitly wins in either direction. The ROM
 file itself is never modified.
 
 Both profiles fit their stock 4M of Ramsey-controlled motherboard fast RAM;
-`[memory] motherboard` resizes it up to 16M (see the `[memory]` section).
+`[memory] motherboard` resizes it up to 16M, and on the A4000 up to 64M
+via the motherboard RAM expansion space (see the `[memory]` section).
+`[memory] accelerator` adds CPU-slot RAM at `$08000000` on any 32-bit
+machine.
 
 `mem_controller` is normally left to the profile. It is broken out because
 Ramsey's registers collide with nothing else, so it can be fitted to
@@ -315,7 +319,8 @@ clock_mhz = 14.0    # optional; defaults to the model's stock speed
 chip = "512K"        # OCS max 512K; ECS/AGA max 2M
 fast = "0"           # Zorro II fast RAM at $200000: 64K..8M board sizes
 slow = "512K"        # A500 trapdoor RAM at $C00000: 0 or up to 512K
-motherboard = "0"    # Ramsey motherboard RAM (A3000/A4000): up to 16M
+motherboard = "0"    # Ramsey motherboard RAM (A3000/A4000): up to 16M (A4000: 64M)
+accelerator = "0"    # CPU-slot RAM at $08000000 (32-bit CPUs): up to 128M
 z3   = "0"           # Zorro III RAM (needs a 32-bit CPU): 64K..1G, power of two
 ```
 
@@ -335,7 +340,16 @@ plain byte counts, and must be multiples of 4 KiB.
   involved. It needs a Ramsey (`[machine] mem_controller`, fitted by the
   A3000/A4000 profiles, which also fit their stock 4M of this RAM by
   default) and a 32-bit CPU, and must fill whole Ramsey banks: 1M-4M in
-  1M steps, or 8M, 12M, 16M. Set `motherboard = "0"` to remove it.
+  1M steps, or 8M, 12M, 16M. On the A4000 (Ramsey-07), sizes beyond 16M
+  keep growing downward into the `$04000000`-`$06FFFFFF` motherboard RAM
+  expansion space, in 4M steps up to 64M (which reaches `$04000000`).
+  Set `motherboard = "0"` to remove it.
+- **Accelerator RAM** is CPU-slot local memory: it starts at `$08000000`
+  and grows upward through the coprocessor-slot expansion space, up to
+  128M (ending at `$10000000`, where Zorro III space begins). This is the
+  RAM an accelerator/CPU board carries, so it needs a 32-bit CPU but no
+  particular machine profile; any whole number of megabytes fits.
+  Kickstart sizes it with its own probe, like the motherboard bank.
 - **Z3 RAM** requires a 68020/68030/68040/68060 (a 24-bit bus cannot reach it);
   Kickstart assigns its base address, usually `$40000000`.
 

docs/internals/peripherals.md

@@ -45,6 +45,17 @@ geometry bits are seeded to describe DRAM parts matching the fitted RAM
 size so sizing probes agree with the RAM that answers. Only the register
 file lives in `ramsey.rs`; the RAM bank itself is `memory::Memory::mb_ram`.
 
+Beyond Ramsey's four banks the big-box memory map reserves
+`$04000000`-`$06FFFFFF` for motherboard RAM expansion; on the A4000
+profile the bank keeps growing downward through it, up to 64 MiB at
+`$04000000`, still sized by Kickstart's top-down probe (the control
+register keeps describing the fully populated 1Mx4 geometry -- it has
+no way to say more). The complementary `[memory] accelerator` bank
+models CPU-slot local RAM: it starts at `$08000000` and grows upward
+through the coprocessor-slot space, up to 128 MiB at `$10000000` where
+Zorro III space begins, gated only on a 32-bit CPU
+(`memory::Memory::accel_ram`).
+
 ## Gayle IDE (`gayle.rs`)
 
 A600/A1200 machines get the Gayle gate array: the ID register at

src/a2065.rs

@@ -556,6 +556,7 @@ mod tests {
             chip_ram: vec![0u8; 0x100],
             slow_ram: Vec::new(),
             mb_ram: Vec::new(),
+            accel_ram: Vec::new(),
             rom: Vec::new(),
             overlay: false,
             zorro: crate::zorro::ZorroChain::default(),

src/a2091.rs

@@ -482,6 +482,7 @@ mod tests {
             chip_ram: vec![0u8; 512 * 1024],
             slow_ram: Vec::new(),
             mb_ram: Vec::new(),
+            accel_ram: Vec::new(),
             rom: Vec::new(),
             overlay: false,
             zorro: ZorroChain::default(),

src/a4091.rs

@@ -1009,6 +1009,7 @@ mod tests {
             chip_ram: vec![0u8; 512 * 1024],
             slow_ram: Vec::new(),
             mb_ram: Vec::new(),
+            accel_ram: Vec::new(),
             rom: Vec::new(),
             overlay: false,
             zorro: ZorroChain::default(),

src/bus.rs

@@ -5330,8 +5330,8 @@ impl Bus {
     }
 
     /// The writable RAM regions a memory hunt should scan: chip RAM,
-    /// slow/ranger RAM, motherboard fast RAM, and configured Zorro RAM
-    /// boards, as (base, length) pairs.
+    /// slow/ranger RAM, motherboard fast RAM, accelerator (CPU-slot) fast
+    /// RAM, and configured Zorro RAM boards, as (base, length) pairs.
     pub fn writable_ram_regions(&self) -> Vec<(u32, u32)> {
         let mut regions = Vec::new();
         if !self.mem.chip_ram.is_empty() {
@@ -5349,15 +5349,21 @@ impl Bus {
         if !self.mem.mb_ram.is_empty() {
             regions.push((self.mem.mb_ram_base() as u32, self.mem.mb_ram.len() as u32));
         }
+        if !self.mem.accel_ram.is_empty() {
+            regions.push((
+                crate::memory::ACCEL_RAM_BASE as u32,
+                self.mem.accel_ram.len() as u32,
+            ));
+        }
         regions.extend(self.mem.zorro.ram_regions());
         regions
     }
 
     /// Read a 16-bit big-endian word from whichever RAM/ROM region maps
-    /// `addr` (chip, fast, slow, motherboard, or ROM), for the debugger's
-    /// memory dumps. Returns 0 for unmapped addresses.
+    /// `addr` (chip, fast, slow, motherboard, accelerator, or ROM), for the
+    /// debugger's memory dumps. Returns 0 for unmapped addresses.
     pub fn peek_word_any(&self, addr: u32) -> u16 {
-        use crate::memory::{CHIP_RAM_BASE, ROM_BASE, SLOW_RAM_BASE};
+        use crate::memory::{ACCEL_RAM_BASE, CHIP_RAM_BASE, ROM_BASE, SLOW_RAM_BASE};
         if let Some((board, off)) = self.mem.zorro.region_at(addr, 2) {
             let ram = self.mem.zorro.board_ram(board);
             return ((ram[off] as u16) << 8) | ram[off + 1] as u16;
@@ -5372,10 +5378,11 @@ impl Bus {
                 .unwrap_or(0);
         }
         let a = addr as usize;
-        let regions: [(usize, &[u8]); 5] = [
+        let regions: [(usize, &[u8]); 6] = [
             (CHIP_RAM_BASE as usize, &self.mem.chip_ram),
             (SLOW_RAM_BASE as usize, &self.mem.slow_ram),
             (self.mem.mb_ram_base() as usize, &self.mem.mb_ram),
+            (ACCEL_RAM_BASE as usize, &self.mem.accel_ram),
             (ROM_BASE as usize, &self.mem.rom),
             (self.mem.extended_rom_base as usize, &self.mem.extended_rom),
         ];

src/bus/tests.rs

@@ -216,6 +216,7 @@ fn empty_bus_with_chip_ram(chip_ram_bytes: usize) -> Bus {
             chip_ram: vec![0; chip_ram_bytes],
             slow_ram: Vec::new(),
             mb_ram: Vec::new(),
+            accel_ram: Vec::new(),
             rom: vec![0; 512 * 1024],
             overlay: true,
             zorro: crate::zorro::ZorroChain::default(),
@@ -236,6 +237,7 @@ fn empty_bus_with_collect_audio() -> (Bus, SharedFrames) {
             chip_ram: vec![0; 512 * 1024],
             slow_ram: Vec::new(),
             mb_ram: Vec::new(),
+            accel_ram: Vec::new(),
             rom: vec![0; 512 * 1024],
             overlay: true,
             zorro: crate::zorro::ZorroChain::default(),

src/cdtv.rs

@@ -1340,6 +1340,7 @@ mod tests {
             chip_ram: vec![0u8; chip_bytes],
             slow_ram: Vec::new(),
             mb_ram: Vec::new(),
+            accel_ram: Vec::new(),
             rom: Vec::new(),
             overlay: false,
             zorro: crate::zorro::ZorroChain::default(),