This repository is a fork of the original Digital-Logic-Sim project by Sebastian Lague.
The purpose of this fork is to explore a small, localized enhancement focused on:
- Deterministic startup behavior
- Optional global custom chip configuration
- Improved reproducibility and simulation control
The goal is to validate these changes locally in a constrained, non-invasive way before proposing a focused upstream contribution for consideration by the original project maintainer.
This fork is not intended to diverge materially from upstream, introduce incompatible behavior, or evolve independently as a long-lived variant. Any changes are kept deliberately narrow and isolated to facilitate review and potential incorporation upstream.
Until an upstream contribution is accepted (if at all), this fork should be treated as an experimental validation branch rather than a separate distribution.