From 2a34625e7fa05335781924e8881a6da90276dcdf Mon Sep 17 00:00:00 2001 From: Handell Desulme Date: Tue, 18 Aug 2020 01:10:23 -0400 Subject: [PATCH 1/4] completes day 1 mvp --- ls8/cpu.py | 36 ++++++++++++++++++++++++++++++++++-- 1 file changed, 34 insertions(+), 2 deletions(-) diff --git a/ls8/cpu.py b/ls8/cpu.py index 9a307496e..0d552f6fa 100644 --- a/ls8/cpu.py +++ b/ls8/cpu.py @@ -7,7 +7,9 @@ class CPU: def __init__(self): """Construct a new CPU.""" - pass + self.pc = 0 + self.ram = [0] * 32 # 32 8-bit addresses + self.reg = [0] * 8 # 8 general-purpose registers def load(self): """Load a program into memory.""" @@ -60,6 +62,36 @@ def trace(self): print() + def ram_read(self, MAR): + return self.ram[MAR] + + def ram_write(self, MAR, MDR): + self.ram[MAR] = MDR + def run(self): """Run the CPU.""" - pass + running = True + while running: + operand_a = self.ram_read(self.pc+1) + operand_b = self.ram_read(self.pc+2) + IR = self.ram_read(self.pc) + if IR == 0b10000010: #LDI + self.reg[operand_a] = operand_b + op_size = 2 + elif IR == 0b01000111: #PRN + print(self.reg[operand_a]) + op_size = 1 + elif IR == 0b00000001: #HLT + running = self.HLT() + + self.pc += op_size + 1 + + def HLT(self): + return False + + +cpu = CPU() + +cpu.load() +cpu.run() + From 726ced443613325062bc196e886ba6dd6110241f Mon Sep 17 00:00:00 2001 From: Handell Desulme Date: Tue, 18 Aug 2020 16:01:24 -0400 Subject: [PATCH 2/4] adds file reading --- ls8/cpu.py | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/ls8/cpu.py b/ls8/cpu.py index 0d552f6fa..c09566cf1 100644 --- a/ls8/cpu.py +++ b/ls8/cpu.py @@ -11,13 +11,22 @@ def __init__(self): self.ram = [0] * 32 # 32 8-bit addresses self.reg = [0] * 8 # 8 general-purpose registers - def load(self): + def load(self, filename): """Load a program into memory.""" address = 0 # For now, we've just hardcoded a program: + with open (filename) as f: + for line in f: + comment_split = line.split("#") + bits = comment_split[0].strip() + if bits == '': + continue + decimal = int(bits, 2) + print(bits) + program = [ # From print8.ls8 0b10000010, # LDI R0,8 @@ -92,6 +101,6 @@ def HLT(self): cpu = CPU() -cpu.load() +cpu.load("./ls8/examples/print8.ls8") cpu.run() From 55fa38cf816f3dcce3644781091ef2edc38bf87a Mon Sep 17 00:00:00 2001 From: Handell Desulme Date: Tue, 18 Aug 2020 17:58:22 -0400 Subject: [PATCH 3/4] completes mvp --- ls8/cpu.py | 39 ++++++++++++++++----------------------- 1 file changed, 16 insertions(+), 23 deletions(-) diff --git a/ls8/cpu.py b/ls8/cpu.py index c09566cf1..1d17b45a6 100644 --- a/ls8/cpu.py +++ b/ls8/cpu.py @@ -19,27 +19,14 @@ def load(self, filename): # For now, we've just hardcoded a program: with open (filename) as f: - for line in f: - comment_split = line.split("#") - bits = comment_split[0].strip() - if bits == '': + for instruction in f: + comment_split = instruction.split("#") + byte = comment_split[0].strip() + if byte == '': continue - decimal = int(bits, 2) - print(bits) - - program = [ - # From print8.ls8 - 0b10000010, # LDI R0,8 - 0b00000000, - 0b00001000, - 0b01000111, # PRN R0 - 0b00000000, - 0b00000001, # HLT - ] - - for instruction in program: - self.ram[address] = instruction - address += 1 + decimal = int(byte, 2) + self.ram[address] = decimal + address += 1 def alu(self, op, reg_a, reg_b): @@ -90,6 +77,9 @@ def run(self): elif IR == 0b01000111: #PRN print(self.reg[operand_a]) op_size = 1 + elif IR == 0b10100010: #MUL + self.reg[operand_a] *= self.reg[operand_b] + op_size = 2 elif IR == 0b00000001: #HLT running = self.HLT() @@ -99,8 +89,11 @@ def HLT(self): return False -cpu = CPU() +cpu1 = CPU() +cpu2 = CPU() -cpu.load("./ls8/examples/print8.ls8") -cpu.run() +cpu1.load("./ls8/examples/print8.ls8") +cpu1.run() +cpu2.load("./ls8/examples/mult.ls8") +cpu2.run() From 4c3c1d03fb25d0a38d55556a504828dd7d4173a9 Mon Sep 17 00:00:00 2001 From: Handell Desulme Date: Wed, 19 Aug 2020 19:13:15 -0400 Subject: [PATCH 4/4] completes day 3 mvp --- ls8/cpu.py | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/ls8/cpu.py b/ls8/cpu.py index 1d17b45a6..b091ed2be 100644 --- a/ls8/cpu.py +++ b/ls8/cpu.py @@ -8,7 +8,8 @@ class CPU: def __init__(self): """Construct a new CPU.""" self.pc = 0 - self.ram = [0] * 32 # 32 8-bit addresses + self.sp = 7 + self.ram = [0] * 256 # 256 8-bit addresses self.reg = [0] * 8 # 8 general-purpose registers def load(self, filename): @@ -67,6 +68,7 @@ def ram_write(self, MAR, MDR): def run(self): """Run the CPU.""" running = True + self.reg[self.sp] = 0xF4 #SP = 244 while running: operand_a = self.ram_read(self.pc+1) operand_b = self.ram_read(self.pc+2) @@ -80,6 +82,14 @@ def run(self): elif IR == 0b10100010: #MUL self.reg[operand_a] *= self.reg[operand_b] op_size = 2 + elif IR == 0b01000101: #PUSH + self.reg[self.sp] -= 1 + self.ram_write(self.reg[self.sp], self.reg[operand_a]) + op_size = 1 + elif IR == 0b01000110: #POP + self.reg[operand_a] = self.ram_read(self.reg[self.sp]) + self.reg[self.sp] += 1 + op_size = 1 elif IR == 0b00000001: #HLT running = self.HLT() @@ -91,9 +101,12 @@ def HLT(self): cpu1 = CPU() cpu2 = CPU() +cpu3 = CPU() cpu1.load("./ls8/examples/print8.ls8") cpu1.run() cpu2.load("./ls8/examples/mult.ls8") cpu2.run() +cpu3.load("./ls8/examples/stack.ls8") +cpu3.run()