diff --git a/HDL/source/rtl/vhdl/top.vhd b/HDL/source/rtl/vhdl/top.vhd
index cde3df0..d8eeeb9 100644
--- a/HDL/source/rtl/vhdl/top.vhd
+++ b/HDL/source/rtl/vhdl/top.vhd
@@ -9,11 +9,13 @@
-- Simple test for VGA control
--
-------------------------------------------------------------------------------
+
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
+
entity top is
generic (
RES_TYPE : natural := 1;
@@ -157,6 +159,11 @@ architecture rtl of top is
signal dir_pixel_column : std_logic_vector(10 downto 0);
signal dir_pixel_row : std_logic_vector(10 downto 0);
+ type color_array is array(7 downto 0) of std_logic_vector(23 downto 0);
+ signal colors : color_array := (
+ x"ffffff", x"cccc00", x"00ccff", x"00cc00",
+ x"e600e6", x"ff0000", x"0000ff", x"000000" );
+
begin
-- calculate message lenght from font size
@@ -246,11 +253,17 @@ begin
blue_o => blue_o
);
+
+
-- na osnovu signala iz vga_top modula dir_pixel_column i dir_pixel_row realizovati logiku koja genereise
--dir_red
--dir_green
--dir_blue
-
+
+ dir_red <= colors( conv_integer( dir_pixel_column(10 downto 8) ) )( 23 downto 16 );
+ dir_green <= colors( conv_integer( dir_pixel_column(10 downto 8) ) )( 15 downto 8 );
+ dir_blue <= colors( conv_integer( dir_pixel_column(10 downto 8) ) )( 7 downto 0 );
+
-- koristeci signale realizovati logiku koja pise po TXT_MEM
--char_address
--char_value
diff --git a/HDL/synthesis/lab2/_xmsgs/pn_parser.xmsgs b/HDL/synthesis/lab2/_xmsgs/pn_parser.xmsgs
index 147c65b..2cc1218 100644
--- a/HDL/synthesis/lab2/_xmsgs/pn_parser.xmsgs
+++ b/HDL/synthesis/lab2/_xmsgs/pn_parser.xmsgs
@@ -8,40 +8,7 @@
-Parsing VHDL file "//samba03/nastavni_materijali/lprs2/vezbe/lab2/HDL/source/coregen/char_rom/char_rom_def.vhd" into library work
-
-
-Parsing VHDL file "//samba03/nastavni_materijali/lprs2/vezbe/lab2/HDL/source/coregen/dcm108MHz.vhd" into library work
-
-
-Parsing VHDL file "//samba03/nastavni_materijali/lprs2/vezbe/lab2/HDL/source/coregen/dcm25MHz.vhd" into library work
-
-
-Parsing VHDL file "//samba03/nastavni_materijali/lprs2/vezbe/lab2/HDL/source/coregen/dcm50MHz.vhd" into library work
-
-
-Parsing VHDL file "//samba03/nastavni_materijali/lprs2/vezbe/lab2/HDL/source/coregen/dcm75MHz.vhd" into library work
-
-
-Parsing VHDL file "//samba03/nastavni_materijali/lprs2/vezbe/lab2/HDL/source/rtl/vhdl/char_rom.vhd" into library work
-
-
-Parsing VHDL file "//samba03/nastavni_materijali/lprs2/vezbe/lab2/HDL/source/rtl/vhdl/graphics_mem.vhd" into library work
-
-
-Parsing VHDL file "//samba03/nastavni_materijali/lprs2/vezbe/lab2/HDL/source/rtl/vhdl/text_mem.vhd" into library work
-
-
-Parsing VHDL file "//samba03/nastavni_materijali/lprs2/vezbe/lab2/HDL/source/rtl/vhdl/top.vhd" into library work
-
-
-Parsing VHDL file "//samba03/nastavni_materijali/lprs2/vezbe/lab2/HDL/source/rtl/vhdl/vga.vhd" into library work
-
-
-Parsing VHDL file "//samba03/nastavni_materijali/lprs2/vezbe/lab2/HDL/source/rtl/vhdl/vga_sync.vhd" into library work
-
-
-Parsing VHDL file "//samba03/nastavni_materijali/lprs2/vezbe/lab2/HDL/source/rtl/vhdl/vga_top.vhd" into library work
+Parsing VHDL file "C:/materija/ra170-2013/lprs2/lab2/HDL/source/rtl/vhdl/top.vhd" into library work
diff --git a/HDL/synthesis/lab2/_xmsgs/xst.xmsgs b/HDL/synthesis/lab2/_xmsgs/xst.xmsgs
index 0dc6b4b..a469cc0 100644
--- a/HDL/synthesis/lab2/_xmsgs/xst.xmsgs
+++ b/HDL/synthesis/lab2/_xmsgs/xst.xmsgs
@@ -5,55 +5,43 @@
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
-"\\samba03\nastavni_materijali\lprs2\vezbe\lab2\HDL\source\rtl\vhdl\top.vhd" Line 163: Assignment to message_lenght ignored, since the identifier is never used
+"C:\materija\ra170-2013\lprs2\lab2\HDL\source\rtl\vhdl\top.vhd" Line 170: Assignment to message_lenght ignored, since the identifier is never used
-"\\samba03\nastavni_materijali\lprs2\vezbe\lab2\HDL\source\rtl\vhdl\top.vhd" Line 168: Assignment to graphics_lenght ignored, since the identifier is never used
+"C:\materija\ra170-2013\lprs2\lab2\HDL\source\rtl\vhdl\top.vhd" Line 175: Assignment to graphics_lenght ignored, since the identifier is never used
-"\\samba03\nastavni_materijali\lprs2\vezbe\lab2\HDL\source\rtl\vhdl\top.vhd" Line 106: <oddr2> remains a black-box since it has no binding entity.
+"C:\materija\ra170-2013\lprs2\lab2\HDL\source\rtl\vhdl\top.vhd" Line 108: <oddr2> remains a black-box since it has no binding entity.
-"\\samba03\nastavni_materijali\lprs2\vezbe\lab2\HDL\source\rtl\vhdl\vga.vhd" Line 123: <srl16> remains a black-box since it has no binding entity.
+"C:\materija\ra170-2013\lprs2\lab2\HDL\source\rtl\vhdl\vga.vhd" Line 123: <srl16> remains a black-box since it has no binding entity.
-"\\samba03\nastavni_materijali\lprs2\vezbe\lab2\HDL\source\rtl\vhdl\vga_top.vhd" Line 301: Assignment to grid_size ignored, since the identifier is never used
+"C:\materija\ra170-2013\lprs2\lab2\HDL\source\rtl\vhdl\vga_top.vhd" Line 301: Assignment to grid_size ignored, since the identifier is never used
-"\\samba03\nastavni_materijali\lprs2\vezbe\lab2\HDL\source\rtl\vhdl\top.vhd" Line 142: Net <char_we> does not have a driver.
+"C:\materija\ra170-2013\lprs2\lab2\HDL\source\rtl\vhdl\top.vhd" Line 144: Net <char_we> does not have a driver.
-"\\samba03\nastavni_materijali\lprs2\vezbe\lab2\HDL\source\rtl\vhdl\top.vhd" Line 143: Net <char_address[13]> does not have a driver.
+"C:\materija\ra170-2013\lprs2\lab2\HDL\source\rtl\vhdl\top.vhd" Line 145: Net <char_address[13]> does not have a driver.
-"\\samba03\nastavni_materijali\lprs2\vezbe\lab2\HDL\source\rtl\vhdl\top.vhd" Line 144: Net <char_value[5]> does not have a driver.
+"C:\materija\ra170-2013\lprs2\lab2\HDL\source\rtl\vhdl\top.vhd" Line 146: Net <char_value[5]> does not have a driver.
-"\\samba03\nastavni_materijali\lprs2\vezbe\lab2\HDL\source\rtl\vhdl\top.vhd" Line 146: Net <pixel_address[19]> does not have a driver.
+"C:\materija\ra170-2013\lprs2\lab2\HDL\source\rtl\vhdl\top.vhd" Line 148: Net <pixel_address[19]> does not have a driver.
-"\\samba03\nastavni_materijali\lprs2\vezbe\lab2\HDL\source\rtl\vhdl\top.vhd" Line 147: Net <pixel_value[31]> does not have a driver.
+"C:\materija\ra170-2013\lprs2\lab2\HDL\source\rtl\vhdl\top.vhd" Line 149: Net <pixel_value[31]> does not have a driver.
-"\\samba03\nastavni_materijali\lprs2\vezbe\lab2\HDL\source\rtl\vhdl\top.vhd" Line 148: Net <pixel_we> does not have a driver.
+"C:\materija\ra170-2013\lprs2\lab2\HDL\source\rtl\vhdl\top.vhd" Line 150: Net <pixel_we> does not have a driver.
-"\\samba03\nastavni_materijali\lprs2\vezbe\lab2\HDL\source\rtl\vhdl\top.vhd" Line 154: Net <dir_red[7]> does not have a driver.
+"C:\materija\ra170-2013\lprs2\lab2\HDL\source\rtl\vhdl\top.vhd" line 206: Output port <dir_pixel_row_o> of the instance <vga_top_i> is unconnected or connected to loadless signal.
-"\\samba03\nastavni_materijali\lprs2\vezbe\lab2\HDL\source\rtl\vhdl\top.vhd" Line 155: Net <dir_green[7]> does not have a driver.
-
-
-"\\samba03\nastavni_materijali\lprs2\vezbe\lab2\HDL\source\rtl\vhdl\top.vhd" Line 156: Net <dir_blue[7]> does not have a driver.
-
-
-"\\samba03\nastavni_materijali\lprs2\vezbe\lab2\HDL\source\rtl\vhdl\top.vhd" line 199: Output port <dir_pixel_column_o> of the instance <vga_top_i> is unconnected or connected to loadless signal.
-
-
-"\\samba03\nastavni_materijali\lprs2\vezbe\lab2\HDL\source\rtl\vhdl\top.vhd" line 199: Output port <dir_pixel_row_o> of the instance <vga_top_i> is unconnected or connected to loadless signal.
-
-
-"\\samba03\nastavni_materijali\lprs2\vezbe\lab2\HDL\source\rtl\vhdl\top.vhd" line 199: Output port <vga_rst_n_o> of the instance <vga_top_i> is unconnected or connected to loadless signal.
+"C:\materija\ra170-2013\lprs2\lab2\HDL\source\rtl\vhdl\top.vhd" line 206: Output port <vga_rst_n_o> of the instance <vga_top_i> is unconnected or connected to loadless signal.
Signal <char_address> is used but never assigned. This sourceless signal will be automatically connected to value GND.
@@ -68,21 +56,15 @@
Signal <pixel_value> is used but never assigned. This sourceless signal will be automatically connected to value GND.
-Signal <dir_red> is used but never assigned. This sourceless signal will be automatically connected to value GND.
-
-
-Signal <dir_green> is used but never assigned. This sourceless signal will be automatically connected to value GND.
-
-
-Signal <dir_blue> is used but never assigned. This sourceless signal will be automatically connected to value GND.
-
-
Signal <char_we> is used but never assigned. This sourceless signal will be automatically connected to value GND.
Signal <pixel_we> is used but never assigned. This sourceless signal will be automatically connected to value GND.
+Signal 'colors', unconnected in block 'top', is tied to its initial value.
+
+
Input <wr_addr_i<13:13>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
@@ -105,152 +87,11 @@
It will be removed from the design.
-FF/Latch <green_r_7> (without init value) has a constant value of 0 in block <vga_sync_i>. This FF/Latch will be trimmed during the optimization process.
-
-
-FF/Latch <green_r_6> (without init value) has a constant value of 0 in block <vga_sync_i>. This FF/Latch will be trimmed during the optimization process.
-
-
-FF/Latch <green_r_5> (without init value) has a constant value of 0 in block <vga_sync_i>. This FF/Latch will be trimmed during the optimization process.
-
-
-FF/Latch <green_r_4> (without init value) has a constant value of 0 in block <vga_sync_i>. This FF/Latch will be trimmed during the optimization process.
-
-
-FF/Latch <green_r_3> (without init value) has a constant value of 0 in block <vga_sync_i>. This FF/Latch will be trimmed during the optimization process.
-
-
-FF/Latch <green_r_2> (without init value) has a constant value of 0 in block <vga_sync_i>. This FF/Latch will be trimmed during the optimization process.
-
-
-FF/Latch <green_r_1> (without init value) has a constant value of 0 in block <vga_sync_i>. This FF/Latch will be trimmed during the optimization process.
-
-
-FF/Latch <green_r_0> (without init value) has a constant value of 0 in block <vga_sync_i>. This FF/Latch will be trimmed during the optimization process.
-
-
-FF/Latch <red_r_7> (without init value) has a constant value of 0 in block <vga_sync_i>. This FF/Latch will be trimmed during the optimization process.
-
-
-FF/Latch <red_r_6> (without init value) has a constant value of 0 in block <vga_sync_i>. This FF/Latch will be trimmed during the optimization process.
-
-
-FF/Latch <red_r_5> (without init value) has a constant value of 0 in block <vga_sync_i>. This FF/Latch will be trimmed during the optimization process.
-
-
-FF/Latch <red_r_4> (without init value) has a constant value of 0 in block <vga_sync_i>. This FF/Latch will be trimmed during the optimization process.
-
-
-FF/Latch <red_r_3> (without init value) has a constant value of 0 in block <vga_sync_i>. This FF/Latch will be trimmed during the optimization process.
-
-
-FF/Latch <red_r_2> (without init value) has a constant value of 0 in block <vga_sync_i>. This FF/Latch will be trimmed during the optimization process.
-
-
-FF/Latch <red_r_1> (without init value) has a constant value of 0 in block <vga_sync_i>. This FF/Latch will be trimmed during the optimization process.
-
-
-FF/Latch <red_r_0> (without init value) has a constant value of 0 in block <vga_sync_i>. This FF/Latch will be trimmed during the optimization process.
-
-
-FF/Latch <blue_r_7> (without init value) has a constant value of 0 in block <vga_sync_i>. This FF/Latch will be trimmed during the optimization process.
-
-
-FF/Latch <blue_r_6> (without init value) has a constant value of 0 in block <vga_sync_i>. This FF/Latch will be trimmed during the optimization process.
-
-
-FF/Latch <blue_r_5> (without init value) has a constant value of 0 in block <vga_sync_i>. This FF/Latch will be trimmed during the optimization process.
-
-
-FF/Latch <blue_r_4> (without init value) has a constant value of 0 in block <vga_sync_i>. This FF/Latch will be trimmed during the optimization process.
-
-
-FF/Latch <blue_r_3> (without init value) has a constant value of 0 in block <vga_sync_i>. This FF/Latch will be trimmed during the optimization process.
-
-
-FF/Latch <blue_r_2> (without init value) has a constant value of 0 in block <vga_sync_i>. This FF/Latch will be trimmed during the optimization process.
-
-
-FF/Latch <blue_r_1> (without init value) has a constant value of 0 in block <vga_sync_i>. This FF/Latch will be trimmed during the optimization process.
-
-
-FF/Latch <blue_r_0> (without init value) has a constant value of 0 in block <vga_sync_i>. This FF/Latch will be trimmed during the optimization process.
-
-
The RAM <Mram_graphics_mem> will be implemented as a BLOCK RAM, absorbing the following register(s):The RAM <Mram_text_mem> will be implemented as a BLOCK RAM, absorbing the following register(s):
-FF/Latch <blue_r_7> (without init value) has a constant value of 0 in block <vga_sync>. This FF/Latch will be trimmed during the optimization process.
-
-
-Due to other FF/Latch trimming, FF/Latch <blue_r_6> (without init value) has a constant value of 0 in block <vga_sync>. This FF/Latch will be trimmed during the optimization process.
-
-
-Due to other FF/Latch trimming, FF/Latch <blue_r_5> (without init value) has a constant value of 0 in block <vga_sync>. This FF/Latch will be trimmed during the optimization process.
-
-
-Due to other FF/Latch trimming, FF/Latch <blue_r_4> (without init value) has a constant value of 0 in block <vga_sync>. This FF/Latch will be trimmed during the optimization process.
-
-
-Due to other FF/Latch trimming, FF/Latch <blue_r_3> (without init value) has a constant value of 0 in block <vga_sync>. This FF/Latch will be trimmed during the optimization process.
-
-
-Due to other FF/Latch trimming, FF/Latch <blue_r_2> (without init value) has a constant value of 0 in block <vga_sync>. This FF/Latch will be trimmed during the optimization process.
-
-
-Due to other FF/Latch trimming, FF/Latch <blue_r_1> (without init value) has a constant value of 0 in block <vga_sync>. This FF/Latch will be trimmed during the optimization process.
-
-
-Due to other FF/Latch trimming, FF/Latch <blue_r_0> (without init value) has a constant value of 0 in block <vga_sync>. This FF/Latch will be trimmed during the optimization process.
-
-
-Due to other FF/Latch trimming, FF/Latch <red_r_7> (without init value) has a constant value of 0 in block <vga_sync>. This FF/Latch will be trimmed during the optimization process.
-
-
-Due to other FF/Latch trimming, FF/Latch <red_r_6> (without init value) has a constant value of 0 in block <vga_sync>. This FF/Latch will be trimmed during the optimization process.
-
-
-Due to other FF/Latch trimming, FF/Latch <red_r_5> (without init value) has a constant value of 0 in block <vga_sync>. This FF/Latch will be trimmed during the optimization process.
-
-
-Due to other FF/Latch trimming, FF/Latch <red_r_4> (without init value) has a constant value of 0 in block <vga_sync>. This FF/Latch will be trimmed during the optimization process.
-
-
-Due to other FF/Latch trimming, FF/Latch <red_r_3> (without init value) has a constant value of 0 in block <vga_sync>. This FF/Latch will be trimmed during the optimization process.
-
-
-Due to other FF/Latch trimming, FF/Latch <red_r_2> (without init value) has a constant value of 0 in block <vga_sync>. This FF/Latch will be trimmed during the optimization process.
-
-
-Due to other FF/Latch trimming, FF/Latch <red_r_1> (without init value) has a constant value of 0 in block <vga_sync>. This FF/Latch will be trimmed during the optimization process.
-
-
-Due to other FF/Latch trimming, FF/Latch <red_r_0> (without init value) has a constant value of 0 in block <vga_sync>. This FF/Latch will be trimmed during the optimization process.
-
-
-Due to other FF/Latch trimming, FF/Latch <green_r_7> (without init value) has a constant value of 0 in block <vga_sync>. This FF/Latch will be trimmed during the optimization process.
-
-
-Due to other FF/Latch trimming, FF/Latch <green_r_6> (without init value) has a constant value of 0 in block <vga_sync>. This FF/Latch will be trimmed during the optimization process.
-
-
-Due to other FF/Latch trimming, FF/Latch <green_r_5> (without init value) has a constant value of 0 in block <vga_sync>. This FF/Latch will be trimmed during the optimization process.
-
-
-Due to other FF/Latch trimming, FF/Latch <green_r_4> (without init value) has a constant value of 0 in block <vga_sync>. This FF/Latch will be trimmed during the optimization process.
-
-
-Due to other FF/Latch trimming, FF/Latch <green_r_3> (without init value) has a constant value of 0 in block <vga_sync>. This FF/Latch will be trimmed during the optimization process.
-
-
-Due to other FF/Latch trimming, FF/Latch <green_r_2> (without init value) has a constant value of 0 in block <vga_sync>. This FF/Latch will be trimmed during the optimization process.
-
-
-Due to other FF/Latch trimming, FF/Latch <green_r_1> (without init value) has a constant value of 0 in block <vga_sync>. This FF/Latch will be trimmed during the optimization process.
-
-
-Due to other FF/Latch trimming, FF/Latch <green_r_0> (without init value) has a constant value of 0 in block <vga_sync>. This FF/Latch will be trimmed during the optimization process.
+HDL ADVISOR - The RAM <Mram_colors> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
Node <vga_top_i/Maddsub_n0100> of sequential type is unconnected in block <top>.
@@ -364,5 +205,35 @@ It will be removed from the design.
FF/Latch <vga_top_i/vga_i/vga_sync_i/v_count_r_10> (without init value) has a constant value of 0 in block <top>. This FF/Latch will be trimmed during the optimization process.
+FF/Latch <vga_top_i/vga_i/vga_sync_i/green_r_5> (without init value) has a constant value of 0 in block <top>. This FF/Latch will be trimmed during the optimization process.
+
+
+FF/Latch <vga_top_i/vga_i/vga_sync_i/green_r_4> (without init value) has a constant value of 0 in block <top>. This FF/Latch will be trimmed during the optimization process.
+
+
+FF/Latch <vga_top_i/vga_i/vga_sync_i/green_r_1> (without init value) has a constant value of 0 in block <top>. This FF/Latch will be trimmed during the optimization process.
+
+
+FF/Latch <vga_top_i/vga_i/vga_sync_i/green_r_0> (without init value) has a constant value of 0 in block <top>. This FF/Latch will be trimmed during the optimization process.
+
+
+Due to other FF/Latch trimming, FF/Latch <vga_top_i/vga_i/vga_sync_i/green_r_7> (without init value) has a constant value of 0 in block <top>. This FF/Latch will be trimmed during the optimization process.
+
+
+Due to other FF/Latch trimming, FF/Latch <vga_top_i/vga_i/vga_sync_i/green_r_6> (without init value) has a constant value of 0 in block <top>. This FF/Latch will be trimmed during the optimization process.
+
+
+Due to other FF/Latch trimming, FF/Latch <vga_top_i/vga_i/vga_sync_i/green_r_3> (without init value) has a constant value of 0 in block <top>. This FF/Latch will be trimmed during the optimization process.
+
+
+Due to other FF/Latch trimming, FF/Latch <vga_top_i/vga_i/vga_sync_i/green_r_2> (without init value) has a constant value of 0 in block <top>. This FF/Latch will be trimmed during the optimization process.
+
+
+The FF/Latch <vga_top_i/vga_i/vga_sync_i/blue_r_7> in Unit <top> is equivalent to the following 7 FFs/Latches, which will be removed : <vga_top_i/vga_i/vga_sync_i/blue_r_6> <vga_top_i/vga_i/vga_sync_i/blue_r_5> <vga_top_i/vga_i/vga_sync_i/blue_r_4> <vga_top_i/vga_i/vga_sync_i/blue_r_3> <vga_top_i/vga_i/vga_sync_i/blue_r_2> <vga_top_i/vga_i/vga_sync_i/blue_r_1> <vga_top_i/vga_i/vga_sync_i/blue_r_0>
+
+
+The FF/Latch <vga_top_i/vga_i/vga_sync_i/red_r_7> in Unit <top> is equivalent to the following 7 FFs/Latches, which will be removed : <vga_top_i/vga_i/vga_sync_i/red_r_6> <vga_top_i/vga_i/vga_sync_i/red_r_5> <vga_top_i/vga_i/vga_sync_i/red_r_4> <vga_top_i/vga_i/vga_sync_i/red_r_3> <vga_top_i/vga_i/vga_sync_i/red_r_2> <vga_top_i/vga_i/vga_sync_i/red_r_1> <vga_top_i/vga_i/vga_sync_i/red_r_0>
+
+
diff --git a/HDL/synthesis/lab2/iseconfig/top.xreport b/HDL/synthesis/lab2/iseconfig/top.xreport
index 4204406..fd7d177 100644
--- a/HDL/synthesis/lab2/iseconfig/top.xreport
+++ b/HDL/synthesis/lab2/iseconfig/top.xreport
@@ -1,11 +1,11 @@
- 2016-02-16T15:42:35
+ 2016-03-14T17:27:52top2014-03-20T11:47:08
- //samba03/nastavni_materijali/lprs2/vezbe/lab2/HDL/synthesis/lab2/iseconfig/top.xreport
- //samba03/nastavni_materijali/lprs2/vezbe/lab2/HDL/synthesis/lab2\
+ C:/materija/ra170-2013/lprs2/lab2/HDL/synthesis/lab2/iseconfig/top.xreport
+ C:/materija/ra170-2013/lprs2/lab2/HDL/synthesis/lab2\2014-03-10T14:57:35false
diff --git a/HDL/synthesis/lab2/lab2.gise b/HDL/synthesis/lab2/lab2.gise
index 4e54d8c..a9589a4 100644
--- a/HDL/synthesis/lab2/lab2.gise
+++ b/HDL/synthesis/lab2/lab2.gise
@@ -22,19 +22,55 @@
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diff --git a/HDL/synthesis/lab2/par_usage_statistics.html b/HDL/synthesis/lab2/par_usage_statistics.html
index eb8fd43..5d8acf0 100644
--- a/HDL/synthesis/lab2/par_usage_statistics.html
+++ b/HDL/synthesis/lab2/par_usage_statistics.html
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