README

The steps to be followed to simulate a Verilog/VHDL design with savant/tyvis/Warped2 are:

1) SAVANT Parser/Code generator is necessary to generate TyVIS compliant
   C++. It can be downloaded from https://github.com/CastMi/savant

2) Download Warped2, from https://github.com/CastMi/warped2

3) Refer to the installation notes/requirements to install SAVANT from the github repository. 

4) Having installed Savant, invoke scram to publish the TyVIS compliant C++ code.
    Command to code-generate is
	    scram --publish-cc design_file.vhd

5) The Equivalent C++ will be generated in work.savant_lib/ directory.

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