diff --git a/.gitignore b/.gitignore index c8560a8..a75528c 100644 --- a/.gitignore +++ b/.gitignore @@ -30,4 +30,5 @@ support/ *.xz venv/ /products_path -/products \ No newline at end of file +/products +/dist diff --git a/Readme.md b/Readme.md index 355700d..83ccf3f 100644 --- a/Readme.md +++ b/Readme.md @@ -1,11 +1,8 @@

DFFRAM Compiler

-

- Open in Google Colab -

License: Apache 2.0 - CI Status - Invite to the Skywater PDK Slack + CI Status + Invite to FOSSi Chat Code Style: Black

@@ -15,10 +12,6 @@ Standard Cell Library based Memory Compiler using DFF/Latch cells. See [this document](./docs/Usage.md). -You can try the -[Google Colaboratory](https://colab.research.google.com/github/Cloud-V/DFFRAM/blob/main/dffram.ipynb), -but it is a bit out-of-date at this point. - ## Platform Support Status | Configured Platform | Working | Silicon-proven\* | @@ -76,7 +69,10 @@ blocks are as follows: Currently, the can compiler generate the layout of the following configurations: -> 1RW1R variants are temporarily disabled due to a bug. +> We currently do not recommend the use of 1RW1R. See this discussion for more +> info: +> +> https://github.com/AUCOHL/DFFRAM/issues/198 * RAM * 32 words with byte write enable (1RW and 1RW1R). @@ -88,9 +84,6 @@ Currently, the can compiler generate the layout of the following configurations: * Register File * 32 x 32-bit words (2R1W) -The [`OpenLane/`](./OpenLane) folder will contain good known OpenLane -configurations to build DFFRAM different macros. - ## File Structure * `.github` contains files for GitHub actions. @@ -116,8 +109,8 @@ using different means. Size1 OpenRAM2 DFFRAM Compiler - DFFRAM/OpenLane - RTL/OpenLane + DFFRAM + OpenROAD Placer + Memory RTL with OpenLane Dim WxH (μm) Bit Density (bits/mm2) diff --git a/dffram.py b/dffram.py index 907351d..59dca65 100755 --- a/dffram.py +++ b/dffram.py @@ -26,12 +26,12 @@ import yaml import cloup -from openlane.common import mkdirp -from openlane.config import Variable -from openlane.logging import warn, err -from openlane.state import DesignFormat -from openlane.flows import SequentialFlow, cloup_flow_opts, Flow -from openlane.steps import Yosys, OpenROAD, Magic, KLayout, Netgen, Odb, Checker, Misc +from librelane.common import mkdirp +from librelane.config import Variable +from librelane.logging import warn, err +from librelane.state import DesignFormat +from librelane.flows import cloup_flow_opts, Flow +from librelane.steps import OpenROAD, Odb class PlaceRAM(Odb.OdbpyStep): @@ -145,49 +145,28 @@ def run(self, state_in, **kwargs): kwargs, env = self.extract_env(kwargs) env["DIE_AREA"] = f"0 0 {die_width} {die_height}" - env[ - "CORE_AREA" - ] = f"{horizontal_halo} {vertical_halo} {horizontal_halo + core_width} {vertical_halo + core_height}" + env["CORE_AREA"] = ( + f"{horizontal_halo} {vertical_halo} {horizontal_halo + core_width} {vertical_halo + core_height}" + ) env["FP_SIZING"] = "absolute" return super().run(state_in, env=env, **kwargs) @Flow.factory.register() -class DFFRAM(SequentialFlow): - Steps = [ - Yosys.Synthesis, - Misc.LoadBaseSDC, - OpenROAD.STAPrePNR, - Floorplan, - PlaceRAM, - Floorplan, - PlaceRAM, - OpenROAD.IOPlacement, - Odb.CustomIOPlacement, - OpenROAD.GeneratePDN, - OpenROAD.STAMidPNR, - OpenROAD.GlobalRouting, - OpenROAD.STAMidPNR, - OpenROAD.DetailedRouting, - Checker.TrDRC, - Odb.ReportDisconnectedPins, - Checker.DisconnectedPins, - Odb.ReportWireLength, - Checker.WireLength, - OpenROAD.RCX, - OpenROAD.STAPostPNR, - OpenROAD.IRDropReport, - Magic.StreamOut, - Magic.WriteLEF, - KLayout.StreamOut, - KLayout.XOR, - Checker.XOR, - Magic.DRC, - Checker.MagicDRC, - Magic.SpiceExtraction, - Checker.IllegalOverlap, - Netgen.LVS, - Checker.LVS, +class DFFRAM(Flow.factory.get("Classic")): + Substitutions = [ + ("*Lint*", None), + ("Checker.NetlistAssignStatements", None), + ("OpenROAD.GlobalPlacement", None), + ("OpenROAD.DetailedPlacement", None), + ("OpenROAD.Resizer*", None), + ("OpenROAD.RepairDesign*", None), + ("OpenROAD.CTS", None), + ("OpenROAD.TapEndcapInsertion", None), + ("OpenROAD.Floorplan", Floorplan), + ("+DFFRAM.Floorplan", PlaceRAM), + ("+DFFRAM.PlaceRAM", Floorplan), + ("+DFFRAM.Floorplan-1", PlaceRAM), ] @@ -245,6 +224,11 @@ def main( pdk_root, **kwargs, ): + if building_blocks == "ram" and variant == "1RW1R": + warn( + "See this issue for discussion on 1RW1R: https://github.com/AUCOHL/DFFRAM/issues/198" + ) + if variant == "DEFAULT": variant = None @@ -339,24 +323,25 @@ def main( ], "SYNTH_ELABORATE_ONLY": True, "SYNTH_ELABORATE_FLATTEN": True, - "SYNTH_READ_BLACKBOX_LIB": True, - "SYNTH_EXCLUSION_CELL_LIST": "/dev/null", + "ERROR_ON_NL_ASSIGN_STATEMENTS": False, + "ERROR_ON_SYNTH_CHECKS": False, + "SYNTH_EXCLUDED_CELL_FILE": "/dev/null", "SYNTH_PARAMETERS": [f"WSIZE={logical_width}"], - "GRT_REPAIR_ANTENNAS": False, + "RUN_ANTENNA_REPAIR": False, "MINIMUM_HEIGHT": min_height, "VERTICAL_HALO": vertical_halo, "HORIZONTAL_HALO": horizontal_halo, "CLOCK_PERIOD": clock_period, # IO Placement - "FP_PIN_ORDER_CFG": pin_order_file, - "FP_IO_VTHICKNESS_MULT": Decimal(2), - "FP_IO_HTHICKNESS_MULT": Decimal(2), - "FP_IO_HEXTEND": Decimal(0), - "FP_IO_VEXTEND": Decimal(0), - "FP_IO_VLENGTH": 2, - "FP_IO_HLENGTH": 2, + "IO_PIN_ORDER_CFG": pin_order_file, + "IO_PIN_V_THICKNESS_MULT": Decimal(2), + "IO_PIN_H_THICKNESS_MULT": Decimal(2), + "IO_PIN_H_EXTENSION": Decimal(0), + "IO_PIN_V_EXTENSION": Decimal(0), + "IO_PIN_V_LENGTH": 2, + "IO_PIN_H_LENGTH": 2, # PDN - "DESIGN_IS_CORE": False, + "PDN_MULTILAYER": False, }, design_dir=os.path.abspath(build_dir), pdk_root=pdk_root, diff --git a/docs/Usage.md b/docs/Usage.md index 854a9e3..6e39d94 100644 --- a/docs/Usage.md +++ b/docs/Usage.md @@ -14,53 +14,16 @@ the RAM modules from elaboration to GDS-II stream out. It incorporates `placeram * The Nix Package Manager ## Installing Nix -You can install Nix by following the instructions at https://nixos.org/download.html. -Or more simply, on Ubuntu, run the following in your Terminal: +Please follow the LibreLane installation guide for Nix: -```sh -sudo apt-get install -y curl -sh <(curl -L https://nixos.org/nix/install) --daemon --yes -``` -> On not systemd-based Linux systems, replace `--daemon` with `--no-daemon`. - -Or on macOS: - -```sh -sh <(curl -L https://nixos.org/nix/install) --yes -``` - -Enter your password if prompted. This hsould take around 5 minutes. - -Make sure to close all terminals after you're done with this step. - -### Setting up the binary cache -Cachix allows the reproducible Nix builds to be stored on a cloud server so you -do not have to build OpenLane's dependencies from scratch on every computer, -which will take a long time. - -First, you want to install Cachix by running the following in your terminal: - -```sh -nix-env -f "" -iA cachix -``` - -Then set up the OpenLane binary cache as follows: - -```sh -cachix use openlane -``` -If `cachix use openlane` fails, re-run it as follows: - -```sh -sudo env PATH="$PATH" cachix use openlane -``` +https://librelane.readthedocs.io/en/latest/getting_started/common/nix_installation/index.html # Basic ```sh git clone https://github.com/Cloud-V/DFFRAM cd DFFRAM -nix-shell +nix develop github:librelane/librelane/3.0.0dev25 ./dffram.py 8x32 # <8-2048>x<8-64> ``` @@ -97,4 +60,4 @@ FORCE_DESIGN_NAME|Design names are found based on the size. If you'd like to for # Appendices - [Appendix A: Using Opendbpy](./md/Using%20Opendbpy.md) -- [Appendix B: How PlaceRAM Works](./md/How%20PlaceRAM%20Works.md) \ No newline at end of file +- [Appendix B: How PlaceRAM Works](./md/How%20PlaceRAM%20Works.md) diff --git a/models/ram/config.yml b/models/ram/config.yml index cfe04c0..a1256dd 100644 --- a/models/ram/config.yml +++ b/models/ram/config.yml @@ -3,4 +3,4 @@ counts: [8, 32, 128, 256, 512, 1024, 2048] design_name_template: "RAM{count}{variant}" variants: - null - # - "1RW1R" + - "1RW1R" diff --git a/placeram/cli.py b/placeram/cli.py index b5cbd95..d1ad352 100644 --- a/placeram/cli.py +++ b/placeram/cli.py @@ -23,6 +23,7 @@ try: import odb import utl + from openroad import Tech, Design except ImportError: print( """ @@ -62,10 +63,11 @@ def __init__( fill_cell_data, tap_distance, ): - # Initialize Database - self.db = odb.dbDatabase.create() + self.ord_tech = Tech() + self.design = Design(self.ord_tech) - odb.read_db(self.db, odb_in) + self.design.readDb(odb_in) + self.db = self.ord_tech.getDB() # Technology Setup self.libs = self.db.getLibs() diff --git a/requirements.txt b/requirements.txt index 640b328..776119e 100644 --- a/requirements.txt +++ b/requirements.txt @@ -1,3 +1,3 @@ -openlane==2.0.0b16 +librelane==3.0.0.dev25 pyyaml cloup diff --git a/shell.nix b/shell.nix deleted file mode 100644 index 142f0f7..0000000 --- a/shell.nix +++ /dev/null @@ -1,23 +0,0 @@ -# Copyright 2023 Efabless Corporation -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -{ - pkgs ? import {} -}: - -let openlane-src = pkgs.fetchFromGitHub { - owner = "efabless"; - repo = "openlane2"; - rev = "83ec6c32add40006cc70d951745667d30193f51d"; - sha256 = "sha256-9Xms6eRf3yyaFJVVjk+uPYYM+EDRl4GYAYYUK5QhiLc="; -}; in import "${openlane-src}/shell.nix" {}