Create simulation models for DFFRAM

[xobs]

It would be nice if DFFRAM contained simulation models to allow testing designs with DFFRAM without simulating the individual cells.

As an example, here is a simple model I'm using to test my design. This model passes the testbench generated by make PATTERN=tb_RAM32x32_1RW1R:

module RAM32_1RW1R  #(parameter    USE_LATCH=1,
                                    WSIZE=1 ) 
(
    input   wire                    CLK,    // FO: 4
    input   wire [WSIZE-1:0]        WE0,     // FO: 4
    input                           EN0,     // FO: 4
    input                           EN1,     // FO: 4
    input   wire [4:0]              A0,     // FO: 1
    input   wire [4:0]              A1,
    input   wire [(WSIZE*8-1):0]    Di0,     // FO: 4
    output  wire [(WSIZE*8-1):0]    Do0,
    output  wire [(WSIZE*8-1):0]    Do1  
);

    reg [31:0] backing[(WSIZE*8-1):0];

    assign Do0 = backing[A0];
    assign Do1 = backing[A1];

    generate
    for (c=0; c < WSIZE; c = c+1) begin
        always @(negedge CLK) begin
            if (WE0[c]) begin
                backing[A0][c*8+7:c*8] <= Di0[c*8+7:c*8];
            end
        end
    end
    endgenerate
endmodule