23-bit RAMs are useful when dealing with tagged memory on RISC-V. In particular, VexRiscv uses 23-bit BRAM blocks when generating its tags, and these can be set to be hard macros when generating CPUs for silicon projects: https://github.com/betrusted-io/pythondata-cpu-vexriscv/blob/d5ff8b357b6ab930c793501c3d5acc22fa454d2e/pythondata_cpu_vexriscv/verilog/VexRiscv_BetrustedSoC.v#L8173
23-bits is kind of a weird length, so it would be nice to have DFFRAM support this. In particular, a 128x22 memory would be nice to have for tagged memory.
23-bit RAMs are useful when dealing with tagged memory on RISC-V. In particular, VexRiscv uses 23-bit BRAM blocks when generating its tags, and these can be set to be hard macros when generating CPUs for silicon projects: https://github.com/betrusted-io/pythondata-cpu-vexriscv/blob/d5ff8b357b6ab930c793501c3d5acc22fa454d2e/pythondata_cpu_vexriscv/verilog/VexRiscv_BetrustedSoC.v#L8173
23-bits is kind of a weird length, so it would be nice to have DFFRAM support this. In particular, a 128x22 memory would be nice to have for tagged memory.