diff --git a/content/datapath-control/exercises.md b/content/datapath-control/exercises.md deleted file mode 100644 index fce7567..0000000 --- a/content/datapath-control/exercises.md +++ /dev/null @@ -1,25 +0,0 @@ ---- -title: "Exercises" -subtitle: "Check your knowledge before section" ---- - -## Conceptual Review - -1. Question - -:::{note} Solution -:class: dropdown - -Solution - - -::: - -## Short Exercises - -1. **True/False**: - -:::{note} Solution -:class: dropdown -**True.** Explanation -::: diff --git a/content/datapath-control/index.md b/content/datapath-control/index.md deleted file mode 100644 index 277cbfb..0000000 --- a/content/datapath-control/index.md +++ /dev/null @@ -1,26 +0,0 @@ ---- -title: "Datapath Control and Design" -subtitle: Coming soon ---- - -## Learning Outcomes - -::::{note} πŸŽ₯ Lecture Video -:class: dropdown - -:::{iframe} https://www.youtube.com/embed/wM85LGWD54U -:width: 100% -:title: "[CS61C FA20] Lecture 20.2 - Single-Cycle CPU Control: Datapath Control" -::: - -:::: - -::::{note} πŸŽ₯ Lecture Video -:class: dropdown - -:::{iframe} https://www.youtube.com/embed/VZHbfvhIEq8 -:width: 100% -:title: "[CS61C FA20] Lecture 20.4 - Single-Cycle CPU Control: Control Logic Design" -::: - -:::: \ No newline at end of file diff --git a/content/datapath-control/special-regs.md b/content/datapath-control/special-regs.md deleted file mode 100644 index 6201625..0000000 --- a/content/datapath-control/special-regs.md +++ /dev/null @@ -1,14 +0,0 @@ ---- -title: "Control and Status Registers" -subtitle: This content is not tested ---- - -::::{note} πŸŽ₯ Lecture Video -:class: dropdown - -:::{iframe} https://www.youtube.com/embed/WgV4h7NTp5U -:width: 100% -:title: "[CS61C FA20] Lecture 20.1 - Single-Cycle CPU Control: Control and Status Registers" -::: - -:::: \ No newline at end of file diff --git a/content/datapath-control/summary-precheck.md b/content/datapath-control/summary-precheck.md deleted file mode 100644 index cd79b75..0000000 --- a/content/datapath-control/summary-precheck.md +++ /dev/null @@ -1,6 +0,0 @@ ---- -title: "Precheck Summary" ---- - -## To Review$\dots$ - diff --git a/content/datapath-control/summary.md b/content/datapath-control/summary.md deleted file mode 100644 index 2507ab6..0000000 --- a/content/datapath-control/summary.md +++ /dev/null @@ -1,51 +0,0 @@ ---- -title: "Summary" ---- - -## And in Conclusion$\dots$ - - -::::{note} πŸŽ₯ Lecture Video -:class: dropdown - -:::{iframe} https://www.youtube.com/embed/qgGy_Ra9hr0 -:width: 100% -:title: "[CS61C FA20] Lecture 20.5 - Single-Cycle CPU Control: Summary" -::: - -:::: - -The **critical path** changed based on instruction. Not all instructions use all hardware units, and therefore not all instructions are active in all five phases of execution ("stages" is the terminology we use for pipelined processors). - -The **controller** pecifies how to execute instructions and it is implemented as ROM (read-only-memory) or as logic gates. - -## Textbook Readings - -P&H 4.4, 4.5 - -## Exercises -Check your knowledge! - -### Short Exercises - -1. **True/False**: The single cycle datapath uses the outputs of all hardware units for each instruction. - -:::{note} Solution -:class: dropdown -**False** All units are active in each cycle, but their output may be ignored (gated) by control signals -::: - -2. **True/False**: It is possible to execute the stages of the single cycle datapath in parallel to speed up execution of a single instruction. - -:::{note} Solution -:class: dropdown -**False** Each stage depends on the value produced by the stage before it (e.g., instruction decode depends on the instruction fetched). -::: - -3. **True/False**: Stores and loads are the only instructions that require input/output from DMEM. - -:::{note} Solution -:class: dropdown -**True** For all other instructions, we don’t need to read the data that is read out from DMEM, and thus don’t need to wait for the output of the MEM stage. -::: - diff --git a/content/datapath/b-type.md b/content/datapath/b-type.md index a8ad673..55006ee 100644 --- a/content/datapath/b-type.md +++ b/content/datapath/b-type.md @@ -1,11 +1,13 @@ --- -title: "Implementing Branches" +title: "Supporting Branches" --- (sec-datapath-b-type)= ## Learning Outcomes -* Coming soon! We provide the animations for now. +* Implement a datapath that supports conditional branches (B-Type). +* Explain how the input/output signals of the branch comparator help determine (for all B-Type instructions) if a branch is "taken." +* Explain how the PCSel control signal determines the instruction to execute in the next clock cycle. ::::{note} πŸŽ₯ Lecture Video :class: dropdown @@ -17,23 +19,114 @@ title: "Implementing Branches" :::: +To support [branch instructions](#sec-b-type) like `beq` we must consider **state element updates**, **arithmetic operations**, and **data selectors**. + +_State element updates_: + +* RegFile: We **read** two registers `rs1` and `rs2` and compare the values `R[rs1]` and `R[rs2]`. We do not write to any registers. +* PC: We **read** from and **write** to PC. The value to write now **conditionally** depends on the result of the two-register comparison, which determines whether a branch is *taken*: + * **taken**: `pc + 4` + * **not taken**: `pc + imm` +* DMEM: No reading nor writing. + +Like before, we **reuse** what already exists in our R-, I-, and S-Type datapath. Even with this, we will need to add three new blocks and some additional control logic. + +(sec-intro-branch-comparator)= +### Branch Comparator + +There are **three** arithmetic operations that branch instructions must (proactively) perform. + +1. `pc + 4`. This hardware is already in our datapath. +1. `pc + imm`. +1. Compare `R[rs1]` and `R[rs2]`. + +We only have one general-purpose [ALU](#fig-element-alu) available during the `EX` phase of our single-cycle datapath. We use this ALU to compute `pc + imm`. We discuss details [below](#sec-datapath-asel) + +Since this ALU is now busy, we must introduce additional combinational logic to compute a comparison of `R[rs1]` and `R[rs2]` within the same clock cycle. We call this new combinational logic block the [**branch comparator**](#sec-datapath-branch-comparator). + +We discuss the details of the branch comparator at the [end of this section](#sec-datapath-branch-comparator). + +### MUX for PC input + +To conditionally update the input to the `PC` element, we introduce a new **mux** that selects between `pc + imm` and `pc + 4` to feed into the `PC` element. We also therefore introduce a new **control signal** `PCSel` to feed into this mux. + +These two new blocks are shown in @fig-branch-new-blocks. The branch comparator performs a logical operation to compare `R[rs1]` and `R[rs2]` and feeds two 1-bit-wide signals, `BrEq` and `BrLT`, into control logic. The new mux uses `PCSel` to update `PC` based on the branch result. + +:::{figure} images/branch-new-blocks.png +:label: fig-branch-new-blocks + +The branch comparator block and the `PCSel` mux, with `PCSel` control signal. +::: + +(sec-datapath-asel)= +### MUX for ALU input + +We need **one more mux** in our datapath to compute `PC + imm` with our existing ALU. The new mux in @fig-branch-new-blocks-asel selects the ALU input `A` based on a new control signal, `ASel`. + +* Set `ASel` to `1` to pass in the program counter value `pc`. +* Set `ASel` to `0` to pass in the register value `R[rs1]`. + +:::{figure} images/branch-new-blocks-asel.png +:label: fig-branch-new-blocks-asel + +Branches require two muxes with two control signals: `PCSel` and `ASel`. The latter determines one of the inputs to our ALU. +::: + +### Immediate Generator Block + +We must also update the Immediate Generator block, `ImmGen`. Immediates in B-Type are [different from I-Type and S-Type](#sec-imm-swirl) and have an [implicit trailing zero](#sec-implicit-zero-b-type). Read more in the [Immediate Generator section](#sec-immgen-b-type). + ## Tracing the Branch Datapath +Let's walk through the updated datapath for branch instructions (B-Type): +